From 556ba87a2a79162370df0ee1a93401256dd2ae58 Mon Sep 17 00:00:00 2001 From: "shaochan.liu" Date: Thu, 30 May 2019 14:11:46 +0800 Subject: [PATCH] lcd: VPU: encl input buffer reset delay and limit input buffer din phase [1/1] PD#SWPL-6649 Problem: encl input buffer reset delay and limit input buffer din phase Solution: set sync_vpp go filed back to encl_clk Verify: t962x3_ab301 Change-Id: I3fc681d408950e7647cfb08bb19bc66f2f8719b6 Signed-off-by: shaochan.liu --- drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c | 6 +++++- drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c index 93b6fe02b134..3f36dd4f1ce7 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c +++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c @@ -196,11 +196,15 @@ static void lcd_venc_set(struct lcd_config_s *pconf) switch (lcd_drv->data->chip_type) { case LCD_CHIP_TL1: - case LCD_CHIP_TM2: /*[15:14]: 2'b10 or 2'b01*/ lcd_vcbus_write(ENCL_INBUF_CNTL1, (2 << 14) | (h_active - 1)); lcd_vcbus_write(ENCL_INBUF_CNTL0, 0x200); break; + case LCD_CHIP_TM2: + /*[15:14]: 2'b10 or 2'b01 bit13:1*/ + lcd_vcbus_write(ENCL_INBUF_CNTL1, (5 << 13) | (h_active - 1)); + lcd_vcbus_write(ENCL_INBUF_CNTL0, 0x200); + break; default: break; } diff --git a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c index 8dd95cb3118b..f3cd86c8de67 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c +++ b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c @@ -181,11 +181,15 @@ static void lcd_venc_set(struct lcd_config_s *pconf) switch (lcd_drv->data->chip_type) { case LCD_CHIP_TL1: - case LCD_CHIP_TM2: /*[15:14]: 2'b10 or 2'b01*/ lcd_vcbus_write(ENCL_INBUF_CNTL1, (2 << 14) | (h_active - 1)); lcd_vcbus_write(ENCL_INBUF_CNTL0, 0x200); break; + case LCD_CHIP_TM2: + /*[15:14]: 2'b10 or 2'b01, bit13:1*/ + lcd_vcbus_write(ENCL_INBUF_CNTL1, (5 << 13) | (h_active - 1)); + lcd_vcbus_write(ENCL_INBUF_CNTL0, 0x200); + break; default: break; }