From 558bea71757ca6808fba72d8fd603f45a3305993 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Tue, 10 Jan 2023 11:33:51 +0800 Subject: [PATCH] Revert "arm64: dts: rockchip: document explicit px30 cru dependencies" This reverts commit 45cb61b4f3bf991ac2011dbc4a155bd5f3b29ebe. For GKI, cru init is deferred_probe_work_func,which make system crash: [ 8.930765][ T6] Unable to handle kernel paging request at virtual address ffffffc8098270e0 [ 8.931691][ T6] Mem abort info: [ 8.932102][ T6] ESR = 0x96000007 [ 8.932541][ T6] EC = 0x25: DABT (current EL), IL = 32 bits [ 8.933192][ T6] SET = 0, FnV = 0 [ 8.933625][ T6] EA = 0, S1PTW = 0 [ 8.934061][ T6] Data abort info: [ 8.934566][ T6] ISV = 0, ISS = 0x00000007 [ 8.935080][ T6] CM = 0, WnR = 0 [ 8.935516][ T6] swapper pgtable: 4k pages, 39-bit VAs, pgdp=000000000297f000 [ 8.936301][ T6] [ffffffc8098270e0] pgd=000000007ffff003, p4d=000000007ffff003, pud=000000007ffff003, pmd=0000000003de9003, pte=0000000000000000 [ 8.937821][ T6] Internal error: Oops: 96000007 [#1] PREEMPT SMP [ 8.938493][ T6] Modules linked in: clk_px30(E) rockchip_cpuinfo(E) clk_rockchip(E) rockchip_sip(E) [ 8.939677][ T6] CPU: 0 PID: 6 Comm: kworker/u8:0 Tainted: G E 5.10.107 #35 [ 8.940574][ T6] Hardware name: Rockchip PX30 evb ddr3 board (DT) [ 8.941305][ T6] Workqueue: events_unbound deferred_probe_work_func [ 8.942062][ T6] pstate: 60400005 (nZCv daif +PAN -UAO -TCO BTYPE=--) [ 8.943125][ T6] pc : rockchip_clk_register_plls+0x164/0x1b8 [clk_rockchip] [ 8.944225][ T6] lr : rockchip_clk_register_plls+0x160/0x1b8 [clk_rockchip] [ 8.944991][ T6] sp : ffffffc812c07980 [ 8.945453][ T6] x29: ffffffc812c079f0 x28: 0000000000000006 [ 8.946173][ T6] x27: 00000000000000a0 x26: ffffffc8098270e0 [ 8.946890][ T6] x25: 0000000000000840 x24: c8ffff800530d100 [ 8.947607][ T6] x23: 00000000000000d8 x22: 0000000000000004 [ 8.948323][ T6] x21: 0000000000000060 x20: 0000000000000001 [ 8.949040][ T6] x19: 0000000000000001 x18: ffffffc812b8d078 [ 8.949760][ T6] x17: 0000000014d453dc x16: 00000000024a8ec8 [ 8.950476][ T6] x15: 0000000000000000 x14: 0000000000000000 [ 8.951193][ T6] x13: 0000000000000000 x12: ffffffc810010644 [ 8.951912][ T6] x11: 0000000000000082 x10: ff800048097f86dc [ 8.952630][ T6] x9 : 0000000000000027 x8 : 00000000000000ff [ 8.953347][ T6] x7 : ffffffffffffffff x6 : 0000000000000000 [ 8.954061][ T6] x5 : 0000000000000000 x4 : a3ffff80048dfc60 [ 8.954778][ T6] x3 : ffffffc8097f86dc x2 : 0000000000000001 [ 8.955493][ T6] x1 : 0000000000000008 x0 : 70ffff8004165308 [ 8.956204][ T6] Call trace: [ 8.956923][ T6] rockchip_clk_register_plls+0x164/0x1b8 [clk_rockchip] [ 8.957665][ T6] 0xffffffc809825168 [ 8.958262][ T6] clk_px30_probe+0x68/0x88 [clk_px30] [ 8.958866][ T6] platform_drv_probe+0xc0/0xe0 [ 8.959421][ T6] really_probe+0x304/0x72c [ 8.959943][ T6] driver_probe_device+0xa4/0xf0 [ 8.960509][ T6] __device_attach_driver+0x1a8/0x1d0 [ 8.961108][ T6] bus_for_each_drv+0xb0/0x10c [ 8.961653][ T6] __device_attach+0x164/0x1d4 [ 8.962201][ T6] device_initial_probe+0x18/0x28 [ 8.962768][ T6] bus_probe_device+0x58/0xf8 [ 8.963308][ T6] deferred_probe_work_func+0xc0/0x164 [ 8.963920][ T6] process_one_work+0x358/0x700 [ 8.964471][ T6] worker_thread+0x52c/0x918 [ 8.964991][ T6] kthread+0x1f8/0x210 [ 8.965466][ T6] ret_from_fork+0x10/0x30 Signed-off-by: Elaine Zhang Change-Id: I255fb5c008077c0c0b430e6922a2ae414cfd422a --- .../bindings/clock/rockchip,px30-cru.txt | 5 ---- arch/arm64/boot/dts/rockchip/px30.dtsi | 25 ++++++++----------- 2 files changed, 10 insertions(+), 20 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt index 55e78cddec8c..39f0c1ac84ee 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt +++ b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt @@ -10,11 +10,6 @@ Required Properties: - compatible: CRU should be "rockchip,px30-cru" - reg: physical base address of the controller and length of memory mapped region. -- clocks: A list of phandle + clock-specifier pairs for the clocks listed - in clock-names -- clock-names: Should contain the following: - - "xin24m" for both PMUCRU and CRU - - "gpll" for CRU (sourced from PMUCRU) - #clock-cells: should be 1. - #reset-cells: should be 1. diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 5a43a617a30f..b0d79064403d 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1215,38 +1215,33 @@ cru: clock-controller@ff2b0000 { compatible = "rockchip,px30-cru"; reg = <0x0 0xff2b0000 0x0 0x1000>; - clocks = <&xin24m>, <&pmucru PLL_GPLL>; - clock-names = "xin24m", "gpll"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru PLL_NPLL>, - <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, - <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, - <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; - - assigned-clock-rates = <1188000000>, - <200000000>, <200000000>, - <150000000>, <150000000>, - <100000000>, <200000000>; + assigned-clocks = <&cru PLL_NPLL>; + assigned-clock-rates = <1188000000>; }; pmucru: clock-controller@ff2bc000 { compatible = "rockchip,px30-pmucru"; reg = <0x0 0xff2bc000 0x0 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, - <&pmucru SCLK_WIFI_PMU>; + <&pmucru SCLK_WIFI_PMU>, <&cru ARMCLK>, + <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, + <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; assigned-clock-rates = <1200000000>, <100000000>, - <26000000>; + <26000000>, <600000000>, + <200000000>, <200000000>, + <150000000>, <150000000>, + <100000000>, <200000000>; }; usb2phy_grf: syscon@ff2c0000 {