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drm/amd/display: skip CLEAR_PAYLOAD_ID_TABLE if device mst_en is 0

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commit a1c9a1e270 upstream.

[Why]
Some dock and mst monitor don't like to receive CLEAR_PAYLOAD_ID_TABLE
when mst_en is set to 0. It doesn't make sense to do so in source
side, either.

[How]
Don't send CLEAR_PAYLOAD_ID_TABLE if mst_en is 0

Reviewed-by: George Shen <George.Shen@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Peichen Huang <PeiChen.Huang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[ 6.1.y doesn't have the file rename from
  54618888d1 ("drm/amd/display: break down dc_link.c") ]
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Peichen Huang
2023-03-20 09:34:23 +08:00
committed by Greg Kroah-Hartman
parent 63eeb50fa1
commit 5656267610
1 changed files with 4 additions and 1 deletions
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5
drivers/gpu/drm/amd/display/dc/core/dc_link.c
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@@ -2092,6 +2092,7 @@ static enum dc_status enable_link_dp_mst(
struct pipe_ctx *pipe_ctx) struct pipe_ctx *pipe_ctx)
{ {
struct dc_link *link = pipe_ctx->stream->link; struct dc_link *link = pipe_ctx->stream->link;
unsigned char mstm_cntl;
/* sink signal type after MST branch is MST. Multiple MST sinks /* sink signal type after MST branch is MST. Multiple MST sinks
* share one link. Link DP PHY is enable or training only once. * share one link. Link DP PHY is enable or training only once.
@@ -2100,7 +2101,9 @@ static enum dc_status enable_link_dp_mst(
return DC_OK; return DC_OK;
/* clear payload table */ /* clear payload table */
dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1);
if (mstm_cntl & DP_MST_EN)
dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
/* to make sure the pending down rep can be processed /* to make sure the pending down rep can be processed
* before enabling the link * before enabling the link