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dt-bindings: mmc: fsl-imx-esdhc: Improve grammar and fix a typo
This makes the text read a little better. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230129130059.1322858-1-j.neuschaefer@gmx.net Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Ulf Hansson
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@@ -107,7 +107,7 @@ properties:
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Specify the number of delay cells for override mode.
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This is used to set the clock delay for DLL(Delay Line) on override mode
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to select a proper data sampling window in case the clock quality is not good
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due to signal path is too long on the board. Please refer to eSDHC/uSDHC
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because the signal path is too long on the board. Please refer to eSDHC/uSDHC
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chapter, DLL (Delay Line) section in RM for details.
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default: 0
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@@ -136,7 +136,7 @@ properties:
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Specify the increasing delay cell steps in tuning procedure.
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The uSDHC use one delay cell as default increasing step to do tuning process.
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This property allows user to change the tuning step to more than one delay
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cells which is useful for some special boards or cards when the default
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cell which is useful for some special boards or cards when the default
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tuning step can't find the proper delay window within limited tuning retries.
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default: 0
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