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amd64_edac: Fix DCT base address selector

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commit 9975a5f22a upstream.

The correct check is to verify whether in high range we're below 4GB
and not to extract the DctSelBaseAddr again. See "2.8.5 Routing DRAM
Requests" in the F10h BKDG.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Acked-by: Doug Thompson <dougthompson@xmission.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Borislav Petkov
2010-03-08 18:29:35 +01:00
committed by Greg Kroah-Hartman
parent fcd6ae1e01
commit 568590d41c
1 changed files with 1 additions and 1 deletions
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2
drivers/edac/amd64_edac.c
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@@ -1491,7 +1491,7 @@ static inline u64 f10_get_base_addr_offset(u64 sys_addr, int hi_range_sel,
u64 chan_off;
if (hi_range_sel) {
if (!(dct_sel_base_addr & 0xFFFFF800) &&
if (!(dct_sel_base_addr & 0xFFFF0000) &&
hole_valid && (sys_addr >= 0x100000000ULL))
chan_off = hole_off << 16;
else