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https://github.com/hardkernel/linux.git
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arm64: dts: rockchip: add px30 ddr relate node
Change-Id: I33119ba0250c6c9fe78d124bf92a94a52f9442bf Signed-off-by: YouMin Chen <cym@rock-chips.com>
This commit is contained in:
YouMin Chen
294
arch/arm64/boot/dts/rockchip/px30-dram-default-timing.dtsi
Normal file
294
arch/arm64/boot/dts/rockchip/px30-dram-default-timing.dtsi
Normal file
@@ -0,0 +1,294 @@
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/*
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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#include <dt-bindings/clock/rockchip-ddr.h>
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#include <dt-bindings/memory/px30-dram.h>
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/ {
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ddr_timing: ddr_timing {
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compatible = "rockchip,ddr-timing";
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ddr2_speed_bin = <DDR2_DEFAULT>;
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ddr3_speed_bin = <DDR3_DEFAULT>;
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ddr4_speed_bin = <DDR4_DEFAULT>;
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pd_idle = <0>;
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sr_idle = <0>;
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sr_mc_gate_idle = <0>;
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srpd_lite_idle = <0>;
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standby_idle = <0>;
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auto_pd_dis_freq = <1066>;
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auto_sr_dis_freq = <800>;
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ddr2_dll_dis_freq = <300>;
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ddr3_dll_dis_freq = <300>;
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ddr4_dll_dis_freq = <625>;
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phy_dll_dis_freq = <400>;
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ddr2_odt_dis_freq = <100>;
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phy_ddr2_odt_dis_freq = <100>;
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ddr2_drv = <DDR2_DS_REDUCE>;
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ddr2_odt = <DDR2_ODT_150ohm>;
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phy_ddr2_ca_drv = <PHY_DDR3_RON_RTT_34ohm>;
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phy_ddr2_ck_drv = <PHY_DDR3_RON_RTT_45ohm>;
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phy_ddr2_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
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phy_ddr2_odt = <PHY_DDR3_RON_RTT_225ohm>;
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ddr3_odt_dis_freq = <100>;
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phy_ddr3_odt_dis_freq = <100>;
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ddr3_drv = <DDR3_DS_40ohm>;
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ddr3_odt = <DDR3_ODT_120ohm>;
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phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_34ohm>;
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phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_45ohm>;
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phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
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phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
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phy_lpddr2_odt_dis_freq = <666>;
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lpddr2_drv = <LP2_DS_40ohm>;
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phy_lpddr2_ca_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>;
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phy_lpddr2_ck_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_43ohm>;
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phy_lpddr2_dq_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>;
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phy_lpddr2_odt = <PHY_DDR4_LPDDR3_2_RON_RTT_DISABLE>;
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lpddr3_odt_dis_freq = <666>;
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phy_lpddr3_odt_dis_freq = <666>;
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lpddr3_drv = <LP3_DS_40ohm>;
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lpddr3_odt = <LP3_ODT_240ohm>;
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phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>;
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phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_43ohm>;
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phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>;
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phy_lpddr3_odt = <PHY_DDR4_LPDDR3_2_RON_RTT_240ohm>;
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lpddr4_odt_dis_freq = <800>;
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phy_lpddr4_odt_dis_freq = <800>;
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lpddr4_drv = <LP4_PDDS_60ohm>;
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lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
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lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
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phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_40ohm>;
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phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_80ohm>;
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phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_80ohm>;
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phy_lpddr4_odt = <PHY_DDR4_LPDDR3_2_RON_RTT_60ohm>;
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ddr4_odt_dis_freq = <666>;
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phy_ddr4_odt_dis_freq = <666>;
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ddr4_drv = <DDR4_DS_34ohm>;
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ddr4_odt = <DDR4_RTT_NOM_240ohm>;
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phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>;
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phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_43ohm>;
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phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>;
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phy_ddr4_odt = <PHY_DDR4_LPDDR3_2_RON_RTT_240ohm>;
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/* CA de-skew, one step is 47.8ps, range 0-15 */
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ddr3a1_ddr4a9_de-skew = <7>;
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ddr3a0_ddr4a10_de-skew = <7>;
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ddr3a3_ddr4a6_de-skew = <8>;
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ddr3a2_ddr4a4_de-skew = <8>;
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ddr3a5_ddr4a8_de-skew = <7>;
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ddr3a4_ddr4a5_de-skew = <9>;
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ddr3a7_ddr4a11_de-skew = <7>;
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ddr3a6_ddr4a7_de-skew = <9>;
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ddr3a9_ddr4a0_de-skew = <8>;
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ddr3a8_ddr4a13_de-skew = <7>;
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ddr3a11_ddr4a3_de-skew = <9>;
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ddr3a10_ddr4cs0_de-skew = <7>;
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ddr3a13_ddr4a2_de-skew = <8>;
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ddr3a12_ddr4ba1_de-skew = <7>;
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ddr3a15_ddr4odt0_de-skew = <7>;
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ddr3a14_ddr4a1_de-skew = <8>;
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ddr3ba1_ddr4a15_de-skew = <7>;
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ddr3ba0_ddr4bg0_de-skew = <7>;
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ddr3ras_ddr4cke_de-skew = <7>;
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ddr3ba2_ddr4ba0_de-skew = <8>;
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ddr3we_ddr4bg1_de-skew = <8>;
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ddr3cas_ddr4a12_de-skew = <7>;
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ddr3ckn_ddr4ckn_de-skew = <8>;
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ddr3ckp_ddr4ckp_de-skew = <8>;
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ddr3cke_ddr4a16_de-skew = <8>;
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ddr3odt0_ddr4a14_de-skew = <7>;
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ddr3cs0_ddr4act_de-skew = <8>;
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ddr3reset_ddr4reset_de-skew = <7>;
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ddr3cs1_ddr4cs1_de-skew = <7>;
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ddr3odt1_ddr4odt1_de-skew = <7>;
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/* DATA de-skew
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* RX one step is 25.1ps, range 0-15
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* TX one step is 47.8ps, range 0-15
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*/
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cs0_dm0_rx_de-skew = <7>;
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cs0_dm0_tx_de-skew = <8>;
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cs0_dq0_rx_de-skew = <7>;
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cs0_dq0_tx_de-skew = <8>;
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cs0_dq1_rx_de-skew = <7>;
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cs0_dq1_tx_de-skew = <8>;
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cs0_dq2_rx_de-skew = <7>;
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cs0_dq2_tx_de-skew = <8>;
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cs0_dq3_rx_de-skew = <7>;
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cs0_dq3_tx_de-skew = <8>;
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cs0_dq4_rx_de-skew = <7>;
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cs0_dq4_tx_de-skew = <8>;
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cs0_dq5_rx_de-skew = <7>;
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cs0_dq5_tx_de-skew = <8>;
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cs0_dq6_rx_de-skew = <7>;
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cs0_dq6_tx_de-skew = <8>;
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cs0_dq7_rx_de-skew = <7>;
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cs0_dq7_tx_de-skew = <8>;
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cs0_dqs0_rx_de-skew = <6>;
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cs0_dqs0p_tx_de-skew = <9>;
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cs0_dqs0n_tx_de-skew = <9>;
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cs0_dm1_rx_de-skew = <7>;
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cs0_dm1_tx_de-skew = <7>;
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cs0_dq8_rx_de-skew = <7>;
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cs0_dq8_tx_de-skew = <8>;
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cs0_dq9_rx_de-skew = <7>;
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cs0_dq9_tx_de-skew = <7>;
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cs0_dq10_rx_de-skew = <7>;
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cs0_dq10_tx_de-skew = <8>;
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cs0_dq11_rx_de-skew = <7>;
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cs0_dq11_tx_de-skew = <7>;
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cs0_dq12_rx_de-skew = <7>;
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cs0_dq12_tx_de-skew = <8>;
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cs0_dq13_rx_de-skew = <7>;
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cs0_dq13_tx_de-skew = <7>;
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cs0_dq14_rx_de-skew = <7>;
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cs0_dq14_tx_de-skew = <8>;
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cs0_dq15_rx_de-skew = <7>;
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cs0_dq15_tx_de-skew = <7>;
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cs0_dqs1_rx_de-skew = <7>;
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cs0_dqs1p_tx_de-skew = <9>;
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cs0_dqs1n_tx_de-skew = <9>;
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cs0_dm2_rx_de-skew = <7>;
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cs0_dm2_tx_de-skew = <8>;
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cs0_dq16_rx_de-skew = <7>;
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cs0_dq16_tx_de-skew = <8>;
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cs0_dq17_rx_de-skew = <7>;
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cs0_dq17_tx_de-skew = <8>;
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cs0_dq18_rx_de-skew = <7>;
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cs0_dq18_tx_de-skew = <8>;
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cs0_dq19_rx_de-skew = <7>;
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cs0_dq19_tx_de-skew = <8>;
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cs0_dq20_rx_de-skew = <7>;
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cs0_dq20_tx_de-skew = <8>;
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cs0_dq21_rx_de-skew = <7>;
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cs0_dq21_tx_de-skew = <8>;
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cs0_dq22_rx_de-skew = <7>;
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cs0_dq22_tx_de-skew = <8>;
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cs0_dq23_rx_de-skew = <7>;
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cs0_dq23_tx_de-skew = <8>;
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cs0_dqs2_rx_de-skew = <6>;
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cs0_dqs2p_tx_de-skew = <9>;
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cs0_dqs2n_tx_de-skew = <9>;
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cs0_dm3_rx_de-skew = <7>;
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cs0_dm3_tx_de-skew = <7>;
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cs0_dq24_rx_de-skew = <7>;
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cs0_dq24_tx_de-skew = <8>;
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cs0_dq25_rx_de-skew = <7>;
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cs0_dq25_tx_de-skew = <7>;
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cs0_dq26_rx_de-skew = <7>;
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cs0_dq26_tx_de-skew = <7>;
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cs0_dq27_rx_de-skew = <7>;
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cs0_dq27_tx_de-skew = <7>;
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cs0_dq28_rx_de-skew = <7>;
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cs0_dq28_tx_de-skew = <7>;
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cs0_dq29_rx_de-skew = <7>;
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cs0_dq29_tx_de-skew = <7>;
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cs0_dq30_rx_de-skew = <7>;
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cs0_dq30_tx_de-skew = <7>;
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cs0_dq31_rx_de-skew = <7>;
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cs0_dq31_tx_de-skew = <7>;
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cs0_dqs3_rx_de-skew = <7>;
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cs0_dqs3p_tx_de-skew = <9>;
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cs0_dqs3n_tx_de-skew = <9>;
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cs1_dm0_rx_de-skew = <7>;
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cs1_dm0_tx_de-skew = <8>;
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cs1_dq0_rx_de-skew = <7>;
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cs1_dq0_tx_de-skew = <8>;
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cs1_dq1_rx_de-skew = <7>;
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cs1_dq1_tx_de-skew = <8>;
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cs1_dq2_rx_de-skew = <7>;
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cs1_dq2_tx_de-skew = <8>;
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cs1_dq3_rx_de-skew = <7>;
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cs1_dq3_tx_de-skew = <8>;
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cs1_dq4_rx_de-skew = <7>;
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cs1_dq4_tx_de-skew = <8>;
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cs1_dq5_rx_de-skew = <7>;
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cs1_dq5_tx_de-skew = <8>;
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cs1_dq6_rx_de-skew = <7>;
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cs1_dq6_tx_de-skew = <8>;
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cs1_dq7_rx_de-skew = <7>;
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cs1_dq7_tx_de-skew = <8>;
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cs1_dqs0_rx_de-skew = <6>;
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cs1_dqs0p_tx_de-skew = <9>;
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cs1_dqs0n_tx_de-skew = <9>;
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cs1_dm1_rx_de-skew = <7>;
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cs1_dm1_tx_de-skew = <7>;
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cs1_dq8_rx_de-skew = <7>;
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cs1_dq8_tx_de-skew = <8>;
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cs1_dq9_rx_de-skew = <7>;
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cs1_dq9_tx_de-skew = <7>;
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cs1_dq10_rx_de-skew = <7>;
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cs1_dq10_tx_de-skew = <8>;
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cs1_dq11_rx_de-skew = <7>;
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cs1_dq11_tx_de-skew = <7>;
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cs1_dq12_rx_de-skew = <7>;
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cs1_dq12_tx_de-skew = <8>;
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cs1_dq13_rx_de-skew = <7>;
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cs1_dq13_tx_de-skew = <7>;
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cs1_dq14_rx_de-skew = <7>;
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cs1_dq14_tx_de-skew = <8>;
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cs1_dq15_rx_de-skew = <7>;
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cs1_dq15_tx_de-skew = <7>;
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cs1_dqs1_rx_de-skew = <7>;
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cs1_dqs1p_tx_de-skew = <9>;
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cs1_dqs1n_tx_de-skew = <9>;
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cs1_dm2_rx_de-skew = <7>;
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cs1_dm2_tx_de-skew = <8>;
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cs1_dq16_rx_de-skew = <7>;
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cs1_dq16_tx_de-skew = <8>;
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cs1_dq17_rx_de-skew = <7>;
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cs1_dq17_tx_de-skew = <8>;
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cs1_dq18_rx_de-skew = <7>;
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cs1_dq18_tx_de-skew = <8>;
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cs1_dq19_rx_de-skew = <7>;
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cs1_dq19_tx_de-skew = <8>;
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cs1_dq20_rx_de-skew = <7>;
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cs1_dq20_tx_de-skew = <8>;
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cs1_dq21_rx_de-skew = <7>;
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cs1_dq21_tx_de-skew = <8>;
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cs1_dq22_rx_de-skew = <7>;
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cs1_dq22_tx_de-skew = <8>;
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cs1_dq23_rx_de-skew = <7>;
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cs1_dq23_tx_de-skew = <8>;
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cs1_dqs2_rx_de-skew = <6>;
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cs1_dqs2p_tx_de-skew = <9>;
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cs1_dqs2n_tx_de-skew = <9>;
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cs1_dm3_rx_de-skew = <7>;
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cs1_dm3_tx_de-skew = <7>;
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cs1_dq24_rx_de-skew = <7>;
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cs1_dq24_tx_de-skew = <8>;
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cs1_dq25_rx_de-skew = <7>;
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cs1_dq25_tx_de-skew = <7>;
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cs1_dq26_rx_de-skew = <7>;
|
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cs1_dq26_tx_de-skew = <7>;
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cs1_dq27_rx_de-skew = <7>;
|
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cs1_dq27_tx_de-skew = <7>;
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cs1_dq28_rx_de-skew = <7>;
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cs1_dq28_tx_de-skew = <7>;
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cs1_dq29_rx_de-skew = <7>;
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cs1_dq29_tx_de-skew = <7>;
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cs1_dq30_rx_de-skew = <7>;
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cs1_dq30_tx_de-skew = <7>;
|
||||
cs1_dq31_rx_de-skew = <7>;
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||||
cs1_dq31_tx_de-skew = <7>;
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||||
cs1_dqs3_rx_de-skew = <7>;
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cs1_dqs3p_tx_de-skew = <9>;
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cs1_dqs3n_tx_de-skew = <9>;
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||||
};
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};
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@@ -12,7 +12,9 @@
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#include <dt-bindings/pinctrl/rockchip.h>
|
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#include <dt-bindings/power/px30-power.h>
|
||||
#include <dt-bindings/soc/rockchip,boot-mode.h>
|
||||
#include <dt-bindings/soc/rockchip-system-status.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include "px30-dram-default-timing.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "rockchip,px30";
|
||||
@@ -1345,6 +1347,74 @@
|
||||
reg = <0x0 0xff558080 0x0 0x20>;
|
||||
};
|
||||
|
||||
dfi: dfi@ff610000 {
|
||||
reg = <0x00 0xff610000 0x00 0x400>;
|
||||
compatible = "rockchip,px30-dfi";
|
||||
rockchip,pmugrf = <&pmugrf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dmc: dmc {
|
||||
compatible = "rockchip,px30-dmc";
|
||||
devfreq-events = <&dfi>;
|
||||
clocks = <&cru SCLK_DDRCLK>;
|
||||
clock-names = "dmc_clk";
|
||||
operating-points-v2 = <&dmc_opp_table>;
|
||||
ddr_timing = <&ddr_timing>;
|
||||
upthreshold = <40>;
|
||||
downdifferential = <20>;
|
||||
system-status-freq = <
|
||||
/*system status freq(KHz)*/
|
||||
SYS_STATUS_NORMAL 786000
|
||||
SYS_STATUS_REBOOT 786000
|
||||
SYS_STATUS_SUSPEND 786000
|
||||
SYS_STATUS_VIDEO_1080P 786000
|
||||
SYS_STATUS_PERFORMANCE 786000
|
||||
SYS_STATUS_BOOST 786000
|
||||
>;
|
||||
auto-min-freq = <400000>;
|
||||
auto-freq-en = <0>;
|
||||
#cooling-cells = <2>;
|
||||
status = "disabled";
|
||||
|
||||
ddr_power_model: ddr_power_model {
|
||||
compatible = "ddr_power_model";
|
||||
dynamic-power-coefficient = <120>;
|
||||
static-power-coefficient = <200>;
|
||||
ts = <32000 4700 (-80) 2>;
|
||||
thermal-zone = "soc-thermal";
|
||||
};
|
||||
};
|
||||
|
||||
dmc_opp_table: dmc-opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <925000>;
|
||||
opp-microvolt-L0 = <925000>;
|
||||
opp-microvolt-L1 = <900000>;
|
||||
};
|
||||
opp-600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-microvolt = <1025000>;
|
||||
opp-microvolt-L0 = <1025000>;
|
||||
opp-microvolt-L1 = <1000000>;
|
||||
};
|
||||
opp-786000000 {
|
||||
opp-hz = /bits/ 64 <786000000>;
|
||||
opp-microvolt = <1075000>;
|
||||
opp-microvolt-L0 = <1075000>;
|
||||
opp-microvolt-L1 = <1050000>;
|
||||
};
|
||||
opp-800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <1075000>;
|
||||
opp-microvolt-L0 = <1075000>;
|
||||
opp-microvolt-L1 = <1050000>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "rockchip,px30-pinctrl";
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
Reference in New Issue
Block a user