From 5778016ed8e997ce2181cf205d00719e0b99a4d7 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Fri, 18 Jan 2019 14:56:14 +0800 Subject: [PATCH] phy/rockchip: mipi-dphy: leave move margin for clk post time Change-Id: I64dc251fb7e0efea1e1cf8d7ce05f792187a5c4d Signed-off-by: Sandy Huang --- drivers/phy/rockchip/phy-rockchip-inno-mipi-dphy.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-mipi-dphy.c b/drivers/phy/rockchip/phy-rockchip-inno-mipi-dphy.c index d70aba4905ba..b2ee0020ecf4 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-mipi-dphy.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-mipi-dphy.c @@ -371,7 +371,11 @@ static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, { /* Global Operation Timing Parameters */ timing->clkmiss = 0; - timing->clkpost = 70 + 52 * period / PSEC_PER_NSEC; + /* + * The D-PHY spec define the clk post min time is 60ns + 52UI and + * no define max time, so we set 200 + 52UI leave move margin. + */ + timing->clkpost = 200 + 52 * period / PSEC_PER_NSEC; timing->clkpre = 8 * period / PSEC_PER_NSEC; timing->clkprepare = 65; timing->clksettle = 95;