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soc: rockchip: power-domain: Add support to repair memory when power up

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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I14e8f85491f6522c073b3a1cd9a8a163c3df935e
This commit is contained in:
Finley Xiao
2021-11-01 20:09:35 +08:00
committed by Tao Huang
parent 932f203d92
commit 57db7e6ba5
1 changed files with 60 additions and 44 deletions
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104
drivers/soc/rockchip/pm_domains.c
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@@ -48,6 +48,7 @@ struct rockchip_domain_info {
bool active_wakeup;
int pwr_w_mask;
int req_w_mask;
int repair_status_mask;
bool keepon_startup;
u32 pwr_offset;
u32 req_offset;
@@ -59,6 +60,7 @@ struct rockchip_pmu_info {
u32 req_offset;
u32 idle_offset;
u32 ack_offset;
u32 repair_status_offset;
u32 core_pwrcnt_offset;
u32 gpu_pwrcnt_offset;
@@ -158,6 +160,23 @@ static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd)
.req_offset = r_offset, \
}
#define DOMAIN_M_O_R(_name, p_offset, pwr, status, r_status, r_offset, req, idle, ack, wakeup, keepon) \
{ \
.name = _name, \
.pwr_offset = p_offset, \
.pwr_w_mask = (pwr) << 16, \
.pwr_mask = (pwr), \
.status_mask = (status), \
.repair_status_mask = (r_status), \
.req_offset = r_offset, \
.req_w_mask = (req) << 16, \
.req_mask = (req), \
.idle_mask = (idle), \
.ack_mask = (ack), \
.active_wakeup = wakeup, \
.keepon_startup = keepon, \
}
#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \
{ \
.name = _name, \
@@ -210,22 +229,11 @@ static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd)
#define DOMAIN_RK3568_PROTECT(name, pwr, req, wakeup) \
DOMAIN_M(name, pwr, pwr, req, req, req, wakeup, true)
#define DOMAIN_RK3588(name, pwr, req, wakeup) \
DOMAIN_M(name, pwr, pwr, req, req, req, wakeup, false)
#define DOMAIN_RK3588(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup) \
DOMAIN_M_O_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, idle, wakeup, false)
#define DOMAIN_RK3588_P_O(name, pwr, req, wakeup) \
DOMAIN_M_O(name, pwr, (pwr) << 16, 0x4, req, req, req, 0, wakeup, false)
#define DOMAIN_RK3588_P_O_PROTECT(name, pwr, req, wakeup) \
DOMAIN_M_O(name, pwr, (pwr) << 16, 0x4, req, req, req, 0, wakeup, true)
#define DOMAIN_RK3588_O(name, pwr, req, wakeup) \
DOMAIN_M_O(name, pwr, (pwr) << 16, 0x4, \
req, (req) << 16, (req) << 16, 0x4, wakeup, false)
#define DOMAIN_RK3588_O_PROTECT(name, pwr, req, wakeup) \
DOMAIN_M_O(name, pwr, (pwr) << 16, 0x4, \
req, (req) << 16, (req) << 16, 0x4, wakeup, false)
#define DOMAIN_RK3588_P(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup) \
DOMAIN_M_O_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, idle, wakeup, true)
static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
{
@@ -423,6 +431,12 @@ static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
struct rockchip_pmu *pmu = pd->pmu;
unsigned int val;
if (pd->info->repair_status_mask) {
regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val);
/* 1'b0: power on, 1'b1: power off */
return !(val & pd->info->repair_status_mask);
}
/* check idle status for idle-only domains */
if (pd->info->status_mask == 0)
return !rockchip_pmu_domain_is_idle(pd);
@@ -1380,35 +1394,36 @@ static const struct rockchip_domain_info rk3568_pm_domains[] = {
};
static const struct rockchip_domain_info rk3588_pm_domains[] = {
[RK3588_PD_GPU] = DOMAIN_RK3588("gpu", BIT(0), BIT(0), false),
[RK3588_PD_NPU] = DOMAIN_RK3588("npu", BIT(1), 0, false),
[RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", BIT(2), 0, false),
[RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", BIT(3), BIT(1), false),
[RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", BIT(4), BIT(2), false),
[RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", BIT(5), BIT(3), false),
[RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", BIT(6), BIT(4), false),
[RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", BIT(7), BIT(5), false),
[RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", BIT(8), BIT(6), false),
[RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", BIT(9), BIT(7), false),
[RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", BIT(10), BIT(8), false),
[RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", BIT(11), 0, false),
[RK3588_PD_AV1] = DOMAIN_RK3588("av1", BIT(12), BIT(9), false),
[RK3588_PD_VI] = DOMAIN_RK3588("vi", BIT(13), BIT(10), false),
[RK3588_PD_FEC] = DOMAIN_RK3588("fec", BIT(14), 0, false),
[RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", BIT(15), BIT(11), false),
[RK3588_PD_RGA31] = DOMAIN_RK3588_P_O("rga31", BIT(0), BIT(12), false),
[RK3588_PD_VOP] = DOMAIN_RK3588_P_O_PROTECT("vop", BIT(1), BIT(13) | BIT(14), false),
[RK3588_PD_VO0] = DOMAIN_RK3588_P_O_PROTECT("vo0", BIT(2), BIT(15), false),
[RK3588_PD_VO1] = DOMAIN_RK3588_O_PROTECT("vo1", BIT(3), BIT(0), false),
[RK3588_PD_AUDIO] = DOMAIN_RK3588_O("audio", BIT(4), BIT(1), false),
[RK3588_PD_PHP] = DOMAIN_RK3588_O("php", BIT(5), BIT(5), false),
[RK3588_PD_GMAC] = DOMAIN_RK3588_O("gmac", BIT(6), 0, false),
[RK3588_PD_PCIE] = DOMAIN_RK3588_O("pcie", BIT(7), 0, true),
[RK3588_PD_NVM] = DOMAIN_RK3588_O("nvm", BIT(8), BIT(2), false),
[RK3588_PD_NVM0] = DOMAIN_RK3588_O("nvm0", BIT(9), 0, false),
[RK3588_PD_SDIO] = DOMAIN_RK3588_O("sdio", BIT(10), BIT(3), false),
[RK3588_PD_USB] = DOMAIN_RK3588_O("usb", BIT(11), BIT(4), true),
[RK3588_PD_SDMMC] = DOMAIN_RK3588_O("sdmmc", BIT(13), 0, false),
/* name p_offset pwr status r_status r_offset req idle wakeup */
[RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, BIT(1), 0x0, BIT(0), BIT(0), false),
[RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0, 0x0, 0, 0, false),
[RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0, 0x0, 0, 0, false),
[RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, BIT(2), 0x0, BIT(1), BIT(1), false),
[RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, BIT(3), 0x0, BIT(2), BIT(2), false),
[RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, BIT(4), 0x0, BIT(3), BIT(3), false),
[RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, BIT(5), 0x0, BIT(4), BIT(4), false),
[RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, BIT(6), 0x0, BIT(5), BIT(5), false),
[RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, BIT(7), 0x0, BIT(6), BIT(6), false),
[RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, BIT(8), 0x0, BIT(7), BIT(7), false),
[RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, BIT(9), 0x0, BIT(8), BIT(8), false),
[RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, BIT(10), 0x0, 0, 0, false),
[RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, BIT(11), 0x0, BIT(9), BIT(9), false),
[RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, BIT(12), 0x0, BIT(10), BIT(10), false),
[RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, BIT(13), 0x0, 0, 0, false),
[RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, BIT(14), 0x0, BIT(11), BIT(11), false),
[RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, BIT(15), 0x0, BIT(12), BIT(12), false),
[RK3588_PD_VOP] = DOMAIN_RK3588_P("vop", 0x4, BIT(1), 0, BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
[RK3588_PD_VO0] = DOMAIN_RK3588_P("vo0", 0x4, BIT(2), 0, BIT(17), 0x0, BIT(15), BIT(15), false),
[RK3588_PD_VO1] = DOMAIN_RK3588_P("vo1", 0x4, BIT(3), 0, BIT(18), 0x4, BIT(0), BIT(16), false),
[RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, BIT(19), 0x4, BIT(1), BIT(17), false),
[RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, BIT(20), 0x4, BIT(5), BIT(21), false),
[RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, BIT(21), 0x0, 0, 0, false),
[RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, BIT(22), 0x0, 0, 0, true),
[RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0, 0x4, BIT(2), BIT(18), false),
[RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, BIT(23), 0x0, 0, 0, false),
[RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, BIT(24), 0x4, BIT(3), BIT(19), false),
[RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, BIT(25), 0x4, BIT(4), BIT(20), true),
[RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, BIT(26), 0x0, 0, 0, false),
};
static const struct rockchip_pmu_info px30_pmu = {
@@ -1585,6 +1600,7 @@ static const struct rockchip_pmu_info rk3588_pmu = {
.req_offset = 0x10c,
.idle_offset = 0x120,
.ack_offset = 0x118,
.repair_status_offset = 0x290,
.num_domains = ARRAY_SIZE(rk3588_pm_domains),
.domain_info = rk3588_pm_domains,