From 57dfaaf4e6c7a2b98b31e9079acccf8d1740cb58 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Tue, 13 Oct 2020 21:11:05 +0800 Subject: [PATCH] ARM: dts: rockchip: rv1126: Add leakage info for cpu, npu and vepu Signed-off-by: Finley Xiao Change-Id: Ia0f0b61f77d22708064058960d38b240988d9bc3 --- arch/arm/boot/dts/rv1126.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi index a2fd2e858561..f1a7a677e85b 100644 --- a/arch/arm/boot/dts/rv1126.dtsi +++ b/arch/arm/boot/dts/rv1126.dtsi @@ -109,6 +109,10 @@ cpu0_opp_table: cpu0-opp-table { compatible = "operating-points-v2"; opp-shared; + + nvmem-cells = <&cpu_leakage>; + nvmem-cell-names = "leakage"; + rockchip,reboot-freq = <816000>; rockchip,temp-freq-table = < @@ -1358,6 +1362,9 @@ npu_leakage: npu-leakage@19 { reg = <0x19 0x1>; }; + venc_leakage: venc-leakage@1a { + reg = <0x1a 0x1>; + }; cpu_tsadc_trim_l: cpu-tsadc-trim-l@23 { reg = <0x23 0x1>; }; @@ -2145,6 +2152,9 @@ rkvenc_opp_table: rkvenc-opp-table { compatible = "operating-points-v2"; + nvmem-cells = <&venc_leakage>; + nvmem-cell-names = "leakage"; + rockchip,temp-freq-table = < 80000 500000 100000 396000 @@ -2338,6 +2348,9 @@ npu_opp_table: npu-opp-table { compatible = "operating-points-v2"; + nvmem-cells = <&npu_leakage>; + nvmem-cell-names = "leakage"; + clocks = <&pmucru PLL_GPLL>; rockchip,bin-scaling-sel = < 0 23