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clk: rockchip: rk3368: remove the flag ROCKCHIP_PLL_SYNC_RATE

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CPLL and NPLL is used for vop dclk, sync rate flag would cause
loader display abnormal.

Change-Id: Ia170a8d0b7d1f39e2c9dcbc10b5d33fd1886d5f7
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Mark Yao
2017-03-17 09:41:10 +08:00
committed by Tao Huang
parent 79f18c47d5
commit 57eb2dfc42
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk3368.c
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@@ -143,11 +143,11 @@ static struct rockchip_pll_clock rk3368_pll_clks[] __initdata = {
[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8),
RK3368_PLL_CON(11), 8, 2, 0, NULL),
[cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
RK3368_PLL_CON(15), 8, 3, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
RK3368_PLL_CON(15), 8, 3, 0, rk3368_pll_rates),
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16),
RK3368_PLL_CON(19), 8, 4, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3368_PLL_CON(20),
RK3368_PLL_CON(23), 8, 5, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
RK3368_PLL_CON(23), 8, 5, 0, rk3368_pll_rates),
};
static struct clk_div_table div_ddrphy_t[] = {