From 57eb2dfc42d02fab5c48564b6e268de8e0f273d3 Mon Sep 17 00:00:00 2001 From: Mark Yao Date: Fri, 17 Mar 2017 09:41:10 +0800 Subject: [PATCH] clk: rockchip: rk3368: remove the flag ROCKCHIP_PLL_SYNC_RATE CPLL and NPLL is used for vop dclk, sync rate flag would cause loader display abnormal. Change-Id: Ia170a8d0b7d1f39e2c9dcbc10b5d33fd1886d5f7 Signed-off-by: Mark Yao Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3368.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c index 7ce6a0636e13..0021b19d1d65 100644 --- a/drivers/clk/rockchip/clk-rk3368.c +++ b/drivers/clk/rockchip/clk-rk3368.c @@ -143,11 +143,11 @@ static struct rockchip_pll_clock rk3368_pll_clks[] __initdata = { [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8), RK3368_PLL_CON(11), 8, 2, 0, NULL), [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12), - RK3368_PLL_CON(15), 8, 3, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates), + RK3368_PLL_CON(15), 8, 3, 0, rk3368_pll_rates), [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16), RK3368_PLL_CON(19), 8, 4, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates), [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3368_PLL_CON(20), - RK3368_PLL_CON(23), 8, 5, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates), + RK3368_PLL_CON(23), 8, 5, 0, rk3368_pll_rates), }; static struct clk_div_table div_ddrphy_t[] = {