From 5c77c0737df7fb74fb912fb3aedc6c63773825b6 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Thu, 21 Sep 2023 19:32:02 +0800 Subject: [PATCH 1/7] ASoC: rockchip: pdm: Use add_component_controls This patch use add_component_controls instead of dai's one to support multiple instance with name_prefix. Signed-off-by: Sugar Zhang Change-Id: I5e4872991eb1115ef0f56aba0635cde817fd31b8 --- sound/soc/rockchip/rockchip_pdm.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/sound/soc/rockchip/rockchip_pdm.c b/sound/soc/rockchip/rockchip_pdm.c index 6186840bcf57..7c445ede5473 100644 --- a/sound/soc/rockchip/rockchip_pdm.c +++ b/sound/soc/rockchip/rockchip_pdm.c @@ -640,10 +640,12 @@ static int rockchip_pdm_dai_probe(struct snd_soc_dai *dai) struct rk_pdm_dev *pdm = to_info(dai); dai->capture_dma_data = &pdm->capture_dma_data; - snd_soc_add_dai_controls(dai, rockchip_pdm_controls, - ARRAY_SIZE(rockchip_pdm_controls)); + if (pdm->clk_calibrate) - snd_soc_add_dai_controls(dai, &rockchip_pdm_compensation_control, 1); + snd_soc_add_component_controls(dai->component, + &rockchip_pdm_compensation_control, + 1); + return 0; } @@ -724,6 +726,8 @@ static struct snd_soc_dai_driver rockchip_pdm_dai = { static const struct snd_soc_component_driver rockchip_pdm_component = { .name = "rockchip-pdm", + .controls = rockchip_pdm_controls, + .num_controls = ARRAY_SIZE(rockchip_pdm_controls), }; static int rockchip_pdm_pinctrl_select_clk_state(struct device *dev) From 352863bfa2098c2261ce5c430a7cfe1558d08a4b Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Fri, 22 Sep 2023 11:59:12 +0800 Subject: [PATCH 2/7] ASoC: rockchip: pdm: Add support for PATHx controls This patch add support PATHx controls which allow user can select PATHx dynamically. Signed-off-by: Sugar Zhang Change-Id: Ie7d286ed60363734bc25bf3127daab0d8fcc7144 --- sound/soc/rockchip/rockchip_pdm.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/sound/soc/rockchip/rockchip_pdm.c b/sound/soc/rockchip/rockchip_pdm.c index 7c445ede5473..43c954d8e11c 100644 --- a/sound/soc/rockchip/rockchip_pdm.c +++ b/sound/soc/rockchip/rockchip_pdm.c @@ -569,7 +569,20 @@ static int rockchip_pdm_filter_delay_put(struct snd_kcontrol *kcontrol, return 1; } +static const char * const rpaths_text[] = { + "From SDI0", "From SDI1", "From SDI2", "From SDI3" }; + +static SOC_ENUM_SINGLE_DECL(rpath3_enum, PDM_CLK_CTRL, 14, rpaths_text); +static SOC_ENUM_SINGLE_DECL(rpath2_enum, PDM_CLK_CTRL, 12, rpaths_text); +static SOC_ENUM_SINGLE_DECL(rpath1_enum, PDM_CLK_CTRL, 10, rpaths_text); +static SOC_ENUM_SINGLE_DECL(rpath0_enum, PDM_CLK_CTRL, 8, rpaths_text); + static const struct snd_kcontrol_new rockchip_pdm_controls[] = { + SOC_ENUM("Receive PATH3 Source Select", rpath3_enum), + SOC_ENUM("Receive PATH2 Source Select", rpath2_enum), + SOC_ENUM("Receive PATH1 Source Select", rpath1_enum), + SOC_ENUM("Receive PATH0 Source Select", rpath0_enum), + { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = "PDM Start Delay Ms", From 19820cc6531ada1b7df295ed50b108f4736c8f34 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Fri, 22 Sep 2023 15:19:38 +0800 Subject: [PATCH 3/7] drm/bridge: synopsys: Recover sound for XRUN routine This patch add audio reset in prepare stage to clean audio FIFO to recover sound from XRUN state. Change-Id: I3808be7973306cc6f8d377f5eb5a0bcec844ab16 Signed-off-by: Sugar Zhang --- .../drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c index f7db2e8e3321..95b0caef8b4e 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c @@ -132,6 +132,23 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, return 0; } +static int dw_hdmi_i2s_prepare(struct device *dev, void *data, + struct hdmi_codec_daifmt *fmt, + struct hdmi_codec_params *hparms) +{ + struct dw_hdmi_i2s_audio_data *audio = data; + struct dw_hdmi *hdmi = audio->hdmi; + + dw_hdmi_audio_disable(hdmi); + + hdmi_write(audio, HDMI_AUD_CONF0_SW_RESET, HDMI_AUD_CONF0); + hdmi_write(audio, (u8)~HDMI_MC_SWRSTZ_I2SSWRST_REQ, HDMI_MC_SWRSTZ); + + dw_hdmi_audio_enable(hdmi); + + return 0; +} + static int dw_hdmi_i2s_audio_startup(struct device *dev, void *data) { struct dw_hdmi_i2s_audio_data *audio = data; @@ -198,6 +215,7 @@ static int dw_hdmi_i2s_hook_plugged_cb(struct device *dev, void *data, static struct hdmi_codec_ops dw_hdmi_i2s_ops = { .hw_params = dw_hdmi_i2s_hw_params, + .prepare = dw_hdmi_i2s_prepare, .audio_startup = dw_hdmi_i2s_audio_startup, .audio_shutdown = dw_hdmi_i2s_audio_shutdown, .get_eld = dw_hdmi_i2s_get_eld, From 78f7fcfc45d955fcdf39711f2ca3633a97d186e1 Mon Sep 17 00:00:00 2001 From: XiaoTan Luo Date: Wed, 19 Jul 2023 16:08:44 +0800 Subject: [PATCH 4/7] pinctrl: rockchip: rv1126: Add I2Sx-SCLK as iomux-route switch Considering the MCLK is not a MUST for codec, but the SCLK is. So, let's add SCLK as iomux-route switch. Still keep the MCLK as iomux-route switch to allow the pin can be used individually. Change-Id: I855cd399ada956434a820db06ca586de986caa11 Signed-off-by: XiaoTan Luo Signed-off-by: Sugar Zhang --- drivers/pinctrl/pinctrl-rockchip.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 81191ae3f8ed..619d19d21f00 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -702,14 +702,23 @@ static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { static struct rockchip_mux_route_data rv1126_mux_route_data[] = { RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ + RK_MUXROUTE_GRF(3, RK_PD1, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_SCLK_RX_M0 */ + RK_MUXROUTE_GRF(3, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_SCLK_TX_M0 */ RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ + RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_SCLK_RX_M1 */ + RK_MUXROUTE_GRF(3, RK_PA4, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_SCLK_TX_M1 */ RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */ + RK_MUXROUTE_GRF(1, RK_PA1, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_SCLK_M0 */ RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */ + RK_MUXROUTE_GRF(1, RK_PD6, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_SCLK_M1 */ RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */ + RK_MUXROUTE_GRF(2, RK_PD1, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_SCLK_M2 */ RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */ + RK_MUXROUTE_GRF(1, RK_PC6, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_SCLK_M0 */ RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */ + RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_SCLK_M1 */ RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */ RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */ From 11f85a1a0fddac7a2cfc9ba4c69c8b7b8759cd6d Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Fri, 1 Sep 2023 15:33:33 +0800 Subject: [PATCH 5/7] pinctrl: rockchip: rk3568: Add I2Sx-SCLK as iomux-route switch Considering the MCLK is not a MUST for codec, but the SCLK is. So, let's add SCLK as iomux-route switch. Still keep the MCLK as iomux-route switch to allow the pin can be used individually. Signed-off-by: Sugar Zhang Change-Id: Iab96f63ab93a5429c6b76dc1b0cb3c9d5e43d2e4 --- drivers/pinctrl/pinctrl-rockchip.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 619d19d21f00..5b876bad86a0 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1021,13 +1021,25 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = { RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */ RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */ RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */ - RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */ - RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */ - RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */ - RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */ - RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */ - RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */ - RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */ + RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 MCLK mux M0 */ + RK_MUXROUTE_GRF(1, RK_PA4, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 SCLKRX mux M0 */ + RK_MUXROUTE_GRF(1, RK_PA3, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 SCLKTX mux M0 */ + RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 MCLK mux M1 */ + RK_MUXROUTE_GRF(4, RK_PA6, 5, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 SCLKRX mux M1 */ + RK_MUXROUTE_GRF(3, RK_PC7, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 SCLKTX mux M1 */ + RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 MCLK mux M2 */ + RK_MUXROUTE_GRF(3, RK_PC3, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 SCLKRX mux M2 */ + RK_MUXROUTE_GRF(2, RK_PD1, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 SCLKTX mux M2 */ + RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 MCLK mux M0 */ + RK_MUXROUTE_GRF(2, RK_PB7, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 SCLKRX mux M0 */ + RK_MUXROUTE_GRF(2, RK_PC2, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 SCLKTX mux M0 */ + RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 MCLK mux M1 */ + RK_MUXROUTE_GRF(4, RK_PC1, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 SCLKRX mux M1 */ + RK_MUXROUTE_GRF(4, RK_PB7, 4, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 SCLKTX mux M1 */ + RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 MCLK mux M0 */ + RK_MUXROUTE_GRF(3, RK_PA3, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 SCLK mux M0 */ + RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 MCLK mux M1 */ + RK_MUXROUTE_GRF(4, RK_PC3, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 SCLK mux M1 */ RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ From 2e8f56f6a521f69409f84e8baeb4675ab2284cbf Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Fri, 1 Sep 2023 15:33:33 +0800 Subject: [PATCH 6/7] pinctrl: rockchip: rk3328: Add I2Sx-SCLK as iomux-route switch Considering the MCLK is not a MUST for codec, but the SCLK is. So, let's add SCLK as iomux-route switch. Signed-off-by: Sugar Zhang Change-Id: I7010268ee4d2ee43670bb7fc118f4a39ab24a666 --- drivers/pinctrl/pinctrl-rockchip.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 5b876bad86a0..01a5c1a2ed62 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -932,7 +932,9 @@ static struct rockchip_mux_route_data rk3328_mux_route_data[] = { RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */ RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */ RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */ + RK_MUXROUTE_SAME(1, RK_PC6, 1, 0x50, BIT(16 + 6)), /* i2s2_sclkm0 */ RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */ + RK_MUXROUTE_SAME(3, RK_PA0, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sclkm1 */ RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */ RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */ RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */ From c2ce04151037c490cfddd1819d17c536cc429277 Mon Sep 17 00:00:00 2001 From: XiaoDong Huang Date: Mon, 25 Sep 2023 10:43:19 +0800 Subject: [PATCH 7/7] soc: rockchip: pm_config: do pm_wakeup_clear when virtual poweroff pm_wakeup_pending will return 1 after system wakeup, witch makes the failure of disable_secondary_cpus when virtual poweroff. So we need to do pm_wakeup_clear before disable_secondary_cpus. Signed-off-by: XiaoDong Huang Change-Id: I96722898d22cd2c2ad8229e44b9ecbfa9024a2e4 --- drivers/soc/rockchip/rockchip_pm_config.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/rockchip/rockchip_pm_config.c b/drivers/soc/rockchip/rockchip_pm_config.c index 4ff89bf8b7c2..0972dbe2893b 100644 --- a/drivers/soc/rockchip/rockchip_pm_config.c +++ b/drivers/soc/rockchip/rockchip_pm_config.c @@ -103,6 +103,8 @@ static void rockchip_pm_virt_pwroff_prepare(void) { int error; + pm_wakeup_clear(0); + regulator_suspend_prepare(PM_SUSPEND_MEM); error = suspend_disable_secondary_cpus();