From 5a0e89a9bf272c57e5f0ce1908b1b5b5e5b3e607 Mon Sep 17 00:00:00 2001
From: Felix Zeng <felix.zeng@rock-chips.com>
Date: Thu, 23 Dec 2021 21:25:07 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3588: Add rknpu relative node

Signed-off-by: Felix Zeng <felix.zeng@rock-chips.com>
Change-Id: I37de6e34fa56bbb38f20cf14d790118458d45ab5
---
 arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 67 +++++++++++++----------
 1 file changed, 39 insertions(+), 28 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 7385fb607870..7fdfdd8b7935 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1880,38 +1880,49 @@
 		};
 	};
 
-	npu0_mmu: iommu@fdab9000 {
-		compatible = "rockchip,iommu-v2";
-		reg = <0x0 0xfdab9000 0x0 0x100>, <0x0 0xfdaba000 0x0 0x100>;
-		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "npu0_mmu";
-		clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>;
-		clock-names = "aclk", "iface";
-		power-domains = <&power RK3588_PD_NPUTOP>;
-		#iommu-cells = <0>;
+	rknpu: npu@fdab0000 {
+		compatible = "rockchip,rk3588-rknpu";
+		reg = <0x0 0xfdab0000 0x0 0x10000>,
+		      <0x0 0xfdac0000 0x0 0x10000>,
+		      <0x0 0xfdad0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "npu0_irq", "npu1_irq", "npu2_irq";
+		clocks = <&cru ACLK_NPU0>, <&cru ACLK_NPU1>, <&cru ACLK_NPU2>,
+			 <&cru HCLK_NPU0>, <&cru HCLK_NPU1>, <&cru HCLK_NPU2>,
+			 <&cru PCLK_NPU_ROOT>;
+		clock-names = "aclk0", "aclk1", "aclk2",
+			      "hclk0", "hclk1", "hclk2",
+			      "pclk";
+		assigned-clocks = <&cru CLK_NPU_DSU0>;
+		assigned-clock-rates = <800000000>;
+		resets = <&cru SRST_A_RKNN0>, <&cru SRST_A_RKNN1>, <&cru SRST_A_RKNN2>,
+			 <&cru SRST_H_RKNN0>, <&cru SRST_H_RKNN1>, <&cru SRST_H_RKNN2>;
+		reset-names = "srst_a0", "srst_a1", "srst_a2",
+			      "srst_h0", "srst_h1", "srst_h2";
+		power-domains = <&power RK3588_PD_NPUTOP>,
+				<&power RK3588_PD_NPU1>,
+				<&power RK3588_PD_NPU2>;
+		power-domain-names = "npu0", "npu1", "npu2";
+		iommus = <&rknpu_mmu>;
 		status = "disabled";
 	};
 
-	npu1_mmu: iommu@fdaca000 {
+	rknpu_mmu: iommu@fdab9000 {
 		compatible = "rockchip,iommu-v2";
-		reg = <0x0 0xfdaca000 0x0 0x100>;
-		interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "npu1_mmu";
-		clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>;
-		clock-names = "aclk", "iface";
-		power-domains = <&power RK3588_PD_NPU1>;
-		#iommu-cells = <0>;
-		status = "disabled";
-	};
-
-	npu2_mmu: iommu@fdada000 {
-		compatible = "rockchip,iommu-v2";
-		reg = <0x0 0xfdada000 0x0 0x100>;
-		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "npu2_mmu";
-		clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>;
-		clock-names = "aclk", "iface";
-		power-domains = <&power RK3588_PD_NPU2>;
+		reg = <0x0 0xfdab9000 0x0 0x100>,
+		      <0x0 0xfdaba000 0x0 0x100>,
+		      <0x0 0xfdaca000 0x0 0x100>,
+		      <0x0 0xfdada000 0x0 0x100>;
+		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "npu0_mmu", "npu1_mmu", "npu2_mmu";
+		clocks = <&cru ACLK_NPU0>, <&cru ACLK_NPU1>, <&cru ACLK_NPU2>,
+			 <&cru HCLK_NPU0>, <&cru HCLK_NPU1>, <&cru HCLK_NPU2>;
+		clock-names = "aclk0", "aclk1", "aclk2",
+			      "iface0", "iface1", "iface2";
 		#iommu-cells = <0>;
 		status = "disabled";
 	};