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rk29: ddr_recofig: add ddr_reconfig.c
This commit is contained in:
黄涛
549
arch/arm/mach-rk29/ddr_reconfig.c
Normal file
549
arch/arm/mach-rk29/ddr_reconfig.c
Normal file
@@ -0,0 +1,549 @@
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static __sramdata uint32_t ddrreg[0x40];
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extern void local_flush_tlb_all(void);
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#if 1
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unsigned int __sramlocalfunc ddr_datatraining(int nMHz)
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{
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pDDR_Reg->CSR =0x0;
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pDDR_Reg->DRR |= RD;
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delayus(1);
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pDDR_Reg->CCR |= DTT;
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dsb();
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do{
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delayus(1);
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}while(pGRF_Reg->GRF_MEM_STATUS[2] &0x1);
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if(pDDR_Reg->CSR & 0x100000)
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while(1);
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pDDR_Reg->DRR &= ~RD;
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return 0;
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}
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void __sramlocalfunc ddrReg_Save(void)
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{
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int i=0;
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// pDDR_REG_T pDDR_Reg=((pDDR_REG_T)RK29_DDRC_BASE);
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for(i =0; i<0x30; i++)
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ddrreg[i] =*(unsigned long volatile *)(RK29_DDRC_BASE +i*4);
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ddrreg[3] =0;
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ddrreg[i++] =*(unsigned long volatile *)(RK29_DDRC_BASE +0x7c*4); //pDDR_Reg->MR;
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ddrreg[i++] =*(unsigned long volatile *)(RK29_DDRC_BASE +0x7d*4);
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ddrreg[i++] =*(unsigned long volatile *)(RK29_DDRC_BASE +0x7e*4);
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ddrreg[i++] =*(unsigned long volatile *)(RK29_DDRC_BASE +0x7f*4);
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//rest reg did not saved yet
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}
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void __sramlocalfunc ddrReg_Restore(void)
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{
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int i=0;
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// pDDR_REG_T pDDR_Reg=((pDDR_REG_T)RK29_DDRC_BASE);
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for(i =0; i<0x30; i++)
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*(unsigned long volatile *)(RK29_DDRC_BASE +i*4) =ddrreg[i];
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*(unsigned long volatile *)(RK29_DDRC_BASE +0x7c*4) =ddrreg[i++];
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*(unsigned long volatile *)(RK29_DDRC_BASE +0x7d*4) =ddrreg[i++];
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*(unsigned long volatile *)(RK29_DDRC_BASE +0x7e*4) =ddrreg[i++];
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*(unsigned long volatile *)(RK29_DDRC_BASE +0x7f*4) =ddrreg[i++];
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//rest reg did not saved yet
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}
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void __sramlocalfunc Delay10cyc(int count)
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{
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volatile int i;
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while(count--)
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{
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for (i=0; i<8; i++); //12*8+8=104cyc
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}
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}
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#define RECONFIG_DEBUG 0
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#if RECONFIG_DEBUG
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unsigned int __sramdata mem[42];
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unsigned int __sramdata maxtimeout =0;
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#endif
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unsigned int __sramdata gpu_suspended;
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unsigned int __sramdata gpu_power;
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unsigned int __sramdata gpu_clock;
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unsigned int __sramdata gpuctl;
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unsigned int __sramdata gpususpendcmd =0x7;
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unsigned int __sramdata currcmdbufadr;
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unsigned int __sramdata clksel17;
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unsigned int __sramdata cru_gatecon[4];
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unsigned int __sramdata i2sxfer;
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void __sramlocalfunc __ddr_reconfig(int mode)
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{
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#if 1
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int i, n, bakdatr;
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volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
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// __cpuc_flush_kern_all();
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// __cpuc_flush_user_all();
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local_flush_tlb_all();
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n=temp[0];
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barrier();
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n=temp[1024];
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barrier();
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n=temp[1024*2];
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barrier();
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n=temp[1024*3];
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barrier();
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n= pSCU_Reg->CRU_SOFTRST_CON[0];
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dsb();
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pDDR_Reg->DLLCR09[0] &=~0x3c000;
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pDDR_Reg->DLLCR09[1] &=~0x3c000;
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pDDR_Reg->DLLCR09[2] &=~0x3c000;
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pDDR_Reg->DLLCR09[3] &=~0x3c000;
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pDDR_Reg->DLLCR09[0] |=0x4000; //set 90-18
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pDDR_Reg->DLLCR09[1] |=0x4000;
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pDDR_Reg->DLLCR09[2] |=0x4000;
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pDDR_Reg->DLLCR09[3] |=0x4000;
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n=pGRF_Reg->GRF_OS_REG[2]; // *(unsigned long volatile *)(0xf50080d8);
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pDDR_Reg->CCR &= ~HOSTEN; //ddr3 400m 4us 4*6*rank+1;
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pDDR_Reg->DCR = (pDDR_Reg->DCR & (~((0x1<<24) | (0x1<<13) | (0xF<<27) | (0x1<<31)))) | ((0x1<<13) | (0x2<<27) | (0x1<<31)); //enter Self Refresh
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while(pDDR_Reg->DCR &(0x1<<31)); //may done soon
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ddrReg_Save();
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#if 1
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#if 1
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//DO_INT Must be cleared before ddrReg_Save
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pSCU_Reg->CRU_SOFTRST_CON[2] |= ((0x3<<15) | (0x3<<11) |(0x3<<8));
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pSCU_Reg->CRU_SOFTRST_CON[0] |= (0x7f<<18);
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dsb();
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Delay10cyc(100);
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pSCU_Reg->CRU_SOFTRST_CON[2] &= ~((0x3<<15) | (0x3<<11) | (0x3<<8));
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// if((mode >>12)&0xfff)
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// *(unsigned long volatile *)(0xf50080ac) =mode &0xfff;
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pDDR_Reg->PQCR[0] =0x0e03f000;
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pDDR_Reg->PQCR[1] =(mode ==0) ?0x0e000000 : 0x0e00f000;
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// pDDR_Reg->PQCR[2] =0x0e00f000;
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ddrReg_Restore();
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pDDR_Reg->MMGCR =((mode&0xf) ==0) ?0 : 2;
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pSCU_Reg->CRU_SOFTRST_CON[0] &=~(0x7F<<18);
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dsb();
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Delay10cyc(200); //need 1024 cycles, worst case assume ddr @200MHZ, cpu at @1GHZ, need 5120 cycles delay
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// if((pDDR_Reg->DRR) &0x0f000000)
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// while(1);
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#else
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cru_gatecon[0] =pSCU_Reg->CRU_CLKGATE_CON[0];
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cru_gatecon[1] =pSCU_Reg->CRU_CLKGATE_CON[1];
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cru_gatecon[3] =pSCU_Reg->CRU_CLKGATE_CON[3];
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pSCU_Reg->CRU_CLKGATE_CON[0] |=/*(2<<19)*/(3<<9);
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pSCU_Reg->CRU_CLKGATE_CON[1] |=(1<<6);
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pSCU_Reg->CRU_CLKGATE_CON[3] |=((1<<1) |(0xf<<10) |(0xf<<14));
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pSCU_Reg->CRU_SOFTRST_CON[2] |=(1<<9);// ((0x1<<15) | (0x3<<11) | (0x3<<8));
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dsb();
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Delay10cyc(100);
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pSCU_Reg->CRU_SOFTRST_CON[0] |= (0x7f<<18);
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Delay10cyc(100);
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pSCU_Reg->CRU_SOFTRST_CON[2] &= ~((0x1<<15) | (0x3<<11) | (0x3<<8));
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if((mode >>12)&0xfff)
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*(unsigned long volatile *)(0xf50080ac) =mode &0xfff;
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pDDR_Reg->PQCR[0] =0x0e03f000;
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pDDR_Reg->PQCR[1] =0x0e01f000;
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pDDR_Reg->PQCR[2] =0x0e00f000;
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ddrReg_Restore();
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pDDR_Reg->MMGCR =(mode ==0) ?0:2;
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dsb();
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pSCU_Reg->CRU_SOFTRST_CON[0] &=~(0x7F<<18);
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dsb();
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Delay10cyc(100);
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pSCU_Reg->CRU_CLKGATE_CON[0]=cru_gatecon[0];
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pSCU_Reg->CRU_CLKGATE_CON[1]=cru_gatecon[1];
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pSCU_Reg->CRU_CLKGATE_CON[3]=cru_gatecon[3];
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Delay10cyc(200); //need 1024 cycles, worst case assume ddr @200MHZ, cpu at @1GHZ, need 5120 cycles delay
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#endif
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pDDR_Reg->DCR |= DO_INIT;
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while(pGRF_Reg->GRF_MEM_STATUS[2] & 0x1) //wait init ok
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Delay10cyc(1);
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pDDR_Reg->DRR |=(1<<31);
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Delay10cyc(10);
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pDDR_Reg->CCR |= DTT; //ddr3 400m 4us 4*6*rank+1;
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Delay10cyc(100);
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while(pGRF_Reg->GRF_MEM_STATUS[2] & 0x1) //wait dtt ok
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Delay10cyc(1);
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if(pGRF_Reg->GRF_MEM_STATUS[2] & 0x2)
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while(1);
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pDDR_Reg->DRR &=~(1<<31);
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pDDR_Reg->DLLCR09[0] &=~0x3c000;
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pDDR_Reg->DLLCR09[1] &=~0x3c000;
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pDDR_Reg->DLLCR09[2] &=~0x3c000;
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pDDR_Reg->DLLCR09[3] &=~0x3c000;
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pDDR_Reg->DLLCR09[0] |=0x10000; //set 90+18
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pDDR_Reg->DLLCR09[1] |=0x10000;
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pDDR_Reg->DLLCR09[2] |=0x10000;
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pDDR_Reg->DLLCR09[3] |=0x10000;
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pDDR_Reg->DCR &=~DO_INIT;
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pDDR_Reg->CCR |= HOSTEN; //enable host port
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dsb();
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#endif
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#endif
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}
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unsigned int tmodelay1us(unsigned int tmo)
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{
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delayus(1);
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return tmo +1;
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}
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/**********************************
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*input mode
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*case mode
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*0 normal
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*1 cpu priority highest
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*2 cpu priority ualtra
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GRF_MEM_CON[1:0]: CPU (host 0)
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[3:2]: PERI (host 1)
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[5:4]: DISPLAY (host 2)
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[7:6]: GPU (host 3)
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[9:8]: VCODEC (host 4)
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***********************************/
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void/* inline*/ __sramfunc sram_printch(char byte);
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int ddr_reconfig(int mode)
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{
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int baklcdctrl;
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int count =0;
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int i;
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unsigned int ret =0;
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unsigned int con3save, flags;
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unsigned int tmo =0;
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mode &=0xf;
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if((pDDR_Reg->MMGCR ==0) &&(mode <2))
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{
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pDDR_Reg->PQCR[0] =(mode ==0) ?0x0e000000 : 0x0e00f000;
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pDDR_Reg->PQCR[1] =(mode ==0) ?0x0e000000 : 0x0e03f000;
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pDDR_Reg->PQCR[2] =(mode ==0) ?0x0e000000 : 0x0e00f000;
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pGRF_Reg->GRF_MEM_CON = (pGRF_Reg->GRF_MEM_CON & ~0x3FF)
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| ((mode ==0) ?((2<<0)|(1<<2)|(0<<4)|(1<<6)|(2<<8)):((0<<0)|(2<<2)|(1<<4)|(2<<6)|(2<<8)));
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return 1;
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}
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local_irq_save(flags);
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sram_printch('1');
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/* if(mode ==2)
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{
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tmp =*(unsigned long volatile *)(0xf50080bc);
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pDDR_Reg->PQCR[0] =0x0e03f000;
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pDDR_Reg->PQCR[1] =0x0e01f000;
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pDDR_Reg->PQCR[2] =0x0e00f000;
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pDDR_Reg->MMGCR =(mode ==0) ?0 : 2;
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}
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*/
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// asm volatile ("cpsid if");
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{
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__cpuc_flush_kern_all();
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__cpuc_flush_user_all();
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dsb();
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//some risk: if a common to lcdc is going, then a read form 0xf410c0000 may retrun an old val
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con3save =pSCU_Reg->CRU_CLKGATE_CON[3];
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pSCU_Reg->CRU_CLKGATE_CON[3] =con3save |(1<<3);
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pGRF_Reg->GRF_SOC_CON[0] |=(1<<0);
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{
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gpu_suspended =0;
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gpu_power =0;
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gpu_clock =0;
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if((*(unsigned long volatile *)(RK29_PMU_BASE +0x10) &0x40) ==0)
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{
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gpu_power =1;
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if((0xf<<14) !=(pSCU_Reg->CRU_CLKGATE_CON[3] &(0xf<<14)))
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{
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gpu_clock =1;
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if(*(unsigned long volatile *)(RK29_GPU_BASE +0x4) !=0x7fffffff)
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{ //clock enable and not at idle
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gpu_suspended =1;
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#if 1
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#if 1
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int chktime =0;
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for(chktime =0; chktime<32; chktime++ )
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{
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if(*(unsigned long volatile *)(RK29_GPU_BASE +0x4) !=0x7ffffffe)
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{ chktime =0;
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//
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if((tmo =tmodelay1us(tmo)) >10)
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#if 0 //RECONFIG_DEBUG
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while(1);
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#else
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goto ddr_reconfig_cancel;
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#endif
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}
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}
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#if RECONFIG_DEBUG
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if(tmo >maxtimeout)
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{
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maxtimeout =tmo;
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printk("maxtimout %d\n", maxtimeout);
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}
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#endif
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{
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unsigned int i,tmp;
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currcmdbufadr =*(unsigned long volatile *)(RK29_GPU_BASE +0x664);
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if((currcmdbufadr&0xfff0) ==0)
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for(i =0; i<6; i++)
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{
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tmp =*(unsigned long volatile *)(RK29_GPU_BASE +0x664);
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if(((tmp >currcmdbufadr) &&((tmp -currcmdbufadr) >0x10))
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||((tmp <currcmdbufadr) &&((currcmdbufadr -tmp) >0x10)))
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{
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printk("gpu:cmdbuffer base reg read error 0x%x !=0x%x\n", tmp, currcmdbufadr);
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i =0;
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}
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else
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delayus(1);
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currcmdbufadr =tmp;
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}
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}
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#if 0
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for(i =0; i<0x1000; i++)
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{
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unsigned int tmp;
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if(currcmdbufadr >(tmp =*(unsigned long volatile *)(0xf4120664)))
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currcmdbufadr =tmp;
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}
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#else
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if(*(int *)(currcmdbufadr +0x60000000) !=0x380000c8) //0x60000000 assume VA =PA +0x60000000
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{
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currcmdbufadr -=8;
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if(*(int *)(currcmdbufadr +0x60000000) !=0x380000c8)
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{
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currcmdbufadr -=8;
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if(*(int *)(currcmdbufadr +0x60000000) !=0x380000c8)
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#if RECONFIG_DEBUG
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while(1);
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#else
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goto ddr_reconfig_cancel;
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#endif
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}
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}
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#endif
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#if 0 //RECONFIG_DEBUG
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if((currcmdbufadr &0xffffe000) !=0x736ce000)
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while(1);
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{
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int i;
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for(i =0; i<16; i++)
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mem[i] =*(int *)(currcmdbufadr +0x60000000 +(i-4)*4);
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}
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#endif
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#endif
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*(unsigned long volatile *)(RK29_GPU_BASE +0x658) =0x2;
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dsb();
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while(*(unsigned long volatile *)(RK29_GPU_BASE +0x4) !=0x7fffffff) delayus(1); //
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#else
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gpuctl =*(unsigned long volatile *)(RK29_GPU_BASE +0x0);
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*(unsigned long volatile *)(RK29_GPU_BASE +0x0) =gpususpendcmd;
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delayus(100);
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#endif
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}
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}
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}
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sram_printch('5');
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if(!(gpu_clock &gpu_power))
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{
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unsigned int tmoadd1ms =tmo +3000;
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sram_printch('c');
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// if(tmo==0)
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if(pGRF_Reg->GRF_OS_REG[3] ==0xff)
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while(1);
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pSCU_Reg->CRU_CLKGATE_CON[3] =(con3save |(1<<3)) &0xfffc3fff;
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clksel17 =pSCU_Reg->CRU_CLKSEL_CON[17];
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pSCU_Reg->CRU_CLKSEL_CON[17]&=~(3<<14);
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dsb();
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*(unsigned long volatile *)(RK29_PMU_BASE +0x10) &=~0x40;
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dsb();
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while((tmo =tmodelay1us(tmo)) <tmoadd1ms);
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pSCU_Reg->CRU_CLKGATE_CON[3] =(con3save |(1<<3)) &0xfffc3fff;
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}
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}
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sram_printch('6');
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//status check
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//3 VIP clock con2[22,18](0x20000064) VIPCTL[0](0x10108010) 0==stop
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while(((0)==(pSCU_Reg->CRU_CLKGATE_CON[2] &((0x1<<18)|(0x1<<22))))
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&&((0)!=(*(unsigned long volatile *)(RK29_VIP_BASE +0x10) &(1<<0))) &&((1)!=(*(unsigned long volatile *)(RK29_VIP_BASE +0x2c) &(1<<0))))
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if((tmo =tmodelay1us(tmo)) >20)
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#if RECONFIG_DEBUG
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// goto ddr_reconfig_cancel2;
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while(1);
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#else
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goto ddr_reconfig_cancel2;
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#endif
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sram_printch('7');
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//1 IPP clock_con3[5:4](0x20000068) INT_ST[6](0x10110010) 1 ==working
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if(((0)==(pSCU_Reg->CRU_CLKGATE_CON[3] &(0x3<<4))) &&
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((0)!=(*(unsigned long volatile *)(RK29_IPP_BASE +0x10) &(1<<6))))
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if((tmo =tmodelay1us(tmo)) >200000)
|
||||
#if RECONFIG_DEBUG
|
||||
while(1);
|
||||
#else
|
||||
goto ddr_reconfig_cancel2;
|
||||
#endif
|
||||
sram_printch('8');
|
||||
//2 SDMA0 clock con0[10](0x2000005c) DSR[3:0](0x20180000) 0 ==stop
|
||||
|
||||
// i2sxfer =*(unsigned long volatile *)(RK29_I2S0_BASE +0x28);
|
||||
// *(unsigned long volatile *)(RK29_I2S0_BASE +0x28) =0;
|
||||
while(((0)==(pSCU_Reg->CRU_CLKGATE_CON[0] &(0x1<<10)))
|
||||
&&(((0)!=(*(unsigned long volatile *)(RK29_SDMAC0_BASE +0x0) &(0xf<<0)))
|
||||
||(((0)!=(*(unsigned long volatile *)(RK29_SDMAC0_BASE +0x100) &(0xf<<0)))/*&& ((0x27)!=(*(unsigned long volatile *)(RK29_SDMAC0_BASE +0x100) &(0xff<<0)))*/)
|
||||
||((0)!=(*(unsigned long volatile *)(RK29_SDMAC0_BASE +0x108) &(0xf<<0)))
|
||||
||((0)!=(*(unsigned long volatile *)(RK29_SDMAC0_BASE +0x110) &(0xf<<0)))
|
||||
||((0)!=(*(unsigned long volatile *)(RK29_SDMAC0_BASE +0x118) &(0xf<<0)))))
|
||||
if((tmo =tmodelay1us(tmo)) >200000)
|
||||
#if RECONFIG_DEBUG
|
||||
while(1);
|
||||
#else
|
||||
goto ddr_reconfig_cancel2;
|
||||
#endif
|
||||
sram_printch('9');
|
||||
//2 DMA0 clock con0[9](0x2000005c) DSR[3:0](0x201C0000) 0 ==stop
|
||||
while(((0)==(pSCU_Reg->CRU_CLKGATE_CON[0] &(0x1<<9)))
|
||||
&&(((0)!=(*(unsigned long volatile *)(RK29_DMAC0_BASE +0x0) &(0xf<<0)))
|
||||
||((0)!=(*(unsigned long volatile *)(RK29_DMAC0_BASE +0x100) &(0xf<<0)))
|
||||
||((0)!=(*(unsigned long volatile *)(RK29_DMAC0_BASE +0x108) &(0xf<<0)))
|
||||
||((0)!=(*(unsigned long volatile *)(RK29_DMAC0_BASE +0x110) &(0xf<<0)))
|
||||
||((0)!=(*(unsigned long volatile *)(RK29_DMAC0_BASE +0x118) &(0xf<<0)))))
|
||||
if((tmo =tmodelay1us(tmo)) >200000)
|
||||
#if RECONFIG_DEBUG
|
||||
while(1);
|
||||
#else
|
||||
goto ddr_reconfig_cancel2;
|
||||
#endif
|
||||
sram_printch('a');
|
||||
//2 DMA1 clock con1[5](0x20000060) DSR[3:0](0x20078000) 0 ==stop
|
||||
while(((0)==(pSCU_Reg->CRU_CLKGATE_CON[1] &(0x1<<5)))
|
||||
&&(((0)!=(*(unsigned long volatile *)(RK29_DMAC1_BASE +0x0) &(0xf<<0)))
|
||||
||((0)!=(*(unsigned long volatile *)(RK29_DMAC1_BASE +0x100) &(0xf<<0)))
|
||||
||((0)!=(*(unsigned long volatile *)(RK29_DMAC1_BASE +0x108) &(0xf<<0)))
|
||||
||((0)!=(*(unsigned long volatile *)(RK29_DMAC1_BASE +0x110) &(0xf<<0)))
|
||||
||((0)!=(*(unsigned long volatile *)(RK29_DMAC1_BASE +0x118) &(0xf<<0)))))
|
||||
if((tmo =tmodelay1us(tmo)) >200000)
|
||||
#if RECONFIG_DEBUG
|
||||
while(1);
|
||||
#else
|
||||
goto ddr_reconfig_cancel2;
|
||||
#endif
|
||||
sram_printch('b');
|
||||
/*
|
||||
//4 USB
|
||||
if(((0)==(*(unsigned long volatile *)(0xf5000068) &(0x3<<4))) &&
|
||||
((0)==(*(unsigned long volatile *)(0xf4110010) &(1<<6))))
|
||||
while(1);
|
||||
*/
|
||||
//5 VPU when select VDPU clk VDPU clock con2[19,13:12]else con2[18,11:10] (0x20000068) wreg[1](0x10104204) 0==stop
|
||||
//wreg24[0] 0==stop
|
||||
{
|
||||
int clkgatemask;
|
||||
clkgatemask =((0x1<<18)|(0x3<<10))<<((((pGRF_Reg->GRF_SOC_CON[0]))>>23) &1);
|
||||
if((0)==(pSCU_Reg->CRU_CLKGATE_CON[3] &clkgatemask))
|
||||
while((((0)!=(*(unsigned long volatile *)(RK29_VCODEC_BASE +0x204) &(1<<0)))
|
||||
&&((0)==(*(unsigned long volatile *)(RK29_VCODEC_BASE +0x204) &(1<<13)))) //until idle or buff_int
|
||||
||((0)!=(*(unsigned long volatile *)(RK29_VCODEC_BASE +0x38) &(1<<0))))
|
||||
if((tmo =tmodelay1us(tmo)) >200000)
|
||||
#if RECONFIG_DEBUG
|
||||
while(1);
|
||||
#else
|
||||
goto ddr_reconfig_cancel2;
|
||||
#endif
|
||||
}
|
||||
// while(((0xf<<14)!=(pSCU_Reg->CRU_CLKGATE_CON[3] &(0xf<<14))) &&
|
||||
// (*(unsigned long volatile *)(0xf4120004) !=0x7fffffff));
|
||||
sram_printch('2');
|
||||
|
||||
{
|
||||
static unsigned long save_sp;
|
||||
|
||||
DDR_SAVE_SP(save_sp);
|
||||
{
|
||||
__ddr_reconfig(mode);
|
||||
|
||||
}
|
||||
DDR_RESTORE_SP(save_sp);
|
||||
} // do_ddr_reconfig(mode);
|
||||
///////////////////////////////////////////////////////////
|
||||
sram_printch('3');
|
||||
ret =1;
|
||||
// *(unsigned long volatile *)(RK29_I2S0_BASE +0x28) =i2sxfer;
|
||||
if(gpu_suspended)
|
||||
{
|
||||
#if 1
|
||||
*(unsigned long volatile *)(RK29_GPU_BASE +0x654) =currcmdbufadr;
|
||||
*(unsigned long volatile *)(RK29_GPU_BASE +0x658) =0x10002;
|
||||
dsb();
|
||||
while(*(unsigned long volatile *)(RK29_GPU_BASE +0x4) !=0x7ffffffe);
|
||||
#if RECONFIG_DEBUG
|
||||
mem[34] =*(unsigned long volatile *)(RK29_GPU_BASE +0x660);
|
||||
mem[35] =*(unsigned long volatile *)(RK29_GPU_BASE +0x664);
|
||||
mem[36] =*(unsigned long volatile *)(RK29_GPU_BASE +0x668);
|
||||
mem[37] =*(unsigned long volatile *)(RK29_GPU_BASE +0x66c);
|
||||
{
|
||||
int i;
|
||||
for(i =0; i<16; i++)
|
||||
mem[i+16] =*(int *)(currcmdbufadr +0x60000000 +(i-4)*4);
|
||||
}
|
||||
mem[32] =currcmdbufadr;
|
||||
mem[33]++;
|
||||
// printk("reconfig 0x%x ,0x%x ,0x%x ,0x%x ,", *(unsigned int volatile *)(0xf4120660),
|
||||
// *(unsigned int volatile *)(0xf4120664),*(unsigned int volatile *)(0xf4120668),
|
||||
// *(unsigned int volatile *)(0xf412066c));
|
||||
#endif
|
||||
#else
|
||||
*(unsigned long volatile *)(RK29_GPU_BASE +0x0) =gpuctl;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if RECONFIG_DEBUG
|
||||
printk("clkgate =0x%x, 0x%x\n",pSCU_Reg->CRU_CLKGATE_CON[3],tmo);
|
||||
#endif
|
||||
count++;
|
||||
|
||||
ddr_reconfig_cancel2:
|
||||
if(!gpu_clock )
|
||||
pSCU_Reg->CRU_CLKSEL_CON[17] =clksel17;
|
||||
if(!gpu_power)
|
||||
*(unsigned long volatile *)(RK29_PMU_BASE +0x10) |=0x40;
|
||||
dsb();
|
||||
#if RECONFIG_DEBUG
|
||||
if((gpu_power ==0) &&( 1 ==gpu_clock))
|
||||
while(1);
|
||||
#endif
|
||||
ddr_reconfig_cancel:
|
||||
pSCU_Reg->CRU_CLKGATE_CON[3] =con3save;
|
||||
pGRF_Reg->GRF_SOC_CON[0]&=~(1<<0);
|
||||
}
|
||||
local_irq_restore(flags);
|
||||
sram_printch('4');
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
int rk29fb_irq_notify_ddr(void)
|
||||
{
|
||||
{
|
||||
int tmp;
|
||||
if(((tmp =*(unsigned long volatile *)(RK29_LCDC_BASE)) &(2<<10)) ==0) //win 0 blanked
|
||||
{
|
||||
if((tmp &(1<<10)) &&(((pDDR_Reg->MMGCR &(1<<1)) ==2) ||((pGRF_Reg->GRF_MEM_CON &0x3) ==0))) //has OSD and current ddr is supper priority
|
||||
ddr_reconfig(0);
|
||||
}
|
||||
else
|
||||
{
|
||||
if(((pDDR_Reg->MMGCR &(1<<1)) ==0) &&((pGRF_Reg->GRF_MEM_CON &0x3) ==2)) //current not supper priority
|
||||
{
|
||||
if((((tmp >>3) &0x7) <2) &&((tmp &(1<<10)) ==0)) //LCD is RGB format, has not OSD
|
||||
ddr_reconfig(1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//#include "ddr_test.c"
|
||||
|
||||
Reference in New Issue
Block a user