From 5a2cf6377478e77d0a23e33231e78fa6bb6de526 Mon Sep 17 00:00:00 2001
From: Liang Chen <cl@rock-chips.com>
Date: Fri, 4 Dec 2020 14:33:50 +0800
Subject: [PATCH] arm64: dts: rockchip: add core dtsi for RK3566 Soc

RK3566 is a Soc from Rockchip, which embedded with quad
ARM Cortex-A55.

This patch add basic core dtsi file for RK3566.

Change-Id: Ide02369e6be3515fb7ec62bea4069f476374f897
Signed-off-by: Liang Chen <cl@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3566.dtsi | 46 ++++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3566.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
new file mode 100644
index 000000000000..4ac532cd1ca4
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ */
+
+#include "rk3568.dtsi"
+
+/ {
+	aliases {
+		/delete-property/ ethernet0;
+	};
+};
+
+&cpu0_opp_table {
+	/delete-node/ opp-1992000000;
+};
+
+&power {
+	pd_pipe@RK3568_PD_PIPE {
+		reg = <RK3568_PD_PIPE>;
+		clocks = <&cru PCLK_PIPE>;
+		pm_qos = <&qos_pcie2x1>,
+			 <&qos_sata0>,
+			 <&qos_sata1>,
+			 <&qos_usb3_0>,
+			 <&qos_usb3_1>;
+	};
+};
+
+&usbdrd_dwc3 {
+	phys = <&u2phy0_otg>;
+	phy-names = "usb2-phy";
+	extcon = <&usb2phy0>;
+	maximum-speed = "high-speed";
+};
+
+/delete-node/ &gmac0_clkin;
+/delete-node/ &gmac0;
+/delete-node/ &pcie30_phy_grf;
+/delete-node/ &pcie30phy;
+/delete-node/ &pcie3x1;
+/delete-node/ &pcie3x2;
+/delete-node/ &qos_pcie3x1;
+/delete-node/ &qos_pcie3x2;
+/delete-node/ &qos_sata2;
+/delete-node/ &sata2;