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codec pll set 798 for gpu 266m,change cpufreq interactive load

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This commit is contained in:
xxx
2012-04-10 13:55:29 -07:00
parent e8d8e5ee34
commit 5b16541e72
5 changed files with 11 additions and 9 deletions
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2
arch/arm/mach-rk30/board-rk30-sdk.c
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@@ -1237,7 +1237,7 @@ static struct cpufreq_frequency_table cpu_dvfs_table[] = {
void __init board_clock_init(void)
{
rk30_clock_data_init(periph_pll_297mhz, codec_pll_360mhz, max_i2s_12288khz);
rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), cpu_dvfs_table);
}

4
arch/arm/mach-rk30/clock_data.c
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@@ -1029,7 +1029,8 @@ static const struct pll_clk_set cpll_clks[] = {
_PLL_SET_CLKS(504000, 1, 21, 1),
_PLL_SET_CLKS(552000, 1, 23, 1),
_PLL_SET_CLKS(600000, 1, 25, 1),
_PLL_SET_CLKS( 0, 1, 23, 1),
_PLL_SET_CLKS(798000, 4, 133, 1),
_PLL_SET_CLKS( 0, 4, 133, 1),
};
static struct _pll_data cpll_data=SET_PLL_DATA(CPLL_ID,(void *)cpll_clks);
static struct clk codec_pll_clk = {
@@ -3007,7 +3008,6 @@ static void __init rk30_clock_common_init(unsigned long gpll_rate,unsigned long
clk_set_rate_nolock(&aclk_vepu, 300*MHZ);
clk_set_rate_nolock(&aclk_vdpu, 300*MHZ);
//gpu auto sel
//clk_set_parent_nolock(&clk_gpu, &general_pll_clk);
}

4
arch/arm/mach-rk30/dvfs.c
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@@ -487,7 +487,7 @@ int dvfs_target_cpu(struct clk *clk, unsigned long rate_hz)
/* if up the voltage*/
if (volt_old < volt_new) {
if(dvfs_clk->vd->regulator&&dvfs_regulator_set_voltage(dvfs_clk->vd->regulator,volt_new, volt_new) < 0) {
DVFS_ERR("set voltage err\n");
DVFS_ERR("set voltage err up\n");
return -1;
}
dvfs_clk->vd->cur_volt = volt_new;
@@ -512,7 +512,7 @@ int dvfs_target_cpu(struct clk *clk, unsigned long rate_hz)
/* if down the voltage */
if (volt_old > volt_new) {
if(dvfs_clk->vd->regulator&&dvfs_regulator_set_voltage(dvfs_clk->vd->regulator, volt_new, volt_new) < 0) {
DVFS_ERR("set voltage err\n");
DVFS_ERR("set voltage err dn\n");
return -1;
}
dvfs_clk->vd->cur_volt = volt_new;

4
arch/arm/mach-rk30/include/mach/board.h
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@@ -63,7 +63,8 @@ enum _codec_pll {
codec_pll_504mhz = 504000000,
codec_pll_552mhz = 552000000, /* for HDMI */
codec_pll_600mhz = 600000000,
codec_pll_default = codec_pll_360mhz,
codec_pll_798mhz = 798000000,
codec_pll_default = codec_pll_798mhz,
};
//has extern 27mhz
#define CLK_FLG_EXT_27MHZ (1<<0)
@@ -74,5 +75,6 @@ enum _codec_pll {
#define CLK_FLG_MAX_I2S_49152KHZ (1<<4)
#define max_i2s_12288khz (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/)
#define RK30_CLOCKS_DEFAULT_FLAGS (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/)
#endif

6
drivers/cpufreq/cpufreq_interactive.c Normal file → Executable file
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@@ -63,7 +63,7 @@ static struct mutex set_speed_lock;
static u64 hispeed_freq;
/* Go to hi speed when CPU load at or above this value. */
#ifdef CONFIG_ARCH_RK29
#ifdef CONFIG_PLAT_RK
#define DEFAULT_GO_HISPEED_LOAD 80
#else
#define DEFAULT_GO_HISPEED_LOAD 95
@@ -186,7 +186,7 @@ static void cpufreq_interactive_timer(unsigned long data)
new_freq = pcpu->freq_table[index].frequency;
#ifdef CONFIG_ARCH_RK29
#ifdef CONFIG_PLAT_RK
pcpu->target_freq = pcpu->policy->cur;
#endif
if (pcpu->target_freq == new_freq)
@@ -570,7 +570,7 @@ static int cpufreq_governor_interactive(struct cpufreq_policy *policy,
}
if (!hispeed_freq)
#ifdef CONFIG_ARCH_RK29
#ifdef CONFIG_PLAT_RK
hispeed_freq = 816000;
#else
hispeed_freq = policy->max;