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net/mlx5: Explicitly set scheduling element and TSAR type

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[ Upstream commit c88146abe4d0f8cf659b2b8883fdc33936d2e3b8 ]

Ensure the scheduling element type and TSAR type are explicitly
initialized in the QoS rate group creation.

This prevents potential issues due to default values.

Fixes: 1ae258f8b3 ("net/mlx5: E-switch, Introduce rate limiting groups API")
Signed-off-by: Carolina Jubran <cjubran@nvidia.com>
Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Carolina Jubran
2024-09-02 11:46:14 +03:00
committed by Greg Kroah-Hartman
parent f062f17f0b
commit 5b3cbf4fbf
1 changed files with 7 additions and 0 deletions
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7
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
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@@ -420,6 +420,7 @@ __esw_qos_create_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *ex
{ {
u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {}; u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {};
struct mlx5_esw_rate_group *group; struct mlx5_esw_rate_group *group;
__be32 *attr;
u32 divider; u32 divider;
int err; int err;
@@ -427,6 +428,12 @@ __esw_qos_create_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *ex
if (!group) if (!group)
return ERR_PTR(-ENOMEM); return ERR_PTR(-ENOMEM);
MLX5_SET(scheduling_context, tsar_ctx, element_type,
SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR);
attr = MLX5_ADDR_OF(scheduling_context, tsar_ctx, element_attributes);
*attr = cpu_to_be32(TSAR_ELEMENT_TSAR_TYPE_DWRR << 16);
MLX5_SET(scheduling_context, tsar_ctx, parent_element_id, MLX5_SET(scheduling_context, tsar_ctx, parent_element_id,
esw->qos.root_tsar_ix); esw->qos.root_tsar_ix);
err = mlx5_create_scheduling_element_cmd(esw->dev, err = mlx5_create_scheduling_element_cmd(esw->dev,