From 5b68eec983778c21db877170bef22bce6aa4454c Mon Sep 17 00:00:00 2001 From: Tao Huang Date: Tue, 27 Mar 2018 17:02:10 +0800 Subject: [PATCH] clk: rockchip: drop severity of 'invalid clk rate' message These are noisy during boot: [ 0.000000] GIC: Using split EOI/Deactivate mode [ 0.000000] rockchip_mmc_get_phase: invalid clk rate [ 0.000000] rockchip_mmc_get_phase: invalid clk rate [ 0.000000] rockchip_mmc_get_phase: invalid clk rate [ 0.000000] rockchip_mmc_get_phase: invalid clk rate [ 0.000000] rockchip_mmc_get_phase: invalid clk rate [ 0.000000] rockchip_mmc_get_phase: invalid clk rate [ 0.000000] Architected cp15 timer(s) running at 24.00MHz (phys). Change-Id: I0a5ca5a1e0b6c6ba9038fa64635dc448bb5c612b Signed-off-by: Tao Huang Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-mmc-phase.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c index 026a26bb702d..b1450f2011bb 100644 --- a/drivers/clk/rockchip/clk-mmc-phase.c +++ b/drivers/clk/rockchip/clk-mmc-phase.c @@ -62,7 +62,7 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw) /* See the comment for rockchip_mmc_set_phase below */ if (!rate) { - pr_err("%s: invalid clk rate\n", __func__); + printk(KERN_DEBUG "%s: invalid clk rate\n", __func__); return -EINVAL; }