From 5b781b56eedc4fbbadb775d7ab0a0e558ac5efab Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Thu, 14 Dec 2023 17:41:54 +0800 Subject: [PATCH] clk: rockchip: px30: mark dpll as critical Signed-off-by: Elaine Zhang Change-Id: Ie72aecf05bcc6f3081f7f837c6ead4a680f9e2f3 --- drivers/clk/rockchip/clk-px30.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c index 82699681b5bf..d76aaf04b3e7 100644 --- a/drivers/clk/rockchip/clk-px30.c +++ b/drivers/clk/rockchip/clk-px30.c @@ -191,7 +191,7 @@ static struct rockchip_pll_clock px30_pll_clks[] __initdata = { CLK_IS_CRITICAL, PX30_PLL_CON(0), PX30_MODE_CON, 0, 0, 0, px30_pll_rates), [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, - 0, PX30_PLL_CON(8), + CLK_IS_CRITICAL, PX30_PLL_CON(8), PX30_MODE_CON, 4, 1, 0, NULL), [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 0, PX30_PLL_CON(16),