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vdin: XGIMI,keytone,Wake up after STR stb,screen is always black [1/1]

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PD#SWPL-12972

Problem:
vdin regs has been set to default when entering suspend.

Solution:
don't set regs since upper layer will not start again after resume.

Verify:
verified by t962x2_x301

Change-Id: Ic1042e0b1a9ba4482fe79c51606e366f60e31f59
Signed-off-by: zhiwei.yuan <zhiwei.yuan@amlogic.com>
This commit is contained in:
zhiwei.yuan
2019-08-20 17:02:52 +08:00
committed by Tao Zeng
parent 57a88b2925
commit 5bad6566dd
1 changed files with 35 additions and 2 deletions
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37
drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c
View File

@@ -3418,7 +3418,24 @@ static int vdin_drv_suspend(struct platform_device *pdev, pm_message_t state)
cpumask_copy(&vdinirq_mask, mask);
}
vdevp->flags |= VDIN_FLAG_SUSPEND;
vdin_enable_module(vdevp->addr_offset, false);
/*no need setting any regs*/
/*vdin_enable_module(vdevp->addr_offset, false);*/
/* disable clock of blackbar, histogram, histogram, line fifo1, matrix,
* hscaler, pre hscaler, clock0
*/
/* [15:14] Disable blackbar clock = 01/(auto, off, on, on) */
/* [13:12] Disable histogram clock = 01/(auto, off, on, on) */
/* [11:10] Disable line fifo1 clock = 01/(auto, off, on, on) */
/* [ 9: 8] Disable matrix clock = 01/(auto, off, on, on) */
/* [ 7: 6] Disable hscaler clock = 01/(auto, off, on, on) */
/* [ 5: 4] Disable pre hscaler clock = 01/(auto, off, on, on) */
/* [ 3: 2] Disable clock0 = 01/(auto, off, on, on) */
/* [ 0] Enable register clock = 00/(auto, off!!!!!!!!) */
switch_vpu_clk_gate_vmod(vdevp->addr_offset == 0
? VPU_VIU_VDIN0 : VPU_VIU_VDIN1,
VPU_CLK_GATE_OFF);
pr_info("%s ok.\n", __func__);
return 0;
}
@@ -3428,7 +3445,23 @@ static int vdin_drv_resume(struct platform_device *pdev)
struct vdin_dev_s *vdevp;
vdevp = platform_get_drvdata(pdev);
vdin_enable_module(vdevp->addr_offset, true);
/*no need resume anything*/
/*vdin_enable_module(vdevp->addr_offset, true);*/
/* enable clock of blackbar, histogram, histogram, line fifo1, matrix,
* hscaler, pre hscaler, clock0
*/
/* [15:14] Enable blackbar clock = 00/(auto, off, on, on) */
/* [13:12] Enable histogram clock = 00/(auto, off, on, on) */
/* [11:10] Enable line fifo1 clock = 00/(auto, off, on, on) */
/* [ 9: 8] Enable matrix clock = 00/(auto, off, on, on) */
/* [ 7: 6] Enable hscaler clock = 00/(auto, off, on, on) */
/* [ 5: 4] Enable pre hscaler clock = 00/(auto, off, on, on) */
/* [ 3: 2] Enable clock0 = 00/(auto, off, on, on) */
/* [ 0] Enable register clock = 00/(auto, off!!!!!!!!) */
switch_vpu_clk_gate_vmod(vdevp->addr_offset == 0
? VPU_VIU_VDIN0 : VPU_VIU_VDIN1,
VPU_CLK_GATE_ON);
if (vdevp->irq) {
if (!irq_can_set_affinity(vdevp->irq))