From 5bc85371a34f7fbb9eab01f8bd056b40da1a3955 Mon Sep 17 00:00:00 2001
From: Shawn Lin <shawn.lin@rock-chips.com>
Date: Tue, 13 Oct 2020 10:12:41 +0800
Subject: [PATCH] arm64: dts: rockchip: Add emmc node for RK3568 Soc

Change-Id: Ie7773e81bc3102379bf4aa30505c6c5cbcfadee3
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3568.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index c5489246d253..d9a7048502d9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -447,6 +447,19 @@
 		reg = <0x0 0xfe1a8100 0x0 0x20>;
 	};
 
+	sdhci: sdhci@fe310000 {
+		compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci";
+		reg = <0x0 0xfe310000 0x0 0x10000>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+		assigned-clocks = <&cru CCLK_EMMC>, <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
+		assigned-clock-rates = <200000000>, <200000000>, <24000000>;
+		clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
+			 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
+			 <&cru TCLK_EMMC>;
+		clock-names = "core", "bus", "axi", "block", "timer";
+		status = "disabled";
+	};
+
 	nandc0: nandc@fe330000 {
 		compatible = "rockchip,rk-nandc";
 		reg = <0x0 0xfe330000 0x0 0x4000>;