shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-05 10:31:46 +09:00
Code Issues Packages Projects Releases Wiki Activity

arm64: dts: mediatek: mt8195: Add missing gce-client-reg to vpp/vdosys

Browse Source 
[ Upstream commit 96b0c1528ef41fe754f5d1378b1db6c098a2e33f ]

Add the missing mediatek,gce-client-reg property to the vppsys and
vdosys nodes to allow them to use the GCE. This prevents the "can't
parse gce-client-reg property" error from being printed and should
result in better performance.

Fixes: 6aa5b46d17 ("arm64: dts: mt8195: Add vdosys and vppsys clock nodes")
Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20240229-gce-client-reg-add-missing-mt8192-95-v1-2-b12c233a8a33@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Nícolas F. R. A. Prado
2024-02-29 14:44:29 -05:00
committed by Greg Kroah-Hartman
parent 18548e2ab9
commit 5bcfc53373
1 changed files with 3 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@@ -1492,6 +1492,7 @@
compatible = "mediatek,mt8195-vppsys0"; compatible = "mediatek,mt8195-vppsys0";
reg = <0 0x14000000 0 0x1000>; reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>; #clock-cells = <1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
}; };
smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
@@ -1597,6 +1598,7 @@
compatible = "mediatek,mt8195-vppsys1"; compatible = "mediatek,mt8195-vppsys1";
reg = <0 0x14f00000 0 0x1000>; reg = <0 0x14f00000 0 0x1000>;
#clock-cells = <1>; #clock-cells = <1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
}; };
larb5: larb@14f02000 { larb5: larb@14f02000 {
@@ -1982,6 +1984,7 @@
reg = <0 0x1c01a000 0 0x1000>; reg = <0 0x1c01a000 0 0x1000>;
mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
#clock-cells = <1>; #clock-cells = <1>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
}; };
larb20: larb@1b010000 { larb20: larb@1b010000 {