From 5bd7ed321edd3b346ec96e3099283a21ff6e1b31 Mon Sep 17 00:00:00 2001 From: Xingyu Chen Date: Mon, 1 May 2017 23:47:31 +0800 Subject: [PATCH] pinctrl: add pinctrl&gpio support for axg PD#142470: add pinctrl&gpio support for axg 1. meson8b keeps the same pin numbers as the gxl/gxm/axg 2. using base address of registers(Eg: mux gpio irq) instead of offset address in dts for gxl/gxm Change-Id: Ib64f9dc0e234884ec9ccab7673da5f2a3fdc1a98 Signed-off-by: Xingyu Chen --- .../bindings/pinctrl/meson,pinctrl.txt | 2 + MAINTAINERS | 5 + arch/arm64/boot/dts/amlogic/mesonaxg.dtsi | 95 +- arch/arm64/boot/dts/amlogic/mesongxl.dtsi | 1052 ++++++++-------- arch/arm64/boot/dts/amlogic/mesongxm.dtsi | 1070 +++++++++-------- drivers/amlogic/pinctrl/Makefile | 2 +- drivers/amlogic/pinctrl/pinctrl-meson.c | 295 ++++- drivers/amlogic/pinctrl/pinctrl-meson.h | 47 +- drivers/amlogic/pinctrl/pinctrl-meson8b.c | 734 ++++++----- drivers/amlogic/pinctrl/pinctrl-mesonaxg.c | 482 ++++++++ include/dt-bindings/gpio/meson8b-gpio.h | 36 +- include/dt-bindings/gpio/mesonaxg-gpio.h | 125 ++ 12 files changed, 2450 insertions(+), 1495 deletions(-) create mode 100644 drivers/amlogic/pinctrl/pinctrl-mesonaxg.c create mode 100644 include/dt-bindings/gpio/mesonaxg-gpio.h diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt index 2392557ede27..2c12f9789116 100644 --- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt @@ -9,6 +9,8 @@ Required properties for the root node: "amlogic,meson-gxbb-aobus-pinctrl" "amlogic,meson-gxl-periphs-pinctrl" "amlogic,meson-gxl-aobus-pinctrl" + "amlogic,meson-axg-periphs-pinctrl" + "amlogic,meson-axg-aobus-pinctrl" - reg: address and size of registers controlling irq functionality === GPIO sub-nodes === diff --git a/MAINTAINERS b/MAINTAINERS index c98316280ac5..9f1bcdc32554 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13890,3 +13890,8 @@ F: sound/soc/codecs/amlogic/Kconfig F: sound/soc/codecs/amlogic/Makefile F: sound/soc/codecs/amlogic/tas5707.c F: sound/soc/codecs/amlogic/tas5707.h + +AMLOGIC PINCTRL SUPPORT FOR AXG +M: Xingyu Chen +F: drivers/amlogic/pinctrl/pinctrl-mesonaxg.c +F: include/dt-bindings/gpio/mesonaxg-gpio.h diff --git a/arch/arm64/boot/dts/amlogic/mesonaxg.dtsi b/arch/arm64/boot/dts/amlogic/mesonaxg.dtsi index d3059506dd84..c57a6dec2325 100644 --- a/arch/arm64/boot/dts/amlogic/mesonaxg.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesonaxg.dtsi @@ -193,6 +193,59 @@ sys_poweroff = <0x84000008>; }; + pinctrl_aobus: pinctrl@ff800014{ + compatible = "amlogic,meson-axg-aobus-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio_ao: ao-bank@ff800014{ + reg = <0x0 0xff800014 0x0 0x8>, + <0x0 0xff80002c 0x0 0x4>, + <0x0 0xff800024 0x0 0x8>, + <0x0 0xff800084 0x0 0x4>; + interrupts = <0 200 1>, + <0 201 1>; + reg-names = "mux", "pull", "gpio", "irq"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pinctrl_periphs: pinctrl@ff634480{ + compatible = "amlogic,meson-axg-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: banks@ff634480{ + reg = <0x0 0xff634480 0x0 0x40>, + <0x0 0xff6344e8 0x0 0x14>, + <0x0 0xff634520 0x0 0x14>, + <0x0 0xff634430 0x0 0x3c>, + <0x0 0xffd0f080 0x0 0x10>; + interrupts = <0 64 1>, + <0 65 1>, + <0 66 1>, + <0 67 1>, + <0 68 1>, + <0 69 1>, + <0 70 1>, + <0 71 1>; + reg-names = "mux", + "pull", + "pull-enable", + "gpio", + "irq"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -225,12 +278,21 @@ }; };/* end of aobus */ - hiubus: hiubus@ff600000 { + periphs: periphs@ff634400 { compatible = "simple-bus"; - reg = <0x0 0xff600000 0x0 0x4c000>; + reg = <0x0 0xff634400 0x0 0x1c00>; #address-cells = <2>; #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff600000 0x0 0x4c000>; + ranges = <0x0 0x0 0x0 0xff634400 0x0 0x1c00>; + + };/* end of periphs */ + + hiubus: hiubus@ff63c000 { + compatible = "simple-bus"; + reg = <0x0 0xff63c000 0x0 0x10000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x10000>; clkc: clock-controller@0 { compatible = "amlogic,axg-clkc"; @@ -238,9 +300,32 @@ reg = <0x0 0x3c000 0x0 0x320>; }; };/* end of hiubus*/ - - }; /* end of soc*/ };/* end of / */ +&pinctrl_aobus { + remote_pins:remote_pin { + mux { + pins = "GPIOAO_6"; + function = "ir_in"; + }; + }; +}; /* end of pinctrl_aobus */ + +&pinctrl_periphs { + a_i2c_master:a_i2c { + mux { + pins = "GPIOZ_6","GPIOZ_7"; + function = "i2c_a"; + }; + }; + + b_i2c_master:b_i2c { + mux { + pins = "GPIOZ_8","GPIOZ_9"; + function = "i2c_b"; + }; + + }; +}; /* end of pinctrl_periphs */ diff --git a/arch/arm64/boot/dts/amlogic/mesongxl.dtsi b/arch/arm64/boot/dts/amlogic/mesongxl.dtsi index 956e10c1996a..6d9691556d2f 100644 --- a/arch/arm64/boot/dts/amlogic/mesongxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesongxl.dtsi @@ -356,81 +356,131 @@ pinctrl-0 = <&ao_b_uart_pins>; }; - i2c_ao: i2c@c8100500{ /*I2C-AO*/ - compatible = "amlogic, meson-i2c"; - dev_name = "i2c-AO"; - status = "disabled"; - reg = <0x0 0xc8100500 0x0 0x1d>; - device_id = <0>; - pinctrl-names="default"; - pinctrl-0=<&ao_i2c_master>; - #address-cells = <1>; - #size-cells = <0>; - use_pio = <0>; - master_i2c_speed = <300000>; - clocks = <&clkc CLKID_AO_I2C>; - clock-names = "clk_i2c"; +i2c_ao: i2c@c8100500{ /*I2C-AO*/ + compatible = "amlogic, meson-i2c"; + dev_name = "i2c-AO"; + status = "disabled"; + reg = <0x0 0xc8100500 0x0 0x1d>; + device_id = <0>; + pinctrl-names="default"; + pinctrl-0=<&ao_i2c_master>; + #address-cells = <1>; + #size-cells = <0>; + use_pio = <0>; + master_i2c_speed = <300000>; + clocks = <&clkc CLKID_AO_I2C>; + clock-names = "clk_i2c"; + }; + i2c_a: i2c@c1108500{ /*I2C-A*/ + compatible = "amlogic, meson-i2c"; + dev_name = "i2c-A"; + status = "disabled"; + reg = <0x0 0xc1108500 0x0 0x20>; + device_id = <1>; + pinctrl-names="default"; + pinctrl-0=<&a_i2c_master>; + #address-cells = <1>; + #size-cells = <0>; + use_pio = <0>; + master_i2c_speed = <300000>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + i2c_b: i2c@c11087c0{ /*I2C-B*/ + compatible = "amlogic, meson-i2c"; + dev_name = "i2c-B"; + status = "disabled"; + reg = <0x0 0xc11087c0 0x0 0x20>; + device_id = <2>; + pinctrl-names="default"; + pinctrl-0=<&b_i2c_master>; + #address-cells = <1>; + #size-cells = <0>; + use_pio = <0>; + master_i2c_speed = <300000>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + i2c_c: i2c@c11087e0{ /*I2C-C*/ + compatible = "amlogic, meson-i2c"; + dev_name = "i2c-C"; + status = "disabled"; + reg = <0x0 0xc11087e0 0x0 0x20>; + device_id = <3>; + pinctrl-names="default"; + pinctrl-0=<&c_i2c_master>; + #address-cells = <1>; + #size-cells = <0>; + use_pio = <0>; + master_i2c_speed = <300000>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + i2c_d: i2c@c1108d20{ /*I2C-D*/ + compatible = "amlogic, meson-i2c"; + dev_name = "i2c-D"; + status = "disabled"; + reg = <0x0 0xc1108d20 0x0 0x20>; + device_id = <4>; + pinctrl-names="default"; + pinctrl-0=<&d_i2c_master>; + #address-cells = <1>; + #size-cells = <0>; + use_pio = <0>; + master_i2c_speed = <300000>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + + pinctrl_aobus: pinctrl@14 { + compatible = "amlogic,meson-gxl-aobus-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio_ao: bank@14 { + reg = <0x0 0xc8100014 0x0 0x8>, + <0x0 0xc810002c 0x0 0x4>, + <0x0 0xc8100024 0x0 0x8>, + <0x0 0xc8100084 0x0 0x4>; + interrupts = <0 200 IRQ_TYPE_EDGE_RISING>, + <0 201 IRQ_TYPE_EDGE_RISING>; + reg-names = "mux", "pull", "gpio", "irq"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; - i2c_a: i2c@c1108500{ /*I2C-A*/ - compatible = "amlogic, meson-i2c"; - dev_name = "i2c-A"; - status = "disabled"; - reg = <0x0 0xc1108500 0x0 0x20>; - device_id = <1>; - pinctrl-names="default"; - pinctrl-0=<&a_i2c_master>; - #address-cells = <1>; - #size-cells = <0>; - use_pio = <0>; - master_i2c_speed = <300000>; - clocks = <&clkc CLKID_I2C>; - clock-names = "clk_i2c"; - }; - i2c_b: i2c@c11087c0{ /*I2C-B*/ - compatible = "amlogic, meson-i2c"; - dev_name = "i2c-B"; - status = "disabled"; - reg = <0x0 0xc11087c0 0x0 0x20>; - device_id = <2>; - pinctrl-names="default"; - pinctrl-0=<&b_i2c_master>; - #address-cells = <1>; - #size-cells = <0>; - use_pio = <0>; - master_i2c_speed = <300000>; - clocks = <&clkc CLKID_I2C>; - clock-names = "clk_i2c"; - }; - i2c_c: i2c@c11087e0{ /*I2C-C*/ - compatible = "amlogic, meson-i2c"; - dev_name = "i2c-C"; - status = "disabled"; - reg = <0x0 0xc11087e0 0x0 0x20>; - device_id = <3>; - pinctrl-names="default"; - pinctrl-0=<&c_i2c_master>; - #address-cells = <1>; - #size-cells = <0>; - use_pio = <0>; - master_i2c_speed = <300000>; - clocks = <&clkc CLKID_I2C>; - clock-names = "clk_i2c"; - }; - i2c_d: i2c@c1108d20{ /*I2C-D*/ - compatible = "amlogic, meson-i2c"; - dev_name = "i2c-D"; - status = "disabled"; - reg = <0x0 0xc1108d20 0x0 0x20>; - device_id = <4>; - pinctrl-names="default"; - pinctrl-0=<&d_i2c_master>; - #address-cells = <1>; - #size-cells = <0>; - use_pio = <0>; - master_i2c_speed = <300000>; - clocks = <&clkc CLKID_I2C>; - clock-names = "clk_i2c"; + }; + + pinctrl_periphs: pinctrl@4b0 { + compatible = "amlogic,meson-gxl-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@4b0 { + reg = <0x0 0xc88344b0 0x0 0x28>, + <0x0 0xc88344e8 0x0 0x14>, + <0x0 0xc8834120 0x0 0x14>, + <0x0 0xc8834430 0x0 0x40>, + <0x0 0xc1109880 0x0 0x10>; + interrupts = <0 64 IRQ_TYPE_EDGE_RISING>, + <0 65 IRQ_TYPE_EDGE_RISING>, + <0 66 IRQ_TYPE_EDGE_RISING>, + <0 67 IRQ_TYPE_EDGE_RISING>, + <0 68 IRQ_TYPE_EDGE_RISING>, + <0 69 IRQ_TYPE_EDGE_RISING>, + <0 70 IRQ_TYPE_EDGE_RISING>, + <0 71 IRQ_TYPE_EDGE_RISING>; + reg-names = "mux", "pull", + "pull-enable", "gpio", "irq"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; + }; soc { compatible = "simple-bus"; @@ -454,8 +504,7 @@ aobus: aobus@c8100000 { compatible = "simple-bus"; - reg = <0x0 0xc8100000 0x0 0x100000>, - <0x0 0xc8100084 0x0 0x4>; + reg = <0x0 0xc8100000 0x0 0x100000>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; @@ -467,8 +516,7 @@ periphs: periphs@c8834000 { compatible = "simple-bus"; - reg = <0x0 0xc8834000 0x0 0x2000>, - <0x0 0xc1109880 0x0 0x10>; + reg = <0x0 0xc8834000 0x0 0x2000>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; @@ -498,461 +546,435 @@ }; /* end of soc */ }; /* end of root */ -&aobus { - pinctrl_aobus: pinctrl@14 { - compatible = "amlogic,meson-gxl-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x00014 0x0 0x8>, - <0x0 0x0002c 0x0 0x4>, - <0x0 0x00024 0x0 0x8>; - interrupts = <0 200 IRQ_TYPE_EDGE_RISING>, - <0 201 IRQ_TYPE_EDGE_RISING>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; +&pinctrl_aobus { + remote_pins:remote_pin { + mux { + groups = "remote_input"; + function = "remote"; }; + }; - remote_pins:remote_pin { - mux { - groups = "remote_input"; - function = "remote"; - }; - }; - sd_to_ao_uart_pins:sd_to_ao_uart_pins { - mux { - groups = "uart_tx_ao_a_0", - "uart_rx_ao_a_0"; - function = "uart_ao"; - bias-pull-up; - input-enable; - }; - }; - - ao_uart_pins:ao_uart { - mux { - groups = "uart_tx_ao_a_0", + sd_to_ao_uart_pins:sd_to_ao_uart_pins { + mux { + groups = "uart_tx_ao_a_0", "uart_rx_ao_a_0"; - function = "uart_ao"; + function = "uart_ao"; + bias-pull-up; + input-enable; + }; + }; + + ao_uart_pins:ao_uart { + mux { + groups = "uart_tx_ao_a_0", + "uart_rx_ao_a_0"; + function = "uart_ao"; + }; + }; + + ao_b_uart_pins:ao_b_uart { + mux { + groups = "uart_tx_ao_b_0", + "uart_rx_ao_b_0"; + function = "uart_ao_b"; + }; + }; + ao_i2c_master:ao_i2c{ + mux { + groups = "i2c_sda_ao", + "i2c_sck_ao"; + function = "i2c_ao"; + }; + }; + + hdmitx_aocec: hdmitx_aocec { + mux { + groups = "ao_cec"; + function = "ao_cec"; + }; + }; + + hdmitx_eecec: hdmitx_eecec { + mux { + groups = "ee_cec"; + function = "ee_cec"; + }; + }; +}; /* end of pinctrl_aobus*/ + +&pinctrl_periphs { + external_eth_pins:external_eth_pins { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_clk_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_rxd2", + "eth_rxd3", + "eth_rgmii_tx_clk", + "eth_tx_en", + "eth_txd0", + "eth_txd1", + "eth_txd2", + "eth_txd3"; + function = "eth"; + }; + }; + + jtag_apao_pins:jtag_apao_pin { + mux { + groups = "jtag_tdi_0", + "jtag_tdo_0", + "jtag_clk_0", + "jtag_tms_0"; + function = "jtag"; + }; + }; + + jtag_apee_pins:jtag_apee_pin { + mux { + groups ="jtag_tdi_1", + "jtag_tdo_1", + "jtag_clk_1", + "jtag_tms_1"; + function = "jtag"; + }; + }; + + a_uart_pins:a_uart { + mux { + groups = "uart_tx_a", + "uart_rx_a", + "uart_cts_a", + "uart_rts_a"; + function = "uart_a"; + }; + }; + + b_uart_pins:b_uart { + mux { + groups = "uart_tx_b", + "uart_rx_b", + "uart_cts_b", + "uart_rts_b"; + function = "uart_b"; + }; + }; + + c_uart_pins:c_uart { + mux { + groups = "uart_tx_c", + "uart_rx_c", + "uart_cts_c", + "uart_rts_c"; + function = "uart_c"; + }; + }; + + wifi_32k_pins:wifi_32k_pins { + mux { + groups ="pwm_e"; + function = "pwm_e"; + }; + }; + +/* +* sd_clk_cmd_pins:sd_clk_cmd_pins{ +* }; +* sd_all_pins:sd_all_pins { +* }; +* sd_1bit_pins:sd_1bit_pins{ +* }; +* sd_clk_cmd_uart_pins:sd_clk_cmd_uart_pins { +* }; +* sd_1bit_uart_pins:sd_1bit_uart_pins { +* }; +* sd_to_ao_jtag_pins:sd_to_ao_jtag_pins{ +* }; +*/ + ao_to_sd_uart_pins:ao_to_sd_uart_pins { + mux { + groups = "uart_tx_ao_a_1", + "uart_rx_ao_a_1"; + function = "uart_ao_a_1"; + bias-pull-up; + input-enable; }; }; - ao_b_uart_pins:ao_b_uart { - mux { - groups = "uart_tx_ao_b_0", - "uart_rx_ao_b_0"; - function = "uart_ao_b"; - }; - }; - ao_i2c_master:ao_i2c{ - mux { - groups = "i2c_sda_ao", - "i2c_sck_ao"; - function = "i2c_ao"; - }; + emmc_clk_cmd_pins:emmc_clk_cmd_pins { + mux { + groups = "emmc_cmd", + "emmc_clk"; + function = "emmc"; + input-enable; + bias-pull-up; }; + }; - hdmitx_aocec: hdmitx_aocec { - mux { - groups = "ao_cec"; - function = "ao_cec"; - }; - }; - hdmitx_eecec: hdmitx_eecec { - mux { - groups = "ee_cec"; - function = "ee_cec"; - }; + emmc_conf_pull_up:emmc_conf_pull_up { + mux { + groups = "emmc_nand_d07", + "emmc_clk", + "emmc_cmd"; + function = "emmc"; + input-enable; + bias-pull-up; }; - }; /* end of pinctrl_aobus*/ + }; -}; /* end of aobus*/ + emmc_conf_pull_done:emmc_conf_pull_done { + mux { + groups = "emmc_ds"; + function = "emmc"; + input-enable; + bias-pull-down; + }; + }; + + sd_clk_cmd_pins:sd_clk_cmd_pins{ + mux { + groups = "sdcard_cmd", + "sdcard_clk"; + function = "sdcard"; + input-enable; + bias-pull-up; + }; + }; + + sd_all_pins:sd_all_pins{ + mux { + groups = "sdcard_d0", + "sdcard_d1", + "sdcard_d2", + "sdcard_d3", + "sdcard_cmd", + "sdcard_clk"; + function = "sdcard"; + input-enable; + bias-pull-up; + }; + }; + + sdio_clk_cmd_pins:sdio_clk_cmd_pins { + mux { + groups = "sdio_clk", + "sdio_cmd"; + function = "sdio"; + input-enable; + bias-pull-up; + }; + }; + + sdio_all_pins:sdio_all_pins { + mux { + groups = "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", + "sdio_clk", + "sdio_cmd"; + function = "sdio"; + input-enable; + bias-pull-up; + }; + }; + + nand_pulldown: nand_pulldown { + mux { + groups = "emmc_nand_d07", + "emmc_ds"; + function = "emmc"; + bias-pull-down; + }; + }; + + nand_pullup: nand_pullup { + mux { + groups = "emmc_clk", + "emmc_cmd"; + function = "emmc"; + bias-pull-up; + }; + }; + + all_nand_pins: all_nand_pins { + mux { + groups = "emmc_nand_d07", + "nand_ce0", + "nand_ce1", + "nand_rb0", + "nand_ale", + "nand_cle", + "nand_wen_clk", + "nand_ren_wr", + "nand_dqs"; + function = "nand"; + input-enable; + }; + }; + + nand_cs_pins: nand_cs { + mux { + groups = "nand_ce0", + "nand_ce1"; + function = "nand"; + }; + }; + + hdmitx_hpd: hdmitx_hpd { + mux { + groups = "hdmi_hpd"; + function = "hdmi_hpd"; + }; + }; + + hdmitx_ddc: hdmitx_ddc { + mux { + groups = "hdmi_sda", + "hdmi_scl"; + function = "hdmi_ddc"; + }; + }; + + a_i2c_master:a_i2c { + mux { + groups = "i2c_sda_a", + "i2c_scl_a"; + function = "i2c_a"; + }; + }; + + b_i2c_master:b_i2c { + mux { + groups = "i2c_sda_b", + "i2c_scl_b"; + function = "i2c_b"; + }; + }; + + /* c_i2c_master: dv28 dv29 */ + /* c_i2c_master_pin1: dv18 dv19 */ + c_i2c_master:c_i2c { + mux { + groups = "i2c_sda_c0", + "i2c_scl_c0"; + function = "i2c_c0"; + }; + }; + c_i2c_master_pin1:c_i2c_pin1{ + mux { + groups = "i2c_sda_c1", + "i2c_scl_c1"; + function = "i2c_c1"; + }; + }; + + d_i2c_master:d_i2c { + mux { + groups = "i2c_sda_d", + "i2c_scl_d"; + function = "i2c_d"; + }; + }; + + spicc_pulldown_z11z12z13: spicc_pulldown_z11z12z13 { + mux { + groups = "spi_sclk_0", + "spi_miso_0", + "spi_mosi_0"; + function = "spi"; + }; + }; + + spicc_pullup_z11z12z13: spicc_pullup_z11z12z13 { + mux { + groups = "spi_sclk_0", + "spi_miso_0", + "spi_mosi_0"; + function = "spi"; + }; + }; + + spicc_pulldown_x8x9x11: spicc_pulldown_x8x9x11 { + mux { + groups = "spi_sclk_1", + "spi_miso_1", + "spi_mosi_1"; + function = "spi"; + bias-pull-down; + }; + }; + + spicc_pullup_x8x9x11: spicc_pullup_x8x9x11 { + mux { + groups = "spi_sclk_1", + "spi_miso_1", + "spi_mosi_1"; + function = "spi"; + bias-pull-up; + }; + }; + + audio_i2s_pins:audio_i2s { + mux { + groups = "i2s_am_clk", + "i2s_ao_clk_out", + "i2s_lr_clk_out", + "i2sout_ch01"; + function = "i2s"; + }; + }; + + audio_spdif_pins:audio_spdif { + mux { + groups = "spdif_out"; + function = "spdif_out"; + }; + }; + + audio_spdif_in_pins:audio_spdif_in { + mux { + groups = "spdif_in"; + function = "spdif_in"; + }; + }; + + audio_spdif_in_1_pins:audio_spdif_in_1 { + mux { + groups = "spdif_in_1"; + function = "spdif_in_1"; + }; + }; + + audio_pcm_pins:audio_pcm { + mux { + groups = "pcm_out_a", + "pcm_in_a", + "pcm_fs_a", + "pcm_clk_a"; + function = "pcm_a"; + }; + }; + aml_dmic_pins:audio_dmic { + mux { + groups = "pdm_in", + "pdm_clk"; + function = "pdm"; + }; + }; + +}; /* end of pinctrl_periphs */ &periphs { rng { compatible = "amlogic,meson-rng"; reg = <0x0 0x0 0x0 0x4>; }; - - pinctrl_periphs: pinctrl@4b0 { - compatible = "amlogic,meson-gxl-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@4b0 { - reg = <0x0 0x004b0 0x0 0x28>, - <0x0 0x004e8 0x0 0x14>, - <0x0 0x00120 0x0 0x14>, - <0x0 0x00430 0x0 0x40>; - interrupts = <0 64 IRQ_TYPE_EDGE_RISING>, - <0 65 IRQ_TYPE_EDGE_RISING>, - <0 66 IRQ_TYPE_EDGE_RISING>, - <0 67 IRQ_TYPE_EDGE_RISING>, - <0 68 IRQ_TYPE_EDGE_RISING>, - <0 69 IRQ_TYPE_EDGE_RISING>, - <0 70 IRQ_TYPE_EDGE_RISING>, - <0 71 IRQ_TYPE_EDGE_RISING>; - reg-names = "mux", "pull", - "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - external_eth_pins:external_eth_pins { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_clk_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_rxd2", - "eth_rxd3", - "eth_rgmii_tx_clk", - "eth_tx_en", - "eth_txd0", - "eth_txd1", - "eth_txd2", - "eth_txd3"; - function = "eth"; - }; - }; - - a_uart_pins:a_uart { - mux { - groups = "uart_tx_a", - "uart_rx_a", - "uart_cts_a", - "uart_rts_a"; - function = "uart_a"; - }; - }; - - b_uart_pins:b_uart { - mux { - groups = "uart_tx_b", - "uart_rx_b", - "uart_cts_b", - "uart_rts_b"; - function = "uart_b"; - }; - }; - - c_uart_pins:c_uart { - mux { - groups = "uart_tx_c", - "uart_rx_c", - "uart_cts_c", - "uart_rts_c"; - function = "uart_c"; - }; - }; - - wifi_32k_pins:wifi_32k_pins { - mux { - groups ="pwm_e"; - function = "pwm_e"; - }; - }; - -/* - * sd_clk_cmd_pins:sd_clk_cmd_pins{ - * }; - * sd_all_pins:sd_all_pins { - * }; - * sd_1bit_pins:sd_1bit_pins{ - * }; - * sd_clk_cmd_uart_pins:sd_clk_cmd_uart_pins { - * }; - * sd_1bit_uart_pins:sd_1bit_uart_pins { - * }; - * sd_to_ao_jtag_pins:sd_to_ao_jtag_pins{ - * }; - */ - ao_to_sd_uart_pins:ao_to_sd_uart_pins { - mux { - groups = "uart_tx_ao_a_1", - "uart_rx_ao_a_1"; - function = "uart_ao_a_1"; - bias-pull-up; - input-enable; - }; - }; - - emmc_clk_cmd_pins:emmc_clk_cmd_pins { - mux { - groups = "emmc_cmd", - "emmc_clk"; - function = "emmc"; - input-enable; - bias-pull-up; - }; - }; - - - emmc_conf_pull_up:emmc_conf_pull_up { - mux { - groups = "emmc_nand_d07", - "emmc_clk", - "emmc_cmd"; - function = "emmc"; - input-enable; - bias-pull-up; - }; - }; - - emmc_conf_pull_done:emmc_conf_pull_done { - mux { - groups = "emmc_ds"; - function = "emmc"; - input-enable; - bias-pull-down; - }; - }; - - sd_clk_cmd_pins:sd_clk_cmd_pins{ - mux { - groups = "sdcard_cmd", - "sdcard_clk"; - function = "sdcard"; - input-enable; - bias-pull-up; - }; - }; - - sd_all_pins:sd_all_pins{ - mux { - groups = "sdcard_d0", - "sdcard_d1", - "sdcard_d2", - "sdcard_d3", - "sdcard_cmd", - "sdcard_clk"; - function = "sdcard"; - input-enable; - bias-pull-up; - }; - }; - - sdio_clk_cmd_pins:sdio_clk_cmd_pins { - mux { - groups = "sdio_clk", - "sdio_cmd"; - function = "sdio"; - input-enable; - bias-pull-up; - }; - }; - - sdio_all_pins:sdio_all_pins { - mux { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_clk", - "sdio_cmd"; - function = "sdio"; - input-enable; - bias-pull-up; - }; - }; - - nand_pulldown: nand_pulldown { - mux { - groups = "emmc_nand_d07", - "emmc_ds"; - function = "emmc"; - bias-pull-down; - }; - }; - - nand_pullup: nand_pullup { - mux { - groups = "emmc_clk", - "emmc_cmd"; - function = "emmc"; - bias-pull-up; - }; - }; - - all_nand_pins: all_nand_pins { - mux { - groups = "emmc_nand_d07", - "nand_ce0", - "nand_ce1", - "nand_rb0", - "nand_ale", - "nand_cle", - "nand_wen_clk", - "nand_ren_wr", - "nand_dqs"; - function = "nand"; - input-enable; - }; - }; - - nand_cs_pins: nand_cs { - mux { - groups = "nand_ce0", - "nand_ce1"; - function = "nand"; - }; - }; - - hdmitx_hpd: hdmitx_hpd { - mux { - groups = "hdmi_hpd"; - function = "hdmi_hpd"; - }; - }; - - hdmitx_ddc: hdmitx_ddc { - mux { - groups = "hdmi_sda", - "hdmi_scl"; - function = "hdmi_ddc"; - }; - }; - - a_i2c_master:a_i2c { - mux { - groups = "i2c_sda_a", - "i2c_scl_a"; - function = "i2c_a"; - }; - }; - - b_i2c_master:b_i2c { - mux { - groups = "i2c_sda_b", - "i2c_scl_b"; - function = "i2c_b"; - }; - }; - - /* c_i2c_master: dv28 dv29 */ - /* c_i2c_master_pin1: dv18 dv19 */ - c_i2c_master:c_i2c { - mux { - groups = "i2c_sda_c0", - "i2c_scl_c0"; - function = "i2c_c0"; - }; - }; - c_i2c_master_pin1:c_i2c_pin1{ - mux { - groups = "i2c_sda_c1", - "i2c_scl_c1"; - function = "i2c_c1"; - }; - }; - - d_i2c_master:d_i2c { - mux { - groups = "i2c_sda_d", - "i2c_scl_d"; - function = "i2c_d"; - }; - }; - - spicc_pulldown_z11z12z13: spicc_pulldown_z11z12z13 { - mux { - groups = "spi_sclk_0", - "spi_miso_0", - "spi_mosi_0"; - function = "spi"; - }; - }; - - spicc_pullup_z11z12z13: spicc_pullup_z11z12z13 { - mux { - groups = "spi_sclk_0", - "spi_miso_0", - "spi_mosi_0"; - function = "spi"; - }; - }; - - spicc_pulldown_x8x9x11: spicc_pulldown_x8x9x11 { - mux { - groups = "spi_sclk_1", - "spi_miso_1", - "spi_mosi_1"; - function = "spi"; - bias-pull-down; - }; - }; - - spicc_pullup_x8x9x11: spicc_pullup_x8x9x11 { - mux { - groups = "spi_sclk_1", - "spi_miso_1", - "spi_mosi_1"; - function = "spi"; - bias-pull-up; - }; - }; - - audio_i2s_pins:audio_i2s { - mux { - groups = "i2s_am_clk", - "i2s_ao_clk_out", - "i2s_lr_clk_out", - "i2sout_ch01"; - function = "i2s"; - }; - }; - - audio_spdif_pins:audio_spdif { - mux { - groups = "spdif_out"; - function = "spdif_out"; - }; - }; - - audio_spdif_in_pins:audio_spdif_in { - mux { - groups = "spdif_in"; - function = "spdif_in"; - }; - }; - - audio_spdif_in_1_pins:audio_spdif_in_1 { - mux { - groups = "spdif_in_1"; - function = "spdif_in_1"; - }; - }; - - audio_pcm_pins:audio_pcm { - mux { - groups = "pcm_out_a", - "pcm_in_a", - "pcm_fs_a", - "pcm_clk_a"; - function = "pcm_a"; - }; - }; - aml_dmic_pins:audio_dmic { - mux { - groups = "pdm_in", - "pdm_clk"; - function = "pdm"; - }; - }; - - }; /* end of pinctrl_periphs */ -}; /* end of periphs */ +}; &cbus{ reset: reset-controller@4404 { diff --git a/arch/arm64/boot/dts/amlogic/mesongxm.dtsi b/arch/arm64/boot/dts/amlogic/mesongxm.dtsi index 171a6478bde7..cc3af4e4d25a 100644 --- a/arch/arm64/boot/dts/amlogic/mesongxm.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesongxm.dtsi @@ -441,80 +441,130 @@ }; i2c_ao: i2c@c8100500{ /*I2C-AO*/ - compatible = "amlogic, meson-i2c"; - dev_name = "i2c-AO"; - status = "disabled"; - reg = <0x0 0xc8100500 0x0 0x1d>; - device_id = <0>; - pinctrl-names="default"; - pinctrl-0=<&ao_i2c_master>; - #address-cells = <1>; - #size-cells = <0>; - use_pio = <0>; - master_i2c_speed = <300000>; - clocks = <&clkc CLKID_AO_I2C>; - clock-names = "clk_i2c"; + compatible = "amlogic, meson-i2c"; + dev_name = "i2c-AO"; + status = "disabled"; + reg = <0x0 0xc8100500 0x0 0x1d>; + device_id = <0>; + pinctrl-names="default"; + pinctrl-0=<&ao_i2c_master>; + #address-cells = <1>; + #size-cells = <0>; + use_pio = <0>; + master_i2c_speed = <300000>; + clocks = <&clkc CLKID_AO_I2C>; + clock-names = "clk_i2c"; + }; + i2c_a: i2c@c1108500{ /*I2C-A*/ + compatible = "amlogic, meson-i2c"; + dev_name = "i2c-A"; + status = "disabled"; + reg = <0x0 0xc1108500 0x0 0x20>; + device_id = <1>; + pinctrl-names="default"; + pinctrl-0=<&a_i2c_master>; + #address-cells = <1>; + #size-cells = <0>; + use_pio = <0>; + master_i2c_speed = <300000>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + i2c_b: i2c@c11087c0{ /*I2C-B*/ + compatible = "amlogic, meson-i2c"; + dev_name = "i2c-B"; + status = "disabled"; + reg = <0x0 0xc11087c0 0x0 0x20>; + device_id = <2>; + pinctrl-names="default"; + pinctrl-0=<&b_i2c_master>; + #address-cells = <1>; + #size-cells = <0>; + use_pio = <0>; + master_i2c_speed = <300000>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + i2c_c: i2c@c11087e0{ /*I2C-C*/ + compatible = "amlogic, meson-i2c"; + dev_name = "i2c-C"; + status = "disabled"; + reg = <0x0 0xc11087e0 0x0 0x20>; + device_id = <3>; + pinctrl-names="default"; + pinctrl-0=<&c_i2c_master>; + #address-cells = <1>; + #size-cells = <0>; + use_pio = <0>; + master_i2c_speed = <300000>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + i2c_d: i2c@c1108d20{ /*I2C-D*/ + compatible = "amlogic, meson-i2c"; + dev_name = "i2c-D"; + status = "disabled"; + reg = <0x0 0xc1108d20 0x0 0x20>; + device_id = <4>; + pinctrl-names="default"; + pinctrl-0=<&d_i2c_master>; + #address-cells = <1>; + #size-cells = <0>; + use_pio = <0>; + master_i2c_speed = <300000>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + + pinctrl_aobus: pinctrl@14 { + compatible = "amlogic,meson-gxl-aobus-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio_ao: bank@14 { + reg = <0x0 0xc8100014 0x0 0x8>, + <0x0 0xc810002c 0x0 0x4>, + <0x0 0xc8100024 0x0 0x8>, + <0x0 0xc8100084 0x0 0x4>; + interrupts = <0 200 IRQ_TYPE_EDGE_RISING>, + <0 201 IRQ_TYPE_EDGE_RISING>; + reg-names = "mux", "pull", "gpio", "irq"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; - i2c_a: i2c@c1108500{ /*I2C-A*/ - compatible = "amlogic, meson-i2c"; - dev_name = "i2c-A"; - status = "disabled"; - reg = <0x0 0xc1108500 0x0 0x20>; - device_id = <1>; - pinctrl-names="default"; - pinctrl-0=<&a_i2c_master>; - #address-cells = <1>; - #size-cells = <0>; - use_pio = <0>; - master_i2c_speed = <300000>; - clocks = <&clkc CLKID_I2C>; - clock-names = "clk_i2c"; - }; - i2c_b: i2c@c11087c0{ /*I2C-B*/ - compatible = "amlogic, meson-i2c"; - dev_name = "i2c-B"; - status = "disabled"; - reg = <0x0 0xc11087c0 0x0 0x20>; - device_id = <2>; - pinctrl-names="default"; - pinctrl-0=<&b_i2c_master>; - #address-cells = <1>; - #size-cells = <0>; - use_pio = <0>; - master_i2c_speed = <300000>; - clocks = <&clkc CLKID_I2C>; - clock-names = "clk_i2c"; - }; - i2c_c: i2c@c11087e0{ /*I2C-C*/ - compatible = "amlogic, meson-i2c"; - dev_name = "i2c-C"; - status = "disabled"; - reg = <0x0 0xc11087e0 0x0 0x20>; - device_id = <3>; - pinctrl-names="default"; - pinctrl-0=<&c_i2c_master>; - #address-cells = <1>; - #size-cells = <0>; - use_pio = <0>; - master_i2c_speed = <300000>; - clocks = <&clkc CLKID_I2C>; - clock-names = "clk_i2c"; - }; - i2c_d: i2c@c1108d20{ /*I2C-D*/ - compatible = "amlogic, meson-i2c"; - dev_name = "i2c-D"; - status = "disabled"; - reg = <0x0 0xc1108d20 0x0 0x20>; - device_id = <4>; - pinctrl-names="default"; - pinctrl-0=<&d_i2c_master>; - #address-cells = <1>; - #size-cells = <0>; - use_pio = <0>; - master_i2c_speed = <300000>; - clocks = <&clkc CLKID_I2C>; - clock-names = "clk_i2c"; + }; + + pinctrl_periphs: pinctrl@4b0 { + compatible = "amlogic,meson-gxl-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@4b0 { + reg = <0x0 0xc88344b0 0x0 0x28>, + <0x0 0xc88344e8 0x0 0x14>, + <0x0 0xc8834120 0x0 0x14>, + <0x0 0xc8834430 0x0 0x40>, + <0x0 0xc1109880 0x0 0x10>; + interrupts = <0 64 IRQ_TYPE_EDGE_RISING>, + <0 65 IRQ_TYPE_EDGE_RISING>, + <0 66 IRQ_TYPE_EDGE_RISING>, + <0 67 IRQ_TYPE_EDGE_RISING>, + <0 68 IRQ_TYPE_EDGE_RISING>, + <0 69 IRQ_TYPE_EDGE_RISING>, + <0 70 IRQ_TYPE_EDGE_RISING>, + <0 71 IRQ_TYPE_EDGE_RISING>; + reg-names = "mux", "pull", + "pull-enable", "gpio", "irq"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; }; + }; soc { compatible = "simple-bus"; @@ -538,8 +588,7 @@ aobus: aobus@c8100000 { compatible = "simple-bus"; - reg = <0x0 0xc8100000 0x0 0x100000>, - <0x0 0xc8100084 0x0 0x4>; + reg = <0x0 0xc8100000 0x0 0x100000>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; @@ -551,8 +600,7 @@ periphs: periphs@c8834000 { compatible = "simple-bus"; - reg = <0x0 0xc8834000 0x0 0x2000>, - <0x0 0xc1109880 0x0 0x10>; + reg = <0x0 0xc8834000 0x0 0x2000>; #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; @@ -582,481 +630,435 @@ }; /* end of soc */ }; /* end of root */ -&aobus { - pinctrl_aobus: pinctrl@14 { - compatible = "amlogic,meson-gxl-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x00014 0x0 0x8>, - <0x0 0x0002c 0x0 0x4>, - <0x0 0x00024 0x0 0x8>; - interrupts = <0 200 IRQ_TYPE_EDGE_RISING>, - <0 201 IRQ_TYPE_EDGE_RISING>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; +&pinctrl_aobus { + remote_pins:remote_pin { + mux { + groups = "remote_input"; + function = "remote"; }; + }; - remote_pins:remote_pin { - mux { - groups = "remote_input"; - function = "remote"; - }; - }; - sd_to_ao_uart_pins:sd_to_ao_uart_pins { - mux { - groups = "uart_tx_ao_a_0", - "uart_rx_ao_a_0"; - function = "uart_ao"; - bias-pull-up; - input-enable; - }; - }; - - ao_uart_pins:ao_uart { - mux { - groups = "uart_tx_ao_a_0", + sd_to_ao_uart_pins:sd_to_ao_uart_pins { + mux { + groups = "uart_tx_ao_a_0", "uart_rx_ao_a_0"; - function = "uart_ao"; + function = "uart_ao"; + bias-pull-up; + input-enable; + }; + }; + + ao_uart_pins:ao_uart { + mux { + groups = "uart_tx_ao_a_0", + "uart_rx_ao_a_0"; + function = "uart_ao"; + }; + }; + + ao_b_uart_pins:ao_b_uart { + mux { + groups = "uart_tx_ao_b_0", + "uart_rx_ao_b_0"; + function = "uart_ao_b"; + }; + }; + ao_i2c_master:ao_i2c{ + mux { + groups = "i2c_sda_ao", + "i2c_sck_ao"; + function = "i2c_ao"; + }; + }; + + hdmitx_aocec: hdmitx_aocec { + mux { + groups = "ao_cec"; + function = "ao_cec"; + }; + }; + + hdmitx_eecec: hdmitx_eecec { + mux { + groups = "ee_cec"; + function = "ee_cec"; + }; + }; +}; /* end of pinctrl_aobus*/ + +&pinctrl_periphs { + external_eth_pins:external_eth_pins { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_clk_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_rxd2", + "eth_rxd3", + "eth_rgmii_tx_clk", + "eth_tx_en", + "eth_txd0", + "eth_txd1", + "eth_txd2", + "eth_txd3"; + function = "eth"; + }; + }; + + jtag_apao_pins:jtag_apao_pin { + mux { + groups = "jtag_tdi_0", + "jtag_tdo_0", + "jtag_clk_0", + "jtag_tms_0"; + function = "jtag"; + }; + }; + + jtag_apee_pins:jtag_apee_pin { + mux { + groups ="jtag_tdi_1", + "jtag_tdo_1", + "jtag_clk_1", + "jtag_tms_1"; + function = "jtag"; + }; + }; + + a_uart_pins:a_uart { + mux { + groups = "uart_tx_a", + "uart_rx_a", + "uart_cts_a", + "uart_rts_a"; + function = "uart_a"; + }; + }; + + b_uart_pins:b_uart { + mux { + groups = "uart_tx_b", + "uart_rx_b", + "uart_cts_b", + "uart_rts_b"; + function = "uart_b"; + }; + }; + + c_uart_pins:c_uart { + mux { + groups = "uart_tx_c", + "uart_rx_c", + "uart_cts_c", + "uart_rts_c"; + function = "uart_c"; + }; + }; + + wifi_32k_pins:wifi_32k_pins { + mux { + groups ="pwm_e"; + function = "pwm_e"; + }; + }; + +/* +* sd_clk_cmd_pins:sd_clk_cmd_pins{ +* }; +* sd_all_pins:sd_all_pins { +* }; +* sd_1bit_pins:sd_1bit_pins{ +* }; +* sd_clk_cmd_uart_pins:sd_clk_cmd_uart_pins { +* }; +* sd_1bit_uart_pins:sd_1bit_uart_pins { +* }; +* sd_to_ao_jtag_pins:sd_to_ao_jtag_pins{ +* }; +*/ + ao_to_sd_uart_pins:ao_to_sd_uart_pins { + mux { + groups = "uart_tx_ao_a_1", + "uart_rx_ao_a_1"; + function = "uart_ao_a_1"; + bias-pull-up; + input-enable; }; }; - ao_b_uart_pins:ao_b_uart { - mux { - groups = "uart_tx_ao_b_0", - "uart_rx_ao_b_0"; - function = "uart_ao_b"; - }; - }; - ao_i2c_master:ao_i2c{ - mux { - groups = "i2c_sda_ao", - "i2c_sck_ao"; - function = "i2c_ao"; - }; + emmc_clk_cmd_pins:emmc_clk_cmd_pins { + mux { + groups = "emmc_cmd", + "emmc_clk"; + function = "emmc"; + input-enable; + bias-pull-up; }; + }; - hdmitx_aocec: hdmitx_aocec { - mux { - groups = "ao_cec"; - function = "ao_cec"; - }; - }; - hdmitx_eecec: hdmitx_eecec { - mux { - groups = "ee_cec"; - function = "ee_cec"; - }; + emmc_conf_pull_up:emmc_conf_pull_up { + mux { + groups = "emmc_nand_d07", + "emmc_clk", + "emmc_cmd"; + function = "emmc"; + input-enable; + bias-pull-up; }; - }; /* end of pinctrl_aobus*/ + }; -}; /* end of aobus*/ + emmc_conf_pull_done:emmc_conf_pull_done { + mux { + groups = "emmc_ds"; + function = "emmc"; + input-enable; + bias-pull-down; + }; + }; + + sd_clk_cmd_pins:sd_clk_cmd_pins{ + mux { + groups = "sdcard_cmd", + "sdcard_clk"; + function = "sdcard"; + input-enable; + bias-pull-up; + }; + }; + + sd_all_pins:sd_all_pins{ + mux { + groups = "sdcard_d0", + "sdcard_d1", + "sdcard_d2", + "sdcard_d3", + "sdcard_cmd", + "sdcard_clk"; + function = "sdcard"; + input-enable; + bias-pull-up; + }; + }; + + sdio_clk_cmd_pins:sdio_clk_cmd_pins { + mux { + groups = "sdio_clk", + "sdio_cmd"; + function = "sdio"; + input-enable; + bias-pull-up; + }; + }; + + sdio_all_pins:sdio_all_pins { + mux { + groups = "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", + "sdio_clk", + "sdio_cmd"; + function = "sdio"; + input-enable; + bias-pull-up; + }; + }; + + nand_pulldown: nand_pulldown { + mux { + groups = "emmc_nand_d07", + "emmc_ds"; + function = "emmc"; + bias-pull-down; + }; + }; + + nand_pullup: nand_pullup { + mux { + groups = "emmc_clk", + "emmc_cmd"; + function = "emmc"; + bias-pull-up; + }; + }; + + all_nand_pins: all_nand_pins { + mux { + groups = "emmc_nand_d07", + "nand_ce0", + "nand_ce1", + "nand_rb0", + "nand_ale", + "nand_cle", + "nand_wen_clk", + "nand_ren_wr", + "nand_dqs"; + function = "nand"; + input-enable; + }; + }; + + nand_cs_pins: nand_cs { + mux { + groups = "nand_ce0", + "nand_ce1"; + function = "nand"; + }; + }; + + hdmitx_hpd: hdmitx_hpd { + mux { + groups = "hdmi_hpd"; + function = "hdmi_hpd"; + }; + }; + + hdmitx_ddc: hdmitx_ddc { + mux { + groups = "hdmi_sda", + "hdmi_scl"; + function = "hdmi_ddc"; + }; + }; + + a_i2c_master:a_i2c { + mux { + groups = "i2c_sda_a", + "i2c_scl_a"; + function = "i2c_a"; + }; + }; + + b_i2c_master:b_i2c { + mux { + groups = "i2c_sda_b", + "i2c_scl_b"; + function = "i2c_b"; + }; + }; + + /* c_i2c_master: dv28 dv29 */ + /* c_i2c_master_pin1: dv18 dv19 */ + c_i2c_master:c_i2c { + mux { + groups = "i2c_sda_c0", + "i2c_scl_c0"; + function = "i2c_c0"; + }; + }; + c_i2c_master_pin1:c_i2c_pin1{ + mux { + groups = "i2c_sda_c1", + "i2c_scl_c1"; + function = "i2c_c1"; + }; + }; + + d_i2c_master:d_i2c { + mux { + groups = "i2c_sda_d", + "i2c_scl_d"; + function = "i2c_d"; + }; + }; + + spicc_pulldown_z11z12z13: spicc_pulldown_z11z12z13 { + mux { + groups = "spi_sclk_0", + "spi_miso_0", + "spi_mosi_0"; + function = "spi"; + }; + }; + + spicc_pullup_z11z12z13: spicc_pullup_z11z12z13 { + mux { + groups = "spi_sclk_0", + "spi_miso_0", + "spi_mosi_0"; + function = "spi"; + }; + }; + + spicc_pulldown_x8x9x11: spicc_pulldown_x8x9x11 { + mux { + groups = "spi_sclk_1", + "spi_miso_1", + "spi_mosi_1"; + function = "spi"; + bias-pull-down; + }; + }; + + spicc_pullup_x8x9x11: spicc_pullup_x8x9x11 { + mux { + groups = "spi_sclk_1", + "spi_miso_1", + "spi_mosi_1"; + function = "spi"; + bias-pull-up; + }; + }; + + audio_i2s_pins:audio_i2s { + mux { + groups = "i2s_am_clk", + "i2s_ao_clk_out", + "i2s_lr_clk_out", + "i2sout_ch01"; + function = "i2s"; + }; + }; + + audio_spdif_pins:audio_spdif { + mux { + groups = "spdif_out"; + function = "spdif_out"; + }; + }; + + audio_spdif_in_pins:audio_spdif_in { + mux { + groups = "spdif_in"; + function = "spdif_in"; + }; + }; + + audio_spdif_in_1_pins:audio_spdif_in_1 { + mux { + groups = "spdif_in_1"; + function = "spdif_in_1"; + }; + }; + + audio_pcm_pins:audio_pcm { + mux { + groups = "pcm_out_a", + "pcm_in_a", + "pcm_fs_a", + "pcm_clk_a"; + function = "pcm_a"; + }; + }; + aml_dmic_pins:audio_dmic { + mux { + groups = "pdm_in", + "pdm_clk"; + function = "pdm"; + }; + }; + +}; /* end of pinctrl_periphs */ &periphs { rng { compatible = "amlogic,meson-rng"; reg = <0x0 0x0 0x0 0x4>; }; - - pinctrl_periphs: pinctrl@4b0 { - compatible = "amlogic,meson-gxl-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@4b0 { - reg = <0x0 0x004b0 0x0 0x28>, - <0x0 0x004e8 0x0 0x14>, - <0x0 0x00120 0x0 0x14>, - <0x0 0x00430 0x0 0x40>; - interrupts = <0 64 IRQ_TYPE_EDGE_RISING>, - <0 65 IRQ_TYPE_EDGE_RISING>, - <0 66 IRQ_TYPE_EDGE_RISING>, - <0 67 IRQ_TYPE_EDGE_RISING>, - <0 68 IRQ_TYPE_EDGE_RISING>, - <0 69 IRQ_TYPE_EDGE_RISING>, - <0 70 IRQ_TYPE_EDGE_RISING>, - <0 71 IRQ_TYPE_EDGE_RISING>; - reg-names = "mux", "pull", - "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - external_eth_pins:external_eth_pins { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_clk_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_rxd2", - "eth_rxd3", - "eth_rgmii_tx_clk", - "eth_tx_en", - "eth_txd0", - "eth_txd1", - "eth_txd2", - "eth_txd3"; - function = "eth"; - }; - }; - - jtag_apao_pins:jtag_apao_pin { - mux { - groups = "jtag_tdi_0", - "jtag_tdo_0", - "jtag_clk_0", - "jtag_tms_0"; - function = "jtag"; - }; - }; - - jtag_apee_pins:jtag_apee_pin { - mux { - groups ="jtag_tdi_1", - "jtag_tdo_1", - "jtag_clk_1", - "jtag_tms_1"; - function = "jtag"; - }; - }; - - a_uart_pins:a_uart { - mux { - groups = "uart_tx_a", - "uart_rx_a", - "uart_cts_a", - "uart_rts_a"; - function = "uart_a"; - }; - }; - - b_uart_pins:b_uart { - mux { - groups = "uart_tx_b", - "uart_rx_b", - "uart_cts_b", - "uart_rts_b"; - function = "uart_b"; - }; - }; - - c_uart_pins:c_uart { - mux { - groups = "uart_tx_c", - "uart_rx_c", - "uart_cts_c", - "uart_rts_c"; - function = "uart_c"; - }; - }; - - wifi_32k_pins:wifi_32k_pins { - mux { - groups ="pwm_e"; - function = "pwm_e"; - }; - }; - -/* - * sd_clk_cmd_pins:sd_clk_cmd_pins{ - * }; - * sd_all_pins:sd_all_pins { - * }; - * sd_1bit_pins:sd_1bit_pins{ - * }; - * sd_clk_cmd_uart_pins:sd_clk_cmd_uart_pins { - * }; - * sd_1bit_uart_pins:sd_1bit_uart_pins { - * }; - * sd_to_ao_jtag_pins:sd_to_ao_jtag_pins{ - * }; - */ - ao_to_sd_uart_pins:ao_to_sd_uart_pins { - mux { - groups = "uart_tx_ao_a_1", - "uart_rx_ao_a_1"; - function = "uart_ao_a_1"; - bias-pull-up; - input-enable; - }; - }; - - emmc_clk_cmd_pins:emmc_clk_cmd_pins { - mux { - groups = "emmc_cmd", - "emmc_clk"; - function = "emmc"; - input-enable; - bias-pull-up; - }; - }; - - - emmc_conf_pull_up:emmc_conf_pull_up { - mux { - groups = "emmc_nand_d07", - "emmc_clk", - "emmc_cmd"; - function = "emmc"; - input-enable; - bias-pull-up; - }; - }; - - emmc_conf_pull_done:emmc_conf_pull_done { - mux { - groups = "emmc_ds"; - function = "emmc"; - input-enable; - bias-pull-down; - }; - }; - - sd_clk_cmd_pins:sd_clk_cmd_pins{ - mux { - groups = "sdcard_cmd", - "sdcard_clk"; - function = "sdcard"; - input-enable; - bias-pull-up; - }; - }; - - sd_all_pins:sd_all_pins{ - mux { - groups = "sdcard_d0", - "sdcard_d1", - "sdcard_d2", - "sdcard_d3", - "sdcard_cmd", - "sdcard_clk"; - function = "sdcard"; - input-enable; - bias-pull-up; - }; - }; - - sdio_clk_cmd_pins:sdio_clk_cmd_pins { - mux { - groups = "sdio_clk", - "sdio_cmd"; - function = "sdio"; - input-enable; - bias-pull-up; - }; - }; - - sdio_all_pins:sdio_all_pins { - mux { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_clk", - "sdio_cmd"; - function = "sdio"; - input-enable; - bias-pull-up; - }; - }; - - nand_pulldown: nand_pulldown { - mux { - groups = "emmc_nand_d07", - "emmc_ds"; - function = "emmc"; - bias-pull-down; - }; - }; - - nand_pullup: nand_pullup { - mux { - groups = "emmc_clk", - "emmc_cmd"; - function = "emmc"; - bias-pull-up; - }; - }; - - all_nand_pins: all_nand_pins { - mux { - groups = "emmc_nand_d07", - "nand_ce0", - "nand_ce1", - "nand_rb0", - "nand_ale", - "nand_cle", - "nand_wen_clk", - "nand_ren_wr", - "nand_dqs"; - function = "nand"; - input-enable; - }; - }; - - nand_cs_pins: nand_cs { - mux { - groups = "nand_ce0", - "nand_ce1"; - function = "nand"; - }; - }; - - hdmitx_hpd: hdmitx_hpd { - mux { - groups = "hdmi_hpd"; - function = "hdmi_hpd"; - }; - }; - - hdmitx_ddc: hdmitx_ddc { - mux { - groups = "hdmi_sda", - "hdmi_scl"; - function = "hdmi_ddc"; - }; - }; - - a_i2c_master:a_i2c { - mux { - groups = "i2c_sda_a", - "i2c_scl_a"; - function = "i2c_a"; - }; - }; - - b_i2c_master:b_i2c { - mux { - groups = "i2c_sda_b", - "i2c_scl_b"; - function = "i2c_b"; - }; - }; - - /* c_i2c_master: dv28 dv29 */ - /* c_i2c_master_pin1: dv18 dv19 */ - c_i2c_master:c_i2c { - mux { - groups = "i2c_sda_c0", - "i2c_scl_c0"; - function = "i2c_c0"; - }; - }; - c_i2c_master_pin1:c_i2c_pin1{ - mux { - groups = "i2c_sda_c1", - "i2c_scl_c1"; - function = "i2c_c1"; - }; - }; - - d_i2c_master:d_i2c { - mux { - groups = "i2c_sda_d", - "i2c_scl_d"; - function = "i2c_d"; - }; - }; - - spicc_pulldown_z11z12z13: spicc_pulldown_z11z12z13 { - mux { - groups = "spi_sclk_0", - "spi_miso_0", - "spi_mosi_0"; - function = "spi"; - }; - }; - - spicc_pullup_z11z12z13: spicc_pullup_z11z12z13 { - mux { - groups = "spi_sclk_0", - "spi_miso_0", - "spi_mosi_0"; - function = "spi"; - }; - }; - - spicc_pulldown_x8x9x11: spicc_pulldown_x8x9x11 { - mux { - groups = "spi_sclk_1", - "spi_miso_1", - "spi_mosi_1"; - function = "spi"; - bias-pull-down; - }; - }; - - spicc_pullup_x8x9x11: spicc_pullup_x8x9x11 { - mux { - groups = "spi_sclk_1", - "spi_miso_1", - "spi_mosi_1"; - function = "spi"; - bias-pull-up; - }; - }; - - audio_i2s_pins:audio_i2s { - mux { - groups = "i2s_am_clk", - "i2s_ao_clk_out", - "i2s_lr_clk_out", - "i2sout_ch01"; - function = "i2s"; - }; - }; - - audio_spdif_pins:audio_spdif { - mux { - groups = "spdif_out"; - function = "spdif_out"; - }; - }; - - audio_spdif_in_pins:audio_spdif_in { - mux { - groups = "spdif_in"; - function = "spdif_in"; - }; - }; - - audio_spdif_in_1_pins:audio_spdif_in_1 { - mux { - groups = "spdif_in_1"; - function = "spdif_in_1"; - }; - }; - - audio_pcm_pins:audio_pcm { - mux { - groups = "pcm_out_a", - "pcm_in_a", - "pcm_fs_a", - "pcm_clk_a"; - function = "pcm_a"; - }; - }; - aml_dmic_pins:audio_dmic { - mux { - groups = "pdm_in", - "pdm_clk"; - function = "pdm"; - }; - }; - - }; /* end of pinctrl_periphs */ -}; /* end of periphs */ +}; &cbus{ reset: reset-controller@4404 { diff --git a/drivers/amlogic/pinctrl/Makefile b/drivers/amlogic/pinctrl/Makefile index dbcd8aef771d..479d497102d2 100644 --- a/drivers/amlogic/pinctrl/Makefile +++ b/drivers/amlogic/pinctrl/Makefile @@ -1,4 +1,4 @@ # #Makefile for the gpio dirver # -obj-$(CONFIG_AMLOGIC_PINCTRL) += pinctrl-meson.o pinctrl_gxl.o pinctrl-meson8b.o +obj-$(CONFIG_AMLOGIC_PINCTRL) += pinctrl-meson.o pinctrl_gxl.o pinctrl-meson8b.o pinctrl-mesonaxg.o diff --git a/drivers/amlogic/pinctrl/pinctrl-meson.c b/drivers/amlogic/pinctrl/pinctrl-meson.c index 3d27abeea6e0..88bc5596c187 100644 --- a/drivers/amlogic/pinctrl/pinctrl-meson.c +++ b/drivers/amlogic/pinctrl/pinctrl-meson.c @@ -65,6 +65,7 @@ #include #include #include +#include #include "../../pinctrl/core.h" #include "../../pinctrl/pinctrl-utils.h" #include "pinctrl-meson.h" @@ -217,7 +218,7 @@ static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc, } } -static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, +static int meson_pmx_v1_set_mux(struct pinctrl_dev *pcdev, unsigned int func_num, unsigned int group_num) { struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); @@ -282,14 +283,79 @@ static int meson_pmx_get_groups(struct pinctrl_dev *pcdev, return 0; } -static const struct pinmux_ops meson_pmx_ops = { - .set_mux = meson_pmx_set_mux, +static const struct pinmux_ops meson_pmx_v1_ops = { + .set_mux = meson_pmx_v1_set_mux, .get_functions_count = meson_pmx_get_funcs_count, .get_function_name = meson_pmx_get_func_name, .get_function_groups = meson_pmx_get_groups, .gpio_request_enable = meson_pmx_request_gpio, }; +static struct meson_desc_function * +meson_pinctrl_desc_find_function_by_name(struct meson_pinctrl *pc, + const char *pin_name, + const char *func_name) +{ + int i; + const struct meson_desc_pin *pin; + struct meson_desc_function *func; + + for (i = 0; i < pc->data->num_pins; i++) { + pin = pc->data->meson_pins + i; + if (!strcmp(pin->pin.name, pin_name)) { + func = pin->functions; + while (func->name) { + if (!strcmp(func->name, func_name)) + return func; + + func++; + } + } + } + + return NULL; +} + +static int meson_pmx_v2_set_mux(struct pinctrl_dev *pcdev, + unsigned int func_num, unsigned int group_num) +{ + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); + struct meson_pmx_func *func = &pc->data->funcs[func_num]; + struct meson_pmx_group *group = &pc->data->groups[group_num]; + struct meson_domain *domain = pc->domain; + struct meson_desc_function *desc; + int ret = 0; + + dev_dbg(pc->dev, "enable function %s, group %s\n", func->name, + group->name); + + desc = meson_pinctrl_desc_find_function_by_name(pc, + group->name, + func->name); + if (!desc) + return -EINVAL; + + dev_dbg(pc->dev, + "group->reg = 0x%x; group->bit = %d; desc->muxval = %d\n", + group->reg, group->bit, desc->muxval); + + /* Function 0 (GPIO) doesn't need any additional setting */ + if (func_num && (group->bit != 0xff)) { + ret = regmap_update_bits(domain->reg_mux, group->reg * 4, + MESON_MUX_V2_MASK(group->bit), + MESON_MUX_V2_VAL(desc->muxval, group->bit)); + } + + return ret; +} + +static const struct pinmux_ops meson_pmx_v2_ops = { + .set_mux = meson_pmx_v2_set_mux, + .get_functions_count = meson_pmx_get_funcs_count, + .get_function_name = meson_pmx_get_func_name, + .get_function_groups = meson_pmx_get_groups, +}; + static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, unsigned long *configs, unsigned int num_configs) { @@ -679,11 +745,7 @@ static int meson_ee_gpio_irq_type(struct irq_data *irqd, unsigned int type) trigger_type[type_cnt] << cnt); /*the gpio hwirq eqaul to gpio offset in gpio chip*/ -#ifdef CONFIG_ARM64 pin = domain->data->pin_base + irqd->hwirq; -#else /*for m8b platform*/ - pin = domain->data->pin_base + irqd->hwirq + 14; -#endif /*set pin select register*/ start_bit = (cnt & 3) << 3; @@ -793,11 +855,8 @@ static int meson_ao_gpio_irq_type(struct irq_data *irqd, unsigned int type) trigger_type[type_cnt] << cnt); /*the gpio hwirq eqaul to gpio offset in gpio chip*/ -#ifdef CONFIG_ARM64 pin = domain->data->pin_base + irqd->hwirq; -#else /*for m8b platform*/ - pin = irqd->hwirq; -#endif + /*set pin select register*/ start_bit = cnt << 2; regmap_update_bits(domain->reg_irq, 0, @@ -856,25 +915,41 @@ static struct irq_chip meson_ao_gpio_irq_chip = { }; struct meson_pinctrl_private meson_gxl_periphs = { + .pinmux_type = PINMUX_V1, .pinctrl_data = &meson_gxl_periphs_pinctrl_data, .irq_chip = &meson_ee_gpio_irq_chip, }; struct meson_pinctrl_private meson_gxl_aobus = { + .pinmux_type = PINMUX_V1, .pinctrl_data = &meson_gxl_aobus_pinctrl_data, .irq_chip = &meson_ao_gpio_irq_chip, }; struct meson_pinctrl_private meson_m8b_cbus = { + .pinmux_type = PINMUX_V1, .pinctrl_data = &meson8b_cbus_pinctrl_data, .irq_chip = &meson_ee_gpio_irq_chip, }; struct meson_pinctrl_private meson_m8b_aobus = { + .pinmux_type = PINMUX_V1, .pinctrl_data = &meson8b_aobus_pinctrl_data, .irq_chip = &meson_ao_gpio_irq_chip, }; +struct meson_pinctrl_private meson_axg_periphs = { + .pinmux_type = PINMUX_V2, + .pinctrl_data = &meson_axg_periphs_pinctrl_data, + .irq_chip = &meson_ee_gpio_irq_chip, +}; + +struct meson_pinctrl_private meson_axg_aobus = { + .pinmux_type = PINMUX_V2, + .pinctrl_data = &meson_axg_aobus_pinctrl_data, + .irq_chip = &meson_ao_gpio_irq_chip, +}; + static const struct of_device_id meson_pinctrl_dt_match[] = { { .compatible = "amlogic,meson-gxl-periphs-pinctrl", @@ -892,6 +967,14 @@ static const struct of_device_id meson_pinctrl_dt_match[] = { .compatible = "amlogic,meson8b-aobus-pinctrl", .data = &meson_m8b_aobus, }, + { + .compatible = "amlogic,meson-axg-periphs-pinctrl", + .data = &meson_axg_periphs, + }, + { + .compatible = "amlogic,meson-axg-aobus-pinctrl", + .data = &meson_axg_aobus, + }, { }, }; @@ -972,33 +1055,6 @@ static struct regmap *meson_map_resource(struct meson_pinctrl *pc, return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); } -#ifdef CONFIG_ARM64 -static struct regmap *meson_irq_map_resource(struct meson_pinctrl *pc, - struct device_node *node, char *name) -{ - struct platform_device *pdev; - struct resource *res; - void __iomem *base; - pdev = of_find_device_by_node(of_get_parent(node)); - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (IS_ERR(res)) { - dev_err(&pdev->dev, "reg: cannot obtain I/O memory region"); - return ERR_CAST(res); - } - base = devm_ioremap_resource(pc->dev, res); - if (IS_ERR(base)) - return ERR_CAST(base); - - meson_regmap_config.max_register = resource_size(res) - 4; - meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL, - "%s-%s", node->name, - name); - if (!meson_regmap_config.name) - return ERR_PTR(-ENOMEM); - - return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); -} -#endif static int meson_irq_parse_and_map(struct meson_pinctrl *pc, struct device_node *node) { @@ -1049,14 +1105,6 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, domain = pc->domain; domain->data = pc->data->domain_data; -#ifdef CONFIG_ARM64 - domain->reg_irq = meson_irq_map_resource(pc, node, "irq"); - if (IS_ERR(domain->reg_irq)) { - dev_err(pc->dev, "gpio irq registers not found\n"); - return PTR_ERR(domain->reg_irq); - } -#endif - for_each_child_of_node(node, np) { if (!of_find_property(np, "gpio-controller", NULL)) continue; @@ -1086,13 +1134,12 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, return PTR_ERR(domain->reg_gpio); } -#ifndef CONFIG_ARM64 /*for m8b platform*/ domain->reg_irq = meson_map_resource(pc, np, "irq"); if (IS_ERR(domain->reg_irq)) { dev_err(pc->dev, "gpio irq registers not found\n"); return PTR_ERR(domain->reg_irq); } -#endif + meson_irq_parse_and_map(pc, np); break; @@ -1157,13 +1204,144 @@ static int meson_irq_setup(struct meson_pinctrl *pc, struct irq_chip *irq_chip) } +static int meson_pinctrl_add_function(struct meson_pinctrl *pc, + const char *name) +{ + struct meson_pmx_func *func = pc->data->funcs; + + while (func->name) { + /* function already there */ + if (strcmp(func->name, name) == 0) { + func->num_groups++; + return -EEXIST; + } + func++; + } + + func->name = name; + func->num_groups = 1; + + pc->data->num_funcs++; + + return 0; +} + +static struct meson_pmx_func * +meson_pinctrl_find_function_by_name(struct meson_pinctrl *pc, + const char *name) +{ + struct meson_pmx_func *func = pc->data->funcs; + int i; + + for (i = 0; i < pc->data->num_funcs; i++) { + if (!func[i].name) + break; + + if (!strcmp(func[i].name, name)) + return func + i; + } + + return NULL; +} + +static int meson_pinctrl_build_state(struct meson_pinctrl *pc) +{ + const struct meson_desc_pin *pin; + struct meson_pmx_group *group; + struct meson_desc_function *func; + struct meson_pmx_func *funcs_tmp; + struct meson_pmx_func *func_item; + const char **func_grp; + int i; + + /* Allocate pin groups */ + pc->data->num_groups = pc->data->num_pins; + pc->data->groups = devm_kzalloc(pc->dev, + pc->data->num_groups * sizeof(*pc->data->groups), + GFP_KERNEL); + if (!pc->data->groups) + return -ENOMEM; + + for (i = 0; i < pc->data->num_pins; i++) { + pin = pc->data->meson_pins + i; + group = pc->data->groups + i; + group->name = pin->pin.name; + group->pins = &(pin->pin.number); + /*per pin group only include one pin*/ + group->num_pins = 1; + group->reg = pin->reg; + group->bit = pin->bit; + } + + /* + * We suppose that we won't have any more functions than pins, + * we'll reallocate that later anyway + */ + pc->data->funcs = devm_kzalloc(pc->dev, + pc->data->num_pins * sizeof(*pc->data->funcs), + GFP_KERNEL); + if (!pc->data->funcs) + return -ENOMEM; + + /* Count functions and their associated groups */ + for (i = 0; i < pc->data->num_pins; i++) { + pin = pc->data->meson_pins + i; + func = pin->functions; + while (func->name) { + meson_pinctrl_add_function(pc, func->name); + func++; + } + } + + funcs_tmp = krealloc(pc->data->funcs, + pc->data->num_funcs * sizeof(*pc->data->funcs), + GFP_KERNEL); + if (!funcs_tmp) + return -ENOMEM; + + pc->data->funcs = funcs_tmp; + + for (i = 0; i < pc->data->num_pins; i++) { + pin = pc->data->meson_pins + i; + func = pin->functions; + + while (func->name) { + func_item = meson_pinctrl_find_function_by_name(pc, + func->name); + if (!func_item) + return -EINVAL; + + if (!func_item->groups) { + func_item->groups = + devm_kzalloc(pc->dev, + func_item->num_groups * + sizeof(*func_item->groups), + GFP_KERNEL); + if (!func_item->groups) + return -ENOMEM; + } + + func_grp = (const char **)func_item->groups; + while (*func_grp) + func_grp++; + + *func_grp = pin->pin.name; + func++; + } + } + + return 0; +} + static int meson_pinctrl_probe(struct platform_device *pdev) { struct meson_pinctrl_private *priv; const struct of_device_id *match; + struct pinctrl_pin_desc *pins; struct device *dev = &pdev->dev; struct meson_pinctrl *pc; int ret; + int i; pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL); if (!pc) @@ -1178,12 +1356,29 @@ static int meson_pinctrl_probe(struct platform_device *pdev) if (ret) return ret; + if (priv->pinmux_type == PINMUX_V2) { + ret = meson_pinctrl_build_state(pc); + if (ret) + dev_err(pc->dev, "can't register pinctrl device\n"); + + pins = devm_kzalloc(pc->dev, pc->data->num_pins * sizeof(*pins), + GFP_KERNEL); + if (!pins) + return -ENOMEM; + for (i = 0; i < pc->data->num_pins; i++) + pins[i] = pc->data->meson_pins[i].pin; + + pc->desc.pins = (const struct pinctrl_pin_desc *)pins; + pc->desc.pmxops = &meson_pmx_v2_ops; + } else { + pc->desc.pmxops = &meson_pmx_v1_ops; + pc->desc.pins = pc->data->pins; + } + pc->desc.name = "pinctrl-meson"; pc->desc.owner = THIS_MODULE; pc->desc.pctlops = &meson_pctrl_ops; - pc->desc.pmxops = &meson_pmx_ops; pc->desc.confops = &meson_pinconf_ops; - pc->desc.pins = pc->data->pins; pc->desc.npins = pc->data->num_pins; pc->pcdev = pinctrl_register(&pc->desc, pc->dev, pc); diff --git a/drivers/amlogic/pinctrl/pinctrl-meson.h b/drivers/amlogic/pinctrl/pinctrl-meson.h index c999eced1512..a1b05cc55d1a 100644 --- a/drivers/amlogic/pinctrl/pinctrl-meson.h +++ b/drivers/amlogic/pinctrl/pinctrl-meson.h @@ -182,6 +182,7 @@ struct meson_pinctrl_data { const struct pinctrl_pin_desc *pins; struct meson_pmx_group *groups; struct meson_pmx_func *funcs; + const struct meson_desc_pin *meson_pins; struct meson_domain_data *domain_data; unsigned int num_pins; unsigned int num_groups; @@ -189,6 +190,7 @@ struct meson_pinctrl_data { }; struct meson_pinctrl_private { + unsigned char pinmux_type; struct meson_pinctrl_data *pinctrl_data; struct irq_chip *irq_chip; }; @@ -201,7 +203,35 @@ struct meson_pinctrl { struct meson_domain *domain; }; +struct meson_desc_function { + const char *name; + unsigned char muxval; +}; + +struct meson_desc_pin { + struct pinctrl_pin_desc pin; + unsigned int reg; + unsigned int bit; + struct meson_desc_function *functions; +}; + +/* enum PINMUX_TYPE - pinmux type + * + *@PINMUX_V1: use more bits that maybe from different registers to choose + * function for per gpio + *@PINMUX_V2: use continuous 4bit to choose function for per gpio + * + */ +enum PINMUX_TYPE { + PINMUX_V1 = 0, + PINMUX_V2, + PINMUX_MAX, +}; + #define PIN(x, b) (b + x) +#define MESON_MUX_V2_MASK(x) (0xf << x) +#define MESON_MUX_V2_VAL(y, x) ((y & 0xf) << x) +#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x) #define GROUP(grp, r, b) \ { \ @@ -241,7 +271,20 @@ struct meson_pinctrl { }, \ } -#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x) +#define MESON_FUNCTION(_val, _name) \ + { \ + .name = _name, \ + .muxval = _val, \ + } + +#define MESON_PINCTRL_PIN(_pin, r, b, ...) \ + { \ + .pin = _pin, \ + .reg = r, \ + .bit = b, \ + .functions = (struct meson_desc_function[]){ \ + __VA_ARGS__, { } }, \ + } extern struct meson_pinctrl_data meson8_cbus_pinctrl_data; extern struct meson_pinctrl_data meson8_aobus_pinctrl_data; @@ -249,3 +292,5 @@ extern struct meson_pinctrl_data meson8b_cbus_pinctrl_data; extern struct meson_pinctrl_data meson8b_aobus_pinctrl_data; extern struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data; extern struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data; +extern struct meson_pinctrl_data meson_axg_periphs_pinctrl_data; +extern struct meson_pinctrl_data meson_axg_aobus_pinctrl_data; diff --git a/drivers/amlogic/pinctrl/pinctrl-meson8b.c b/drivers/amlogic/pinctrl/pinctrl-meson8b.c index df6819fa7be2..2b7b3b1f9a66 100644 --- a/drivers/amlogic/pinctrl/pinctrl-meson8b.c +++ b/drivers/amlogic/pinctrl/pinctrl-meson8b.c @@ -18,401 +18,399 @@ #include #include "pinctrl-meson.h" -#define AO_OFF 115 +#define EE_OFF 14 static const struct pinctrl_pin_desc meson8b_cbus_pins[] = { - MESON_PIN(GPIOX_0, 0), - MESON_PIN(GPIOX_1, 0), - MESON_PIN(GPIOX_2, 0), - MESON_PIN(GPIOX_3, 0), - MESON_PIN(GPIOX_4, 0), - MESON_PIN(GPIOX_5, 0), - MESON_PIN(GPIOX_6, 0), - MESON_PIN(GPIOX_7, 0), - MESON_PIN(GPIOX_8, 0), - MESON_PIN(GPIOX_9, 0), - MESON_PIN(GPIOX_10, 0), - MESON_PIN(GPIOX_11, 0), - MESON_PIN(GPIOX_16, 0), - MESON_PIN(GPIOX_17, 0), - MESON_PIN(GPIOX_18, 0), - MESON_PIN(GPIOX_19, 0), - MESON_PIN(GPIOX_20, 0), - MESON_PIN(GPIOX_21, 0), + MESON_PIN(GPIOX_0, EE_OFF), + MESON_PIN(GPIOX_1, EE_OFF), + MESON_PIN(GPIOX_2, EE_OFF), + MESON_PIN(GPIOX_3, EE_OFF), + MESON_PIN(GPIOX_4, EE_OFF), + MESON_PIN(GPIOX_5, EE_OFF), + MESON_PIN(GPIOX_6, EE_OFF), + MESON_PIN(GPIOX_7, EE_OFF), + MESON_PIN(GPIOX_8, EE_OFF), + MESON_PIN(GPIOX_9, EE_OFF), + MESON_PIN(GPIOX_10, EE_OFF), + MESON_PIN(GPIOX_11, EE_OFF), + MESON_PIN(GPIOX_16, EE_OFF), + MESON_PIN(GPIOX_17, EE_OFF), + MESON_PIN(GPIOX_18, EE_OFF), + MESON_PIN(GPIOX_19, EE_OFF), + MESON_PIN(GPIOX_20, EE_OFF), + MESON_PIN(GPIOX_21, EE_OFF), - MESON_PIN(GPIOY_0, 0), - MESON_PIN(GPIOY_1, 0), - MESON_PIN(GPIOY_3, 0), - MESON_PIN(GPIOY_6, 0), - MESON_PIN(GPIOY_7, 0), - MESON_PIN(GPIOY_8, 0), - MESON_PIN(GPIOY_9, 0), - MESON_PIN(GPIOY_10, 0), - MESON_PIN(GPIOY_11, 0), - MESON_PIN(GPIOY_12, 0), - MESON_PIN(GPIOY_13, 0), - MESON_PIN(GPIOY_14, 0), + MESON_PIN(GPIOY_0, EE_OFF), + MESON_PIN(GPIOY_1, EE_OFF), + MESON_PIN(GPIOY_3, EE_OFF), + MESON_PIN(GPIOY_6, EE_OFF), + MESON_PIN(GPIOY_7, EE_OFF), + MESON_PIN(GPIOY_8, EE_OFF), + MESON_PIN(GPIOY_9, EE_OFF), + MESON_PIN(GPIOY_10, EE_OFF), + MESON_PIN(GPIOY_11, EE_OFF), + MESON_PIN(GPIOY_12, EE_OFF), + MESON_PIN(GPIOY_13, EE_OFF), + MESON_PIN(GPIOY_14, EE_OFF), - MESON_PIN(GPIODV_9, 0), - MESON_PIN(GPIODV_24, 0), - MESON_PIN(GPIODV_25, 0), - MESON_PIN(GPIODV_26, 0), - MESON_PIN(GPIODV_27, 0), - MESON_PIN(GPIODV_28, 0), - MESON_PIN(GPIODV_29, 0), + MESON_PIN(GPIODV_9, EE_OFF), + MESON_PIN(GPIODV_24, EE_OFF), + MESON_PIN(GPIODV_25, EE_OFF), + MESON_PIN(GPIODV_26, EE_OFF), + MESON_PIN(GPIODV_27, EE_OFF), + MESON_PIN(GPIODV_28, EE_OFF), + MESON_PIN(GPIODV_29, EE_OFF), - MESON_PIN(GPIOH_0, 0), - MESON_PIN(GPIOH_1, 0), - MESON_PIN(GPIOH_2, 0), - MESON_PIN(GPIOH_3, 0), - MESON_PIN(GPIOH_4, 0), - MESON_PIN(GPIOH_5, 0), - MESON_PIN(GPIOH_6, 0), - MESON_PIN(GPIOH_7, 0), - MESON_PIN(GPIOH_8, 0), - MESON_PIN(GPIOH_9, 0), + MESON_PIN(GPIOH_0, EE_OFF), + MESON_PIN(GPIOH_1, EE_OFF), + MESON_PIN(GPIOH_2, EE_OFF), + MESON_PIN(GPIOH_3, EE_OFF), + MESON_PIN(GPIOH_4, EE_OFF), + MESON_PIN(GPIOH_5, EE_OFF), + MESON_PIN(GPIOH_6, EE_OFF), + MESON_PIN(GPIOH_7, EE_OFF), + MESON_PIN(GPIOH_8, EE_OFF), + MESON_PIN(GPIOH_9, EE_OFF), - MESON_PIN(CARD_0, 0), - MESON_PIN(CARD_1, 0), - MESON_PIN(CARD_2, 0), - MESON_PIN(CARD_3, 0), - MESON_PIN(CARD_4, 0), - MESON_PIN(CARD_5, 0), - MESON_PIN(CARD_6, 0), + MESON_PIN(CARD_0, EE_OFF), + MESON_PIN(CARD_1, EE_OFF), + MESON_PIN(CARD_2, EE_OFF), + MESON_PIN(CARD_3, EE_OFF), + MESON_PIN(CARD_4, EE_OFF), + MESON_PIN(CARD_5, EE_OFF), + MESON_PIN(CARD_6, EE_OFF), - MESON_PIN(BOOT_0, 0), - MESON_PIN(BOOT_1, 0), - MESON_PIN(BOOT_2, 0), - MESON_PIN(BOOT_3, 0), - MESON_PIN(BOOT_4, 0), - MESON_PIN(BOOT_5, 0), - MESON_PIN(BOOT_6, 0), - MESON_PIN(BOOT_7, 0), - MESON_PIN(BOOT_8, 0), - MESON_PIN(BOOT_9, 0), - MESON_PIN(BOOT_10, 0), - MESON_PIN(BOOT_11, 0), - MESON_PIN(BOOT_12, 0), - MESON_PIN(BOOT_13, 0), - MESON_PIN(BOOT_14, 0), - MESON_PIN(BOOT_15, 0), - MESON_PIN(BOOT_16, 0), - MESON_PIN(BOOT_17, 0), - MESON_PIN(BOOT_18, 0), + MESON_PIN(BOOT_0, EE_OFF), + MESON_PIN(BOOT_1, EE_OFF), + MESON_PIN(BOOT_2, EE_OFF), + MESON_PIN(BOOT_3, EE_OFF), + MESON_PIN(BOOT_4, EE_OFF), + MESON_PIN(BOOT_5, EE_OFF), + MESON_PIN(BOOT_6, EE_OFF), + MESON_PIN(BOOT_7, EE_OFF), + MESON_PIN(BOOT_8, EE_OFF), + MESON_PIN(BOOT_9, EE_OFF), + MESON_PIN(BOOT_10, EE_OFF), + MESON_PIN(BOOT_11, EE_OFF), + MESON_PIN(BOOT_12, EE_OFF), + MESON_PIN(BOOT_13, EE_OFF), + MESON_PIN(BOOT_14, EE_OFF), + MESON_PIN(BOOT_15, EE_OFF), + MESON_PIN(BOOT_16, EE_OFF), + MESON_PIN(BOOT_17, EE_OFF), + MESON_PIN(BOOT_18, EE_OFF), - MESON_PIN(DIF_0_P, 0), - MESON_PIN(DIF_0_N, 0), - MESON_PIN(DIF_1_P, 0), - MESON_PIN(DIF_1_N, 0), - MESON_PIN(DIF_2_P, 0), - MESON_PIN(DIF_2_N, 0), - MESON_PIN(DIF_3_P, 0), - MESON_PIN(DIF_3_N, 0), - MESON_PIN(DIF_4_P, 0), - MESON_PIN(DIF_4_N, 0), + MESON_PIN(DIF_0_P, EE_OFF), + MESON_PIN(DIF_0_N, EE_OFF), + MESON_PIN(DIF_1_P, EE_OFF), + MESON_PIN(DIF_1_N, EE_OFF), + MESON_PIN(DIF_2_P, EE_OFF), + MESON_PIN(DIF_2_N, EE_OFF), + MESON_PIN(DIF_3_P, EE_OFF), + MESON_PIN(DIF_3_N, EE_OFF), + MESON_PIN(DIF_4_P, EE_OFF), + MESON_PIN(DIF_4_N, EE_OFF), }; static const struct pinctrl_pin_desc meson8b_aobus_pins[] = { - MESON_PIN(GPIOAO_0, AO_OFF), - MESON_PIN(GPIOAO_1, AO_OFF), - MESON_PIN(GPIOAO_2, AO_OFF), - MESON_PIN(GPIOAO_3, AO_OFF), - MESON_PIN(GPIOAO_4, AO_OFF), - MESON_PIN(GPIOAO_5, AO_OFF), - MESON_PIN(GPIOAO_6, AO_OFF), - MESON_PIN(GPIOAO_7, AO_OFF), - MESON_PIN(GPIOAO_8, AO_OFF), - MESON_PIN(GPIOAO_9, AO_OFF), - MESON_PIN(GPIOAO_10, AO_OFF), - MESON_PIN(GPIOAO_11, AO_OFF), - MESON_PIN(GPIOAO_12, AO_OFF), - MESON_PIN(GPIOAO_13, AO_OFF), - MESON_PIN(GPIO_BSD_EN, AO_OFF), - MESON_PIN(GPIO_TEST_N, AO_OFF), + MESON_PIN(GPIOAO_0, 0), + MESON_PIN(GPIOAO_1, 0), + MESON_PIN(GPIOAO_2, 0), + MESON_PIN(GPIOAO_3, 0), + MESON_PIN(GPIOAO_4, 0), + MESON_PIN(GPIOAO_5, 0), + MESON_PIN(GPIOAO_6, 0), + MESON_PIN(GPIOAO_7, 0), + MESON_PIN(GPIOAO_8, 0), + MESON_PIN(GPIOAO_9, 0), + MESON_PIN(GPIOAO_10, 0), + MESON_PIN(GPIOAO_11, 0), + MESON_PIN(GPIOAO_12, 0), + MESON_PIN(GPIOAO_13, 0), }; /* bank X */ -static const unsigned int sd_d0_a_pins[] = { PIN(GPIOX_0, 0) }; -static const unsigned int sd_d1_a_pins[] = { PIN(GPIOX_1, 0) }; -static const unsigned int sd_d2_a_pins[] = { PIN(GPIOX_2, 0) }; -static const unsigned int sd_d3_a_pins[] = { PIN(GPIOX_3, 0) }; -static const unsigned int sdxc_d0_0_a_pins[] = { PIN(GPIOX_4, 0) }; -static const unsigned int sdxc_d47_a_pins[] = { PIN(GPIOX_4, 0), - PIN(GPIOX_5, 0), PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) }; -static const unsigned int sdxc_d13_0_a_pins[] = { PIN(GPIOX_5, 0), - PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) }; -static const unsigned int sd_clk_a_pins[] = { PIN(GPIOX_8, 0) }; -static const unsigned int sd_cmd_a_pins[] = { PIN(GPIOX_9, 0) }; -static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, 0) }; -static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, 0) }; -static const unsigned int uart_tx_b0_pins[] = { PIN(GPIOX_16, 0) }; -static const unsigned int uart_rx_b0_pins[] = { PIN(GPIOX_17, 0) }; -static const unsigned int uart_cts_b0_pins[] = { PIN(GPIOX_18, 0) }; -static const unsigned int uart_rts_b0_pins[] = { PIN(GPIOX_19, 0) }; +static const unsigned int sd_d0_a_pins[] = { PIN(GPIOX_0, EE_OFF) }; +static const unsigned int sd_d1_a_pins[] = { PIN(GPIOX_1, EE_OFF) }; +static const unsigned int sd_d2_a_pins[] = { PIN(GPIOX_2, EE_OFF) }; +static const unsigned int sd_d3_a_pins[] = { PIN(GPIOX_3, EE_OFF) }; +static const unsigned int sdxc_d0_0_a_pins[] = { PIN(GPIOX_4, EE_OFF) }; +static const unsigned int sdxc_d47_a_pins[] = { PIN(GPIOX_4, EE_OFF), + PIN(GPIOX_5, EE_OFF), PIN(GPIOX_6, EE_OFF), PIN(GPIOX_7, EE_OFF) }; +static const unsigned int sdxc_d13_0_a_pins[] = { PIN(GPIOX_5, EE_OFF), + PIN(GPIOX_6, EE_OFF), PIN(GPIOX_7, EE_OFF) }; +static const unsigned int sd_clk_a_pins[] = { PIN(GPIOX_8, EE_OFF) }; +static const unsigned int sd_cmd_a_pins[] = { PIN(GPIOX_9, EE_OFF) }; +static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, EE_OFF) }; +static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, EE_OFF) }; +static const unsigned int uart_tx_b0_pins[] = { PIN(GPIOX_16, EE_OFF) }; +static const unsigned int uart_rx_b0_pins[] = { PIN(GPIOX_17, EE_OFF) }; +static const unsigned int uart_cts_b0_pins[] = { PIN(GPIOX_18, EE_OFF) }; +static const unsigned int uart_rts_b0_pins[] = { PIN(GPIOX_19, EE_OFF) }; -static const unsigned int sdxc_d0_1_a_pins[] = { PIN(GPIOX_0, 0) }; -static const unsigned int sdxc_d13_1_a_pins[] = { PIN(GPIOX_1, 0), - PIN(GPIOX_2, 0), PIN(GPIOX_3, 0) }; -static const unsigned int pcm_out_a_pins[] = { PIN(GPIOX_4, 0) }; -static const unsigned int pcm_in_a_pins[] = { PIN(GPIOX_5, 0) }; -static const unsigned int pcm_fs_a_pins[] = { PIN(GPIOX_6, 0) }; -static const unsigned int pcm_clk_a_pins[] = { PIN(GPIOX_7, 0) }; -static const unsigned int sdxc_clk_a_pins[] = { PIN(GPIOX_8, 0) }; -static const unsigned int sdxc_cmd_a_pins[] = { PIN(GPIOX_9, 0) }; -static const unsigned int pwm_vs_0_pins[] = { PIN(GPIOX_10, 0) }; -static const unsigned int pwm_e_pins[] = { PIN(GPIOX_10, 0) }; -static const unsigned int pwm_vs_1_pins[] = { PIN(GPIOX_11, 0) }; +static const unsigned int sdxc_d0_1_a_pins[] = { PIN(GPIOX_0, EE_OFF) }; +static const unsigned int sdxc_d13_1_a_pins[] = { PIN(GPIOX_1, EE_OFF), + PIN(GPIOX_2, EE_OFF), PIN(GPIOX_3, EE_OFF) }; +static const unsigned int pcm_out_a_pins[] = { PIN(GPIOX_4, EE_OFF) }; +static const unsigned int pcm_in_a_pins[] = { PIN(GPIOX_5, EE_OFF) }; +static const unsigned int pcm_fs_a_pins[] = { PIN(GPIOX_6, EE_OFF) }; +static const unsigned int pcm_clk_a_pins[] = { PIN(GPIOX_7, EE_OFF) }; +static const unsigned int sdxc_clk_a_pins[] = { PIN(GPIOX_8, EE_OFF) }; +static const unsigned int sdxc_cmd_a_pins[] = { PIN(GPIOX_9, EE_OFF) }; +static const unsigned int pwm_vs_0_pins[] = { PIN(GPIOX_10, EE_OFF) }; +static const unsigned int pwm_e_pins[] = { PIN(GPIOX_10, EE_OFF) }; +static const unsigned int pwm_vs_1_pins[] = { PIN(GPIOX_11, EE_OFF) }; -static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_4, 0) }; -static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_5, 0) }; -static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_6, 0) }; -static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_7, 0) }; -static const unsigned int uart_tx_b1_pins[] = { PIN(GPIOX_8, 0) }; -static const unsigned int uart_rx_b1_pins[] = { PIN(GPIOX_9, 0) }; -static const unsigned int uart_cts_b1_pins[] = { PIN(GPIOX_10, 0) }; -static const unsigned int uart_rts_b1_pins[] = { PIN(GPIOX_20, 0) }; +static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_4, EE_OFF) }; +static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_5, EE_OFF) }; +static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_6, EE_OFF) }; +static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_7, EE_OFF) }; +static const unsigned int uart_tx_b1_pins[] = { PIN(GPIOX_8, EE_OFF) }; +static const unsigned int uart_rx_b1_pins[] = { PIN(GPIOX_9, EE_OFF) }; +static const unsigned int uart_cts_b1_pins[] = { PIN(GPIOX_10, EE_OFF) }; +static const unsigned int uart_rts_b1_pins[] = { PIN(GPIOX_20, EE_OFF) }; -static const unsigned int iso7816_0_clk_pins[] = { PIN(GPIOX_6, 0) }; -static const unsigned int iso7816_0_data_pins[] = { PIN(GPIOX_7, 0) }; -static const unsigned int spi_sclk_0_pins[] = { PIN(GPIOX_8, 0) }; -static const unsigned int spi_miso_0_pins[] = { PIN(GPIOX_9, 0) }; -static const unsigned int spi_mosi_0_pins[] = { PIN(GPIOX_10, 0) }; -static const unsigned int iso7816_det_pins[] = { PIN(GPIOX_16, 0) }; -static const unsigned int iso7816_reset_pins[] = { PIN(GPIOX_17, 0) }; -static const unsigned int iso7816_1_clk_pins[] = { PIN(GPIOX_18, 0) }; -static const unsigned int iso7816_1_data_pins[] = { PIN(GPIOX_19, 0) }; -static const unsigned int spi_ss0_0_pins[] = { PIN(GPIOX_20, 0) }; +static const unsigned int iso7816_0_clk_pins[] = { PIN(GPIOX_6, EE_OFF) }; +static const unsigned int iso7816_0_data_pins[] = { PIN(GPIOX_7, EE_OFF) }; +static const unsigned int spi_sclk_0_pins[] = { PIN(GPIOX_8, EE_OFF) }; +static const unsigned int spi_miso_0_pins[] = { PIN(GPIOX_9, EE_OFF) }; +static const unsigned int spi_mosi_0_pins[] = { PIN(GPIOX_10, EE_OFF) }; +static const unsigned int iso7816_det_pins[] = { PIN(GPIOX_16, EE_OFF) }; +static const unsigned int iso7816_reset_pins[] = { PIN(GPIOX_17, EE_OFF) }; +static const unsigned int iso7816_1_clk_pins[] = { PIN(GPIOX_18, EE_OFF) }; +static const unsigned int iso7816_1_data_pins[] = { PIN(GPIOX_19, EE_OFF) }; +static const unsigned int spi_ss0_0_pins[] = { PIN(GPIOX_20, EE_OFF) }; -static const unsigned int tsin_clk_b_pins[] = { PIN(GPIOX_8, 0) }; -static const unsigned int tsin_sop_b_pins[] = { PIN(GPIOX_9, 0) }; -static const unsigned int tsin_d0_b_pins[] = { PIN(GPIOX_10, 0) }; -static const unsigned int pwm_b_pins[] = { PIN(GPIOX_11, 0) }; -static const unsigned int i2c_sda_d0_pins[] = { PIN(GPIOX_16, 0) }; -static const unsigned int i2c_sck_d0_pins[] = { PIN(GPIOX_17, 0) }; -static const unsigned int tsin_d_valid_b_pins[] = { PIN(GPIOX_20, 0) }; +static const unsigned int tsin_clk_b_pins[] = { PIN(GPIOX_8, EE_OFF) }; +static const unsigned int tsin_sop_b_pins[] = { PIN(GPIOX_9, EE_OFF) }; +static const unsigned int tsin_d0_b_pins[] = { PIN(GPIOX_10, EE_OFF) }; +static const unsigned int pwm_b_pins[] = { PIN(GPIOX_11, EE_OFF) }; +static const unsigned int i2c_sda_d0_pins[] = { PIN(GPIOX_16, EE_OFF) }; +static const unsigned int i2c_sck_d0_pins[] = { PIN(GPIOX_17, EE_OFF) }; +static const unsigned int tsin_d_valid_b_pins[] = { PIN(GPIOX_20, EE_OFF) }; /* bank Y */ -static const unsigned int tsin_d_valid_a_pins[] = { PIN(GPIOY_0, 0) }; -static const unsigned int tsin_sop_a_pins[] = { PIN(GPIOY_1, 0) }; -static const unsigned int tsin_d17_a_pins[] = { PIN(GPIOY_6, 0), - PIN(GPIOY_7, 0), PIN(GPIOY_10, 0), PIN(GPIOY_11, 0), - PIN(GPIOY_12, 0), PIN(GPIOY_13, 0), PIN(GPIOY_14, 0) }; -static const unsigned int tsin_clk_a_pins[] = { PIN(GPIOY_8, 0) }; -static const unsigned int tsin_d0_a_pins[] = { PIN(GPIOY_9, 0) }; +static const unsigned int tsin_d_valid_a_pins[] = { PIN(GPIOY_0, EE_OFF) }; +static const unsigned int tsin_sop_a_pins[] = { PIN(GPIOY_1, EE_OFF) }; +static const unsigned int tsin_d17_a_pins[] = { PIN(GPIOY_6, EE_OFF), + PIN(GPIOY_7, EE_OFF), PIN(GPIOY_10, EE_OFF), PIN(GPIOY_11, EE_OFF), + PIN(GPIOY_12, EE_OFF), PIN(GPIOY_13, EE_OFF), PIN(GPIOY_14, EE_OFF) }; +static const unsigned int tsin_clk_a_pins[] = { PIN(GPIOY_8, EE_OFF) }; +static const unsigned int tsin_d0_a_pins[] = { PIN(GPIOY_9, EE_OFF) }; -static const unsigned int spdif_out_0_pins[] = { PIN(GPIOY_3, 0) }; +static const unsigned int spdif_out_0_pins[] = { PIN(GPIOY_3, EE_OFF) }; -static const unsigned int xtal_24m_pins[] = { PIN(GPIOY_3, 0) }; -static const unsigned int iso7816_2_clk_pins[] = { PIN(GPIOY_13, 0) }; -static const unsigned int iso7816_2_data_pins[] = { PIN(GPIOY_14, 0) }; +static const unsigned int xtal_24m_pins[] = { PIN(GPIOY_3, EE_OFF) }; +static const unsigned int iso7816_2_clk_pins[] = { PIN(GPIOY_13, EE_OFF) }; +static const unsigned int iso7816_2_data_pins[] = { PIN(GPIOY_14, EE_OFF) }; /* bank DV */ -static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, 0) }; -static const unsigned int pwm_c0_pins[] = { PIN(GPIODV_29, 0) }; +static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, EE_OFF) }; +static const unsigned int pwm_c0_pins[] = { PIN(GPIODV_29, EE_OFF) }; -static const unsigned int pwm_vs_2_pins[] = { PIN(GPIODV_9, 0) }; -static const unsigned int pwm_vs_3_pins[] = { PIN(GPIODV_28, 0) }; -static const unsigned int pwm_vs_4_pins[] = { PIN(GPIODV_29, 0) }; +static const unsigned int pwm_vs_2_pins[] = { PIN(GPIODV_9, EE_OFF) }; +static const unsigned int pwm_vs_3_pins[] = { PIN(GPIODV_28, EE_OFF) }; +static const unsigned int pwm_vs_4_pins[] = { PIN(GPIODV_29, EE_OFF) }; -static const unsigned int xtal24_out_pins[] = { PIN(GPIODV_29, 0) }; +static const unsigned int xtal24_out_pins[] = { PIN(GPIODV_29, EE_OFF) }; -static const unsigned int uart_tx_c_pins[] = { PIN(GPIODV_24, 0) }; -static const unsigned int uart_rx_c_pins[] = { PIN(GPIODV_25, 0) }; -static const unsigned int uart_cts_c_pins[] = { PIN(GPIODV_26, 0) }; -static const unsigned int uart_rts_c_pins[] = { PIN(GPIODV_27, 0) }; +static const unsigned int uart_tx_c_pins[] = { PIN(GPIODV_24, EE_OFF) }; +static const unsigned int uart_rx_c_pins[] = { PIN(GPIODV_25, EE_OFF) }; +static const unsigned int uart_cts_c_pins[] = { PIN(GPIODV_26, EE_OFF) }; +static const unsigned int uart_rts_c_pins[] = { PIN(GPIODV_27, EE_OFF) }; -static const unsigned int pwm_c1_pins[] = { PIN(GPIODV_9, 0) }; +static const unsigned int pwm_c1_pins[] = { PIN(GPIODV_9, EE_OFF) }; -static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, 0) }; -static const unsigned int i2c_sck_a_pins[] = { PIN(GPIODV_25, 0) }; -static const unsigned int i2c_sda_b0_pins[] = { PIN(GPIODV_26, 0) }; -static const unsigned int i2c_sck_b0_pins[] = { PIN(GPIODV_27, 0) }; -static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIODV_28, 0) }; -static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIODV_29, 0) }; +static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, EE_OFF) }; +static const unsigned int i2c_sck_a_pins[] = { PIN(GPIODV_25, EE_OFF) }; +static const unsigned int i2c_sda_b0_pins[] = { PIN(GPIODV_26, EE_OFF) }; +static const unsigned int i2c_sck_b0_pins[] = { PIN(GPIODV_27, EE_OFF) }; +static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIODV_28, EE_OFF) }; +static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIODV_29, EE_OFF) }; /* bank H */ -static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, 0) }; -static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, 0) }; -static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, 0) }; -static const unsigned int hdmi_cec_0_pins[] = { PIN(GPIOH_3, 0) }; -static const unsigned int eth_txd1_0_pins[] = { PIN(GPIOH_5, 0) }; -static const unsigned int eth_txd0_0_pins[] = { PIN(GPIOH_6, 0) }; -static const unsigned int clk_24m_out_pins[] = { PIN(GPIOH_9, 0) }; +static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, EE_OFF) }; +static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, EE_OFF) }; +static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, EE_OFF) }; +static const unsigned int hdmi_cec_0_pins[] = { PIN(GPIOH_3, EE_OFF) }; +static const unsigned int eth_txd1_0_pins[] = { PIN(GPIOH_5, EE_OFF) }; +static const unsigned int eth_txd0_0_pins[] = { PIN(GPIOH_6, EE_OFF) }; +static const unsigned int clk_24m_out_pins[] = { PIN(GPIOH_9, EE_OFF) }; -static const unsigned int spi_ss1_pins[] = { PIN(GPIOH_0, 0) }; -static const unsigned int spi_ss2_pins[] = { PIN(GPIOH_1, 0) }; -static const unsigned int spi_ss0_1_pins[] = { PIN(GPIOH_3, 0) }; -static const unsigned int spi_miso_1_pins[] = { PIN(GPIOH_4, 0) }; -static const unsigned int spi_mosi_1_pins[] = { PIN(GPIOH_5, 0) }; -static const unsigned int spi_sclk_1_pins[] = { PIN(GPIOH_6, 0) }; +static const unsigned int spi_ss1_pins[] = { PIN(GPIOH_0, EE_OFF) }; +static const unsigned int spi_ss2_pins[] = { PIN(GPIOH_1, EE_OFF) }; +static const unsigned int spi_ss0_1_pins[] = { PIN(GPIOH_3, EE_OFF) }; +static const unsigned int spi_miso_1_pins[] = { PIN(GPIOH_4, EE_OFF) }; +static const unsigned int spi_mosi_1_pins[] = { PIN(GPIOH_5, EE_OFF) }; +static const unsigned int spi_sclk_1_pins[] = { PIN(GPIOH_6, EE_OFF) }; -static const unsigned int eth_txd3_pins[] = { PIN(GPIOH_7, 0) }; -static const unsigned int eth_txd2_pins[] = { PIN(GPIOH_8, 0) }; -static const unsigned int eth_tx_clk_pins[] = { PIN(GPIOH_9, 0) }; +static const unsigned int eth_txd3_pins[] = { PIN(GPIOH_7, EE_OFF) }; +static const unsigned int eth_txd2_pins[] = { PIN(GPIOH_8, EE_OFF) }; +static const unsigned int eth_tx_clk_pins[] = { PIN(GPIOH_9, EE_OFF) }; -static const unsigned int i2c_sda_b1_pins[] = { PIN(GPIOH_3, 0) }; -static const unsigned int i2c_sck_b1_pins[] = { PIN(GPIOH_4, 0) }; -static const unsigned int i2c_sda_c1_pins[] = { PIN(GPIOH_5, 0) }; -static const unsigned int i2c_sck_c1_pins[] = { PIN(GPIOH_6, 0) }; -static const unsigned int i2c_sda_d1_pins[] = { PIN(GPIOH_7, 0) }; -static const unsigned int i2c_sck_d1_pins[] = { PIN(GPIOH_8, 0) }; +static const unsigned int i2c_sda_b1_pins[] = { PIN(GPIOH_3, EE_OFF) }; +static const unsigned int i2c_sck_b1_pins[] = { PIN(GPIOH_4, EE_OFF) }; +static const unsigned int i2c_sda_c1_pins[] = { PIN(GPIOH_5, EE_OFF) }; +static const unsigned int i2c_sck_c1_pins[] = { PIN(GPIOH_6, EE_OFF) }; +static const unsigned int i2c_sda_d1_pins[] = { PIN(GPIOH_7, EE_OFF) }; +static const unsigned int i2c_sck_d1_pins[] = { PIN(GPIOH_8, EE_OFF) }; /* bank BOOT */ -static const unsigned int nand_io_pins[] = { PIN(BOOT_0, 0), - PIN(BOOT_1, 0), PIN(BOOT_2, 0), PIN(BOOT_3, 0), - PIN(BOOT_4, 0), PIN(BOOT_5, 0), PIN(BOOT_6, 0), - PIN(BOOT_7, 0) }; -static const unsigned int nand_io_ce0_pins[] = { PIN(BOOT_8, 0) }; -static const unsigned int nand_io_ce1_pins[] = { PIN(BOOT_9, 0) }; -static const unsigned int nand_io_rb0_pins[] = { PIN(BOOT_10, 0) }; -static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, 0) }; -static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, 0) }; -static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, 0) }; -static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, 0) }; -static const unsigned int nand_dqs_0_pins[] = { PIN(BOOT_15, 0) }; -static const unsigned int nand_dqs_1_pins[] = { PIN(BOOT_18, 0) }; +static const unsigned int nand_io_pins[] = { PIN(BOOT_0, EE_OFF), + PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF), PIN(BOOT_3, EE_OFF), + PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF), PIN(BOOT_6, EE_OFF), + PIN(BOOT_7, EE_OFF) }; +static const unsigned int nand_io_ce0_pins[] = { PIN(BOOT_8, EE_OFF) }; +static const unsigned int nand_io_ce1_pins[] = { PIN(BOOT_9, EE_OFF) }; +static const unsigned int nand_io_rb0_pins[] = { PIN(BOOT_10, EE_OFF) }; +static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, EE_OFF) }; +static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, EE_OFF) }; +static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, EE_OFF) }; +static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, EE_OFF) }; +static const unsigned int nand_dqs_0_pins[] = { PIN(BOOT_15, EE_OFF) }; +static const unsigned int nand_dqs_1_pins[] = { PIN(BOOT_18, EE_OFF) }; -static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, 0)}; -static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, 0), - PIN(BOOT_2, 0), PIN(BOOT_3, 0) }; -static const unsigned int sdxc_d47_c_pins[] = { PIN(BOOT_4, 0), - PIN(BOOT_5, 0), PIN(BOOT_6, 0), PIN(BOOT_7, 0) }; -static const unsigned int sdxc_clk_c_pins[] = { PIN(BOOT_8, 0) }; -static const unsigned int sdxc_cmd_c_pins[] = { PIN(BOOT_10, 0) }; -static const unsigned int nor_d_pins[] = { PIN(BOOT_11, 0) }; -static const unsigned int nor_q_pins[] = { PIN(BOOT_12, 0) }; -static const unsigned int nor_c_pins[] = { PIN(BOOT_13, 0) }; -static const unsigned int nor_cs_pins[] = { PIN(BOOT_18, 0) }; +static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, EE_OFF)}; +static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, EE_OFF), + PIN(BOOT_2, EE_OFF), PIN(BOOT_3, EE_OFF) }; +static const unsigned int sdxc_d47_c_pins[] = { PIN(BOOT_4, EE_OFF), + PIN(BOOT_5, EE_OFF), PIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF) }; +static const unsigned int sdxc_clk_c_pins[] = { PIN(BOOT_8, EE_OFF) }; +static const unsigned int sdxc_cmd_c_pins[] = { PIN(BOOT_10, EE_OFF) }; +static const unsigned int nor_d_pins[] = { PIN(BOOT_11, EE_OFF) }; +static const unsigned int nor_q_pins[] = { PIN(BOOT_12, EE_OFF) }; +static const unsigned int nor_c_pins[] = { PIN(BOOT_13, EE_OFF) }; +static const unsigned int nor_cs_pins[] = { PIN(BOOT_18, EE_OFF) }; -static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, 0) }; -static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, 0) }; -static const unsigned int sd_d2_c_pins[] = { PIN(BOOT_2, 0) }; -static const unsigned int sd_d3_c_pins[] = { PIN(BOOT_3, 0) }; -static const unsigned int sd_cmd_c_pins[] = { PIN(BOOT_8, 0) }; -static const unsigned int sd_clk_c_pins[] = { PIN(BOOT_10, 0) }; +static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, EE_OFF) }; +static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, EE_OFF) }; +static const unsigned int sd_d2_c_pins[] = { PIN(BOOT_2, EE_OFF) }; +static const unsigned int sd_d3_c_pins[] = { PIN(BOOT_3, EE_OFF) }; +static const unsigned int sd_cmd_c_pins[] = { PIN(BOOT_8, EE_OFF) }; +static const unsigned int sd_clk_c_pins[] = { PIN(BOOT_10, EE_OFF) }; /* bank CARD */ -static const unsigned int sd_d1_b_pins[] = { PIN(CARD_0, 0) }; -static const unsigned int sd_d0_b_pins[] = { PIN(CARD_1, 0) }; -static const unsigned int sd_clk_b_pins[] = { PIN(CARD_2, 0) }; -static const unsigned int sd_cmd_b_pins[] = { PIN(CARD_3, 0) }; -static const unsigned int sd_d3_b_pins[] = { PIN(CARD_4, 0) }; -static const unsigned int sd_d2_b_pins[] = { PIN(CARD_5, 0) }; +static const unsigned int sd_d1_b_pins[] = { PIN(CARD_0, EE_OFF) }; +static const unsigned int sd_d0_b_pins[] = { PIN(CARD_1, EE_OFF) }; +static const unsigned int sd_clk_b_pins[] = { PIN(CARD_2, EE_OFF) }; +static const unsigned int sd_cmd_b_pins[] = { PIN(CARD_3, EE_OFF) }; +static const unsigned int sd_d3_b_pins[] = { PIN(CARD_4, EE_OFF) }; +static const unsigned int sd_d2_b_pins[] = { PIN(CARD_5, EE_OFF) }; -static const unsigned int sdxc_d13_b_pins[] = { PIN(CARD_0, 0), - PIN(CARD_4, 0), PIN(CARD_5, 0) }; -static const unsigned int sdxc_d0_b_pins[] = { PIN(CARD_1, 0) }; -static const unsigned int sdxc_clk_b_pins[] = { PIN(CARD_2, 0) }; -static const unsigned int sdxc_cmd_b_pins[] = { PIN(CARD_3, 0) }; +static const unsigned int sdxc_d13_b_pins[] = { PIN(CARD_0, EE_OFF), + PIN(CARD_4, EE_OFF), PIN(CARD_5, EE_OFF) }; +static const unsigned int sdxc_d0_b_pins[] = { PIN(CARD_1, EE_OFF) }; +static const unsigned int sdxc_clk_b_pins[] = { PIN(CARD_2, EE_OFF) }; +static const unsigned int sdxc_cmd_b_pins[] = { PIN(CARD_3, EE_OFF) }; /* bank AO */ -static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, AO_OFF) }; -static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, AO_OFF) }; -static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, AO_OFF) }; -static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, AO_OFF) }; -static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; -static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; -static const unsigned int clk_32k_in_out_pins[] = { PIN(GPIOAO_6, AO_OFF) }; -static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, AO_OFF) }; -static const unsigned int hdmi_cec_1_pins[] = { PIN(GPIOAO_12, AO_OFF) }; -static const unsigned int ir_blaster_pins[] = { PIN(GPIOAO_13, AO_OFF) }; +static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, 0) }; +static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, 0) }; +static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, 0) }; +static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, 0) }; +static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, 0) }; +static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, 0) }; +static const unsigned int clk_32k_in_out_pins[] = { PIN(GPIOAO_6, 0) }; +static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, 0) }; +static const unsigned int hdmi_cec_1_pins[] = { PIN(GPIOAO_12, 0) }; +static const unsigned int ir_blaster_pins[] = { PIN(GPIOAO_13, 0) }; -static const unsigned int pwm_c2_pins[] = { PIN(GPIOAO_3, AO_OFF) }; -static const unsigned int i2c_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; -static const unsigned int i2c_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; -static const unsigned int ir_remote_out_pins[] = { PIN(GPIOAO_7, AO_OFF) }; -static const unsigned int i2s_am_clk_out_pins[] = { PIN(GPIOAO_8, AO_OFF) }; -static const unsigned int i2s_ao_clk_out_pins[] = { PIN(GPIOAO_9, AO_OFF) }; -static const unsigned int i2s_lr_clk_out_pins[] = { PIN(GPIOAO_10, AO_OFF) }; -static const unsigned int i2s_out_01_pins[] = { PIN(GPIOAO_11, AO_OFF) }; +static const unsigned int pwm_c2_pins[] = { PIN(GPIOAO_3, 0) }; +static const unsigned int i2c_sck_ao_pins[] = { PIN(GPIOAO_4, 0) }; +static const unsigned int i2c_sda_ao_pins[] = { PIN(GPIOAO_5, 0) }; +static const unsigned int ir_remote_out_pins[] = { PIN(GPIOAO_7, 0) }; +static const unsigned int i2s_am_clk_out_pins[] = { PIN(GPIOAO_8, 0) }; +static const unsigned int i2s_ao_clk_out_pins[] = { PIN(GPIOAO_9, 0) }; +static const unsigned int i2s_lr_clk_out_pins[] = { PIN(GPIOAO_10, 0) }; +static const unsigned int i2s_out_01_pins[] = { PIN(GPIOAO_11, 0) }; -static const unsigned int uart_tx_ao_b0_pins[] = { PIN(GPIOAO_0, AO_OFF) }; -static const unsigned int uart_rx_ao_b0_pins[] = { PIN(GPIOAO_1, AO_OFF) }; -static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, AO_OFF) }; -static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, AO_OFF) }; -static const unsigned int uart_tx_ao_b1_pins[] = { PIN(GPIOAO_4, AO_OFF) }; -static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) }; -static const unsigned int spdif_out_1_pins[] = { PIN(GPIOAO_6, AO_OFF) }; -static const unsigned int spdif_out_2_pins[] = { PIN(GPIOAO_13, AO_OFF) }; +static const unsigned int uart_tx_ao_b0_pins[] = { PIN(GPIOAO_0, 0) }; +static const unsigned int uart_rx_ao_b0_pins[] = { PIN(GPIOAO_1, 0) }; +static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, 0) }; +static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, 0) }; +static const unsigned int uart_tx_ao_b1_pins[] = { PIN(GPIOAO_4, 0) }; +static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, 0) }; +static const unsigned int spdif_out_1_pins[] = { PIN(GPIOAO_6, 0) }; +static const unsigned int spdif_out_2_pins[] = { PIN(GPIOAO_13, 0) }; -static const unsigned int i2s_in_ch01_pins[] = { PIN(GPIOAO_6, AO_OFF) }; -static const unsigned int i2s_ao_clk_in_pins[] = { PIN(GPIOAO_9, AO_OFF) }; -static const unsigned int i2s_lr_clk_in_pins[] = { PIN(GPIOAO_10, AO_OFF) }; +static const unsigned int i2s_in_ch01_pins[] = { PIN(GPIOAO_6, 0) }; +static const unsigned int i2s_ao_clk_in_pins[] = { PIN(GPIOAO_9, 0) }; +static const unsigned int i2s_lr_clk_in_pins[] = { PIN(GPIOAO_10, 0) }; /* bank DIF */ -static const unsigned int eth_rxd1_pins[] = { PIN(DIF_0_P, 0) }; -static const unsigned int eth_rxd0_pins[] = { PIN(DIF_0_N, 0) }; -static const unsigned int eth_rx_dv_pins[] = { PIN(DIF_1_P, 0) }; -static const unsigned int eth_rx_clk_pins[] = { PIN(DIF_1_N, 0) }; -static const unsigned int eth_txd0_1_pins[] = { PIN(DIF_2_P, 0) }; -static const unsigned int eth_txd1_1_pins[] = { PIN(DIF_2_N, 0) }; -static const unsigned int eth_tx_en_pins[] = { PIN(DIF_3_P, 0) }; -static const unsigned int eth_ref_clk_pins[] = { PIN(DIF_3_N, 0) }; -static const unsigned int eth_mdc_pins[] = { PIN(DIF_4_P, 0) }; -static const unsigned int eth_mdio_en_pins[] = { PIN(DIF_4_N, 0) }; +static const unsigned int eth_rxd1_pins[] = { PIN(DIF_0_P, EE_OFF) }; +static const unsigned int eth_rxd0_pins[] = { PIN(DIF_0_N, EE_OFF) }; +static const unsigned int eth_rx_dv_pins[] = { PIN(DIF_1_P, EE_OFF) }; +static const unsigned int eth_rx_clk_pins[] = { PIN(DIF_1_N, EE_OFF) }; +static const unsigned int eth_txd0_1_pins[] = { PIN(DIF_2_P, EE_OFF) }; +static const unsigned int eth_txd1_1_pins[] = { PIN(DIF_2_N, EE_OFF) }; +static const unsigned int eth_tx_en_pins[] = { PIN(DIF_3_P, EE_OFF) }; +static const unsigned int eth_ref_clk_pins[] = { PIN(DIF_3_N, EE_OFF) }; +static const unsigned int eth_mdc_pins[] = { PIN(DIF_4_P, EE_OFF) }; +static const unsigned int eth_mdio_en_pins[] = { PIN(DIF_4_N, EE_OFF) }; static struct meson_pmx_group meson8b_cbus_groups[] = { - GPIO_GROUP(GPIOX_0, 0), - GPIO_GROUP(GPIOX_1, 0), - GPIO_GROUP(GPIOX_2, 0), - GPIO_GROUP(GPIOX_3, 0), - GPIO_GROUP(GPIOX_4, 0), - GPIO_GROUP(GPIOX_5, 0), - GPIO_GROUP(GPIOX_6, 0), - GPIO_GROUP(GPIOX_7, 0), - GPIO_GROUP(GPIOX_8, 0), - GPIO_GROUP(GPIOX_9, 0), - GPIO_GROUP(GPIOX_10, 0), - GPIO_GROUP(GPIOX_11, 0), - GPIO_GROUP(GPIOX_16, 0), - GPIO_GROUP(GPIOX_17, 0), - GPIO_GROUP(GPIOX_18, 0), - GPIO_GROUP(GPIOX_19, 0), - GPIO_GROUP(GPIOX_20, 0), - GPIO_GROUP(GPIOX_21, 0), + GPIO_GROUP(GPIOX_0, EE_OFF), + GPIO_GROUP(GPIOX_1, EE_OFF), + GPIO_GROUP(GPIOX_2, EE_OFF), + GPIO_GROUP(GPIOX_3, EE_OFF), + GPIO_GROUP(GPIOX_4, EE_OFF), + GPIO_GROUP(GPIOX_5, EE_OFF), + GPIO_GROUP(GPIOX_6, EE_OFF), + GPIO_GROUP(GPIOX_7, EE_OFF), + GPIO_GROUP(GPIOX_8, EE_OFF), + GPIO_GROUP(GPIOX_9, EE_OFF), + GPIO_GROUP(GPIOX_10, EE_OFF), + GPIO_GROUP(GPIOX_11, EE_OFF), + GPIO_GROUP(GPIOX_16, EE_OFF), + GPIO_GROUP(GPIOX_17, EE_OFF), + GPIO_GROUP(GPIOX_18, EE_OFF), + GPIO_GROUP(GPIOX_19, EE_OFF), + GPIO_GROUP(GPIOX_20, EE_OFF), + GPIO_GROUP(GPIOX_21, EE_OFF), - GPIO_GROUP(GPIOY_0, 0), - GPIO_GROUP(GPIOY_1, 0), - GPIO_GROUP(GPIOY_3, 0), - GPIO_GROUP(GPIOY_6, 0), - GPIO_GROUP(GPIOY_7, 0), - GPIO_GROUP(GPIOY_8, 0), - GPIO_GROUP(GPIOY_9, 0), - GPIO_GROUP(GPIOY_10, 0), - GPIO_GROUP(GPIOY_11, 0), - GPIO_GROUP(GPIOY_12, 0), - GPIO_GROUP(GPIOY_13, 0), - GPIO_GROUP(GPIOY_14, 0), + GPIO_GROUP(GPIOY_0, EE_OFF), + GPIO_GROUP(GPIOY_1, EE_OFF), + GPIO_GROUP(GPIOY_3, EE_OFF), + GPIO_GROUP(GPIOY_6, EE_OFF), + GPIO_GROUP(GPIOY_7, EE_OFF), + GPIO_GROUP(GPIOY_8, EE_OFF), + GPIO_GROUP(GPIOY_9, EE_OFF), + GPIO_GROUP(GPIOY_10, EE_OFF), + GPIO_GROUP(GPIOY_11, EE_OFF), + GPIO_GROUP(GPIOY_12, EE_OFF), + GPIO_GROUP(GPIOY_13, EE_OFF), + GPIO_GROUP(GPIOY_14, EE_OFF), - GPIO_GROUP(GPIODV_9, 0), - GPIO_GROUP(GPIODV_24, 0), - GPIO_GROUP(GPIODV_25, 0), - GPIO_GROUP(GPIODV_26, 0), - GPIO_GROUP(GPIODV_27, 0), - GPIO_GROUP(GPIODV_28, 0), - GPIO_GROUP(GPIODV_29, 0), + GPIO_GROUP(GPIODV_9, EE_OFF), + GPIO_GROUP(GPIODV_24, EE_OFF), + GPIO_GROUP(GPIODV_25, EE_OFF), + GPIO_GROUP(GPIODV_26, EE_OFF), + GPIO_GROUP(GPIODV_27, EE_OFF), + GPIO_GROUP(GPIODV_28, EE_OFF), + GPIO_GROUP(GPIODV_29, EE_OFF), - GPIO_GROUP(GPIOH_0, 0), - GPIO_GROUP(GPIOH_1, 0), - GPIO_GROUP(GPIOH_2, 0), - GPIO_GROUP(GPIOH_3, 0), - GPIO_GROUP(GPIOH_4, 0), - GPIO_GROUP(GPIOH_5, 0), - GPIO_GROUP(GPIOH_6, 0), - GPIO_GROUP(GPIOH_7, 0), - GPIO_GROUP(GPIOH_8, 0), - GPIO_GROUP(GPIOH_9, 0), + GPIO_GROUP(GPIOH_0, EE_OFF), + GPIO_GROUP(GPIOH_1, EE_OFF), + GPIO_GROUP(GPIOH_2, EE_OFF), + GPIO_GROUP(GPIOH_3, EE_OFF), + GPIO_GROUP(GPIOH_4, EE_OFF), + GPIO_GROUP(GPIOH_5, EE_OFF), + GPIO_GROUP(GPIOH_6, EE_OFF), + GPIO_GROUP(GPIOH_7, EE_OFF), + GPIO_GROUP(GPIOH_8, EE_OFF), + GPIO_GROUP(GPIOH_9, EE_OFF), - GPIO_GROUP(DIF_0_P, 0), - GPIO_GROUP(DIF_0_N, 0), - GPIO_GROUP(DIF_1_P, 0), - GPIO_GROUP(DIF_1_N, 0), - GPIO_GROUP(DIF_2_P, 0), - GPIO_GROUP(DIF_2_N, 0), - GPIO_GROUP(DIF_3_P, 0), - GPIO_GROUP(DIF_3_N, 0), - GPIO_GROUP(DIF_4_P, 0), - GPIO_GROUP(DIF_4_N, 0), + GPIO_GROUP(DIF_0_P, EE_OFF), + GPIO_GROUP(DIF_0_N, EE_OFF), + GPIO_GROUP(DIF_1_P, EE_OFF), + GPIO_GROUP(DIF_1_N, EE_OFF), + GPIO_GROUP(DIF_2_P, EE_OFF), + GPIO_GROUP(DIF_2_N, EE_OFF), + GPIO_GROUP(DIF_3_P, EE_OFF), + GPIO_GROUP(DIF_3_N, EE_OFF), + GPIO_GROUP(DIF_4_P, EE_OFF), + GPIO_GROUP(DIF_4_N, EE_OFF), GPIO_GROUP(BOOT_0, 0), GPIO_GROUP(BOOT_1, 0), @@ -585,22 +583,20 @@ static struct meson_pmx_group meson8b_cbus_groups[] = { }; static struct meson_pmx_group meson8b_aobus_groups[] = { - GPIO_GROUP(GPIOAO_0, AO_OFF), - GPIO_GROUP(GPIOAO_1, AO_OFF), - GPIO_GROUP(GPIOAO_2, AO_OFF), - GPIO_GROUP(GPIOAO_3, AO_OFF), - GPIO_GROUP(GPIOAO_4, AO_OFF), - GPIO_GROUP(GPIOAO_5, AO_OFF), - GPIO_GROUP(GPIOAO_6, AO_OFF), - GPIO_GROUP(GPIOAO_7, AO_OFF), - GPIO_GROUP(GPIOAO_8, AO_OFF), - GPIO_GROUP(GPIOAO_9, AO_OFF), - GPIO_GROUP(GPIOAO_10, AO_OFF), - GPIO_GROUP(GPIOAO_11, AO_OFF), - GPIO_GROUP(GPIOAO_12, AO_OFF), - GPIO_GROUP(GPIOAO_13, AO_OFF), - GPIO_GROUP(GPIO_BSD_EN, AO_OFF), - GPIO_GROUP(GPIO_TEST_N, AO_OFF), + GPIO_GROUP(GPIOAO_0, 0), + GPIO_GROUP(GPIOAO_1, 0), + GPIO_GROUP(GPIOAO_2, 0), + GPIO_GROUP(GPIOAO_3, 0), + GPIO_GROUP(GPIOAO_4, 0), + GPIO_GROUP(GPIOAO_5, 0), + GPIO_GROUP(GPIOAO_6, 0), + GPIO_GROUP(GPIOAO_7, 0), + GPIO_GROUP(GPIOAO_8, 0), + GPIO_GROUP(GPIOAO_9, 0), + GPIO_GROUP(GPIOAO_10, 0), + GPIO_GROUP(GPIOAO_11, 0), + GPIO_GROUP(GPIOAO_12, 0), + GPIO_GROUP(GPIOAO_13, 0), /* bank AO */ GROUP(uart_tx_ao_a, 0, 12), @@ -661,7 +657,7 @@ static const char * const gpio_groups[] = { "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11", - "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N", + "GPIOAO_12", "GPIOAO_13", "DIF_0_P", "DIF_0_N", "DIF_1_P", "DIF_1_N", "DIF_2_P", "DIF_2_N", "DIF_3_P", "DIF_3_N", @@ -925,25 +921,25 @@ static struct meson_pmx_func meson8b_aobus_functions[] = { static struct meson_bank meson8b_cbus_banks[] = { /* name first last pullen pull dir out in */ - BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), + BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_21, EE_OFF), 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), - BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_16, 0), + BANK("Y", PIN(GPIOY_0, EE_OFF), PIN(GPIOY_16, EE_OFF), 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), - BANK("DV", PIN(GPIODV_0, 0), PIN(GPIODV_29, 0), + BANK("DV", PIN(GPIODV_0, EE_OFF), PIN(GPIODV_29, EE_OFF), 0, 0, 0, 0, 6, 0, 7, 0, 8, 0), - BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), + BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_9, EE_OFF), 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), - BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), + BANK("CARD", PIN(CARD_0, EE_OFF), PIN(CARD_6, EE_OFF), 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), - BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), + BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_18, EE_OFF), 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), - BANK("DIF", PIN(DIF_0_P, 0), PIN(DIF_4_N, 0), + BANK("DIF", PIN(DIF_0_P, EE_OFF), PIN(DIF_4_N, EE_OFF), 5, 8, 5, 8, 12, 12, 13, 12, 14, 12), }; static struct meson_bank meson8b_aobus_banks[] = { /* name first last pullen pull dir out in */ - BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), + BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_13, 0), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), }; @@ -951,7 +947,7 @@ static struct meson_domain_data meson8b_periphs_domain_data = { .name = "cbus-banks", .banks = meson8b_cbus_banks, .num_banks = ARRAY_SIZE(meson8b_cbus_banks), - .pin_base = 0, + .pin_base = 14, .num_pins = 115, }; @@ -959,8 +955,8 @@ static struct meson_domain_data meson8b_aobus_domain_data = { .name = "aobus-banks", .banks = meson8b_aobus_banks, .num_banks = ARRAY_SIZE(meson8b_aobus_banks), - .pin_base = 115, - .num_pins = 16, + .pin_base = 0, + .num_pins = 14, }; struct meson_pinctrl_data meson8b_cbus_pinctrl_data = { diff --git a/drivers/amlogic/pinctrl/pinctrl-mesonaxg.c b/drivers/amlogic/pinctrl/pinctrl-mesonaxg.c new file mode 100644 index 000000000000..0da04a9ef54d --- /dev/null +++ b/drivers/amlogic/pinctrl/pinctrl-mesonaxg.c @@ -0,0 +1,482 @@ +/* + * drivers/amlogic/pinctrl/pinctrl-mesonaxg.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include "pinctrl-meson.h" + +#define EE_OFF 14 + +static const struct meson_desc_pin mesonaxg_periphs_pins[] = { + MESON_PINCTRL_PIN(MESON_PIN(GPIOZ_0, EE_OFF), 0x2, 0, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "spi_a"), /*SPI_CLK_A*/ + MESON_FUNCTION(0x2, "uart_b")), /*UART_RTS_EE_B*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOZ_1, EE_OFF), 0x2, 4, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "spi_a"), /*SPI_MOSI_A*/ + MESON_FUNCTION(0x2, "uart_b")), /*UART_CTS_EE_B*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOZ_2, EE_OFF), 0x2, 8, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "spi_a"), /*SPI_MISO_A*/ + MESON_FUNCTION(0x2, "uart_b")), /*UART_TX_EE_B*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOZ_3, EE_OFF), 0x2, 12, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "spi_a"), /*SPI_SS0_A*/ + MESON_FUNCTION(0x2, "uart_b")), /*UART_RX_EE_B*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOZ_4, EE_OFF), 0x2, 16, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "spi_a"), /*SPI_SS1_A*/ + MESON_FUNCTION(0x2, "pwm_b"), /*PWM_B*/ + MESON_FUNCTION(0x3, "spdif_in")), /*SPDIF_IN*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOZ_5, EE_OFF), 0x2, 20, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "spi_a"), /*SPI_SS2_A*/ + MESON_FUNCTION(0x2, "pwm_a"), /*PWM_A*/ + MESON_FUNCTION(0x3, "spdif_out")), /*SPDIF_OUT*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOZ_6, EE_OFF), 0x2, 24, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "i2c_a"), /*I2C_SCK_A*/ + MESON_FUNCTION(0x2, "uart_ao_b")), /*UART_CTS_AO_B*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOZ_7, EE_OFF), 0x2, 28, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "i2c_a"), /*I2C_SDA_A*/ + MESON_FUNCTION(0x2, "uart_ao_b")), /*UART_RTS_AO_B*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOZ_8, EE_OFF), 0x3, 0, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "i2c_b"), /*I2C_SCK_B*/ + MESON_FUNCTION(0x2, "uart_ao_b")), /*UART_TX_AO_B*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOZ_9, EE_OFF), 0x3, 4, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "i2c_b"), /*I2C_SDA_B*/ + MESON_FUNCTION(0x2, "uart_ao_b")), /*UART_RX_AO_B*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOZ_10, EE_OFF), 0x3, 8, + MESON_FUNCTION(0x0, "gpio")), + MESON_PINCTRL_PIN(MESON_PIN(BOOT_0, EE_OFF), 0x0, 0, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "emmc")), /*EMMC_D0*/ + MESON_PINCTRL_PIN(MESON_PIN(BOOT_1, EE_OFF), 0x0, 4, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "emmc")), /*EMMC_D1*/ + MESON_PINCTRL_PIN(MESON_PIN(BOOT_2, EE_OFF), 0x0, 8, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "emmc")), /*EMMC_D2*/ + MESON_PINCTRL_PIN(MESON_PIN(BOOT_3, EE_OFF), 0x0, 12, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "emmc"), /*EMMC_D3*/ + MESON_FUNCTION(0x3, "norflash")), /*NOR_HOLD*/ + MESON_PINCTRL_PIN(MESON_PIN(BOOT_4, EE_OFF), 0x0, 16, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "emmc"), /*EMMC_D4*/ + MESON_FUNCTION(0x3, "norflash")), /*NOR_D*/ + MESON_PINCTRL_PIN(MESON_PIN(BOOT_5, EE_OFF), 0x0, 20, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "emmc"), /*EMMC_D5*/ + MESON_FUNCTION(0x3, "norflash")), /*NOR_Q*/ + MESON_PINCTRL_PIN(MESON_PIN(BOOT_6, EE_OFF), 0x0, 24, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "emmc"), /*EMMC_D6*/ + MESON_FUNCTION(0x3, "norflash")), /*NOR_C*/ + MESON_PINCTRL_PIN(MESON_PIN(BOOT_7, EE_OFF), 0x0, 28, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "emmc")), /*EMMC_D7*/ + MESON_PINCTRL_PIN(MESON_PIN(BOOT_8, EE_OFF), 0x1, 0, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "emmc"), /*EMMC_CLK*/ + MESON_FUNCTION(0x2, "nandflash")), /*NAND_CE0 */ + MESON_PINCTRL_PIN(MESON_PIN(BOOT_9, EE_OFF), 0x1, 4, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x2, "nandflash"), /*NAND_ALE*/ + MESON_FUNCTION(0x3, "norflash")), /*NOR_WP*/ + MESON_PINCTRL_PIN(MESON_PIN(BOOT_10, EE_OFF), 0x1, 8, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "emmc"), /*EMMC_CMD*/ + MESON_FUNCTION(0x2, "nandflash")), /*NAND_CLE */ + MESON_PINCTRL_PIN(MESON_PIN(BOOT_11, EE_OFF), 0x1, 12, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x2, "nandflash")), /*NAND_WEN_CLK*/ + MESON_PINCTRL_PIN(MESON_PIN(BOOT_12, EE_OFF), 0x1, 16, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x2, "nandflash")), /*NAND_REN_WR */ + MESON_PINCTRL_PIN(MESON_PIN(BOOT_13, EE_OFF), 0x1, 20, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "emmc"), /*EMMC_DS*/ + MESON_FUNCTION(0x2, "nandflash")), /*NAND_RB0*/ + MESON_PINCTRL_PIN(MESON_PIN(BOOT_14, EE_OFF), 0x1, 24, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x3, "norflash")), /*NOR_CS */ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_0, EE_OFF), 0xb, 0, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "mclk_a"), /*MCLK_A*/ + MESON_FUNCTION(0x2, "pwm_vs"), /*PWM_VS*/ + MESON_FUNCTION(0x5, "wifi")), /*WIFI_BEACON*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_1, EE_OFF), 0xb, 4, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "mclk_a"), /*MCLK_A*/ + MESON_FUNCTION(0x3, "spdif_in"), /*SPDIF_IN*/ + MESON_FUNCTION(0x4, "spdif_out"), /*SPDIF_OUT*/ + MESON_FUNCTION(0x5, "wifi")), /*WIFI_BEACON*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_2, EE_OFF), 0xb, 8, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "tdmc_out"), /*TDMC_SCLK*/ + MESON_FUNCTION(0x2, "tdmc_in"), /*TDMC_SLV_SCLK*/ + MESON_FUNCTION(0x3, "spi_b")), /*SPI_MOSI_B*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_3, EE_OFF), 0xb, 12, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "tdmc_out"), /*TDMC_FS*/ + MESON_FUNCTION(0x2, "tdmc_in"), /*TDMC_SLV_FS*/ + MESON_FUNCTION(0x3, "spi_b")), /*SPI_MISO_B*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_4, EE_OFF), 0xb, 16, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "tdmc_out"), /*TDMC_DOUT0*/ + MESON_FUNCTION(0x2, "tdmc_in"), /*TDMC_DIN0*/ + MESON_FUNCTION(0x3, "spi_b")), /*SPI_CLK_B*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_5, EE_OFF), 0xb, 20, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "tdmc_out"), /*TDMC_DOUT1*/ + MESON_FUNCTION(0x2, "tdmc_in"), /*TDMC_DIN1*/ + MESON_FUNCTION(0x3, "spi_b")), /*SPI_SS0_B*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_6, EE_OFF), 0xb, 24, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "tdmc_out"), /*TDMC_DOUT2*/ + MESON_FUNCTION(0x2, "tdmc_in"), /*TDMC_DIN2*/ + MESON_FUNCTION(0x3, "spi_b"), /*SPI_SS1_B*/ + MESON_FUNCTION(0x4, "i2c_d")), /*I2C_SDA_D*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_7, EE_OFF), 0xb, 28, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "tdmc_out"), /*TDMC_DOUT3*/ + MESON_FUNCTION(0x2, "tdmc_in"), /*TDMC_DIN3*/ + MESON_FUNCTION(0x3, "spdif_in"), /*SPDIF_IN*/ + MESON_FUNCTION(0x4, "i2c_d")), /*I2C_SCK_D*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_8, EE_OFF), 0xc, 0, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "tdmb_out"), /*TDMB_SCLK*/ + MESON_FUNCTION(0x2, "tdmb_in")), /*TDMB_SLV_SCLK*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_9, EE_OFF), 0xc, 4, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "tdmb_out"), /*TDMB_FS*/ + MESON_FUNCTION(0x2, "tdmb_in")), /*TDMB_SLV_FS*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_10, EE_OFF), 0xc, 8, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "tdmb_out"), /*TDMB_DOUT0*/ + MESON_FUNCTION(0x2, "tdmb_in")), /*TDMB_DIN0*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_11, EE_OFF), 0xc, 12, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "tdmb_out"), /*TDMB_DOUT1*/ + MESON_FUNCTION(0x2, "tdmb_in"), /*TDMB_DIN1*/ + MESON_FUNCTION(0x3, "spdif_out")), /*SPDIF_OUT*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_12, EE_OFF), 0xc, 16, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "tdmb_out"), /*TDMB_DOUT2*/ + MESON_FUNCTION(0x2, "tdmb_in"), /*TDMB_DIN2*/ + MESON_FUNCTION(0x4, "i2c_d")), /*I2C_SDA_D*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_13, EE_OFF), 0xc, 20, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "tdmb_out"), /*TDMB_DOUT3*/ + MESON_FUNCTION(0x2, "tdmb_in"), /*TDMB_DIN3*/ + MESON_FUNCTION(0x4, "i2c_d")), /*I2C_SCK_D*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_14, EE_OFF), 0xc, 24, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "pdm"), /*PDM_DCLK*/ + MESON_FUNCTION(0x3, "pwm_a"), /*PWM_A*/ + MESON_FUNCTION(0x5, "wifi")), /*WIFI_BEACON*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_15, EE_OFF), 0xc, 28, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "pdm"), /*PDM_DIN0*/ + MESON_FUNCTION(0x2, "tdmc_out"), /*TDMC_DOUT2*/ + MESON_FUNCTION(0x3, "pwm_b"), /*PWM_B*/ + MESON_FUNCTION(0x4, "tdmc_in")), /*TDMC_DIN2*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_16, EE_OFF), 0xd, 0, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "pdm"), /*PDM_DIN1*/ + MESON_FUNCTION(0x2, "tdmc_out"), /*TDMC_DOUT3*/ + MESON_FUNCTION(0x3, "pwm_c"), /*PWM_C*/ + MESON_FUNCTION(0x4, "tdmc_in")), /*TDMC_DIN3*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_17, EE_OFF), 0xd, 4, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "pdm"), /*PDM_DIN2*/ + MESON_FUNCTION(0x2, "tdmb_out"), /*TDMB_DOUT2*/ + MESON_FUNCTION(0x3, "i2c_c"), /*I2C_SDA_C*/ + MESON_FUNCTION(0x4, "tdmb_in"), /*TDMB_DIN2*/ + MESON_FUNCTION(0x5, "eth")), /*ETH_MDIO*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_18, EE_OFF), 0xd, 8, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "pdm"), /*PDM_DIN3*/ + MESON_FUNCTION(0x2, "tdmb_out"), /*TDMB_DOUT3*/ + MESON_FUNCTION(0x3, "i2c_c"), /*I2C_SCK_C*/ + MESON_FUNCTION(0x4, "tdmb_in"), /*TDMB_DIN3*/ + MESON_FUNCTION(0x5, "eth")), /*ETH_MDC*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_19, EE_OFF), 0xd, 12, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "spdif_in"), /*SPDIF_IN*/ + MESON_FUNCTION(0x2, "spdif_out"), /*SPDIF_OUT*/ + MESON_FUNCTION(0x3, "pdm"), /*PDM_DCLK*/ + MESON_FUNCTION(0x4, "i2c_d")), /*I2C_SDA_D*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOA_20, EE_OFF), 0xd, 16, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "spdif_out"), /*SPDIF_OUT*/ + MESON_FUNCTION(0x2, "spdif_in"), /*SPDIF_IN*/ + MESON_FUNCTION(0x4, "i2c_d"), /*I2C_SCK_D*/ + MESON_FUNCTION(0x5, "wifi")), /*WIFI_BEACON*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_0, EE_OFF), 0x4, 0, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "sdio"), /*SDIO_D0*/ + MESON_FUNCTION(0x2, "jtag")), /*JTAG_TDO*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_1, EE_OFF), 0x4, 4, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "sdio"), /*SDIO_D1*/ + MESON_FUNCTION(0x2, "jtag")), /*JTAG_TDI*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_2, EE_OFF), 0x4, 8, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "sdio"), /*SDIO_D2*/ + MESON_FUNCTION(0x2, "uart_ao_a")), /*UART_RX_AO_A*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_3, EE_OFF), 0x4, 12, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "sdio"), /*SDIO_D3*/ + MESON_FUNCTION(0x2, "uart_ao_a")), /*UART_TX_AO_A*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_4, EE_OFF), 0x4, 16, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "sdio"), /*SDIO_CLK*/ + MESON_FUNCTION(0x2, "jtag")), /*JTAG_CLK*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_5, EE_OFF), 0x4, 20, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "sdio"), /*SDIO_CMD*/ + MESON_FUNCTION(0x2, "jtag")), /*JTAG_TMS*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_6, EE_OFF), 0x4, 24, + MESON_FUNCTION(0x0, "gpio")), + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_7, EE_OFF), 0x4, 28, + MESON_FUNCTION(0x0, "gpio")), + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_8, EE_OFF), 0x5, 0, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "uart_a"), /*UART_TX_EE_A*/ + MESON_FUNCTION(0x4, "eth")), /*ETH_TXD0*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_9, EE_OFF), 0x5, 4, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "uart_a"), /*UART_RX_EE_A*/ + MESON_FUNCTION(0x4, "eth")), /*ETH_TXD1*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_10, EE_OFF), 0x5, 8, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "uart_a"), /*UART_CTS_EE_A*/ + MESON_FUNCTION(0x3, "pwm_c"), /*PWM_C*/ + MESON_FUNCTION(0x4, "eth")), /*ETH_TXEN*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_11, EE_OFF), 0x5, 12, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "uart_a"), /*UART_RTS_EE_A*/ + MESON_FUNCTION(0x3, "pwm_d")), /*PWM_D*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_12, EE_OFF), 0x5, 16, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x4, "eth")), /*ETH_RGMII_RX_CLK*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_13, EE_OFF), 0x5, 20, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x4, "eth")), /*ETH_RXD0*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_14, EE_OFF), 0x5, 24, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x4, "eth")), /*ETH_RXD1*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_15, EE_OFF), 0x5, 28, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x4, "eth")), /*ETH_RX_DV*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_16, EE_OFF), 0x6, 0, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "i2c_b"), /*I2C_SCK_B*/ + MESON_FUNCTION(0x2, "uart_b"), /*UART_TX_EE_B*/ + MESON_FUNCTION(0x3, "pwm_d"), /*PWM_D*/ + MESON_FUNCTION(0x4, "spi_b")), /*SPI_SS0_B*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_17, EE_OFF), 0x6, 4, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "i2c_b"), /*I2C_SDA_B*/ + MESON_FUNCTION(0x2, "uart_b"), /*UART_RX_EE_B*/ + MESON_FUNCTION(0x3, "pwm_c"), /*PWM_C*/ + MESON_FUNCTION(0x4, "spi_b")), /*SPI_MOSI_B*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_18, EE_OFF), 0x6, 8, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "i2c_c"), /*I2C_SCK_C*/ + MESON_FUNCTION(0x2, "uart_b"), /*UART_RTS_EE_B*/ + MESON_FUNCTION(0x3, "pwm_a"), /*PWM_A*/ + MESON_FUNCTION(0x4, "spi_b")), /*SPI_MISO_B*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_19, EE_OFF), 0x6, 12, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "i2c_c"), /*I2C_SDA_C*/ + MESON_FUNCTION(0x2, "uart_b"), /*UART_CTS_EE_B*/ + MESON_FUNCTION(0x3, "pwm_b"), /*PWM_B*/ + MESON_FUNCTION(0x4, "spi_b")), /*SPI_CLK_B*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_20, EE_OFF), 0x6, 16, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "pwm_a")), /*PWM_A*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_21, EE_OFF), 0x6, 20, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x4, "eth")), /*ETH_MDIO*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOX_22, EE_OFF), 0x6, 24, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x4, "eth")), /*ETH_MDC*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOY_0, EE_OFF), 0x8, 0, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "eth")), /*ETH_MDIO*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOY_1, EE_OFF), 0x8, 4, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "eth")), /*ETH_MDC*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOY_2, EE_OFF), 0x8, 8, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "eth")), /*ETH_RGMII_RX_CLK*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOY_3, EE_OFF), 0x8, 12, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "eth")), /*ETH_RX_DV*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOY_4, EE_OFF), 0x8, 16, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "eth")), /*ETH_RXD0*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOY_5, EE_OFF), 0x8, 20, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "eth")), /*ETH_RXD1*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOY_6, EE_OFF), 0x8, 24, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "eth")), /*ETH_RXD2_RGMII*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOY_7, EE_OFF), 0x8, 28, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "eth")), /*ETH_RXD3_RGMII*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOY_8, EE_OFF), 0x9, 0, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "eth")), /*ETH_RGMII_TX_CLK*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOY_9, EE_OFF), 0x9, 4, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "eth")), /*ETH_TXEN*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOY_10, EE_OFF), 0x9, 8, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "eth")), /*ETH_TXD0*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOY_11, EE_OFF), 0x9, 12, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "eth")), /*ETH_TXD1*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOY_12, EE_OFF), 0x9, 16, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "eth")), /*ETH_TXD2_RGMII*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOY_13, EE_OFF), 0x9, 20, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "eth")), /*ETH_TXD3_RGMII*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOY_14, EE_OFF), 0x9, 24, + MESON_FUNCTION(0x0, "gpio")), + MESON_PINCTRL_PIN(MESON_PIN(GPIOY_15, EE_OFF), 0x9, 28, + MESON_FUNCTION(0x0, "gpio")), +}; + +static const struct meson_desc_pin mesonaxg_aobus_pins[] = { + MESON_PINCTRL_PIN(MESON_PIN(GPIOAO_0, 0), 0x0, 0, + MESON_FUNCTION(0x0, "gpio_ao"), + MESON_FUNCTION(0x1, "uart_ao_a")), /*UART_TX_AO_A*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOAO_1, 0), 0x0, 4, + MESON_FUNCTION(0x0, "gpio_ao"), + MESON_FUNCTION(0x1, "uart_ao_a")), /*UART_RX_AO_A*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOAO_2, 0), 0x0, 8, + MESON_FUNCTION(0x0, "gpio_ao"), + MESON_FUNCTION(0x1, "uart_ao_b"), /*UART_CTS_AO_B*/ + MESON_FUNCTION(0x2, "uart_ao_a"), /*UART_CTS_AO_A*/ + MESON_FUNCTION(0x3, "pwm_ao_b")), /* PWMAO_B */ + MESON_PINCTRL_PIN(MESON_PIN(GPIOAO_3, 0), 0x0, 12, + MESON_FUNCTION(0x0, "gpio_ao"), + MESON_FUNCTION(0x1, "uart_ao_b"), /*UART_RTS_AO_B*/ + MESON_FUNCTION(0x2, "uart_ao_a"), /*UART_RTS_AO_A*/ + MESON_FUNCTION(0x3, "pwm_ao_a"), /* PWMAO_A */ + MESON_FUNCTION(0x4, "jtag")), /*JTAG_TDI */ + MESON_PINCTRL_PIN(MESON_PIN(GPIOAO_4, 0), 0x0, 16, + MESON_FUNCTION(0x0, "gpio_ao"), + MESON_FUNCTION(0x1, "uart_ao_b"), /*UART_TX_AO_B*/ + MESON_FUNCTION(0x2, "i2c_ao"), /*I2C_SCK_AO*/ + MESON_FUNCTION(0x4, "jtag")), /*JTAG_TDO */ + MESON_PINCTRL_PIN(MESON_PIN(GPIOAO_5, 0), 0x0, 20, + MESON_FUNCTION(0x0, "gpio_ao"), + MESON_FUNCTION(0x1, "uart_ao_b"), /*UART_RX_AO_B*/ + MESON_FUNCTION(0x2, "i2c_ao"), /*I2C_SDA_AO*/ + MESON_FUNCTION(0x4, "jtag")), /*JTAG_CLK */ + MESON_PINCTRL_PIN(MESON_PIN(GPIOAO_6, 0), 0x0, 24, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "ir_in")), /*IR_REMOTE_INPUT*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOAO_7, 0), 0x0, 28, + MESON_FUNCTION(0x0, "gpio"), + MESON_FUNCTION(0x1, "ir_out"), /*IR_REMOTE_OUT*/ + MESON_FUNCTION(0x4, "jtag")), /*JTAG_TMS*/ + MESON_PINCTRL_PIN(MESON_PIN(GPIOAO_8, 0), 0x1, 0, + MESON_FUNCTION(0x0, "gpio_ao"), + MESON_FUNCTION(0x1, "clk32"), /*CLK_32K_IN*/ + MESON_FUNCTION(0x2, "i2c_ao"), /*I2C_SCK_AO*/ + MESON_FUNCTION(0x3, "pwm_ao_c")), /*PWMAO_C */ + MESON_PINCTRL_PIN(MESON_PIN(GPIOAO_9, 0), 0x1, 4, + MESON_FUNCTION(0x0, "gpio_ao"), + MESON_FUNCTION(0x2, "i2c_ao"), /*I2C_SDA_AO*/ + MESON_FUNCTION(0x3, "pwm_ao_d")), /*PWMAO_D */ + MESON_PINCTRL_PIN(MESON_PIN(GPIOAO_10, 0), 0x1, 8, + MESON_FUNCTION(0x0, "gpio_ao"), + MESON_FUNCTION(0x1, "i2c_slave_ao"),/*I2C_SLAVE_SCK_AO*/ + MESON_FUNCTION(0x2, "i2c_ao")), /*I2C_SCK_AO */ + MESON_PINCTRL_PIN(MESON_PIN(GPIOAO_11, 0), 0x1, 12, + MESON_FUNCTION(0x0, "gpio_ao"), + MESON_FUNCTION(0x1, "i2c_slave_ao"),/*I2C_SLAVE_SDA_AO*/ + MESON_FUNCTION(0x2, "i2c_ao")), /*I2C_SDA_AO */ + MESON_PINCTRL_PIN(MESON_PIN(GPIOAO_12, 0), 0x1, 16, + MESON_FUNCTION(0x0, "gpio_ao"), + MESON_FUNCTION(0x1, "clk12"), /*CLK12_24*/ + MESON_FUNCTION(0x3, "pwm_ao_b")), /*PWMAO_B */ + MESON_PINCTRL_PIN(MESON_PIN(GPIOAO_13, 0), 0x1, 20, + MESON_FUNCTION(0x0, "gpio_ao"), + MESON_FUNCTION(0x1, "clk25"), /*CLK25_EE*/ + MESON_FUNCTION(0x2, "gen_clk_ao"), /*GEN_CLK_AO */ + MESON_FUNCTION(0x3, "pwm_ao_c"), /*PWMAO_C */ + MESON_FUNCTION(0x4, "gen_clk")), /*GEN_CLK_EE*/ +}; + +static struct meson_bank mesonaxg_periphs_banks[] = { + /* name first last pullen pull dir out in */ + BANK("A", PIN(GPIOA_0, EE_OFF), PIN(GPIOA_20, EE_OFF), + 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), + BANK("Y", PIN(GPIOY_0, EE_OFF), PIN(GPIOY_15, EE_OFF), + 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), + BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_22, EE_OFF), + 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), + BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_10, EE_OFF), + 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), + BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_14, EE_OFF), + 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), +}; + +static struct meson_bank mesonaxg_aobus_banks[] = { + /* name first last pullen pull dir out in */ + BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_13, 0), + 0, 16, 0, 0, 0, 0, 0, 16, 1, 0), +}; + +static struct meson_domain_data mesonaxg_periphs_domain_data = { + .name = "periphs-banks", + .banks = mesonaxg_periphs_banks, + .num_banks = ARRAY_SIZE(mesonaxg_periphs_banks), + .pin_base = 14, + .num_pins = 85, +}; + +static struct meson_domain_data mesonaxg_aobus_domain_data = { + .name = "aobus-banks", + .banks = mesonaxg_aobus_banks, + .num_banks = ARRAY_SIZE(mesonaxg_aobus_banks), + .pin_base = 0, + .num_pins = 14, +}; + +struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = { + .meson_pins = mesonaxg_periphs_pins, + .domain_data = &mesonaxg_periphs_domain_data, + .num_pins = ARRAY_SIZE(mesonaxg_periphs_pins), +}; + +struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = { + .meson_pins = mesonaxg_aobus_pins, + .domain_data = &mesonaxg_aobus_domain_data, + .num_pins = ARRAY_SIZE(mesonaxg_aobus_pins), +}; diff --git a/include/dt-bindings/gpio/meson8b-gpio.h b/include/dt-bindings/gpio/meson8b-gpio.h index 72a30677798c..46e87f14c356 100644 --- a/include/dt-bindings/gpio/meson8b-gpio.h +++ b/include/dt-bindings/gpio/meson8b-gpio.h @@ -14,8 +14,23 @@ #ifndef _DT_BINDINGS_MESON8B_GPIO_H #define _DT_BINDINGS_MESON8B_GPIO_H - /* First GPIO chip */ +#define GPIOAO_0 0 +#define GPIOAO_1 1 +#define GPIOAO_2 2 +#define GPIOAO_3 3 +#define GPIOAO_4 4 +#define GPIOAO_5 5 +#define GPIOAO_6 6 +#define GPIOAO_7 7 +#define GPIOAO_8 8 +#define GPIOAO_9 9 +#define GPIOAO_10 10 +#define GPIOAO_11 11 +#define GPIOAO_12 12 +#define GPIOAO_13 13 + +/* Second GPIO chip */ #define GPIOH_0 0 #define GPIOH_1 1 #define GPIOH_2 2 @@ -122,25 +137,6 @@ #define GPIOX_20 103 #define GPIOX_21 104 -/* Second GPIO chip */ -#define GPIOAO_0 0 -#define GPIOAO_1 1 -#define GPIOAO_2 2 -#define GPIOAO_3 3 -#define GPIOAO_4 4 -#define GPIOAO_5 5 -#define GPIOAO_6 6 -#define GPIOAO_7 7 -#define GPIOAO_8 8 -#define GPIOAO_9 9 -#define GPIOAO_10 10 -#define GPIOAO_11 11 -#define GPIOAO_12 12 -#define GPIOAO_13 13 -#define GPIO_BSD_EN 14 -#define GPIO_TEST_N 15 - - /* GPIO Bank DIF */ #define DIF_0_P 105 #define DIF_0_N 106 diff --git a/include/dt-bindings/gpio/mesonaxg-gpio.h b/include/dt-bindings/gpio/mesonaxg-gpio.h new file mode 100644 index 000000000000..e916b734d88d --- /dev/null +++ b/include/dt-bindings/gpio/mesonaxg-gpio.h @@ -0,0 +1,125 @@ +/* + * include/dt-bindings/gpio/mesonaxg-gpio.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef _DT_BINDINGS_MESONAXG_GPIO_H +#define _DT_BINDINGS_MESONAXG_GPIO_H + +/* First GPIO chip */ +#define GPIOAO_0 0 +#define GPIOAO_1 1 +#define GPIOAO_2 2 +#define GPIOAO_3 3 +#define GPIOAO_4 4 +#define GPIOAO_5 5 +#define GPIOAO_6 6 +#define GPIOAO_7 7 +#define GPIOAO_8 8 +#define GPIOAO_9 9 +#define GPIOAO_10 10 +#define GPIOAO_11 11 +#define GPIOAO_12 12 +#define GPIOAO_13 13 + +/* Second GPIO chip */ +#define GPIOZ_0 0 +#define GPIOZ_1 1 +#define GPIOZ_2 2 +#define GPIOZ_3 3 +#define GPIOZ_4 4 +#define GPIOZ_5 5 +#define GPIOZ_6 6 +#define GPIOZ_7 7 +#define GPIOZ_8 8 +#define GPIOZ_9 9 +#define GPIOZ_10 10 +#define BOOT_0 11 +#define BOOT_1 12 +#define BOOT_2 13 +#define BOOT_3 14 +#define BOOT_4 15 +#define BOOT_5 16 +#define BOOT_6 17 +#define BOOT_7 18 +#define BOOT_8 19 +#define BOOT_9 20 +#define BOOT_10 21 +#define BOOT_11 22 +#define BOOT_12 23 +#define BOOT_13 24 +#define BOOT_14 25 +#define GPIOA_0 26 +#define GPIOA_1 27 +#define GPIOA_2 28 +#define GPIOA_3 29 +#define GPIOA_4 30 +#define GPIOA_5 31 +#define GPIOA_6 32 +#define GPIOA_7 33 +#define GPIOA_8 34 +#define GPIOA_9 35 +#define GPIOA_10 36 +#define GPIOA_11 37 +#define GPIOA_12 38 +#define GPIOA_13 39 +#define GPIOA_14 40 +#define GPIOA_15 41 +#define GPIOA_16 42 +#define GPIOA_17 43 +#define GPIOA_18 44 +#define GPIOA_19 45 +#define GPIOA_20 46 +#define GPIOX_0 47 +#define GPIOX_1 48 +#define GPIOX_2 49 +#define GPIOX_3 50 +#define GPIOX_4 51 +#define GPIOX_5 52 +#define GPIOX_6 53 +#define GPIOX_7 54 +#define GPIOX_8 55 +#define GPIOX_9 56 +#define GPIOX_10 57 +#define GPIOX_11 58 +#define GPIOX_12 59 +#define GPIOX_13 60 +#define GPIOX_14 61 +#define GPIOX_15 62 +#define GPIOX_16 63 +#define GPIOX_17 64 +#define GPIOX_18 65 +#define GPIOX_19 66 +#define GPIOX_20 67 +#define GPIOX_21 68 +#define GPIOX_22 69 +#define GPIOY_0 70 +#define GPIOY_1 71 +#define GPIOY_2 72 +#define GPIOY_3 73 +#define GPIOY_4 74 +#define GPIOY_5 75 +#define GPIOY_6 76 +#define GPIOY_7 77 +#define GPIOY_8 78 +#define GPIOY_9 79 +#define GPIOY_10 80 +#define GPIOY_11 81 +#define GPIOY_12 82 +#define GPIOY_13 83 +#define GPIOY_14 84 +#define GPIOY_15 85 + +#endif /* _DT_BINDINGS_MESONAXG_GPIO_H */