From 5bdeec86b6ebbb8536177d0598e7a4107ee3b092 Mon Sep 17 00:00:00 2001
From: Ren Jianing <jianing.ren@rock-chips.com>
Date: Tue, 16 Mar 2021 18:10:19 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3566-box: fix combphy1 ref-clk to
 100MHz

Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: I2808f908d087843aba7c4c0fd769b7c80518c022
---
 arch/arm64/boot/dts/rockchip/rk3566-box-demo-v10.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-box-demo-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-box-demo-v10.dtsi
index 68666f597637..10213b62aebf 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-box-demo-v10.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566-box-demo-v10.dtsi
@@ -125,6 +125,8 @@
 };
 
 &combphy1_usq {
+	assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
+	assigned-clock-rates = <100000000>;
 	status = "okay";
 };