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Merge commit '8b9ce96e9b27632cbf780e95eca4a6e35b44589c'

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* commit '8b9ce96e9b27632cbf780e95eca4a6e35b44589c': (25 commits)
  arm64: dts: rockchip: Add rk3576m.dtsi
  drm/rockchip: vop: remove afbc support for rk3399 vop lit
  soc: rockchip: opp_select: Add support to config pvtpll volt sel
  firmware: rockchip_sip: Add sub func id PVTPLL_VOLT_SEL for SIP_PVTPLL_CFG
  arm64: dts: rockchip: Add rk3576j.dtsi
  arm64: dts: rockchip: rk3576: Add opp table rk3576j/m
  mtd: spinand: dosilicon: Support new device DS35Q2GBS
  mtd: spinand: foresee: Support new device F35SQB002G
  mtd: spinand: HIKSEMI: Support new device HSESYHDSW2G
  mtd: spinand: GSTO: Support new device GSS01GSAX1 and GSS02GSAX1
  mtd: spinand: xtx: Support new device XT26Q01DWSIGA
  mtd: spi-nor: xtx: Support xt25q256f
  mtd: spinand: Winbond: Set W25N01KWZPIG buffer read
  mtd: spinand: fmsh: Support new device FM25G02D
  mtd: spinand: xtx: Support new device XT26Q04DWSIGT-B
  mtd: spinand: UNIM: Support new device UM19A9LISW and UM19A9HISW
  mtd: spinand: Winbond: Support new device W25N01KWZPIG
  mtd: spinand: zbit: Add code
  mtd: rawnand: rockchip: Reset controller registers during resume process
  mtd: spinand: foresee: Support new device F35SQB004G
  ...

Change-Id: I466d469f61fec9e6f685645a3cc7010cb6040b56
This commit is contained in:
Tao Huang
2024-11-07 20:30:08 +08:00
parent 80bc0e28fb 8b9ce96e9b
commit 5c06bf0787
23 changed files with 1097 additions and 53 deletions
Download Patch File Download Diff File Expand all files Collapse all files

500
arch/arm64/boot/dts/rockchip/rk3576.dtsi
View File

@@ -400,6 +400,20 @@
nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
rockchip,supported-hw;
rockchip,pvtm-hw = <0x06>;
rockchip,pvtm-voltage-sel-hw = <
0 1744 0
1745 1774 1
1775 1804 2
1805 1839 3
1840 1874 4
1875 1909 5
1910 1949 6
1950 1989 7
1990 2029 8
2030 2069 9
2070 9999 10
>;
rockchip,pvtm-voltage-sel = <
0 1764 0
1765 1789 1
@@ -439,32 +453,32 @@
rockchip,low-temp-min-volt = <800000>;
opp-408000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <712500 712500 950000>;
clock-latency-ns = <40000>;
};
opp-600000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <712500 712500 950000>;
clock-latency-ns = <40000>;
};
opp-816000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <712500 712500 950000>;
clock-latency-ns = <40000>;
};
opp-1008000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <712500 712500 950000>;
opp-microvolt-L0 = <725000 725000 950000>;
clock-latency-ns = <40000>;
};
opp-1200000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <712500 712500 950000>;
opp-microvolt-L0 = <737500 737500 950000>;
@@ -472,7 +486,7 @@
clock-latency-ns = <40000>;
};
opp-1416000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <712500 712500 950000>;
opp-microvolt-L0 = <775000 775000 950000>;
@@ -484,7 +498,7 @@
clock-latency-ns = <40000>;
};
opp-1608000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <812500 812500 950000>;
opp-microvolt-L1 = <800000 800000 950000>;
@@ -500,7 +514,7 @@
clock-latency-ns = <40000>;
};
opp-1800000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <887500 887500 950000>;
opp-microvolt-L1 = <875000 875000 950000>;
@@ -534,7 +548,7 @@
clock-latency-ns = <40000>;
};
opp-2016000000 {
opp-supported-hw = <0xf7 0xffff>;
opp-supported-hw = <0xf1 0xffff>;
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <950000 950000 950000>;
opp-microvolt-L1 = <937500 937500 950000>;
@@ -549,6 +563,96 @@
opp-microvolt-L10 = <825000 825000 950000>;
clock-latency-ns = <40000>;
};
/* RK3576J/M cluster0 OPPs */
opp-j-m-408000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <750000 750000 950000>;
clock-latency-ns = <40000>;
};
opp-j-m-600000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <750000 750000 950000>;
clock-latency-ns = <40000>;
};
opp-j-m-816000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <750000 750000 950000>;
clock-latency-ns = <40000>;
};
opp-j-m-1008000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <750000 750000 950000>;
clock-latency-ns = <40000>;
};
opp-j-m-1200000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <750000 750000 950000>;
clock-latency-ns = <40000>;
};
opp-j-m-1416000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <750000 750000 950000>;
opp-microvolt-L0 = <775000 775000 950000>;
opp-microvolt-L1 = <762500 762500 950000>;
clock-latency-ns = <40000>;
opp-suspend;
};
cluster0_opp_j_m_1608000000: opp-j-m-1608000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <825000 825000 950000>;
opp-microvolt-L1 = <812500 812500 950000>;
opp-microvolt-L2 = <800000 800000 950000>;
opp-microvolt-L3 = <787500 787500 950000>;
opp-microvolt-L4 = <787500 787500 950000>;
opp-microvolt-L5 = <775000 775000 950000>;
opp-microvolt-L6 = <762500 762500 950000>;
opp-microvolt-L7 = <750000 750000 950000>;
opp-microvolt-L8 = <750000 750000 950000>;
opp-microvolt-L9 = <750000 750000 950000>;
opp-microvolt-L10 = <750000 750000 950000>;
clock-latency-ns = <40000>;
};
cluster0_opp_j_m_1800000000: opp-j-m-1800000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <887500 887500 950000>;
opp-microvolt-L1 = <875000 875000 950000>;
opp-microvolt-L2 = <862500 862500 950000>;
opp-microvolt-L3 = <850000 850000 950000>;
opp-microvolt-L4 = <837500 837500 950000>;
opp-microvolt-L5 = <825000 825000 950000>;
opp-microvolt-L6 = <812500 812500 950000>;
opp-microvolt-L7 = <800000 800000 950000>;
opp-microvolt-L8 = <787500 787500 950000>;
opp-microvolt-L9 = <775000 775000 950000>;
opp-microvolt-L10 = <762500 762500 950000>;
clock-latency-ns = <40000>;
};
cluster0_opp_j_m_1920000000: opp-j-m-1920000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <1920000000>;
opp-microvolt = <937500 937500 950000>;
opp-microvolt-L1 = <925000 925000 950000>;
opp-microvolt-L2 = <912500 912500 950000>;
opp-microvolt-L3 = <900000 900000 950000>;
opp-microvolt-L4 = <887500 887500 950000>;
opp-microvolt-L5 = <875000 875000 950000>;
opp-microvolt-L6 = <862500 862500 950000>;
opp-microvolt-L7 = <850000 850000 950000>;
opp-microvolt-L8 = <837500 837500 950000>;
opp-microvolt-L9 = <825000 825000 950000>;
opp-microvolt-L10 = <812500 812500 950000>;
clock-latency-ns = <40000>;
};
};
cluster1_opp_table: cluster1-opp-table {
@@ -560,6 +664,20 @@
nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
rockchip,supported-hw;
rockchip,pvtm-hw = <0x06>;
rockchip,pvtm-voltage-sel-hw = <
0 1874 0
1875 1904 1
1905 1934 2
1935 1969 3
1970 2009 4
2010 2049 5
2050 2089 6
2090 2129 7
2130 2169 8
2170 2209 9
2210 9999 10
>;
rockchip,pvtm-voltage-sel = <
0 1919 0
1920 1949 1
@@ -599,32 +717,32 @@
rockchip,low-temp-min-volt = <800000>;
opp-408000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <712500 712500 950000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-600000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <712500 712500 950000>;
clock-latency-ns = <40000>;
};
opp-816000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <712500 712500 950000>;
clock-latency-ns = <40000>;
};
opp-1008000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <712500 712500 950000>;
clock-latency-ns = <40000>;
};
opp-1200000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <712500 712500 950000>;
opp-microvolt-L0 = <750000 750000 950000>;
@@ -634,7 +752,7 @@
clock-latency-ns = <40000>;
};
opp-1416000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <712500 712500 950000>;
opp-microvolt-L0 = <750000 750000 950000>;
@@ -644,7 +762,7 @@
clock-latency-ns = <40000>;
};
opp-1608000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <725000 725000 950000>;
opp-microvolt-L0 = <775000 775000 950000>;
@@ -655,7 +773,7 @@
clock-latency-ns = <40000>;
};
opp-1800000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <825000 825000 950000>;
opp-microvolt-L1 = <825000 825000 950000>;
@@ -671,7 +789,7 @@
clock-latency-ns = <40000>;
};
opp-2016000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <887500 887500 950000>;
opp-microvolt-L1 = <887500 887500 950000>;
@@ -704,7 +822,7 @@
clock-latency-ns = <40000>;
};
opp-2208000000 {
opp-supported-hw = <0xf7 0xffff>;
opp-supported-hw = <0xf1 0xffff>;
opp-hz = /bits/ 64 <2208000000>;
opp-microvolt = <950000 950000 950000>;
opp-microvolt-L1 = <950000 950000 950000>;
@@ -719,6 +837,103 @@
opp-microvolt-L10 = <837500 837500 950000>;
clock-latency-ns = <40000>;
};
/* RK3576J/M cluster1 OPPs */
opp-j-m-408000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <750000 750000 950000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-j-m-600000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <750000 750000 950000>;
clock-latency-ns = <40000>;
};
opp-j-m-816000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <750000 750000 950000>;
clock-latency-ns = <40000>;
};
opp-j-m-1008000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <750000 750000 950000>;
clock-latency-ns = <40000>;
};
opp-j-m-1200000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <750000 750000 950000>;
clock-latency-ns = <40000>;
};
opp-j-m-1416000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <750000 750000 950000>;
opp-microvolt-L0 = <762500 762500 950000>;
clock-latency-ns = <40000>;
};
opp-j-m-1608000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <750000 750000 950000>;
opp-microvolt-L0 = <787500 787500 950000>;
opp-microvolt-L1 = <775000 775000 950000>;
opp-microvolt-L2 = <762500 762500 950000>;
clock-latency-ns = <40000>;
};
cluster1_opp_j_m_1800000000: opp-j-m-1800000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <850000 850000 950000>;
opp-microvolt-L1 = <837500 837500 950000>;
opp-microvolt-L2 = <825000 825000 950000>;
opp-microvolt-L3 = <812500 812500 950000>;
opp-microvolt-L4 = <800000 800000 950000>;
opp-microvolt-L5 = <787500 787500 950000>;
opp-microvolt-L6 = <775000 775000 950000>;
opp-microvolt-L7 = <762500 762500 950000>;
opp-microvolt-L8 = <750000 750000 950000>;
opp-microvolt-L9 = <750000 750000 950000>;
opp-microvolt-L10 = <750000 750000 950000>;
clock-latency-ns = <40000>;
};
cluster1_opp_j_m_2016000000: opp-j-m-2016000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <912500 912500 950000>;
opp-microvolt-L1 = <900000 900000 950000>;
opp-microvolt-L2 = <887500 887500 950000>;
opp-microvolt-L3 = <875000 875000 950000>;
opp-microvolt-L4 = <862500 862500 950000>;
opp-microvolt-L5 = <850000 850000 950000>;
opp-microvolt-L6 = <837500 837500 950000>;
opp-microvolt-L7 = <825000 825000 950000>;
opp-microvolt-L8 = <812500 812500 950000>;
opp-microvolt-L9 = <800000 800000 950000>;
opp-microvolt-L10 = <787500 787500 950000>;
clock-latency-ns = <40000>;
};
cluster1_opp_j_m_2112000000: opp-j-m-2112000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <2112000000>;
opp-microvolt = <950000 950000 950000>;
opp-microvolt-L1 = <937500 937500 950000>;
opp-microvolt-L2 = <925000 925000 950000>;
opp-microvolt-L3 = <912500 912500 950000>;
opp-microvolt-L4 = <900000 900000 950000>;
opp-microvolt-L5 = <887500 887500 950000>;
opp-microvolt-L6 = <875000 875000 950000>;
opp-microvolt-L7 = <862500 862500 950000>;
opp-microvolt-L8 = <850000 850000 950000>;
opp-microvolt-L9 = <837500 837500 950000>;
opp-microvolt-L10 = <825000 825000 950000>;
clock-latency-ns = <40000>;
};
};
bus_a72: bus-a72 {
@@ -734,8 +949,9 @@
compatible = "operating-points-v2";
opp-shared;
nvmem-cells = <&log_leakage>;
nvmem-cell-names = "leakage";
nvmem-cells = <&log_leakage>, <&specification_serial_number>;
nvmem-cell-names = "leakage", "specification_serial_number";
rockchip,supported-hw;
rockchip,leakage-voltage-sel = <
1 10 0
@@ -744,23 +960,46 @@
>;
opp-1800000000 {
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <750000 750000 800000>;
opp-microvolt-L1 = <725000 725000 800000>;
opp-microvolt-L2 = <712500 712500 800000>;
};
opp-2016000000 {
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <775000 775000 800000>;
opp-microvolt-L1 = <750000 750000 800000>;
opp-microvolt-L2 = <712500 712500 800000>;
};
opp-2208000000 {
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <2208000000>;
opp-microvolt = <800000 800000 800000>;
opp-microvolt-L1 = <775000 775000 800000>;
opp-microvolt-L2 = <737500 737500 800000>;
};
opp-j-m-1800000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <750000 750000 800000>;
};
opp-j-m-2016000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <775000 775000 800000>;
opp-microvolt-L1 = <750000 750000 800000>;
opp-microvolt-L2 = <750000 750000 800000>;
};
opp-j-m-2208000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <2208000000>;
opp-microvolt = <800000 800000 800000>;
opp-microvolt-L1 = <775000 775000 800000>;
opp-microvolt-L2 = <750000 750000 800000>;
};
};
cpuinfo {
@@ -943,8 +1182,9 @@
dmc_opp_table: dmc-opp-table {
compatible = "operating-points-v2";
nvmem-cells = <&log_leakage>, <&logic_opp_info>;
nvmem-cell-names = "leakage", "opp-info";
nvmem-cells = <&log_leakage>, <&logic_opp_info>, <&specification_serial_number>;
nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
rockchip,supported-hw;
rockchip,early-min-microvolt = <0 750000>; /* <vdd_ddr vdd_logic> */
@@ -958,6 +1198,7 @@
21 254 2
>;
opp-528000000 {
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <528000000>;
opp-microvolt = <750000 750000 850000>,
<750000 750000 800000>;
@@ -967,6 +1208,7 @@
<712500 712500 800000>;
};
opp-1068000000 {
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1068000000>;
opp-microvolt = <750000 750000 850000>,
<750000 750000 800000>;
@@ -976,6 +1218,7 @@
<712500 712500 800000>;
};
opp-1560000000 {
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1560000000>;
opp-microvolt = <750000 750000 850000>,
<750000 750000 800000>;
@@ -985,6 +1228,7 @@
<725000 725000 800000>;
};
opp-2736000000 {
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <2736000000>;
opp-microvolt = <825000 825000 850000>,
<750000 750000 800000>;
@@ -993,6 +1237,35 @@
opp-microvolt-L2 = <775000 775000 850000>,
<725000 725000 800000>;
};
/* RK3576J/M DMC OPPs */
opp-j-m-528000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <528000000>;
opp-microvolt = <750000 750000 850000>,
<750000 750000 800000>;
};
opp-j-m-1068000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <1068000000>;
opp-microvolt = <750000 750000 850000>,
<750000 750000 800000>;
};
opp-j-m-1560000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <1560000000>;
opp-microvolt = <750000 750000 850000>,
<750000 750000 800000>;
};
opp-j-m-2736000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <2736000000>;
opp-microvolt = <825000 825000 850000>,
<750000 750000 800000>;
opp-microvolt-L1 = <800000 800000 850000>,
<750000 750000 800000>;
opp-microvolt-L2 = <775000 775000 850000>,
<750000 750000 800000>;
};
};
firmware {
@@ -2170,6 +2443,19 @@
nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
rockchip,supported-hw;
rockchip,pvtm-hw = <0x06>;
rockchip,pvtm-voltage-sel-hw = <
0 739 0
740 759 1
760 779 2
780 799 3
800 819 4
820 839 5
840 859 6
860 879 7
880 899 8
900 9999 9
>;
rockchip,pvtm-voltage-sel = <
0 719 0
720 739 1
@@ -2211,12 +2497,12 @@
rockchip,low-temp-min-volt = <750000>;
opp-300000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <725000 725000 875000>;
};
opp-400000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <725000 725000 875000>;
};
@@ -2230,21 +2516,21 @@
opp-microvolt-L2 = <737500 737500 875000>;
};
opp-500000000 {
opp-supported-hw = <0xf7 0xffff>;
opp-supported-hw = <0xf1 0xffff>;
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <725000 725000 875000>;
opp-microvolt-L0 = <737500 737500 875000>;
opp-microvolt-L1 = <737500 737500 875000>;
};
opp-600000000 {
opp-supported-hw = <0xf7 0xffff>;
opp-supported-hw = <0xf1 0xffff>;
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <725000 725000 875000>;
opp-microvolt-L0 = <737500 737500 875000>;
opp-microvolt-L1 = <737500 737500 875000>;
};
opp-700000000 {
opp-supported-hw = <0xf7 0xffff>;
opp-supported-hw = <0xf1 0xffff>;
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <725000 725000 875000>;
opp-microvolt-L0 = <775000 775000 875000>;
@@ -2256,7 +2542,7 @@
opp-microvolt-L6 = <725000 725000 875000>;
};
opp-800000000 {
opp-supported-hw = <0xf7 0xffff>;
opp-supported-hw = <0xf1 0xffff>;
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <800000 800000 875000>;
opp-microvolt-L1 = <800000 800000 875000>;
@@ -2271,7 +2557,7 @@
opp-microvolt-L10 = <725000 725000 875000>;
};
opp-900000000 {
opp-supported-hw = <0xf7 0xffff>;
opp-supported-hw = <0xf1 0xffff>;
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <850000 850000 875000>;
opp-microvolt-L1 = <850000 850000 875000>;
@@ -2286,7 +2572,7 @@
opp-microvolt-L10 = <737500 737500 875000>;
};
opp-950000000 {
opp-supported-hw = <0xf7 0xffff>;
opp-supported-hw = <0xf1 0xffff>;
opp-hz = /bits/ 64 <950000000>;
opp-microvolt = <875000 875000 875000>;
opp-microvolt-L1 = <875000 875000 875000>;
@@ -2300,6 +2586,61 @@
opp-microvolt-L9 = <775000 775000 875000>;
opp-microvolt-L10 = <762500 762500 875000>;
};
/* RK3576J/M NPU OPPs */
opp-j-m-300000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <750000 750000 875000>;
};
opp-j-m-400000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <750000 750000 875000>;
};
opp-j-m-500000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <750000 750000 875000>;
};
opp-j-m-600000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <750000 750000 875000>;
};
opp-j-m-700000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <750000 750000 875000>;
opp-microvolt-L0 = <787500 787500 875000>;
opp-microvolt-L1 = <775000 775000 875000>;
opp-microvolt-L2 = <762500 762500 875000>;
};
npu_opp_j_m_800000000: opp-j-m-800000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <750000 750000 875000>;
opp-microvolt-L0 = <812500 812500 875000>;
opp-microvolt-L1 = <800000 800000 875000>;
opp-microvolt-L2 = <787500 787500 875000>;
opp-microvolt-L3 = <775000 775000 875000>;
opp-microvolt-L4 = <762500 762500 875000>;
};
npu_opp_j_m_850000000: opp-j-m-850000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <850000000>;
opp-microvolt = <837500 837500 875000>;
opp-microvolt-L1 = <825000 825000 875000>;
opp-microvolt-L2 = <812500 812500 875000>;
opp-microvolt-L3 = <800000 800000 875000>;
opp-microvolt-L4 = <787500 787500 875000>;
opp-microvolt-L5 = <775000 775000 875000>;
opp-microvolt-L6 = <762500 762500 875000>;
opp-microvolt-L7 = <750000 750000 875000>;
opp-microvolt-L8 = <750000 750000 875000>;
opp-microvolt-L9 = <750000 750000 875000>;
};
};
rknpu_mmu: iommu@27702000 {
@@ -2347,6 +2688,20 @@
nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
rockchip,supported-hw;
rockchip,pvtm-hw = <0x06>;
rockchip,pvtm-voltage-sel-hw = <
0 689 0
690 709 1
710 729 2
730 749 3
750 769 4
770 789 5
790 809 6
810 829 7
830 849 8
850 869 9
870 9999 10
>;
rockchip,pvtm-voltage-sel = <
0 704 0
705 724 1
@@ -2386,27 +2741,27 @@
rockchip,low-temp-min-volt = <750000>;
opp-300000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <712500 712500 875000>;
};
opp-400000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <712500 712500 875000>;
};
opp-500000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <712500 712500 875000>;
};
opp-600000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <712500 712500 875000>;
};
opp-700000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <712500 712500 875000>;
opp-microvolt-L0 = <750000 750000 875000>;
@@ -2432,7 +2787,7 @@
opp-microvolt-L10 = <725000 725000 875000>;
};
opp-800000000 {
opp-supported-hw = <0xf7 0xffff>;
opp-supported-hw = <0xf1 0xffff>;
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <812500 812500 875000>;
opp-microvolt-L1 = <812500 812500 875000>;
@@ -2447,7 +2802,7 @@
opp-microvolt-L10 = <725000 725000 875000>;
};
opp-900000000 {
opp-supported-hw = <0xf7 0xffff>;
opp-supported-hw = <0xf1 0xffff>;
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <875000 875000 875000>;
opp-microvolt-L1 = <875000 875000 875000>;
@@ -2461,6 +2816,50 @@
opp-microvolt-L9 = <775000 775000 875000>;
opp-microvolt-L10 = <762500 762500 875000>;
};
/* RK3576J/M GPU OPPs */
opp-j-m-300000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <750000 750000 950000>;
};
opp-j-m-400000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <750000 750000 950000>;
};
opp-j-m-500000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <750000 750000 950000>;
};
opp-j-m-600000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <750000 750000 950000>;
};
opp-j-m-700000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <750000 750000 950000>;
opp-microvolt-L0 = <775000 775000 950000>;
opp-microvolt-L1 = <762500 762500 950000>;
};
gpu_opp_j_m_800000000: opp-j-m-800000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <850000 850000 875000>;
opp-microvolt-L1 = <837500 837500 875000>;
opp-microvolt-L2 = <825000 825000 875000>;
opp-microvolt-L3 = <812500 812500 875000>;
opp-microvolt-L4 = <800000 800000 875000>;
opp-microvolt-L5 = <787500 787500 875000>;
opp-microvolt-L6 = <775000 775000 875000>;
opp-microvolt-L7 = <762500 762500 875000>;
opp-microvolt-L8 = <750000 750000 875000>;
opp-microvolt-L9 = <750000 750000 875000>;
opp-microvolt-L10 = <750000 750000 875000>;
};
};
ebc: ebc@27900000 {
@@ -3140,8 +3539,9 @@
vop_opp_table: vop-opp-table {
compatible = "operating-points-v2";
nvmem-cells = <&log_leakage>;
nvmem-cell-names = "leakage";
nvmem-cells = <&log_leakage>, <&specification_serial_number>;
nvmem-cell-names = "leakage", "specification_serial_number";
rockchip,supported-hw;
rockchip,early-min-microvolt = <750000>; /* vdd_logic */
@@ -3157,23 +3557,43 @@
21 254 2
>;
opp-500000000 {
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <725000 725000 800000>;
opp-microvolt-L1 = <712500 712500 800000>;
opp-microvolt-L2 = <712500 712500 800000>;
};
opp-594000000 {
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <594000000>;
opp-microvolt = <750000 750000 800000>;
opp-microvolt-L1 = <750000 750000 800000>;
opp-microvolt-L2 = <725000 725000 800000>;
};
opp-702000000 {
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <702000000>;
opp-microvolt = <750000 750000 800000>;
opp-microvolt-L1 = <750000 750000 800000>;
opp-microvolt-L2 = <725000 725000 800000>;
};
/* RK3576J/M VOP OPPs */
opp-j-m-500000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <750000 750000 800000>;
};
opp-j-m-594000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <594000000>;
opp-microvolt = <750000 750000 800000>;
};
opp-j-m-702000000 {
opp-supported-hw = <0x06 0xffff>;
opp-hz = /bits/ 64 <702000000>;
opp-microvolt = <750000 750000 800000>;
};
};
vop_mmu: iommu@27d07e00 {

71
arch/arm64/boot/dts/rockchip/rk3576j.dtsi Normal file
View File

@@ -0,0 +1,71 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3576.dtsi"
/*
* The Max frequency of cluster0 is 1416MHz in default normal mode.
* The Max frequency of cluster0 is 1920MHz in overdrive mode,
* but under the overdrive mode for a long time,
* the chipset may shorten the lifetime,
* especially in high temperature condition.
*/
&cluster0_opp_j_m_1608000000 {
status = "disabled";
};
&cluster0_opp_j_m_1800000000 {
status = "disabled";
};
&cluster0_opp_j_m_1920000000 {
status = "disabled";
};
/*
* The Max frequency of cluster1 is 1608MHz in default normal mode.
* The Max frequency of cluster1 is 2112MHz in overdrive mode,
* but under the overdrive mode for a long time,
* the chipset may shorten the lifetime,
* especially in high temperature condition.
*/
&cluster1_opp_j_m_1800000000 {
status = "disabled";
};
&cluster1_opp_j_m_2016000000 {
status = "disabled";
};
&cluster1_opp_j_m_2112000000 {
status = "disabled";
};
/*
* The Max frequency of GPU is 700MHz in default normal mode.
* The Max frequency of GPU is 800MHz in overdrive mode,
* but under the overdrive mode for a long time,
* the chipset may shorten the lifetime,
* especially in high temperature condition.
*/
&gpu_opp_j_m_800000000 {
status = "disabled";
};
/*
* The Max frequency of NPU is 700MHz in default normal mode.
* The Max frequency of NPU is 850MHz in overdrive mode,
* but under the overdrive mode for a long time,
* the chipset may shorten the lifetime,
* especially in high temperature condition.
*/
&npu_opp_j_m_800000000 {
status = "disabled";
};
&npu_opp_j_m_850000000 {
status = "disabled";
};

7
arch/arm64/boot/dts/rockchip/rk3576m.dtsi Normal file
View File

@@ -0,0 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3576.dtsi"

4
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View File

@@ -742,13 +742,11 @@ static const struct vop_data rk3399_vop_big = {
static const struct vop_win_data rk3399_vop_lit_win_data[] = {
{ .base = 0x00, .phy = &rk3399_win01_data, .csc = &rk3399_win0_csc,
.format_modifiers = format_modifiers,
.type = DRM_PLANE_TYPE_OVERLAY,
.feature = WIN_FEATURE_AFBDC },
.type = DRM_PLANE_TYPE_OVERLAY },
{ .phy = NULL },
{ .base = 0x00, .phy = &rk3368_win23_data, .csc = &rk3399_win2_csc,
.format_modifiers = format_modifiers,
.type = DRM_PLANE_TYPE_PRIMARY,
.feature = WIN_FEATURE_AFBDC,
.area = rk3368_area_data,
.area_size = ARRAY_SIZE(rk3368_area_data), },
{ .phy = NULL },

4
drivers/media/platform/rockchip/cif/hw.c
View File

@@ -1568,8 +1568,8 @@ static int rkcif_plat_hw_probe(struct platform_device *pdev)
if (irq < 0)
return irq;
if (cif_hw->chip_id == CHIP_RV1106_CIF ||
cif_hw->chip_id == CHIP_RV1103B_CIF) {
if (data->chip_id == CHIP_RV1106_CIF ||
data->chip_id == CHIP_RV1103B_CIF) {
irq_set_status_flags(irq, IRQ_NOAUTOEN);
ret = devm_request_irq(dev, irq, rkcif_irq_handler,
0,

87
drivers/media/platform/rockchip/cif/subdev-itf.c
View File

@@ -23,6 +23,7 @@
#include <linux/regulator/consumer.h>
#include <linux/rk-camera-module.h>
#include "common.h"
#include "../../../i2c/cam-tb-setup.h"
static inline struct sditf_priv *to_sditf_priv(struct v4l2_subdev *subdev)
{
@@ -377,6 +378,79 @@ static void sditf_reinit_mode(struct sditf_priv *priv, struct rkisp_vicap_mode *
__func__, mode->rdbk_mode, mode->name, priv->toisp_inf.link_mode);
}
#ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_SETUP
static void sditf_select_sensor_setting_for_thunderboot(struct sditf_priv *priv)
{
struct rkcif_device *dev = priv->cif_dev;
struct v4l2_subdev_format fmt;
struct rk_sensor_setting sensor_setting = {0};
struct v4l2_subdev_frame_interval fi = {0};
struct rkmodule_hdr_cfg hdr_cfg;
int width = 0;
int height = 0;
int hdr_mode = 0;
int max_fps = 0;
int ret = 0;
bool is_match = false;
if (!dev->terminal_sensor.sd)
rkcif_update_sensor_info(&dev->stream[0]);
if (dev->terminal_sensor.sd) {
if (priv->mode.dev_id == 0) {
width = get_rk_cam_w();
height = get_rk_cam_h();
hdr_mode = get_rk_cam_hdr();
max_fps = get_rk_cam1_max_fps();
} else {
width = get_rk_cam2_w();
height = get_rk_cam2_h();
hdr_mode = get_rk_cam2_hdr();
max_fps = get_rk_cam2_max_fps();
}
fmt.pad = 0;
fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
fmt.reserved[0] = 0;
fmt.format.field = V4L2_FIELD_NONE;
ret = v4l2_subdev_call(dev->terminal_sensor.sd, pad, get_fmt, NULL, &fmt);
if (!ret) {
if (dev->rdbk_debug)
v4l2_info(&dev->v4l2_dev,
"cmdline get %dx%d@%dfps, hdr_mode %d\n",
width, height, max_fps, hdr_mode);
sensor_setting.fmt = fmt.format.code;
sensor_setting.width = width;
sensor_setting.height = height;
sensor_setting.mode = hdr_mode;
sensor_setting.fps = max_fps;
ret = v4l2_subdev_call(dev->terminal_sensor.sd,
core, ioctl,
RKCIS_CMD_SELECT_SETTING,
&sensor_setting);
if (!ret)
is_match = true;
}
if (!is_match) {
fmt.format.width = width;
fmt.format.height = height;
v4l2_subdev_call(dev->terminal_sensor.sd, pad, set_fmt, NULL, &fmt);
v4l2_subdev_call(dev->terminal_sensor.sd, video, g_frame_interval, &fi);
fi.interval.numerator = 1;
fi.interval.denominator = max_fps;
v4l2_subdev_call(dev->terminal_sensor.sd, video, s_frame_interval, &fi);
v4l2_subdev_call(dev->terminal_sensor.sd,
core, ioctl,
RKMODULE_GET_HDR_CFG,
&hdr_cfg);
hdr_cfg.hdr_mode = hdr_mode;
v4l2_subdev_call(dev->terminal_sensor.sd,
core, ioctl,
RKMODULE_SET_HDR_CFG,
&hdr_cfg);
}
}
}
#endif
static void sditf_enable_immediately(struct sditf_priv *priv);
static long sditf_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
@@ -429,6 +503,10 @@ static long sditf_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
mode->input.multi_sync = 0;
else
mode->input.multi_sync = 1;
#ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_SETUP
if (cif_dev->is_thunderboot)
sditf_select_sensor_setting_for_thunderboot(priv);
#endif
return 0;
case RKISP_VICAP_CMD_INIT_BUF:
pisp_buf_info = (struct rkisp_init_buf *)arg;
@@ -1175,7 +1253,6 @@ static int sditf_s_rx_buffer(struct v4l2_subdev *sd,
{
struct sditf_priv *priv = to_sditf_priv(sd);
struct rkcif_device *cif_dev = priv->cif_dev;
struct rkcif_sensor_info *sensor = &cif_dev->terminal_sensor;
struct rkcif_stream *stream = NULL;
struct rkisp_rx_buf *dbufs;
struct rkcif_rx_buffer *rx_buf = NULL;
@@ -1315,13 +1392,13 @@ static int sditf_s_rx_buffer(struct v4l2_subdev *sd,
diff_time = 200000;
else
diff_time = 1000000;
if (dbufs->runtime_us * 1000 < cif_dev->sensor_linetime * sensor->raw_rect.height &&
if (dbufs->runtime_us * 1000 < cif_dev->sensor_linetime * stream->pixm.height &&
dbufs->runtime_us * 1000 + cif_dev->sensor_linetime > diff_time)
early_time = dbufs->runtime_us * 1000 - diff_time;
else
early_time = diff_time;
cif_dev->early_line = div_u64(early_time, cif_dev->sensor_linetime);
cif_dev->wait_line_cache = sensor->raw_rect.height - cif_dev->early_line;
cif_dev->wait_line_cache = stream->pixm.height - cif_dev->early_line;
if (cif_dev->rdbk_debug &&
dbufs->sequence < 15)
v4l2_info(&cif_dev->v4l2_dev,
@@ -1336,13 +1413,13 @@ static int sditf_s_rx_buffer(struct v4l2_subdev *sd,
diff_time = 200000;
else
diff_time = 1000000;
if (dbufs->runtime_us * 1000 < cif_dev->sensor_linetime * sensor->raw_rect.height &&
if (dbufs->runtime_us * 1000 < cif_dev->sensor_linetime * stream->pixm.height &&
dbufs->runtime_us * 1000 + cif_dev->sensor_linetime > diff_time)
early_time = dbufs->runtime_us * 1000 - diff_time;
else
early_time = diff_time;
cif_dev->early_line = div_u64(early_time, cif_dev->sensor_linetime);
cif_dev->wait_line_cache = sensor->raw_rect.height - cif_dev->early_line;
cif_dev->wait_line_cache = stream->pixm.height - cif_dev->early_line;
}
if (cif_dev->rdbk_debug &&
dbufs->sequence < 15)

7
drivers/mtd/nand/raw/rockchip-nand-controller.c
View File

@@ -795,8 +795,10 @@ static int rk_nfc_read_page_hwecc(struct nand_chip *chip, u8 *buf, int oob_on,
dma_oob);
ret = wait_for_completion_timeout(&nfc->done,
msecs_to_jiffies(100));
if (!ret)
if (!ret) {
print_hex_dump(KERN_WARNING, "reg:", DUMP_PREFIX_OFFSET, 4, 4, nfc->regs, 0x84, 0);
dev_warn(nfc->dev, "read: wait dma done timeout.\n");
}
/*
* Whether the DMA transfer is completed or not. The driver
* needs to check the NFC`s status register to see if the data
@@ -1465,6 +1467,9 @@ static int __maybe_unused rk_nfc_resume(struct device *dev)
if (ret)
return ret;
rk_nfc_hw_init(nfc);
nfc->cur_ecc = 0;
/* Reset NAND chip if VCC was powered off. */
list_for_each_entry(rknand, &nfc->chips, node) {
chip = &rknand->chip;

2
drivers/mtd/nand/spi/Makefile
View File

@@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
spinand-objs := core.o ato.o gigadevice.o gsto.o macronix.o micron.o paragon.o toshiba.o winbond.o biwin.o dosilicon.o esmt.o etron.o fmsh.o foresee.o hyf.o jsc.o silicongo.o skyhigh.o unim.o xincun.o xtx.o
spinand-objs := core.o ato.o gigadevice.o gsto.o macronix.o micron.o paragon.o toshiba.o winbond.o biwin.o dosilicon.o esmt.o etron.o fmsh.o foresee.o hiksemi.o hyf.o jsc.o silicongo.o skyhigh.o unim.o xincun.o xtx.o zbit.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o

2
drivers/mtd/nand/spi/core.c
View File

@@ -960,6 +960,7 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = {
&foresee_spinand_manufacturer,
&gigadevice_spinand_manufacturer,
&gsto_spinand_manufacturer,
&hiksemi_spinand_manufacturer,
&hyf_spinand_manufacturer,
&jsc_spinand_manufacturer,
&macronix_spinand_manufacturer,
@@ -973,6 +974,7 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = {
&winbond_spinand_manufacturer,
&xincun_spinand_manufacturer,
&xtx_spinand_manufacturer,
&zbit_spinand_manufacturer,
};
static int spinand_manufacturer_match(struct spinand_device *spinand,

9
drivers/mtd/nand/spi/dosilicon.c
View File

@@ -258,6 +258,15 @@ static const struct spinand_info dosilicon_spinand_table[] = {
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
SPINAND_INFO("DS35Q2GBS",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2),
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)),
};
static const struct spinand_manufacturer_ops dosilicon_spinand_manuf_ops = {

73
drivers/mtd/nand/spi/fmsh.c
View File

@@ -105,6 +105,61 @@ static int fm25s01bi3_ecc_ecc_get_status(struct spinand_device *spinand,
return -EBADMSG;
}
static int fm25g0xd_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
return -ERANGE;
region->offset = 64;
region->length = 64;
return 0;
}
static int fm25g0xd_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
return -ERANGE;
/* Reserve 2 bytes for the BBM. */
region->offset = 2;
region->length = 62;
return 0;
}
static const struct mtd_ooblayout_ops fm25g0xd_ooblayout = {
.ecc = fm25g0xd_ooblayout_ecc,
.free = fm25g0xd_ooblayout_free,
};
/*
* ecc bits: 0xC0[4,6]
* [0x0], No bit errors were detected;
* [0x001, 0x011], Bit errors were detected and corrected. Not
* reach Flipping Bits;
* [0x100], Bit error count equals the bit flip
* detectionthreshold
* [0x101, 0x110], Reserved;
* [0x111], Multiple bit errors were detected and
* not corrected.
*/
static int fm25g0xd_ecc_get_status(struct spinand_device *spinand,
u8 status)
{
struct nand_device *nand = spinand_to_nand(spinand);
u8 eccsr = (status & GENMASK(6, 4)) >> 4;
if (eccsr <= 3)
return 0;
else if (eccsr == 4)
return nanddev_get_ecc_requirements(nand)->strength;
else
return -EBADMSG;
}
static const struct spinand_info fmsh_spinand_table[] = {
SPINAND_INFO("FM25S01A",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4),
@@ -151,6 +206,24 @@ static const struct spinand_info fmsh_spinand_table[] = {
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&fm25s01_ooblayout, fm25s01bi3_ecc_ecc_get_status)),
SPINAND_INFO("FM25S02BI3-DND-A-G3",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD6),
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&fm25s01_ooblayout, fm25s01bi3_ecc_ecc_get_status)),
SPINAND_INFO("FM25G02D",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF2),
NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(4, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&fm25g0xd_ooblayout, fm25g0xd_ecc_get_status)),
};
static const struct spinand_manufacturer_ops fmsh_spinand_manuf_ops = {

69
drivers/mtd/nand/spi/foresee.c
View File

@@ -51,6 +51,57 @@ static const struct mtd_ooblayout_ops fsxxndxxg_ooblayout = {
.free = fsxxndxxg_ooblayout_free,
};
static int f35sqb00xg_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section > 0)
return -ERANGE;
region->offset = mtd->oobsize / 2;
region->length = mtd->oobsize / 2;
return 0;
}
static int f35sqb00xg_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
return -ERANGE;
/* 2 bytes reserved for BBM */
region->offset = 2;
region->length = mtd->oobsize / 2 - 2;
return 0;
}
static const struct mtd_ooblayout_ops f35sqb00xg_ooblayout = {
.ecc = f35sqb00xg_ooblayout_ecc,
.free = f35sqb00xg_ooblayout_free,
};
/*
* ecc bits: 0xC0[4,6]
* [0b000], No bit errors were detected;
* [0b001, 0b101], 3~7 Bit errors were detected and corrected. Not
* reach Flipping Bits;
* [0b110], Bit error count equals the bit flip detection threshold
* [0b111], Bit errors greater than ECC capability(8 bits) and not corrected;
*/
static int f35sqb00xg_ecc_get_status(struct spinand_device *spinand, u8 status)
{
struct nand_device *nand = spinand_to_nand(spinand);
u8 eccsr = (status & GENMASK(6, 4)) >> 4;
if (eccsr < 6)
return 0;
else if (eccsr == 6)
return nanddev_get_ecc_requirements(nand)->strength;
else
return -EBADMSG;
}
static const struct spinand_info foresee_spinand_table[] = {
SPINAND_INFO("FS35ND01G-S1Y2",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEA),
@@ -133,6 +184,24 @@ static const struct spinand_info foresee_spinand_table[] = {
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&fsxxndxxg_ooblayout, NULL)),
SPINAND_INFO("F35SQB004G",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x53),
NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&f35sqb00xg_ooblayout, f35sqb00xg_ecc_get_status)),
SPINAND_INFO("F35SQB002G",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),
NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&fsxxndxxg_ooblayout, f35sqb00xg_ecc_get_status)),
};
static const struct spinand_manufacturer_ops foresee_spinand_manuf_ops = {

47
drivers/mtd/nand/spi/gsto.c
View File

@@ -57,6 +57,35 @@ static const struct mtd_ooblayout_ops gss0xgsak1_ooblayout = {
.free = gss0xgsak1_ooblayout_free,
};
static int gss0xgsax1_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
return -ERANGE;
region->offset = 64;
region->length = 64;
return 0;
}
static int gss0xgsax1_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
return -ERANGE;
region->offset = 2;
region->length = 62;
return 0;
}
static const struct mtd_ooblayout_ops gss0xgsax1_ooblayout = {
.ecc = gss0xgsax1_ooblayout_ecc,
.free = gss0xgsax1_ooblayout_free,
};
static const struct spinand_info gsto_spinand_table[] = {
SPINAND_INFO("GSS01GSAK1",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBA, 0x13),
@@ -76,6 +105,24 @@ static const struct spinand_info gsto_spinand_table[] = {
&update_cache_variants),
0,
SPINAND_ECCINFO(&gss0xgsak1_ooblayout, NULL)),
SPINAND_INFO("GSS02GSAX1",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCA),
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&gss0xgsax1_ooblayout, NULL)),
SPINAND_INFO("GSS01GSAX1",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCA),
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&gss0xgsax1_ooblayout, NULL)),
};
static const struct spinand_manufacturer_ops gsto_spinand_manuf_ops = {

81
drivers/mtd/nand/spi/hiksemi.c Normal file
View File

@@ -0,0 +1,81 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd
*
* Authors:
* Dingqiang Lin <jon.lin@rock-chips.com>
*/
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/mtd/spinand.h>
#define SPINAND_MFR_HIKSEMI 0x52
static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
static SPINAND_OP_VARIANTS(write_cache_variants,
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
SPINAND_PROG_LOAD(true, 0, NULL, 0));
static SPINAND_OP_VARIANTS(update_cache_variants,
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
static int hsesyhdswxg_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
return -ERANGE;
region->offset = 64;
region->length = 64;
return 0;
}
static int hsesyhdswxg_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
return -ERANGE;
region->offset = 2;
region->length = 62;
return 0;
}
static const struct mtd_ooblayout_ops hsesyhdswxg_ooblayout = {
.ecc = hsesyhdswxg_ooblayout_ecc,
.free = hsesyhdswxg_ooblayout_free,
};
static const struct spinand_info hiksemi_spinand_table[] = {
SPINAND_INFO("HSESYHDSW2G",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD2),
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(4, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&hsesyhdswxg_ooblayout, NULL)),
};
static const struct spinand_manufacturer_ops hiksemi_spinand_manuf_ops = {
};
const struct spinand_manufacturer hiksemi_spinand_manufacturer = {
.id = SPINAND_MFR_HIKSEMI,
.name = "HIKSEMI",
.chips = hiksemi_spinand_table,
.nchips = ARRAY_SIZE(hiksemi_spinand_table),
.ops = &hiksemi_spinand_manuf_ops,
};

42
drivers/mtd/nand/spi/unim.c
View File

@@ -159,6 +159,30 @@ static int um19axxisw_ecc_ecc_get_status(struct spinand_device *spinand,
return -EBADMSG;
}
/*
* ecc bits: 0xC0[4,5]
* 0b00, No bit errors were detected
* 0b01, Bit errors were detected and corrected.
* 0b10, Multiple bit errors were detected and not corrected.
* 0b11, Bits errors were detected and corrected, bit error count
* reach the bit flip detection threshold
*/
static int um19a9xisw_ecc_get_status(struct spinand_device *spinand,
u8 status)
{
struct nand_device *nand = spinand_to_nand(spinand);
switch (status & STATUS_ECC_MASK) {
case STATUS_ECC_NO_BITFLIPS:
case STATUS_ECC_HAS_BITFLIPS:
return 0;
case STATUS_ECC_UNCOR_ERROR:
return -EBADMSG;
default:
return nanddev_get_ecc_requirements(nand)->strength;
}
}
static const struct spinand_info unim_zl_spinand_table[] = {
SPINAND_INFO("TX25G01",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF1),
@@ -208,6 +232,24 @@ static const struct spinand_info unim_spinand_table[] = {
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&um19a1xisw_ooblayout, um19axxisw_ecc_ecc_get_status)),
SPINAND_INFO("UM19A9LISW",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x0D),
NAND_MEMORG(1, 2048, 128, 64, 512, 10, 1, 1, 1),
NAND_ECCREQ(4, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&um19a1xisw_ooblayout, um19a9xisw_ecc_get_status)),
SPINAND_INFO("UM19A9HISW",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x0C),
NAND_MEMORG(1, 2048, 128, 64, 512, 10, 1, 1, 1),
NAND_ECCREQ(4, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&um19a1xisw_ooblayout, um19a9xisw_ecc_get_status)),
};
static const struct spinand_manufacturer_ops unim_spinand_manuf_ops = {

15
drivers/mtd/nand/spi/winbond.c
View File

@@ -216,6 +216,15 @@ static const struct spinand_info winbond_spinand_table[] = {
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
SPINAND_INFO("W25N01KWZPIG",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBE),
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(4, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
};
static int winbond_spinand_init(struct spinand_device *spinand)
@@ -233,6 +242,12 @@ static int winbond_spinand_init(struct spinand_device *spinand)
WINBOND_CFG_BUF_READ);
}
/* W25N01JWZEIG enable continuous read */
if (spinand->id.data[1] == 0xaa && spinand->id.data[2] == 0x21) {
spinand_upd_cfg(spinand, BIT(3), BIT(3));
dev_info(&spinand->spimem->spi->dev, "Enable buf_read\n");
}
return 0;
}

18
drivers/mtd/nand/spi/xtx.c
View File

@@ -386,6 +386,24 @@ static const struct spinand_info xtx_spinand_table[] = {
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)),
SPINAND_INFO("XT26Q04DWSIGT-B",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x53),
NAND_MEMORG(1, 4096, 128, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(14, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)),
SPINAND_INFO("XT26Q01DWSIGA",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)),
};
static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = {

77
drivers/mtd/nand/spi/zbit.c Normal file
View File

@@ -0,0 +1,77 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd
*
* Authors:
* Dingqiang Lin <jon.lin@rock-chips.com>
*/
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/mtd/spinand.h>
#define SPINAND_MFR_ZBIT 0x5E
#define ZBIT_STATUS_ECC_HAS_BITFLIPS_T (3 << 4)
static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
static SPINAND_OP_VARIANTS(write_cache_variants,
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
SPINAND_PROG_LOAD(true, 0, NULL, 0));
static SPINAND_OP_VARIANTS(update_cache_variants,
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
static int zb35q01b_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
return -ERANGE;
}
static int zb35q01b_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
return -ERANGE;
/* Reserve 2 bytes for the BBM. */
region->offset = 2;
region->length = mtd->oobsize - 2;
return 0;
}
static const struct mtd_ooblayout_ops zb35q01b_ooblayout = {
.ecc = zb35q01b_ooblayout_ecc,
.free = zb35q01b_ooblayout_free,
};
static const struct spinand_info zbit_spinand_table[] = {
SPINAND_INFO("ZB35Q01BYIG",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA1),
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&zb35q01b_ooblayout, NULL)),
};
static const struct spinand_manufacturer_ops zbit_spinand_manuf_ops = {
};
const struct spinand_manufacturer zbit_spinand_manufacturer = {
.id = SPINAND_MFR_ZBIT,
.name = "ZBIT",
.chips = zbit_spinand_table,
.nchips = ARRAY_SIZE(zbit_spinand_table),
.ops = &zbit_spinand_manuf_ops,
};

2
drivers/mtd/spi-nor/eon.c
View File

@@ -29,6 +29,8 @@ static const struct flash_info eon_nor_parts[] = {
PARSE_SFDP },
{ "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128)
NO_SFDP_FLAGS(SECT_4K) },
{ "en25qx128a", INFO(0x1c7118, 0, 64 * 1024, 256)
NO_SFDP_FLAGS(SECT_4K) },
};
const struct spi_nor_manufacturer spi_nor_eon = {

3
drivers/mtd/spi-nor/xtx.c
View File

@@ -23,6 +23,9 @@ static const struct flash_info xtx_parts[] = {
{ "xt25f256b", INFO(0x0b4019, 0, 64 * 1024, 512)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ) },
{ "xt25q256f", INFO(0x0b6019, 0, 64 * 1024, 512)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ) },
};
const struct spi_nor_manufacturer spi_nor_xtx = {

27
drivers/soc/rockchip/rockchip_opp_select.c
View File

@@ -1389,8 +1389,10 @@ static void rockchip_init_pvtpll_table(struct device *dev,
of_node_put(clkspec.np);
res = sip_smc_get_pvtpll_info(PVTPLL_GET_INFO, info->pvtpll_clk_id);
if (res.a0)
if (res.a0) {
info->pvtpll_clk_id = UINT_MAX;
goto out;
}
if (!res.a1)
info->pvtpll_low_temp = true;
@@ -1695,6 +1697,7 @@ int rockchip_init_opp_info(struct device *dev, struct rockchip_opp_info *info,
info->bin = -EINVAL;
info->process = -EINVAL;
info->volt_sel = -EINVAL;
info->pvtpll_clk_id = UINT_MAX;
info->is_runtime_active = true;
mutex_init(&info->dvfs_mutex);
@@ -2055,12 +2058,34 @@ static int rockchip_opp_parse_supplies(struct device *dev,
return 0;
}
static int rockchip_pvtpll_set_volt_sel(struct device *dev,
struct rockchip_opp_info *info)
{
struct arm_smccc_res res;
if (!info)
return 0;
if (info->volt_sel < 0)
return 0;
if (info->pvtpll_clk_id == UINT_MAX)
return 0;
res = sip_smc_pvtpll_config(PVTPLL_VOLT_SEL, info->pvtpll_clk_id,
(u32)info->volt_sel, 0, 0, 0, 0);
if (res.a0)
dev_err(dev, "%s: error cfg clk_id=%u voltsel (%d)\n", __func__,
info->pvtpll_clk_id, (int)res.a0);
return 0;
}
int rockchip_adjust_opp_table(struct device *dev, struct rockchip_opp_info *info)
{
rockchip_opp_parse_supplies(dev, info);
rockchip_adjust_power_scale(dev, info);
rockchip_pvtpll_calibrate_opp(info);
rockchip_pvtpll_add_length(info);
rockchip_pvtpll_set_volt_sel(dev, info);
return 0;
}

2
include/linux/mtd/spinand.h
View File

@@ -270,6 +270,7 @@ extern const struct spinand_manufacturer fmsh_spinand_manufacturer;
extern const struct spinand_manufacturer foresee_spinand_manufacturer;
extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
extern const struct spinand_manufacturer gsto_spinand_manufacturer;
extern const struct spinand_manufacturer hiksemi_spinand_manufacturer;
extern const struct spinand_manufacturer hyf_spinand_manufacturer;
extern const struct spinand_manufacturer jsc_spinand_manufacturer;
extern const struct spinand_manufacturer macronix_spinand_manufacturer;
@@ -283,6 +284,7 @@ extern const struct spinand_manufacturer unim_zl_spinand_manufacturer;
extern const struct spinand_manufacturer winbond_spinand_manufacturer;
extern const struct spinand_manufacturer xincun_spinand_manufacturer;
extern const struct spinand_manufacturer xtx_spinand_manufacturer;
extern const struct spinand_manufacturer zbit_spinand_manufacturer;
/**
* struct spinand_op_variants - SPI NAND operation variants

1
include/linux/rockchip/rockchip_sip.h
View File

@@ -239,6 +239,7 @@ enum {
PVTPLL_GET_INFO = 0,
PVTPLL_ADJUST_TABLE = 1,
PVTPLL_LOW_TEMP = 2,
PVTPLL_VOLT_SEL = 3,
};
struct pt_regs;