From 47dc4814190410ed5f5a7d694170c5005ac92406 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Thu, 5 Sep 2024 16:18:54 +0800 Subject: [PATCH 01/25] media: rockchip: vicap support to select sensor setting with thunderboot mode Signed-off-by: Zefa Chen Change-Id: I538d9a20f41b975dec303be60d1bb2b021fd6e57 --- .../media/platform/rockchip/cif/subdev-itf.c | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/media/platform/rockchip/cif/subdev-itf.c b/drivers/media/platform/rockchip/cif/subdev-itf.c index 0620e60c0784..d76cd43938e7 100644 --- a/drivers/media/platform/rockchip/cif/subdev-itf.c +++ b/drivers/media/platform/rockchip/cif/subdev-itf.c @@ -23,6 +23,7 @@ #include #include #include "common.h" +#include "../../../i2c/cam-tb-setup.h" static inline struct sditf_priv *to_sditf_priv(struct v4l2_subdev *subdev) { @@ -377,6 +378,79 @@ static void sditf_reinit_mode(struct sditf_priv *priv, struct rkisp_vicap_mode * __func__, mode->rdbk_mode, mode->name, priv->toisp_inf.link_mode); } +#ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_SETUP +static void sditf_select_sensor_setting_for_thunderboot(struct sditf_priv *priv) +{ + struct rkcif_device *dev = priv->cif_dev; + struct v4l2_subdev_format fmt; + struct rk_sensor_setting sensor_setting = {0}; + struct v4l2_subdev_frame_interval fi = {0}; + struct rkmodule_hdr_cfg hdr_cfg; + int width = 0; + int height = 0; + int hdr_mode = 0; + int max_fps = 0; + int ret = 0; + bool is_match = false; + + if (!dev->terminal_sensor.sd) + rkcif_update_sensor_info(&dev->stream[0]); + if (dev->terminal_sensor.sd) { + if (priv->mode.dev_id == 0) { + width = get_rk_cam_w(); + height = get_rk_cam_h(); + hdr_mode = get_rk_cam_hdr(); + max_fps = get_rk_cam1_max_fps(); + } else { + width = get_rk_cam2_w(); + height = get_rk_cam2_h(); + hdr_mode = get_rk_cam2_hdr(); + max_fps = get_rk_cam2_max_fps(); + } + fmt.pad = 0; + fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; + fmt.reserved[0] = 0; + fmt.format.field = V4L2_FIELD_NONE; + ret = v4l2_subdev_call(dev->terminal_sensor.sd, pad, get_fmt, NULL, &fmt); + if (!ret) { + if (dev->rdbk_debug) + v4l2_info(&dev->v4l2_dev, + "cmdline get %dx%d@%dfps, hdr_mode %d\n", + width, height, max_fps, hdr_mode); + sensor_setting.fmt = fmt.format.code; + sensor_setting.width = width; + sensor_setting.height = height; + sensor_setting.mode = hdr_mode; + sensor_setting.fps = max_fps; + ret = v4l2_subdev_call(dev->terminal_sensor.sd, + core, ioctl, + RKCIS_CMD_SELECT_SETTING, + &sensor_setting); + if (!ret) + is_match = true; + } + if (!is_match) { + fmt.format.width = width; + fmt.format.height = height; + v4l2_subdev_call(dev->terminal_sensor.sd, pad, set_fmt, NULL, &fmt); + v4l2_subdev_call(dev->terminal_sensor.sd, video, g_frame_interval, &fi); + fi.interval.numerator = 1; + fi.interval.denominator = max_fps; + v4l2_subdev_call(dev->terminal_sensor.sd, video, s_frame_interval, &fi); + v4l2_subdev_call(dev->terminal_sensor.sd, + core, ioctl, + RKMODULE_GET_HDR_CFG, + &hdr_cfg); + hdr_cfg.hdr_mode = hdr_mode; + v4l2_subdev_call(dev->terminal_sensor.sd, + core, ioctl, + RKMODULE_SET_HDR_CFG, + &hdr_cfg); + } + } +} +#endif + static void sditf_enable_immediately(struct sditf_priv *priv); static long sditf_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) { @@ -429,6 +503,10 @@ static long sditf_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) mode->input.multi_sync = 0; else mode->input.multi_sync = 1; +#ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_SETUP + if (cif_dev->is_thunderboot) + sditf_select_sensor_setting_for_thunderboot(priv); +#endif return 0; case RKISP_VICAP_CMD_INIT_BUF: pisp_buf_info = (struct rkisp_init_buf *)arg; From 84486274f54d563b6067d48e3ab2f160d9bbbb19 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Tue, 5 Nov 2024 17:14:12 +0800 Subject: [PATCH 02/25] media: rockchip: vicap fixes error path of irq register Signed-off-by: Zefa Chen Change-Id: I2ab6627f5d0de93b6c1cd743a86edec699da4c49 --- drivers/media/platform/rockchip/cif/hw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/rockchip/cif/hw.c b/drivers/media/platform/rockchip/cif/hw.c index 13a4a6fc10e7..5b154bef73dd 100644 --- a/drivers/media/platform/rockchip/cif/hw.c +++ b/drivers/media/platform/rockchip/cif/hw.c @@ -1568,8 +1568,8 @@ static int rkcif_plat_hw_probe(struct platform_device *pdev) if (irq < 0) return irq; - if (cif_hw->chip_id == CHIP_RV1106_CIF || - cif_hw->chip_id == CHIP_RV1103B_CIF) { + if (data->chip_id == CHIP_RV1106_CIF || + data->chip_id == CHIP_RV1103B_CIF) { irq_set_status_flags(irq, IRQ_NOAUTOEN); ret = devm_request_irq(dev, irq, rkcif_irq_handler, 0, From 42cb9e9dd8d34aa2f18287d0a860ba15d5e25714 Mon Sep 17 00:00:00 2001 From: Zefa Chen Date: Wed, 6 Nov 2024 15:25:44 +0800 Subject: [PATCH 03/25] media: rockchip: vicap fixes error cnt of line intr line intr trigger by height after crop Signed-off-by: Zefa Chen Change-Id: I03828b88bce2bcd27225f929f4c7bc894137cb70 --- drivers/media/platform/rockchip/cif/subdev-itf.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/rockchip/cif/subdev-itf.c b/drivers/media/platform/rockchip/cif/subdev-itf.c index d76cd43938e7..7cb8a67ea2ae 100644 --- a/drivers/media/platform/rockchip/cif/subdev-itf.c +++ b/drivers/media/platform/rockchip/cif/subdev-itf.c @@ -1253,7 +1253,6 @@ static int sditf_s_rx_buffer(struct v4l2_subdev *sd, { struct sditf_priv *priv = to_sditf_priv(sd); struct rkcif_device *cif_dev = priv->cif_dev; - struct rkcif_sensor_info *sensor = &cif_dev->terminal_sensor; struct rkcif_stream *stream = NULL; struct rkisp_rx_buf *dbufs; struct rkcif_rx_buffer *rx_buf = NULL; @@ -1393,13 +1392,13 @@ static int sditf_s_rx_buffer(struct v4l2_subdev *sd, diff_time = 200000; else diff_time = 1000000; - if (dbufs->runtime_us * 1000 < cif_dev->sensor_linetime * sensor->raw_rect.height && + if (dbufs->runtime_us * 1000 < cif_dev->sensor_linetime * stream->pixm.height && dbufs->runtime_us * 1000 + cif_dev->sensor_linetime > diff_time) early_time = dbufs->runtime_us * 1000 - diff_time; else early_time = diff_time; cif_dev->early_line = div_u64(early_time, cif_dev->sensor_linetime); - cif_dev->wait_line_cache = sensor->raw_rect.height - cif_dev->early_line; + cif_dev->wait_line_cache = stream->pixm.height - cif_dev->early_line; if (cif_dev->rdbk_debug && dbufs->sequence < 15) v4l2_info(&cif_dev->v4l2_dev, @@ -1414,13 +1413,13 @@ static int sditf_s_rx_buffer(struct v4l2_subdev *sd, diff_time = 200000; else diff_time = 1000000; - if (dbufs->runtime_us * 1000 < cif_dev->sensor_linetime * sensor->raw_rect.height && + if (dbufs->runtime_us * 1000 < cif_dev->sensor_linetime * stream->pixm.height && dbufs->runtime_us * 1000 + cif_dev->sensor_linetime > diff_time) early_time = dbufs->runtime_us * 1000 - diff_time; else early_time = diff_time; cif_dev->early_line = div_u64(early_time, cif_dev->sensor_linetime); - cif_dev->wait_line_cache = sensor->raw_rect.height - cif_dev->early_line; + cif_dev->wait_line_cache = stream->pixm.height - cif_dev->early_line; } if (cif_dev->rdbk_debug && dbufs->sequence < 15) From 1d3bcf7c99fbdad1515016898b767828af4ae521 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Mon, 3 Jun 2024 16:04:39 +0800 Subject: [PATCH 04/25] mtd: spinand: fmsh: Support new devices FM25S02BI3-DND-A-G3. Change-Id: I641c71cbd5fe1eff22d504e110ef0670595d9ef2 Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/fmsh.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mtd/nand/spi/fmsh.c b/drivers/mtd/nand/spi/fmsh.c index ef4a586ea50c..428a532d085f 100644 --- a/drivers/mtd/nand/spi/fmsh.c +++ b/drivers/mtd/nand/spi/fmsh.c @@ -151,6 +151,15 @@ static const struct spinand_info fmsh_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&fm25s01_ooblayout, fm25s01bi3_ecc_ecc_get_status)), + SPINAND_INFO("FM25S02BI3-DND-A-G3", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD6), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&fm25s01_ooblayout, fm25s01bi3_ecc_ecc_get_status)), }; static const struct spinand_manufacturer_ops fmsh_spinand_manuf_ops = { From cd25a595d289aaeb5f716483fd8ae994024f2401 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Thu, 7 Nov 2024 10:14:48 +0800 Subject: [PATCH 05/25] mtd: spi-nor: eon: Support en25qx128a Change-Id: I32a4a04947e8fb0128b4aef2e5514933f37615bf Signed-off-by: Jon Lin --- drivers/mtd/spi-nor/eon.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi-nor/eon.c b/drivers/mtd/spi-nor/eon.c index 50a11053711f..9e6f9fc651d5 100644 --- a/drivers/mtd/spi-nor/eon.c +++ b/drivers/mtd/spi-nor/eon.c @@ -29,6 +29,8 @@ static const struct flash_info eon_nor_parts[] = { PARSE_SFDP }, { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128) NO_SFDP_FLAGS(SECT_4K) }, + { "en25qx128a", INFO(0x1c7118, 0, 64 * 1024, 256) + NO_SFDP_FLAGS(SECT_4K) }, }; const struct spi_nor_manufacturer spi_nor_eon = { From e2955302eb498529089a7c8233660b631603d5b9 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Thu, 13 Jun 2024 15:01:36 +0800 Subject: [PATCH 06/25] mtd: spinand: foresee: Support new device F35SQB004G Change-Id: I252c934617d614e4a826ec66b53b305c2732e3b8 Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/foresee.c | 60 ++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/mtd/nand/spi/foresee.c b/drivers/mtd/nand/spi/foresee.c index 403c33157c37..e52623e967e8 100644 --- a/drivers/mtd/nand/spi/foresee.c +++ b/drivers/mtd/nand/spi/foresee.c @@ -51,6 +51,57 @@ static const struct mtd_ooblayout_ops fsxxndxxg_ooblayout = { .free = fsxxndxxg_ooblayout_free, }; +static int f35sqb00xg_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section > 0) + return -ERANGE; + + region->offset = mtd->oobsize / 2; + region->length = mtd->oobsize / 2; + + return 0; +} + +static int f35sqb00xg_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + /* 2 bytes reserved for BBM */ + region->offset = 2; + region->length = mtd->oobsize / 2 - 2; + + return 0; +} + +static const struct mtd_ooblayout_ops f35sqb00xg_ooblayout = { + .ecc = f35sqb00xg_ooblayout_ecc, + .free = f35sqb00xg_ooblayout_free, +}; + +/* + * ecc bits: 0xC0[4,6] + * [0b000], No bit errors were detected; + * [0b001, 0b101], 3~7 Bit errors were detected and corrected. Not + * reach Flipping Bits; + * [0b110], Bit error count equals the bit flip detection threshold + * [0b111], Bit errors greater than ECC capability(8 bits) and not corrected; + */ +static int f35sqb00xg_ecc_get_status(struct spinand_device *spinand, u8 status) +{ + struct nand_device *nand = spinand_to_nand(spinand); + u8 eccsr = (status & GENMASK(6, 4)) >> 4; + + if (eccsr < 6) + return 0; + else if (eccsr == 6) + return nanddev_get_ecc_requirements(nand)->strength; + else + return -EBADMSG; +} + static const struct spinand_info foresee_spinand_table[] = { SPINAND_INFO("FS35ND01G-S1Y2", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEA), @@ -133,6 +184,15 @@ static const struct spinand_info foresee_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&fsxxndxxg_ooblayout, NULL)), + SPINAND_INFO("F35SQB004G", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x53), + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&f35sqb00xg_ooblayout, f35sqb00xg_ecc_get_status)), }; static const struct spinand_manufacturer_ops foresee_spinand_manuf_ops = { From 3aed5bf52d780fbd9a4df111938e8cf1b814125c Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Thu, 4 Jul 2024 16:38:26 +0800 Subject: [PATCH 07/25] mtd: rawnand: rockchip: Reset controller registers during resume process Change-Id: I14f0f9b9ab6635b1649f687dc567e86a8705b39f Signed-off-by: Jon Lin --- drivers/mtd/nand/raw/rockchip-nand-controller.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/rockchip-nand-controller.c b/drivers/mtd/nand/raw/rockchip-nand-controller.c index d8456b849c13..2a2f0b9fc9b9 100644 --- a/drivers/mtd/nand/raw/rockchip-nand-controller.c +++ b/drivers/mtd/nand/raw/rockchip-nand-controller.c @@ -795,8 +795,10 @@ static int rk_nfc_read_page_hwecc(struct nand_chip *chip, u8 *buf, int oob_on, dma_oob); ret = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(100)); - if (!ret) + if (!ret) { + print_hex_dump(KERN_WARNING, "reg:", DUMP_PREFIX_OFFSET, 4, 4, nfc->regs, 0x84, 0); dev_warn(nfc->dev, "read: wait dma done timeout.\n"); + } /* * Whether the DMA transfer is completed or not. The driver * needs to check the NFC`s status register to see if the data @@ -1465,6 +1467,9 @@ static int __maybe_unused rk_nfc_resume(struct device *dev) if (ret) return ret; + rk_nfc_hw_init(nfc); + nfc->cur_ecc = 0; + /* Reset NAND chip if VCC was powered off. */ list_for_each_entry(rknand, &nfc->chips, node) { chip = &rknand->chip; From 1cead8b60e4861214582115c189efc243fb02e3f Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Wed, 17 Jul 2024 14:42:26 +0800 Subject: [PATCH 08/25] mtd: spinand: zbit: Add code Support ZB35Q01BYIG. Change-Id: I03c886d2de63052aff2f3361758ac51d3f9166c6 Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/Makefile | 2 +- drivers/mtd/nand/spi/core.c | 1 + drivers/mtd/nand/spi/zbit.c | 77 +++++++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 1 + 4 files changed, 80 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/nand/spi/zbit.c diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile index 5fb739def8d1..eab7028debb3 100644 --- a/drivers/mtd/nand/spi/Makefile +++ b/drivers/mtd/nand/spi/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -spinand-objs := core.o ato.o gigadevice.o gsto.o macronix.o micron.o paragon.o toshiba.o winbond.o biwin.o dosilicon.o esmt.o etron.o fmsh.o foresee.o hyf.o jsc.o silicongo.o skyhigh.o unim.o xincun.o xtx.o +spinand-objs := core.o ato.o gigadevice.o gsto.o macronix.o micron.o paragon.o toshiba.o winbond.o biwin.o dosilicon.o esmt.o etron.o fmsh.o foresee.o hyf.o jsc.o silicongo.o skyhigh.o unim.o xincun.o xtx.o zbit.o obj-$(CONFIG_MTD_SPI_NAND) += spinand.o diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 50ec3f4ac7c4..21bb68e1bf3c 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -973,6 +973,7 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = { &winbond_spinand_manufacturer, &xincun_spinand_manufacturer, &xtx_spinand_manufacturer, + &zbit_spinand_manufacturer, }; static int spinand_manufacturer_match(struct spinand_device *spinand, diff --git a/drivers/mtd/nand/spi/zbit.c b/drivers/mtd/nand/spi/zbit.c new file mode 100644 index 000000000000..466a67a467b0 --- /dev/null +++ b/drivers/mtd/nand/spi/zbit.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd + * + * Authors: + * Dingqiang Lin + */ + +#include +#include +#include + +#define SPINAND_MFR_ZBIT 0x5E +#define ZBIT_STATUS_ECC_HAS_BITFLIPS_T (3 << 4) + +static SPINAND_OP_VARIANTS(read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + +static SPINAND_OP_VARIANTS(write_cache_variants, + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), + SPINAND_PROG_LOAD(true, 0, NULL, 0)); + +static SPINAND_OP_VARIANTS(update_cache_variants, + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + +static int zb35q01b_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + return -ERANGE; +} + +static int zb35q01b_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + /* Reserve 2 bytes for the BBM. */ + region->offset = 2; + region->length = mtd->oobsize - 2; + + return 0; +} + +static const struct mtd_ooblayout_ops zb35q01b_ooblayout = { + .ecc = zb35q01b_ooblayout_ecc, + .free = zb35q01b_ooblayout_free, +}; + +static const struct spinand_info zbit_spinand_table[] = { + SPINAND_INFO("ZB35Q01BYIG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA1), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&zb35q01b_ooblayout, NULL)), +}; + +static const struct spinand_manufacturer_ops zbit_spinand_manuf_ops = { +}; + +const struct spinand_manufacturer zbit_spinand_manufacturer = { + .id = SPINAND_MFR_ZBIT, + .name = "ZBIT", + .chips = zbit_spinand_table, + .nchips = ARRAY_SIZE(zbit_spinand_table), + .ops = &zbit_spinand_manuf_ops, +}; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 2aef7a9324f8..d80a0e2f1178 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -283,6 +283,7 @@ extern const struct spinand_manufacturer unim_zl_spinand_manufacturer; extern const struct spinand_manufacturer winbond_spinand_manufacturer; extern const struct spinand_manufacturer xincun_spinand_manufacturer; extern const struct spinand_manufacturer xtx_spinand_manufacturer; +extern const struct spinand_manufacturer zbit_spinand_manufacturer; /** * struct spinand_op_variants - SPI NAND operation variants From 607197353eec000d05cf533428b290776442136d Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Wed, 21 Aug 2024 10:49:44 +0800 Subject: [PATCH 09/25] mtd: spinand: Winbond: Support new device W25N01KWZPIG Change-Id: Ie6a672a9279413bcb2298f92f0a65656dd809645 Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/winbond.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 8eff6cb39eeb..96681c24a9af 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -216,6 +216,15 @@ static const struct spinand_info winbond_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)), + SPINAND_INFO("W25N01KWZPIG", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBE), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)), }; static int winbond_spinand_init(struct spinand_device *spinand) From 1267238e655e5b6a1a522adf1672186b40a394d2 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Wed, 21 Aug 2024 11:15:59 +0800 Subject: [PATCH 10/25] mtd: spinand: UNIM: Support new device UM19A9LISW and UM19A9HISW Change-Id: Iaa8a7c35590224ad6956009c8768c6469c91f3a9 Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/unim.c | 42 +++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/mtd/nand/spi/unim.c b/drivers/mtd/nand/spi/unim.c index 75a1912a23a3..0650290cf358 100644 --- a/drivers/mtd/nand/spi/unim.c +++ b/drivers/mtd/nand/spi/unim.c @@ -159,6 +159,30 @@ static int um19axxisw_ecc_ecc_get_status(struct spinand_device *spinand, return -EBADMSG; } +/* + * ecc bits: 0xC0[4,5] + * 0b00, No bit errors were detected + * 0b01, Bit errors were detected and corrected. + * 0b10, Multiple bit errors were detected and not corrected. + * 0b11, Bits errors were detected and corrected, bit error count + * reach the bit flip detection threshold + */ +static int um19a9xisw_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + struct nand_device *nand = spinand_to_nand(spinand); + + switch (status & STATUS_ECC_MASK) { + case STATUS_ECC_NO_BITFLIPS: + case STATUS_ECC_HAS_BITFLIPS: + return 0; + case STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; + default: + return nanddev_get_ecc_requirements(nand)->strength; + } +} + static const struct spinand_info unim_zl_spinand_table[] = { SPINAND_INFO("TX25G01", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF1), @@ -208,6 +232,24 @@ static const struct spinand_info unim_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&um19a1xisw_ooblayout, um19axxisw_ecc_ecc_get_status)), + SPINAND_INFO("UM19A9LISW", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x0D), + NAND_MEMORG(1, 2048, 128, 64, 512, 10, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&um19a1xisw_ooblayout, um19a9xisw_ecc_get_status)), + SPINAND_INFO("UM19A9HISW", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x0C), + NAND_MEMORG(1, 2048, 128, 64, 512, 10, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&um19a1xisw_ooblayout, um19a9xisw_ecc_get_status)), }; static const struct spinand_manufacturer_ops unim_spinand_manuf_ops = { From 271daa37216fca868788fafb4dbc4033c5a67adc Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Wed, 21 Aug 2024 11:29:52 +0800 Subject: [PATCH 11/25] mtd: spinand: xtx: Support new device XT26Q04DWSIGT-B Change-Id: Ia146c4a53fa574f512c078594578c12704586945 Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/xtx.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mtd/nand/spi/xtx.c b/drivers/mtd/nand/spi/xtx.c index 90f55b091d19..4500d93aee9b 100644 --- a/drivers/mtd/nand/spi/xtx.c +++ b/drivers/mtd/nand/spi/xtx.c @@ -386,6 +386,15 @@ static const struct spinand_info xtx_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)), + SPINAND_INFO("XT26Q04DWSIGT-B", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x53), + NAND_MEMORG(1, 4096, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(14, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)), }; static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = { From 55568a9c758564a544ee2af14441d7cd600d9f75 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Wed, 21 Aug 2024 11:41:58 +0800 Subject: [PATCH 12/25] mtd: spinand: fmsh: Support new device FM25G02D Change-Id: I3a0d5c609f7cc01ce48f734ae58f20c4112828eb Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/fmsh.c | 64 +++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/mtd/nand/spi/fmsh.c b/drivers/mtd/nand/spi/fmsh.c index 428a532d085f..07818c692006 100644 --- a/drivers/mtd/nand/spi/fmsh.c +++ b/drivers/mtd/nand/spi/fmsh.c @@ -105,6 +105,61 @@ static int fm25s01bi3_ecc_ecc_get_status(struct spinand_device *spinand, return -EBADMSG; } +static int fm25g0xd_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = 64; + region->length = 64; + + return 0; +} + +static int fm25g0xd_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + /* Reserve 2 bytes for the BBM. */ + region->offset = 2; + region->length = 62; + + return 0; +} + +static const struct mtd_ooblayout_ops fm25g0xd_ooblayout = { + .ecc = fm25g0xd_ooblayout_ecc, + .free = fm25g0xd_ooblayout_free, +}; + +/* + * ecc bits: 0xC0[4,6] + * [0x0], No bit errors were detected; + * [0x001, 0x011], Bit errors were detected and corrected. Not + * reach Flipping Bits; + * [0x100], Bit error count equals the bit flip + * detectionthreshold + * [0x101, 0x110], Reserved; + * [0x111], Multiple bit errors were detected and + * not corrected. + */ +static int fm25g0xd_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + struct nand_device *nand = spinand_to_nand(spinand); + u8 eccsr = (status & GENMASK(6, 4)) >> 4; + + if (eccsr <= 3) + return 0; + else if (eccsr == 4) + return nanddev_get_ecc_requirements(nand)->strength; + else + return -EBADMSG; +} + static const struct spinand_info fmsh_spinand_table[] = { SPINAND_INFO("FM25S01A", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4), @@ -160,6 +215,15 @@ static const struct spinand_info fmsh_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&fm25s01_ooblayout, fm25s01bi3_ecc_ecc_get_status)), + SPINAND_INFO("FM25G02D", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF2), + NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&fm25g0xd_ooblayout, fm25g0xd_ecc_get_status)), }; static const struct spinand_manufacturer_ops fmsh_spinand_manuf_ops = { From 3fd41c6a82b75cec8b2f297a9d5102fadd52d3a5 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Tue, 10 Sep 2024 18:02:28 +0800 Subject: [PATCH 13/25] mtd: spinand: Winbond: Set W25N01KWZPIG buffer read Change-Id: I10ed4747df9412af3a826c94822fe68dc3ead705 Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/winbond.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 96681c24a9af..b6eac0bf706a 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -242,6 +242,12 @@ static int winbond_spinand_init(struct spinand_device *spinand) WINBOND_CFG_BUF_READ); } + /* W25N01JWZEIG enable continuous read */ + if (spinand->id.data[1] == 0xaa && spinand->id.data[2] == 0x21) { + spinand_upd_cfg(spinand, BIT(3), BIT(3)); + dev_info(&spinand->spimem->spi->dev, "Enable buf_read\n"); + } + return 0; } From 16c25d539eee610348885c16c61be5937aa999bd Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Thu, 7 Nov 2024 10:21:19 +0800 Subject: [PATCH 14/25] mtd: spi-nor: xtx: Support xt25q256f Change-Id: Iebf4baf5e7c8dc8c4e4b318def3c0eee03b08ea2 Signed-off-by: Jon Lin --- drivers/mtd/spi-nor/xtx.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/spi-nor/xtx.c b/drivers/mtd/spi-nor/xtx.c index 3f064e58e0fa..24e032e271e3 100644 --- a/drivers/mtd/spi-nor/xtx.c +++ b/drivers/mtd/spi-nor/xtx.c @@ -23,6 +23,9 @@ static const struct flash_info xtx_parts[] = { { "xt25f256b", INFO(0x0b4019, 0, 64 * 1024, 512) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { "xt25q256f", INFO(0x0b6019, 0, 64 * 1024, 512) + NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | + SPI_NOR_QUAD_READ) }, }; const struct spi_nor_manufacturer spi_nor_xtx = { From afba0edeb60931e371b14cf6d7e14ef111de72da Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Sat, 14 Sep 2024 17:24:45 +0800 Subject: [PATCH 15/25] mtd: spinand: xtx: Support new device XT26Q01DWSIGA Change-Id: Ibc2a2e0e9eae9520f57b4bbf239232be85418cee Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/xtx.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mtd/nand/spi/xtx.c b/drivers/mtd/nand/spi/xtx.c index 4500d93aee9b..ee705de096c9 100644 --- a/drivers/mtd/nand/spi/xtx.c +++ b/drivers/mtd/nand/spi/xtx.c @@ -395,6 +395,15 @@ static const struct spinand_info xtx_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)), + SPINAND_INFO("XT26Q01DWSIGA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)), }; static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = { From 21b62edb4b7f5d2fd6f0a0920cf27414fd6b8fd8 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Sat, 14 Sep 2024 17:33:38 +0800 Subject: [PATCH 16/25] mtd: spinand: GSTO: Support new device GSS01GSAX1 and GSS02GSAX1 Change-Id: I898bcc599fe338ef71012de0b170d08c888644bc Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/gsto.c | 47 +++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/mtd/nand/spi/gsto.c b/drivers/mtd/nand/spi/gsto.c index fc4098e22b38..56c0dcbbd0be 100644 --- a/drivers/mtd/nand/spi/gsto.c +++ b/drivers/mtd/nand/spi/gsto.c @@ -57,6 +57,35 @@ static const struct mtd_ooblayout_ops gss0xgsak1_ooblayout = { .free = gss0xgsak1_ooblayout_free, }; +static int gss0xgsax1_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = 64; + region->length = 64; + + return 0; +} + +static int gss0xgsax1_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = 2; + region->length = 62; + + return 0; +} + +static const struct mtd_ooblayout_ops gss0xgsax1_ooblayout = { + .ecc = gss0xgsax1_ooblayout_ecc, + .free = gss0xgsax1_ooblayout_free, +}; + static const struct spinand_info gsto_spinand_table[] = { SPINAND_INFO("GSS01GSAK1", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBA, 0x13), @@ -76,6 +105,24 @@ static const struct spinand_info gsto_spinand_table[] = { &update_cache_variants), 0, SPINAND_ECCINFO(&gss0xgsak1_ooblayout, NULL)), + SPINAND_INFO("GSS02GSAX1", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCA), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&gss0xgsax1_ooblayout, NULL)), + SPINAND_INFO("GSS01GSAX1", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCA), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&gss0xgsax1_ooblayout, NULL)), }; static const struct spinand_manufacturer_ops gsto_spinand_manuf_ops = { From 4e64a24d6238411f8210a14d5b6e03191019f725 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Tue, 22 Oct 2024 22:14:44 +0800 Subject: [PATCH 17/25] mtd: spinand: HIKSEMI: Support new device HSESYHDSW2G Change-Id: I5ff5e791412d3d81296c8c806145b88da6545cae Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/Makefile | 2 +- drivers/mtd/nand/spi/core.c | 1 + drivers/mtd/nand/spi/hiksemi.c | 81 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 1 + 4 files changed, 84 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/nand/spi/hiksemi.c diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile index eab7028debb3..b28cdffeaa6d 100644 --- a/drivers/mtd/nand/spi/Makefile +++ b/drivers/mtd/nand/spi/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -spinand-objs := core.o ato.o gigadevice.o gsto.o macronix.o micron.o paragon.o toshiba.o winbond.o biwin.o dosilicon.o esmt.o etron.o fmsh.o foresee.o hyf.o jsc.o silicongo.o skyhigh.o unim.o xincun.o xtx.o zbit.o +spinand-objs := core.o ato.o gigadevice.o gsto.o macronix.o micron.o paragon.o toshiba.o winbond.o biwin.o dosilicon.o esmt.o etron.o fmsh.o foresee.o hiksemi.o hyf.o jsc.o silicongo.o skyhigh.o unim.o xincun.o xtx.o zbit.o obj-$(CONFIG_MTD_SPI_NAND) += spinand.o diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 21bb68e1bf3c..a46142634b1c 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -960,6 +960,7 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = { &foresee_spinand_manufacturer, &gigadevice_spinand_manufacturer, &gsto_spinand_manufacturer, + &hiksemi_spinand_manufacturer, &hyf_spinand_manufacturer, &jsc_spinand_manufacturer, ¯onix_spinand_manufacturer, diff --git a/drivers/mtd/nand/spi/hiksemi.c b/drivers/mtd/nand/spi/hiksemi.c new file mode 100644 index 000000000000..a1d8236a7888 --- /dev/null +++ b/drivers/mtd/nand/spi/hiksemi.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd + * + * Authors: + * Dingqiang Lin + */ + +#include +#include +#include + +#define SPINAND_MFR_HIKSEMI 0x52 + +static SPINAND_OP_VARIANTS(read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + +static SPINAND_OP_VARIANTS(write_cache_variants, + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), + SPINAND_PROG_LOAD(true, 0, NULL, 0)); + +static SPINAND_OP_VARIANTS(update_cache_variants, + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + +static int hsesyhdswxg_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = 64; + region->length = 64; + + return 0; +} + +static int hsesyhdswxg_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = 2; + region->length = 62; + + return 0; +} + +static const struct mtd_ooblayout_ops hsesyhdswxg_ooblayout = { + .ecc = hsesyhdswxg_ooblayout_ecc, + .free = hsesyhdswxg_ooblayout_free, +}; + +static const struct spinand_info hiksemi_spinand_table[] = { + SPINAND_INFO("HSESYHDSW2G", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD2), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&hsesyhdswxg_ooblayout, NULL)), +}; + +static const struct spinand_manufacturer_ops hiksemi_spinand_manuf_ops = { +}; + +const struct spinand_manufacturer hiksemi_spinand_manufacturer = { + .id = SPINAND_MFR_HIKSEMI, + .name = "HIKSEMI", + .chips = hiksemi_spinand_table, + .nchips = ARRAY_SIZE(hiksemi_spinand_table), + .ops = &hiksemi_spinand_manuf_ops, +}; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index d80a0e2f1178..861ce3ee6ef0 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -270,6 +270,7 @@ extern const struct spinand_manufacturer fmsh_spinand_manufacturer; extern const struct spinand_manufacturer foresee_spinand_manufacturer; extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; extern const struct spinand_manufacturer gsto_spinand_manufacturer; +extern const struct spinand_manufacturer hiksemi_spinand_manufacturer; extern const struct spinand_manufacturer hyf_spinand_manufacturer; extern const struct spinand_manufacturer jsc_spinand_manufacturer; extern const struct spinand_manufacturer macronix_spinand_manufacturer; From 049d5bbd60d8ce9a994f51550ec7e59fd1e56acf Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Tue, 22 Oct 2024 22:17:10 +0800 Subject: [PATCH 18/25] mtd: spinand: foresee: Support new device F35SQB002G Change-Id: Ib7aef1f2e4a68925e30dcab8b8bfd76996820437 Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/foresee.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mtd/nand/spi/foresee.c b/drivers/mtd/nand/spi/foresee.c index e52623e967e8..87f17f1d4252 100644 --- a/drivers/mtd/nand/spi/foresee.c +++ b/drivers/mtd/nand/spi/foresee.c @@ -193,6 +193,15 @@ static const struct spinand_info foresee_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&f35sqb00xg_ooblayout, f35sqb00xg_ecc_get_status)), + SPINAND_INFO("F35SQB002G", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52), + NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&fsxxndxxg_ooblayout, f35sqb00xg_ecc_get_status)), }; static const struct spinand_manufacturer_ops foresee_spinand_manuf_ops = { From 4cbd30a423866bbb0c8230a008baf3ceb322fa92 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Tue, 22 Oct 2024 22:18:49 +0800 Subject: [PATCH 19/25] mtd: spinand: dosilicon: Support new device DS35Q2GBS Change-Id: I40b452063b71b9407eda1fd7b134585f6a7823dc Signed-off-by: Jon Lin --- drivers/mtd/nand/spi/dosilicon.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mtd/nand/spi/dosilicon.c b/drivers/mtd/nand/spi/dosilicon.c index 4b3034abcfb6..8bc660579101 100644 --- a/drivers/mtd/nand/spi/dosilicon.c +++ b/drivers/mtd/nand/spi/dosilicon.c @@ -258,6 +258,15 @@ static const struct spinand_info dosilicon_spinand_table[] = { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), + SPINAND_INFO("DS35Q2GBS", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ds35xxgb_ooblayout, ds35xxgb_ecc_get_status)), }; static const struct spinand_manufacturer_ops dosilicon_spinand_manuf_ops = { From 4ae43cfd70808a51912676119d8ec4549fbe45d5 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Mon, 14 Oct 2024 09:36:12 +0800 Subject: [PATCH 20/25] arm64: dts: rockchip: rk3576: Add opp table rk3576j/m Change-Id: I4b06f3f7ee4b515a1933e30b6ce385de4312516d Signed-off-by: Finley Xiao --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 500 +++++++++++++++++++++-- 1 file changed, 460 insertions(+), 40 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 68c8fef38576..010b3aa1693c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -400,6 +400,20 @@ nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; rockchip,supported-hw; + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = < + 0 1744 0 + 1745 1774 1 + 1775 1804 2 + 1805 1839 3 + 1840 1874 4 + 1875 1909 5 + 1910 1949 6 + 1950 1989 7 + 1990 2029 8 + 2030 2069 9 + 2070 9999 10 + >; rockchip,pvtm-voltage-sel = < 0 1764 0 1765 1789 1 @@ -439,32 +453,32 @@ rockchip,low-temp-min-volt = <800000>; opp-408000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <408000000>; opp-microvolt = <712500 712500 950000>; clock-latency-ns = <40000>; }; opp-600000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <600000000>; opp-microvolt = <712500 712500 950000>; clock-latency-ns = <40000>; }; opp-816000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <816000000>; opp-microvolt = <712500 712500 950000>; clock-latency-ns = <40000>; }; opp-1008000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <712500 712500 950000>; opp-microvolt-L0 = <725000 725000 950000>; clock-latency-ns = <40000>; }; opp-1200000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <712500 712500 950000>; opp-microvolt-L0 = <737500 737500 950000>; @@ -472,7 +486,7 @@ clock-latency-ns = <40000>; }; opp-1416000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1416000000>; opp-microvolt = <712500 712500 950000>; opp-microvolt-L0 = <775000 775000 950000>; @@ -484,7 +498,7 @@ clock-latency-ns = <40000>; }; opp-1608000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1608000000>; opp-microvolt = <812500 812500 950000>; opp-microvolt-L1 = <800000 800000 950000>; @@ -500,7 +514,7 @@ clock-latency-ns = <40000>; }; opp-1800000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <887500 887500 950000>; opp-microvolt-L1 = <875000 875000 950000>; @@ -534,7 +548,7 @@ clock-latency-ns = <40000>; }; opp-2016000000 { - opp-supported-hw = <0xf7 0xffff>; + opp-supported-hw = <0xf1 0xffff>; opp-hz = /bits/ 64 <2016000000>; opp-microvolt = <950000 950000 950000>; opp-microvolt-L1 = <937500 937500 950000>; @@ -549,6 +563,96 @@ opp-microvolt-L10 = <825000 825000 950000>; clock-latency-ns = <40000>; }; + + /* RK3576J/M cluster0 OPPs */ + opp-j-m-408000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-816000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1008000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1200000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1416000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>; + opp-microvolt-L0 = <775000 775000 950000>; + opp-microvolt-L1 = <762500 762500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + cluster0_opp_j_m_1608000000: opp-j-m-1608000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <825000 825000 950000>; + opp-microvolt-L1 = <812500 812500 950000>; + opp-microvolt-L2 = <800000 800000 950000>; + opp-microvolt-L3 = <787500 787500 950000>; + opp-microvolt-L4 = <787500 787500 950000>; + opp-microvolt-L5 = <775000 775000 950000>; + opp-microvolt-L6 = <762500 762500 950000>; + opp-microvolt-L7 = <750000 750000 950000>; + opp-microvolt-L8 = <750000 750000 950000>; + opp-microvolt-L9 = <750000 750000 950000>; + opp-microvolt-L10 = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + cluster0_opp_j_m_1800000000: opp-j-m-1800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <887500 887500 950000>; + opp-microvolt-L1 = <875000 875000 950000>; + opp-microvolt-L2 = <862500 862500 950000>; + opp-microvolt-L3 = <850000 850000 950000>; + opp-microvolt-L4 = <837500 837500 950000>; + opp-microvolt-L5 = <825000 825000 950000>; + opp-microvolt-L6 = <812500 812500 950000>; + opp-microvolt-L7 = <800000 800000 950000>; + opp-microvolt-L8 = <787500 787500 950000>; + opp-microvolt-L9 = <775000 775000 950000>; + opp-microvolt-L10 = <762500 762500 950000>; + clock-latency-ns = <40000>; + }; + cluster0_opp_j_m_1920000000: opp-j-m-1920000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1920000000>; + opp-microvolt = <937500 937500 950000>; + opp-microvolt-L1 = <925000 925000 950000>; + opp-microvolt-L2 = <912500 912500 950000>; + opp-microvolt-L3 = <900000 900000 950000>; + opp-microvolt-L4 = <887500 887500 950000>; + opp-microvolt-L5 = <875000 875000 950000>; + opp-microvolt-L6 = <862500 862500 950000>; + opp-microvolt-L7 = <850000 850000 950000>; + opp-microvolt-L8 = <837500 837500 950000>; + opp-microvolt-L9 = <825000 825000 950000>; + opp-microvolt-L10 = <812500 812500 950000>; + clock-latency-ns = <40000>; + }; + }; cluster1_opp_table: cluster1-opp-table { @@ -560,6 +664,20 @@ nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; rockchip,supported-hw; + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = < + 0 1874 0 + 1875 1904 1 + 1905 1934 2 + 1935 1969 3 + 1970 2009 4 + 2010 2049 5 + 2050 2089 6 + 2090 2129 7 + 2130 2169 8 + 2170 2209 9 + 2210 9999 10 + >; rockchip,pvtm-voltage-sel = < 0 1919 0 1920 1949 1 @@ -599,32 +717,32 @@ rockchip,low-temp-min-volt = <800000>; opp-408000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <408000000>; opp-microvolt = <712500 712500 950000>; clock-latency-ns = <40000>; opp-suspend; }; opp-600000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <600000000>; opp-microvolt = <712500 712500 950000>; clock-latency-ns = <40000>; }; opp-816000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <816000000>; opp-microvolt = <712500 712500 950000>; clock-latency-ns = <40000>; }; opp-1008000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <712500 712500 950000>; clock-latency-ns = <40000>; }; opp-1200000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <712500 712500 950000>; opp-microvolt-L0 = <750000 750000 950000>; @@ -634,7 +752,7 @@ clock-latency-ns = <40000>; }; opp-1416000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1416000000>; opp-microvolt = <712500 712500 950000>; opp-microvolt-L0 = <750000 750000 950000>; @@ -644,7 +762,7 @@ clock-latency-ns = <40000>; }; opp-1608000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1608000000>; opp-microvolt = <725000 725000 950000>; opp-microvolt-L0 = <775000 775000 950000>; @@ -655,7 +773,7 @@ clock-latency-ns = <40000>; }; opp-1800000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <825000 825000 950000>; opp-microvolt-L1 = <825000 825000 950000>; @@ -671,7 +789,7 @@ clock-latency-ns = <40000>; }; opp-2016000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <2016000000>; opp-microvolt = <887500 887500 950000>; opp-microvolt-L1 = <887500 887500 950000>; @@ -704,7 +822,7 @@ clock-latency-ns = <40000>; }; opp-2208000000 { - opp-supported-hw = <0xf7 0xffff>; + opp-supported-hw = <0xf1 0xffff>; opp-hz = /bits/ 64 <2208000000>; opp-microvolt = <950000 950000 950000>; opp-microvolt-L1 = <950000 950000 950000>; @@ -719,6 +837,103 @@ opp-microvolt-L10 = <837500 837500 950000>; clock-latency-ns = <40000>; }; + + /* RK3576J/M cluster1 OPPs */ + opp-j-m-408000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-816000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1008000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1200000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1416000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>; + opp-microvolt-L0 = <762500 762500 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1608000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <750000 750000 950000>; + opp-microvolt-L0 = <787500 787500 950000>; + opp-microvolt-L1 = <775000 775000 950000>; + opp-microvolt-L2 = <762500 762500 950000>; + clock-latency-ns = <40000>; + }; + cluster1_opp_j_m_1800000000: opp-j-m-1800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 950000>; + opp-microvolt-L1 = <837500 837500 950000>; + opp-microvolt-L2 = <825000 825000 950000>; + opp-microvolt-L3 = <812500 812500 950000>; + opp-microvolt-L4 = <800000 800000 950000>; + opp-microvolt-L5 = <787500 787500 950000>; + opp-microvolt-L6 = <775000 775000 950000>; + opp-microvolt-L7 = <762500 762500 950000>; + opp-microvolt-L8 = <750000 750000 950000>; + opp-microvolt-L9 = <750000 750000 950000>; + opp-microvolt-L10 = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + cluster1_opp_j_m_2016000000: opp-j-m-2016000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <912500 912500 950000>; + opp-microvolt-L1 = <900000 900000 950000>; + opp-microvolt-L2 = <887500 887500 950000>; + opp-microvolt-L3 = <875000 875000 950000>; + opp-microvolt-L4 = <862500 862500 950000>; + opp-microvolt-L5 = <850000 850000 950000>; + opp-microvolt-L6 = <837500 837500 950000>; + opp-microvolt-L7 = <825000 825000 950000>; + opp-microvolt-L8 = <812500 812500 950000>; + opp-microvolt-L9 = <800000 800000 950000>; + opp-microvolt-L10 = <787500 787500 950000>; + clock-latency-ns = <40000>; + }; + cluster1_opp_j_m_2112000000: opp-j-m-2112000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <2112000000>; + opp-microvolt = <950000 950000 950000>; + opp-microvolt-L1 = <937500 937500 950000>; + opp-microvolt-L2 = <925000 925000 950000>; + opp-microvolt-L3 = <912500 912500 950000>; + opp-microvolt-L4 = <900000 900000 950000>; + opp-microvolt-L5 = <887500 887500 950000>; + opp-microvolt-L6 = <875000 875000 950000>; + opp-microvolt-L7 = <862500 862500 950000>; + opp-microvolt-L8 = <850000 850000 950000>; + opp-microvolt-L9 = <837500 837500 950000>; + opp-microvolt-L10 = <825000 825000 950000>; + clock-latency-ns = <40000>; + }; }; bus_a72: bus-a72 { @@ -734,8 +949,9 @@ compatible = "operating-points-v2"; opp-shared; - nvmem-cells = <&log_leakage>; - nvmem-cell-names = "leakage"; + nvmem-cells = <&log_leakage>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "specification_serial_number"; + rockchip,supported-hw; rockchip,leakage-voltage-sel = < 1 10 0 @@ -744,23 +960,46 @@ >; opp-1800000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <750000 750000 800000>; opp-microvolt-L1 = <725000 725000 800000>; opp-microvolt-L2 = <712500 712500 800000>; }; opp-2016000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <2016000000>; opp-microvolt = <775000 775000 800000>; opp-microvolt-L1 = <750000 750000 800000>; opp-microvolt-L2 = <712500 712500 800000>; }; opp-2208000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <2208000000>; opp-microvolt = <800000 800000 800000>; opp-microvolt-L1 = <775000 775000 800000>; opp-microvolt-L2 = <737500 737500 800000>; }; + + opp-j-m-1800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <750000 750000 800000>; + }; + opp-j-m-2016000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <775000 775000 800000>; + opp-microvolt-L1 = <750000 750000 800000>; + opp-microvolt-L2 = <750000 750000 800000>; + }; + opp-j-m-2208000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <800000 800000 800000>; + opp-microvolt-L1 = <775000 775000 800000>; + opp-microvolt-L2 = <750000 750000 800000>; + }; }; cpuinfo { @@ -943,8 +1182,9 @@ dmc_opp_table: dmc-opp-table { compatible = "operating-points-v2"; - nvmem-cells = <&log_leakage>, <&logic_opp_info>; - nvmem-cell-names = "leakage", "opp-info"; + nvmem-cells = <&log_leakage>, <&logic_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + rockchip,supported-hw; rockchip,early-min-microvolt = <0 750000>; /* */ @@ -958,6 +1198,7 @@ 21 254 2 >; opp-528000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <528000000>; opp-microvolt = <750000 750000 850000>, <750000 750000 800000>; @@ -967,6 +1208,7 @@ <712500 712500 800000>; }; opp-1068000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1068000000>; opp-microvolt = <750000 750000 850000>, <750000 750000 800000>; @@ -976,6 +1218,7 @@ <712500 712500 800000>; }; opp-1560000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <1560000000>; opp-microvolt = <750000 750000 850000>, <750000 750000 800000>; @@ -985,6 +1228,7 @@ <725000 725000 800000>; }; opp-2736000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <2736000000>; opp-microvolt = <825000 825000 850000>, <750000 750000 800000>; @@ -993,6 +1237,35 @@ opp-microvolt-L2 = <775000 775000 850000>, <725000 725000 800000>; }; + /* RK3576J/M DMC OPPs */ + opp-j-m-528000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <528000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 800000>; + }; + opp-j-m-1068000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1068000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 800000>; + }; + opp-j-m-1560000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1560000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 800000>; + }; + opp-j-m-2736000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <2736000000>; + opp-microvolt = <825000 825000 850000>, + <750000 750000 800000>; + opp-microvolt-L1 = <800000 800000 850000>, + <750000 750000 800000>; + opp-microvolt-L2 = <775000 775000 850000>, + <750000 750000 800000>; + }; }; firmware { @@ -2170,6 +2443,19 @@ nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; rockchip,supported-hw; + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = < + 0 739 0 + 740 759 1 + 760 779 2 + 780 799 3 + 800 819 4 + 820 839 5 + 840 859 6 + 860 879 7 + 880 899 8 + 900 9999 9 + >; rockchip,pvtm-voltage-sel = < 0 719 0 720 739 1 @@ -2211,12 +2497,12 @@ rockchip,low-temp-min-volt = <750000>; opp-300000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <300000000>; opp-microvolt = <725000 725000 875000>; }; opp-400000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <400000000>; opp-microvolt = <725000 725000 875000>; }; @@ -2230,21 +2516,21 @@ opp-microvolt-L2 = <737500 737500 875000>; }; opp-500000000 { - opp-supported-hw = <0xf7 0xffff>; + opp-supported-hw = <0xf1 0xffff>; opp-hz = /bits/ 64 <500000000>; opp-microvolt = <725000 725000 875000>; opp-microvolt-L0 = <737500 737500 875000>; opp-microvolt-L1 = <737500 737500 875000>; }; opp-600000000 { - opp-supported-hw = <0xf7 0xffff>; + opp-supported-hw = <0xf1 0xffff>; opp-hz = /bits/ 64 <600000000>; opp-microvolt = <725000 725000 875000>; opp-microvolt-L0 = <737500 737500 875000>; opp-microvolt-L1 = <737500 737500 875000>; }; opp-700000000 { - opp-supported-hw = <0xf7 0xffff>; + opp-supported-hw = <0xf1 0xffff>; opp-hz = /bits/ 64 <700000000>; opp-microvolt = <725000 725000 875000>; opp-microvolt-L0 = <775000 775000 875000>; @@ -2256,7 +2542,7 @@ opp-microvolt-L6 = <725000 725000 875000>; }; opp-800000000 { - opp-supported-hw = <0xf7 0xffff>; + opp-supported-hw = <0xf1 0xffff>; opp-hz = /bits/ 64 <800000000>; opp-microvolt = <800000 800000 875000>; opp-microvolt-L1 = <800000 800000 875000>; @@ -2271,7 +2557,7 @@ opp-microvolt-L10 = <725000 725000 875000>; }; opp-900000000 { - opp-supported-hw = <0xf7 0xffff>; + opp-supported-hw = <0xf1 0xffff>; opp-hz = /bits/ 64 <900000000>; opp-microvolt = <850000 850000 875000>; opp-microvolt-L1 = <850000 850000 875000>; @@ -2286,7 +2572,7 @@ opp-microvolt-L10 = <737500 737500 875000>; }; opp-950000000 { - opp-supported-hw = <0xf7 0xffff>; + opp-supported-hw = <0xf1 0xffff>; opp-hz = /bits/ 64 <950000000>; opp-microvolt = <875000 875000 875000>; opp-microvolt-L1 = <875000 875000 875000>; @@ -2300,6 +2586,61 @@ opp-microvolt-L9 = <775000 775000 875000>; opp-microvolt-L10 = <762500 762500 875000>; }; + + /* RK3576J/M NPU OPPs */ + opp-j-m-300000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <750000 750000 875000>; + }; + opp-j-m-400000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <750000 750000 875000>; + }; + opp-j-m-500000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <750000 750000 875000>; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 875000>; + }; + opp-j-m-700000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <750000 750000 875000>; + opp-microvolt-L0 = <787500 787500 875000>; + opp-microvolt-L1 = <775000 775000 875000>; + opp-microvolt-L2 = <762500 762500 875000>; + }; + npu_opp_j_m_800000000: opp-j-m-800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 875000>; + opp-microvolt-L0 = <812500 812500 875000>; + opp-microvolt-L1 = <800000 800000 875000>; + opp-microvolt-L2 = <787500 787500 875000>; + opp-microvolt-L3 = <775000 775000 875000>; + opp-microvolt-L4 = <762500 762500 875000>; + }; + npu_opp_j_m_850000000: opp-j-m-850000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <850000000>; + opp-microvolt = <837500 837500 875000>; + opp-microvolt-L1 = <825000 825000 875000>; + opp-microvolt-L2 = <812500 812500 875000>; + opp-microvolt-L3 = <800000 800000 875000>; + opp-microvolt-L4 = <787500 787500 875000>; + opp-microvolt-L5 = <775000 775000 875000>; + opp-microvolt-L6 = <762500 762500 875000>; + opp-microvolt-L7 = <750000 750000 875000>; + opp-microvolt-L8 = <750000 750000 875000>; + opp-microvolt-L9 = <750000 750000 875000>; + }; + }; rknpu_mmu: iommu@27702000 { @@ -2347,6 +2688,20 @@ nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; rockchip,supported-hw; + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = < + 0 689 0 + 690 709 1 + 710 729 2 + 730 749 3 + 750 769 4 + 770 789 5 + 790 809 6 + 810 829 7 + 830 849 8 + 850 869 9 + 870 9999 10 + >; rockchip,pvtm-voltage-sel = < 0 704 0 705 724 1 @@ -2386,27 +2741,27 @@ rockchip,low-temp-min-volt = <750000>; opp-300000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <300000000>; opp-microvolt = <712500 712500 875000>; }; opp-400000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <400000000>; opp-microvolt = <712500 712500 875000>; }; opp-500000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <500000000>; opp-microvolt = <712500 712500 875000>; }; opp-600000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <600000000>; opp-microvolt = <712500 712500 875000>; }; opp-700000000 { - opp-supported-hw = <0xff 0xffff>; + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <700000000>; opp-microvolt = <712500 712500 875000>; opp-microvolt-L0 = <750000 750000 875000>; @@ -2432,7 +2787,7 @@ opp-microvolt-L10 = <725000 725000 875000>; }; opp-800000000 { - opp-supported-hw = <0xf7 0xffff>; + opp-supported-hw = <0xf1 0xffff>; opp-hz = /bits/ 64 <800000000>; opp-microvolt = <812500 812500 875000>; opp-microvolt-L1 = <812500 812500 875000>; @@ -2447,7 +2802,7 @@ opp-microvolt-L10 = <725000 725000 875000>; }; opp-900000000 { - opp-supported-hw = <0xf7 0xffff>; + opp-supported-hw = <0xf1 0xffff>; opp-hz = /bits/ 64 <900000000>; opp-microvolt = <875000 875000 875000>; opp-microvolt-L1 = <875000 875000 875000>; @@ -2461,6 +2816,50 @@ opp-microvolt-L9 = <775000 775000 875000>; opp-microvolt-L10 = <762500 762500 875000>; }; + + /* RK3576J/M GPU OPPs */ + opp-j-m-300000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <750000 750000 950000>; + }; + opp-j-m-400000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <750000 750000 950000>; + }; + opp-j-m-500000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <750000 750000 950000>; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 950000>; + }; + opp-j-m-700000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <750000 750000 950000>; + opp-microvolt-L0 = <775000 775000 950000>; + opp-microvolt-L1 = <762500 762500 950000>; + }; + gpu_opp_j_m_800000000: opp-j-m-800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <850000 850000 875000>; + opp-microvolt-L1 = <837500 837500 875000>; + opp-microvolt-L2 = <825000 825000 875000>; + opp-microvolt-L3 = <812500 812500 875000>; + opp-microvolt-L4 = <800000 800000 875000>; + opp-microvolt-L5 = <787500 787500 875000>; + opp-microvolt-L6 = <775000 775000 875000>; + opp-microvolt-L7 = <762500 762500 875000>; + opp-microvolt-L8 = <750000 750000 875000>; + opp-microvolt-L9 = <750000 750000 875000>; + opp-microvolt-L10 = <750000 750000 875000>; + }; }; ebc: ebc@27900000 { @@ -3140,8 +3539,9 @@ vop_opp_table: vop-opp-table { compatible = "operating-points-v2"; - nvmem-cells = <&log_leakage>; - nvmem-cell-names = "leakage"; + nvmem-cells = <&log_leakage>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "specification_serial_number"; + rockchip,supported-hw; rockchip,early-min-microvolt = <750000>; /* vdd_logic */ @@ -3157,23 +3557,43 @@ 21 254 2 >; opp-500000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <500000000>; opp-microvolt = <725000 725000 800000>; opp-microvolt-L1 = <712500 712500 800000>; opp-microvolt-L2 = <712500 712500 800000>; }; opp-594000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <594000000>; opp-microvolt = <750000 750000 800000>; opp-microvolt-L1 = <750000 750000 800000>; opp-microvolt-L2 = <725000 725000 800000>; }; opp-702000000 { + opp-supported-hw = <0xf9 0xffff>; opp-hz = /bits/ 64 <702000000>; opp-microvolt = <750000 750000 800000>; opp-microvolt-L1 = <750000 750000 800000>; opp-microvolt-L2 = <725000 725000 800000>; }; + + /* RK3576J/M VOP OPPs */ + opp-j-m-500000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <750000 750000 800000>; + }; + opp-j-m-594000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <594000000>; + opp-microvolt = <750000 750000 800000>; + }; + opp-j-m-702000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <702000000>; + opp-microvolt = <750000 750000 800000>; + }; }; vop_mmu: iommu@27d07e00 { From 1b8e6e3e0214b3dcadad515b1ccb079a3a7886d4 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 16 Oct 2024 18:03:56 +0800 Subject: [PATCH 21/25] arm64: dts: rockchip: Add rk3576j.dtsi Change-Id: I072199c8749b4115e94909368f02886d4a118ced Signed-off-by: Finley Xiao --- arch/arm64/boot/dts/rockchip/rk3576j.dtsi | 71 +++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3576j.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3576j.dtsi b/arch/arm64/boot/dts/rockchip/rk3576j.dtsi new file mode 100644 index 000000000000..3d90aaeab22d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576j.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3576.dtsi" + +/* + * The Max frequency of cluster0 is 1416MHz in default normal mode. + * The Max frequency of cluster0 is 1920MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, + * especially in high temperature condition. + */ +&cluster0_opp_j_m_1608000000 { + status = "disabled"; +}; + +&cluster0_opp_j_m_1800000000 { + status = "disabled"; +}; + +&cluster0_opp_j_m_1920000000 { + status = "disabled"; +}; + +/* + * The Max frequency of cluster1 is 1608MHz in default normal mode. + * The Max frequency of cluster1 is 2112MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, + * especially in high temperature condition. + */ +&cluster1_opp_j_m_1800000000 { + status = "disabled"; +}; + +&cluster1_opp_j_m_2016000000 { + status = "disabled"; +}; + +&cluster1_opp_j_m_2112000000 { + status = "disabled"; +}; + +/* + * The Max frequency of GPU is 700MHz in default normal mode. + * The Max frequency of GPU is 800MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, + * especially in high temperature condition. + */ +&gpu_opp_j_m_800000000 { + status = "disabled"; +}; + +/* + * The Max frequency of NPU is 700MHz in default normal mode. + * The Max frequency of NPU is 850MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, + * especially in high temperature condition. + */ +&npu_opp_j_m_800000000 { + status = "disabled"; +}; + +&npu_opp_j_m_850000000 { + status = "disabled"; +}; From 4d6637906b9e37563c9533041a508b648e02808d Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 16 Oct 2024 23:04:51 +0800 Subject: [PATCH 22/25] firmware: rockchip_sip: Add sub func id PVTPLL_VOLT_SEL for SIP_PVTPLL_CFG Change-Id: I389fdb0f36b2709d7cc75d4962c3f0a33816a840 Signed-off-by: Finley Xiao --- include/linux/rockchip/rockchip_sip.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/rockchip/rockchip_sip.h b/include/linux/rockchip/rockchip_sip.h index 20b91a1dfa34..b05a0a624209 100644 --- a/include/linux/rockchip/rockchip_sip.h +++ b/include/linux/rockchip/rockchip_sip.h @@ -239,6 +239,7 @@ enum { PVTPLL_GET_INFO = 0, PVTPLL_ADJUST_TABLE = 1, PVTPLL_LOW_TEMP = 2, + PVTPLL_VOLT_SEL = 3, }; struct pt_regs; From e00e223f66019572211d7f31454d7ba29d781193 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 16 Oct 2024 23:08:52 +0800 Subject: [PATCH 23/25] soc: rockchip: opp_select: Add support to config pvtpll volt sel Change-Id: I8ffc9b9e2ad3f743f46c3b77cc5c745cfb0d17ce Signed-off-by: Finley Xiao --- drivers/soc/rockchip/rockchip_opp_select.c | 27 +++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/soc/rockchip/rockchip_opp_select.c b/drivers/soc/rockchip/rockchip_opp_select.c index 77e73bdf8b6c..549c8b6c5b4f 100644 --- a/drivers/soc/rockchip/rockchip_opp_select.c +++ b/drivers/soc/rockchip/rockchip_opp_select.c @@ -1389,8 +1389,10 @@ static void rockchip_init_pvtpll_table(struct device *dev, of_node_put(clkspec.np); res = sip_smc_get_pvtpll_info(PVTPLL_GET_INFO, info->pvtpll_clk_id); - if (res.a0) + if (res.a0) { + info->pvtpll_clk_id = UINT_MAX; goto out; + } if (!res.a1) info->pvtpll_low_temp = true; @@ -1695,6 +1697,7 @@ int rockchip_init_opp_info(struct device *dev, struct rockchip_opp_info *info, info->bin = -EINVAL; info->process = -EINVAL; info->volt_sel = -EINVAL; + info->pvtpll_clk_id = UINT_MAX; info->is_runtime_active = true; mutex_init(&info->dvfs_mutex); @@ -2055,12 +2058,34 @@ static int rockchip_opp_parse_supplies(struct device *dev, return 0; } +static int rockchip_pvtpll_set_volt_sel(struct device *dev, + struct rockchip_opp_info *info) +{ + struct arm_smccc_res res; + + if (!info) + return 0; + if (info->volt_sel < 0) + return 0; + if (info->pvtpll_clk_id == UINT_MAX) + return 0; + + res = sip_smc_pvtpll_config(PVTPLL_VOLT_SEL, info->pvtpll_clk_id, + (u32)info->volt_sel, 0, 0, 0, 0); + if (res.a0) + dev_err(dev, "%s: error cfg clk_id=%u voltsel (%d)\n", __func__, + info->pvtpll_clk_id, (int)res.a0); + + return 0; +} + int rockchip_adjust_opp_table(struct device *dev, struct rockchip_opp_info *info) { rockchip_opp_parse_supplies(dev, info); rockchip_adjust_power_scale(dev, info); rockchip_pvtpll_calibrate_opp(info); rockchip_pvtpll_add_length(info); + rockchip_pvtpll_set_volt_sel(dev, info); return 0; } From e8d003fc7efc6025745a2251edabd69bb13276c0 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Thu, 10 Oct 2024 19:29:19 +0800 Subject: [PATCH 24/25] drm/rockchip: vop: remove afbc support for rk3399 vop lit rk3399 vop lite can't support afbc, so remove afbc support from win feature. Signed-off-by: Sandy Huang Change-Id: I3ccdc2a821bc97fd4993688c61b776c1c77d0cb9 --- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 8b3edda93ec5..d3455091ed9c 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -742,13 +742,11 @@ static const struct vop_data rk3399_vop_big = { static const struct vop_win_data rk3399_vop_lit_win_data[] = { { .base = 0x00, .phy = &rk3399_win01_data, .csc = &rk3399_win0_csc, .format_modifiers = format_modifiers, - .type = DRM_PLANE_TYPE_OVERLAY, - .feature = WIN_FEATURE_AFBDC }, + .type = DRM_PLANE_TYPE_OVERLAY }, { .phy = NULL }, { .base = 0x00, .phy = &rk3368_win23_data, .csc = &rk3399_win2_csc, .format_modifiers = format_modifiers, .type = DRM_PLANE_TYPE_PRIMARY, - .feature = WIN_FEATURE_AFBDC, .area = rk3368_area_data, .area_size = ARRAY_SIZE(rk3368_area_data), }, { .phy = NULL }, From 8b9ce96e9b27632cbf780e95eca4a6e35b44589c Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Thu, 7 Nov 2024 15:38:23 +0800 Subject: [PATCH 25/25] arm64: dts: rockchip: Add rk3576m.dtsi Change-Id: I64a712e3751274359fdfbaae4f5ffe332cbac12e Signed-off-by: Finley Xiao --- arch/arm64/boot/dts/rockchip/rk3576m.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3576m.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3576m.dtsi b/arch/arm64/boot/dts/rockchip/rk3576m.dtsi new file mode 100644 index 000000000000..34870ea3fa22 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576m.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3576.dtsi"