diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index a73fea168424..337cf3ef8287 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -166,12 +166,6 @@ config ROCKCHIP_CLK_PVTM help Say y here to enable clk pvtm. -config ROCKCHIP_DCLK_DIV - bool "Rockchip Dclk Divider" - default y if !CPU_RV1126 && !CPU_RV1106 - help - Say y here to enable dclk divider. - config ROCKCHIP_DDRCLK_SCPI bool "Rockchip DDR Clk SCPI" default y if RK3368_SCPI_PROTOCOL diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index e45fa0a0ba0d..394bf71850fb 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -15,7 +15,6 @@ clk-rockchip-y += clk-muxgrf.o clk-rockchip-y += clk-ddr.o clk-rockchip-$(CONFIG_ROCKCHIP_CLK_INV) += clk-inverter.o clk-rockchip-$(CONFIG_ROCKCHIP_CLK_PVTM) += clk-pvtm.o -clk-rockchip-$(CONFIG_ROCKCHIP_DCLK_DIV) += clk-dclk-divider.o clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o obj-$(CONFIG_ROCKCHIP_CLK_LINK) += clk-link.o diff --git a/drivers/clk/rockchip/clk-dclk-divider.c b/drivers/clk/rockchip/clk-dclk-divider.c index 77c35b42207e..88cf7ab82a57 100644 --- a/drivers/clk/rockchip/clk-dclk-divider.c +++ b/drivers/clk/rockchip/clk-dclk-divider.c @@ -18,7 +18,7 @@ static unsigned long clk_dclk_recalc_rate(struct clk_hw *hw, struct clk_divider *divider = to_clk_divider(hw); unsigned int val; - val = readl(divider->reg) >> divider->shift; + val = clk_readl(divider->reg) >> divider->shift; val &= div_mask(divider->width); return DIV_ROUND_UP_ULL(((u64)parent_rate), val + 1); @@ -57,11 +57,11 @@ static int clk_dclk_set_rate(struct clk_hw *hw, unsigned long rate, if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { val = div_mask(divider->width) << (divider->shift + 16); } else { - val = readl(divider->reg); + val = clk_readl(divider->reg); val &= ~(div_mask(divider->width) << divider->shift); } val |= value << divider->shift; - writel(val, divider->reg); + clk_writel(val, divider->reg); if (divider->lock) spin_unlock_irqrestore(divider->lock, flags); diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c index 4b4513a26740..facd1fa493ba 100644 --- a/drivers/clk/rockchip/clk-rk3368.c +++ b/drivers/clk/rockchip/clk-rk3368.c @@ -470,9 +470,9 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { RK3368_CLKSEL_CON(18), 6, 2, MFLAGS, 0, 5, DFLAGS, RK3368_CLKGATE_CON(4), 4, GFLAGS), - COMPOSITE_DCLK(DCLK_VOP, "dclk_vop", mux_pll_src_dmycpll_dmygpll_npll_p, CLK_SET_RATE_PARENT, + COMPOSITE(DCLK_VOP, "dclk_vop", mux_pll_src_dmycpll_dmygpll_npll_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS, - RK3368_CLKGATE_CON(4), 1, GFLAGS, RK3368_DCLK_PARENT_MAX_PRATE), + RK3368_CLKGATE_CON(4), 1, GFLAGS), GATE(SCLK_VOP0_PWM, "sclk_vop0_pwm", "xin24m", 0, RK3368_CLKGATE_CON(4), 2, GFLAGS), diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 44ce9cc542ce..02cee1d3b226 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -1074,9 +1074,9 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS, RK3568_CLKGATE_CON(20), 10, GFLAGS), - COMPOSITE_DCLK(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS, - RK3568_CLKGATE_CON(20), 11, GFLAGS, RK3568_DCLK_PARENT_MAX_PRATE), + RK3568_CLKGATE_CON(20), 11, GFLAGS), COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0, RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS, RK3568_CLKGATE_CON(20), 12, GFLAGS), diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index b5ad51b8df7e..3684966101f3 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -2070,9 +2070,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(DCLK_VOP1_SRC, "dclk_vop1_src", gpll_cpll_v0pll_aupll_p, 0, RK3588_CLKSEL_CON(111), 14, 2, MFLAGS, 9, 5, DFLAGS, RK3588_CLKGATE_CON(52), 11, GFLAGS), - COMPOSITE_DCLK(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, RK3588_CLKSEL_CON(112), 5, 2, MFLAGS, 0, 5, DFLAGS, - RK3588_CLKGATE_CON(52), 12, GFLAGS, RK3588_DCLK_MAX_PRATE), + RK3588_CLKGATE_CON(52), 12, GFLAGS), COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, RK3588_CLKSEL_CON(112), 7, 2, MFLAGS, RK3588_CLKGATE_CON(52), 13, GFLAGS), diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index b2d104fc15f6..63b73b76947e 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -679,18 +679,6 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, list->div_width, list->div_flags, ctx->reg_base); break; - case branch_dclk_divider: -#ifdef CONFIG_ROCKCHIP_DCLK_DIV - clk = rockchip_clk_register_dclk_branch(list->name, - list->parent_names, list->num_parents, - ctx->reg_base, list->muxdiv_offset, list->mux_shift, - list->mux_width, list->mux_flags, - list->div_offset, list->div_shift, list->div_width, - list->div_flags, list->div_table, - list->gate_offset, list->gate_shift, - list->gate_flags, flags, list->max_prate, &ctx->lock); -#endif - break; } /* none of the cases above matched */ diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 31e10c559c8c..f778c6513020 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -634,7 +634,6 @@ enum rockchip_clk_branch_type { branch_factor, branch_ddrclk, branch_half_divider, - branch_dclk_divider, }; struct rockchip_clk_branch { @@ -1183,28 +1182,6 @@ struct rockchip_clk_branch { .gate_offset = -1, \ } -#define COMPOSITE_DCLK(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\ - df, go, gs, gf, prate) \ - { \ - .id = _id, \ - .branch_type = branch_dclk_divider, \ - .name = cname, \ - .parent_names = pnames, \ - .num_parents = ARRAY_SIZE(pnames), \ - .flags = f, \ - .muxdiv_offset = mo, \ - .mux_shift = ms, \ - .mux_width = mw, \ - .mux_flags = mf, \ - .div_shift = ds, \ - .div_width = dw, \ - .div_flags = df, \ - .gate_offset = go, \ - .gate_shift = gs, \ - .gate_flags = gf, \ - .max_prate = prate, \ - } - /* SGRF clocks are only accessible from secure mode, so not controllable */ #define SGRF_GATE(_id, cname, pname) \ FACTOR(_id, cname, pname, 0, 1, 1) @@ -1248,21 +1225,6 @@ struct clk *rockchip_clk_register_halfdiv(const char *name, u8 gate_flags, unsigned long flags, spinlock_t *lock); -struct clk *rockchip_clk_register_dclk_branch(const char *name, - const char *const *parent_names, - u8 num_parents, - void __iomem *base, - int muxdiv_offset, u8 mux_shift, - u8 mux_width, u8 mux_flags, - int div_offset, u8 div_shift, - u8 div_width, u8 div_flags, - struct clk_div_table *div_table, - int gate_offset, - u8 gate_shift, u8 gate_flags, - unsigned long flags, - unsigned long max_prate, - spinlock_t *lock); - #ifdef CONFIG_RESET_CONTROLLER void rockchip_register_softrst(struct device_node *np, unsigned int num_regs, diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 200a80e4bfed..051b33a17d5b 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -574,7 +574,6 @@ struct clk_div_table { * @reg: register containing the divider * @shift: shift to the divider bit field * @width: width of the divider bit field - * @max_prate: the maximum frequency of the parent clock * @table: array of value/divider pairs, last entry should have div = 0 * @lock: register lock * @@ -614,7 +613,6 @@ struct clk_divider { u8 shift; u8 width; u8 flags; - unsigned long max_prate; const struct clk_div_table *table; spinlock_t *lock; };