From 5d2e0b332bdbbe88461d0bc740a8e693d938ee56 Mon Sep 17 00:00:00 2001
From: Sugar Zhang <sugar.zhang@rock-chips.com>
Date: Mon, 30 Jan 2023 09:40:23 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3588: Add I2Sx_MCLK{OUT,IN} nodes

e.g.

  mclkin_i2s0: mclkin-i2s0 {
      compatible = "fixed-clock";
      #clock-cells = <0>;
      clock-frequency = <12288000>;
      clock-output-names = "i2s0_mclkin";
  };

  mclkout_i2s0: mclkout-i2s0@fd58c318 {
      compatible = "rockchip,clk-out";
      reg = <0 0xfd58c318 0 0x4>;
      clocks = <&cru I2S0_8CH_MCLKOUT>;
      #clock-cells = <0>;
      clock-output-names = "i2s0_mclkout_to_io";
      rockchip,bit-shift = <0>;
      rockchip,bit-set-to-disable;
  };

Note:

clock-output-names of mclkin_i2s0 should equal to strings in drivers. such as:

drivers/clk/rockchip/clk-rk3588.c:

PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin12m" };
PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin12m" };

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Iefca0d7f8b90473a1331a15b1b82f389254ca015
---
 arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 68 +++++++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index fd5053c69eaf..a1fc41745f59 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -295,6 +295,74 @@
 			clock-names = "link";
 			#clock-cells = <0>;
 		};
+
+		mclkin_i2s0: mclkin-i2s0 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <12288000>;
+			clock-output-names = "i2s0_mclkin";
+		};
+
+		mclkin_i2s1: mclkin-i2s1 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <12288000>;
+			clock-output-names = "i2s1_mclkin";
+		};
+
+		mclkin_i2s2: mclkin-i2s2 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <12288000>;
+			clock-output-names = "i2s2_mclkin";
+		};
+
+		mclkin_i2s3: mclkin-i2s3 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <12288000>;
+			clock-output-names = "i2s3_mclkin";
+		};
+
+		mclkout_i2s0: mclkout-i2s0@fd58c318 {
+			compatible = "rockchip,clk-out";
+			reg = <0 0xfd58c318 0 0x4>;
+			clocks = <&cru I2S0_8CH_MCLKOUT>;
+			#clock-cells = <0>;
+			clock-output-names = "i2s0_mclkout_to_io";
+			rockchip,bit-shift = <0>;
+			rockchip,bit-set-to-disable;
+		};
+
+		mclkout_i2s1: mclkout-i2s1@fd58c318 {
+			compatible = "rockchip,clk-out";
+			reg = <0 0xfd58c318 0 0x4>;
+			clocks = <&cru I2S1_8CH_MCLKOUT>;
+			#clock-cells = <0>;
+			clock-output-names = "i2s1_mclkout_to_io";
+			rockchip,bit-shift = <1>;
+			rockchip,bit-set-to-disable;
+		};
+
+		mclkout_i2s2: mclkout-i2s2@fd58c318 {
+			compatible = "rockchip,clk-out";
+			reg = <0 0xfd58c318 0 0x4>;
+			clocks = <&cru I2S2_2CH_MCLKOUT>;
+			#clock-cells = <0>;
+			clock-output-names = "i2s2_mclkout_to_io";
+			rockchip,bit-shift = <2>;
+			rockchip,bit-set-to-disable;
+		};
+
+		mclkout_i2s3: mclkout-i2s3@fd58c318 {
+			compatible = "rockchip,clk-out";
+			reg = <0 0xfd58c318 0 0x4>;
+			clocks = <&cru I2S3_2CH_MCLKOUT>;
+			#clock-cells = <0>;
+			clock-output-names = "i2s3_mclkout_to_io";
+			rockchip,bit-shift = <7>;
+			rockchip,bit-set-to-disable;
+		};
 	};
 
 	cpus {