diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index feed69aad526..f78b8feff94d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -863,6 +863,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3229-gva-sdk.dtb \ rk3288-evb-act8846.dtb \ rk3288-evb-rk808.dtb \ + rk3288-evb-android-rk808-edp-avb.dtb \ rk3288-fennec.dtb \ rk3288-firefly-beta.dtb \ rk3288-firefly.dtb \ diff --git a/arch/arm/boot/dts/rk3288-android.dtsi b/arch/arm/boot/dts/rk3288-android.dtsi index 275be05e1e14..fcb033579443 100644 --- a/arch/arm/boot/dts/rk3288-android.dtsi +++ b/arch/arm/boot/dts/rk3288-android.dtsi @@ -46,10 +46,6 @@ #include / { - firmware { - firmware_android: android {}; - }; - chosen: chosen { bootargs = "earlycon=uart8250,mmio32,0xff690000 vmalloc=496M"; }; @@ -320,7 +316,8 @@ "rockchip,rk3368-hdmi-analog"; rockchip,model = "rockchip,rt5640-codec"; rockchip,cpu = <&i2s>; - rockchip,codec = <&rt5640>, <&hdmi>; + //rockchip,codec = <&rt5640>, <&hdmi>; + rockchip,codec = <&hdmi>; rockchip,widgets = "Microphone", "Microphone Jack", "Headphone", "Headphone Jack"; @@ -385,8 +382,8 @@ dma-coherent; }; -&video_phy { - status = "okay"; +&uart2 { + status = "disabled"; }; &pinctrl { diff --git a/arch/arm/boot/dts/rk3288-evb-android-rk808-edp-avb.dts b/arch/arm/boot/dts/rk3288-evb-android-rk808-edp-avb.dts index 6bce23eb3fc4..1bdd71b36a90 100644 --- a/arch/arm/boot/dts/rk3288-evb-android-rk808-edp-avb.dts +++ b/arch/arm/boot/dts/rk3288-evb-android-rk808-edp-avb.dts @@ -15,25 +15,6 @@ }; }; -&firmware_android { - compatible = "android,firmware"; - boot_devices = "ff0f0000.dwmmc"; - vbmeta { - compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo"; - }; - fstab { - compatible = "android,fstab"; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/by-name/vendor"; - type = "ext4"; - mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; - fsmgr_flags = "wait,avb"; - }; - }; -}; - &vopb { assigned-clocks = <&cru DCLK_VOP0>; assigned-clock-parents = <&cru PLL_GPLL>; diff --git a/arch/arm/boot/dts/rk3288-evb-android-rk808-edp.dtsi b/arch/arm/boot/dts/rk3288-evb-android-rk808-edp.dtsi index fac0f3bd657c..1f5c1be40447 100644 --- a/arch/arm/boot/dts/rk3288-evb-android-rk808-edp.dtsi +++ b/arch/arm/boot/dts/rk3288-evb-android-rk808-edp.dtsi @@ -73,7 +73,7 @@ status = "okay"; }; -&edp_panel { +&panel { compatible = "simple-panel"; backlight = <&backlight>; enable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; @@ -371,10 +371,6 @@ wifi-supply = <&vcc_wl>; }; -&lvds_panel { - power-supply = <&vcc_lcd>; -}; - &rockchip_suspend { status = "okay"; rockchip,pwm-regulator-config = < diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 97e4d552ff0f..c9c7904e0b7e 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -336,6 +336,12 @@ }; }; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdmmc { /* * Default drive strength isn't enough to achieve even diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts index 58ea8bed040a..44ee3411116a 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -192,7 +192,10 @@ &hdmi { ddc-i2c-bus = <&i2c5>; pinctrl-names = "default"; - pinctrl-0 = <&hdmi_cec_c0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hdmi_ddc>; + pinctrl-1 = <&hdmi_gpio>; + status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3288-linux.dtsi b/arch/arm/boot/dts/rk3288-linux.dtsi index 89c60a8e9581..9ea9dfe09e60 100644 --- a/arch/arm/boot/dts/rk3288-linux.dtsi +++ b/arch/arm/boot/dts/rk3288-linux.dtsi @@ -86,7 +86,7 @@ fiq-debugger { compatible = "rockchip,fiq-debugger"; - interrupts = ; + interrupts = ; rockchip,serial-id = <2>; rockchip,wake-irq = <0>; /* If enable uart uses irq instead of fiq */ @@ -181,6 +181,10 @@ compatible = "rockchip,rk3288-secure-efuse"; }; +&uart2 { + status = "disabled"; +}; + &video_phy { status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 52c8f3840cfd..457125cd231d 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -39,6 +39,8 @@ spi0 = &spi0; spi1 = &spi1; spi2 = &spi2; + dsi0 = &dsi0; + dsi1 = &dsi1; }; arm-pmu { @@ -168,6 +170,7 @@ ; #dma-cells = <1>; arm,pl330-broken-no-flushp; + peripherals-req-type-burst; clocks = <&cru ACLK_DMAC2>; clock-names = "apb_pclk"; }; @@ -179,6 +182,7 @@ ; #dma-cells = <1>; arm,pl330-broken-no-flushp; + peripherals-req-type-burst; clocks = <&cru ACLK_DMAC1>; clock-names = "apb_pclk"; status = "disabled"; @@ -191,6 +195,7 @@ ; #dma-cells = <1>; arm,pl330-broken-no-flushp; + peripherals-req-type-burst; clocks = <&cru ACLK_DMAC1>; clock-names = "apb_pclk"; }; @@ -301,6 +306,7 @@ resets = <&cru SRST_EMMC>; reset-names = "reset"; status = "disabled"; + supports-emmc; }; saradc: saradc@ff100000 { @@ -360,6 +366,19 @@ status = "disabled"; }; + i2c0: i2c@ff650000 { + compatible = "rockchip,rk3288-i2c"; + reg = <0x0 0xff650000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + status = "disabled"; + }; + i2c1: i2c@ff140000 { compatible = "rockchip,rk3288-i2c"; reg = <0x0 0xff140000 0x0 0x1000>; @@ -558,6 +577,8 @@ interrupts = ; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <5000>; resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; pinctrl-names = "gpio", "otpout"; @@ -591,16 +612,29 @@ usb_host0_ehci: usb@ff500000 { compatible = "generic-ehci"; - reg = <0x0 0xff500000 0x0 0x100>; + reg = <0x0 0xff500000 0x0 0x20000>; interrupts = ; - clocks = <&cru HCLK_USBHOST0>; - clock-names = "usbhost"; + clocks = <&cru HCLK_USBHOST0>, <&usbphy1>; + clock-names = "usbhost", "utmi"; phys = <&usbphy1>; phy-names = "usb"; status = "disabled"; }; - /* NOTE: ohci@ff520000 doesn't actually work on hardware */ + /* + * NOTE: ohci@ff520000 doesn't actually work on rk3288 + * hardware, but can work on rk3288w hardware. + */ + usb_host0_ohci: usb@ff520000 { + compatible = "generic-ohci"; + reg = <0x0 0xff520000 0x0 0x20000>; + interrupts = ; + clocks = <&cru HCLK_USBHOST0>, <&usbphy1>; + clock-names = "usbhost", "utmi"; + phys = <&usbphy1>; + phy-names = "usb"; + status = "disabled"; + }; usb_host1: usb@ff540000 { compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", @@ -626,6 +660,7 @@ g-np-tx-fifo-size = <16>; g-rx-fifo-size = <280>; g-tx-fifo-size = <256 128 128 64 32 16>; + g-use-dma; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; @@ -640,17 +675,24 @@ status = "disabled"; }; - i2c0: i2c@ff650000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff650000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; + dmc: dmc@ff610000 { + compatible = "rockchip,rk3288-dmc", "syscon"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmu>; + rockchip,sgrf = <&sgrf>; + rockchip,noc = <&noc>; + reg = <0x0 0xff610000 0x0 0x3fc + 0x0 0xff620000 0x0 0x294 + 0x0 0xff630000 0x0 0x3fc + 0x0 0xff640000 0x0 0x294>; + rockchip,sram = <&ddr_sram>; + clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>, + <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>, + <&cru ARMCLK>, <&cru ACLK_DMAC1>; + clock-names = "pclk_ddrupctl0", "pclk_publ0", + "pclk_ddrupctl1", "pclk_publ1", + "arm_clk", "aclk_dmac1"; }; i2c2: i2c@ff660000 { @@ -720,6 +762,10 @@ compatible = "rockchip,rk3066-smp-sram"; reg = <0x00 0x10>; }; + ddr_sram: ddr-sram@1000 { + compatible = "rockchip,rk3288-ddr-sram"; + reg = <0x1000 0x4000>; + }; }; sram@ff720000 { @@ -727,6 +773,76 @@ reg = <0x0 0xff720000 0x0 0x1000>; }; + qos_gpu_r: qos@ffaa0000 { + compatible = "syscon"; + reg = <0x0 0xffaa0000 0x0 0x20>; + }; + + qos_gpu_w: qos@ffaa0080 { + compatible = "syscon"; + reg = <0x0 0xffaa0080 0x0 0x20>; + }; + + qos_vio1_vop: qos@ffad0000 { + compatible = "syscon"; + reg = <0x0 0xffad0000 0x0 0x20>; + }; + + qos_vio1_isp_w0: qos@ffad0100 { + compatible = "syscon"; + reg = <0x0 0xffad0100 0x0 0x20>; + }; + + qos_vio1_isp_w1: qos@ffad0180 { + compatible = "syscon"; + reg = <0x0 0xffad0180 0x0 0x20>; + }; + + qos_vio0_vop: qos@ffad0400 { + compatible = "syscon"; + reg = <0x0 0xffad0400 0x0 0x20>; + }; + + qos_vio0_vip: qos@ffad0480 { + compatible = "syscon"; + reg = <0x0 0xffad0480 0x0 0x20>; + }; + + qos_vio0_iep: qos@ffad0500 { + compatible = "syscon"; + reg = <0x0 0xffad0500 0x0 0x20>; + }; + + qos_vio2_rga_r: qos@ffad0800 { + compatible = "syscon"; + reg = <0x0 0xffad0800 0x0 0x20>; + }; + + qos_vio2_rga_w: qos@ffad0880 { + compatible = "syscon"; + reg = <0x0 0xffad0880 0x0 0x20>; + }; + + qos_vio1_isp_r: qos@ffad0900 { + compatible = "syscon"; + reg = <0x0 0xffad0900 0x0 0x20>; + }; + + qos_video: qos@ffae0000 { + compatible = "syscon"; + reg = <0x0 0xffae0000 0x0 0x20>; + }; + + qos_hevc_r: qos@ffaf0000 { + compatible = "syscon"; + reg = <0x0 0xffaf0000 0x0 0x20>; + }; + + qos_hevc_w: qos@ffaf0080 { + compatible = "syscon"; + reg = <0x0 0xffaf0080 0x0 0x20>; + }; + pmu: power-management@ff730000 { compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; reg = <0x0 0xff730000 0x0 0x100>; @@ -737,9 +853,6 @@ #address-cells = <1>; #size-cells = <0>; - assigned-clocks = <&cru SCLK_EDP_24M>; - assigned-clock-parents = <&xin24m>; - /* * Note: Although SCLK_* are the working clocks * of device without including on the NOC, needed for @@ -787,6 +900,7 @@ <&cru PCLK_MIPI_DSI1>, <&cru SCLK_EDP_24M>, <&cru SCLK_EDP>, + <&cru SCLK_HDMI_CEC>, <&cru SCLK_ISP_JPE>, <&cru SCLK_ISP>, <&cru SCLK_RGA>; @@ -860,16 +974,20 @@ rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_NPLL>, <&cru ACLK_CPU>, - <&cru HCLK_CPU>, <&cru PCLK_CPU>, - <&cru ACLK_PERI>, <&cru HCLK_PERI>, - <&cru PCLK_PERI>; - assigned-clock-rates = <594000000>, <400000000>, - <1250000000>, <300000000>, - <150000000>, <75000000>, - <300000000>, <150000000>, - <75000000>; + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_NPLL>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>, + <&cru ACLK_VIO0>, <&cru ACLK_VIO1>, + <&cru ACLK_GPU>; + assigned-clock-rates = + <594000000>, <1250000000>, + <300000000>, <150000000>, + <75000000>, <300000000>, + <150000000>, <75000000>, + <594000000>, <297000000>, + <200000000>; }; grf: syscon@ff770000 { @@ -889,6 +1007,65 @@ status = "disabled"; }; + lvds: lvds { + compatible = "rockchip,rk3288-lvds"; + phys = <&video_phy>; + phy-names = "phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + lvds_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_lvds>; + }; + + lvds_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_lvds>; + }; + }; + }; + }; + + rgb: rgb { + compatible = "rockchip,rk3288-rgb"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcdc_rgb_pins>; + pinctrl-1 = <&lcdc_sleep_pins>; + phys = <&video_phy>; + phy-names = "phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_rgb>; + }; + + rgb_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_rgb>; + }; + }; + }; + }; + usbphy: usbphy { compatible = "rockchip,rk3288-usb-phy"; #address-cells = <1>; @@ -933,21 +1110,6 @@ status = "disabled"; }; - spdif: sound@ff88b0000 { - compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; - reg = <0x0 0xff8b0000 0x0 0x10000>; - #sound-dai-cells = <0>; - clock-names = "hclk", "mclk"; - clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; - dmas = <&dmac_bus_s 3>; - dma-names = "tx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - i2s: i2s@ff890000 { compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff890000 0x0 0x10000>; @@ -992,6 +1154,35 @@ status = "disabled"; }; + spdif: sound@ff8b0000 { + compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; + reg = <0x0 0xff8b0000 0x0 0x10000>; + #sound-dai-cells = <0>; + clock-names = "hclk", "mclk"; + clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; + dmas = <&dmac_bus_s 3>; + dma-names = "tx"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + iep: iep@ff90000 { + compatible = "rockchip,iep"; + iommu_enabled = <1>; + iommus = <&iep_mmu>; + reg = <0x0 0xff900000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk_iep", "hclk_iep"; + power-domains = <&power RK3288_PD_VIO>; + allocator = <1>; + version = <1>; + status = "disabled"; + }; + iep_mmu: iommu@ff900800 { compatible = "rockchip,iommu"; reg = <0x0 0xff900800 0x0 0x40>; @@ -1003,6 +1194,87 @@ status = "disabled"; }; + cif_isp0: cif_isp@ff910000 { + compatible = "rockchip,rk3288-cif-isp"; + rockchip,grf = <&grf>; + reg = <0x0 0xff910000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>; + reg-names = "register", "csihost-register"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, + <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>, + <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>, + <&cru SCLK_MIPIDSI_24M>; + clock-names = "aclk_isp", "hclk_isp", + "sclk_isp", "sclk_isp_jpe", + "pclk_mipi_csi", "pclk_isp_in", + "sclk_mipidsi_24m"; + resets = <&cru SRST_ISP>; + reset-names = "rst_isp"; + interrupts = ; + interrupt-names = "cif_isp10_irq"; + power-domains = <&power RK3288_PD_VIO>; + rockchip,isp,iommu-enable = <1>; + iommus = <&isp_mmu>; + status = "disabled"; + }; + + isp: isp@ff910000 { + compatible = "rockchip,rk3288-isp", "rockchip,isp"; + reg = <0x0 0xff910000 0x0 0x4000>; + interrupts = ; + power-domains = <&power RK3288_PD_VIO>; + clocks = + <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, + <&cru SCLK_ISP_JPE>, <&cru PCLK_ISP_IN>, + <&cru SCLK_VIP_OUT>, <&cru SCLK_MIPIDSI_24M>, + <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>; + clock-names = + "aclk_isp", "hclk_isp", "clk_isp", + "clk_isp_jpe", "pclkin_isp", "clk_cif_out", + "clk_mipi_24m", "clk_cif_pll", "hclk_mipiphy1"; + pinctrl-names = + "default", "isp_dvp8bit2", "isp_dvp10bit", + "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", + "isp_mipi_fl_prefl", "isp_flash_as_gpio", + "isp_flash_as_trigger_out"; + pinctrl-0 = <&isp_mipi>; + pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>; + pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>; + pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1 + &isp_dvp_d10d11>; + pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>; + pinctrl-5 = <&isp_mipi>; + pinctrl-6 = <&isp_mipi &isp_prelight>; + pinctrl-7 = <&isp_flash_trigger_as_gpio>; + pinctrl-8 = <&isp_flash_trigger>; + rockchip,isp,mipiphy = <2>; + rockchip,isp,cifphy = <1>; + rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>; + rockchip,grf = <&grf>; + rockchip,cru = <&cru>; + rockchip,gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; + rockchip,isp,iommu_enable = <1>; + iommus = <&isp_mmu>; + status = "disabled"; + }; + + rkisp1: rkisp1@ff910000 { + compatible = "rockchip,rk3288-rkisp1"; + reg = <0x0 0xff910000 0x0 0x4000>; + interrupts = ; + interrupt-names = "isp_irq"; + clocks = <&cru SCLK_ISP>, <&cru ACLK_ISP>, + <&cru HCLK_ISP>, <&cru PCLK_ISP_IN>, + <&cru SCLK_ISP_JPE>; + clock-names = "clk_isp", "aclk_isp", + "hclk_isp", "pclk_isp_in", + "sclk_isp_jpe"; + assigned-clocks = <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>; + assigned-clock-rates = <400000000>, <400000000>; + power-domains = <&power RK3288_PD_VIO>; + iommus = <&isp_mmu>; + status = "disabled"; + }; + isp_mmu: iommu@ff914000 { compatible = "rockchip,iommu"; reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; @@ -1024,10 +1296,11 @@ power-domains = <&power RK3288_PD_VIO>; resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; reset-names = "core", "axi", "ahb"; + status = "disabled"; }; vopb: vop@ff930000 { - compatible = "rockchip,rk3288-vop"; + compatible = "rockchip,rk3288-vop-big"; reg = <0x0 0xff930000 0x0 0x19c>; interrupts = ; clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; @@ -1052,15 +1325,25 @@ remote-endpoint = <&edp_in_vopb>; }; - vopb_out_mipi: endpoint@2 { + vopb_out_dsi0: endpoint@2 { reg = <2>; - remote-endpoint = <&mipi_in_vopb>; + remote-endpoint = <&dsi0_in_vopb>; }; vopb_out_lvds: endpoint@3 { reg = <3>; remote-endpoint = <&lvds_in_vopb>; }; + + vopb_out_dsi1: endpoint@4 { + reg = <4>; + remote-endpoint = <&dsi1_in_vopb>; + }; + + vopb_out_rgb: endpoint@5 { + reg = <5>; + remote-endpoint = <&rgb_in_vopb>; + }; }; }; @@ -1073,11 +1356,12 @@ clock-names = "aclk", "iface"; power-domains = <&power RK3288_PD_VIO>; #iommu-cells = <0>; + rockchip,disable-device-link-resume; status = "disabled"; }; vopl: vop@ff940000 { - compatible = "rockchip,rk3288-vop"; + compatible = "rockchip,rk3288-vop-lit"; reg = <0x0 0xff940000 0x0 0x19c>; interrupts = ; clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; @@ -1102,15 +1386,25 @@ remote-endpoint = <&edp_in_vopl>; }; - vopl_out_mipi: endpoint@2 { + vopl_out_dsi0: endpoint@2 { reg = <2>; - remote-endpoint = <&mipi_in_vopl>; + remote-endpoint = <&dsi0_in_vopl>; }; vopl_out_lvds: endpoint@3 { reg = <3>; remote-endpoint = <&lvds_in_vopl>; }; + + vopl_out_dsi1: endpoint@4 { + reg = <4>; + remote-endpoint = <&dsi1_in_vopl>; + }; + + vopl_out_rgb: endpoint@5 { + reg = <5>; + remote-endpoint = <&rgb_in_vopl>; + }; }; }; @@ -1123,15 +1417,36 @@ clock-names = "aclk", "iface"; power-domains = <&power RK3288_PD_VIO>; #iommu-cells = <0>; + rockchip,disable-device-link-resume; status = "disabled"; }; - mipi_dsi: mipi@ff960000 { + cif: cif@ff950000 { + compatible = "rockchip,cif", "rockchip,rk3288-cif"; + reg = <0x0 0xff950000 0x0 0x400>; + interrupts = ; + clocks = <&cru ACLK_VIP>, <&cru HCLK_VIP>, + <&cru PCLK_VIP_IN>, <&cru SCLK_VIP_OUT>; + clock-names = "aclk_cif0", "hclk_cif0", + "cif0_in", "cif0_out"; + resets = <&cru SRST_VIP>; + reset-names = "rst_cif"; + pinctrl-names = "cif_pin_all"; + pinctrl-0 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d10d11>; + rockchip,grf = <&grf>; + rockchip,cru = <&cru>; + power-domains = <&power RK3288_PD_VIO>; + status = "disabled"; + }; + + dsi0: dsi@ff960000 { compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x4000>; interrupts = ; clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; clock-names = "ref", "pclk"; + resets = <&cru SRST_MIPIDSI0>; + reset-names = "apb"; power-domains = <&power RK3288_PD_VIO>; rockchip,grf = <&grf>; #address-cells = <1>; @@ -1142,57 +1457,71 @@ mipi_in: port { #address-cells = <1>; #size-cells = <0>; - mipi_in_vopb: endpoint@0 { + dsi0_in_vopb: endpoint@0 { reg = <0>; - remote-endpoint = <&vopb_out_mipi>; + remote-endpoint = <&vopb_out_dsi0>; }; - mipi_in_vopl: endpoint@1 { + dsi0_in_vopl: endpoint@1 { reg = <1>; - remote-endpoint = <&vopl_out_mipi>; + remote-endpoint = <&vopl_out_dsi0>; }; }; }; }; - lvds: lvds@ff96c000 { - compatible = "rockchip,rk3288-lvds"; - reg = <0x0 0xff96c000 0x0 0x4000>; - clocks = <&cru PCLK_LVDS_PHY>; - clock-names = "pclk_lvds"; - pinctrl-names = "lcdc"; - pinctrl-0 = <&lcdc_ctl>; + dsi1: dsi@ff964000 { + compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x0 0xff964000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI1>; + clock-names = "ref", "pclk"; + resets = <&cru SRST_MIPIDSI1>; + reset-names = "apb"; power-domains = <&power RK3288_PD_VIO>; rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; - lvds_in: port@0 { - reg = <0>; - + dsi1_in: port { #address-cells = <1>; #size-cells = <0>; - lvds_in_vopb: endpoint@0 { + dsi1_in_vopb: endpoint@0 { reg = <0>; - remote-endpoint = <&vopb_out_lvds>; + remote-endpoint = <&vopb_out_dsi1>; }; - lvds_in_vopl: endpoint@1 { + dsi1_in_vopl: endpoint@1 { reg = <1>; - remote-endpoint = <&vopl_out_lvds>; + remote-endpoint = <&vopl_out_dsi1>; }; }; }; }; + video_phy: video-phy@ff96c000 { + compatible = "rockchip,rk3288-video-phy"; + reg = <0x0 0xff96c000 0x0 0x4000>; + clocks = <&cru PCLK_LVDS_PHY>; + clock-names = "pclk"; + resets = <&cru SRST_LVDS_PHY>; + reset-names = "rst"; + power-domains = <&power RK3288_PD_VIO>; + #phy-cells = <0>; + status = "disabled"; + }; + edp: dp@ff970000 { compatible = "rockchip,rk3288-dp"; reg = <0x0 0xff970000 0x0 0x4000>; interrupts = ; clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; clock-names = "dp", "pclk"; + power-domains = <&power RK3288_PD_VIO>; phys = <&edp_phy>; phy-names = "dp"; resets = <&cru SRST_EDP>; @@ -1228,6 +1557,9 @@ interrupts = ; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; clock-names = "iahb", "isfr", "cec"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hdmi_ddc>; + pinctrl-1 = <&hdmi_gpio>; power-domains = <&power RK3288_PD_VIO>; unsupported-yuv-input; status = "disabled"; @@ -1261,7 +1593,8 @@ hevc_mmu: iommu@ff9c0440 { compatible = "rockchip,iommu"; - reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; + reg = <0x0 0xff9c0440 0x0 0x40>, + <0x0 0xff9c0480 0x0 0x40>; interrupts = ; interrupt-names = "hevc_mmu"; clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; @@ -1271,21 +1604,47 @@ }; gpu: gpu@ffa30000 { - compatible = "rockchip,rk3288-mali", "arm,mali-t760"; + compatible = "arm,malit764", + "arm,malit76x", + "arm,malit7xx", + "arm,mali-midgard"; reg = <0x0 0xffa30000 0x0 0x10000>; interrupts = , , ; - interrupt-names = "job", "mmu", "gpu"; + interrupt-names = "JOB", "MMU", "GPU"; clocks = <&cru ACLK_GPU>; + clock-names = "clk_mali"; operating-points-v2 = <&gpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ power-domains = <&power RK3288_PD_GPU>; status = "disabled"; + + upthreshold = <75>; + downdifferential = <10>; + + gpu_power_model: power_model { + compatible = "arm,mali-simple-power-model"; + static-coefficient = <411000>; + dynamic-coefficient = <733>; + ts = <32000 4700 (-80) 2>; + thermal-zone = "gpu-thermal"; + }; }; - gpu_opp_table: gpu-opp-table { + gpu_opp_table: opp-table1 { compatible = "operating-points-v2"; + clocks = <&cru PLL_GPLL>; + nvmem-cells = <&performance>, <&performance_w>; + nvmem-cell-names = "performance", "performance-w"; + rockchip,bin-scaling-sel = < + 0 59 + 1 59 + 2 61 + 3 61 + >; + opp-200000000 { opp-hz = /bits/ 64 <200000000>; opp-microvolt = <950000>; @@ -1302,93 +1661,11 @@ opp-hz = /bits/ 64 <500000000>; opp-microvolt = <1200000>; }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1250000>; - }; }; - qos_gpu_r: qos@ffaa0000 { - compatible = "syscon"; - reg = <0x0 0xffaa0000 0x0 0x20>; - }; - - qos_gpu_w: qos@ffaa0080 { - compatible = "syscon"; - reg = <0x0 0xffaa0080 0x0 0x20>; - }; - - qos_vio1_vop: qos@ffad0000 { - compatible = "syscon"; - reg = <0x0 0xffad0000 0x0 0x20>; - }; - - qos_vio1_isp_w0: qos@ffad0100 { - compatible = "syscon"; - reg = <0x0 0xffad0100 0x0 0x20>; - }; - - qos_vio1_isp_w1: qos@ffad0180 { - compatible = "syscon"; - reg = <0x0 0xffad0180 0x0 0x20>; - }; - - qos_vio0_vop: qos@ffad0400 { - compatible = "syscon"; - reg = <0x0 0xffad0400 0x0 0x20>; - }; - - qos_vio0_vip: qos@ffad0480 { - compatible = "syscon"; - reg = <0x0 0xffad0480 0x0 0x20>; - }; - - qos_vio0_iep: qos@ffad0500 { - compatible = "syscon"; - reg = <0x0 0xffad0500 0x0 0x20>; - }; - - qos_vio2_rga_r: qos@ffad0800 { - compatible = "syscon"; - reg = <0x0 0xffad0800 0x0 0x20>; - }; - - qos_vio2_rga_w: qos@ffad0880 { - compatible = "syscon"; - reg = <0x0 0xffad0880 0x0 0x20>; - }; - - qos_vio1_isp_r: qos@ffad0900 { - compatible = "syscon"; - reg = <0x0 0xffad0900 0x0 0x20>; - }; - - qos_video: qos@ffae0000 { - compatible = "syscon"; - reg = <0x0 0xffae0000 0x0 0x20>; - }; - - qos_hevc_r: qos@ffaf0000 { - compatible = "syscon"; - reg = <0x0 0xffaf0000 0x0 0x20>; - }; - - qos_hevc_w: qos@ffaf0080 { - compatible = "syscon"; - reg = <0x0 0xffaf0080 0x0 0x20>; - }; - - gic: interrupt-controller@ffc01000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x0 0xffc01000 0x0 0x1000>, - <0x0 0xffc02000 0x0 0x2000>, - <0x0 0xffc04000 0x0 0x2000>, - <0x0 0xffc06000 0x0 0x2000>; - interrupts = ; + noc: syscon@ffac0000 { + compatible = "rockchip,rk3288-noc", "syscon"; + reg = <0x0 0xffac0000 0x0 0x2000>; }; nocp_core: nocp-core@ffac0400 { @@ -1427,16 +1704,52 @@ }; efuse: efuse@ffb40000 { - compatible = "rockchip,rk3288-efuse"; + compatible = "rockchip,rockchip-efuse"; reg = <0x0 0xffb40000 0x0 0x20>; #address-cells = <1>; #size-cells = <1>; clocks = <&cru PCLK_EFUSE256>; clock-names = "pclk_efuse"; - cpu_leakage: cpu_leakage@17 { + special_function: special-function@5 { + reg = <0x5 0x1>; + bits = <4 4>; + }; + package_info: package-info@5 { + reg = <0x5 0x1>; + bits = <2 2>; + }; + process_version: process-version@6 { + reg = <0x6 0x1>; + bits = <0 4>; + }; + efuse_id: id@7 { + reg = <0x7 0x10>; + }; + cpu_leakage: cpu-leakage@17 { reg = <0x17 0x1>; }; + performance_w: performance@1c { + reg = <0x1c 0x1>; + bits = <4 3>; + }; + performance: performance@1d { + reg = <0x1d 0x1>; + bits = <4 3>; + }; + }; + + gic: interrupt-controller@ffc01000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x0 0xffc01000 0x0 0x1000>, + <0x0 0xffc02000 0x0 0x2000>, + <0x0 0xffc04000 0x0 0x2000>, + <0x0 0xffc06000 0x0 0x2000>; + interrupts = ; }; rockchip_system_monitor: rockchip-system-monitor { @@ -1569,12 +1882,15 @@ }; hdmi { - hdmi_cec_c0: hdmi-cec-c0 { - rockchip,pins = <7 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; + hdmi_gpio: hdmi-gpio { + rockchip,pins = <7 19 RK_FUNC_GPIO + &pcfg_pull_none>, + <7 20 RK_FUNC_GPIO + &pcfg_pull_none>; }; - hdmi_cec_c7: hdmi-cec-c7 { - rockchip,pins = <7 RK_PC7 RK_FUNC_4 &pcfg_pull_none>; + hdmi_cec: hdmi-cec { + rockchip,pins = <7 16 RK_FUNC_2 &pcfg_pull_none>; }; hdmi_ddc: hdmi-ddc { @@ -1672,17 +1988,27 @@ <6 1 RK_FUNC_1 &pcfg_pull_none>, <6 2 RK_FUNC_1 &pcfg_pull_none>, <6 3 RK_FUNC_1 &pcfg_pull_none>, - <6 4 RK_FUNC_1 &pcfg_pull_none>, - <6 8 RK_FUNC_1 &pcfg_pull_none>; + <6 4 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s0_mclk: i2s0-mclk { + rockchip,pins = <6 8 RK_FUNC_1 &pcfg_pull_none>; }; }; lcdc { - lcdc_ctl: lcdc-ctl { - rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>, - <1 25 RK_FUNC_1 &pcfg_pull_none>, - <1 26 RK_FUNC_1 &pcfg_pull_none>, - <1 27 RK_FUNC_1 &pcfg_pull_none>; + lcdc_rgb_pins: lcdc-rgb-pins { + rockchip,pins = <1 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_DCLK */ + <1 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_DEN */ + <1 25 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_VSYNC */ + <1 24 RK_FUNC_1 &pcfg_pull_none>; /* LCDC_HSYNC */ + }; + + lcdc_sleep_pins: lcdc-sleep-pins { + rockchip,pins = <1 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */ + <1 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DEN */ + <1 25 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_VSYNC */ + <1 24 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_HSYNC */ }; }; @@ -2036,7 +2362,114 @@ rockchip,pins = ; }; }; + + isp_pin { + isp_mipi: isp-mipi { + rockchip,pins = + /* cif_clkout */ + <2 11 RK_FUNC_1 &pcfg_pull_none>; + }; + + isp_dvp_d2d9: isp-d2d9 { + rockchip,pins = + /* cif_data2 ... cif_data9 */ + <2 0 RK_FUNC_1 &pcfg_pull_none>, + <2 1 RK_FUNC_1 &pcfg_pull_none>, + <2 2 RK_FUNC_1 &pcfg_pull_none>, + <2 3 RK_FUNC_1 &pcfg_pull_none>, + <2 4 RK_FUNC_1 &pcfg_pull_none>, + <2 5 RK_FUNC_1 &pcfg_pull_none>, + <2 6 RK_FUNC_1 &pcfg_pull_none>, + <2 7 RK_FUNC_1 &pcfg_pull_none>, + /* cif_sync, cif_href */ + <2 8 RK_FUNC_1 &pcfg_pull_none>, + <2 9 RK_FUNC_1 &pcfg_pull_none>, + /* cif_clkin */ + <2 10 RK_FUNC_1 &pcfg_pull_none>; + }; + + isp_dvp_d0d1: isp-d0d1 { + rockchip,pins = + /* cif_data0, cif_data1 */ + <2 12 RK_FUNC_1 &pcfg_pull_none>, + <2 13 RK_FUNC_1 &pcfg_pull_none>; + }; + + isp_dvp_d10d11: isp-d10d11 { + rockchip,pins = + /* cif_data10, cif_data11 */ + <2 14 RK_FUNC_1 &pcfg_pull_none>, + <2 15 RK_FUNC_1 &pcfg_pull_none>; + }; + + isp_dvp_d0d7: isp-d0d7 { + rockchip,pins = + /* cif_data0 ... cif_data7 */ + <2 12 RK_FUNC_1 &pcfg_pull_none>, + <2 13 RK_FUNC_1 &pcfg_pull_none>, + <2 0 RK_FUNC_1 &pcfg_pull_none>, + <2 1 RK_FUNC_1 &pcfg_pull_none>, + <2 2 RK_FUNC_1 &pcfg_pull_none>, + <2 3 RK_FUNC_1 &pcfg_pull_none>, + <2 4 RK_FUNC_1 &pcfg_pull_none>, + <2 5 RK_FUNC_1 &pcfg_pull_none>; + }; + + isp_shutter: isp-shutter { + rockchip,pins = + /* SHUTTEREN, SHUTTERTRIG */ + <7 12 RK_FUNC_2 &pcfg_pull_none>, + <7 15 RK_FUNC_2 &pcfg_pull_none>; + }; + + isp_flash_trigger: isp-flash-trigger { + rockchip,pins = + /* ISP_FLASHTRIGOU */ + <7 13 RK_FUNC_2 &pcfg_pull_none>; + }; + + isp_prelight: isp-prelight { + rockchip,pins = + /* ISP_PRELIGHTTRIG */ + <7 14 RK_FUNC_2 &pcfg_pull_none>; + }; + + isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio { + rockchip,pins = + /* ISP_FLASHTRIGOU */ + <7 13 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + cif_pin { + cif_dvp_d0d1: cif-dvp-d0d1 { + rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>, /* cif_data0 */ + <2 13 RK_FUNC_1 &pcfg_pull_none>; /* cif_data1 */ + }; + + cif_dvp_d2d9: cif-dvp-d2d9 { + rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>, /* cif_data2 */ + <2 1 RK_FUNC_1 &pcfg_pull_none>, /* cif_data3 */ + <2 2 RK_FUNC_1 &pcfg_pull_none>, /* cif_data4 */ + <2 3 RK_FUNC_1 &pcfg_pull_none>, /* cif_data5 */ + <2 4 RK_FUNC_1 &pcfg_pull_none>, /* cif_data6 */ + <2 5 RK_FUNC_1 &pcfg_pull_none>, /* cif_data7 */ + <2 6 RK_FUNC_1 &pcfg_pull_none>, /* cif_data8 */ + <2 7 RK_FUNC_1 &pcfg_pull_none>, /* cif_data9 */ + <2 8 RK_FUNC_1 &pcfg_pull_none>, /* cif_sync */ + <2 9 RK_FUNC_1 &pcfg_pull_none>, /* cif_href */ + <2 10 RK_FUNC_1 &pcfg_pull_none>, /* cif_clkin */ + <2 11 RK_FUNC_1 &pcfg_pull_none>; /* cif_clkout */ + }; + + cif_dvp_d10d11: cif-dvp-d10d11 { + rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>, /* cif_data10 */ + <2 15 RK_FUNC_1 &pcfg_pull_none>; /* cif_data11 */ + }; + }; + }; + rockchip_suspend: rockchip-suspend { compatible = "rockchip,pm-rk3288"; status = "disabled";