diff --git a/drivers/amlogic/clk/g12a/g12a.c b/drivers/amlogic/clk/g12a/g12a.c
index ab3a65d4c453..156f66b7dc8b 100644
--- a/drivers/amlogic/clk/g12a/g12a.c
+++ b/drivers/amlogic/clk/g12a/g12a.c
@@ -654,6 +654,7 @@ static MESON_GATE(g12a_vclk2_encl, HHI_GCLK_OTHER, 23);
 static MESON_GATE(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24);
 static MESON_GATE(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25);
 static MESON_GATE(g12a_vclk2_other1, HHI_GCLK_OTHER, 26);
+static MESON_GATE(g12a_efuse, HHI_GCLK_SP_MPEG, 1);
 
 /* Array of all clocks provided by this provider */
 
@@ -742,6 +743,7 @@ static struct clk_hw *g12a_clk_hws[] = {
 	[CLKID_VCLK2_VENCLMMC]  = &g12a_vclk2_venclmmc.hw,
 	[CLKID_VCLK2_VENCL]     = &g12a_vclk2_vencl.hw,
 	[CLKID_VCLK2_OTHER1]    = &g12a_vclk2_other1.hw,
+	[CLKID_EFUSE]           = &g12a_efuse.hw,
 
 	[CLKID_CPU_FCLK_P]      = &g12a_cpu_fclk_p.hw,
 	[CLKID_CPU_CLK]         = &g12a_cpu_clk.mux.hw,
@@ -833,6 +835,7 @@ static struct clk_gate *g12a_clk_gates[] = {
 	&g12a_vclk2_venclmmc,
 	&g12a_vclk2_vencl,
 	&g12a_vclk2_other1,
+	&g12a_efuse,
 	&g12a_24m,
 	&g12a_12m_gate,
 };
diff --git a/drivers/amlogic/clk/g12a/g12a.h b/drivers/amlogic/clk/g12a/g12a.h
index 9cf4596c1a66..44ce4867e50e 100644
--- a/drivers/amlogic/clk/g12a/g12a.h
+++ b/drivers/amlogic/clk/g12a/g12a.h
@@ -44,6 +44,7 @@
 #define HHI_GCLK_MPEG1			0x144 /* 0x51 offset in data sheet */
 #define HHI_GCLK_MPEG2			0x148 /* 0x52 offset in data sheet */
 #define HHI_GCLK_OTHER			0x150 /* 0x54 offset in data sheet */
+#define HHI_GCLK_SP_MPEG		0x154 /* 0x55 offset in data sheet */
 
 #define HHI_APICALGDC_CNTL		0x168 /* 0x5a offset in data sheet */
 
diff --git a/include/dt-bindings/clock/amlogic,g12a-clkc.h b/include/dt-bindings/clock/amlogic,g12a-clkc.h
index 37fdde18d445..6cf7109d2397 100644
--- a/include/dt-bindings/clock/amlogic,g12a-clkc.h
+++ b/include/dt-bindings/clock/amlogic,g12a-clkc.h
@@ -132,7 +132,11 @@
 #define CLKID_VCLK2_VENCL       (GATE_BASE3 + 17)
 #define CLKID_VCLK2_OTHER1      (GATE_BASE3 + 18)
 
-#define GATE_AO_BASE            (GATE_BASE3 + 19)
+/*HHI_GCLK_SP_MPEG: 0x55*/
+#define GATE_BASE4              (GATE_BASE3 + 19)
+#define CLKID_EFUSE             (GATE_BASE4 + 0)
+
+#define GATE_AO_BASE            (GATE_BASE4 + 1)
 #define CLKID_AO_MEDIA_CPU      (GATE_AO_BASE + 0)
 #define CLKID_AO_AHB_SRAM       (GATE_AO_BASE + 1)
 #define CLKID_AO_AHB_BUS        (GATE_AO_BASE + 2)