From 5db5a4cf85e766ee0d72ffb8e6b86e2b44bed6e4 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Sat, 8 Jan 2022 18:14:40 +0800 Subject: [PATCH] clk: rockchip: rk3588: Fix pll rate table for 216MHz and 96MHz Signed-off-by: Finley Xiao Change-Id: I06b086dab6f1a6663804f032ad4a3ea905d4bf23 --- drivers/clk/rockchip/clk-rk3588.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index 08af0a8fe7a4..02de68ff9f0e 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -88,8 +88,8 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = { RK3588_PLL_RATE(594000000, 2, 198, 2, 0), RK3588_PLL_RATE(408000000, 2, 272, 3, 0), RK3588_PLL_RATE(312000000, 2, 208, 3, 0), - RK3588_PLL_RATE(216000000, 2, 216, 3, 0), - RK3588_PLL_RATE(96000000, 2, 216, 3, 0), + RK3588_PLL_RATE(216000000, 2, 288, 4, 0), + RK3588_PLL_RATE(96000000, 2, 256, 5, 0), { /* sentinel */ }, };