diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c
index 961b3c4c3491..5fe3f80c2266 100644
--- a/drivers/clk/rockchip/clk-rk3588.c
+++ b/drivers/clk/rockchip/clk-rk3588.c
@@ -1336,11 +1336,11 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
 	COMPOSITE_NOMUX(CLK_GPU_STACKS, "clk_gpu_stacks", "clk_gpu_src", 0,
 			RK3588_CLKSEL_CON(159), 0, 5, DFLAGS,
 			RK3588_CLKGATE_CON(66), 7, GFLAGS),
-	GATE(PCLK_PVTM2, "pclk_pvtm2", "pclk_gpu_root", 0,
+	GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_root", 0,
 			RK3588_CLKGATE_CON(66), 15, GFLAGS),
-	GATE(CLK_PVTM2, "clk_pvtm2", "xin24m", 0,
+	GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0,
 			RK3588_CLKGATE_CON(67), 0, GFLAGS),
-	GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "clk_gpu_src", 0,
+	GATE(CLK_CORE_GPU_PVTM, "clk_core_gpu_pvtm", "clk_gpu_src", 0,
 			RK3588_CLKGATE_CON(67), 1, GFLAGS),
 	GATE(PCLK_GPU_GRF, "pclk_gpu_grf", "pclk_gpu_root", CLK_IGNORE_UNUSED,
 			RK3588_CLKGATE_CON(67), 2, GFLAGS),
@@ -1381,13 +1381,13 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
 	COMPOSITE(CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc", mux_24m_32k_p, 0,
 			RK3588_CLKSEL_CON(74), 12, 1, MFLAGS, 7, 5, DFLAGS,
 			RK3588_CLKGATE_CON(30), 5, GFLAGS),
-	GATE(PCLK_PVTM1, "pclk_pvtm1", "pclk_npu_root", 0,
+	GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_root", 0,
 			RK3588_CLKGATE_CON(29), 12, GFLAGS),
 	GATE(PCLK_NPU_GRF, "pclk_npu_grf", "pclk_npu_root", CLK_IGNORE_UNUSED,
 			RK3588_CLKGATE_CON(29), 13, GFLAGS),
-	GATE(CLK_PVTM1, "clk_pvtm1", "xin24m", 0,
+	GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0,
 			RK3588_CLKGATE_CON(29), 14, GFLAGS),
-	GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "clk_npu_dsu0", 0,
+	GATE(CLK_CORE_NPU_PVTM, "clk_core_npu_pvtm", "clk_npu_dsu0", 0,
 			RK3588_CLKGATE_CON(29), 15, GFLAGS),
 	GATE(ACLK_NPU0, "aclk_npu0", "clk_npu_dsu0", 0,
 			RK3588_CLKGATE_CON(30), 6, GFLAGS),
@@ -2349,16 +2349,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
 	COMPOSITE(CLK_CR_PARA, "clk_cr_para", mux_24m_ppll_spll_p, 0,
 			RK3588_PMU_CLKSEL_CON(15), 5, 2, MFLAGS, 0, 5, DFLAGS,
 			RK3588_PMU_CLKGATE_CON(4), 11, GFLAGS),
-	COMPOSITE(CLK_HDPTX0_REF_XTAL, "clk_hdptx0_ref_xtal", mux_24m_ppll_p, CLK_IS_CRITICAL,
-			RK3588_PMU_CLKSEL_CON(12), 11, 1, MFLAGS, 6, 5, DFLAGS,
-			RK3588_PMU_CLKGATE_CON(3), 11, GFLAGS),
-	COMPOSITE(CLK_REF_MIPI_DCPHY0, "clk_ref_mipi_dcphy0", mux_24m_ppll_spll_p, CLK_IS_CRITICAL,
-			RK3588_PMU_CLKSEL_CON(14), 7, 2, MFLAGS, 0, 7, DFLAGS,
-			RK3588_PMU_CLKGATE_CON(4), 3, GFLAGS),
-	COMPOSITE(CLK_OTGPHY_U3_0, "clk_otgphy_u3_0", mux_24m_ppll_p, CLK_IS_CRITICAL,
+	COMPOSITE(CLK_USB2PHY_HDPTXRXPHY_REF, "clk_usb2phy_hdptxrxphy_ref", mux_24m_ppll_p, CLK_IS_CRITICAL,
 			RK3588_PMU_CLKSEL_CON(14), 14, 1, MFLAGS, 9, 5, DFLAGS,
 			RK3588_PMU_CLKGATE_CON(4), 7, GFLAGS),
-	COMPOSITE(CLK_USBDP_PHY0_REF_XTAL, "clk_usbdp_phy0_ref_xtal", mux_24m_ppll_p, CLK_IS_CRITICAL,
+	COMPOSITE(CLK_USBDPPHY_MIPIDCPPHY_REF, "clk_usbdpphy_mipidcpphy_ref", mux_24m_ppll_p, CLK_IS_CRITICAL,
 			RK3588_PMU_CLKSEL_CON(9), 10, 1, MFLAGS, 5, 5, DFLAGS,
 			RK3588_PMU_CLKGATE_CON(3), 5, GFLAGS),
 };
diff --git a/include/dt-bindings/clock/rk3588-cru.h b/include/dt-bindings/clock/rk3588-cru.h
index 2f046f048a83..d8d2b7fc3a28 100644
--- a/include/dt-bindings/clock/rk3588-cru.h
+++ b/include/dt-bindings/clock/rk3588-cru.h
@@ -277,9 +277,9 @@
 #define CLK_GPU				276
 #define CLK_GPU_COREGROUP		277
 #define CLK_GPU_STACKS			278
-#define PCLK_PVTM2			279
-#define CLK_PVTM2			280
-#define CLK_GPU_PVTM			281
+#define PCLK_GPU_PVTM			279
+#define CLK_GPU_PVTM			280
+#define CLK_CORE_GPU_PVTM		281
 #define PCLK_GPU_GRF			282
 #define ACLK_ISP1_ROOT			283
 #define HCLK_ISP1_ROOT			284
@@ -295,10 +295,10 @@
 #define HCLK_NPU_CM0_ROOT		294
 #define FCLK_NPU_CM0_CORE		295
 #define CLK_NPU_CM0_RTC			296
-#define PCLK_PVTM1			297
+#define PCLK_NPU_PVTM			297
 #define PCLK_NPU_GRF			298
-#define CLK_PVTM1			299
-#define CLK_NPU_PVTM			300
+#define CLK_NPU_PVTM			299
+#define CLK_CORE_NPU_PVTM		300
 #define ACLK_NPU0			301
 #define HCLK_NPU0			302
 #define HCLK_NPU_ROOT			303
@@ -684,10 +684,8 @@
 #define PCLK_PMU1WDT			688
 #define TCLK_PMU1WDT			689
 #define CLK_CR_PARA			690
-#define CLK_HDPTX0_REF_XTAL		691
-#define CLK_REF_MIPI_DCPHY0		692
-#define CLK_OTGPHY_U3_0			693
-#define CLK_USBDP_PHY0_REF_XTAL		694
+#define CLK_USB2PHY_HDPTXRXPHY_REF	693
+#define CLK_USBDPPHY_MIPIDCPPHY_REF	694
 #define CLK_REF_PIPE_PHY0_OSC_SRC	695
 #define CLK_REF_PIPE_PHY1_OSC_SRC	696
 #define CLK_REF_PIPE_PHY2_OSC_SRC	697
@@ -1006,9 +1004,9 @@
 #define SRST_NPUTIMER1			473
 #define SRST_P_NPU_WDT			474
 #define SRST_T_NPU_WDT			475
-#define SRST_P_PVTM1			476
+#define SRST_P_NPU_PVTM			476
 #define SRST_P_NPU_GRF			477
-#define SRST_PVTM1			478
+#define SRST_NPU_PVTM			478
 /********Name=SOFTRST_CON30,Offset=0xA78********/
 #define SRST_NPU_PVTPLL			480
 #define SRST_H_NPU_CM0_BIU		482
@@ -1276,9 +1274,9 @@
 #define SRST_A_M2_GPU_BIU		1067
 #define SRST_A_M3_GPU_BIU		1068
 #define SRST_P_GPU_BIU			1070
-#define SRST_P_PVTM2			1071
+#define SRST_P_GPU_PVTM			1071
 /********Name=SOFTRST_CON67,Offset=0xB0C********/
-#define SRST_PVTM2			1072
+#define SRST_GPU_PVTM			1072
 #define SRST_P_GPU_GRF			1074
 #define SRST_GPU_PVTPLL			1075
 #define SRST_GPU_JTAG			1076