From 5e1410d56b070f24e94c0de357c26ffbe2df6df3 Mon Sep 17 00:00:00 2001 From: Jiyu Yang Date: Sat, 28 Oct 2017 16:04:54 +0800 Subject: [PATCH] clk: fixed gp0_pll spell error PD#151164: fixed gp0_pll spell error Change-Id: I06b0c03492ad97260a1a12ca9f3882a8ec579388 Signed-off-by: Jiyu Yang --- arch/arm64/boot/dts/amlogic/mesongxbb-gpu-mali450.dtsi | 6 +++--- arch/arm64/boot/dts/amlogic/mesongxm-gpu-t82x.dtsi | 4 ++-- arch/arm64/boot/dts/amlogic/mesongxtvbb-gpu-t83x.dtsi | 4 ++-- drivers/amlogic/clk/gxl/clk_gpu.c | 4 ++-- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/mesongxbb-gpu-mali450.dtsi b/arch/arm64/boot/dts/amlogic/mesongxbb-gpu-mali450.dtsi index 0d744c321c96..b04c6d9e0563 100644 --- a/arch/arm64/boot/dts/amlogic/mesongxbb-gpu-mali450.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesongxbb-gpu-mali450.dtsi @@ -27,7 +27,7 @@ 0x0 0x0 0x0 0x1 0x2 0x0>; pmu_switch_delay = <0xffff> ; num_of_pp = <3> ; - def_clk = <2> ; + def_clk = <4> ; sc_mpp = <3>;/* number of pp used most of time.*/ tbl = <&clk125_cfg &clk285_cfg @@ -36,8 +36,8 @@ &clk666_cfg &clk800_cfg>; - clocks = <&clkc CLKID_GPU_MUX>; - clock-names = "gpu_mux"; + clocks = <&clkc CLKID_GPU_MUX &clkc CLKID_GP0_PLL>; + clock-names = "gpu_mux","gp0_pll"; /*control_interval x keep_count == 900 - 1000ms */ control_interval = <200>; diff --git a/arch/arm64/boot/dts/amlogic/mesongxm-gpu-t82x.dtsi b/arch/arm64/boot/dts/amlogic/mesongxm-gpu-t82x.dtsi index a67f1d5da27c..042cd90bbf59 100644 --- a/arch/arm64/boot/dts/amlogic/mesongxm-gpu-t82x.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesongxm-gpu-t82x.dtsi @@ -40,8 +40,8 @@ &dvfs666_cfg &dvfs750_cfg>; - clocks = <&clkc CLKID_GPU_MUX>; - clock-names = "gpu_mux"; + clocks = <&clkc CLKID_GPU_MUX &clkc CLKID_GP0_PLL>; + clock-names = "gpu_mux","gp0_pll"; dvfs125_cfg:clk125_cfg { clk_freq = <125000000>; diff --git a/arch/arm64/boot/dts/amlogic/mesongxtvbb-gpu-t83x.dtsi b/arch/arm64/boot/dts/amlogic/mesongxtvbb-gpu-t83x.dtsi index 5b02ca965204..01a5586c04fa 100644 --- a/arch/arm64/boot/dts/amlogic/mesongxtvbb-gpu-t83x.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesongxtvbb-gpu-t83x.dtsi @@ -40,8 +40,8 @@ &dvfs666_cfg &dvfs666_cfg>; - clocks = <&clkc CLKID_GPU_MUX>; - clock-names = "gpu_mux"; + clocks = <&clkc CLKID_GPU_MUX &clkc CLKID_GP0_PLL>; + clock-names = "gpu_mux","gp0_pll"; dvfs125_cfg:clk125_cfg { clk_freq = <125000000>; diff --git a/drivers/amlogic/clk/gxl/clk_gpu.c b/drivers/amlogic/clk/gxl/clk_gpu.c index 131cf0328d5a..f7c06bf70879 100644 --- a/drivers/amlogic/clk/gxl/clk_gpu.c +++ b/drivers/amlogic/clk/gxl/clk_gpu.c @@ -26,8 +26,8 @@ #include "../clkc.h" #include "gxl.h" -const char *gpu_parent_names[] = { "xtal", "gp0", "mpll2", "mpll1", "fclk_div7", - "fclk_div4", "fclk_div3", "fclk_div5"}; +const char *gpu_parent_names[] = { "xtal", "gp0_pll", "mpll2", "mpll1", + "fclk_div7", "fclk_div4", "fclk_div3", "fclk_div5"}; static struct clk_mux gpu_p0_mux = { .reg = (void *)HHI_MALI_CLK_CNTL,