From 5e2e107ee608ba0b8e27da1af28597da5e0ee2eb Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Fri, 8 Nov 2019 20:14:48 +0800
Subject: [PATCH] arm64: dts: rockchip: px30: add SFC node

Change-Id: Ia7ef02ee734f148deb2b626526c3cb615e9daaf2
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/px30.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index b958c5d08728..5a43a617a30f 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -41,6 +41,7 @@
 		serial5 = &uart5;
 		spi0 = &spi0;
 		spi1 = &spi1;
+		spi2 = &sfc;
 	};
 
 	cpus {
@@ -1422,6 +1423,17 @@
 		status = "disabled";
 	};
 
+	sfc: spi@ff3a0000 {
+		compatible = "rockchip,sfc";
+		reg = <0x0 0xff3a0000 0x0 0x4000>;
+		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+		clock-names = "clk_sfc", "hclk_sfc";
+		assigned-clocks = <&cru SCLK_SFC>;
+		assigned-clock-rates = <100000000>;
+		status = "disabled";
+	};
+
 	nandc0: nandc@ff3b0000 {
 		compatible = "rockchip,rk-nandc";
 		reg = <0x0 0xff3b0000 0x0 0x4000>;