From 5e3370fa00f32dc3567ad012697d2d5044af9610 Mon Sep 17 00:00:00 2001 From: Xinhuang Li Date: Tue, 24 Apr 2018 19:37:22 +0800 Subject: [PATCH] clk: rockchip: rk3368: set true clk for spdif the mux_spdif_8ch_p is composed of spdif_8ch_src not spdif_8ch_pre Change-Id: I7dd40e35078b2d012af2c777de763d14e93c3d4e Signed-off-by: Xinhuang Li --- drivers/clk/rockchip/clk-rk3368.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c index 975ae6006536..39ec324e2fd3 100644 --- a/drivers/clk/rockchip/clk-rk3368.c +++ b/drivers/clk/rockchip/clk-rk3368.c @@ -139,7 +139,7 @@ PNAME(mux_i2s_8ch_pre_p) = { "i2s_8ch_src", "i2s_8ch_frac", PNAME(mux_i2s_8ch_clkout_p) = { "i2s_8ch_pre", "xin12m" }; PNAME(mux_i2s_2ch_p) = { "i2s_2ch_src", "i2s_2ch_frac", "dummy", "xin12m" }; -PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac", +PNAME(mux_spdif_8ch_p) = { "spdif_8ch_src", "spdif_8ch_frac", "ext_i2s", "xin12m" }; PNAME(mux_edp_24m_p) = { "xin24m", "dummy" }; PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };