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clk: fix mpll3 jitter too large

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PD#142470: fix mpll3 jitter too large

Change-Id: I106bf9c627a0125ec61ec221d02c0689e547c965
Signed-off-by: Yun Cai <yun.cai@amlogic.com>
This commit is contained in:
Yun Cai
2017-06-12 17:02:36 +08:00
parent d39d45ead6
commit 5e57727788
1 changed files with 2 additions and 0 deletions
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2
drivers/amlogic/clk/clk-mpll.c
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@@ -115,12 +115,14 @@ static int mpll_set_rate(struct clk_hw *hw, unsigned long rate,
reg = PARM_SET(p->width, p->shift, reg, n2);
reg = PARM_SET(1, mpll->sdm_en, reg, 1);
reg = PARM_SET(1, mpll->en_dds, reg, 1);
#if 0
if (!strcmp(clk_hw_get_name(hw), "mpll3"))
/* MPLL_CNTL10 bit14 should be set together
* with MPLL3_CNTL0 bit0
*/
writel(readl(mpll->base + p->reg_off - 0x3c) |
0x1<<14, mpll->base + p->reg_off - 0x3c);
#endif
writel(reg, mpll->base + p->reg_off);
/* mpll top misc for cpu after txlx */
if (mpll->top_misc_reg)