From 5e89a41104f0a18228c10d78c579d14a9be02bd3 Mon Sep 17 00:00:00 2001
From: Wu Liangqing <wlq@rock-chips.com>
Date: Fri, 24 Aug 2018 14:44:47 +0800
Subject: [PATCH] arm: dts: rockchip: rk312x: remove PLL_CPLL set in cru

cpll just for display no need to init. init will result in dispaly error
in next-dev uboot

Change-Id: Ie63c8d44aa6b54fb81abfb3a32d71995b8426c7d
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
---
 arch/arm/boot/dts/rk312x.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/rk312x.dtsi b/arch/arm/boot/dts/rk312x.dtsi
index 6fa1c69350dc..d0e7b12fb106 100644
--- a/arch/arm/boot/dts/rk312x.dtsi
+++ b/arch/arm/boot/dts/rk312x.dtsi
@@ -820,11 +820,11 @@
 		rockchip,grf = <&grf>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
-		assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+		assigned-clocks = <&cru PLL_GPLL>,
 				  <&cru ACLK_CPU>, <&cru HCLK_CPU>,
 				  <&cru PCLK_CPU>, <&cru ACLK_PERI>,
 				  <&cru HCLK_PERI>, <&cru PCLK_PERI>;
-		assigned-clock-rates = <594000000>, <400000000>,
+		assigned-clock-rates = <594000000>,
 				       <300000000>, <150000000>,
 				       <75000000>, <300000000>,
 				       <150000000>, <75000000>;