diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson-clkc.txt index 651860382060..d9b8a3da5da5 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,meson-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,meson-clkc.txt @@ -22,6 +22,9 @@ Required Properties: "amlogic,tl1-clkc" - for tl1 ee clock "amlogic,tl1-aoclkc" - for tl1 ao clock "amlogic,tl1-measure" - for tl1 clock measurement + "amlogic,sm1-clkc-1" - for sm1 ee part1 clock + "amlogic,sm1-clkc-2" - for sm1 ee part2 clock + "amlogic,sm1-aoclkc" - for sm1 ao clock - reg: physical base address of the clock controller and length of memory mapped region. diff --git a/MAINTAINERS b/MAINTAINERS index 982e1bc9d9ec..b29568b57d86 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14815,3 +14815,7 @@ F: arch/arm64/boot/dts/amlogic/mesongsm1.dtsi F: arch/arm64/boot/dts/amlogic/sm1_pxp.dts F: arch/arm/boot/dts/amlogic/mesonsm1.dtsi F: arch/arm/boot/dts/amlogic/sm1_pxp.dts + +AMLOGIC SM1 CLOCK DRIVERS +M: Shunzhou Jiang +F: drivers/amlogic/clk/sm1/* diff --git a/arch/arm/boot/dts/amlogic/mesonsm1.dtsi b/arch/arm/boot/dts/amlogic/mesonsm1.dtsi index 8f19bcca50f4..37343bf85e5a 100644 --- a/arch/arm/boot/dts/amlogic/mesonsm1.dtsi +++ b/arch/arm/boot/dts/amlogic/mesonsm1.dtsi @@ -665,9 +665,9 @@ }; aoclkc: clock-controller@0 { - compatible = "amlogic,g12a-aoclkc"; + compatible = "amlogic,sm1-aoclkc"; #clock-cells = <1>; - reg = <0x0 0x320>; + reg = <0x0 0x3dc>; }; pwm_AO_ab: pwm@7000 { @@ -765,9 +765,15 @@ ranges = <0x0 0xff63c000 0x2000>; clkc: clock-controller@0 { - compatible = "amlogic,g12a-clkc"; + compatible = "amlogic,sm1-clkc-1"; #clock-cells = <1>; - reg = <0x0 0x320>; + reg = <0x0 0x3dc>; + }; + + clkc_b: clock-controller@1 { + compatible = "amlogic,sm1-clkc-2"; + #clock-cells = <1>; + reg = <0x0 0x3dc>; }; };/* end of hiubus*/ diff --git a/arch/arm64/boot/dts/amlogic/mesonsm1.dtsi b/arch/arm64/boot/dts/amlogic/mesonsm1.dtsi index ee0cf0c11663..42f3cd8fd4ba 100644 --- a/arch/arm64/boot/dts/amlogic/mesonsm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesonsm1.dtsi @@ -665,9 +665,9 @@ }; aoclkc: clock-controller@0 { - compatible = "amlogic,g12a-aoclkc"; + compatible = "amlogic,sm1-aoclkc"; #clock-cells = <1>; - reg = <0x0 0x0 0x0 0x320>; + reg = <0x0 0x0 0x0 0x3dc>; }; pwm_AO_ab: pwm@7000 { @@ -765,9 +765,15 @@ ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>; clkc: clock-controller@0 { - compatible = "amlogic,g12a-clkc"; + compatible = "amlogic,sm1-clkc-1"; #clock-cells = <1>; - reg = <0x0 0x0 0x0 0x320>; + reg = <0x0 0x0 0x0 0x3dc>; + }; + + clkc_b: clock-controller@1 { + compatible = "amlogic,sm1-clkc-2"; + #clock-cells = <1>; + reg = <0x0 0x0 0x0 0x3dc>; }; };/* end of hiubus*/ diff --git a/drivers/amlogic/clk/Makefile b/drivers/amlogic/clk/Makefile index 77fdb66e5b07..95486a70024a 100644 --- a/drivers/amlogic/clk/Makefile +++ b/drivers/amlogic/clk/Makefile @@ -18,5 +18,6 @@ obj-$(CONFIG_AMLOGIC_GX_CLK) += txl/ obj-$(CONFIG_AMLOGIC_GX_CLK) += g12a/ obj-$(CONFIG_AMLOGIC_GX_CLK) += g12b/ obj-$(CONFIG_AMLOGIC_GX_CLK) += tl1/ +obj-$(CONFIG_AMLOGIC_GX_CLK) += sm1/ obj-$(CONFIG_AMLOGIC_M8B_CLK) += m8b/ diff --git a/drivers/amlogic/clk/g12a/g12a.c b/drivers/amlogic/clk/g12a/g12a.c index 1364835d50c5..af48752f663e 100644 --- a/drivers/amlogic/clk/g12a/g12a.c +++ b/drivers/amlogic/clk/g12a/g12a.c @@ -1027,6 +1027,20 @@ static void __init g12a_clkc_init(struct device_node *np) __func__); goto iounmap; } + + if (of_property_read_bool(np, "own-dsu-clk")) { + if (clks[CLKID_DSU_CLK]) { + clk_set_parent(clks[CLKID_DSU_CLK], + clks[CLKID_CPU_CLK]); + /* set sm1_dsu_pre_clk to 1.5G, gp1 pll is 1.5G */ + clk_set_rate(clks[CLKID_DSU_PRE_CLK], 1500000000); + clk_prepare_enable(clks[CLKID_DSU_PRE_CLK]); + /* set sm1_dsu_pre_clk as dsu_pre's parent */ + clk_set_parent(clks[CLKID_DSU_CLK], + clks[CLKID_DSU_PRE_CLK]); + } + } + pr_debug("%s: cpu clk register notifier ok!", __func__); ret = of_clk_add_provider(np, of_clk_src_onecell_get, @@ -1045,4 +1059,5 @@ iounmap: CLK_OF_DECLARE(g12a, "amlogic,g12a-clkc", g12a_clkc_init); CLK_OF_DECLARE(g12b, "amlogic,g12b-clkc-1", g12a_clkc_init); +CLK_OF_DECLARE(sm1, "amlogic,sm1-clkc-1", g12a_clkc_init); diff --git a/drivers/amlogic/clk/g12a/g12a_ao.c b/drivers/amlogic/clk/g12a/g12a_ao.c index 6ea40b9d4be8..40319856b59e 100644 --- a/drivers/amlogic/clk/g12a/g12a_ao.c +++ b/drivers/amlogic/clk/g12a/g12a_ao.c @@ -145,5 +145,6 @@ static void __init g12a_aoclkc_init(struct device_node *np) CLK_OF_DECLARE(g12a, "amlogic,g12a-aoclkc", g12a_aoclkc_init); CLK_OF_DECLARE(g12b, "amlogic,g12b-aoclkc", g12a_aoclkc_init); +CLK_OF_DECLARE(sm1, "amlogic,sm1-aoclkc", g12a_aoclkc_init); diff --git a/drivers/amlogic/clk/g12a/g12a_clk-pll.c b/drivers/amlogic/clk/g12a/g12a_clk-pll.c index 505a6aa81024..1deab0e0b1c0 100644 --- a/drivers/amlogic/clk/g12a/g12a_clk-pll.c +++ b/drivers/amlogic/clk/g12a/g12a_clk-pll.c @@ -363,7 +363,8 @@ static int meson_g12a_pll_set_rate(struct clk_hw *hw, unsigned long rate, writel(G12A_PLL_CNTL6, cntlbase + (unsigned long)(6*4)); udelay(10); - } else if (!strcmp(clk_hw_get_name(hw), "gp0_pll")) { + } else if (!strcmp(clk_hw_get_name(hw), "gp0_pll") + || !strcmp(clk_hw_get_name(hw), "gp1_pll")) { writel((readl(cntlbase) | MESON_PLL_RESET) & (~MESON_PLL_ENABLE), cntlbase); writel(G12A_GP0_PLL_CNTL1, @@ -487,6 +488,7 @@ static int meson_g12a_pll_enable(struct clk_hw *hw) } if (!strcmp(clk_hw_get_name(hw), "gp0_pll") + || !strcmp(clk_hw_get_name(hw), "gp1_pll") || !strcmp(clk_hw_get_name(hw), "hifi_pll") || !strcmp(clk_hw_get_name(hw), "pcie_pll") || !strcmp(clk_hw_get_name(hw), "sys_pll") diff --git a/drivers/amlogic/clk/sm1/Makefile b/drivers/amlogic/clk/sm1/Makefile new file mode 100644 index 000000000000..e36dd8e5ef2d --- /dev/null +++ b/drivers/amlogic/clk/sm1/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for Meson SM1 clk +# + +obj-$(CONFIG_AMLOGIC_GX_CLK) += sm1.o diff --git a/drivers/amlogic/clk/sm1/sm1.c b/drivers/amlogic/clk/sm1/sm1.c new file mode 100644 index 000000000000..18698c42cf3c --- /dev/null +++ b/drivers/amlogic/clk/sm1/sm1.c @@ -0,0 +1,292 @@ +/* + * drivers/amlogic/clk/sm1/sm1.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "../clkc.h" +#include "../g12a/g12a.h" +#include "sm1.h" + +static struct meson_clk_pll sm1_gp1_pll = { + .m = { + .reg_off = HHI_GP1_PLL_CNTL0, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_GP1_PLL_CNTL0, + .shift = 10, + .width = 5, + }, + .od = { + .reg_off = HHI_GP1_PLL_CNTL0, + .shift = 16, + .width = 3, + }, + .rate_table = g12a_pll_rate_table, + .rate_count = ARRAY_SIZE(g12a_pll_rate_table), + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "gp1_pll", + .ops = &meson_g12a_pll_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + }, +}; + +static struct clk_mux sm1_dsu_pre_src_clk_mux0 = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL5, + .mask = 0x3, + .shift = 0, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "dsu_pre_src0", + .ops = &clk_mux_ops, + .parent_names = (const char *[]){ "xtal", "fclk_div2", + "fclk_div3", "gp1_pll" }, + .num_parents = 4, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + }, +}; + +static struct clk_mux sm1_dsu_pre_src_clk_mux1 = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL5, + .mask = 0x3, + .shift = 16, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "dsu_pre_src1", + .ops = &clk_mux_ops, + .parent_names = (const char *[]){ "xtal", "fclk_div2", + "fclk_div3", "gp1_pll" }, + .num_parents = 4, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + }, +}; + +static struct clk_divider sm1_dsu_clk_div0 = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL5, + .shift = 4, + .width = 5, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "dsu_clk_div0", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "dsu_pre_src0" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_divider sm1_dsu_clk_div1 = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL5, + .shift = 20, + .width = 5, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "dsu_clk_div1", + .ops = &clk_divider_ops, + .parent_names = (const char *[]){ "dsu_pre_src1" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_mux sm1_dsu_pre_clk_mux0 = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL5, + .mask = 0x1, + .shift = 2, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "dsu_pre0", + .ops = &clk_mux_ops, + .parent_names = (const char *[]){ "dsu_pre_src0", + "dsu_clk_div0",}, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + }, +}; + +static struct clk_mux sm1_dsu_pre_clk_mux1 = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL5, + .mask = 0x1, + .shift = 18, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "dsu_pre1", + .ops = &clk_mux_ops, + .parent_names = (const char *[]){ "dsu_pre_src1", + "dsu_clk_div1",}, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + }, +}; + +static struct clk_mux sm1_dsu_pre_post_clk_mux = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL5, + .mask = 0x1, + .shift = 10, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "dsu_pre_post", + .ops = &clk_mux_ops, + .parent_names = (const char *[]){ "dsu_pre0", + "dsu_pre1",}, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + }, +}; + +static struct clk_mux sm1_dsu_pre_clk = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL5, + .mask = 0x1, + .shift = 11, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "dsu_pre_clk", + .ops = &clk_mux_ops, + .parent_names = (const char *[]){ "dsu_pre_post", + "sys_pll",}, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + }, +}; + +static struct clk_mux sm1_dsu_clk = { + .reg = (void *)HHI_SYS_CPU_CLK_CNTL6, + .mask = 0x1, + .shift = 11, + .lock = &clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "dsu_clk", + .ops = &clk_mux_ops, + .parent_names = (const char *[]){ "cpu_clk", + "dsu_pre_clk",}, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct meson_clk_pll *const sm1_clk_plls[] = { + &sm1_gp1_pll, +}; + +static struct clk_hw *sm1_clk_hws[] = { + [CLKID_GP1_PLL - CLKID_SM1_ADD_BASE] = &sm1_gp1_pll.hw, + [CLKID_DSU_PRE_SRC0 - CLKID_SM1_ADD_BASE] = + &sm1_dsu_pre_src_clk_mux0.hw, + [CLKID_DSU_PRE_SRC1 - CLKID_SM1_ADD_BASE] = + &sm1_dsu_pre_src_clk_mux1.hw, + [CLKID_DSU_CLK_DIV0 - CLKID_SM1_ADD_BASE] = + &sm1_dsu_clk_div0.hw, + [CLKID_DSU_CLK_DIV1 - CLKID_SM1_ADD_BASE] = + &sm1_dsu_clk_div1.hw, + [CLKID_DSU_PRE_MUX0 - CLKID_SM1_ADD_BASE] = + &sm1_dsu_pre_clk_mux0.hw, + [CLKID_DSU_PRE_MUX1 - CLKID_SM1_ADD_BASE] = + &sm1_dsu_pre_clk_mux1.hw, + [CLKID_DSU_PRE_POST_MUX - CLKID_SM1_ADD_BASE] = + &sm1_dsu_pre_post_clk_mux.hw, + [CLKID_DSU_PRE_CLK - CLKID_SM1_ADD_BASE] = + &sm1_dsu_pre_clk.hw, + [CLKID_DSU_CLK - CLKID_SM1_ADD_BASE] = &sm1_dsu_clk.hw, +}; + +static void __init sm1_clkc_init(struct device_node *np) +{ + int ret = 0, clkid, i; + + if (!clk_base) + clk_base = of_iomap(np, 0); + if (!clk_base) { + pr_err("%s: Unable to map clk base\n", __func__); + return; + } + for (i = 0; i < ARRAY_SIZE(sm1_clk_plls); i++) + sm1_clk_plls[i]->base = clk_base; + + sm1_dsu_pre_src_clk_mux0.reg = clk_base + + (unsigned long)sm1_dsu_pre_src_clk_mux0.reg; + sm1_dsu_pre_src_clk_mux1.reg = clk_base + + (unsigned long)sm1_dsu_pre_src_clk_mux1.reg; + sm1_dsu_clk_div0.reg = clk_base + + (unsigned long)sm1_dsu_clk_div0.reg; + sm1_dsu_clk_div1.reg = clk_base + + (unsigned long)sm1_dsu_clk_div1.reg; + sm1_dsu_pre_clk_mux0.reg = clk_base + + (unsigned long)sm1_dsu_pre_clk_mux0.reg; + sm1_dsu_pre_clk_mux1.reg = clk_base + + (unsigned long)sm1_dsu_pre_clk_mux1.reg; + sm1_dsu_pre_post_clk_mux.reg = clk_base + + (unsigned long)sm1_dsu_pre_post_clk_mux.reg; + sm1_dsu_pre_clk.reg = clk_base + + (unsigned long)sm1_dsu_pre_clk.reg; + sm1_dsu_clk.reg = clk_base + + (unsigned long)sm1_dsu_clk.reg; + if (!clks) { + clks = kzalloc(NR_CLKS*sizeof(struct clk *), GFP_KERNEL); + if (!clks) { + pr_err("%s: alloc clks fail!", __func__); + return; + } + clk_numbers = NR_CLKS; + } + + /* + * register all clks + */ + + for (clkid = 0; clkid < ARRAY_SIZE(sm1_clk_hws); clkid++) { + if (sm1_clk_hws[clkid]) { + clks[clkid + CLKID_SM1_ADD_BASE] + = clk_register(NULL, sm1_clk_hws[clkid]); + if (IS_ERR(clks[clkid + CLKID_SM1_ADD_BASE])) { + pr_err("%s: failed to register %s\n", __func__, + clk_hw_get_name(sm1_clk_hws[clkid])); + goto iounmap; + } + } + } + + if (clks[CLKID_CPU_CLK]) { + if (!of_property_read_bool(np, "own-dsu-clk")) + return; + /* set cpu clk as dsu_clk's parent*/ + clk_set_parent(sm1_dsu_clk.hw.clk, clks[CLKID_CPU_CLK]); + /* set sm1_dsu_pre_clk to 1.5G, gp1 pll is 1.5G */ + clk_set_rate(sm1_dsu_pre_clk.hw.clk, 1500000000); + clk_prepare_enable(sm1_dsu_pre_clk.hw.clk); + /* set sm1_dsu_pre_clk as dsu_clk's parent */ + clk_set_parent(sm1_dsu_clk.hw.clk, sm1_dsu_pre_clk.hw.clk); + } + return; + +iounmap: + iounmap(clk_base); + pr_info("%s: %d: ret: %d\n", __func__, __LINE__, ret); +} + +CLK_OF_DECLARE(sm1, "amlogic,sm1-clkc-2", sm1_clkc_init); + + diff --git a/drivers/amlogic/clk/sm1/sm1.h b/drivers/amlogic/clk/sm1/sm1.h new file mode 100644 index 000000000000..d937329277bd --- /dev/null +++ b/drivers/amlogic/clk/sm1/sm1.h @@ -0,0 +1,33 @@ +/* + * drivers/amlogic/clk/sm1/sm1.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __SM1_H +#define __SM1_H + +/* + * Clock controller register offsets + * + * Register offsets from the data sheet are listed in comment blocks below. + * Those offsets must be multiplied by 4 before adding them to the base address + * to get the right value + */ + +#define HHI_GP1_PLL_CNTL0 0x60 /* 0x18 offset in data sheet */ +#define HHI_SYS_CPU_CLK_CNTL5 0x21C /* 0x87 offset in data sheet */ +#define HHI_SYS_CPU_CLK_CNTL6 0x220 /* 0x88 offset in data sheet */ + +#endif /* __SM1_H */ diff --git a/include/dt-bindings/clock/amlogic,g12a-clkc.h b/include/dt-bindings/clock/amlogic,g12a-clkc.h index 5c1f32477c5f..d9d8a61b11f8 100644 --- a/include/dt-bindings/clock/amlogic,g12a-clkc.h +++ b/include/dt-bindings/clock/amlogic,g12a-clkc.h @@ -297,7 +297,19 @@ #define CLKID_MIPI_CSI_PHY_MUX (CLKID_G12B_ADD_BASE + 16) #define CLKID_SYS1_PLL (CLKID_G12B_ADD_BASE + 17) -#define CLKID_AO_BASE (CLKID_G12B_ADD_BASE + 18) +#define CLKID_SM1_ADD_BASE (CLKID_G12B_ADD_BASE + 18) +#define CLKID_GP1_PLL (CLKID_SM1_ADD_BASE + 0) +#define CLKID_DSU_PRE_SRC0 (CLKID_SM1_ADD_BASE + 1) +#define CLKID_DSU_PRE_SRC1 (CLKID_SM1_ADD_BASE + 2) +#define CLKID_DSU_CLK_DIV0 (CLKID_SM1_ADD_BASE + 3) +#define CLKID_DSU_CLK_DIV1 (CLKID_SM1_ADD_BASE + 4) +#define CLKID_DSU_PRE_MUX0 (CLKID_SM1_ADD_BASE + 5) +#define CLKID_DSU_PRE_MUX1 (CLKID_SM1_ADD_BASE + 6) +#define CLKID_DSU_PRE_POST_MUX (CLKID_SM1_ADD_BASE + 7) +#define CLKID_DSU_PRE_CLK (CLKID_SM1_ADD_BASE + 8) +#define CLKID_DSU_CLK (CLKID_SM1_ADD_BASE + 9) + +#define CLKID_AO_BASE (CLKID_SM1_ADD_BASE + 10) #define CLKID_AO_CLK81 (CLKID_AO_BASE + 0) #define CLKID_SARADC_MUX (CLKID_AO_BASE + 1) #define CLKID_SARADC_DIV (CLKID_AO_BASE + 2)