diff --git a/arch/arm64/configs/odroidn2_defconfig b/arch/arm64/configs/odroidn2_defconfig index acb6fd0c44b5..adb152f9a9cc 100644 --- a/arch/arm64/configs/odroidn2_defconfig +++ b/arch/arm64/configs/odroidn2_defconfig @@ -1502,6 +1502,22 @@ CONFIG_AMLOGIC_DEFENDKEY=y # # Meson SPI NOR Flash Support # +CONFIG_AMLOGIC_MEDIA_VDEC_MPEG12=m +CONFIG_AMLOGIC_MEDIA_VDEC_MPEG4=m +CONFIG_AMLOGIC_MEDIA_VDEC_MPEG4_MULTI=m +CONFIG_AMLOGIC_MEDIA_VDEC_VC1=m +CONFIG_AMLOGIC_MEDIA_VDEC_H264=m +CONFIG_AMLOGIC_MEDIA_VDEC_H264_MULTI=m +CONFIG_AMLOGIC_MEDIA_VDEC_H264_MVC=m +CONFIG_AMLOGIC_MEDIA_VDEC_H265=m +CONFIG_AMLOGIC_MEDIA_VDEC_VP9=m +CONFIG_AMLOGIC_MEDIA_VDEC_MJPEG=m +CONFIG_AMLOGIC_MEDIA_VDEC_MJPEG_MULTI=m +CONFIG_AMLOGIC_MEDIA_VDEC_REAL=m +CONFIG_AMLOGIC_MEDIA_VDEC_AVS=m +CONFIG_AMLOGIC_MEDIA_VDEC_AVS2=m +CONFIG_AMLOGIC_MEDIA_VENC_H264=m +CONFIG_AMLOGIC_MEDIA_VENC_H265=m CONFIG_ARM_AMBA=y # @@ -4447,6 +4463,29 @@ CONFIG_NVMEM=y # CONFIG_FPGA is not set # CONFIG_TEE is not set +# +# ARM GPU Configuration +# +CONFIG_MALI_MIDGARD=y +# CONFIG_MALI_GATOR_SUPPORT is not set +# CONFIG_MALI_MIDGARD_DVFS is not set +# CONFIG_MALI_MIDGARD_ENABLE_TRACE is not set +# CONFIG_MALI_DEVFREQ is not set +# CONFIG_MALI_DMA_FENCE is not set +CONFIG_MALI_PLATFORM_NAME="devicetree" +CONFIG_MALI_EXPERT=y +# CONFIG_MALI_CORESTACK is not set +# CONFIG_MALI_PRFCNT_SET_SECONDARY is not set +# CONFIG_MALI_DEBUG is not set +# CONFIG_MALI_FENCE_DEBUG is not set +# CONFIG_MALI_NO_MALI is not set +# CONFIG_MALI_TRACE_TIMELINE is not set +# CONFIG_MALI_SYSTEM_TRACE is not set +# CONFIG_MALI_JOB_DUMP is not set +# CONFIG_MALI_2MB_ALLOC is not set +# CONFIG_MALI_PWRSOFT_765 is not set +CONFIG_MALI_KUTF=m + # # Firmware Drivers # @@ -4721,7 +4760,7 @@ CONFIG_DEBUG_INFO=y # CONFIG_GDB_SCRIPTS is not set CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=2048 +CONFIG_FRAME_WARN=0 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set # CONFIG_UNUSED_SYMBOLS is not set @@ -4836,6 +4875,7 @@ CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACE_CLOCK=y CONFIG_RING_BUFFER=y CONFIG_EVENT_TRACING=y +CONFIG_GPU_TRACEPOINTS=y CONFIG_CONTEXT_SWITCH_TRACER=y CONFIG_TRACING=y CONFIG_GENERIC_TRACER=y diff --git a/drivers/amlogic/Kconfig b/drivers/amlogic/Kconfig index d1a1afbdea25..277a95bfdbc0 100644 --- a/drivers/amlogic/Kconfig +++ b/drivers/amlogic/Kconfig @@ -135,5 +135,7 @@ source "drivers/amlogic/defendkey/Kconfig" source "drivers/amlogic/battery/Kconfig" source "drivers/amlogic/spi-nor/Kconfig" + +source "drivers/amlogic/media_modules/Kconfig" endmenu endif diff --git a/drivers/amlogic/Makefile b/drivers/amlogic/Makefile index 424dd5e89eb9..76fdc98c761b 100644 --- a/drivers/amlogic/Makefile +++ b/drivers/amlogic/Makefile @@ -7,14 +7,8 @@ ## Do not change. ########################################## -ifndef CONFIG_KASAN KBUILD_CFLAGS += -Wlarger-than=28792 KBUILD_CFLAGS += -Wstack-usage=1856 -Wno-bool-operation -Wno-maybe-uninitialized -else -ifeq ($(call cc-ifversion, -lt, 0500, y), y) - $(error -----GCC VERSION TOO SMALL FOR KASAN -----) -endif -endif # These 2 marked sentence is just for generate warning messages #KBUILD_CFLAGS += -Wno-error=larger-than=28792 @@ -133,3 +127,5 @@ obj-$(CONFIG_AMLOGIC_DEBUG) += debug/ obj-$(CONFIG_AMLOGIC_DEFENDKEY) += defendkey/ obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/ + +obj-y += media_modules/ diff --git a/drivers/amlogic/media_modules/Kconfig b/drivers/amlogic/media_modules/Kconfig new file mode 100644 index 000000000000..74796884bf25 --- /dev/null +++ b/drivers/amlogic/media_modules/Kconfig @@ -0,0 +1,101 @@ +config AMLOGIC_MEDIA_VDEC_MPEG12 + tristate "Amlogic Video decoder" + default m + help + Enables amlogic video decoder + +config AMLOGIC_MEDIA_VDEC_MPEG4 + tristate "Amlogic Video decoder" + default m + help + Enables amlogic video decoder + +config AMLOGIC_MEDIA_VDEC_MPEG4_MULTI + tristate "Amlogic Video decoder" + default m + help + Enables amlogic video decoder + +config AMLOGIC_MEDIA_VDEC_VC1 + tristate "Amlogic Video decoder" + default m + help + Enables amlogic video decoder + +config AMLOGIC_MEDIA_VDEC_H264 + tristate "Amlogic Video decoder" + default m + help + Enables amlogic video decoder + +config AMLOGIC_MEDIA_VDEC_H264_MULTI + tristate "Amlogic Video decoder" + default m + help + Enables amlogic video decoder + +config AMLOGIC_MEDIA_VDEC_H264_MVC + tristate "Amlogic Video decoder" + default m + help + Enables amlogic video decoder + +config AMLOGIC_MEDIA_VDEC_H265 + tristate "Amlogic Video decoder" + default m + help + Enables amlogic video decoder + +config AMLOGIC_MEDIA_VDEC_VP9 + tristate "Amlogic Video decoder" + default m + help + Enables amlogic video decoder + +config AMLOGIC_MEDIA_VDEC_MJPEG + tristate "Amlogic Video decoder" + default m + help + Enables amlogic video decoder + +config AMLOGIC_MEDIA_VDEC_MJPEG_MULTI + tristate "Amlogic Video decoder" + default m + help + Enables amlogic video decoder + +config AMLOGIC_MEDIA_VDEC_REAL + tristate "Amlogic Video decoder" + default m + help + Enables amlogic video decoder + +config AMLOGIC_MEDIA_VDEC_AVS + tristate "Amlogic Video decoder" + default m + help + Enables amlogic video decoder + +config AMLOGIC_MEDIA_VDEC_AVS2 + tristate "Amlogic Video decoder" + default m + help + Enables amlogic video decoder + +config AMLOGIC_MEDIA_VENC_H264 + tristate "Amlogic Video decoder" + default m + help + Enables amlogic video decoder + +config AMLOGIC_MEDIA_VENC_H265 + tristate "Amlogic Video decoder" + default m + help + Enables amlogic video decoder + +config AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + tristate "Amlogic Video decoder" + default m + help + Enables amlogic video decoder diff --git a/drivers/amlogic/media_modules/Makefile b/drivers/amlogic/media_modules/Makefile new file mode 100644 index 000000000000..f2a514848876 --- /dev/null +++ b/drivers/amlogic/media_modules/Makefile @@ -0,0 +1,4 @@ +obj-y += common/ +obj-y += frame_provider/ +obj-y += frame_sink/ +obj-y += stream_input/ diff --git a/drivers/amlogic/media_modules/common/Makefile b/drivers/amlogic/media_modules/common/Makefile new file mode 100644 index 000000000000..77ce080249db --- /dev/null +++ b/drivers/amlogic/media_modules/common/Makefile @@ -0,0 +1,2 @@ +obj-y += media_clock/ +obj-y += firmware/ diff --git a/drivers/amlogic/media_modules/common/chips/chips.c b/drivers/amlogic/media_modules/common/chips/chips.c new file mode 100644 index 000000000000..a9912f498602 --- /dev/null +++ b/drivers/amlogic/media_modules/common/chips/chips.c @@ -0,0 +1,183 @@ +/* + * drivers/amlogic/media/common/arch/chips/chips.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "../../stream_input/amports/amports_priv.h" +#include "../../frame_provider/decoder/utils/vdec.h" +#include "chips.h" +#include +#include + +#define VIDEO_FIRMWARE_FATHER_NAME "video" + +/* + *#define MESON_CPU_MAJOR_ID_M6 0x16 + *#define MESON_CPU_MAJOR_ID_M6TV 0x17 + *#define MESON_CPU_MAJOR_ID_M6TVL 0x18 + *#define MESON_CPU_MAJOR_ID_M8 0x19 + *#define MESON_CPU_MAJOR_ID_MTVD 0x1A + *#define MESON_CPU_MAJOR_ID_M8B 0x1B + *#define MESON_CPU_MAJOR_ID_MG9TV 0x1C + *#define MESON_CPU_MAJOR_ID_M8M2 0x1D + *#define MESON_CPU_MAJOR_ID_GXBB 0x1F + *#define MESON_CPU_MAJOR_ID_GXTVBB 0x20 + *#define MESON_CPU_MAJOR_ID_GXL 0x21 + *#define MESON_CPU_MAJOR_ID_GXM 0x22 + *#define MESON_CPU_MAJOR_ID_TXL 0x23 + */ +struct type_name { + + int type; + + const char *name; +}; +static const struct type_name cpu_type_name[] = { + {MESON_CPU_MAJOR_ID_M6, "m6"}, + {MESON_CPU_MAJOR_ID_M6TV, "m6tv"}, + {MESON_CPU_MAJOR_ID_M6TVL, "m6tvl"}, + {MESON_CPU_MAJOR_ID_M8, "m8"}, + {MESON_CPU_MAJOR_ID_MTVD, "mtvd"}, + {MESON_CPU_MAJOR_ID_M8B, "m8b"}, + {MESON_CPU_MAJOR_ID_MG9TV, "mg9tv"}, + {MESON_CPU_MAJOR_ID_M8M2, "m8"}, + {MESON_CPU_MAJOR_ID_GXBB, "gxbb"}, + {MESON_CPU_MAJOR_ID_GXTVBB, "gxtvbb"}, + {MESON_CPU_MAJOR_ID_GXL, "gxl"}, + {MESON_CPU_MAJOR_ID_GXM, "gxm"}, + {MESON_CPU_MAJOR_ID_TXL, "txl"}, + {MESON_CPU_MAJOR_ID_TXLX, "txlx"}, + {MESON_CPU_MAJOR_ID_G12A, "g12a"}, + {MESON_CPU_MAJOR_ID_G12B, "g12b"}, + {0, NULL}, +}; + +static const char *get_type_name(const struct type_name *typename, int size, + int type) +{ + + const char *name = "unknown"; + + int i; + + for (i = 0; i < size; i++) { + + if (type == typename[i].type) + + name = typename[i].name; + + } + + return name; +} + +const char *get_cpu_type_name(void) +{ + + return get_type_name(cpu_type_name, + sizeof(cpu_type_name) / sizeof(struct type_name), + get_cpu_type()); +} +EXPORT_SYMBOL(get_cpu_type_name); + +/* + *enum vformat_e { + * VFORMAT_MPEG12 = 0, + * VFORMAT_MPEG4, + * VFORMAT_H264, + * VFORMAT_MJPEG, + * VFORMAT_REAL, + * VFORMAT_JPEG, + * VFORMAT_VC1, + * VFORMAT_AVS, + * VFORMAT_YUV, + * VFORMAT_H264MVC, + * VFORMAT_H264_4K2K, + * VFORMAT_HEVC, + * VFORMAT_H264_ENC, + * VFORMAT_JPEG_ENC, + * VFORMAT_VP9, +* VFORMAT_AVS2, + * VFORMAT_MAX + *}; + */ +static const struct type_name vformat_type_name[] = { + {VFORMAT_MPEG12, "mpeg12"}, + {VFORMAT_MPEG4, "mpeg4"}, + {VFORMAT_H264, "h264"}, + {VFORMAT_MJPEG, "mjpeg"}, + {VFORMAT_REAL, "real"}, + {VFORMAT_JPEG, "jpeg"}, + {VFORMAT_VC1, "vc1"}, + {VFORMAT_AVS, "avs"}, + {VFORMAT_YUV, "yuv"}, + {VFORMAT_H264MVC, "h264mvc"}, + {VFORMAT_H264_4K2K, "h264_4k"}, + {VFORMAT_HEVC, "hevc"}, + {VFORMAT_H264_ENC, "h264_enc"}, + {VFORMAT_JPEG_ENC, "jpeg_enc"}, + {VFORMAT_VP9, "vp9"}, + {VFORMAT_AVS2, "avs2"}, + {VFORMAT_YUV, "yuv"}, + {0, NULL}, +}; + +const char *get_video_format_name(enum vformat_e type) +{ + + return get_type_name(vformat_type_name, + sizeof(vformat_type_name) / sizeof(struct type_name), type); +} +EXPORT_SYMBOL(get_video_format_name); + +static struct chip_vdec_info_s current_chip_info; + +struct chip_vdec_info_s *get_current_vdec_chip(void) +{ + + return ¤t_chip_info; +} +EXPORT_SYMBOL(get_current_vdec_chip); + +bool check_efuse_chip(int vformat) +{ + unsigned int status, i = 0; + int type[] = {15, 14, 11, 2}; /* avs2, vp9, h265, h264 */ + + status = (READ_EFUSE_REG(EFUSE_LIC2) >> 8 & 0xf); + if (!status) + return false; + + do { + if ((status & 1) && (type[i] == vformat)) + return true; + i++; + } while (status >>= 1); + + return false; +} +EXPORT_SYMBOL(check_efuse_chip); + diff --git a/drivers/amlogic/media_modules/common/chips/chips.h b/drivers/amlogic/media_modules/common/chips/chips.h new file mode 100644 index 000000000000..003e9d2bf689 --- /dev/null +++ b/drivers/amlogic/media_modules/common/chips/chips.h @@ -0,0 +1,40 @@ +/* + * drivers/amlogic/media/common/arch/chips/chips.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef UCODE_MANAGER_HEADER +#define UCODE_MANAGER_HEADER +#include "../media_clock/clk/clk_priv.h" + +struct chip_vdec_info_s { + + int cpu_type; + + struct video_firmware_s *firmware; + + struct chip_vdec_clk_s *clk_mgr[VDEC_MAX]; + + struct clk_set_setting *clk_setting_array; +}; + +const char *get_cpu_type_name(void); +const char *get_video_format_name(enum vformat_e type); + +struct chip_vdec_info_s *get_current_vdec_chip(void); + +bool check_efuse_chip(int vformat); + +#endif diff --git a/drivers/amlogic/media_modules/common/firmware/Makefile b/drivers/amlogic/media_modules/common/firmware/Makefile new file mode 100644 index 000000000000..748039cc1f71 --- /dev/null +++ b/drivers/amlogic/media_modules/common/firmware/Makefile @@ -0,0 +1,3 @@ +obj-m += firmware.o +firmware-objs += firmware_drv.o +firmware-objs += firmware_type.o diff --git a/drivers/amlogic/media_modules/common/firmware/firmware_cfg.h b/drivers/amlogic/media_modules/common/firmware/firmware_cfg.h new file mode 100644 index 000000000000..082d8f457535 --- /dev/null +++ b/drivers/amlogic/media_modules/common/firmware/firmware_cfg.h @@ -0,0 +1,32 @@ +/* + * drivers/amlogic/media/common/firmware/firmware_cfg.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/*all firmwares in one bin.*/ +{VIDEO_MISC, VIDEO_PACKAGE, "video_ucode.bin"}, + +/* Note: if the addition of new package has the same name */ +/* as the firmware in the video_ucode.bin, the firmware */ +/* in the video_ucode.bin will be ignored yet, because the */ +/* video_ucode.bin will always be processed in the end */ +{VIDEO_ENCODE, VIDEO_PACKAGE, "h264_enc.bin"}, + + +/*firmware for a special format, to replace the format in the package.*/ +{VIDEO_DECODE, VIDEO_FW_FILE, "h265.bin"}, +{VIDEO_DECODE, VIDEO_FW_FILE, "h264.bin"}, +{VIDEO_DECODE, VIDEO_FW_FILE, "h264_multi.bin"}, + diff --git a/drivers/amlogic/media_modules/common/firmware/firmware_drv.c b/drivers/amlogic/media_modules/common/firmware/firmware_drv.c new file mode 100644 index 000000000000..775f9352c728 --- /dev/null +++ b/drivers/amlogic/media_modules/common/firmware/firmware_drv.c @@ -0,0 +1,927 @@ +/* + * drivers/amlogic/media/common/firmware/firmware.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "../../stream_input/amports/amports_priv.h" +#include "../../frame_provider/decoder/utils/vdec.h" +#include "firmware_priv.h" +#include "../chips/chips.h" +#include +#include +#include +#include +#include +#include +#include + +/* major.minor.revision */ +#define PACK_VERS "v0.0.1" + +#define CLASS_NAME "firmware_codec" +#define DEV_NAME "firmware_vdec" +#define DIR "video" +#define FRIMWARE_SIZE (64 * 1024) /*64k*/ +#define BUFF_SIZE (1024 * 1024 * 2) + +#define FW_LOAD_FORCE (0x1) +#define FW_LOAD_TRY (0X2) + +/*the first 256 bytes are signature data*/ +#define SEC_OFFSET (256) + +#define PACK ('P' << 24 | 'A' << 16 | 'C' << 8 | 'K') +#define CODE ('C' << 24 | 'O' << 16 | 'D' << 8 | 'E') + +static DEFINE_MUTEX(mutex); + +static struct ucode_file_info_s ucode_info[] = { +#include "firmware_cfg.h" +}; + +static const struct file_operations fw_fops = { + .owner = THIS_MODULE +}; + +struct fw_mgr_s *g_mgr; +struct fw_dev_s *g_dev; + +static u32 debug; +static u32 detail; + +int get_firmware_data(unsigned int format, char *buf) +{ + int data_len, ret = -1; + struct fw_mgr_s *mgr = g_mgr; + struct fw_info_s *info; + + if (tee_enabled()) { + pr_info ("tee load firmware fomat = %d\n",(u32)format); + ret = tee_load_video_fw((u32)format, 0); + if (ret == 0) + ret = 1; + else + ret = -1; + return ret; + } + + mutex_lock(&mutex); + + if (list_empty(&mgr->fw_head)) { + pr_info("the info list is empty.\n"); + goto out; + } + + list_for_each_entry(info, &mgr->fw_head, node) { + if (format != info->format) + continue; + + data_len = info->data->head.data_size; + memcpy(buf, info->data->data, data_len); + ret = data_len; + + break; + } +out: + mutex_unlock(&mutex); + + return ret; +} +EXPORT_SYMBOL(get_firmware_data); + +int get_data_from_name(const char *name, char *buf) +{ + int data_len, ret = -1; + struct fw_mgr_s *mgr = g_mgr; + struct fw_info_s *info; + char *fw_name = __getname(); + + if (IS_ERR_OR_NULL(fw_name)) + return -ENOMEM; + + strcat(fw_name, name); + strcat(fw_name, ".bin"); + + mutex_lock(&mutex); + + if (list_empty(&mgr->fw_head)) { + pr_info("the info list is empty.\n"); + goto out; + } + + list_for_each_entry(info, &mgr->fw_head, node) { + if (strcmp(fw_name, info->name)) + continue; + + data_len = info->data->head.data_size; + memcpy(buf, info->data->data, data_len); + ret = data_len; + + break; + } +out: + mutex_unlock(&mutex); + + __putname(fw_name); + + return ret; +} +EXPORT_SYMBOL(get_data_from_name); + +static int fw_probe(char *buf) +{ + int magic = 0; + + memcpy(&magic, buf, sizeof(int)); + return magic; +} + +static int request_firmware_from_sys(const char *file_name, + char *buf, int size) +{ + int ret = -1; + const struct firmware *fw; + int magic, offset = 0; + + pr_info("Try to load %s ...\n", file_name); + + ret = request_firmware(&fw, file_name, g_dev->dev); + if (ret < 0) { + pr_info("Error : %d can't load the %s.\n", ret, file_name); + goto err; + } + + if (fw->size > size) { + pr_info("Not enough memory size for ucode.\n"); + ret = -ENOMEM; + goto release; + } + + magic = fw_probe((char *)fw->data); + if (magic != PACK && magic != CODE) { + if (fw->size < SEC_OFFSET) { + pr_info("This is an invalid firmware file.\n"); + goto release; + } + + magic = fw_probe((char *)fw->data + SEC_OFFSET); + if (magic != PACK) { + pr_info("The firmware file is not packet.\n"); + goto release; + } + + offset = SEC_OFFSET; + } + + memcpy(buf, (char *)fw->data + offset, fw->size - offset); + + pr_info("load firmware size : %zd, Name : %s.\n", + fw->size, file_name); + ret = fw->size; +release: + release_firmware(fw); +err: + return ret; +} + +int request_decoder_firmware_on_sys(enum vformat_e format, + const char *file_name, char *buf, int size) +{ + int ret; + + ret = get_data_from_name(file_name, buf); + if (ret < 0) + pr_info("Get firmware fail.\n"); + + if (ret > size) { + pr_info("Not enough memory.\n"); + return -ENOMEM; + } + + return ret; +} +int get_decoder_firmware_data(enum vformat_e format, + const char *file_name, char *buf, int size) +{ + int ret; + + ret = request_decoder_firmware_on_sys(format, file_name, buf, size); + if (ret < 0) + pr_info("get_decoder_firmware_data %s for format %d failed!\n", + file_name, format); + + return ret; +} +EXPORT_SYMBOL(get_decoder_firmware_data); + +static unsigned long fw_mgr_lock(struct fw_mgr_s *mgr) +{ + unsigned long flags; + + spin_lock_irqsave(&mgr->lock, flags); + return flags; +} + +static void fw_mgr_unlock(struct fw_mgr_s *mgr, unsigned long flags) +{ + spin_unlock_irqrestore(&mgr->lock, flags); +} + +static void fw_add_info(struct fw_info_s *info) +{ + unsigned long flags; + struct fw_mgr_s *mgr = g_mgr; + + flags = fw_mgr_lock(mgr); + list_add(&info->node, &mgr->fw_head); + fw_mgr_unlock(mgr, flags); +} + +static void fw_del_info(struct fw_info_s *info) +{ + unsigned long flags; + struct fw_mgr_s *mgr = g_mgr; + + flags = fw_mgr_lock(mgr); + list_del(&info->node); + kfree(info); + fw_mgr_unlock(mgr, flags); +} + +static void fw_info_walk(void) +{ + struct fw_mgr_s *mgr = g_mgr; + struct fw_info_s *info; + + if (list_empty(&mgr->fw_head)) { + pr_info("the info list is empty.\n"); + return; + } + + list_for_each_entry(info, &mgr->fw_head, node) { + if (IS_ERR_OR_NULL(info->data)) + continue; + + pr_info("name : %s.\n", info->name); + pr_info("ver : %s.\n", + info->data->head.version); + pr_info("crc : 0x%x.\n", + info->data->head.checksum); + pr_info("size : %d.\n", + info->data->head.data_size); + pr_info("maker: %s.\n", + info->data->head.maker); + pr_info("from : %s.\n", info->src_from); + pr_info("date : %s.\n\n", + info->data->head.date); + } +} + +static void fw_files_info_walk(void) +{ + struct fw_mgr_s *mgr = g_mgr; + struct fw_files_s *files; + + if (list_empty(&mgr->files_head)) { + pr_info("the file list is empty.\n"); + return; + } + + list_for_each_entry(files, &mgr->files_head, node) { + pr_info("type : %s.\n", !files->fw_type ? + "VIDEO_DECODE" : files->fw_type == 1 ? + "VIDEO_ENCODE" : "VIDEO_MISC"); + pr_info("from : %s.\n", !files->file_type ? + "VIDEO_PACKAGE" : "VIDEO_FW_FILE"); + pr_info("path : %s.\n", files->path); + pr_info("name : %s.\n\n", files->name); + } +} + +static ssize_t info_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + char *pbuf = buf; + struct fw_mgr_s *mgr = g_mgr; + struct fw_info_s *info; + unsigned int secs = 0; + struct tm tm; + + mutex_lock(&mutex); + + if (list_empty(&mgr->fw_head)) { + pbuf += sprintf(pbuf, "No firmware.\n"); + goto out; + } + + list_for_each_entry(info, &mgr->fw_head, node) { + if (IS_ERR_OR_NULL(info->data)) + continue; + + if (detail) { + pr_info("%-5s: %s\n", "name", info->name); + pr_info("%-5s: %s\n", "ver", + info->data->head.version); + pr_info("%-5s: 0x%x\n", "sum", + info->data->head.checksum); + pr_info("%-5s: %d\n", "size", + info->data->head.data_size); + pr_info("%-5s: %s\n", "maker", + info->data->head.maker); + pr_info("%-5s: %s\n", "from", + info->src_from); + pr_info("%-5s: %s\n\n", "date", + info->data->head.date); + continue; + } + + secs = info->data->head.time + - sys_tz.tz_minuteswest * 60; + time_to_tm(secs, 0, &tm); + + pr_info("%s %-16s, %02d:%02d:%02d %d/%d/%ld, %s %-8s, %s %s\n", + "fmt:", info->data->head.format, + tm.tm_hour, tm.tm_min, tm.tm_sec, + tm.tm_mon + 1, tm.tm_mday, tm.tm_year + 1900, + "id:", info->data->head.commit, + "mk:", info->data->head.maker); + } +out: + mutex_unlock(&mutex); + + return pbuf - buf; +} + +static ssize_t info_store(struct class *cls, + struct class_attribute *attr, const char *buf, size_t count) +{ + if (kstrtoint(buf, 0, &detail) < 0) + return -EINVAL; + + return count; +} + +static int fw_info_fill(void) +{ + int ret = 0, i, len; + struct fw_mgr_s *mgr = g_mgr; + struct fw_files_s *files; + int info_size = ARRAY_SIZE(ucode_info); + char *path = __getname(); + const char *name; + + if (IS_ERR_OR_NULL(path)) + return -ENOMEM; + + for (i = 0; i < info_size; i++) { + name = ucode_info[i].name; + if (IS_ERR_OR_NULL(name)) + break; + + len = snprintf(path, PATH_MAX, "%s/%s", DIR, + ucode_info[i].name); + if (len >= PATH_MAX) + continue; + + files = kzalloc(sizeof(struct fw_files_s), GFP_KERNEL); + if (IS_ERR_OR_NULL(files)) { + __putname(path); + return -ENOMEM; + } + + files->file_type = ucode_info[i].file_type; + files->fw_type = ucode_info[i].fw_type; + strncpy(files->path, path, sizeof(files->path)); + strncpy(files->name, name, sizeof(files->name)); + + list_add(&files->node, &mgr->files_head); + } + + __putname(path); + + if (debug) + fw_files_info_walk(); + + return ret; +} + +static int fw_data_check_sum(struct firmware_s *fw) +{ + unsigned int crc; + + crc = crc32_le(~0U, fw->data, fw->head.data_size); + + /*pr_info("firmware crc result : 0x%x\n", crc ^ ~0U);*/ + + return fw->head.checksum != (crc ^ ~0U) ? 0 : 1; +} + +static int fw_data_filter(struct firmware_s *fw, + struct fw_info_s *fw_info) +{ + struct fw_mgr_s *mgr = g_mgr; + struct fw_info_s *info, *tmp; + int cpu = fw_get_cpu(fw->head.cpu); + + if (mgr->cur_cpu < cpu) { + pr_info("the fw %s is not match.\n", fw_info->name); + kfree(fw_info); + kfree(fw); + return -1; + } + + /* the encode fw need to ignoring filtering rules. */ + if (fw_info->format == FIRMWARE_MAX) + return 0; + + list_for_each_entry_safe(info, tmp, &mgr->fw_head, node) { + if (info->format != fw_info->format) + continue; + + if (IS_ERR_OR_NULL(info->data)) { + fw_del_info(info); + return 0; + } + + /* high priority of VIDEO_FW_FILE */ + if (info->file_type == VIDEO_FW_FILE) { + pr_info("the %s need to priority proc.\n",info->name); + kfree(fw_info); + kfree(fw); + return 1; + } + + /* the cpu ver is lower and needs to be filtered */ + if (cpu < fw_get_cpu(info->data->head.cpu)) { + pr_info("the fw %s is not match.\n", + fw_info->name); + kfree(fw_info); + kfree(fw); + return 1; + } + + /* removes not match fw from info list */ + pr_info("the fw %s is not match.\n", info->name); + kfree(info->data); + fw_del_info(info); + } + + return 0; +} + +static int fw_check_pack_version(char *buf) +{ + struct package_s *pack = NULL; + int major, minor, rev, ver = 0; + + pack = (struct package_s *) buf; + sscanf(PACK_VERS, "v%x.%x.%x", &major, &minor, &rev); + ver = (major << 24 | minor << 16 | rev); + + pr_info("the package has %d fws totally.\n", pack->head.total); + + major = pack->head.version >> 24; + minor = (pack->head.version >> 16) & 0xf; + rev = pack->head.version & 0xff; + + if (ver < pack->head.version) { + pr_info("the pack ver v%d.%d.%d too higher to unsupport.\n", + major, minor, rev); + return -1; + } + + if (ver != pack->head.version) { + pr_info("the fw pack ver v%d.%d.%d is too lower.\n", major, minor, rev); + pr_info("it may work abnormally so need to be update in time.\n"); + } + + return 0; +} + +static int fw_package_parse(struct fw_files_s *files, + char *buf, int size) +{ + int ret = 0; + struct package_info_s *pack_info; + struct fw_info_s *info; + struct firmware_s *data; + char *pack_data; + int info_len, len; + int try_cnt = 100; + char *path = __getname(); + + if (IS_ERR_OR_NULL(path)) + return -ENOMEM; + + pack_data = ((struct package_s *)buf)->data; + pack_info = (struct package_info_s *)pack_data; + info_len = sizeof(struct package_info_s); + + do { + if (!pack_info->head.length) + break; + + len = snprintf(path, PATH_MAX, "%s/%s", DIR, + pack_info->head.name); + if (len >= PATH_MAX) + continue; + + info = kzalloc(sizeof(struct fw_info_s), GFP_KERNEL); + if (IS_ERR_OR_NULL(info)) { + ret = -ENOMEM; + goto out; + } + + data = kzalloc(FRIMWARE_SIZE, GFP_KERNEL); + if (IS_ERR_OR_NULL(data)) { + kfree(info); + ret = -ENOMEM; + goto out; + } + + info->file_type = files->file_type; + strncpy(info->src_from, files->name, + sizeof(info->src_from)); + strncpy(info->name, pack_info->head.name, + sizeof(info->name)); + info->format = get_fw_format(pack_info->head.format); + + len = pack_info->head.length; + memcpy(data, pack_info->data, len); + + pack_data += (pack_info->head.length + info_len); + pack_info = (struct package_info_s *)pack_data; + + if (!fw_data_check_sum(data)) { + pr_info("check sum fail !\n"); + kfree(data); + kfree(info); + goto out; + } + + if (fw_data_filter(data, info)) + continue; + + if (debug) + pr_info("adds %s to the fw list.\n", info->name); + + info->data = data; + fw_add_info(info); + } while (try_cnt--); +out: + __putname(path); + + return ret; +} + +static int fw_code_parse(struct fw_files_s *files, + char *buf, int size) +{ + struct fw_info_s *info; + + info = kzalloc(sizeof(struct fw_info_s), GFP_KERNEL); + if (IS_ERR_OR_NULL(info)) + return -ENOMEM; + + info->data = kzalloc(FRIMWARE_SIZE, GFP_KERNEL); + if (IS_ERR_OR_NULL(info->data)) + return -ENOMEM; + + info->file_type = files->file_type; + strncpy(info->src_from, files->name, + sizeof(info->src_from)); + memcpy(info->data, buf, size); + + if (!fw_data_check_sum(info->data)) { + pr_info("check sum fail !\n"); + kfree(info->data); + return -1; + } + + if (debug) + pr_info("adds %s to the fw list.\n", info->name); + + fw_add_info(info); + + return 0; +} + +static int get_firmware_from_sys(const char *path, + char *buf, int size) +{ + int len = 0; + + len = request_firmware_from_sys(path, buf, size); + if (len < 0) + pr_info("get data from fsys fail.\n"); + + return len; +} + +static int fw_data_binding(void) +{ + int ret = 0, magic = 0; + struct fw_mgr_s *mgr = g_mgr; + struct fw_files_s *files, *tmp; + char *buf = vmalloc(BUFF_SIZE); + int size; + + if (list_empty(&mgr->files_head)) { + pr_info("the file list is empty.\n"); + return 0; + } + + if (IS_ERR_OR_NULL(buf)) + return -ENOMEM; + + memset(buf, 0, BUFF_SIZE); + + list_for_each_entry_safe(files, tmp, &mgr->files_head, node) { + size = get_firmware_from_sys(files->path, buf, BUFF_SIZE); + magic = fw_probe(buf); + + if (files->file_type == VIDEO_PACKAGE && magic == PACK) { + pr_info("start to parse fw package.\n"); + + if (!fw_check_pack_version(buf)) + ret = fw_package_parse(files, buf, size); + } else if (files->file_type == VIDEO_FW_FILE && magic == CODE) { + pr_info("start to parse fw code.\n"); + + ret = fw_code_parse(files, buf, size); + } else { + list_del(&files->node); + kfree(files); + pr_info("invaild file type.\n"); + } + + memset(buf, 0, BUFF_SIZE); + } + + if (debug) + fw_info_walk(); + + vfree(buf); + + return ret; +} + +static int fw_pre_load(void) +{ + if (fw_info_fill() < 0) { + pr_info("Get path fail.\n"); + return -1; + } + + if (fw_data_binding() < 0) { + pr_info("Set data fail.\n"); + return -1; + } + + return 0; +} + +static int fw_mgr_init(void) +{ + g_mgr = kzalloc(sizeof(struct fw_mgr_s), GFP_KERNEL); + if (IS_ERR_OR_NULL(g_mgr)) + return -ENOMEM; + + g_mgr->cur_cpu = get_cpu_type(); + INIT_LIST_HEAD(&g_mgr->files_head); + INIT_LIST_HEAD(&g_mgr->fw_head); + spin_lock_init(&g_mgr->lock); + + return 0; +} + +static void fw_ctx_clean(void) +{ + struct fw_mgr_s *mgr = g_mgr; + struct fw_files_s *files; + struct fw_info_s *info; + unsigned long flags; + + flags = fw_mgr_lock(mgr); + while (!list_empty(&mgr->files_head)) { + files = list_entry(mgr->files_head.next, + struct fw_files_s, node); + list_del(&files->node); + kfree(files); + } + + while (!list_empty(&mgr->fw_head)) { + info = list_entry(mgr->fw_head.next, + struct fw_info_s, node); + list_del(&info->node); + kfree(info->data); + kfree(info); + } + fw_mgr_unlock(mgr, flags); +} + +int video_fw_reload(int mode) +{ + int ret = 0; + struct fw_mgr_s *mgr = g_mgr; + + if (tee_enabled()) + return 0; + + mutex_lock(&mutex); + + if (mode & FW_LOAD_FORCE) { + fw_ctx_clean(); + + ret = fw_pre_load(); + if (ret < 0) + pr_err("The fw reload fail.\n"); + } else if (mode & FW_LOAD_TRY) { + if (!list_empty(&mgr->fw_head)) { + pr_info("The fw has been loaded.\n"); + goto out; + } + + ret = fw_pre_load(); + if (ret < 0) + pr_err("The fw try to reload fail.\n"); + } +out: + mutex_unlock(&mutex); + + return ret; +} +EXPORT_SYMBOL(video_fw_reload); + +static ssize_t reload_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + char *pbuf = buf; + + pbuf += sprintf(pbuf, "The fw reload usage.\n"); + pbuf += sprintf(pbuf, "> set 1 means that the fw is forced to update\n"); + pbuf += sprintf(pbuf, "> set 2 means that the fw is try to reload\n"); + + return pbuf - buf; +} + +static ssize_t reload_store(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size) +{ + int ret = -1; + unsigned int val; + + ret = kstrtoint(buf, 0, &val); + if (ret != 0) + return -EINVAL; + + ret = video_fw_reload(val); + if (ret < 0) + pr_err("fw reload fail.\n"); + + return size; +} + +static ssize_t debug_show(struct class *cls, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "%x\n", debug); +} + +static ssize_t debug_store(struct class *cls, + struct class_attribute *attr, const char *buf, size_t count) +{ + if (kstrtoint(buf, 0, &debug) < 0) + return -EINVAL; + + return count; +} + +static struct class_attribute fw_class_attrs[] = { + __ATTR(info, 0664, info_show, info_store), + __ATTR(reload, 0664, reload_show, reload_store), + __ATTR(debug, 0664, debug_show, debug_store), + __ATTR_NULL +}; + +static struct class fw_class = { + .name = CLASS_NAME, + .class_attrs = fw_class_attrs, +}; + +static int fw_driver_init(void) +{ + int ret = -1; + + g_dev = kzalloc(sizeof(struct fw_dev_s), GFP_KERNEL); + if (IS_ERR_OR_NULL(g_dev)) + return -ENOMEM; + + g_dev->dev_no = MKDEV(AMSTREAM_MAJOR, 100); + + ret = register_chrdev_region(g_dev->dev_no, 1, DEV_NAME); + if (ret < 0) { + pr_info("Can't get major number %d.\n", AMSTREAM_MAJOR); + goto err; + } + + cdev_init(&g_dev->cdev, &fw_fops); + g_dev->cdev.owner = THIS_MODULE; + + ret = cdev_add(&g_dev->cdev, g_dev->dev_no, 1); + if (ret) { + pr_info("Error %d adding cdev fail.\n", ret); + goto err; + } + + ret = class_register(&fw_class); + if (ret < 0) { + pr_info("Failed in creating class.\n"); + goto err; + } + + g_dev->dev = device_create(&fw_class, NULL, + g_dev->dev_no, NULL, DEV_NAME); + if (IS_ERR_OR_NULL(g_dev->dev)) { + pr_info("Create device failed.\n"); + ret = -ENODEV; + goto err; + } + + pr_info("Registered firmware driver success.\n"); +err: + return ret; +} + +static void fw_driver_exit(void) +{ + cdev_del(&g_dev->cdev); + device_destroy(&fw_class, g_dev->dev_no); + class_unregister(&fw_class); + unregister_chrdev_region(g_dev->dev_no, 1); + kfree(g_dev); + kfree(g_mgr); +} + +static int __init fw_module_init(void) +{ + int ret = -1; + + ret = fw_driver_init(); + if (ret) { + pr_info("Error %d firmware driver init fail.\n", ret); + goto err; + } + + ret = fw_mgr_init(); + if (ret) { + pr_info("Error %d firmware mgr init fail.\n", ret); + goto err; + } + + ret = fw_pre_load(); + if (ret) { + pr_info("Error %d firmware pre load fail.\n", ret); + goto err; + } +err: + return ret; +} + +static void __exit fw_module_exit(void) +{ + fw_ctx_clean(); + fw_driver_exit(); + pr_info("Firmware driver cleaned up.\n"); +} + +module_init(fw_module_init); +module_exit(fw_module_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Nanxin Qin "); diff --git a/drivers/amlogic/media_modules/common/firmware/firmware_priv.h b/drivers/amlogic/media_modules/common/firmware/firmware_priv.h new file mode 100644 index 000000000000..811fdc6e0159 --- /dev/null +++ b/drivers/amlogic/media_modules/common/firmware/firmware_priv.h @@ -0,0 +1,117 @@ +/* + * drivers/amlogic/media/common/firmware/firmware.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * +*/ + +#ifndef __VIDEO_FIRMWARE_PRIV_HEAD_ +#define __VIDEO_FIRMWARE_PRIV_HEAD_ +#include +#include +#include +#include +#include "firmware_type.h" + +struct fw_mgr_s { + struct list_head fw_head; + struct list_head files_head; + spinlock_t lock; + int cur_cpu; +}; + +struct fw_files_s { + struct list_head node; + int fw_type; + int file_type; + char name[32]; + char path[64]; +}; + +struct ucode_file_info_s { + int fw_type; + int file_type; + const char *name; +}; + +struct fw_info_s { + struct list_head node; + char name[32]; + char src_from[32]; + int file_type; + unsigned int format; + struct firmware_s *data; +}; + +struct fw_head_s { + int magic; + int checksum; + char name[32]; + char cpu[16]; + char format[32]; + char version[32]; + char maker[32]; + char date[32]; + char commit[16]; + int data_size; + unsigned int time; + char reserved[128]; +}; + +struct firmware_s { + union { + struct fw_head_s head; + char buf[512]; + }; + char data[0]; +}; + +struct package_head_s { + int magic; + int size; + int checksum; + int total; + int version; + char reserved[128]; +}; + +struct package_s { + union { + struct package_head_s head; + char buf[256]; + }; + char data[0]; +}; + +struct info_head_s { + char name[32]; + char format[32]; + char cpu[32]; + int length; +}; + +struct package_info_s { + union { + struct info_head_s head; + char buf[256]; + }; + char data[0]; +}; + +struct fw_dev_s { + struct cdev cdev; + struct device *dev; + dev_t dev_no; +}; + +#endif diff --git a/drivers/amlogic/media_modules/common/firmware/firmware_type.c b/drivers/amlogic/media_modules/common/firmware/firmware_type.c new file mode 100644 index 000000000000..b2d9f17d6572 --- /dev/null +++ b/drivers/amlogic/media_modules/common/firmware/firmware_type.c @@ -0,0 +1,92 @@ +#include "firmware_type.h" +#include + +static const struct format_name_s format_name[] = { + {VIDEO_DEC_MPEG12, "mpeg12"}, + {VIDEO_DEC_MPEG12_MULTI, "mpeg12_multi"}, + {VIDEO_DEC_MPEG4_3, "divx311"}, + {VIDEO_DEC_MPEG4_4, "divx4x"}, + {VIDEO_DEC_MPEG4_4_MULTI, "divx4x_multi"}, + {VIDEO_DEC_MPEG4_5, "xvid"}, + {VIDEO_DEC_MPEG4_5_MULTI, "xvid_multi"}, + {VIDEO_DEC_H263, "h263"}, + {VIDEO_DEC_H263_MULTI, "h263_multi"}, + {VIDEO_DEC_MJPEG, "mjpeg"}, + {VIDEO_DEC_MJPEG_MULTI, "mjpeg_multi"}, + {VIDEO_DEC_REAL_V8, "real_v8"}, + {VIDEO_DEC_REAL_V9, "real_v9"}, + {VIDEO_DEC_VC1, "vc1"}, + {VIDEO_DEC_VC1_G12A, "vc1_g12a"}, + {VIDEO_DEC_AVS, "avs"}, + {VIDEO_DEC_AVS_GXM, "avs_gxm"}, + {VIDEO_DEC_AVS_NOCABAC, "avs_no_cabac"}, + {VIDEO_DEC_H264, "h264"}, + {VIDEO_DEC_H264_4k2K, "h264_4k2k"}, + {VIDEO_DEC_H264_4k2K_SINGLE, "h264_4k2k_single"}, + {VIDEO_DEC_H264_MVC, "h264_mvc"}, + {VIDEO_DEC_H264_MVC_GXM, "h264_mvc_gxm"}, + {VIDEO_DEC_H264_MULTI, "h264_multi"}, + {VIDEO_DEC_H264_MULTI_MMU, "h264_multi_mmu"}, + {VIDEO_DEC_H264_MULTI_GXM, "h264_multi_gxm"}, + {VIDEO_DEC_HEVC, "hevc"}, + {VIDEO_DEC_HEVC_MMU, "hevc_mmu"}, + {VIDEO_DEC_HEVC_G12A, "hevc_g12a"}, + {VIDEO_DEC_VP9, "vp9"}, + {VIDEO_DEC_VP9_MMU, "vp9_mmu"}, + {VIDEO_DEC_VP9_G12A, "vp9_g12a"}, + {VIDEO_DEC_AVS2, "avs2"}, + {VIDEO_DEC_AVS2_MMU, "avs2_mmu"}, + {VIDEO_ENC_H264, "h264_enc"}, + {VIDEO_ENC_JPEG, "jpeg_enc"}, + {FIRMWARE_MAX, "unknown"}, +}; + +static const struct cpu_type_s cpu_type[] = { + {MESON_CPU_MAJOR_ID_GXL, "gxl"}, + {MESON_CPU_MAJOR_ID_GXM, "gxm"}, + {MESON_CPU_MAJOR_ID_G12A, "g12a"}, + {MESON_CPU_MAJOR_ID_G12B, "g12b"}, +}; + +const char *get_fw_format_name(unsigned int format) +{ + const char *name = "unknown"; + int i, size = ARRAY_SIZE(format_name); + + for (i = 0; i < size; i++) { + if (format == format_name[i].format) + name = format_name[i].name; + } + + return name; +} +EXPORT_SYMBOL(get_fw_format_name); + +unsigned int get_fw_format(const char *name) +{ + unsigned int format = FIRMWARE_MAX; + int i, size = ARRAY_SIZE(format_name); + + for (i = 0; i < size; i++) { + if (!strcmp(name, format_name[i].name)) + format = format_name[i].format; + } + + return format; +} +EXPORT_SYMBOL(get_fw_format); + +int fw_get_cpu(const char *name) +{ + int type = 0; + int i, size = ARRAY_SIZE(cpu_type); + + for (i = 0; i < size; i++) { + if (!strcmp(name, cpu_type[i].name)) + type = cpu_type[i].type; + } + + return type; +} +EXPORT_SYMBOL(fw_get_cpu); + diff --git a/drivers/amlogic/media_modules/common/firmware/firmware_type.h b/drivers/amlogic/media_modules/common/firmware/firmware_type.h new file mode 100644 index 000000000000..f51956bbf561 --- /dev/null +++ b/drivers/amlogic/media_modules/common/firmware/firmware_type.h @@ -0,0 +1,76 @@ +#ifndef __VIDEO_FIRMWARE_FORMAT_ +#define __VIDEO_FIRMWARE_FORMAT_ + +#include + +/* example: #define VIDEO_DEC_AV1 TAG('A', 'V', '1', '-')*/ +#define TAG(a, b, c, d)\ + ((a << 24) | (b << 16) | (c << 8) | d) + +/* fws define */ +#define VIDEO_DEC_MPEG12 (0) +#define VIDEO_DEC_MPEG4_3 (1) +#define VIDEO_DEC_MPEG4_4 (2) +#define VIDEO_DEC_MPEG4_5 (3) +#define VIDEO_DEC_H263 (4) +#define VIDEO_DEC_MJPEG (5) +#define VIDEO_DEC_MJPEG_MULTI (6) +#define VIDEO_DEC_REAL_V8 (7) +#define VIDEO_DEC_REAL_V9 (8) +#define VIDEO_DEC_VC1 (9) +#define VIDEO_DEC_AVS (10) +#define VIDEO_DEC_H264 (11) +#define VIDEO_DEC_H264_4k2K (12) +#define VIDEO_DEC_H264_4k2K_SINGLE (13) +#define VIDEO_DEC_H264_MVC (14) +#define VIDEO_DEC_H264_MULTI (15) +#define VIDEO_DEC_HEVC (16) +#define VIDEO_DEC_HEVC_MMU (17) +#define VIDEO_DEC_VP9 (18) +#define VIDEO_DEC_VP9_MMU (19) +#define VIDEO_ENC_H264 (20) +#define VIDEO_ENC_JPEG (21) +#define VIDEO_DEC_H264_MULTI_MMU (23) +#define VIDEO_DEC_HEVC_G12A (24) +#define VIDEO_DEC_VP9_G12A (25) +#define VIDEO_DEC_AVS2 (26) +#define VIDEO_DEC_AVS2_MMU (27) +#define VIDEO_DEC_AVS_GXM (28) +#define VIDEO_DEC_AVS_NOCABAC (29) +#define VIDEO_DEC_H264_MULTI_GXM (30) +#define VIDEO_DEC_H264_MVC_GXM (31) +#define VIDEO_DEC_VC1_G12A (32) +#define VIDEO_DEC_MPEG12_MULTI TAG('M', '1', '2', 'M') +#define VIDEO_DEC_MPEG4_4_MULTI TAG('M', '4', '4', 'M') +#define VIDEO_DEC_MPEG4_5_MULTI TAG('M', '4', '5', 'M') +#define VIDEO_DEC_H263_MULTI TAG('2', '6', '3', 'M') + +/* ... */ +#define FIRMWARE_MAX (UINT_MAX) + +#define VIDEO_PACKAGE (0) +#define VIDEO_FW_FILE (1) + +#define VIDEO_DECODE (0) +#define VIDEO_ENCODE (1) +#define VIDEO_MISC (2) + +#define OPTEE_VDEC_LEGENCY (0) +#define OPTEE_VDEC (1) +#define OPTEE_VDEC_HEVC (2) + +struct format_name_s { + unsigned int format; + const char *name; +}; + +struct cpu_type_s { + int type; + const char *name; +}; + +const char *get_firmware_type_name(unsigned int format); +unsigned int get_fw_format(const char *name); +int fw_get_cpu(const char *name); + +#endif diff --git a/drivers/amlogic/media_modules/common/media_clock/Makefile b/drivers/amlogic/media_modules/common/media_clock/Makefile new file mode 100644 index 000000000000..994857a05219 --- /dev/null +++ b/drivers/amlogic/media_modules/common/media_clock/Makefile @@ -0,0 +1,5 @@ +obj-m += media_clock.o +media_clock-objs += ../chips/chips.o +media_clock-objs += clk/clkg12.o +media_clock-objs += clk/clk.o +media_clock-objs += switch/amports_gate.o diff --git a/drivers/amlogic/media_modules/common/media_clock/clk/clk.c b/drivers/amlogic/media_modules/common/media_clock/clk/clk.c new file mode 100644 index 000000000000..4ffaf12bfb46 --- /dev/null +++ b/drivers/amlogic/media_modules/common/media_clock/clk/clk.c @@ -0,0 +1,455 @@ +/* + * drivers/amlogic/media/common/arch/clk/clk.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "../../../stream_input/amports/amports_priv.h" +#include "../../../frame_provider/decoder/utils/vdec.h" +#include "../../chips/chips.h" +#include "clk_priv.h" +#include + +#define p_vdec() (get_current_vdec_chip()->clk_mgr[VDEC_1]) +#define p_vdec2() (get_current_vdec_chip()->clk_mgr[VDEC_2]) +#define p_vdec_hcodec() (get_current_vdec_chip()->clk_mgr[VDEC_HCODEC]) +#define p_vdec_hevc() (get_current_vdec_chip()->clk_mgr[VDEC_HEVC]) +#define p_vdec_hevc_back() (get_current_vdec_chip()->clk_mgr[VDEC_HEVCB]) + +static int clock_source_wxhxfps_saved[VDEC_MAX + 1]; + +#define IF_HAVE_RUN(p, fn)\ + do {\ + if (p && p->fn)\ + p->fn();\ + } while (0) +/* + *#define IF_HAVE_RUN_P1_RET(p, fn, p1)\ + * do {\ + * pr_debug("%s-----%d\n", __func__, clk);\ + * if (p && p->fn)\ + * return p->fn(p1);\ + * else\ + * return -1;\ + * } while (0) + * + *#define IF_HAVE_RUN_RET(p, fn)\ + * do {\ + * if (p && p->fn)\ + * return p->fn();\ + * else\ + * return 0;\ + * } while (0) + */ + +int vdec_clock_init(void) +{ + if (p_vdec() && p_vdec()->clock_init) + return p_vdec()->clock_init(); + else + return 0; +} +EXPORT_SYMBOL(vdec_clock_init); + +/* + *clk ==0 : + * to be release. + * released shared clk, + *clk ==1 :default low clk + *clk ==2 :default high clk + */ +int vdec_clock_set(int clk) +{ + pr_debug("%s-----%d\n", __func__, clk); + if (p_vdec() && p_vdec()->clock_set) + return p_vdec()->clock_set(clk); + else + return -1; +} +EXPORT_SYMBOL(vdec_clock_set); + +void vdec_clock_enable(void) +{ + vdec_clock_set(1); +} +EXPORT_SYMBOL(vdec_clock_enable); + +void vdec_clock_hi_enable(void) +{ + vdec_clock_set(2); +} +EXPORT_SYMBOL(vdec_clock_hi_enable); + +void vdec_clock_on(void) +{ + IF_HAVE_RUN(p_vdec(), clock_on); +} +EXPORT_SYMBOL(vdec_clock_on); + +void vdec_clock_off(void) +{ + IF_HAVE_RUN(p_vdec(), clock_off); + clock_source_wxhxfps_saved[VDEC_1] = 0; +} +EXPORT_SYMBOL(vdec_clock_off); + +int vdec2_clock_set(int clk) +{ + pr_debug("%s-----%d\n", __func__, clk); + if (p_vdec2() && p_vdec2()->clock_set) + return p_vdec2()->clock_set(clk); + else + return -1; +} +EXPORT_SYMBOL(vdec2_clock_set); + +void vdec2_clock_enable(void) +{ + vdec2_clock_set(1); +} +EXPORT_SYMBOL(vdec2_clock_enable); + +void vdec2_clock_hi_enable(void) +{ + vdec2_clock_set(2); +} +EXPORT_SYMBOL(vdec2_clock_hi_enable); + +void vdec2_clock_on(void) +{ + IF_HAVE_RUN(p_vdec2(), clock_on); +} +EXPORT_SYMBOL(vdec2_clock_on); + +void vdec2_clock_off(void) +{ + IF_HAVE_RUN(p_vdec2(), clock_off); + clock_source_wxhxfps_saved[VDEC_2] = 0; +} +EXPORT_SYMBOL(vdec2_clock_off); + +int hcodec_clock_set(int clk) +{ + pr_debug("%s-----%d\n", __func__, clk); + if (p_vdec_hcodec() && p_vdec_hcodec()->clock_set) + return p_vdec_hcodec()->clock_set(clk); + else + return -1; +} +EXPORT_SYMBOL(hcodec_clock_set); + +void hcodec_clock_enable(void) +{ + hcodec_clock_set(1); +} +EXPORT_SYMBOL(hcodec_clock_enable); + +void hcodec_clock_hi_enable(void) +{ + hcodec_clock_set(2); +} +EXPORT_SYMBOL(hcodec_clock_hi_enable); + +void hcodec_clock_on(void) +{ + IF_HAVE_RUN(p_vdec_hcodec(), clock_on); +} +EXPORT_SYMBOL(hcodec_clock_on); + +void hcodec_clock_off(void) +{ + IF_HAVE_RUN(p_vdec_hcodec(), clock_off); + clock_source_wxhxfps_saved[VDEC_HCODEC] = 0; +} +EXPORT_SYMBOL(hcodec_clock_off); + +int hevc_back_clock_init(void) +{ + if (p_vdec_hevc_back() && p_vdec_hevc_back()->clock_init) + return p_vdec_hevc_back()->clock_init(); + else + return 0; +} +EXPORT_SYMBOL(hevc_back_clock_init); + +int hevc_back_clock_set(int clk) +{ + pr_debug("%s-----%d\n", __func__, clk); + if (p_vdec_hevc_back() && p_vdec_hevc_back()->clock_set) + return p_vdec_hevc_back()->clock_set(clk); + else + return -1; +} +EXPORT_SYMBOL(hevc_back_clock_set); + +void hevc_back_clock_enable(void) +{ + hevc_back_clock_set(1); +} +EXPORT_SYMBOL(hevc_back_clock_enable); + +void hevc_back_clock_hi_enable(void) +{ + hevc_back_clock_set(2); +} +EXPORT_SYMBOL(hevc_back_clock_hi_enable); + +int hevc_clock_init(void) +{ + if (p_vdec_hevc() && p_vdec_hevc()->clock_init) + return p_vdec_hevc()->clock_init(); + else + return 0; +} +EXPORT_SYMBOL(hevc_clock_init); + +int hevc_clock_set(int clk) +{ + pr_debug("%s-----%d\n", __func__, clk); + if (p_vdec_hevc() && p_vdec_hevc()->clock_set) + return p_vdec_hevc()->clock_set(clk); + else + return -1; +} +EXPORT_SYMBOL(hevc_clock_set); + +void hevc_clock_enable(void) +{ + hevc_clock_set(1); +} +EXPORT_SYMBOL(hevc_clock_enable); + +void hevc_clock_hi_enable(void) +{ + hevc_clock_set(2); +} +EXPORT_SYMBOL(hevc_clock_hi_enable); + +void hevc_back_clock_on(void) +{ + IF_HAVE_RUN(p_vdec_hevc_back(), clock_on); +} +EXPORT_SYMBOL(hevc_back_clock_on); + +void hevc_back_clock_off(void) +{ + IF_HAVE_RUN(p_vdec_hevc_back(), clock_off); + clock_source_wxhxfps_saved[VDEC_HEVCB] = 0; +} +EXPORT_SYMBOL(hevc_back_clock_off); + +void hevc_clock_on(void) +{ + IF_HAVE_RUN(p_vdec_hevc(), clock_on); +} +EXPORT_SYMBOL(hevc_clock_on); + +void hevc_clock_off(void) +{ + IF_HAVE_RUN(p_vdec_hevc(), clock_off); + clock_source_wxhxfps_saved[VDEC_HEVC] = 0; +} +EXPORT_SYMBOL(hevc_clock_off); + +int vdec_source_get(enum vdec_type_e core) +{ + return clock_source_wxhxfps_saved[core]; +} +EXPORT_SYMBOL(vdec_source_get); + +int vdec_clk_get(enum vdec_type_e core) +{ + return get_current_vdec_chip()->clk_mgr[core]->clock_get(core); +} +EXPORT_SYMBOL(vdec_clk_get); + +int get_clk_with_source(int format, int w_x_h_fps) +{ + struct clk_set_setting *p_setting; + int i; + int clk = -2; + + p_setting = get_current_vdec_chip()->clk_setting_array; + if (!p_setting || format < 0 || format > VFORMAT_MAX) { + pr_info("error on get_clk_with_source ,%p,%d\n", + p_setting, format); + return -1; /*no setting found. */ + } + p_setting = &p_setting[format]; + for (i = 0; i < MAX_CLK_SET; i++) { + if (p_setting->set[i].wh_X_fps > w_x_h_fps) { + clk = p_setting->set[i].clk_Mhz; + break; + } + } + return clk; +} +EXPORT_SYMBOL(get_clk_with_source); + +int vdec_source_changed_for_clk_set(int format, int width, int height, int fps) +{ + int clk = get_clk_with_source(format, width * height * fps); + int ret_clk; + + if (clk < 0) { + pr_info("can't get valid clk for source ,%d,%d,%d\n", + width, height, fps); + if (format >= 1920 && width >= 1080 && fps >= 30) + clk = 2; /*default high clk */ + else + clk = 0; /*default clk. */ + } + if (width * height * fps == 0) + clk = 0; + /* + *clk == 0 + *is used for set default clk; + *if used supper clk. + *changed to default min clk. + */ + + if (format == VFORMAT_HEVC || format == VFORMAT_VP9 + || format == VFORMAT_AVS2) { + ret_clk = hevc_clock_set(clk); + clock_source_wxhxfps_saved[VDEC_HEVC] = width * height * fps; + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) { + ret_clk = hevc_back_clock_set(clk); + clock_source_wxhxfps_saved[VDEC_HEVCB] = width * height * fps; + } + } else if (format == VFORMAT_H264_ENC || format == VFORMAT_JPEG_ENC) { + ret_clk = hcodec_clock_set(clk); + clock_source_wxhxfps_saved[VDEC_HCODEC] = width * height * fps; + } else if (format == VFORMAT_H264_4K2K && + get_cpu_type() == MESON_CPU_MAJOR_ID_M8) { + ret_clk = vdec2_clock_set(clk); + clock_source_wxhxfps_saved[VDEC_2] = width * height * fps; + ret_clk = vdec_clock_set(clk); + clock_source_wxhxfps_saved[VDEC_1] = width * height * fps; + } else { + ret_clk = vdec_clock_set(clk); + clock_source_wxhxfps_saved[VDEC_1] = width * height * fps; + } + return ret_clk; +} +EXPORT_SYMBOL(vdec_source_changed_for_clk_set); + +static int register_vdec_clk_mgr_per_cpu(int cputype, + enum vdec_type_e vdec_type, struct chip_vdec_clk_s *t_mgr) +{ + + struct chip_vdec_clk_s *mgr; + + if (cputype != get_cpu_type() || vdec_type >= VDEC_MAX) { + /* + *pr_info("ignore vdec clk mgr for vdec[%d] cpu=%d\n", + *vdec_type, cputype); + */ + return 0; /* ignore don't needed firmare. */ + } + mgr = kmalloc(sizeof(struct chip_vdec_clk_s), GFP_KERNEL); + if (!mgr) + return -ENOMEM; + *mgr = *t_mgr; + /* + *pr_info("register vdec clk mgr for vdec[%d]\n", vdec_type); + */ + if (mgr->clock_init) { + if (mgr->clock_init()) { + kfree(mgr); + return -ENOMEM; + } + } + get_current_vdec_chip()->clk_mgr[vdec_type] = mgr; + return 0; +} + +int register_vdec_clk_mgr(int cputype[], enum vdec_type_e vdec_type, + struct chip_vdec_clk_s *t_mgr) +{ + int i = 0; + + while (cputype[i] > 0) { + register_vdec_clk_mgr_per_cpu(cputype[i], vdec_type, t_mgr); + i++; + } + return 0; +} +EXPORT_SYMBOL(register_vdec_clk_mgr); + +int unregister_vdec_clk_mgr(enum vdec_type_e vdec_type) +{ + kfree(get_current_vdec_chip()->clk_mgr[vdec_type]); + + return 0; +} +EXPORT_SYMBOL(unregister_vdec_clk_mgr); + +static int register_vdec_clk_setting_per_cpu(int cputype, + struct clk_set_setting *setting, int size) +{ + + struct clk_set_setting *p_setting; + + if (cputype != get_cpu_type()) { + /* + *pr_info("ignore clk_set_setting for cpu=%d\n", + *cputype); + */ + return 0; /* ignore don't needed this setting . */ + } + p_setting = kmalloc(size, GFP_KERNEL); + if (!p_setting) + return -ENOMEM; + memcpy(p_setting, setting, size); + + pr_info("register clk_set_setting cpu[%d]\n", cputype); + + get_current_vdec_chip()->clk_setting_array = p_setting; + return 0; +} + +int register_vdec_clk_setting(int cputype[], + struct clk_set_setting *p_seting, int size) +{ + int i = 0; + + while (cputype[i] > 0) { + register_vdec_clk_setting_per_cpu(cputype[i], p_seting, size); + i++; + } + return 0; +} +EXPORT_SYMBOL(register_vdec_clk_setting); + +int unregister_vdec_clk_setting(void) +{ + kfree(get_current_vdec_chip()->clk_setting_array); + + return 0; +} +EXPORT_SYMBOL(unregister_vdec_clk_setting); + diff --git a/drivers/amlogic/media_modules/common/media_clock/clk/clk.h b/drivers/amlogic/media_modules/common/media_clock/clk/clk.h new file mode 100644 index 000000000000..5fefcbc6c335 --- /dev/null +++ b/drivers/amlogic/media_modules/common/media_clock/clk/clk.h @@ -0,0 +1,172 @@ +/* + * drivers/amlogic/media/common/arch/clk/clk.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef VDEC_CHIP_CLK_HEADER +#define VDEC_CHIP_CLK_HEADER +#include +#include +#include +#include "clk_priv.h" +#include + +#ifndef INCLUDE_FROM_ARCH_CLK_MGR +int vdec_clock_init(void); +int vdec_clock_set(int clk); +int vdec2_clock_set(int clk); + +int hcodec_clock_set(int clk); +int hevc_clock_init(void); +int hevc_clock_set(int clk); + +void vdec_clock_on(void); +void vdec_clock_off(void); +void vdec2_clock_on(void); + +void vdec2_clock_off(void); +void hcodec_clock_on(void); +void hcodec_clock_off(void); +void hevc_clock_on(void); +void hevc_clock_off(void); + +int hevc_back_clock_init(void); +void hevc_back_clock_on(void); +void hevc_back_clock_off(void); +int hevc_back_clock_set(int clk); +void hevc_back_clock_enable(void); +void hevc_back_clock_hi_enable(void); + +int vdec_source_get(enum vdec_type_e core); +int vdec_clk_get(enum vdec_type_e core); + +int vdec_source_changed_for_clk_set(int format, int width, int height, int fps); +int get_clk_with_source(int format, int w_x_h_fps); + +void vdec_clock_enable(void); +void vdec_clock_hi_enable(void); +void hcodec_clock_enable(void); +void hcodec_clock_hi_enable(void); +void hevc_clock_enable(void); +void hevc_clock_hi_enable(void); +void vdec2_clock_enable(void); +void vdec2_clock_hi_enable(void); +void set_clock_gate(struct gate_switch_node *nodes, int num); + +#endif +int register_vdec_clk_mgr(int cputype[], + enum vdec_type_e vdec_type, struct chip_vdec_clk_s *t_mgr); + +int unregister_vdec_clk_mgr(enum vdec_type_e vdec_type); + +int register_vdec_clk_setting(int cputype[], + struct clk_set_setting *p_seting, int size); + +int unregister_vdec_clk_setting(void); + +#ifdef INCLUDE_FROM_ARCH_CLK_MGR +static struct chip_vdec_clk_s vdec_clk_mgr __initdata = { + .clock_init = vdec_clock_init, + .clock_set = vdec_clock_set, + .clock_on = vdec_clock_on, + .clock_off = vdec_clock_off, + .clock_get = vdec_clock_get, +}; + +#ifdef VDEC_HAS_VDEC2 +static struct chip_vdec_clk_s vdec2_clk_mgr __initdata = { + .clock_set = vdec2_clock_set, + .clock_on = vdec2_clock_on, + .clock_off = vdec2_clock_off, + .clock_get = vdec_clock_get, +}; +#endif + +#ifdef VDEC_HAS_HEVC +static struct chip_vdec_clk_s vdec_hevc_clk_mgr __initdata = { + .clock_init = hevc_clock_init, + .clock_set = hevc_clock_set, + .clock_on = hevc_clock_on, + .clock_off = hevc_clock_off, + .clock_get = vdec_clock_get, +}; +static struct chip_vdec_clk_s vdec_hevc_back_clk_mgr __initdata = { + .clock_init = hevc_back_clock_init, + .clock_set = hevc_back_clock_set, + .clock_on = hevc_back_clock_on, + .clock_off = hevc_back_clock_off, + .clock_get = vdec_clock_get, +}; +#endif + +#ifdef VDEC_HAS_VDEC_HCODEC +static struct chip_vdec_clk_s vdec_hcodec_clk_mgr __initdata = { + .clock_set = hcodec_clock_set, + .clock_on = hcodec_clock_on, + .clock_off = hcodec_clock_off, + .clock_get = vdec_clock_get, +}; +#endif + +static int __init vdec_init_clk(void) +{ + int cpus[] = CLK_FOR_CPU; + + register_vdec_clk_mgr(cpus, VDEC_1, &vdec_clk_mgr); +#ifdef VDEC_HAS_VDEC2 + register_vdec_clk_mgr(cpus, VDEC_2, &vdec2_clk_mgr); +#endif +#ifdef VDEC_HAS_HEVC + register_vdec_clk_mgr(cpus, VDEC_HEVC, &vdec_hevc_clk_mgr); + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) + register_vdec_clk_mgr(cpus, VDEC_HEVCB, &vdec_hevc_back_clk_mgr); +#endif +#ifdef VDEC_HAS_VDEC_HCODEC + register_vdec_clk_mgr(cpus, VDEC_HCODEC, &vdec_hcodec_clk_mgr); +#endif + +#ifdef VDEC_HAS_CLK_SETTINGS + register_vdec_clk_setting(cpus, + clks_for_formats, sizeof(clks_for_formats)); +#endif + return 0; +} + +static void __exit vdec_clk_exit(void) +{ + unregister_vdec_clk_mgr(VDEC_1); +#ifdef VDEC_HAS_VDEC2 + unregister_vdec_clk_mgr(VDEC_2); +#endif +#ifdef VDEC_HAS_HEVC + unregister_vdec_clk_mgr(VDEC_HEVC); +#endif +#ifdef VDEC_HAS_VDEC_HCODEC + unregister_vdec_clk_mgr(VDEC_HCODEC); +#endif +#ifdef VDEC_HAS_CLK_SETTINGS + unregister_vdec_clk_setting(); +#endif + pr_info("media clock exit.\n"); +} + +#define ARCH_VDEC_CLK_INIT()\ + module_init(vdec_init_clk) + +#define ARCH_VDEC_CLK_EXIT()\ + module_exit(vdec_clk_exit) + +#endif +#endif diff --git a/drivers/amlogic/media_modules/common/media_clock/clk/clk_priv.h b/drivers/amlogic/media_modules/common/media_clock/clk/clk_priv.h new file mode 100644 index 000000000000..60b7be09d6e9 --- /dev/null +++ b/drivers/amlogic/media_modules/common/media_clock/clk/clk_priv.h @@ -0,0 +1,38 @@ +/* + * drivers/amlogic/media/common/arch/clk/clk_priv.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef AMPORTS_CLK_PRIV_HEADER +#define AMPORTS_CLK_PRIV_HEADER + +struct clk_set { + u32 wh_X_fps; /* [x*y*fps */ + u32 clk_Mhz; /*min MHZ */ +}; +#define MAX_CLK_SET 6 +struct clk_set_setting { + struct clk_set set[MAX_CLK_SET]; +}; + +struct chip_vdec_clk_s { + int (*clock_get)(enum vdec_type_e core); + int (*clock_init)(void); + int (*clock_set)(int clk); + void (*clock_on)(void); + void (*clock_off)(void); + void (*clock_prepare_switch)(void); +}; +#endif diff --git a/drivers/amlogic/media_modules/common/media_clock/clk/clkg12.c b/drivers/amlogic/media_modules/common/media_clock/clk/clkg12.c new file mode 100644 index 000000000000..d7111eb63eca --- /dev/null +++ b/drivers/amlogic/media_modules/common/media_clock/clk/clkg12.c @@ -0,0 +1,1006 @@ +/* + * drivers/amlogic/media/common/arch/clk/clkgx.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../../frame_provider/decoder/utils/vdec.h" +#include +#include "clk_priv.h" +#include + +#include +#include "../switch/amports_gate.h" +#define MHz (1000000) +#define debug_print pr_info + +//#define NO_CLKTREE + +/* set gp0 648M vdec use gp0 clk*/ +#define VDEC1_648M() \ + WRITE_HHI_REG_BITS(HHI_VDEC_CLK_CNTL, (6 << 9) | (0), 0, 16) + +#define HEVC_648M() \ + WRITE_HHI_REG_BITS(HHI_VDEC2_CLK_CNTL, (6 << 9) | (0), 16, 16) + +/*set gp0 1296M vdec use gp0 clk div2*/ +#define VDEC1_648M_DIV() \ + WRITE_HHI_REG_BITS(HHI_VDEC_CLK_CNTL, (6 << 9) | (1), 0, 16) + +#define HEVC_648M_DIV() \ + WRITE_HHI_REG_BITS(HHI_VDEC2_CLK_CNTL, (6 << 9) | (1), 16, 16) + +#define VDEC1_WITH_GP_PLL() \ + ((READ_HHI_REG(HHI_VDEC_CLK_CNTL) & 0xe00) == 0xc00) +#define HEVC_WITH_GP_PLL() \ + ((READ_HHI_REG(HHI_VDEC2_CLK_CNTL) & 0xe000000) == 0xc000000) + +#define VDEC1_CLOCK_ON() \ + do { if (is_meson_m8_cpu()) { \ + WRITE_HHI_REG_BITS(HHI_VDEC_CLK_CNTL, 1, 8, 1); \ + WRITE_VREG_BITS(DOS_GCLK_EN0, 0x3ff, 0, 10); \ + } else { \ + WRITE_HHI_REG_BITS(HHI_VDEC_CLK_CNTL, 1, 8, 1); \ + WRITE_HHI_REG_BITS(HHI_VDEC3_CLK_CNTL, 0, 15, 1); \ + WRITE_HHI_REG_BITS(HHI_VDEC3_CLK_CNTL, 0, 8, 1); \ + WRITE_VREG_BITS(DOS_GCLK_EN0, 0x3ff, 0, 10); \ + } \ + } while (0) + +#define VDEC2_CLOCK_ON() do {\ + WRITE_HHI_REG_BITS(HHI_VDEC2_CLK_CNTL, 1, 8, 1); \ + WRITE_VREG(DOS_GCLK_EN1, 0x3ff);\ + } while (0) + +#define HCODEC_CLOCK_ON() do {\ + WRITE_HHI_REG_BITS(HHI_VDEC_CLK_CNTL, 1, 24, 1); \ + WRITE_VREG_BITS(DOS_GCLK_EN0, 0x7fff, 12, 15);\ + } while (0) +#define HEVC_CLOCK_ON() do {\ + WRITE_HHI_REG_BITS(HHI_VDEC2_CLK_CNTL, 1, 24, 1); \ + WRITE_HHI_REG_BITS(HHI_VDEC2_CLK_CNTL, 1, 8, 1); \ + WRITE_HHI_REG_BITS(HHI_VDEC4_CLK_CNTL, 0, 31, 1); \ + WRITE_HHI_REG_BITS(HHI_VDEC4_CLK_CNTL, 0, 15, 1); \ + WRITE_HHI_REG_BITS(HHI_VDEC4_CLK_CNTL, 0, 24, 1); \ + WRITE_VREG(DOS_GCLK_EN3, 0xffffffff);\ + } while (0) +#define VDEC1_SAFE_CLOCK() do {\ + WRITE_HHI_REG_BITS(HHI_VDEC3_CLK_CNTL, \ + READ_HHI_REG(HHI_VDEC_CLK_CNTL) & 0x7f, 0, 7); \ + WRITE_HHI_REG_BITS(HHI_VDEC3_CLK_CNTL, 1, 8, 1); \ + WRITE_HHI_REG_BITS(HHI_VDEC3_CLK_CNTL, 1, 15, 1);\ + } while (0) + +#define VDEC1_CLOCK_OFF() \ + WRITE_HHI_REG_BITS(HHI_VDEC_CLK_CNTL, 0, 8, 1) +#define VDEC2_CLOCK_OFF() \ + WRITE_HHI_REG_BITS(HHI_VDEC2_CLK_CNTL, 0, 8, 1) +#define HCODEC_CLOCK_OFF() \ + WRITE_HHI_REG_BITS(HHI_VDEC_CLK_CNTL, 0, 24, 1) +#define HEVC_SAFE_CLOCK() do { \ + WRITE_HHI_REG_BITS(HHI_VDEC4_CLK_CNTL, \ + (READ_HHI_REG(HHI_VDEC2_CLK_CNTL) >> 16) & 0x7f, 16, 7);\ + WRITE_HHI_REG_BITS(HHI_VDEC4_CLK_CNTL, \ + (READ_HHI_REG(HHI_VDEC2_CLK_CNTL) >> 25) & 0x7f, 25, 7);\ + WRITE_HHI_REG_BITS(HHI_VDEC4_CLK_CNTL, 1, 24, 1); \ + WRITE_HHI_REG_BITS(HHI_VDEC4_CLK_CNTL, 1, 31, 1);\ + WRITE_HHI_REG_BITS(HHI_VDEC4_CLK_CNTL, 1, 15, 1);\ + } while (0) + +#define HEVC_CLOCK_OFF() do {\ + WRITE_HHI_REG_BITS(HHI_VDEC2_CLK_CNTL, 0, 24, 1);\ + WRITE_HHI_REG_BITS(HHI_VDEC2_CLK_CNTL, 0, 8, 1);\ +}while(0) + +static int clock_real_clk[VDEC_MAX + 1]; + +static unsigned int set_frq_enable, vdec_frq, hevc_frq, hevcb_frq; + +#ifdef NO_CLKTREE +static struct gp_pll_user_handle_s *gp_pll_user_vdec, *gp_pll_user_hevc; +static bool is_gp0_div2 = true; + +static int gp_pll_user_cb_vdec(struct gp_pll_user_handle_s *user, + int event) +{ + debug_print("gp_pll_user_cb_vdec call\n"); + if (event == GP_PLL_USER_EVENT_GRANT) { + struct clk *clk = clk_get(NULL, "gp0_pll"); + if (!IS_ERR(clk)) { + if (is_gp0_div2) + clk_set_rate(clk, 1296000000UL); + else + clk_set_rate(clk, 648000000UL); + VDEC1_SAFE_CLOCK(); + VDEC1_CLOCK_OFF(); + if (is_gp0_div2) + VDEC1_648M_DIV(); + else + VDEC1_648M(); + + VDEC1_CLOCK_ON(); + debug_print("gp_pll_user_cb_vdec call set\n"); + } + } + return 0; +} + +static int gp_pll_user_cb_hevc(struct gp_pll_user_handle_s *user, + int event) +{ + debug_print("gp_pll_user_cb_hevc callback\n"); + if (event == GP_PLL_USER_EVENT_GRANT) { + struct clk *clk = clk_get(NULL, "gp0_pll"); + if (!IS_ERR(clk)) { + if (is_gp0_div2) + clk_set_rate(clk, 1296000000UL); + else + clk_set_rate(clk, 648000000UL); +// HEVC_SAFE_CLOCK(); + HEVC_CLOCK_OFF(); + if (is_gp0_div2) + HEVC_648M_DIV(); + else + HEVC_648M(); + HEVC_CLOCK_ON(); + debug_print("gp_pll_user_cb_hevc callback2\n"); + } + } + + return 0; +} + + +#endif + +struct clk_mux_s { + struct gate_switch_node *vdec_mux_node; + struct gate_switch_node *hcodec_mux_node; + struct gate_switch_node *hevc_mux_node; + struct gate_switch_node *hevc_back_mux_node; +}; + +struct clk_mux_s gclk; + +void vdec1_set_clk(int source, int div) +{ + pr_debug("vdec1_set_clk %d, %d\n", source, div); + WRITE_HHI_REG_BITS(HHI_VDEC_CLK_CNTL, (source << 9) | (div - 1), 0, 16); +} +EXPORT_SYMBOL(vdec1_set_clk); + +void hcodec_set_clk(int source, int div) +{ + WRITE_HHI_REG_BITS(HHI_VDEC_CLK_CNTL, + (source << 9) | (div - 1), 16, 16); +} +EXPORT_SYMBOL(hcodec_set_clk); + +void vdec2_set_clk(int source, int div) +{ + WRITE_HHI_REG_BITS(HHI_VDEC2_CLK_CNTL, + (source << 9) | (div - 1), 0, 16); +} +EXPORT_SYMBOL(vdec2_set_clk); + +//extern uint force_hevc_clock_cntl; +uint force_hevc_clock_cntl = 0; +void hevc_set_clk(int source, int div) +{ + if (force_hevc_clock_cntl) { + pr_info("%s, write force clock cntl %x\n", __func__, force_hevc_clock_cntl); + WRITE_HHI_REG(HHI_VDEC2_CLK_CNTL, force_hevc_clock_cntl); + } else { + pr_debug("hevc_set_clk %d, %d\n", source, div); + WRITE_HHI_REG_BITS(HHI_VDEC2_CLK_CNTL, + (source << 9) | (div - 1), 16, 16); + WRITE_HHI_REG_BITS(HHI_VDEC2_CLK_CNTL, (source << 9) | (div - 1), 0, 16); + } +} +EXPORT_SYMBOL(hevc_set_clk); + +void vdec_get_clk_source(int clk, int *source, int *div, int *rclk) +{ +#define source_div4 (0) +#define source_div3 (1) +#define source_div5 (2) +#define source_div7 (3) + if (clk > 500) { + *source = source_div3; + *div = 1; + *rclk = 667; + } else if (clk >= 500) { + *source = source_div4; + *div = 1; + *rclk = 500; + } else if (clk >= 400) { + *source = source_div5; + *div = 1; + *rclk = 400; + } else if (clk >= 333) { + *source = source_div3; + *div = 2; + *rclk = 333; + } else if (clk >= 200) { + *source = source_div5; + *div = 2; + *rclk = 200; + } else if (clk >= 166) { + *source = source_div4; + *div = 3; + *rclk = 166; + } else if (clk >= 133) { + *source = source_div5; + *div = 3; + *rclk = 133; + } else if (clk >= 100) { + *source = source_div5; + *div = 4; + *rclk = 100; + } else if (clk >= 50) { + *source = source_div5; + *div = 8; + *rclk = 50; + } else { + *source = source_div5; + *div = 20; + *rclk = 10; + } +} +EXPORT_SYMBOL(vdec_get_clk_source); + + +/* + *enum vformat_e { + * VFORMAT_MPEG12 = 0, + * VFORMAT_MPEG4, + * VFORMAT_H264, + * VFORMAT_MJPEG, + * VFORMAT_REAL, + * VFORMAT_JPEG, + * VFORMAT_VC1, + * VFORMAT_AVS, + * VFORMAT_YUV, + * VFORMAT_H264MVC, + * VFORMAT_H264_4K2K, + * VFORMAT_HEVC, + * VFORMAT_H264_ENC, + * VFORMAT_JPEG_ENC, + * VFORMAT_VP9, + * VFORMAT_MAX + *}; + *sample: + *{{1280*720*30, 100}, {1920*1080*30, 166}, {1920*1080*60, 333}, + * {4096*2048*30, 600}, {4096*2048*60, 600}, {INT_MAX, 600},} + *mean: + *width * height * fps + *<720p30fps clk=100MHZ + *>=720p30fps & < 1080p30fps clk=166MHZ + *>=1080p 30fps & < 1080p60fps clk=333MHZ + */ +static struct clk_set_setting clks_for_formats[] = { + { /*[VFORMAT_MPEG12] */ + {{1280 * 720 * 30, 100}, {1920 * 1080 * 30, 166}, + {1920 * 1080 * 60, 333}, + {4096 * 2048 * 30, 600}, {4096 * 2048 * 60, + 600}, {INT_MAX, 600}, + } + }, + { /*[VFORMAT_MPEG4] */ + {{1280 * 720 * 30, 100}, {1920 * 1080 * 30, 166}, + {1920 * 1080 * 60, 333}, + {4096 * 2048 * 30, 600}, {4096 * 2048 * 60, + 600}, {INT_MAX, 600}, + } + }, + { /*[VFORMAT_H264] */ + {{1280 * 720 * 30, 100}, {1920 * 1080 * 21, 166}, + {1920 * 1080 * 30, 333}, + {1920 * 1080 * 60, 600}, {4096 * 2048 * 60, + 600}, {INT_MAX, 600}, + } + }, + { /*[VFORMAT_MJPEG] */ + {{1280 * 720 * 30, 200}, {1920 * 1080 * 30, 200}, + {1920 * 1080 * 60, 333}, + {4096 * 2048 * 30, 600}, {4096 * 2048 * 60, + 600}, {INT_MAX, 600}, + } + }, + { /*[VFORMAT_REAL] */ + {{1280 * 720 * 20, 200}, {1920 * 1080 * 30, 500}, + {1920 * 1080 * 60, 500}, + {4096 * 2048 * 30, 600}, {4096 * 2048 * 60, + 600}, {INT_MAX, 600}, + } + }, + { /*[VFORMAT_JPEG] */ + {{1280 * 720 * 30, 100}, {1920 * 1080 * 30, 166}, + {1920 * 1080 * 60, 333}, + {4096 * 2048 * 30, 600}, {4096 * 2048 * 60, + 600}, {INT_MAX, 600}, + } + }, + { /*[VFORMAT_VC1] */ + {{1280 * 720 * 30, 100}, {1920 * 1080 * 30, 166}, + {1920 * 1080 * 60, 333}, + {4096 * 2048 * 30, 600}, {4096 * 2048 * 60, + 600}, {INT_MAX, 600}, + } + }, + { /*[VFORMAT_AVS] */ + {{1280 * 720 * 30, 100}, {1920 * 1080 * 30, 166}, + {1920 * 1080 * 60, 333}, + {4096 * 2048 * 30, 600}, {4096 * 2048 * 60, + 600}, {INT_MAX, 600}, + } + }, + { /*[VFORMAT_YUV] */ + {{1280 * 720 * 30, 100}, {INT_MAX, 100}, + {0, 0}, {0, 0}, {0, 0}, {0, 0}, + } + }, + { /*VFORMAT_H264MVC */ + {{1280 * 720 * 30, 333}, {1920 * 1080 * 30, 333}, + {4096 * 2048 * 60, 600}, + {INT_MAX, 630}, {0, 0}, {0, 0}, + } + }, + { /*VFORMAT_H264_4K2K */ + {{1280 * 720 * 30, 600}, {4096 * 2048 * 60, 630}, + {INT_MAX, 630}, + {0, 0}, {0, 0}, {0, 0}, + } + }, + { /*VFORMAT_HEVC */ + {{1280 * 720 * 30, 100}, {1920 * 1080 * 60, 600}, + {4096 * 2048 * 25, 630}, + {4096 * 2048 * 30, 630}, {4096 * 2048 * 60, + 630}, {INT_MAX, 630}, + } + }, + { /*VFORMAT_H264_ENC */ + {{1280 * 720 * 30, 0}, {INT_MAX, 0}, + {0, 0}, {0, 0}, {0, 0}, {0, 0}, + } + }, + { /*VFORMAT_JPEG_ENC */ + {{1280 * 720 * 30, 0}, {INT_MAX, 0}, + {0, 0}, {0, 0}, {0, 0}, {0, 0}, + } + }, + { /*VFORMAT_VP9 */ + {{1280 * 720 * 30, 100}, {1920 * 1080 * 30, 100}, + {1920 * 1080 * 60, 166}, + {4096 * 2048 * 30, 333}, {4096 * 2048 * 60, + 630}, {INT_MAX, 630}, + } + }, + +}; + +void set_clock_gate(struct gate_switch_node *nodes, int num) +{ + struct gate_switch_node *node = NULL; + + do { + node = &nodes[num - 1]; + if (IS_ERR_OR_NULL(node)) + pr_info("get mux clk err.\n"); + + if (!strcmp(node->name, "clk_vdec_mux")) + gclk.vdec_mux_node = node; + else if (!strcmp(node->name, "clk_hcodec_mux")) + gclk.hcodec_mux_node = node; + else if (!strcmp(node->name, "clk_hevc_mux")) + gclk.hevc_mux_node = node; + else if (!strcmp(node->name, "clk_hevcb_mux")) + gclk.hevc_back_mux_node = node; + } while(--num); +} +EXPORT_SYMBOL(set_clock_gate); +#ifdef NO_CLKTREE +int vdec_set_clk(int dec, int source, int div) +{ + + if (dec == VDEC_1) + vdec1_set_clk(source, div); + else if (dec == VDEC_2) + vdec2_set_clk(source, div); + else if (dec == VDEC_HEVC) + hevc_set_clk(source, div); + else if (dec == VDEC_HCODEC) + hcodec_set_clk(source, div); + return 0; +} + +#else +static int vdec_set_clk(int dec, int rate) +{ + struct clk *clk = NULL; + + switch (dec) { + case VDEC_1: + clk = gclk.vdec_mux_node->clk; + WRITE_VREG_BITS(DOS_GCLK_EN0, 0x3ff, 0, 10); + break; + + case VDEC_HCODEC: + clk = gclk.hcodec_mux_node->clk; + WRITE_VREG_BITS(DOS_GCLK_EN0, 0x7fff, 12, 15); + break; + + case VDEC_2: + clk = gclk.vdec_mux_node->clk; + WRITE_VREG(DOS_GCLK_EN1, 0x3ff); + break; + + case VDEC_HEVC: + clk = gclk.hevc_mux_node->clk; + WRITE_VREG(DOS_GCLK_EN3, 0xffffffff); + break; + + case VDEC_HEVCB: + clk = gclk.hevc_back_mux_node->clk; + WRITE_VREG(DOS_GCLK_EN3, 0xffffffff); + break; + + case VDEC_MAX: + break; + + default: + pr_info("invaild vdec type.\n"); + } + + if (IS_ERR_OR_NULL(clk)) { + pr_info("the mux clk err.\n"); + return -1; + } + + clk_set_rate(clk, rate); + + return 0; +} + +static int vdec_clock_init(void) +{ + return 0; +} + +#endif +#ifdef NO_CLKTREE +static int vdec_clock_init(void) +{ + gp_pll_user_vdec = gp_pll_user_register("vdec", 0, + gp_pll_user_cb_vdec); + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) + is_gp0_div2 = false; + else + is_gp0_div2 = true; + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) { + pr_info("used fix clk for vdec clk source!\n"); + //update_vdec_clk_config_settings(1); + } + return (gp_pll_user_vdec) ? 0 : -ENOMEM; +} + + + +static void update_clk_with_clk_configs( + int clk, int *source, int *div, int *rclk) +{ + unsigned int config = 0;//get_vdec_clk_config_settings(); + + if (!config) + return; + if (config >= 10) { + int wantclk; + wantclk = config; + vdec_get_clk_source(wantclk, source, div, rclk); + } + return; +} +#define NO_GP0_PLL 0//(get_vdec_clk_config_settings() == 1) +#define ALWAYS_GP0_PLL 0//(get_vdec_clk_config_settings() == 2) + +#define NO_GP0_PLL 0//(get_vdec_clk_config_settings() == 1) +#define ALWAYS_GP0_PLL 0//(get_vdec_clk_config_settings() == 2) + +static int vdec_clock_set(int clk) +{ + int use_gpll = 0; + int source, div, rclk; + int clk_seted = 0; + int gp_pll_wait = 0; + if (clk == 1) + clk = 200; + else if (clk == 2) { + if (clock_real_clk[VDEC_1] != 648) + clk = 500; + else + clk = 648; + } else if (clk == 0) { + /*used for release gp pull. + if used, release it. + if not used gp pll + do nothing. + */ + if (clock_real_clk[VDEC_1] == 667 || + (clock_real_clk[VDEC_1] == 648) || + clock_real_clk[VDEC_1] <= 0) + clk = 200; + else + clk = clock_real_clk[VDEC_1]; + } + vdec_get_clk_source(clk, &source, &div, &rclk); + update_clk_with_clk_configs(clk, &source, &div, &rclk); + + if (clock_real_clk[VDEC_1] == rclk) + return rclk; + if (NO_GP0_PLL) { + use_gpll = 0; + clk_seted = 0; + } else if ((rclk > 500 && clk != 667) || ALWAYS_GP0_PLL) { + if (clock_real_clk[VDEC_1] == 648) + return 648; + use_gpll = 1; + gp_pll_request(gp_pll_user_vdec); + while (!VDEC1_WITH_GP_PLL() && gp_pll_wait++ < 1000000) + udelay(1); + if (VDEC1_WITH_GP_PLL()) { + clk_seted = 1; + rclk = 648; + } else { + use_gpll = 0; + rclk = 667; + /*gp_pull request failed,used default 500Mhz*/ + pr_info("get gp pll failed used fix pull\n"); + } + } + if (!clk_seted) {/*if 648 not set,*/ + VDEC1_SAFE_CLOCK(); + VDEC1_CLOCK_OFF(); + vdec_set_clk(VDEC_1, source, div); + VDEC1_CLOCK_ON(); + } + + if (!use_gpll) + gp_pll_release(gp_pll_user_vdec); + clock_real_clk[VDEC_1] = rclk; + debug_print("vdec_clock_set 2 to %d\n", rclk); + return rclk; +} +static int hevc_clock_init(void) +{ + gp_pll_user_hevc = gp_pll_user_register("hevc", 0, + gp_pll_user_cb_hevc); + + return (gp_pll_user_hevc) ? 0 : -ENOMEM; +} +static int hevc_clock_set(int clk) +{ + int use_gpll = 0; + int source, div, rclk; + int gp_pll_wait = 0; + int clk_seted = 0; + + debug_print("hevc_clock_set 1 to clk %d\n", clk); + if (clk == 1) + clk = 200; + else if (clk == 2) { + if (clock_real_clk[VDEC_HEVC] != 648) + clk = 500; + else + clk = 648; + } else if (clk == 0) { + /*used for release gp pull. + if used, release it. + if not used gp pll + do nothing. + */ + if ((clock_real_clk[VDEC_HEVC] == 667) || + (clock_real_clk[VDEC_HEVC] == 648) || + (clock_real_clk[VDEC_HEVC] <= 0)) + clk = 200; + else + clk = clock_real_clk[VDEC_HEVC]; + } + vdec_get_clk_source(clk, &source, &div, &rclk); + update_clk_with_clk_configs(clk, &source, &div, &rclk); + + if (rclk == clock_real_clk[VDEC_HEVC]) + return rclk;/*clk not changed,*/ + if (NO_GP0_PLL) { + use_gpll = 0; + clk_seted = 0; + } else if ((rclk > 500 && clk != 667) || ALWAYS_GP0_PLL) { + if (clock_real_clk[VDEC_HEVC] == 648) + return 648; + use_gpll = 1; + gp_pll_request(gp_pll_user_hevc); + while (!HEVC_WITH_GP_PLL() && gp_pll_wait++ < 1000000) + udelay(1); + if (HEVC_WITH_GP_PLL()) { + clk_seted = 1; + rclk = 648; + } else { + rclk = 667; + /*gp_pull request failed,used default 500Mhz*/ + pr_info("get gp pll failed used fix pull\n"); + } + } + if (!clk_seted) {/*if 648 not set,*/ +// HEVC_SAFE_CLOCK(); + HEVC_CLOCK_OFF(); + vdec_set_clk(VDEC_HEVC, source, div); + HEVC_CLOCK_ON(); + } + if (!use_gpll) + gp_pll_release(gp_pll_user_hevc); + clock_real_clk[VDEC_HEVC] = rclk; + /*debug_print("hevc_clock_set 2 to rclk=%d, configs=%d\n", + rclk, + get_vdec_clk_config_settings());*/ //DEBUG_TMP + return rclk; +} + +static int hcodec_clock_set(int clk) +{ + int source, div, rclk; + HCODEC_CLOCK_OFF(); + vdec_get_clk_source(200, &source, &div, &rclk); + vdec_set_clk(VDEC_HCODEC, source, div); + HCODEC_CLOCK_ON(); + clock_real_clk[VDEC_HCODEC] = rclk; + return rclk; +} + + +#else +static int vdec_clock_set(int clk) +{ + if (clk == 1) + clk = 200; + else if (clk == 2) { + if (clock_real_clk[VDEC_1] != 648) + clk = 500; + else + clk = 648; + } else if (clk == 0) { + if (clock_real_clk[VDEC_1] == 667 || + (clock_real_clk[VDEC_1] == 648) || + clock_real_clk[VDEC_1] <= 0) + clk = 200; + else + clk = clock_real_clk[VDEC_1]; + } + + if ((clk > 500 && clk != 667)) { + if (clock_real_clk[VDEC_1] == 648) + return 648; + clk = 667; + } + + if (set_frq_enable && vdec_frq) { + pr_info("Set the vdec frq is %u MHz\n", vdec_frq); + clk = vdec_frq; + } + + vdec_set_clk(VDEC_1, clk * MHz); + + clock_real_clk[VDEC_1] = clk; + + pr_debug("vdec mux clock is %lu Hz\n", + clk_get_rate(gclk.vdec_mux_node->clk)); + + return clk; +} + +static int hevc_clock_init(void) +{ + return 0; +} + +static int hevc_back_clock_init(void) +{ + return 0; +} + +static int hevc_back_clock_set(int clk) +{ + if (clk == 1) + clk = 200; + else if (clk == 2) { + if (clock_real_clk[VDEC_HEVCB] != 648) + clk = 500; + else + clk = 648; + } else if (clk == 0) { + if (clock_real_clk[VDEC_HEVCB] == 667 || + (clock_real_clk[VDEC_HEVCB] == 648) || + clock_real_clk[VDEC_HEVCB] <= 0) + clk = 200; + else + clk = clock_real_clk[VDEC_HEVCB]; + } + + if ((clk > 500 && clk != 667)) { + if (clock_real_clk[VDEC_HEVCB] == 648) + return 648; + clk = 667; + } + + if (set_frq_enable && hevcb_frq) { + pr_info("Set the hevcb frq is %u MHz\n", hevcb_frq); + clk = hevcb_frq; + } + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXLX) { + if ((READ_EFUSE_REG(EFUSE_LIC1) >> 28 & 0x1) && clk > 333) { + pr_info("The hevcb clock limit to 333MHz.\n"); + clk = 333; + } + } + + vdec_set_clk(VDEC_HEVCB, clk * MHz); + + clock_real_clk[VDEC_HEVCB] = clk; + pr_debug("hevc back mux clock is %lu Hz\n", + clk_get_rate(gclk.hevc_back_mux_node->clk)); + + return clk; +} + +static int hevc_clock_set(int clk) +{ + if (clk == 1) + clk = 200; + else if (clk == 2) { + if (clock_real_clk[VDEC_HEVC] != 648) + clk = 500; + else + clk = 648; + } else if (clk == 0) { + if (clock_real_clk[VDEC_HEVC] == 667 || + (clock_real_clk[VDEC_HEVC] == 648) || + clock_real_clk[VDEC_HEVC] <= 0) + clk = 200; + else + clk = clock_real_clk[VDEC_HEVC]; + } + + if ((clk > 500 && clk != 667)) { + if (clock_real_clk[VDEC_HEVC] == 648) + return 648; + clk = 667; + } + + if (set_frq_enable && hevc_frq) { + pr_info("Set the hevc frq is %u MHz\n", hevc_frq); + clk = hevc_frq; + } + + vdec_set_clk(VDEC_HEVC, clk * MHz); + + clock_real_clk[VDEC_HEVC] = clk; + + pr_debug("hevc mux clock is %lu Hz\n", + clk_get_rate(gclk.hevc_mux_node->clk)); + + return clk; +} + +static int hcodec_clock_set(int clk) +{ + if (clk == 1) + clk = 200; + else if (clk == 2) { + if (clock_real_clk[VDEC_HCODEC] != 648) + clk = 500; + else + clk = 648; + } else if (clk == 0) { + if (clock_real_clk[VDEC_HCODEC] == 667 || + (clock_real_clk[VDEC_HCODEC] == 648) || + clock_real_clk[VDEC_HCODEC] <= 0) + clk = 200; + else + clk = clock_real_clk[VDEC_HCODEC]; + } + + if ((clk > 500 && clk != 667)) { + if (clock_real_clk[VDEC_HCODEC] == 648) + return 648; + clk = 667; + } + + vdec_set_clk(VDEC_HCODEC, clk * MHz); + + clock_real_clk[VDEC_HCODEC] = clk; + + pr_debug("hcodec mux clock is %lu Hz\n", + clk_get_rate(gclk.hcodec_mux_node->clk)); + + return clk; +} +#endif + +static void vdec_clock_on(void) +{ + mutex_lock(&gclk.vdec_mux_node->mutex); + if (!gclk.vdec_mux_node->ref_count) + clk_prepare_enable(gclk.vdec_mux_node->clk); + + gclk.vdec_mux_node->ref_count++; + mutex_unlock(&gclk.vdec_mux_node->mutex); + + pr_debug("the %-15s clock on, ref cnt: %d\n", + gclk.vdec_mux_node->name, + gclk.vdec_mux_node->ref_count); +} + +static void vdec_clock_off(void) +{ + mutex_lock(&gclk.vdec_mux_node->mutex); + gclk.vdec_mux_node->ref_count--; + if (!gclk.vdec_mux_node->ref_count) + clk_disable_unprepare(gclk.vdec_mux_node->clk); + + clock_real_clk[VDEC_1] = 0; + mutex_unlock(&gclk.vdec_mux_node->mutex); + + pr_debug("the %-15s clock off, ref cnt: %d\n", + gclk.vdec_mux_node->name, + gclk.vdec_mux_node->ref_count); +} + +static void hcodec_clock_on(void) +{ + mutex_lock(&gclk.hcodec_mux_node->mutex); + if (!gclk.hcodec_mux_node->ref_count) + clk_prepare_enable(gclk.hcodec_mux_node->clk); + + gclk.hcodec_mux_node->ref_count++; + mutex_unlock(&gclk.hcodec_mux_node->mutex); + + pr_debug("the %-15s clock on, ref cnt: %d\n", + gclk.hcodec_mux_node->name, + gclk.hcodec_mux_node->ref_count); +} + +static void hcodec_clock_off(void) +{ + mutex_lock(&gclk.hcodec_mux_node->mutex); + gclk.hcodec_mux_node->ref_count--; + if (!gclk.hcodec_mux_node->ref_count) + clk_disable_unprepare(gclk.hcodec_mux_node->clk); + + mutex_unlock(&gclk.hcodec_mux_node->mutex); + + pr_debug("the %-15s clock off, ref cnt: %d\n", + gclk.hcodec_mux_node->name, + gclk.hcodec_mux_node->ref_count); +} + +static void hevc_clock_on(void) +{ + mutex_lock(&gclk.hevc_mux_node->mutex); + if (!gclk.hevc_mux_node->ref_count) + clk_prepare_enable(gclk.hevc_mux_node->clk); + + gclk.hevc_mux_node->ref_count++; + WRITE_VREG(DOS_GCLK_EN3, 0xffffffff); + mutex_unlock(&gclk.hevc_mux_node->mutex); + + pr_debug("the %-15s clock on, ref cnt: %d\n", + gclk.hevc_mux_node->name, + gclk.hevc_mux_node->ref_count); +} + +static void hevc_clock_off(void) +{ + mutex_lock(&gclk.hevc_mux_node->mutex); + gclk.hevc_mux_node->ref_count--; + if (!gclk.hevc_mux_node->ref_count) + clk_disable_unprepare(gclk.hevc_mux_node->clk); + + clock_real_clk[VDEC_HEVC] = 0; + mutex_unlock(&gclk.hevc_mux_node->mutex); + + pr_debug("the %-15s clock off, ref cnt: %d\n", + gclk.hevc_mux_node->name, + gclk.hevc_mux_node->ref_count); +} + +static void hevc_back_clock_on(void) +{ + mutex_lock(&gclk.hevc_back_mux_node->mutex); + if (!gclk.hevc_back_mux_node->ref_count) + clk_prepare_enable(gclk.hevc_back_mux_node->clk); + + gclk.hevc_back_mux_node->ref_count++; + WRITE_VREG(DOS_GCLK_EN3, 0xffffffff); + mutex_unlock(&gclk.hevc_back_mux_node->mutex); + + pr_debug("the %-15s clock on, ref cnt: %d\n", + gclk.hevc_back_mux_node->name, + gclk.hevc_back_mux_node->ref_count); +} + +static void hevc_back_clock_off(void) +{ + mutex_lock(&gclk.hevc_back_mux_node->mutex); + gclk.hevc_back_mux_node->ref_count--; + if (!gclk.hevc_back_mux_node->ref_count) + clk_disable_unprepare(gclk.hevc_back_mux_node->clk); + + clock_real_clk[VDEC_HEVC] = 0; + mutex_unlock(&gclk.hevc_back_mux_node->mutex); + + pr_debug("the %-15s clock off, ref cnt: %d\n", + gclk.hevc_back_mux_node->name, + gclk.hevc_back_mux_node->ref_count); +} + +static int vdec_clock_get(enum vdec_type_e core) +{ + if (core >= VDEC_MAX) + return 0; + + return clock_real_clk[core]; +} + +#define INCLUDE_FROM_ARCH_CLK_MGR + +/*#define VDEC_HAS_VDEC2*/ +#define VDEC_HAS_HEVC +#define VDEC_HAS_VDEC_HCODEC +#define VDEC_HAS_CLK_SETTINGS +#define CLK_FOR_CPU {\ + MESON_CPU_MAJOR_ID_GXBB,\ + MESON_CPU_MAJOR_ID_GXTVBB,\ + MESON_CPU_MAJOR_ID_GXL,\ + MESON_CPU_MAJOR_ID_GXM,\ + MESON_CPU_MAJOR_ID_TXL,\ + MESON_CPU_MAJOR_ID_TXLX,\ + MESON_CPU_MAJOR_ID_G12A,\ + MESON_CPU_MAJOR_ID_G12B,\ + 0} +#include "clk.h" + +module_param(set_frq_enable, uint, 0664); +MODULE_PARM_DESC(set_frq_enable, "\n set frequency enable\n"); + +module_param(vdec_frq, uint, 0664); +MODULE_PARM_DESC(vdec_frq, "\n set vdec frequency\n"); + +module_param(hevc_frq, uint, 0664); +MODULE_PARM_DESC(hevc_frq, "\n set hevc frequency\n"); + +module_param(hevcb_frq, uint, 0664); +MODULE_PARM_DESC(hevcb_frq, "\n set hevcb frequency\n"); + +ARCH_VDEC_CLK_INIT(); +ARCH_VDEC_CLK_EXIT(); + +MODULE_LICENSE("GPL"); diff --git a/drivers/amlogic/media_modules/common/media_clock/switch/amports_gate.c b/drivers/amlogic/media_modules/common/media_clock/switch/amports_gate.c new file mode 100644 index 000000000000..c6898217300e --- /dev/null +++ b/drivers/amlogic/media_modules/common/media_clock/switch/amports_gate.c @@ -0,0 +1,206 @@ +/* + * drivers/amlogic/media/common/arch/switch/amports_gate.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#define DEBUG +#include +#include +#include +#include +#include +#include +#include "amports_gate.h" +#include +#include "../../../stream_input/amports/amports_priv.h" +#include "../../../frame_provider/decoder/utils/vdec.h" +#include "../clk/clk.h" + + +#define DEBUG_REF 1 +#define GATE_RESET_OK + +#ifdef GATE_RESET_OK + +struct gate_switch_node gates[] = { + { + .name = "demux", + }, + { + .name = "parser_top", + }, + { + .name = "vdec", + }, + { + .name = "clk_81", + }, + { + .name = "clk_vdec_mux", + }, + { + .name = "clk_hcodec_mux", + }, + { + .name = "clk_hevc_mux", + }, + { + .name = "clk_hevcb_mux", + }, + { + .name = "ahbarb0", + }, + { + .name = "asyncfifo", + }, +}; + +/* + *mesonstream { + * compatible = "amlogic, codec, streambuf"; + * dev_name = "mesonstream"; + * status = "okay"; + * clocks = <&clkc CLKID_DOS_PARSER + * &clkc CLKID_DEMUX + * &clkc CLKID_DOS + * &clkc CLKID_VDEC_MUX + * &clkc CLKID_HCODEC_MUX + * &clkc CLKID_HEVCF_MUX + * &clkc CLKID_HEVC_MUX>; + * clock-names = "parser_top", + * "demux", + * "vdec", + * "clk_vdec_mux", + * "clk_hcodec_mux", + * "clk_hevc_mux", + * "clk_hevcb_mux"; + *}; + */ + +int amports_clock_gate_init(struct device *dev) +{ + int i; + + for (i = 0; i < sizeof(gates) / sizeof(struct gate_switch_node); i++) { + gates[i].clk = devm_clk_get(dev, gates[i].name); + if (IS_ERR_OR_NULL(gates[i].clk)) { + gates[i].clk = NULL; + pr_info("get gate %s control failed %p\n", + gates[i].name, + gates[i].clk); + } else { + pr_info("get gate %s control ok %p\n", + gates[i].name, + gates[i].clk); + } + gates[i].ref_count = 0; + mutex_init(&gates[i].mutex); + } + + set_clock_gate(gates, ARRAY_SIZE(gates)); + + return 0; +} +EXPORT_SYMBOL(amports_clock_gate_init); + +static int amports_gate_clk(struct gate_switch_node *gate_node, int enable) +{ + mutex_lock(&gate_node->mutex); + if (enable) { + if (gate_node->ref_count == 0) + clk_prepare_enable(gate_node->clk); + + gate_node->ref_count++; + + if (DEBUG_REF) + pr_debug("the %-15s clock on, ref cnt: %d\n", + gate_node->name, gate_node->ref_count); + } else { + gate_node->ref_count--; + if (gate_node->ref_count == 0) + clk_disable_unprepare(gate_node->clk); + + if (DEBUG_REF) + pr_debug("the %-15s clock off, ref cnt: %d\n", + gate_node->name, gate_node->ref_count); + } + mutex_unlock(&gate_node->mutex); + + return 0; +} + +int amports_switch_gate(const char *name, int enable) +{ + int i; + + for (i = 0; i < sizeof(gates) / sizeof(struct gate_switch_node); i++) { + if (!strcmp(name, gates[i].name)) { + + /*pr_info("openclose:%d gate %s control\n", enable, + * gates[i].name); + */ + + if (gates[i].clk) + amports_gate_clk(&gates[i], enable); + } + } + return 0; +} +EXPORT_SYMBOL(amports_switch_gate); + +#else +/* + *can used for debug. + *on chip bringup. + */ +int amports_clock_gate_init(struct device *dev) +{ + static int gate_inited; + + if (gate_inited) + return 0; +/* + *#define HHI_GCLK_MPEG0 0x1050 + *#define HHI_GCLK_MPEG1 0x1051 + *#define HHI_GCLK_MPEG2 0x1052 + *#define HHI_GCLK_OTHER 0x1054 + *#define HHI_GCLK_AO 0x1055 + */ + WRITE_HHI_REG_BITS(HHI_GCLK_MPEG0, 1, 1, 1);/*dos*/ + WRITE_HHI_REG_BITS(HHI_GCLK_MPEG1, 1, 25, 1);/*U_parser_top()*/ + WRITE_HHI_REG_BITS(HHI_GCLK_MPEG1, 0xff, 6, 8);/*aiu()*/ + WRITE_HHI_REG_BITS(HHI_GCLK_MPEG1, 1, 4, 1);/*demux()*/ + WRITE_HHI_REG_BITS(HHI_GCLK_MPEG1, 1, 2, 1);/*audio in()*/ + WRITE_HHI_REG_BITS(HHI_GCLK_MPEG2, 1, 25, 1);/*VPU Interrupt*/ + gate_inited++; + + + + return 0; +} +EXPORT_SYMBOL(amports_clock_gate_init); + +static int amports_switch_gate(struct gate_switch_node *gate_node, int enable) +{ + return 0; +} + +int amports_switch_gate(const char *name, int enable) +{ + amports_switch_gate(0, 0); + return 0; +} +EXPORT_SYMBOL(amports_switch_gate); + +#endif diff --git a/drivers/amlogic/media_modules/common/media_clock/switch/amports_gate.h b/drivers/amlogic/media_modules/common/media_clock/switch/amports_gate.h new file mode 100644 index 000000000000..58abc9274d9d --- /dev/null +++ b/drivers/amlogic/media_modules/common/media_clock/switch/amports_gate.h @@ -0,0 +1,32 @@ +/* + * drivers/amlogic/media/common/arch/switch/amports_gate.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef AMPORT_GATE_H +#define AMPORT_GATE_H +#include + +struct gate_switch_node { + struct clk *clk; + const char *name; + struct mutex mutex; + int ref_count; +}; + +extern int amports_clock_gate_init(struct device *dev); +extern int amports_switch_gate(const char *name, int enable); + +#endif diff --git a/drivers/amlogic/media_modules/frame_provider/Makefile b/drivers/amlogic/media_modules/frame_provider/Makefile new file mode 100644 index 000000000000..371e088259c5 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/Makefile @@ -0,0 +1 @@ +obj-y += decoder/ diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/Makefile b/drivers/amlogic/media_modules/frame_provider/decoder/Makefile new file mode 100644 index 000000000000..12121b43f36d --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/Makefile @@ -0,0 +1,12 @@ +obj-y += utils/ +obj-y += mpeg12/ +obj-y += mpeg4/ +obj-y += vc1/ +obj-y += h264/ +obj-y += h264_multi/ +obj-y += h265/ +obj-y += vp9/ +obj-y += mjpeg/ +obj-y += real/ +obj-y += avs/ +obj-y += avs2/ diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/avs/Makefile b/drivers/amlogic/media_modules/frame_provider/decoder/avs/Makefile new file mode 100644 index 000000000000..1d56236f9ef2 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/avs/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_AMLOGIC_MEDIA_VDEC_AVS) += amvdec_avs.o +amvdec_avs-objs += avs.o avsp_trans.o diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/avs/avs.c b/drivers/amlogic/media_modules/frame_provider/decoder/avs/avs.c new file mode 100644 index 000000000000..bb2ea4a504e7 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/avs/avs.c @@ -0,0 +1,1887 @@ +/* + * drivers/amlogic/amports/vavs.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../../stream_input/parser/streambuf_reg.h" +#include "../utils/amvdec.h" +#include +#include "../../../stream_input/amports/amports_priv.h" +#include +#include +#include +#include "avs.h" +#include +#include "../utils/decoder_mmu_box.h" +#include "../utils/decoder_bmmu_box.h" +#include "../utils/firmware.h" + +#define DRIVER_NAME "amvdec_avs" +#define MODULE_NAME "amvdec_avs" + +#define ENABLE_USER_DATA + +#if 1/* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ +#define NV21 +#endif + +#define USE_AVS_SEQ_INFO +#define HANDLE_AVS_IRQ +#define DEBUG_PTS + +#define I_PICTURE 0 +#define P_PICTURE 1 +#define B_PICTURE 2 + +/* #define ORI_BUFFER_START_ADDR 0x81000000 */ +#define ORI_BUFFER_START_ADDR 0x80000000 + +#define INTERLACE_FLAG 0x80 +#define TOP_FIELD_FIRST_FLAG 0x40 + +/* protocol registers */ +#define AVS_PIC_RATIO AV_SCRATCH_0 +#define AVS_PIC_WIDTH AV_SCRATCH_1 +#define AVS_PIC_HEIGHT AV_SCRATCH_2 +#define AVS_FRAME_RATE AV_SCRATCH_3 + +#define AVS_ERROR_COUNT AV_SCRATCH_6 +#define AVS_SOS_COUNT AV_SCRATCH_7 +#define AVS_BUFFERIN AV_SCRATCH_8 +#define AVS_BUFFEROUT AV_SCRATCH_9 +#define AVS_REPEAT_COUNT AV_SCRATCH_A +#define AVS_TIME_STAMP AV_SCRATCH_B +#define AVS_OFFSET_REG AV_SCRATCH_C +#define MEM_OFFSET_REG AV_SCRATCH_F +#define AVS_ERROR_RECOVERY_MODE AV_SCRATCH_G + +#define VF_POOL_SIZE 32 +#define PUT_INTERVAL (HZ/100) + +#if 1 /*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8*/ +#define INT_AMVENCODER INT_DOS_MAILBOX_1 +#else +/* #define AMVENC_DEV_VERSION "AML-MT" */ +#define INT_AMVENCODER INT_MAILBOX_1A +#endif + +#define VPP_VD1_POSTBLEND (1 << 10) + +static int debug_flag; + +/******************************** +firmware_sel + 0: use avsp_trans long cabac ucode; + 1: not use avsp_trans long cabac ucode +********************************/ +static int firmware_sel; +static int disable_longcabac_trans = 1; + + +int avs_get_debug_flag(void) +{ + return debug_flag; +} + +static struct vframe_s *vavs_vf_peek(void *); +static struct vframe_s *vavs_vf_get(void *); +static void vavs_vf_put(struct vframe_s *, void *); +static int vavs_vf_states(struct vframe_states *states, void *); + +static const char vavs_dec_id[] = "vavs-dev"; + +#define PROVIDER_NAME "decoder.avs" +static DEFINE_SPINLOCK(lock); +static DEFINE_MUTEX(vavs_mutex); + +static const struct vframe_operations_s vavs_vf_provider = { + .peek = vavs_vf_peek, + .get = vavs_vf_get, + .put = vavs_vf_put, + .vf_states = vavs_vf_states, +}; +static void *mm_blk_handle; +static struct vframe_provider_s vavs_vf_prov; + +#define VF_BUF_NUM_MAX 16 +#define WORKSPACE_SIZE (4 * SZ_1M) + +#ifdef AVSP_LONG_CABAC +#define MAX_BMMU_BUFFER_NUM (VF_BUF_NUM_MAX + 2) +#define WORKSPACE_SIZE_A (MAX_CODED_FRAME_SIZE + LOCAL_HEAP_SIZE) +#else +#define MAX_BMMU_BUFFER_NUM (VF_BUF_NUM_MAX + 1) +#endif + +#define RV_AI_BUFF_START_ADDR 0x01a00000 +#define LONG_CABAC_RV_AI_BUFF_START_ADDR 0x00000000 + +static u32 vf_buf_num = 4; +static u32 vf_buf_num_used; +static u32 canvas_base = 128; +#ifdef NV21 + int canvas_num = 2; /*NV21*/ +#else + int canvas_num = 3; +#endif + + +static struct vframe_s vfpool[VF_POOL_SIZE]; +/*static struct vframe_s vfpool2[VF_POOL_SIZE];*/ +static struct vframe_s *cur_vfpool; +static unsigned char recover_flag; +static s32 vfbuf_use[VF_BUF_NUM_MAX]; +static u32 saved_resolution; +static u32 frame_width, frame_height, frame_dur, frame_prog; +static struct timer_list recycle_timer; +static u32 stat; +static u32 buf_size = 32 * 1024 * 1024; +static u32 buf_offset; +static u32 avi_flag; +static u32 vavs_ratio; +static u32 pic_type; +static u32 pts_by_offset = 1; +static u32 total_frame; +static u32 next_pts; +static unsigned char throw_pb_flag; +#ifdef DEBUG_PTS +static u32 pts_hit, pts_missed, pts_i_hit, pts_i_missed; +#endif + +static u32 radr, rval; +static struct dec_sysinfo vavs_amstream_dec_info; +static struct vdec_info *gvs; +static u32 fr_hint_status; +static struct work_struct notify_work; +static struct work_struct set_clk_work; +static bool is_reset; + +static struct vdec_s *vdec; + +#ifdef AVSP_LONG_CABAC +static struct work_struct long_cabac_wd_work; +void *es_write_addr_virt; +dma_addr_t es_write_addr_phy; + +void *bitstream_read_tmp; +dma_addr_t bitstream_read_tmp_phy; +void *avsp_heap_adr; +static uint long_cabac_busy; +#endif + +#ifdef ENABLE_USER_DATA +static void *user_data_buffer; +static dma_addr_t user_data_buffer_phys; +#endif +static DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE); +static DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE); +static DECLARE_KFIFO(recycle_q, struct vframe_s *, VF_POOL_SIZE); + +static inline u32 index2canvas(u32 index) +{ + const u32 canvas_tab[VF_BUF_NUM_MAX] = { + 0x010100, 0x030302, 0x050504, 0x070706, + 0x090908, 0x0b0b0a, 0x0d0d0c, 0x0f0f0e, + 0x111110, 0x131312, 0x151514, 0x171716, + 0x191918, 0x1b1b1a, 0x1d1d1c, 0x1f1f1e, + }; + const u32 canvas_tab_3[4] = { + 0x010100, 0x040403, 0x070706, 0x0a0a09 + }; + + if (canvas_num == 2) + return canvas_tab[index] + (canvas_base << 16) + + (canvas_base << 8) + canvas_base; + + return canvas_tab_3[index] + (canvas_base << 16) + + (canvas_base << 8) + canvas_base; +} + +static const u32 frame_rate_tab[16] = { + 96000 / 30, /* forbidden */ + 96000000 / 23976, /* 24000/1001 (23.967) */ + 96000 / 24, + 96000 / 25, + 9600000 / 2997, /* 30000/1001 (29.97) */ + 96000 / 30, + 96000 / 50, + 9600000 / 5994, /* 60000/1001 (59.94) */ + 96000 / 60, + /* > 8 reserved, use 24 */ + 96000 / 24, 96000 / 24, 96000 / 24, 96000 / 24, + 96000 / 24, 96000 / 24, 96000 / 24 +}; + +static void set_frame_info(struct vframe_s *vf, unsigned int *duration) +{ + int ar = 0; + + unsigned int pixel_ratio = READ_VREG(AVS_PIC_RATIO); +#ifndef USE_AVS_SEQ_INFO + if (vavs_amstream_dec_info.width > 0 + && vavs_amstream_dec_info.height > 0) { + vf->width = vavs_amstream_dec_info.width; + vf->height = vavs_amstream_dec_info.height; + } else +#endif + { + vf->width = READ_VREG(AVS_PIC_WIDTH); + vf->height = READ_VREG(AVS_PIC_HEIGHT); + frame_width = vf->width; + frame_height = vf->height; + /* pr_info("%s: (%d,%d)\n", __func__,vf->width, vf->height);*/ + } + +#ifndef USE_AVS_SEQ_INFO + if (vavs_amstream_dec_info.rate > 0) + *duration = vavs_amstream_dec_info.rate; + else +#endif + { + *duration = frame_rate_tab[READ_VREG(AVS_FRAME_RATE) & 0xf]; + /* pr_info("%s: duration = %d\n", __func__, *duration); */ + frame_dur = *duration; + schedule_work(¬ify_work); + } + + if (vavs_ratio == 0) { + /* always stretch to 16:9 */ + vf->ratio_control |= (0x90 << + DISP_RATIO_ASPECT_RATIO_BIT); + } else { + switch (pixel_ratio) { + case 1: + ar = (vf->height * vavs_ratio) / vf->width; + break; + case 2: + ar = (vf->height * 3 * vavs_ratio) / (vf->width * 4); + break; + case 3: + ar = (vf->height * 9 * vavs_ratio) / (vf->width * 16); + break; + case 4: + ar = (vf->height * 100 * vavs_ratio) / (vf->width * + 221); + break; + default: + ar = (vf->height * vavs_ratio) / vf->width; + break; + } + } + + ar = min(ar, DISP_RATIO_ASPECT_RATIO_MAX); + + vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT); + /*vf->ratio_control |= DISP_RATIO_FORCECONFIG | DISP_RATIO_KEEPRATIO; */ + + vf->flag = 0; +} + +#ifdef ENABLE_USER_DATA + +static struct work_struct userdata_push_work; +/* +#define DUMP_LAST_REPORTED_USER_DATA +*/ +static void userdata_push_do_work(struct work_struct *work) +{ + unsigned int user_data_flags; + unsigned int user_data_wp; + unsigned int user_data_length; + struct userdata_poc_info_t user_data_poc; +#ifdef DUMP_LAST_REPORTED_USER_DATA + int user_data_len; + int wp_start; + unsigned char *pdata; + int nLeft; +#endif + + user_data_flags = READ_VREG(AV_SCRATCH_N); + user_data_wp = (user_data_flags >> 16) & 0xffff; + user_data_length = user_data_flags & 0x7fff; + +#ifdef DUMP_LAST_REPORTED_USER_DATA + dma_sync_single_for_cpu(amports_get_dma_device(), + user_data_buffer_phys, USER_DATA_SIZE, + DMA_FROM_DEVICE); + + if (user_data_length & 0x07) + user_data_len = (user_data_length + 8) & 0xFFFFFFF8; + else + user_data_len = user_data_length; + + if (user_data_wp >= user_data_len) { + wp_start = user_data_wp - user_data_len; + + pdata = (unsigned char *)user_data_buffer; + pdata += wp_start; + nLeft = user_data_len; + while (nLeft >= 8) { + pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n", + pdata[0], pdata[1], pdata[2], pdata[3], + pdata[4], pdata[5], pdata[6], pdata[7]); + nLeft -= 8; + pdata += 8; + } + } else { + wp_start = user_data_wp + + USER_DATA_SIZE - user_data_len; + + pdata = (unsigned char *)user_data_buffer; + pdata += wp_start; + nLeft = USER_DATA_SIZE - wp_start; + + while (nLeft >= 8) { + pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n", + pdata[0], pdata[1], pdata[2], pdata[3], + pdata[4], pdata[5], pdata[6], pdata[7]); + nLeft -= 8; + pdata += 8; + } + + pdata = (unsigned char *)user_data_buffer; + nLeft = user_data_wp; + while (nLeft >= 8) { + pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n", + pdata[0], pdata[1], pdata[2], pdata[3], + pdata[4], pdata[5], pdata[6], pdata[7]); + nLeft -= 8; + pdata += 8; + } + } +#endif + +/* + pr_info("pocinfo 0x%x, poc %d, wp 0x%x, len %d\n", + READ_VREG(AV_SCRATCH_L), READ_VREG(AV_SCRATCH_M), + user_data_wp, user_data_length); +*/ + user_data_poc.poc_info = READ_VREG(AV_SCRATCH_L); + user_data_poc.poc_number = READ_VREG(AV_SCRATCH_M); + + WRITE_VREG(AV_SCRATCH_N, 0); +/* + wakeup_userdata_poll(user_data_poc, user_data_wp, + (unsigned long)user_data_buffer, + USER_DATA_SIZE, user_data_length); +*/ +} + +static void UserDataHandler(void) +{ + unsigned int user_data_flags; + + user_data_flags = READ_VREG(AV_SCRATCH_N); + if (user_data_flags & (1 << 15)) { /* data ready */ + schedule_work(&userdata_push_work); + } +} +#endif + +#ifdef HANDLE_AVS_IRQ +static irqreturn_t vavs_isr(int irq, void *dev_id) +#else +static void vavs_isr(void) +#endif +{ + u32 reg; + struct vframe_s *vf; + u32 dur; + u32 repeat_count; + u32 picture_type; + u32 buffer_index; + + unsigned int pts, pts_valid = 0, offset; + u64 pts_us64; + if (debug_flag & AVS_DEBUG_UCODE) { + if (READ_VREG(AV_SCRATCH_E) != 0) { + pr_info("dbg%x: %x\n", READ_VREG(AV_SCRATCH_E), + READ_VREG(AV_SCRATCH_D)); + WRITE_VREG(AV_SCRATCH_E, 0); + } + } +#ifdef AVSP_LONG_CABAC + if (firmware_sel == 0 && READ_VREG(LONG_CABAC_REQ)) { +#ifdef PERFORMANCE_DEBUG + pr_info("%s:schedule long_cabac_wd_work\r\n", __func__); +#endif + pr_info("schedule long_cabac_wd_work and requested from %d\n", + (READ_VREG(LONG_CABAC_REQ) >> 8)&0xFF); + schedule_work(&long_cabac_wd_work); + } +#endif + +#ifdef ENABLE_USER_DATA + UserDataHandler(); +#endif + reg = READ_VREG(AVS_BUFFEROUT); + + if (reg) { + if (debug_flag & AVS_DEBUG_PRINT) + pr_info("AVS_BUFFEROUT=%x\n", reg); + if (pts_by_offset) { + offset = READ_VREG(AVS_OFFSET_REG); + if (debug_flag & AVS_DEBUG_PRINT) + pr_info("AVS OFFSET=%x\n", offset); + if (pts_lookup_offset_us64(PTS_TYPE_VIDEO, offset, &pts, + 0, &pts_us64) == 0) { + pts_valid = 1; +#ifdef DEBUG_PTS + pts_hit++; +#endif + } else { +#ifdef DEBUG_PTS + pts_missed++; +#endif + } + } + + repeat_count = READ_VREG(AVS_REPEAT_COUNT); + if (firmware_sel == 0) + buffer_index = + ((reg & 0x7) + + (((reg >> 8) & 0x3) << 3) - 1) & 0x1f; + else + buffer_index = + ((reg & 0x7) - 1) & 3; + + picture_type = (reg >> 3) & 7; +#ifdef DEBUG_PTS + if (picture_type == I_PICTURE) { + /* pr_info("I offset 0x%x, pts_valid %d\n", + * offset, pts_valid); + */ + if (!pts_valid) + pts_i_missed++; + else + pts_i_hit++; + } +#endif + + if (throw_pb_flag && picture_type != I_PICTURE) { + + if (debug_flag & AVS_DEBUG_PRINT) { + pr_info("picture type %d throwed\n", + picture_type); + } + WRITE_VREG(AVS_BUFFERIN, ~(1 << buffer_index)); + } else if (reg & INTERLACE_FLAG) { /* interlace */ + throw_pb_flag = 0; + + if (debug_flag & AVS_DEBUG_PRINT) { + pr_info("interlace, picture type %d\n", + picture_type); + } + + if (kfifo_get(&newframe_q, &vf) == 0) { + pr_info + ("fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + set_frame_info(vf, &dur); + vf->bufWidth = 1920; + pic_type = 2; + if ((picture_type == I_PICTURE) && pts_valid) { + vf->pts = pts; + if ((repeat_count > 1) && avi_flag) { + /* next_pts = pts + + * (vavs_amstream_dec_info.rate * + * repeat_count >> 1)*15/16; + */ + next_pts = + pts + + (dur * repeat_count >> 1) * + 15 / 16; + } else + next_pts = 0; + } else { + vf->pts = next_pts; + if ((repeat_count > 1) && avi_flag) { + /* vf->duration = + * vavs_amstream_dec_info.rate * + * repeat_count >> 1; + */ + vf->duration = dur * repeat_count >> 1; + if (next_pts != 0) { + next_pts += + ((vf->duration) - + ((vf->duration) >> 4)); + } + } else { + /* vf->duration = + * vavs_amstream_dec_info.rate >> 1; + */ + vf->duration = dur >> 1; + next_pts = 0; + } + } + vf->signal_type = 0; + vf->index = buffer_index; + vf->duration_pulldown = 0; + vf->type = + (reg & TOP_FIELD_FIRST_FLAG) + ? VIDTYPE_INTERLACE_TOP + : VIDTYPE_INTERLACE_BOTTOM; +#ifdef NV21 + vf->type |= VIDTYPE_VIU_NV21; +#endif + vf->canvas0Addr = vf->canvas1Addr = + index2canvas(buffer_index); + vf->type_original = vf->type; + + if (debug_flag & AVS_DEBUG_PRINT) { + pr_info("buffer_index %d, canvas addr %x\n", + buffer_index, vf->canvas0Addr); + } + vf->pts_us64 = (pts_valid) ? pts_us64 : 0; + vfbuf_use[buffer_index]++; + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + buffer_index); + + kfifo_put(&display_q, + (const struct vframe_s *)vf); + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + + if (kfifo_get(&newframe_q, &vf) == 0) { + pr_info("fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + set_frame_info(vf, &dur); + vf->bufWidth = 1920; + + vf->pts = next_pts; + if ((repeat_count > 1) && avi_flag) { + /* vf->duration = vavs_amstream_dec_info.rate * + * repeat_count >> 1; + */ + vf->duration = dur * repeat_count >> 1; + if (next_pts != 0) { + next_pts += + ((vf->duration) - + ((vf->duration) >> 4)); + } + } else { + /* vf->duration = vavs_amstream_dec_info.rate + * >> 1; + */ + vf->duration = dur >> 1; + next_pts = 0; + } + vf->signal_type = 0; + vf->index = buffer_index; + vf->duration_pulldown = 0; + vf->type = + (reg & TOP_FIELD_FIRST_FLAG) ? + VIDTYPE_INTERLACE_BOTTOM : + VIDTYPE_INTERLACE_TOP; +#ifdef NV21 + vf->type |= VIDTYPE_VIU_NV21; +#endif + vf->canvas0Addr = vf->canvas1Addr = + index2canvas(buffer_index); + vf->type_original = vf->type; + vf->pts_us64 = 0; + vfbuf_use[buffer_index]++; + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + buffer_index); + + kfifo_put(&display_q, + (const struct vframe_s *)vf); + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + total_frame++; + } else { /* progressive */ + throw_pb_flag = 0; + + if (debug_flag & AVS_DEBUG_PRINT) { + pr_info("progressive picture type %d\n", + picture_type); + } + if (kfifo_get(&newframe_q, &vf) == 0) { + pr_info + ("fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + set_frame_info(vf, &dur); + vf->bufWidth = 1920; + pic_type = 1; + + if ((picture_type == I_PICTURE) && pts_valid) { + vf->pts = pts; + if ((repeat_count > 1) && avi_flag) { + /* next_pts = pts + + * (vavs_amstream_dec_info.rate * + * repeat_count)*15/16; + */ + next_pts = + pts + + (dur * repeat_count) * 15 / 16; + } else + next_pts = 0; + } else { + vf->pts = next_pts; + if ((repeat_count > 1) && avi_flag) { + /* vf->duration = + * vavs_amstream_dec_info.rate * + * repeat_count; + */ + vf->duration = dur * repeat_count; + if (next_pts != 0) { + next_pts += + ((vf->duration) - + ((vf->duration) >> 4)); + } + } else { + /* vf->duration = + * vavs_amstream_dec_info.rate; + */ + vf->duration = dur; + next_pts = 0; + } + } + vf->signal_type = 0; + vf->index = buffer_index; + vf->duration_pulldown = 0; + vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD; +#ifdef NV21 + vf->type |= VIDTYPE_VIU_NV21; +#endif + vf->canvas0Addr = vf->canvas1Addr = + index2canvas(buffer_index); + vf->type_original = vf->type; + + vf->pts_us64 = (pts_valid) ? pts_us64 : 0; + if (debug_flag & AVS_DEBUG_PRINT) { + pr_info("buffer_index %d, canvas addr %x\n", + buffer_index, vf->canvas0Addr); + } + + vfbuf_use[buffer_index]++; + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + buffer_index); + kfifo_put(&display_q, + (const struct vframe_s *)vf); + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + total_frame++; + } + + /*count info*/ + gvs->frame_dur = frame_dur; + vdec_count_info(gvs, 0, offset); + + /* pr_info("PicType = %d, PTS = 0x%x\n", + * picture_type, vf->pts); + */ + WRITE_VREG(AVS_BUFFEROUT, 0); + } + + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + +#ifdef HANDLE_AVS_IRQ + return IRQ_HANDLED; +#else + return; +#endif +} +/* + *static int run_flag = 1; + *static int step_flag; + */ +static int error_recovery_mode; /*0: blocky 1: mosaic*/ +/* + *static uint error_watchdog_threshold=10; + *static uint error_watchdog_count; + *static uint error_watchdog_buf_threshold = 0x4000000; + */ + +static struct vframe_s *vavs_vf_peek(void *op_arg) +{ + struct vframe_s *vf; + + if (recover_flag) + return NULL; + + if (kfifo_peek(&display_q, &vf)) + return vf; + + return NULL; + +} + +static struct vframe_s *vavs_vf_get(void *op_arg) +{ + struct vframe_s *vf; + + if (recover_flag) + return NULL; + + if (kfifo_get(&display_q, &vf)) + return vf; + + return NULL; + +} + +static void vavs_vf_put(struct vframe_s *vf, void *op_arg) +{ + int i; + + if (recover_flag) + return; + + for (i = 0; i < VF_POOL_SIZE; i++) { + if (vf == &cur_vfpool[i]) + break; + } + if (i < VF_POOL_SIZE) + kfifo_put(&recycle_q, (const struct vframe_s *)vf); + +} + +int vavs_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus) +{ + vstatus->frame_width = frame_width; + vstatus->frame_height = frame_height; + if (frame_dur != 0) + vstatus->frame_rate = 96000 / frame_dur; + else + vstatus->frame_rate = -1; + vstatus->error_count = READ_VREG(AV_SCRATCH_C); + vstatus->status = stat; + vstatus->bit_rate = gvs->bit_rate; + vstatus->frame_dur = frame_dur; + vstatus->frame_data = gvs->frame_data; + vstatus->total_data = gvs->total_data; + vstatus->frame_count = gvs->frame_count; + vstatus->error_frame_count = gvs->error_frame_count; + vstatus->drop_frame_count = gvs->drop_frame_count; + vstatus->total_data = gvs->total_data; + vstatus->samp_cnt = gvs->samp_cnt; + vstatus->offset = gvs->offset; + snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name), + "%s", DRIVER_NAME); + + return 0; +} + +int vavs_set_isreset(struct vdec_s *vdec, int isreset) +{ + is_reset = isreset; + return 0; +} + +static int vavs_vdec_info_init(void) +{ + gvs = kzalloc(sizeof(struct vdec_info), GFP_KERNEL); + if (NULL == gvs) { + pr_info("the struct of vdec status malloc failed.\n"); + return -ENOMEM; + } + return 0; +} +/****************************************/ +static int vavs_canvas_init(void) +{ + int i, ret; + u32 canvas_width, canvas_height; + u32 decbuf_size, decbuf_y_size, decbuf_uv_size; + unsigned long buf_start; + int need_alloc_buf_num; + + vf_buf_num_used = vf_buf_num; + if (buf_size <= 0x00400000) { + /* SD only */ + canvas_width = 768; + canvas_height = 576; + decbuf_y_size = 0x80000; + decbuf_uv_size = 0x20000; + decbuf_size = 0x100000; + } else { + /* HD & SD */ + canvas_width = 1920; + canvas_height = 1088; + decbuf_y_size = 0x200000; + decbuf_uv_size = 0x80000; + decbuf_size = 0x300000; + } + +#ifdef AVSP_LONG_CABAC + need_alloc_buf_num = vf_buf_num_used + 2; +#else + need_alloc_buf_num = vf_buf_num_used + 1; +#endif + for (i = 0; i < need_alloc_buf_num; i++) { + + if (i == (need_alloc_buf_num - 1)) + decbuf_size = WORKSPACE_SIZE; +#ifdef AVSP_LONG_CABAC + else if (i == (need_alloc_buf_num - 2)) + decbuf_size = WORKSPACE_SIZE_A; +#endif + ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, i, + decbuf_size, DRIVER_NAME, &buf_start); + if (ret < 0) + return ret; + if (i == (need_alloc_buf_num - 1)) { + if (firmware_sel == 1) + buf_offset = buf_start - + RV_AI_BUFF_START_ADDR; + else + buf_offset = buf_start - + LONG_CABAC_RV_AI_BUFF_START_ADDR; + continue; + } +#ifdef AVSP_LONG_CABAC + else if (i == (need_alloc_buf_num - 2)) { + avsp_heap_adr = codec_mm_phys_to_virt(buf_start); + continue; + } +#endif + +#ifdef NV21 + canvas_config(canvas_base + canvas_num * i + 0, + buf_start, + canvas_width, canvas_height, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_32X32); + canvas_config(canvas_base + canvas_num * i + 1, + buf_start + + decbuf_y_size, canvas_width, + canvas_height / 2, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_32X32); +#else + canvas_config(canvas_num * i + 0, + buf_start, + canvas_width, canvas_height, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_32X32); + canvas_config(canvas_num * i + 1, + buf_start + + decbuf_y_size, canvas_width / 2, + canvas_height / 2, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_32X32); + canvas_config(canvas_num * i + 2, + buf_start + + decbuf_y_size + decbuf_uv_size, + canvas_width / 2, canvas_height / 2, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_32X32); +#endif + if (debug_flag & AVS_DEBUG_PRINT) { + pr_info("canvas config %d, addr %p\n", i, + (void *)buf_start); + } + + } + return 0; +} + +void vavs_recover(void) +{ + vavs_canvas_init(); + + WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4)); + WRITE_VREG(DOS_SW_RESET0, 0); + + READ_VREG(DOS_SW_RESET0); + + WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4)); + WRITE_VREG(DOS_SW_RESET0, 0); + + WRITE_VREG(DOS_SW_RESET0, (1 << 9) | (1 << 8)); + WRITE_VREG(DOS_SW_RESET0, 0); + + if (firmware_sel == 1) { + WRITE_VREG(POWER_CTL_VLD, 0x10); + WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL, 2, + MEM_FIFO_CNT_BIT, 2); + WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL, 8, + MEM_LEVEL_CNT_BIT, 6); + } + + + if (firmware_sel == 0) { + /* fixed canvas index */ + WRITE_VREG(AV_SCRATCH_0, canvas_base); + WRITE_VREG(AV_SCRATCH_1, vf_buf_num_used); + } else { + int ii; + + for (ii = 0; ii < 4; ii++) { + WRITE_VREG(AV_SCRATCH_0 + ii, + (canvas_base + canvas_num * ii) | + ((canvas_base + canvas_num * ii + 1) + << 8) | + ((canvas_base + canvas_num * ii + 1) + << 16) + ); + } + } + + /* notify ucode the buffer offset */ + WRITE_VREG(AV_SCRATCH_F, buf_offset); + + /* disable PSCALE for hardware sharing */ + WRITE_VREG(PSCALE_CTRL, 0); + + WRITE_VREG(AVS_SOS_COUNT, 0); + WRITE_VREG(AVS_BUFFERIN, 0); + WRITE_VREG(AVS_BUFFEROUT, 0); + if (error_recovery_mode) + WRITE_VREG(AVS_ERROR_RECOVERY_MODE, 0); + else + WRITE_VREG(AVS_ERROR_RECOVERY_MODE, 1); + /* clear mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + /* enable mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_MASK, 1); +#if 1 /* def DEBUG_UCODE */ + WRITE_VREG(AV_SCRATCH_D, 0); +#endif + +#ifdef NV21 + SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17); +#endif + +#ifdef PIC_DC_NEED_CLEAR + CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31); +#endif + +#ifdef AVSP_LONG_CABAC + if (firmware_sel == 0) { + WRITE_VREG(LONG_CABAC_DES_ADDR, es_write_addr_phy); + WRITE_VREG(LONG_CABAC_REQ, 0); + WRITE_VREG(LONG_CABAC_PIC_SIZE, 0); + WRITE_VREG(LONG_CABAC_SRC_ADDR, 0); + } +#endif + WRITE_VREG(AV_SCRATCH_5, 0); + +} + +static int vavs_prot_init(void) +{ + int r; +#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ + WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4)); + WRITE_VREG(DOS_SW_RESET0, 0); + + READ_VREG(DOS_SW_RESET0); + + WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4)); + WRITE_VREG(DOS_SW_RESET0, 0); + + WRITE_VREG(DOS_SW_RESET0, (1 << 9) | (1 << 8)); + WRITE_VREG(DOS_SW_RESET0, 0); + +#else + WRITE_RESET_REG(RESET0_REGISTER, + RESET_IQIDCT | RESET_MC | RESET_VLD_PART); + READ_RESET_REG(RESET0_REGISTER); + WRITE_RESET_REG(RESET0_REGISTER, + RESET_IQIDCT | RESET_MC | RESET_VLD_PART); + + WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK); +#endif + + /***************** reset vld **********************************/ + WRITE_VREG(POWER_CTL_VLD, 0x10); + WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL, 2, MEM_FIFO_CNT_BIT, 2); + WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL, 8, MEM_LEVEL_CNT_BIT, 6); + /*************************************************************/ + + r = vavs_canvas_init(); +#ifdef NV21 + if (firmware_sel == 0) { + /* fixed canvas index */ + WRITE_VREG(AV_SCRATCH_0, canvas_base); + WRITE_VREG(AV_SCRATCH_1, vf_buf_num_used); + } else { + int ii; + + for (ii = 0; ii < 4; ii++) { + WRITE_VREG(AV_SCRATCH_0 + ii, + (canvas_base + canvas_num * ii) | + ((canvas_base + canvas_num * ii + 1) + << 8) | + ((canvas_base + canvas_num * ii + 1) + << 16) + ); + } + /* + *WRITE_VREG(AV_SCRATCH_0, 0x010100); + *WRITE_VREG(AV_SCRATCH_1, 0x040403); + *WRITE_VREG(AV_SCRATCH_2, 0x070706); + *WRITE_VREG(AV_SCRATCH_3, 0x0a0a09); + */ + } +#else + /* index v << 16 | u << 8 | y */ + WRITE_VREG(AV_SCRATCH_0, 0x020100); + WRITE_VREG(AV_SCRATCH_1, 0x050403); + WRITE_VREG(AV_SCRATCH_2, 0x080706); + WRITE_VREG(AV_SCRATCH_3, 0x0b0a09); +#endif + /* notify ucode the buffer offset */ + WRITE_VREG(AV_SCRATCH_F, buf_offset); + + /* disable PSCALE for hardware sharing */ + WRITE_VREG(PSCALE_CTRL, 0); + + WRITE_VREG(AVS_SOS_COUNT, 0); + WRITE_VREG(AVS_BUFFERIN, 0); + WRITE_VREG(AVS_BUFFEROUT, 0); + if (error_recovery_mode) + WRITE_VREG(AVS_ERROR_RECOVERY_MODE, 0); + else + WRITE_VREG(AVS_ERROR_RECOVERY_MODE, 1); + /* clear mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + /* enable mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_MASK, 1); +#if 1 /* def DEBUG_UCODE */ + WRITE_VREG(AV_SCRATCH_D, 0); +#endif + +#ifdef NV21 + SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17); +#endif + +#ifdef PIC_DC_NEED_CLEAR + CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31); +#endif + +#ifdef AVSP_LONG_CABAC + if (firmware_sel == 0) { + WRITE_VREG(LONG_CABAC_DES_ADDR, es_write_addr_phy); + WRITE_VREG(LONG_CABAC_REQ, 0); + WRITE_VREG(LONG_CABAC_PIC_SIZE, 0); + WRITE_VREG(LONG_CABAC_SRC_ADDR, 0); + } +#endif + +#ifdef ENABLE_USER_DATA + WRITE_VREG(AV_SCRATCH_N, (u32)(user_data_buffer_phys - buf_offset)); + pr_debug("AV_SCRATCH_N = 0x%x\n", READ_VREG(AV_SCRATCH_N)); +#endif + + return r; +} + +#ifdef AVSP_LONG_CABAC +static unsigned char es_write_addr[MAX_CODED_FRAME_SIZE] __aligned(64); +#endif +static void vavs_local_init(void) +{ + int i; + + vavs_ratio = vavs_amstream_dec_info.ratio; + + avi_flag = (unsigned long) vavs_amstream_dec_info.param; + + frame_width = frame_height = frame_dur = frame_prog = 0; + + throw_pb_flag = 1; + + total_frame = 0; + saved_resolution = 0; + next_pts = 0; + +#ifdef DEBUG_PTS + pts_hit = pts_missed = pts_i_hit = pts_i_missed = 0; +#endif + INIT_KFIFO(display_q); + INIT_KFIFO(recycle_q); + INIT_KFIFO(newframe_q); + + for (i = 0; i < VF_POOL_SIZE; i++) { + const struct vframe_s *vf = &vfpool[i]; + + vfpool[i].index = vf_buf_num; + vfpool[i].bufWidth = 1920; + kfifo_put(&newframe_q, vf); + } + for (i = 0; i < vf_buf_num; i++) + vfbuf_use[i] = 0; + + cur_vfpool = vfpool; + + if (recover_flag == 1) + return; + + if (mm_blk_handle) { + decoder_bmmu_box_free(mm_blk_handle); + mm_blk_handle = NULL; + } + + mm_blk_handle = decoder_bmmu_box_alloc_box( + DRIVER_NAME, + 0, + MAX_BMMU_BUFFER_NUM, + 4 + PAGE_SHIFT, + CODEC_MM_FLAGS_CMA_CLEAR | + CODEC_MM_FLAGS_FOR_VDECODER); + +} + +static int vavs_vf_states(struct vframe_states *states, void *op_arg) +{ + unsigned long flags; + + spin_lock_irqsave(&lock, flags); + states->vf_pool_size = VF_POOL_SIZE; + states->buf_free_num = kfifo_len(&newframe_q); + states->buf_avail_num = kfifo_len(&display_q); + states->buf_recycle_num = kfifo_len(&recycle_q); + spin_unlock_irqrestore(&lock, flags); + return 0; +} + +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER +static void vavs_ppmgr_reset(void) +{ + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_RESET, NULL); + + vavs_local_init(); + + pr_info("vavs: vf_ppmgr_reset\n"); +} +#endif + +static void vavs_local_reset(void) +{ + mutex_lock(&vavs_mutex); + recover_flag = 1; + pr_info("error, local reset\n"); + amvdec_stop(); + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_RESET, NULL); + vavs_local_init(); + vavs_recover(); + +#ifdef ENABLE_USER_DATA + reset_userdata_fifo(1); +#endif + + amvdec_start(); + recover_flag = 0; +#if 0 + error_watchdog_count = 0; + + pr_info("pc %x stream buf wp %x rp %x level %x\n", + READ_VREG(MPC_E), + READ_VREG(VLD_MEM_VIFIFO_WP), + READ_VREG(VLD_MEM_VIFIFO_RP), + READ_VREG(VLD_MEM_VIFIFO_LEVEL)); +#endif + + + + mutex_unlock(&vavs_mutex); +} + +static struct work_struct fatal_error_wd_work; +static struct work_struct notify_work; +static atomic_t error_handler_run = ATOMIC_INIT(0); +static void vavs_fatal_error_handler(struct work_struct *work) +{ + if (debug_flag & AVS_DEBUG_OLD_ERROR_HANDLE) { + mutex_lock(&vavs_mutex); + pr_info("vavs fatal error reset !\n"); + amvdec_stop(); +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vavs_ppmgr_reset(); +#else + vf_light_unreg_provider(&vavs_vf_prov); + vavs_local_init(); + vf_reg_provider(&vavs_vf_prov); +#endif + vavs_recover(); + amvdec_start(); + mutex_unlock(&vavs_mutex); + } else { + pr_info("avs fatal_error_handler\n"); + vavs_local_reset(); + } + atomic_set(&error_handler_run, 0); +} + +static void vavs_notify_work(struct work_struct *work) +{ + if (fr_hint_status == VDEC_NEED_HINT) { + vf_notify_receiver(PROVIDER_NAME , + VFRAME_EVENT_PROVIDER_FR_HINT , + (void *)((unsigned long)frame_dur)); + fr_hint_status = VDEC_HINTED; + } + return; +} + +static void avs_set_clk(struct work_struct *work) +{ + if (frame_dur > 0 && saved_resolution != + frame_width * frame_height * (96000 / frame_dur)) { + int fps = 96000 / frame_dur; + + saved_resolution = frame_width * frame_height * fps; + if (firmware_sel == 0 && + (debug_flag & AVS_DEBUG_USE_FULL_SPEED)) { + vdec_source_changed(VFORMAT_AVS, + 4096, 2048, 60); + } else { + vdec_source_changed(VFORMAT_AVS, + frame_width, frame_height, fps); + } + + } +} + +static void vavs_put_timer_func(unsigned long arg) +{ + struct timer_list *timer = (struct timer_list *)arg; + +#ifndef HANDLE_AVS_IRQ + vavs_isr(); +#endif + + if (READ_VREG(AVS_SOS_COUNT)) { + if (!error_recovery_mode) { +#if 0 + if (debug_flag & AVS_DEBUG_OLD_ERROR_HANDLE) { + mutex_lock(&vavs_mutex); + pr_info("vavs fatal error reset !\n"); + amvdec_stop(); +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vavs_ppmgr_reset(); +#else + vf_light_unreg_provider(&vavs_vf_prov); + vavs_local_init(); + vf_reg_provider(&vavs_vf_prov); +#endif + vavs_recover(); + amvdec_start(); + mutex_unlock(&vavs_mutex); + } else { + vavs_local_reset(); + } +#else + if (!atomic_read(&error_handler_run)) { + atomic_set(&error_handler_run, 1); + pr_info("AVS_SOS_COUNT = %d\n", + READ_VREG(AVS_SOS_COUNT)); + pr_info("WP = 0x%x, RP = 0x%x, LEVEL = 0x%x, AVAIL = 0x%x, CUR_PTR = 0x%x\n", + READ_VREG(VLD_MEM_VIFIFO_WP), + READ_VREG(VLD_MEM_VIFIFO_RP), + READ_VREG(VLD_MEM_VIFIFO_LEVEL), + READ_VREG(VLD_MEM_VIFIFO_BYTES_AVAIL), + READ_VREG(VLD_MEM_VIFIFO_CURR_PTR)); + schedule_work(&fatal_error_wd_work); + } +#endif + } + } +#if 0 + if (long_cabac_busy == 0 && + error_watchdog_threshold > 0 && + kfifo_len(&display_q) == 0 && + READ_VREG(VLD_MEM_VIFIFO_LEVEL) > + error_watchdog_buf_threshold) { + pr_info("newq %d dispq %d recyq %d\r\n", + kfifo_len(&newframe_q), + kfifo_len(&display_q), + kfifo_len(&recycle_q)); + pr_info("pc %x stream buf wp %x rp %x level %x\n", + READ_VREG(MPC_E), + READ_VREG(VLD_MEM_VIFIFO_WP), + READ_VREG(VLD_MEM_VIFIFO_RP), + READ_VREG(VLD_MEM_VIFIFO_LEVEL)); + error_watchdog_count++; + if (error_watchdog_count >= error_watchdog_threshold) + vavs_local_reset(); + } else + error_watchdog_count = 0; +#endif + if (radr != 0) { + if (rval != 0) { + WRITE_VREG(radr, rval); + pr_info("WRITE_VREG(%x,%x)\n", radr, rval); + } else + pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr)); + rval = 0; + radr = 0; + } + + if (!kfifo_is_empty(&recycle_q) && (READ_VREG(AVS_BUFFERIN) == 0)) { + struct vframe_s *vf; + + if (kfifo_get(&recycle_q, &vf)) { + if ((vf->index < vf_buf_num) && + (--vfbuf_use[vf->index] == 0)) { + WRITE_VREG(AVS_BUFFERIN, ~(1 << vf->index)); + vf->index = vf_buf_num; + } + kfifo_put(&newframe_q, + (const struct vframe_s *)vf); + } + + } + + schedule_work(&set_clk_work); + + timer->expires = jiffies + PUT_INTERVAL; + + add_timer(timer); +} + +#ifdef AVSP_LONG_CABAC + +static void long_cabac_do_work(struct work_struct *work) +{ + int status = 0; +#ifdef PERFORMANCE_DEBUG + pr_info("enter %s buf level (new %d, display %d, recycle %d)\r\n", + __func__, + kfifo_len(&newframe_q), + kfifo_len(&display_q), + kfifo_len(&recycle_q) + ); +#endif + mutex_lock(&vavs_mutex); + long_cabac_busy = 1; + while (READ_VREG(LONG_CABAC_REQ)) { + if (process_long_cabac() < 0) { + status = -1; + break; + } + } + long_cabac_busy = 0; + mutex_unlock(&vavs_mutex); +#ifdef PERFORMANCE_DEBUG + pr_info("exit %s buf level (new %d, display %d, recycle %d)\r\n", + __func__, + kfifo_len(&newframe_q), + kfifo_len(&display_q), + kfifo_len(&recycle_q) + ); +#endif + if (status < 0) { + pr_info("transcoding error, local reset\r\n"); + vavs_local_reset(); + } + +} +#endif + +#ifdef AVSP_LONG_CABAC +static void init_avsp_long_cabac_buf(void) +{ +#if 0 + es_write_addr_phy = (unsigned long)codec_mm_alloc_for_dma( + "vavs", + PAGE_ALIGN(MAX_CODED_FRAME_SIZE)/PAGE_SIZE, + 0, CODEC_MM_FLAGS_DMA_CPU); + es_write_addr_virt = codec_mm_phys_to_virt(es_write_addr_phy); + +#elif 0 + es_write_addr_virt = + (void *)dma_alloc_coherent(amports_get_dma_device(), + MAX_CODED_FRAME_SIZE, &es_write_addr_phy, + GFP_KERNEL); +#else + /*es_write_addr_virt = kmalloc(MAX_CODED_FRAME_SIZE, GFP_KERNEL); + * es_write_addr_virt = (void *)__get_free_pages(GFP_KERNEL, + * get_order(MAX_CODED_FRAME_SIZE)); + */ + es_write_addr_virt = &es_write_addr[0]; + if (es_write_addr_virt == NULL) { + pr_err("%s: failed to alloc es_write_addr_virt buffer\n", + __func__); + return; + } + + es_write_addr_phy = dma_map_single(amports_get_dma_device(), + es_write_addr_virt, + MAX_CODED_FRAME_SIZE, DMA_BIDIRECTIONAL); + if (dma_mapping_error(amports_get_dma_device(), + es_write_addr_phy)) { + pr_err("%s: failed to map es_write_addr_virt buffer\n", + __func__); + /*kfree(es_write_addr_virt);*/ + es_write_addr_virt = NULL; + return; + } +#endif + + +#ifdef BITSTREAM_READ_TMP_NO_CACHE + bitstream_read_tmp = + (void *)dma_alloc_coherent(amports_get_dma_device(), + SVA_STREAM_BUF_SIZE, &bitstream_read_tmp_phy, + GFP_KERNEL); + +#else + + bitstream_read_tmp = kmalloc(SVA_STREAM_BUF_SIZE, GFP_KERNEL); + /*bitstream_read_tmp = (void *)__get_free_pages(GFP_KERNEL, + *get_order(MAX_CODED_FRAME_SIZE)); + */ + if (bitstream_read_tmp == NULL) { + pr_err("%s: failed to alloc bitstream_read_tmp buffer\n", + __func__); + return; + } + + bitstream_read_tmp_phy = dma_map_single(amports_get_dma_device(), + bitstream_read_tmp, + SVA_STREAM_BUF_SIZE, DMA_FROM_DEVICE); + if (dma_mapping_error(amports_get_dma_device(), + bitstream_read_tmp_phy)) { + pr_err("%s: failed to map rpm buffer\n", __func__); + kfree(bitstream_read_tmp); + bitstream_read_tmp = NULL; + return; + } +#endif +} +#endif + + +static s32 vavs_init(void) +{ + int r, size = -1; + char *buf = vmalloc(0x1000 * 16); + + if (IS_ERR_OR_NULL(buf)) + return -ENOMEM; + + pr_info("vavs_init\n"); + init_timer(&recycle_timer); + + stat |= STAT_TIMER_INIT; + + amvdec_enable(); + + vavs_local_init(); + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXM) + size = get_firmware_data(VIDEO_DEC_AVS, buf); + else { + if (firmware_sel == 1) + size = get_firmware_data(VIDEO_DEC_AVS_NOCABAC, buf); +#ifdef AVSP_LONG_CABAC + else { + init_avsp_long_cabac_buf(); + size = get_firmware_data(VIDEO_DEC_AVS, buf); + } +#endif + } + + if (size < 0) { + amvdec_disable(); + pr_err("get firmware fail."); + vfree(buf); + return -1; + } + + if (size == 1) + pr_info("tee load ok\n"); + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXM) + size = amvdec_loadmc_ex(VFORMAT_AVS, NULL, buf); + else if (firmware_sel == 1) + size = amvdec_loadmc_ex(VFORMAT_AVS, "avs_no_cabac", buf); + else + size = amvdec_loadmc_ex(VFORMAT_AVS, NULL, buf); + + if (size < 0) { + amvdec_disable(); + vfree(buf); + return -EBUSY; + } + + vfree(buf); + + stat |= STAT_MC_LOAD; + + /* enable AMRISC side protocol */ + r = vavs_prot_init(); + if (r < 0) + return r; + +#ifdef HANDLE_AVS_IRQ + if (vdec_request_irq(VDEC_IRQ_1, vavs_isr, + "vavs-irq", (void *)vavs_dec_id)) { + amvdec_disable(); + pr_info("vavs irq register error.\n"); + return -ENOENT; + } +#endif + + stat |= STAT_ISR_REG; + +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_provider_init(&vavs_vf_prov, PROVIDER_NAME, &vavs_vf_provider, NULL); + vf_reg_provider(&vavs_vf_prov); + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL); +#else + vf_provider_init(&vavs_vf_prov, PROVIDER_NAME, &vavs_vf_provider, NULL); + vf_reg_provider(&vavs_vf_prov); +#endif + + if (vavs_amstream_dec_info.rate != 0) { + if (!is_reset) + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_FR_HINT, + (void *)((unsigned long) + vavs_amstream_dec_info.rate)); + fr_hint_status = VDEC_HINTED; + } else + fr_hint_status = VDEC_NEED_HINT; + + stat |= STAT_VF_HOOK; + + recycle_timer.data = (ulong)(&recycle_timer); + recycle_timer.function = vavs_put_timer_func; + recycle_timer.expires = jiffies + PUT_INTERVAL; + + add_timer(&recycle_timer); + + stat |= STAT_TIMER_ARM; + +#ifdef AVSP_LONG_CABAC + if (firmware_sel == 0) + INIT_WORK(&long_cabac_wd_work, long_cabac_do_work); +#endif + + amvdec_start(); + + stat |= STAT_VDEC_RUN; + + return 0; +} + +static int amvdec_avs_probe(struct platform_device *pdev) +{ + struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; + + if (pdata == NULL) { + pr_info("amvdec_avs memory resource undefined.\n"); + return -EFAULT; + } + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXM || disable_longcabac_trans) + firmware_sel = 1; + + if (firmware_sel == 1) { + vf_buf_num = 4; + canvas_base = 0; + canvas_num = 3; + } else { + + canvas_base = 128; + canvas_num = 2; /*NV21*/ + } + + + if (pdata->sys_info) + vavs_amstream_dec_info = *pdata->sys_info; + + pr_info("%s (%d,%d) %d\n", __func__, vavs_amstream_dec_info.width, + vavs_amstream_dec_info.height, vavs_amstream_dec_info.rate); + + pdata->dec_status = vavs_dec_status; + pdata->set_isreset = vavs_set_isreset; + is_reset = 0; + + pdata->user_data_read = NULL; + pdata->reset_userdata_fifo = NULL; + + vavs_vdec_info_init(); + +#ifdef ENABLE_USER_DATA + if (NULL == user_data_buffer) { + user_data_buffer = + dma_alloc_coherent(amports_get_dma_device(), + USER_DATA_SIZE, + &user_data_buffer_phys, GFP_KERNEL); + if (!user_data_buffer) { + pr_info("%s: Can not allocate user_data_buffer\n", + __func__); + return -ENOMEM; + } + pr_debug("user_data_buffer = 0x%p, user_data_buffer_phys = 0x%x\n", + user_data_buffer, (u32)user_data_buffer_phys); + } +#endif + INIT_WORK(&set_clk_work, avs_set_clk); + if (vavs_init() < 0) { + pr_info("amvdec_avs init failed.\n"); + kfree(gvs); + gvs = NULL; + + return -ENODEV; + } + vdec = pdata; + + INIT_WORK(&fatal_error_wd_work, vavs_fatal_error_handler); + atomic_set(&error_handler_run, 0); +#ifdef ENABLE_USER_DATA + INIT_WORK(&userdata_push_work, userdata_push_do_work); +#endif + INIT_WORK(¬ify_work, vavs_notify_work); + + return 0; +} + +static int amvdec_avs_remove(struct platform_device *pdev) +{ + cancel_work_sync(&fatal_error_wd_work); + atomic_set(&error_handler_run, 0); +#ifdef ENABLE_USER_DATA + cancel_work_sync(&userdata_push_work); +#endif + cancel_work_sync(¬ify_work); + cancel_work_sync(&set_clk_work); + if (stat & STAT_VDEC_RUN) { + amvdec_stop(); + stat &= ~STAT_VDEC_RUN; + } + + if (stat & STAT_ISR_REG) { + vdec_free_irq(VDEC_IRQ_1, (void *)vavs_dec_id); + stat &= ~STAT_ISR_REG; + } + + if (stat & STAT_TIMER_ARM) { + del_timer_sync(&recycle_timer); + stat &= ~STAT_TIMER_ARM; + } +#ifdef AVSP_LONG_CABAC + if (firmware_sel == 0) { + mutex_lock(&vavs_mutex); + cancel_work_sync(&long_cabac_wd_work); + mutex_unlock(&vavs_mutex); + + if (es_write_addr_virt) { +#if 0 + codec_mm_free_for_dma("vavs", es_write_addr_phy); +#else + dma_unmap_single(amports_get_dma_device(), + es_write_addr_phy, + MAX_CODED_FRAME_SIZE, DMA_FROM_DEVICE); + /*kfree(es_write_addr_virt);*/ + es_write_addr_virt = NULL; +#endif + } + +#ifdef BITSTREAM_READ_TMP_NO_CACHE + if (bitstream_read_tmp) { + dma_free_coherent(amports_get_dma_device(), + SVA_STREAM_BUF_SIZE, bitstream_read_tmp, + bitstream_read_tmp_phy); + bitstream_read_tmp = NULL; + } +#else + if (bitstream_read_tmp) { + dma_unmap_single(amports_get_dma_device(), + bitstream_read_tmp_phy, + SVA_STREAM_BUF_SIZE, DMA_FROM_DEVICE); + kfree(bitstream_read_tmp); + bitstream_read_tmp = NULL; + } +#endif + } +#endif + if (stat & STAT_VF_HOOK) { + if (fr_hint_status == VDEC_HINTED && !is_reset) + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_FR_END_HINT, NULL); + fr_hint_status = VDEC_NO_NEED_HINT; + vf_unreg_provider(&vavs_vf_prov); + stat &= ~STAT_VF_HOOK; + } + +#ifdef ENABLE_USER_DATA + if (user_data_buffer != NULL) { + dma_free_coherent( + amports_get_dma_device(), + USER_DATA_SIZE, + user_data_buffer, + user_data_buffer_phys); + user_data_buffer = NULL; + user_data_buffer_phys = 0; + } +#endif + amvdec_disable(); + + pic_type = 0; + if (mm_blk_handle) { + decoder_bmmu_box_free(mm_blk_handle); + mm_blk_handle = NULL; + } +#ifdef DEBUG_PTS + pr_debug("pts hit %d, pts missed %d, i hit %d, missed %d\n", pts_hit, + pts_missed, pts_i_hit, pts_i_missed); + pr_debug("total frame %d, avi_flag %d, rate %d\n", total_frame, avi_flag, + vavs_amstream_dec_info.rate); +#endif + kfree(gvs); + gvs = NULL; + + return 0; +} + +/****************************************/ + +static struct platform_driver amvdec_avs_driver = { + .probe = amvdec_avs_probe, + .remove = amvdec_avs_remove, + .driver = { + .name = DRIVER_NAME, + } +}; + +static struct codec_profile_t amvdec_avs_profile = { + .name = "avs", + .profile = "" +}; + +static struct mconfig avs_configs[] = { + MC_PU32("stat", &stat), + MC_PU32("debug_flag", &debug_flag), + MC_PU32("error_recovery_mode", &error_recovery_mode), + MC_PU32("pic_type", &pic_type), + MC_PU32("radr", &radr), + MC_PU32("vf_buf_num", &vf_buf_num), + MC_PU32("vf_buf_num_used", &vf_buf_num_used), + MC_PU32("canvas_base", &canvas_base), + MC_PU32("firmware_sel", &firmware_sel), +}; +static struct mconfig_node avs_node; + + +static int __init amvdec_avs_driver_init_module(void) +{ + pr_debug("amvdec_avs module init\n"); + + if (platform_driver_register(&amvdec_avs_driver)) { + pr_info("failed to register amvdec_avs driver\n"); + return -ENODEV; + } + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) + amvdec_avs_profile.profile = "avs+"; + + vcodec_profile_register(&amvdec_avs_profile); + INIT_REG_NODE_CONFIGS("media.decoder", &avs_node, + "avs", avs_configs, CONFIG_FOR_RW); + return 0; +} + +static void __exit amvdec_avs_driver_remove_module(void) +{ + pr_debug("amvdec_avs module remove.\n"); + + platform_driver_unregister(&amvdec_avs_driver); +} + +/****************************************/ + +module_param(stat, uint, 0664); +MODULE_PARM_DESC(stat, "\n amvdec_avs stat\n"); + +/****************************************** + *module_param(run_flag, uint, 0664); + *MODULE_PARM_DESC(run_flag, "\n run_flag\n"); + * + *module_param(step_flag, uint, 0664); + *MODULE_PARM_DESC(step_flag, "\n step_flag\n"); + ******************************************* + */ + +module_param(debug_flag, uint, 0664); +MODULE_PARM_DESC(debug_flag, "\n debug_flag\n"); + +module_param(error_recovery_mode, uint, 0664); +MODULE_PARM_DESC(error_recovery_mode, "\n error_recovery_mode\n"); + +/****************************************** + *module_param(error_watchdog_threshold, uint, 0664); + *MODULE_PARM_DESC(error_watchdog_threshold, "\n error_watchdog_threshold\n"); + * + *module_param(error_watchdog_buf_threshold, uint, 0664); + *MODULE_PARM_DESC(error_watchdog_buf_threshold, + * "\n error_watchdog_buf_threshold\n"); + ******************************************* + */ + +module_param(pic_type, uint, 0444); +MODULE_PARM_DESC(pic_type, "\n amdec_vas picture type\n"); + +module_param(radr, uint, 0664); +MODULE_PARM_DESC(radr, "\nradr\n"); + +module_param(rval, uint, 0664); +MODULE_PARM_DESC(rval, "\nrval\n"); + +module_param(vf_buf_num, uint, 0664); +MODULE_PARM_DESC(vf_buf_num, "\nvf_buf_num\n"); + +module_param(vf_buf_num_used, uint, 0664); +MODULE_PARM_DESC(vf_buf_num_used, "\nvf_buf_num_used\n"); + +module_param(canvas_base, uint, 0664); +MODULE_PARM_DESC(canvas_base, "\ncanvas_base\n"); + + +module_param(firmware_sel, uint, 0664); +MODULE_PARM_DESC(firmware_sel, "\n firmware_sel\n"); + +module_param(disable_longcabac_trans, uint, 0664); +MODULE_PARM_DESC(disable_longcabac_trans, "\n disable_longcabac_trans\n"); + +module_init(amvdec_avs_driver_init_module); +module_exit(amvdec_avs_driver_remove_module); + +MODULE_DESCRIPTION("AMLOGIC AVS Video Decoder Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Qi Wang "); diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/avs/avs.h b/drivers/amlogic/media_modules/frame_provider/decoder/avs/avs.h new file mode 100644 index 000000000000..93a04de603df --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/avs/avs.h @@ -0,0 +1,72 @@ +#ifndef AVS_H_ +#define AVS_H_ + +#ifdef CONFIG_AMLOGIC_AVSP_LONG_CABAC +#define AVSP_LONG_CABAC +#endif +/*#define BITSTREAM_READ_TMP_NO_CACHE*/ + +#ifdef AVSP_LONG_CABAC +#define MAX_CODED_FRAME_SIZE 1500000 /*!< bytes for one frame*/ +#define LOCAL_HEAP_SIZE (1024*1024*10) +/* + *#define MAX_CODED_FRAME_SIZE 240000 + *#define MAX_CODED_FRAME_SIZE 700000 + */ +#define SVA_STREAM_BUF_SIZE 1024 + +extern void *es_write_addr_virt; +extern dma_addr_t es_write_addr_phy; + +extern void *bitstream_read_tmp; +extern dma_addr_t bitstream_read_tmp_phy; +extern void *avsp_heap_adr; + +int avs_get_debug_flag(void); + +int process_long_cabac(void); + +/* bit [6] - skip_mode_flag + * bit [5:4] - picture_type + * bit [3] - picture_structure (0-Field, 1-Frame) + * bit [2] - fixed_picture_qp + * bit [1] - progressive_sequence + * bit [0] - active + */ +#define LONG_CABAC_REQ AV_SCRATCH_K +#define LONG_CABAC_SRC_ADDR AV_SCRATCH_H +#define LONG_CABAC_DES_ADDR AV_SCRATCH_I +/* bit[31:16] - vertical_size + * bit[15:0] - horizontal_size + */ +#define LONG_CABAC_PIC_SIZE AV_SCRATCH_J + +#endif + +/* + *#define PERFORMANCE_DEBUG + *#define DUMP_DEBUG + */ +#define AVS_DEBUG_PRINT 0x01 +#define AVS_DEBUG_UCODE 0x02 +#define AVS_DEBUG_OLD_ERROR_HANDLE 0x10 +#define AVS_DEBUG_USE_FULL_SPEED 0x80 +#define AEC_DUMP 0x100 +#define STREAM_INFO_DUMP 0x200 +#define SLICE_INFO_DUMP 0x400 +#define MB_INFO_DUMP 0x800 +#define MB_NUM_DUMP 0x1000 +#define BLOCK_NUM_DUMP 0x2000 +#define COEFF_DUMP 0x4000 +#define ES_DUMP 0x8000 +#define DQUANT_DUMP 0x10000 +#define STREAM_INFO_DUMP_MORE 0x20000 +#define STREAM_INFO_DUMP_MORE2 0x40000 + +extern void *es_write_addr_virt; +extern void *bitstream_read_tmp; +extern dma_addr_t bitstream_read_tmp_phy; +int read_bitstream(unsigned char *Buf, int size); +int u_v(int LenInBits, char *tracestring); + +#endif diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/avs/avsp_trans.c b/drivers/amlogic/media_modules/frame_provider/decoder/avs/avsp_trans.c new file mode 100644 index 000000000000..2aca5ebe094d --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/avs/avsp_trans.c @@ -0,0 +1,5046 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +/* #include */ +#include +#include +#include "../../../stream_input/parser/streambuf_reg.h" +#include "../utils/amvdec.h" +#include +#include "../../../stream_input/amports/amports_priv.h" + +#include "avs.h" +#ifdef AVSP_LONG_CABAC + +#define DECODING_SANITY_CHECK + +#define TRACE 0 +#define LIWR_FIX 0 +#define pow2(a, b) (1< 0) { + if (num >= 8) + push_num = 8; + else + push_num = num; + + num = num - push_num; + push_value = (value >> num); + + es_res = (es_res << push_num) | push_value; + es_res_ptr = es_res_ptr + push_num; + +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & ES_DUMP) + io_printf(" #### es_res : 0x%X, es_res_ptr : %d\n", + es_res, es_res_ptr); +#endif + + while (es_res_ptr >= 8) { + es_res_ptr = es_res_ptr & 7; + wr_es_data = (es_res >> es_res_ptr) & 0xff; + if ((previous_es == 0) & (wr_es_data < 4)) { + io_printf( + " Insert 2'b10 for emu at position : %d\n", + es_ptr); + + es_res_ptr = es_res_ptr + 2; + wr_es_data = 2; + } +#ifdef AVSP_LONG_CABAC +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & ES_DUMP) + pr_info("es_buf[%d] = 0x%02x\r\n", + es_buf_ptr, wr_es_data); +#endif + if (!es_buf_is_overflow) { + es_buf[es_buf_ptr++] = wr_es_data; + if (es_buf_ptr >= MAX_CODED_FRAME_SIZE) + es_buf_is_overflow = 1; + } +#else + putc(wr_es_data, f_es); +#endif + es_ptr++; + previous_es = ((previous_es << 8) | wr_es_data) + & 0xffff; + } + + } +} + +#ifdef BLOCK_SIZE +#undef BLOCK_SIZE +#endif + +#define MIN_QP 0 +#define MAX_QP 63 + +#define BLOCK_SIZE 4 +#define B8_SIZE 8 +#define MB_BLOCK_SIZE 16 + +#define BLOCK_MULTIPLE (MB_BLOCK_SIZE/(BLOCK_SIZE*2)) + +#define DECODE_COPY_MB 0 +#define DECODE_MB 1 + +#define NO_INTRA_PMODE 5 +#define INTRA_PMODE_4x4 10 +#define NO_INTRA_PMODE_4x4 19 +/* 8x8 intra prediction modes */ +#define VERT_PRED 0 +#define HOR_PRED 1 +#define DC_PRED 2 +#define DOWN_LEFT_PRED 3 +#define DOWN_RIGHT_PRED 4 + +#define VERT_PRED_4x4 0 +#define HOR_PRED_4x4 1 +#define DC_PRED_4x4 2 +#define DOWN_LEFT_PRED_4x4 3 +#define DOWN_RIGHT_PRED_4x4 4 + +#define HOR_DOWN_PRED_4x4 5 +#define VERT_LEFT_PRED_4x4 6 +#define HOR_UP_PRED_4x4 7 +#define VERT_RIGHT_PRED_4x4 8 + +#define DC_PRED_8 0 +#define HOR_PRED_8 1 +#define VERT_PRED_8 2 +#define PLANE_8 3 + +#define LUMA_16DC 0 +#define LUMA_16AC 1 +#define LUMA_8x8 2 +#define LUMA_8x4 3 +#define LUMA_4x8 4 +#define LUMA_4x4 5 +#define CHROMA_DC 6 +#define CHROMA_AC 7 +#define NUM_BLOCK_TYPES 8 + +#define I_PICTURE_START_CODE 0xB3 +#define PB_PICTURE_START_CODE 0xB6 +#define SLICE_START_CODE_MIN 0x00 +#define SLICE_START_CODE_MAX 0xAF +#define USER_DATA_START_CODE 0xB2 +#define SEQUENCE_HEADER_CODE 0xB0 +#define EXTENSION_START_CODE 0xB5 +#define SEQUENCE_END_CODE 0xB1 +#define VIDEO_EDIT_CODE 0xB7 + +#define EOS 1 +#define SOP 2 +#define SOS 3 +#define P8x8 8 +#define I8MB 9 +#define I4MB 10 +#define IBLOCK 11 +#define SI4MB 12 +#define MAXMODE 13 + +#define IS_INTRA(MB) ((MB)->mb_type == I8MB || (MB)->mb_type == I4MB) +#define IS_NEWINTRA(MB) ((MB)->mb_type == I4MB) +#define IS_OLDINTRA(MB) ((MB)->mb_type == I8MB) +#define IS_INTER(MB) ((MB)->mb_type != I8MB && (MB)->mb_type != I4MB) +#define IS_INTERMV(MB) ((MB)->mb_type != I8MB && (MB)->mb_type != I4MB\ + && (MB)->mb_type != 0) + +#define IS_DIRECT(MB) ((MB)->mb_type == 0 && (img->type == B_IMG)) +#define IS_COPY(MB) ((MB)->mb_type == 0 && (img->type == P_IMG)) +#define IS_P8x8(MB) ((MB)->mb_type == P8x8) + +#define P_IMG 0 +#define B_IMG 1 +#define I_IMG 2 + +#define FIELD 0 +#define FRAME 1 + +#define SE_CABP 21 +struct decoding_environment_s { + unsigned int dbuffer; + int dbits_to_go; + unsigned char *dcodestrm; + int *dcodestrm_len; +}; + +struct bi_context_type_s { + unsigned char MPS; + unsigned int LG_PMPS; + unsigned char cycno; +}; + + +/********************************************************************** + * C O N T E X T S F O R R M S Y N T A X E L E M E N T S + ********************************************************************** + */ + +#define NUM_MB_TYPE_CTX 11 +#define NUM_B8_TYPE_CTX 9 +#define NUM_MV_RES_CTX 10 +#define NUM_REF_NO_CTX 6 +#define NUM_DELTA_QP_CTX 4 +#define NUM_MB_AFF_CTX 4 + +struct motion_info_contexts_s { + struct bi_context_type_s mb_type_contexts[4][NUM_MB_TYPE_CTX]; + struct bi_context_type_s b8_type_contexts[2][NUM_B8_TYPE_CTX]; + struct bi_context_type_s mv_res_contexts[2][NUM_MV_RES_CTX]; + struct bi_context_type_s ref_no_contexts[2][NUM_REF_NO_CTX]; + struct bi_context_type_s delta_qp_contexts[NUM_DELTA_QP_CTX]; + struct bi_context_type_s mb_aff_contexts[NUM_MB_AFF_CTX]; +#ifdef TEST_WEIGHTING_AEC +struct bi_context_type_s mb_weighting_pred; +#endif +}; + +#define NUM_IPR_CTX 2 +#define NUM_CIPR_CTX 4 +#define NUM_CBP_CTX 4 +#define NUM_BCBP_CTX 4 +#define NUM_MAP_CTX 16 +#define NUM_LAST_CTX 16 + +#define NUM_ONE_CTX 5 +#define NUM_ABS_CTX 5 + +struct texture_info_contexts { + struct bi_context_type_s ipr_contexts[NUM_IPR_CTX]; + struct bi_context_type_s cipr_contexts[NUM_CIPR_CTX]; + struct bi_context_type_s cbp_contexts[3][NUM_CBP_CTX]; + struct bi_context_type_s bcbp_contexts[NUM_BLOCK_TYPES][NUM_BCBP_CTX]; + struct bi_context_type_s one_contexts[NUM_BLOCK_TYPES][NUM_ONE_CTX]; + struct bi_context_type_s abs_contexts[NUM_BLOCK_TYPES][NUM_ABS_CTX]; + struct bi_context_type_s fld_map_contexts[NUM_BLOCK_TYPES][NUM_MAP_CTX]; + struct bi_context_type_s fld_last_contexts + [NUM_BLOCK_TYPES][NUM_LAST_CTX]; + struct bi_context_type_s map_contexts[NUM_BLOCK_TYPES][NUM_MAP_CTX]; + struct bi_context_type_s last_contexts[NUM_BLOCK_TYPES][NUM_LAST_CTX]; +}; +struct img_par; + +struct syntaxelement { + int type; + int value1; + int value2; + int len; + int inf; + unsigned int bitpattern; + int context; + int k; + int golomb_grad; + int golomb_maxlevels; +#if TRACE +#define TRACESTRING_SIZE 100 + char tracestring[TRACESTRING_SIZE]; +#endif + + void (*mapping)(int len, int info, int *value1, int *value2); + + void (*reading)(struct syntaxelement *, struct img_par *, + struct decoding_environment_s *); + +}; + +struct bitstream_s { + + int read_len; + int code_len; + + int frame_bitoffset; + int bitstream_length; + + unsigned char *stream_buffer; +}; + +struct datapartition { + + struct bitstream_s *bitstream; + struct decoding_environment_s de_aec; + + int (*read_syntax_element)(struct syntaxelement *, struct img_par *, + struct datapartition *); +/*!< virtual function; + * actual method depends on chosen data partition and + * entropy coding method + */ +}; + +struct slice_s { + int picture_id; + int qp; + int picture_type; + int start_mb_nr; + int max_part_nr; + int num_mb; + + struct datapartition *part_arr; + struct motion_info_contexts_s *mot_ctx; + struct texture_info_contexts *tex_ctx; + int field_ctx[3][2]; +}; + +struct img_par { + int number; + int current_mb_nr; + int max_mb_nr; + int current_slice_nr; + int tr; + int qp; + int type; + + int typeb; + + int width; + int height; + int width_cr; + int height_cr; + int source_bitdepth; + int mb_y; + int mb_x; + int block_y; + int pix_y; + int pix_x; + int pix_c_y; + int block_x; + int pix_c_x; + + int ***mv; + int mpr[16][16]; + + int m7[16][16]; + int m8[/*2*/4][8][8]; + int cof[4][/*6*/8][4][4]; + int cofu[4]; + int **ipredmode; + int quad[256]; + int cod_counter; + + int ***dfmv; + int ***dbmv; + int **fw_reffrarr; + int **bw_reffrarr; + + int ***mv_frm; + int **fw_reffrarr_frm; + int **bw_reffrarr_frm; + int imgtr_next_p; + int imgtr_last_p; + int tr_frm; + int tr_fld; + int imgtr_last_prev_p; + + int no_forward_reference; + int seq_header_indicate; + int b_discard_flag; + + int ***fw_mv; + int ***bw_mv; + int subblock_x; + int subblock_y; + + int buf_cycle; + + int direct_type; + + int ***mv_top; + int ***mv_bot; + int **fw_reffrarr_top; + int **bw_reffrarr_top; + int **fw_reffrarr_bot; + int **bw_reffrarr_bot; + + int **ipredmode_top; + int **ipredmode_bot; + int ***fw_mv_top; + int ***fw_mv_bot; + int ***bw_mv_top; + int ***bw_mv_bot; + int ***dfmv_top; + int ***dbmv_top; + int ***dfmv_bot; + int ***dbm_bot; + + int toppoc; + int bottompoc; + int framepoc; + unsigned int frame_num; + + unsigned int pic_distance; + int delta_pic_order_cnt_bottom; + + signed int pic_distance_msb; + unsigned int prev_pic_distance_lsb; + signed int curr_pic_distance_msb; + unsigned int this_poc; + + int pic_width_inmbs; + int pic_height_inmbs; + int pic_size_inmbs; + + int block8_x, block8_y; + int structure; + int pn; + int buf_used; + int buf_size; + int picture_structure; + int advanced_pred_mode_disable; + int types; + int current_mb_nr_fld; + + int p_field_enhanced; + int b_field_enhanced; + + int slice_weighting_flag; + int lum_scale[4]; + int lum_shift[4]; + int chroma_scale[4]; + int chroma_shift[4]; + int mb_weighting_flag; + int weighting_prediction; + int mpr_weight[16][16]; + int top_bot; + int bframe_number; + + int auto_crop_right; + int auto_crop_bottom; + + struct slice_s *current_slice; + int is_v_block; + int is_intra_block; + + int new_seq_header_flag; + int new_sequence_flag; + int last_pic_bbv_delay; + + int sequence_end_flag; + int is_top_field; + + int abt_flag; + int qp_shift; + +#ifdef EIGHTH +int eighth_subpixel_flag; +int subpixel_precision; +int unit_length; +int subpixel_mask; + +int max_mvd; +int min_mvd; +#endif + +}; + +struct macroblock { + int qp; + int slice_nr; + int delta_quant; + struct macroblock *mb_available[3][3]; + /*!< pointer to neighboring MBs in a 3x3 window of current MB, + *which is located at [1][1] + * NULL pointer identifies neighboring MBs which are unavailable + */ + + int mb_type; + int mvd[2][BLOCK_MULTIPLE][BLOCK_MULTIPLE][2]; + int cbp, cbp_blk, cbp01; + unsigned long cbp_bits; + + int b8mode[4]; + int b8pdir[4]; + int mb_type_2; + int c_ipred_mode_2; + int dct_mode; + + int c_ipred_mode; + int lf_disable; + int lf_alpha_c0_offset; + int lf_beta_offset; + + int CABT[4]; + int CABP[4]; + int cbp_4x4[4]; + + int skip_flag; + + struct macroblock *mb_available_up; + struct macroblock *mb_available_left; + unsigned int mbaddr_a, mbaddr_b, mbaddr_c, mbaddr_d; + unsigned int mbavail_a, mbavail_b, mbavail_c, mbavail_d; + +}; + +struct macroblock *mb_data; + +struct img_par *img; + +struct bitstream_s *curr_stream; + +struct datapartition *alloc_partition(int n); + +unsigned int vld_mem_start_addr; +unsigned int vld_mem_end_addr; + +int marker_bit; + +int progressive_sequence; +int horizontal_size; +int vertical_size; + +int second_ifield; +int pre_img_type; + +/* slice_header() */ +int slice_vertical_position; +int slice_vertical_position_extension; +int fixed_picture_qp; +int fixed_slice_qp; +int slice_qp; + +/* + ************************************************************************* + * Function:ue_v, reads an u(v) syntax element, the length in bits is stored in + the global UsedBits variable + * Input: + tracestring + the string for the trace file + bitstream + the stream to be read from + * Output: + * Return: the value of the coded syntax element + * Attention: + ************************************************************************* + */ +/*! + * definition of AVS syntaxelements + * order of elements follow dependencies for picture reconstruction + */ +/*! + * \brief Assignment of old TYPE partition elements to new + * elements + * + * old element | new elements + * TYPE_HEADER | SE_HEADER, SE_PTYPE + * TYPE_MBHEADER | SE_MBTYPE, SE_REFFRAME, SE_INTRAPREDMODE + * TYPE_MVD | SE_MVD + * TYPE_CBP | SE_CBP_INTRA, SE_CBP_INTER * SE_DELTA_QUANT_INTER + * SE_DELTA_QUANT_INTRA + * TYPE_COEFF_Y | SE_LUM_DC_INTRA, SE_LUM_AC_INTRA, + SE_LUM_DC_INTER, SE_LUM_AC_INTER + * TYPE_2x2DC | SE_CHR_DC_INTRA, SE_CHR_DC_INTER + * TYPE_COEFF_C | SE_CHR_AC_INTRA, SE_CHR_AC_INTER + * TYPE_EOS | SE_EOS + */ + +#define SE_HEADER 0 +#define SE_PTYPE 1 +#define SE_MBTYPE 2 +#define SE_REFFRAME 3 +#define SE_INTRAPREDMODE 4 +#define SE_MVD 5 +#define SE_CBP_INTRA 6 +#define SE_LUM_DC_INTRA 7 +#define SE_CHR_DC_INTRA 8 +#define SE_LUM_AC_INTRA 9 +#define SE_CHR_AC_INTRA 10 +#define SE_CBP_INTER 11 +#define SE_LUM_DC_INTER 12 +#define SE_CHR_DC_INTER 13 +#define SE_LUM_AC_INTER 14 +#define SE_CHR_AC_INTER 15 +#define SE_DELTA_QUANT_INTER 16 +#define SE_DELTA_QUANT_INTRA 17 +#define SE_BFRAME 18 +#define SE_EOS 19 +#define SE_MAX_ELEMENTS 20 +#define SE_CBP01 21 +int chroma_format; +/* + ************************************************************************* + * Function:Reads bits from the bitstream buffer + * Input: + byte buffer[] + containing VLC-coded data bits + int totbitoffset + bit offset from start of partition + int bytecount + total bytes in bitstream + int numbits + number of bits to read + * Output: + * Return: + * Attention: + ************************************************************************* + */ + +int get_bits(unsigned char buffer[], int totbitoffset, int *info, int bytecount, + int numbits) +{ + register int inf; + long byteoffset; + int bitoffset; + + int bitcounter = numbits; + + byteoffset = totbitoffset / 8; + bitoffset = 7 - (totbitoffset % 8); + + inf = 0; + while (numbits) { + inf <<= 1; + inf |= (buffer[byteoffset] & (0x01 << bitoffset)) >> bitoffset; + numbits--; + bitoffset--; + if (bitoffset < 0) { + byteoffset++; + bitoffset += 8; + if (byteoffset > bytecount) + return -1; + } + } + + *info = inf; + + + return bitcounter; +} + +/* + ************************************************************************* + * Function:read FLC codeword from UVLC-partition + * Input: + * Output: + * Return: + * Attention: + ************************************************************************* + */ + +int read_syntaxelement_flc(struct syntaxelement *sym) +{ + int frame_bitoffset = curr_stream->frame_bitoffset; + unsigned char *buf = curr_stream->stream_buffer; + int bitstreamlengthinbytes = curr_stream->bitstream_length; + + if ((get_bits(buf, frame_bitoffset, &(sym->inf), bitstreamlengthinbytes, + sym->len)) < 0) + return -1; + + curr_stream->frame_bitoffset += sym->len; + sym->value1 = sym->inf; + +#if TRACE + tracebits2(sym->tracestring, sym->len, sym->inf); +#endif + + return 1; +} + +/* + ************************************************************************* + * Function:ue_v, reads an u(1) syntax element, the length in bits is stored in + the global UsedBits variable + * Input: + tracestring + the string for the trace file + bitstream + the stream to be read from + * Output: + * Return: the value of the coded syntax element + * Attention: + ************************************************************************* + */ +int u_1(char *tracestring) +{ + return u_v(1, tracestring); +} + +/* + ************************************************************************* + * Function:mapping rule for ue(v) syntax elements + * Input:length and info + * Output:number in the code table + * Return: + * Attention: + ************************************************************************* + */ +void linfo_ue(int len, int info, int *value1, int *dummy) +{ + *value1 = (int)pow2(2, (len / 2)) + info - 1; +} + +int u_v(int leninbits, char *tracestring) +{ + struct syntaxelement symbol, *sym = &symbol; + +#ifdef AVSP_LONG_CABAC +#else + assert(curr_stream->stream_buffer != NULL); +#endif + sym->type = SE_HEADER; + sym->mapping = linfo_ue; + sym->len = leninbits; + read_syntaxelement_flc(sym); + + return sym->inf; +} + +/* + ************************************************************************* + * Function:mapping rule for se(v) syntax elements + * Input:length and info + * Output:signed mvd + * Return: + * Attention: + ************************************************************************* + */ + +void linfo_se(int len, int info, int *value1, int *dummy) +{ + int n; + + n = (int)pow2(2, (len / 2)) + info - 1; + *value1 = (n + 1) / 2; + if ((n & 0x01) == 0) + *value1 = -*value1; + +} + +/* + ************************************************************************* + * Function:length and info + * Input: + * Output:cbp (intra) + * Return: + * Attention: + ************************************************************************* + */ + +void linfo_cbp_intra(int len, int info, int *cbp, int *dummy) +{ +} + +const int NCBP[64][2] = {{4, 0}, {16, 19}, {17, 16}, {19, 15}, {14, 18}, + {9, 11}, {22, 31}, {8, 13}, {11, 17}, {21, 30}, {10, 12}, + {7, 9}, {12, 10}, {6, 7}, {5, 8}, {1, 1}, {35, 4}, {47, 42}, { + 48, 38}, {38, 27}, {46, 39}, {36, 33}, {50, 59}, + {26, 26}, {45, 40}, {52, 58}, {41, 35}, {28, 25}, {37, 29}, {23, + 24}, {31, 28}, {2, 3}, {43, 5}, {51, 51}, {56, + 52}, {39, 37}, {55, 50}, {33, 43}, {62, 63}, { + 27, 44}, {54, 53}, {60, 62}, {40, 48}, {32, 47}, + {42, 34}, {24, 45}, {29, 49}, {3, 6}, {49, 14}, {53, 55}, {57, + 56}, {25, 36}, {58, 54}, {30, 41}, {59, 60}, { + 15, 21}, {61, 57}, {63, 61}, {44, 46}, {18, 22}, + {34, 32}, {13, 20}, {20, 23}, {0, 2} }; + +unsigned int s1, t1, value_s, value_t; +unsigned char dec_bypass, dec_final; + +#define get_byte() { \ + dbuffer = dcodestrm[(*dcodestrm_len)++];\ + dbits_to_go = 7; \ +} + +#define dbuffer (dep->dbuffer) +#define dbits_to_go (dep->dbits_to_go) +#define dcodestrm (dep->dcodestrm) +#define dcodestrm_len (dep->dcodestrm_len) + +#define B_BITS 10 + +#define LG_PMPS_SHIFTNO 2 + +#define HALF (1 << (B_BITS-1)) +#define QUARTER (1 << (B_BITS-2)) + +unsigned int biari_decode_symbol(struct decoding_environment_s *dep, + struct bi_context_type_s *bi_ct) +{ + register unsigned char bit; + register unsigned char s_flag; + register unsigned char is_lps = 0; + register unsigned char cwr; + register unsigned char cycno = bi_ct->cycno; + register unsigned int lg_pmps = bi_ct->LG_PMPS; + register unsigned int t_rlps; + register unsigned int s2, t2; + +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & AEC_DUMP) + io_printf("LG_PMPS : %03X, MPS : %d, cycno : %d -- %p\n", + bi_ct->LG_PMPS, bi_ct->MPS, bi_ct->cycno, bi_ct); +#endif + + bit = bi_ct->MPS; + + cwr = (cycno <= 1) ? 3 : (cycno == 2) ? 4 : 5; + + if (t1 >= (lg_pmps >> LG_PMPS_SHIFTNO)) { + s2 = s1; + t2 = t1 - (lg_pmps >> LG_PMPS_SHIFTNO); + s_flag = 0; + } else { + s2 = s1 + 1; + t2 = 256 + t1 - (lg_pmps >> LG_PMPS_SHIFTNO); + s_flag = 1; + } + +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & AEC_DUMP) + io_printf(" s2 : %d, t2 : %03X\n", s2, t2); +#endif + + if (s2 > value_s || (s2 == value_s && value_t >= t2)) { + is_lps = 1; + bit = !bit; + + t_rlps = (s_flag == 0) ? + (lg_pmps >> LG_PMPS_SHIFTNO) : + (t1 + (lg_pmps >> LG_PMPS_SHIFTNO)); + + if (s2 == value_s) + value_t = (value_t - t2); + else { + if (--dbits_to_go < 0) + get_byte(); + + value_t = (value_t << 1) + | ((dbuffer >> dbits_to_go) & 0x01); + value_t = 256 + value_t - t2; + + } + + while (t_rlps < QUARTER) { + t_rlps = t_rlps << 1; + if (--dbits_to_go < 0) + get_byte(); + + value_t = (value_t << 1) + | ((dbuffer >> dbits_to_go) & 0x01); + } + + s1 = 0; + t1 = t_rlps & 0xff; + + value_s = 0; + while (value_t < QUARTER) { + int j; + + if (--dbits_to_go < 0) + get_byte(); + j = (dbuffer >> dbits_to_go) & 0x01; + + value_t = (value_t << 1) | j; + value_s++; + } + value_t = value_t & 0xff; + } else { + + s1 = s2; + t1 = t2; + } + + if (dec_bypass) + return bit; + + if (is_lps) + cycno = (cycno <= 2) ? (cycno + 1) : 3; + else if (cycno == 0) + cycno = 1; + bi_ct->cycno = cycno; + + if (is_lps) { + switch (cwr) { + case 3: + lg_pmps = lg_pmps + 197; + break; + case 4: + lg_pmps = lg_pmps + 95; + break; + default: + lg_pmps = lg_pmps + 46; + } + + if (lg_pmps >= (256 << LG_PMPS_SHIFTNO)) { + lg_pmps = (512 << LG_PMPS_SHIFTNO) - 1 - lg_pmps; + bi_ct->MPS = !(bi_ct->MPS); + } + } else { +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & AEC_DUMP) + io_printf(" - lg_pmps_MPS : %X (%X - %X - %X)\n", + lg_pmps - (unsigned int)(lg_pmps>>cwr) + - (unsigned int)(lg_pmps>>(cwr+2)), + lg_pmps, + (unsigned int)(lg_pmps>>cwr), + (unsigned int)(lg_pmps>>(cwr+2)) + ); +#endif + lg_pmps = lg_pmps - (unsigned int)(lg_pmps >> cwr) + - (unsigned int)(lg_pmps >> (cwr + 2)); + } + + bi_ct->LG_PMPS = lg_pmps; + + return bit; +} + +unsigned int biari_decode_symbolw(struct decoding_environment_s *dep, + struct bi_context_type_s *bi_ct1, + struct bi_context_type_s *bi_ct2) +{ + register unsigned char bit1, bit2; + register unsigned char pred_mps, bit; + register unsigned int lg_pmps; + register unsigned char cwr1, cycno1 = bi_ct1->cycno; + register unsigned char cwr2, cycno2 = bi_ct2->cycno; + register unsigned int lg_pmps1 = bi_ct1->LG_PMPS; + register unsigned int lg_pmps2 = + bi_ct2->LG_PMPS; + register unsigned int t_rlps; + register unsigned char s_flag, is_lps = 0; + register unsigned int s2, t2; + + + bit1 = bi_ct1->MPS; + bit2 = bi_ct2->MPS; + + cwr1 = (cycno1 <= 1) ? 3 : (cycno1 == 2) ? 4 : 5; + cwr2 = (cycno2 <= 1) ? 3 : (cycno2 == 2) ? 4 : 5; + + if (bit1 == bit2) { + pred_mps = bit1; + lg_pmps = (lg_pmps1 + lg_pmps2) / 2; + } else { + if (lg_pmps1 < lg_pmps2) { + pred_mps = bit1; + lg_pmps = (256 << LG_PMPS_SHIFTNO) - 1 + - ((lg_pmps2 - lg_pmps1) >> 1); + } else { + pred_mps = bit2; + lg_pmps = (256 << LG_PMPS_SHIFTNO) - 1 + - ((lg_pmps1 - lg_pmps2) >> 1); + } + } + +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & AEC_DUMP) + io_printf(" - Begin - LG_PMPS : %03X, MPS : %d\n", + lg_pmps, pred_mps); +#endif + if (t1 >= (lg_pmps >> LG_PMPS_SHIFTNO)) { + s2 = s1; + t2 = t1 - (lg_pmps >> LG_PMPS_SHIFTNO); + s_flag = 0; + } else { + s2 = s1 + 1; + t2 = 256 + t1 - (lg_pmps >> LG_PMPS_SHIFTNO); + s_flag = 1; + } + + bit = pred_mps; + if (s2 > value_s || (s2 == value_s && value_t >= t2)) { + is_lps = 1; + bit = !bit; + t_rlps = (s_flag == 0) ? + (lg_pmps >> LG_PMPS_SHIFTNO) : + (t1 + (lg_pmps >> LG_PMPS_SHIFTNO)); + + if (s2 == value_s) + value_t = (value_t - t2); + else { + if (--dbits_to_go < 0) + get_byte(); + + value_t = (value_t << 1) + | ((dbuffer >> dbits_to_go) & 0x01); + value_t = 256 + value_t - t2; + } + + while (t_rlps < QUARTER) { + t_rlps = t_rlps << 1; + if (--dbits_to_go < 0) + get_byte(); + + value_t = (value_t << 1) + | ((dbuffer >> dbits_to_go) & 0x01); + } + s1 = 0; + t1 = t_rlps & 0xff; + + value_s = 0; + while (value_t < QUARTER) { + int j; + + if (--dbits_to_go < 0) + get_byte(); + j = (dbuffer >> dbits_to_go) & 0x01; + + value_t = (value_t << 1) | j; + value_s++; + } + value_t = value_t & 0xff; + } else { + s1 = s2; + t1 = t2; + } + + if (bit != bit1) { + cycno1 = (cycno1 <= 2) ? (cycno1 + 1) : 3; + } else { + if (cycno1 == 0) + cycno1 = 1; + } + + if (bit != bit2) { + cycno2 = (cycno2 <= 2) ? (cycno2 + 1) : 3; + } else { + if (cycno2 == 0) + cycno2 = 1; + } + bi_ct1->cycno = cycno1; + bi_ct2->cycno = cycno2; + + { + + if (bit == bit1) { + lg_pmps1 = + lg_pmps1 + - (unsigned int)(lg_pmps1 + >> cwr1) + - (unsigned int)(lg_pmps1 + >> (cwr1 + + 2)); + } else { + switch (cwr1) { + case 3: + lg_pmps1 = lg_pmps1 + 197; + break; + case 4: + lg_pmps1 = lg_pmps1 + 95; + break; + default: + lg_pmps1 = lg_pmps1 + 46; + } + + if (lg_pmps1 >= (256 << LG_PMPS_SHIFTNO)) { + lg_pmps1 = (512 << LG_PMPS_SHIFTNO) - 1 + - lg_pmps1; + bi_ct1->MPS = !(bi_ct1->MPS); + } + } + bi_ct1->LG_PMPS = lg_pmps1; + + if (bit == bit2) { + lg_pmps2 = + lg_pmps2 + - (unsigned int)(lg_pmps2 + >> cwr2) + - (unsigned int)(lg_pmps2 + >> (cwr2 + + 2)); + } else { + switch (cwr2) { + case 3: + lg_pmps2 = lg_pmps2 + 197; + break; + case 4: + lg_pmps2 = lg_pmps2 + 95; + break; + default: + lg_pmps2 = lg_pmps2 + 46; + } + + if (lg_pmps2 >= (256 << LG_PMPS_SHIFTNO)) { + lg_pmps2 = (512 << LG_PMPS_SHIFTNO) - 1 + - lg_pmps2; + bi_ct2->MPS = !(bi_ct2->MPS); + } + } + bi_ct2->LG_PMPS = lg_pmps2; + } + + + return bit; +} + +/*! + ************************************************************************ + * \brief + * biari_decode_symbol_eq_prob(): + * \return + * the decoded symbol + ************************************************************************ + */ +unsigned int biari_decode_symbol_eq_prob(struct decoding_environment_s *dep) +{ + unsigned char bit; + struct bi_context_type_s octx; + struct bi_context_type_s *ctx = &octx; + + ctx->LG_PMPS = (QUARTER << LG_PMPS_SHIFTNO) - 1; + ctx->MPS = 0; + ctx->cycno = 0xfe; + dec_bypass = 1; + bit = biari_decode_symbol(dep, ctx); + dec_bypass = 0; + return bit; +} + +unsigned int biari_decode_final(struct decoding_environment_s *dep) +{ + unsigned char bit; + struct bi_context_type_s octx; + struct bi_context_type_s *ctx = &octx; + + ctx->LG_PMPS = 1 << LG_PMPS_SHIFTNO; + ctx->MPS = 0; + ctx->cycno = 0xff; + dec_final = 1; + bit = biari_decode_symbol(dep, ctx); + dec_final = 0; + return bit; +} + +int i_8(char *tracestring) +{ + int frame_bitoffset = curr_stream->frame_bitoffset; + unsigned char *buf = curr_stream->stream_buffer; + int bitstreamlengthinbytes = curr_stream->bitstream_length; + struct syntaxelement symbol, *sym = &symbol; +#ifdef AVSP_LONG_CABAC +#else + assert(curr_stream->stream_buffer != NULL); +#endif + + sym->len = 8; + sym->type = SE_HEADER; + sym->mapping = linfo_ue; + + if ((get_bits(buf, frame_bitoffset, &(sym->inf), bitstreamlengthinbytes, + sym->len)) < 0) + return -1; + curr_stream->frame_bitoffset += sym->len; + sym->value1 = sym->inf; + if (sym->inf & 0x80) + sym->inf = -(~((int)0xffffff00 | sym->inf) + 1); +#if TRACE + tracebits2(sym->tracestring, sym->len, sym->inf); +#endif + return sym->inf; +} + +/*! + ************************************************************************ + * \brief + * arideco_bits_read + ************************************************************************ + */ +int arideco_bits_read(struct decoding_environment_s *dep) +{ + + return 8 * ((*dcodestrm_len) - 1) + (8 - dbits_to_go); +} + +/*! + ************************************************************************ + * \brief + * arithmetic decoding + ************************************************************************ + */ +int read_syntaxelement_aec(struct syntaxelement *se, struct img_par *img, + struct datapartition *this_data_part) +{ + int curr_len; + struct decoding_environment_s *dep_dp = &(this_data_part->de_aec); + + curr_len = arideco_bits_read(dep_dp); + + se->reading(se, img, dep_dp); + + se->len = (arideco_bits_read(dep_dp) - curr_len); + return se->len; +} + +/*! + ************************************************************************ + * \brief + * This function is used to arithmetically decode the + * run length info of the skip mb + ************************************************************************ + */ +void readrunlenghtfrombuffer_aec(struct syntaxelement *se, struct img_par *img, + struct decoding_environment_s *dep_dp) +{ + struct bi_context_type_s *pctx; + int ctx, symbol; + + pctx = img->current_slice->tex_ctx->one_contexts[0]; + symbol = 0; + ctx = 0; + while (biari_decode_symbol(dep_dp, pctx + ctx) == 0) { + symbol += 1; + ctx++; + if (ctx >= 3) + ctx = 3; + } + se->value1 = symbol; +#if TRACE + fprintf(p_trace, "@%d%s\t\t\t%d\n", + symbol_count++, se->tracestring, se->value1); + fflush(p_trace); +#endif +} + +/*! + ************************************************************************ + * \brief + * This function is used to arithmetically decode a pair of + * intra prediction modes of a given MB. + ************************************************************************ + */ +int mapd_intrap[5] = {0, 2, 3, 4, 1}; +void read_intrapredmode_aec(struct syntaxelement *se, struct img_par *img, + struct decoding_environment_s *dep_dp) +{ + struct bi_context_type_s *pctx; + int ctx, symbol; + + pctx = img->current_slice->tex_ctx->one_contexts[1]; + symbol = 0; + ctx = 0; +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & AEC_DUMP) + io_printf(" -- read_intrapredmode_aec ctx : %d\n", ctx); +#endif + while (biari_decode_symbol(dep_dp, pctx + ctx) == 0) { + symbol += 1; + ctx++; + if (ctx >= 3) + ctx = 3; +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & AEC_DUMP) + io_printf(" -- read_intrapredmode_aec ctx : %d\n", ctx); +#endif + if (symbol == 4) + break; + } + se->value1 = mapd_intrap[symbol] - 1; + +#if TRACE + fprintf(p_trace, "@%d %s\t\t\t%d\n", + symbol_count++, se->tracestring, se->value1); + fflush(p_trace); +#endif +} + +/*! + ************************************************************************ + * \brief + * decoding of unary binarization using one or 2 distinct + * models for the first and all remaining bins; no terminating + * "0" for max_symbol + *********************************************************************** + */ +unsigned int unary_bin_max_decode(struct decoding_environment_s *dep_dp, + struct bi_context_type_s *ctx, + int ctx_offset, unsigned int max_symbol) +{ + unsigned int l; + unsigned int symbol; + struct bi_context_type_s *ictx; + + symbol = biari_decode_symbol(dep_dp, ctx); + + if (symbol == 0) + return 0; + + if (max_symbol == 1) + return symbol; + symbol = 0; + ictx = ctx + ctx_offset; + do { + l = biari_decode_symbol(dep_dp, ictx); + symbol++; + } while ((l != 0) && (symbol < max_symbol - 1)); + if ((l != 0) && (symbol == max_symbol - 1)) + symbol++; + return symbol; +} + +/*! + ************************************************************************ + * \brief + * decoding of unary binarization using one or 2 distinct + * models for the first and all remaining bins + *********************************************************************** + */ +unsigned int unary_bin_decode(struct decoding_environment_s *dep_dp, + struct bi_context_type_s *ctx, int ctx_offset) +{ + unsigned int l; + unsigned int symbol; + struct bi_context_type_s *ictx; + + symbol = 1 - biari_decode_symbol(dep_dp, ctx); + + if (symbol == 0) + return 0; + symbol = 0; + ictx = ctx + ctx_offset; + do { + l = 1 - biari_decode_symbol(dep_dp, ictx); + symbol++; + } while (l != 0); + return symbol; +} + +/*! + ************************************************************************ + * \brief + * This function is used to arithmetically decode the chroma + * intra prediction mode of a given MB. + ************************************************************************ + */ +void read_cipredmode_aec(struct syntaxelement *se, + struct img_par *img, + struct decoding_environment_s *dep_dp) +{ + struct texture_info_contexts *ctx = img->current_slice->tex_ctx; + struct macroblock *curr_mb = &mb_data[img->current_mb_nr]; + int act_ctx, a, b; + int act_sym = se->value1; + + if (curr_mb->mb_available_up == NULL) + b = 0; + else { + /*if ( (curr_mb->mb_available_up)->mb_type==IPCM) + * b=0; + * else + */ + b = (((curr_mb->mb_available_up)->c_ipred_mode != 0) ? 1 : 0); + } + + if (curr_mb->mb_available_left == NULL) + a = 0; + else { + /* if ( (curr_mb->mb_available_left)->mb_type==IPCM) + * a=0; + * else + */ + a = (((curr_mb->mb_available_left)->c_ipred_mode != 0) ? 1 : 0); + } + + act_ctx = a + b; + + + act_sym = biari_decode_symbol(dep_dp, ctx->cipr_contexts + act_ctx); + + if (act_sym != 0) + act_sym = unary_bin_max_decode(dep_dp, ctx->cipr_contexts + 3, + 0, 2) + 1; + + se->value1 = act_sym; + +#if TRACE + fprintf(p_trace, "@%d %s\t\t%d\n", + symbol_count++, se->tracestring, se->value1); + fflush(p_trace); +#endif + +} + +int slice_header(char *buf, int startcodepos, int length) +{ + int i; + + int weight_para_num = 0; + int mb_row; + int mb_column; + int mb_index; + int mb_width, mb_height; + + mb_column = 0; + + memcpy(curr_stream->stream_buffer, buf, length); + curr_stream->code_len = curr_stream->bitstream_length = length; + + curr_stream->read_len = + curr_stream->frame_bitoffset = (startcodepos) * 8; + slice_vertical_position = u_v(8, "slice vertical position"); + + push_es(slice_vertical_position, 8); + +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & SLICE_INFO_DUMP) + io_printf(" * 8-bits slice_vertical_position : %d\n", + slice_vertical_position); +#endif + + if (vertical_size > 2800) { + slice_vertical_position_extension = u_v(3, + "slice vertical position extension"); + push_es(slice_vertical_position_extension, 3); + + } + + if (vertical_size > 2800) + mb_row = (slice_vertical_position_extension << 7) + + slice_vertical_position; + else + mb_row = slice_vertical_position; + + mb_width = (horizontal_size + 15) / 16; + if (!progressive_sequence) + mb_height = 2 * ((vertical_size + 31) / 32); + else + mb_height = (vertical_size + 15) / 16; + + + mb_index = mb_row * mb_width + mb_column; + + if (!img->picture_structure && img->type == I_IMG + && (mb_index >= mb_width * mb_height / 2)) { + second_ifield = 1; + img->type = P_IMG; + pre_img_type = P_IMG; + } + + { + if (!fixed_picture_qp) { + fixed_slice_qp = u_v(1, "fixed_slice_qp"); + push_es(fixed_slice_qp, 1); +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & SLICE_INFO_DUMP) + io_printf(" * 1-bit fixed_slice_qp : %d\n", + fixed_slice_qp); +#endif + slice_qp = u_v(6, "slice_qp"); + push_es(slice_qp, 6); +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & SLICE_INFO_DUMP) + io_printf(" * 6-bits slice_qp : %d\n", + slice_qp); +#endif + + img->qp = slice_qp; + } + + if (img->type != I_IMG) { + img->slice_weighting_flag = u_v(1, + "slice weighting flag"); + + if (img->slice_weighting_flag) { + + if (second_ifield && !img->picture_structure) + weight_para_num = 1; + else if (img->type == P_IMG + && img->picture_structure) + weight_para_num = 2; + else if (img->type == P_IMG + && !img->picture_structure) + weight_para_num = 4; + else if (img->type == B_IMG + && img->picture_structure) + weight_para_num = 2; + else if (img->type == B_IMG + && !img->picture_structure) + weight_para_num = 4; + +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & SLICE_INFO_DUMP) + io_printf(" - weight_para_num : %d\n", + weight_para_num); +#endif + for (i = 0; i < weight_para_num; i++) { + img->lum_scale[i] = u_v(8, + "luma scale"); + + img->lum_shift[i] = i_8("luma shift"); + + marker_bit = u_1("insert bit"); + + + { + img->chroma_scale[i] = u_v(8, + "chroma scale"); + + img->chroma_shift[i] = i_8( + "chroma shift"); + + marker_bit = u_1("insert bit"); + + } + } + img->mb_weighting_flag = u_v(1, + "MB weighting flag"); + + } + } + } + + +#if 1 + return mb_index; +#endif +} + +void no_mem_exit(char *where) +{ + io_printf("%s\r\n", where); +} + +unsigned char bit[8] = {0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01}; + +struct inputstream_s { + /*FILE *f;*/ + unsigned char buf[SVA_STREAM_BUF_SIZE]; + unsigned int uclear_bits; + unsigned int upre_3bytes; + int ibyte_position; + int ibuf_bytesnum; + int iclear_bitsnum; + int istuff_bitsnum; + int ibits_count; +}; + +struct inputstream_s IRABS; +struct inputstream_s *p_irabs = &IRABS; + +struct stat_bits { + int curr_frame_bits; + int prev_frame_bits; + int emulate_bits; + int prev_emulate_bits; + int last_unit_bits; + int bitrate; + int total_bitrate[1000]; + int coded_pic_num; + int time_s; +}; + +struct stat_bits *stat_bits_ptr; + +unsigned char *temp_slice_buf; +int start_codeposition; +int first_slice_length; +int first_slice_startpos; + +int bitstream_buf_used; +int startcode_offset; + +int bitstream_read_ptr; + +int demulate_enable; + +int last_dquant; + +int total_mb_count; + +int current_mb_skip; + +int skip_mode_flag; + +int current_mb_intra; + +/* + ************************************************************************* + * Function: Check start code's type + * Input: + * Output: + * Return: + * Author: XZHENG, 20080515 + ************************************************************************* + */ +void check_type(int startcode) +{ + startcode = startcode & 0x000000ff; + switch (startcode) { + case 0xb0: + case 0xb2: + case 0xb5: + demulate_enable = 0; + break; + default: + demulate_enable = 1; + break; + } + +} +/* + ************************************************************************* + * Function: + * Input: + * Output: + * Return: 0 : OK + -1 : arrive at stream end + -2 : meet another start code + * Attention: + ************************************************************************* + */ +int clear_nextbyte(struct inputstream_s *p) +{ + int i, k, j; + unsigned char temp[3]; + + i = p->ibyte_position; + k = p->ibuf_bytesnum - i; + if (k < 3) { + for (j = 0; j < k; j++) + temp[j] = p->buf[i + j]; + + p->ibuf_bytesnum = read_bitstream(p->buf + k, + SVA_STREAM_BUF_SIZE - k); + bitstream_buf_used++; + if (p->ibuf_bytesnum == 0) { + if (k > 0) { + while (k > 0) { + p->upre_3bytes = ((p->upre_3bytes << 8) + | p->buf[i]) + & 0x00ffffff; + if (p->upre_3bytes < 4 + && demulate_enable) { + p->uclear_bits = + (p->uclear_bits + << 6) + | (p->buf[i] + >> 2); + p->iclear_bitsnum += 6; + stat_bits_ptr->emulate_bits + += 2; + } else { + p->uclear_bits = (p->uclear_bits + << 8) + | p->buf[i]; + p->iclear_bitsnum += 8; + } + p->ibyte_position++; + k--; + i++; + } + return 0; + } else { + return -1; + } + } else { + for (j = 0; j < k; j++) + p->buf[j] = temp[j]; + p->ibuf_bytesnum += k; + i = p->ibyte_position = 0; + } + } + if (p->buf[i] == 0 && p->buf[i + 1] == 0 && p->buf[i + 2] == 1) + return -2; + p->upre_3bytes = ((p->upre_3bytes << 8) | p->buf[i]) & 0x00ffffff; + if (p->upre_3bytes < 4 && demulate_enable) { + p->uclear_bits = (p->uclear_bits << 6) | (p->buf[i] >> 2); + p->iclear_bitsnum += 6; + stat_bits_ptr->emulate_bits += 2; + } else { + p->uclear_bits = (p->uclear_bits << 8) | p->buf[i]; + p->iclear_bitsnum += 8; + } + p->ibyte_position++; + return 0; +} + +/* + ************************************************************************* + * Function: + * Input: + * Output: + * Return: 0 : OK + -1 : arrive at stream end + -2 : meet another start code + * Attention: + ************************************************************************* + */ +int read_n_bit(struct inputstream_s *p, int n, int *v) +{ + int r; + unsigned int t; + + while (n > p->iclear_bitsnum) { + r = clear_nextbyte(p); + if (r) { + if (r == -1) { + if (p->ibuf_bytesnum - p->ibyte_position > 0) + break; + } + return r; + } + } + t = p->uclear_bits; + r = 32 - p->iclear_bitsnum; + *v = (t << r) >> (32 - n); + p->iclear_bitsnum -= n; + return 0; +} + +#ifdef AVSP_LONG_CABAC +unsigned char TMP_BUF[2 * SVA_STREAM_BUF_SIZE]; +int tmp_buf_wr_ptr; +int tmp_buf_rd_ptr; +int tmp_buf_count; +#endif +void open_irabs(struct inputstream_s *p) +{ + p->uclear_bits = 0xffffffff; + p->ibyte_position = 0; + p->ibuf_bytesnum = 0; + p->iclear_bitsnum = 0; + p->istuff_bitsnum = 0; + p->ibits_count = 0; + p->upre_3bytes = 0; + + bitstream_buf_used = 0; + bitstream_read_ptr = (src_start - 16) & 0xfffffff0; + +#ifdef AVSP_LONG_CABAC + tmp_buf_count = 0; + tmp_buf_wr_ptr = 0; + tmp_buf_rd_ptr = 0; +#endif + +} + +void move_bitstream(unsigned int move_from_addr, unsigned int move_to_addr, + int move_size) +{ + int move_bytes_left = move_size; + unsigned int move_read_addr; + unsigned int move_write_addr = move_to_addr; + + int move_byte; + unsigned int data32; + + while (move_from_addr > vld_mem_end_addr) { + move_from_addr = move_from_addr + vld_mem_start_addr + - vld_mem_end_addr - 8; + } + move_read_addr = move_from_addr; + while (move_bytes_left > 0) { + move_byte = move_bytes_left; + if (move_byte > 512) + move_byte = 512; + if ((move_read_addr + move_byte) > vld_mem_end_addr) + move_byte = (vld_mem_end_addr + 8) - move_read_addr; + + WRITE_VREG(LMEM_DMA_ADR, move_read_addr); + WRITE_VREG(LMEM_DMA_COUNT, move_byte / 2); + WRITE_VREG(LMEM_DMA_CTRL, 0xc200); + + data32 = 0x8000; + while (data32 & 0x8000) + data32 = READ_VREG(LMEM_DMA_CTRL); + + WRITE_VREG(LMEM_DMA_ADR, move_write_addr); + WRITE_VREG(LMEM_DMA_COUNT, move_byte / 2); + WRITE_VREG(LMEM_DMA_CTRL, 0x8200); + + data32 = 0x8000; + while (data32 & 0x8000) + data32 = READ_VREG(LMEM_DMA_CTRL); + + data32 = 0x0fff; + while (data32 & 0x0fff) + data32 = READ_VREG(WRRSP_LMEM); + +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & STREAM_INFO_DUMP) + io_printf(" 2 MOVE %d Bytes from 0x%x to 0x%x\n", + move_byte, move_read_addr, move_write_addr); +#endif + + move_read_addr = move_read_addr + move_byte; + if (move_read_addr > vld_mem_end_addr) + move_read_addr = vld_mem_start_addr; + move_write_addr = move_write_addr + move_byte; + move_bytes_left = move_bytes_left - move_byte; + } + +} + +int read_bitstream(unsigned char *buf, int size) +{ + int i; + +#ifdef AVSP_LONG_CABAC + + unsigned int *TMP_BUF_32 = (unsigned int *)bitstream_read_tmp; + + if (tmp_buf_count < size) { + dma_sync_single_for_cpu(amports_get_dma_device(), + bitstream_read_tmp_phy, SVA_STREAM_BUF_SIZE, + DMA_FROM_DEVICE); + + move_bitstream(bitstream_read_ptr, bitstream_read_tmp_phy, + SVA_STREAM_BUF_SIZE); + + for (i = 0; i < SVA_STREAM_BUF_SIZE / 8; i++) { + TMP_BUF[tmp_buf_wr_ptr++] = + (TMP_BUF_32[2 * i + 1] >> 24) & 0xff; + if (tmp_buf_wr_ptr >= (2 * SVA_STREAM_BUF_SIZE)) + tmp_buf_wr_ptr = 0; + TMP_BUF[tmp_buf_wr_ptr++] = + (TMP_BUF_32[2 * i + 1] >> 16) & 0xff; + if (tmp_buf_wr_ptr >= (2 * SVA_STREAM_BUF_SIZE)) + tmp_buf_wr_ptr = 0; + TMP_BUF[tmp_buf_wr_ptr++] = (TMP_BUF_32[2 * i + 1] >> 8) + & 0xff; + if (tmp_buf_wr_ptr >= (2 * SVA_STREAM_BUF_SIZE)) + tmp_buf_wr_ptr = 0; + TMP_BUF[tmp_buf_wr_ptr++] = (TMP_BUF_32[2 * i + 1] >> 0) + & 0xff; + if (tmp_buf_wr_ptr >= (2 * SVA_STREAM_BUF_SIZE)) + tmp_buf_wr_ptr = 0; + TMP_BUF[tmp_buf_wr_ptr++] = + (TMP_BUF_32[2 * i + 0] >> 24) & 0xff; + if (tmp_buf_wr_ptr >= (2 * SVA_STREAM_BUF_SIZE)) + tmp_buf_wr_ptr = 0; + TMP_BUF[tmp_buf_wr_ptr++] = + (TMP_BUF_32[2 * i + 0] >> 16) & 0xff; + if (tmp_buf_wr_ptr >= (2 * SVA_STREAM_BUF_SIZE)) + tmp_buf_wr_ptr = 0; + TMP_BUF[tmp_buf_wr_ptr++] = (TMP_BUF_32[2 * i + 0] >> 8) + & 0xff; + if (tmp_buf_wr_ptr >= (2 * SVA_STREAM_BUF_SIZE)) + tmp_buf_wr_ptr = 0; + TMP_BUF[tmp_buf_wr_ptr++] = (TMP_BUF_32[2 * i + 0] >> 0) + & 0xff; + if (tmp_buf_wr_ptr >= (2 * SVA_STREAM_BUF_SIZE)) + tmp_buf_wr_ptr = 0; + } + tmp_buf_count = tmp_buf_count + SVA_STREAM_BUF_SIZE; + bitstream_read_ptr = bitstream_read_ptr + SVA_STREAM_BUF_SIZE; + } + +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & STREAM_INFO_DUMP) + io_printf(" Read %d bytes from %d, size left : %d\n", + size, tmp_buf_rd_ptr, tmp_buf_count); +#endif + for (i = 0; i < size; i++) { + buf[i] = TMP_BUF[tmp_buf_rd_ptr++]; + if (tmp_buf_rd_ptr >= (2 * SVA_STREAM_BUF_SIZE)) + tmp_buf_rd_ptr = 0; + } + tmp_buf_count = tmp_buf_count - size; + +#else + for (i = 0; i < size; i++) + buf[i] = tmp_stream[bitstream_read_ptr + i]; + bitstream_read_ptr = bitstream_read_ptr + size; +#endif + + return size; +} + +int next_startcode(struct inputstream_s *p) +{ + int i, m; + unsigned char a = 0, b = 0; + + m = 0; + + while (1) { + if (p->ibyte_position >= p->ibuf_bytesnum - 2) { + m = p->ibuf_bytesnum - p->ibyte_position; + if (m < 0) + return -2; + if (m == 1) + b = p->buf[p->ibyte_position + 1]; + if (m == 2) { + b = p->buf[p->ibyte_position + 1]; + a = p->buf[p->ibyte_position]; + } + p->ibuf_bytesnum = read_bitstream(p->buf, + SVA_STREAM_BUF_SIZE); + p->ibyte_position = 0; + bitstream_buf_used++; + } + + if (p->ibuf_bytesnum + m < 3) + return -1; + + if (m == 1 && b == 0 && p->buf[0] == 0 && p->buf[1] == 1) { + p->ibyte_position = 2; + p->iclear_bitsnum = 0; + p->istuff_bitsnum = 0; + p->ibits_count += 24; + p->upre_3bytes = 1; + return 0; + } + + if (m == 2 && b == 0 && a == 0 && p->buf[0] == 1) { + p->ibyte_position = 1; + p->iclear_bitsnum = 0; + p->istuff_bitsnum = 0; + p->ibits_count += 24; + p->upre_3bytes = 1; + return 0; + } + + if (m == 2 && b == 0 && p->buf[0] == 0 && p->buf[1] == 1) { + p->ibyte_position = 2; + p->iclear_bitsnum = 0; + p->istuff_bitsnum = 0; + p->ibits_count += 24; + p->upre_3bytes = 1; + return 0; + } + + for (i = p->ibyte_position; i < p->ibuf_bytesnum - 2; i++) { + if (p->buf[i] == 0 && p->buf[i + 1] == 0 + && p->buf[i + 2] == 1) { + p->ibyte_position = i + 3; + p->iclear_bitsnum = 0; + p->istuff_bitsnum = 0; + p->ibits_count += 24; + p->upre_3bytes = 1; + return 0; + } + p->ibits_count += 8; + } + p->ibyte_position = i; + } +} + +int get_oneunit(char *buf, int *startcodepos, int *length) +{ + int i, j, k; + + i = next_startcode(p_irabs); + + if (i != 0) { + if (i == -1) + io_printf( + "\narrive at stream end and start code is not found!"); + if (i == -2) + io_printf("\np->ibyte_position error!"); + + } + startcode_offset = + p_irabs->ibyte_position + - 3 + (bitstream_buf_used-1) + * SVA_STREAM_BUF_SIZE; + buf[0] = 0; + buf[1] = 0; + buf[2] = 1; + *startcodepos = 3; + i = read_n_bit(p_irabs, 8, &j); + buf[3] = (char)j; + + check_type(buf[3]); + if (buf[3] == SEQUENCE_END_CODE) { + *length = 4; + return -1; + } + k = 4; + while (1) { + i = read_n_bit(p_irabs, 8, &j); + if (i < 0) + break; + buf[k++] = (char)j; + if (k >= (MAX_CODED_FRAME_SIZE - 1)) + break; + } + if (p_irabs->iclear_bitsnum > 0) { + int shift; + + shift = 8 - p_irabs->iclear_bitsnum; + i = read_n_bit(p_irabs, p_irabs->iclear_bitsnum, &j); + + if (j != 0) + buf[k++] = (char)(j << shift); + stat_bits_ptr->last_unit_bits += shift; + } + *length = k; + return k; +} + +/*unsigned char tmp_buf[MAX_CODED_FRAME_SIZE] __attribute__ ((aligned(64)));*/ +/*unsigned char tmp_buf[MAX_CODED_FRAME_SIZE] __aligned(64);*/ +int header(void) +{ + unsigned char *buf; + int startcodepos, length; + + unsigned char *tmp_buf; + + tmp_buf = (unsigned char *)avsp_heap_adr; + + buf = &tmp_buf[0]; + while (1) { + start_codeposition = get_oneunit(buf, &startcodepos, &length); + + switch (buf[startcodepos]) { + case SEQUENCE_HEADER_CODE: + io_printf( + "# SEQUENCE_HEADER_CODE (0x%02x) found at offset %d (0x%x)\n", + buf[startcodepos], startcode_offset, + startcode_offset); + break; + case EXTENSION_START_CODE: + io_printf( + "# EXTENSION_START_CODE (0x%02x) found at offset %d (0x%x)\n", + buf[startcodepos], startcode_offset, + startcode_offset); + break; + case USER_DATA_START_CODE: + io_printf( + "# USER_DATA_START_CODE (0x%02x) found at offset %d (0x%x)\n", + buf[startcodepos], startcode_offset, + startcode_offset); + break; + case VIDEO_EDIT_CODE: + io_printf( + "# VIDEO_EDIT_CODE (0x%02x) found at offset %d (0x%x)\n", + buf[startcodepos], startcode_offset, + startcode_offset); + break; + case I_PICTURE_START_CODE: + io_printf( + "# I_PICTURE_START_CODE (0x%02x) found at offset %d (0x%x)\n", + buf[startcodepos], startcode_offset, + startcode_offset); + break; + case PB_PICTURE_START_CODE: + io_printf( + "# PB_PICTURE_START_CODE (0x%02x) found at offset %d (0x%x)\n", + buf[startcodepos], startcode_offset, + startcode_offset); + break; + case SEQUENCE_END_CODE: + io_printf( + "# SEQUENCE_END_CODE (0x%02x) found at offset %d (0x%x)\n", + buf[startcodepos], startcode_offset, + startcode_offset); + break; + default: + io_printf( + "# SLICE_START_CODE (0x%02x) found at offset %d (0x%x)\n", + buf[startcodepos], startcode_offset, + startcode_offset); +#if 0 + io_printf("VLD_MEM_VIFIFO_START_PTR %x\r\n", + READ_VREG(VLD_MEM_VIFIFO_START_PTR)); + io_printf("VLD_MEM_VIFIFO_CURR_PTR %x\r\n", + READ_VREG(VLD_MEM_VIFIFO_CURR_PTR)); + io_printf("VLD_MEM_VIFIFO_END_PTR %x\r\n", + READ_VREG(VLD_MEM_VIFIFO_END_PTR)); + io_printf("VLD_MEM_VIFIFO_WP %x\r\n" + READ_VREG(VLD_MEM_VIFIFO_WP)); + io_printf("VLD_MEM_VIFIFO_RP %x\r\n", + READ_VREG(VLD_MEM_VIFIFO_RP)); + io_printf("VLD_MEM_VBUF_RD_PTR %x\r\n" + READ_VREG(VLD_MEM_VBUF_RD_PTR)); + io_printf("VLD_MEM_VIFIFO_BUF_CNTL %x\r\n", + READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL)); + io_printf("PARSER_VIDEO_HOLE %x\r\n", + READ_MPEG_REG(PARSER_VIDEO_HOLE)); +#endif + if ((buf[startcodepos] >= SLICE_START_CODE_MIN + && buf[startcodepos] + <= SLICE_START_CODE_MAX) + && ((!img->seq_header_indicate) + || (img->type == B_IMG + && img->b_discard_flag + == 1 + && !img->no_forward_reference))) { + break; + } else if (buf[startcodepos] >= SLICE_START_CODE_MIN) { + + first_slice_length = length; + first_slice_startpos = startcodepos; + + temp_slice_buf = &tmp_buf[0]; + return SOP; + } else { + io_printf("Can't find start code"); + return -EOS; + } + } + } + +} + +/* + ************************************************************************* + * Function:Allocates a Bitstream + * Input: + * Output:allocated Bitstream point + * Return: + * Attention: + ************************************************************************* + */ +struct bitstream_s *alloc_bitstream(void) +{ + struct bitstream_s *bitstream; + + bitstream = (struct bitstream_s *)local_alloc(1, + sizeof(struct bitstream_s)); + if (bitstream == NULL) { + io_printf( + "AllocBitstream: Memory allocation for Bitstream failed"); + return NULL; + } + bitstream->stream_buffer = (unsigned char *)local_alloc( + MAX_CODED_FRAME_SIZE, + sizeof(unsigned char)); + if (bitstream->stream_buffer == NULL) { + io_printf( + "AllocBitstream: Memory allocation for streamBuffer failed"); + return NULL; + } + + return bitstream; +} + +void biari_init_context_logac(struct bi_context_type_s *ctx) +{ + ctx->LG_PMPS = (QUARTER << LG_PMPS_SHIFTNO) - 1; + ctx->MPS = 0; + ctx->cycno = 0; +} + +#define BIARI_CTX_INIT1_LOG(jj, ctx)\ +{\ + for (j = 0; j < jj; j++)\ + biari_init_context_logac(&(ctx[j]));\ +} + +#define BIARI_CTX_INIT2_LOG(ii, jj, ctx)\ +{\ + for (i = 0; i < ii; i++)\ + for (j = 0; j < jj; j++)\ + biari_init_context_logac(&(ctx[i][j]));\ +} + +#define BIARI_CTX_INIT3_LOG(ii, jj, kk, ctx)\ +{\ + for (i = 0; i < ii; i++)\ + for (j = 0; j < jj; j++)\ + for (k = 0; k < kk; k++)\ + biari_init_context_logac(&(ctx[i][j][k]));\ +} + +#define BIARI_CTX_INIT4_LOG(ii, jj, kk, ll, ctx)\ +{\ + for (i = 0; i < ii; i++)\ + for (j = 0; j < jj; j++)\ + for (k = 0; k < kk; k++)\ + for (l = 0; l < ll; l++)\ + biari_init_context_logac\ + (&(ctx[i][j][k][l]));\ +} + +void init_contexts(struct img_par *img) +{ + struct motion_info_contexts_s *mc = img->current_slice->mot_ctx; + struct texture_info_contexts *tc = img->current_slice->tex_ctx; + int i, j; + +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & SLICE_INFO_DUMP) + io_printf(" ---- init_contexts ----\n"); +#endif + + BIARI_CTX_INIT2_LOG(3, NUM_MB_TYPE_CTX, mc->mb_type_contexts); + BIARI_CTX_INIT2_LOG(2, NUM_B8_TYPE_CTX, mc->b8_type_contexts); + BIARI_CTX_INIT2_LOG(2, NUM_MV_RES_CTX, mc->mv_res_contexts); + BIARI_CTX_INIT2_LOG(2, NUM_REF_NO_CTX, mc->ref_no_contexts); + BIARI_CTX_INIT1_LOG(NUM_DELTA_QP_CTX, mc->delta_qp_contexts); + BIARI_CTX_INIT1_LOG(NUM_MB_AFF_CTX, mc->mb_aff_contexts); + + BIARI_CTX_INIT1_LOG(NUM_IPR_CTX, tc->ipr_contexts); + BIARI_CTX_INIT1_LOG(NUM_CIPR_CTX, tc->cipr_contexts); + BIARI_CTX_INIT2_LOG(3, NUM_CBP_CTX, tc->cbp_contexts); + BIARI_CTX_INIT2_LOG(NUM_BLOCK_TYPES, NUM_BCBP_CTX, tc->bcbp_contexts); + BIARI_CTX_INIT2_LOG(NUM_BLOCK_TYPES, NUM_ONE_CTX, tc->one_contexts); + BIARI_CTX_INIT2_LOG(NUM_BLOCK_TYPES, NUM_ABS_CTX, tc->abs_contexts); + BIARI_CTX_INIT2_LOG(NUM_BLOCK_TYPES, NUM_MAP_CTX, tc->fld_map_contexts); + BIARI_CTX_INIT2_LOG(NUM_BLOCK_TYPES, NUM_LAST_CTX, + tc->fld_last_contexts); + BIARI_CTX_INIT2_LOG(NUM_BLOCK_TYPES, NUM_MAP_CTX, tc->map_contexts); + BIARI_CTX_INIT2_LOG(NUM_BLOCK_TYPES, NUM_LAST_CTX, tc->last_contexts); +#ifdef TEST_WEIGHTING_AEC + biari_init_context_logac(&mc->mb_weighting_pred); +#endif +} + +/*! + ************************************************************************ + * \brief + * Allocation of contexts models for the motion info + * used for arithmetic decoding + * + ************************************************************************ + */ +struct motion_info_contexts_s *create_contexts_motioninfo(void) +{ + struct motion_info_contexts_s *deco_ctx; + + deco_ctx = (struct motion_info_contexts_s *)local_alloc(1, + sizeof(struct motion_info_contexts_s)); + if (deco_ctx == NULL) + no_mem_exit("create_contexts_motioninfo: deco_ctx"); + + return deco_ctx; +} + +/*! + ************************************************************************ + * \brief + * Allocates of contexts models for the texture info + * used for arithmetic decoding + ************************************************************************ + */ +struct texture_info_contexts *create_contexts_textureinfo(void) +{ + struct texture_info_contexts *deco_ctx; + + deco_ctx = (struct texture_info_contexts *)local_alloc(1, + sizeof(struct texture_info_contexts)); + if (deco_ctx == NULL) + no_mem_exit("create_contexts_textureinfo: deco_ctx"); + + return deco_ctx; +} + +struct datapartition *alloc_partition(int n) +{ + struct datapartition *part_arr, *datapart; + int i; + + part_arr = + (struct datapartition *)local_alloc(n, sizeof(struct datapartition)); + if (part_arr == NULL) { + no_mem_exit( + "alloc_partition: Memory allocation for Data Partition failed"); + return NULL; + } + +#if LIWR_FIX + part_arr[0].bitstream = NULL; +#else + for (i = 0; i < n; i++) { + datapart = &(part_arr[i]); + datapart->bitstream = (struct bitstream_s *)local_alloc(1, + sizeof(struct bitstream_s)); + if (datapart->bitstream == NULL) { + no_mem_exit( + "alloc_partition: Memory allocation for Bitstream failed"); + return NULL; + } + } +#endif + return part_arr; +} + +int malloc_slice(struct img_par *img) +{ + struct slice_s *currslice; + + img->current_slice = + (struct slice_s *)local_alloc(1, sizeof(struct slice_s)); + currslice = img->current_slice; + if (currslice == NULL) { + no_mem_exit( + "Memory allocation for struct slice_s datastruct Failed" + ); + return 0; + } + if (1) { + + currslice->mot_ctx = create_contexts_motioninfo(); + if (currslice->mot_ctx == NULL) + return 0; + + currslice->tex_ctx = create_contexts_textureinfo(); + if (currslice->tex_ctx == NULL) + return 0; + } +#if LIWR_FIX + currslice->max_part_nr = 1; +#else + currslice->max_part_nr = 3; +#endif + currslice->part_arr = alloc_partition(currslice->max_part_nr); + if (currslice->part_arr == NULL) + return 0; + return 1; +} + +void init(struct img_par *img) +{ + int i; + + for (i = 0; i < 256; i++) + img->quad[i] = i * i; +} + +/* + ************************************************************************* + * Function:Allocate 2D memory array -> int array2D[rows][columns] + * Input: + * Output: memory size in bytes + * Return: + * Attention: + ************************************************************************* + */ + +int get_mem2Dint(int ***array2D, int rows, int columns) +{ + int i; + + *array2D = (int **)local_alloc(rows, sizeof(int *)); + if (*array2D == NULL) { + no_mem_exit("get_mem2Dint: array2D"); + return -1; + } + (*array2D)[0] = (int *)local_alloc(rows * columns, sizeof(int)); + if ((*array2D)[0] == NULL) { + no_mem_exit("get_mem2Dint: array2D"); + return -1; + } + + for (i = 1; i < rows; i++) + (*array2D)[i] = (*array2D)[i - 1] + columns; + + return rows * columns * sizeof(int); +} + +int initial_decode(void) +{ + int i, j; + int ret; + int img_height = (vertical_size + img->auto_crop_bottom); + int memory_size = 0; + + ret = malloc_slice(img); + if (ret == 0) + return 0; + + mb_data = (struct macroblock *)local_alloc( + (img->width / MB_BLOCK_SIZE) + * (img_height /*vertical_size*/ + / MB_BLOCK_SIZE), sizeof(struct macroblock)); + if (mb_data == NULL) { + no_mem_exit("init_global_buffers: mb_data"); + return 0; + } + + if (progressive_sequence) { + int size; + size = get_mem2Dint(&(img->ipredmode), + img->width / B8_SIZE * 2 + 4, + vertical_size / B8_SIZE * 2 + 4); + if (size == -1) + return 0; + + memory_size += size; + } else { + int size; + size = get_mem2Dint(&(img->ipredmode), + img->width / B8_SIZE * 2 + 4, + (vertical_size + 32) / (2 * B8_SIZE) * 4 + 4); + if (size == -1) + return 0; + + memory_size += size; + } + + for (i = 0; i < img->width / (B8_SIZE) * 2 + 4; i++) { + for (j = 0; j < img->height / (B8_SIZE) * 2 + 4; j++) + img->ipredmode[i][j] = -1; + } + + init(img); + img->number = 0; + img->type = I_IMG; + img->imgtr_last_p = 0; + img->imgtr_next_p = 0; + + img->new_seq_header_flag = 1; + img->new_sequence_flag = 1; + + return 1; +} + +void aec_new_slice(void) +{ + last_dquant = 0; +} + +/*! + ************************************************************************ + * \brief + * Initializes the DecodingEnvironment for the arithmetic coder + ************************************************************************ + */ + +void arideco_start_decoding(struct decoding_environment_s *dep, + unsigned char *cpixcode, + int firstbyte, int *cpixcode_len, int slice_type) +{ + + dcodestrm = cpixcode; + dcodestrm_len = cpixcode_len; + *dcodestrm_len = firstbyte; + + s1 = 0; + t1 = QUARTER - 1; + value_s = 0; + + value_t = 0; + + { + int i; + + dbits_to_go = 0; + for (i = 0; i < B_BITS - 1; i++) { + if (--dbits_to_go < 0) + get_byte(); + + value_t = (value_t << 1) + | ((dbuffer >> dbits_to_go) & 0x01); + } + } + + while (value_t < QUARTER) { + if (--dbits_to_go < 0) + get_byte(); + + value_t = (value_t << 1) | ((dbuffer >> dbits_to_go) & 0x01); + value_s++; + } + value_t = value_t & 0xff; + + dec_final = dec_bypass = 0; + + + +} + +/* + ************************************************************************* + * Function:Checks the availability of neighboring macroblocks of + the current macroblock for prediction and context determination; + marks the unavailable MBs for intra prediction in the + ipredmode-array by -1. Only neighboring MBs in the causal + past of the current MB are checked. + * Input: + * Output: + * Return: + * Attention: + ************************************************************************* + */ + +void checkavailabilityofneighbors(struct img_par *img) +{ + int i, j; + const int mb_width = img->width / MB_BLOCK_SIZE; + const int mb_nr = img->current_mb_nr; + struct macroblock *curr_mb = &mb_data[mb_nr]; + int check_value; + int remove_prediction; + + curr_mb->mb_available_up = NULL; + curr_mb->mb_available_left = NULL; + + for (i = 0; i < 3; i++) + for (j = 0; j < 3; j++) + mb_data[mb_nr].mb_available[i][j] = NULL; + + mb_data[mb_nr].mb_available[1][1] = curr_mb; + + if (img->pix_x >= MB_BLOCK_SIZE) { + remove_prediction = curr_mb->slice_nr + != mb_data[mb_nr - 1].slice_nr; + + if (remove_prediction) + + { + + img->ipredmode[(img->block_x + 1) * 2 - 1][(img->block_y + + 1) * 2] = -1; + img->ipredmode[(img->block_x + 1) * 2 - 1][(img->block_y + + 1) * 2 + 1] = -1; + img->ipredmode[(img->block_x + 1) * 2 - 1][(img->block_y + + 2) * 2] = -1; + img->ipredmode[(img->block_x + 1) * 2 - 1][(img->block_y + + 2) * 2 + 1] = -1; + } + if (!remove_prediction) + curr_mb->mb_available[1][0] = &(mb_data[mb_nr - 1]); + + } + + check_value = (img->pix_y >= MB_BLOCK_SIZE); + if (check_value) { + remove_prediction = curr_mb->slice_nr + != mb_data[mb_nr - mb_width].slice_nr; + + if (remove_prediction) { + img->ipredmode + [(img->block_x + 1) * 2][(img->block_y + 1) + * 2 - 1] = -1; + img->ipredmode[(img->block_x + 1) * 2 + 1][(img->block_y + + 1) * 2 - 1] = -1; + img->ipredmode[(img->block_x + 1) * 2 + 2][(img->block_y + + 1) * 2 - 1] = -1; + img->ipredmode[(img->block_x + 1) * 2 + 3][(img->block_y + + 1) * 2 - 1] = -1; + } + + if (!remove_prediction) { + curr_mb->mb_available[0][1] = + &(mb_data[mb_nr - mb_width]); + } + } + + if (img->pix_y >= MB_BLOCK_SIZE && img->pix_x >= MB_BLOCK_SIZE) { + remove_prediction = curr_mb->slice_nr + != mb_data[mb_nr - mb_width - 1].slice_nr; + + if (remove_prediction) { + img->ipredmode[img->block_x * 2 + 1][img->block_y * 2 + + 1] = -1; + } + if (!remove_prediction) { + curr_mb->mb_available[0][0] = &(mb_data[mb_nr - mb_width + - 1]); + } + } + + if (img->pix_y >= MB_BLOCK_SIZE + && img->pix_x < (img->width - MB_BLOCK_SIZE)) { + if (curr_mb->slice_nr == mb_data[mb_nr - mb_width + 1].slice_nr) + curr_mb->mb_available[0][2] = &(mb_data[mb_nr - mb_width + + 1]); + } + + if (1) { + curr_mb->mbaddr_a = mb_nr - 1; + curr_mb->mbaddr_b = mb_nr - img->pic_width_inmbs; + curr_mb->mbaddr_c = mb_nr - img->pic_width_inmbs + 1; + curr_mb->mbaddr_d = mb_nr - img->pic_width_inmbs - 1; + + curr_mb->mbavail_a = + (curr_mb->mb_available[1][0] != NULL) ? 1 : 0; + curr_mb->mbavail_b = + (curr_mb->mb_available[0][1] != NULL) ? 1 : 0; + curr_mb->mbavail_c = + (curr_mb->mb_available[0][2] != NULL) ? 1 : 0; + curr_mb->mbavail_d = + (curr_mb->mb_available[0][0] != NULL) ? 1 : 0; + + } + +} + +void checkavailabilityofneighborsaec(void) +{ + + int i, j; + const int mb_width = img->width / MB_BLOCK_SIZE; + const int mb_nr = img->current_mb_nr; + struct macroblock *curr_mb = &(mb_data[mb_nr]); + int check_value; + + for (i = 0; i < 3; i++) + for (j = 0; j < 3; j++) + mb_data[mb_nr].mb_available[i][j] = NULL; + mb_data[mb_nr].mb_available[1][1] = &(mb_data[mb_nr]); + + if (img->pix_x >= MB_BLOCK_SIZE) { + int remove_prediction = curr_mb->slice_nr + != mb_data[mb_nr - 1].slice_nr; + if (!remove_prediction) + curr_mb->mb_available[1][0] = &(mb_data[mb_nr - 1]); + } + + check_value = (img->pix_y >= MB_BLOCK_SIZE); + if (check_value) { + int remove_prediction = curr_mb->slice_nr + != mb_data[mb_nr - mb_width].slice_nr; + + if (!remove_prediction) { + curr_mb->mb_available[0][1] = + &(mb_data[mb_nr - mb_width]); + } + } + + if (img->pix_y >= MB_BLOCK_SIZE && img->pix_x >= MB_BLOCK_SIZE) { + int remove_prediction = curr_mb->slice_nr + != mb_data[mb_nr - mb_width - 1].slice_nr; + if (!remove_prediction) { + curr_mb->mb_available[0][0] = &(mb_data[mb_nr - mb_width + - 1]); + } + } + + if (img->pix_y >= MB_BLOCK_SIZE + && img->pix_x < (img->width - MB_BLOCK_SIZE)) { + if (curr_mb->slice_nr == mb_data[mb_nr - mb_width + 1].slice_nr) + curr_mb->mb_available[0][2] = &(mb_data[mb_nr - mb_width + + 1]); + } + curr_mb->mb_available_left = curr_mb->mb_available[1][0]; + curr_mb->mb_available_up = curr_mb->mb_available[0][1]; + curr_mb->mbaddr_a = mb_nr - 1; + curr_mb->mbaddr_b = mb_nr - img->pic_width_inmbs; + curr_mb->mbaddr_c = mb_nr - img->pic_width_inmbs + 1; + curr_mb->mbaddr_d = mb_nr - img->pic_width_inmbs - 1; + + curr_mb->mbavail_a = (curr_mb->mb_available[1][0] != NULL) ? 1 : 0; + curr_mb->mbavail_b = (curr_mb->mb_available[0][1] != NULL) ? 1 : 0; + curr_mb->mbavail_c = (curr_mb->mb_available[0][2] != NULL) ? 1 : 0; + curr_mb->mbavail_d = (curr_mb->mb_available[0][0] != NULL) ? 1 : 0; +} + +/* + ************************************************************************* + * Function:initializes the current macroblock + * Input: + * Output: + * Return: + * Attention: + ************************************************************************* + */ + +void start_macroblock(struct img_par *img) +{ + int i, j, k, l; + struct macroblock *curr_mb; + +#ifdef AVSP_LONG_CABAC +#else + +#endif + + curr_mb = &mb_data[img->current_mb_nr]; + + /* Update coordinates of the current macroblock */ + img->mb_x = (img->current_mb_nr) % (img->width / MB_BLOCK_SIZE); + img->mb_y = (img->current_mb_nr) / (img->width / MB_BLOCK_SIZE); + +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & MB_NUM_DUMP) + io_printf(" #Begin MB : %d, (%x, %x) es_ptr %d\n", + img->current_mb_nr, img->mb_x, img->mb_y, es_ptr); +#endif + + + total_mb_count = total_mb_count + 1; + + /* Define vertical positions */ + img->block_y = img->mb_y * BLOCK_SIZE / 2; /* luma block position */ + img->block8_y = img->mb_y * BLOCK_SIZE / 2; + img->pix_y = img->mb_y * MB_BLOCK_SIZE; /* luma macroblock position */ + if (chroma_format == 2) + img->pix_c_y = img->mb_y * + MB_BLOCK_SIZE; /* chroma macroblock position */ + else + img->pix_c_y = img->mb_y * + MB_BLOCK_SIZE / 2; /* chroma macroblock position */ + + /* Define horizontal positions */ + img->block_x = img->mb_x * BLOCK_SIZE / 2; /* luma block position */ + img->block8_x = img->mb_x * BLOCK_SIZE / 2; + img->pix_x = img->mb_x * MB_BLOCK_SIZE; /* luma pixel position */ + img->pix_c_x = img->mb_x * + MB_BLOCK_SIZE / 2; /* chroma pixel position */ + + checkavailabilityofneighbors(img); + + /*qp = img->qp; + curr_mb->mb_type = 0; + curr_mb->delta_quant = 0; + curr_mb->cbp = 0; + curr_mb->cbp_blk = 0; + curr_mb->c_ipred_mode = DC_PRED_8; + curr_mb->c_ipred_mode_2 = DC_PRED_8; + + for (l = 0; l < 2; l++) + for (j = 0; j < BLOCK_MULTIPLE; j++) + for (i = 0; i < BLOCK_MULTIPLE; i++) + for (k = 0; k < 2; k++) + curr_mb->mvd[l][j][i][k] = 0; + + curr_mb->cbp_bits = 0; + + for (j = 0; j < MB_BLOCK_SIZE; j++) + for (i = 0; i < MB_BLOCK_SIZE; i++) + img->m7[i][j] = 0; + + for (j = 0; j < 2 * BLOCK_SIZE; j++) + for (i = 0; i < 2 * BLOCK_SIZE; i++) { + img->m8[0][i][j] = 0; + img->m8[1][i][j] = 0; + img->m8[2][i][j] = 0; + img->m8[3][i][j] = 0; + } + + curr_mb->lf_disable = 1; + + img->weighting_prediction = 0; +} + +/* + ************************************************************************* + * Function:init macroblock I and P frames + * Input: + * Output: + * Return: + * Attention: + ************************************************************************* + */ + +void init_macroblock(struct img_par *img) +{ + int i, j; + + + for (i = 0; i < 4; i++) { + for (j = 0; j < 4; j++) { + img->ipredmode[img->block_x * 2 + i + 2][img->block_y + * 2 + j + 2] = -1; + } + } + +} + +/* + ************************************************************************* + * Function:Interpret the mb mode for I-Frames + * Input: + * Output: + * Return: + * Attention: + ************************************************************************* + */ + +void interpret_mb_mode_i(struct img_par *img) +{ + int i; + + struct macroblock *curr_mb = &mb_data[img->current_mb_nr]; + int num = 4; + + curr_mb->mb_type = I8MB; + + + current_mb_intra = 1; + + for (i = 0; i < 4; i++) { + curr_mb->b8mode[i] = IBLOCK; + curr_mb->b8pdir[i] = -1; + } + + for (i = num; i < 4; i++) { + curr_mb->b8mode[i] = + curr_mb->mb_type_2 == P8x8 ? + 4 : curr_mb->mb_type_2; + curr_mb->b8pdir[i] = 0; + } +} + +const int pred_4x4[9][9] = {{0, 0, 0, 0, 0, 0, 0, 0, 0}, {1, 1, 1, 1, 1, 1, 1, + 1, 1}, {0, 1, 2, 3, 4, 5, 6, 7, 8}, {0, 0, 0, 3, 3, 3, 3, 3, 3}, + {0, 1, 4, 4, 4, 4, 4, 4, 4}, {0, 1, 5, 5, 5, 5, 5, 5, 5}, {0, 0, + 0, 0, 0, 0, 6, 0, 0}, + {0, 1, 7, 7, 7, 7, 7, 7, 7}, {0, 0, 0, 0, 4, 5, 6, 7, 8} + +}; + +const int pred_4x4to8x8[9] = {0, 1, 2, 3, 4, 1, 0, 1, 0 + +}; + +const int pred_8x8to4x4[5] = {0, 1, 2, 3, 4}; + +void read_ipred_block_modes(struct img_par *img, int b8) +{ + int bi, bj, dec; + struct syntaxelement curr_se; + struct macroblock *curr_mb; + int j2; + int mostprobableintrapredmode; + int upintrapredmode; + int uprightintrapredmode; + int leftintrapredmode; + int leftdownintrapredmode; + int intrachromapredmodeflag; + + struct slice_s *currslice = img->current_slice; + struct datapartition *dp; + + curr_mb = mb_data + img->current_mb_nr; + intrachromapredmodeflag = IS_INTRA(curr_mb); + + curr_se.type = SE_INTRAPREDMODE; +#if TRACE + strncpy(curr_se.tracestring, "Ipred Mode", TRACESTRING_SIZE); +#endif + + if (b8 < 4) { + if (curr_mb->b8mode[b8] == IBLOCK) { + intrachromapredmodeflag = 1; + + if (1) { + dp = &(currslice->part_arr[0]); + curr_se.reading = read_intrapredmode_aec; + dp->read_syntax_element(&curr_se, img, dp); + + if (curr_se.value1 == -1) + push_es(1, 1); + else + push_es(curr_se.value1, 3); + + + } + bi = img->block_x + (b8 & 1); + bj = img->block_y + (b8 / 2); + + upintrapredmode = img->ipredmode[(bi + 1) * 2][(bj) * 2 + + 1]; + uprightintrapredmode = + img->ipredmode[(bi + 1) * 2 + 1][(bj) + * 2 + 1]; + leftintrapredmode = + img->ipredmode[(bi) * 2 + 1][(bj + 1) + * 2]; + leftdownintrapredmode = img->ipredmode[(bi) * 2 + 1][(bj + + 1) * 2 + 1]; + + if ((upintrapredmode < 0) || (leftintrapredmode < 0)) { + mostprobableintrapredmode = DC_PRED; + } else if ((upintrapredmode < NO_INTRA_PMODE) + && (leftintrapredmode < + NO_INTRA_PMODE)) { + mostprobableintrapredmode = + upintrapredmode + < leftintrapredmode ? + upintrapredmode : + leftintrapredmode; + } else if (upintrapredmode < NO_INTRA_PMODE) { + mostprobableintrapredmode = upintrapredmode; + } else if (leftintrapredmode < NO_INTRA_PMODE) { + mostprobableintrapredmode = leftintrapredmode; + } else { + mostprobableintrapredmode = + pred_4x4[leftintrapredmode + - INTRA_PMODE_4x4][upintrapredmode + - INTRA_PMODE_4x4]; + mostprobableintrapredmode = + pred_4x4to8x8[mostprobableintrapredmode]; + } + + + + dec = + (curr_se.value1 == -1) ? + mostprobableintrapredmode : + curr_se.value1 + + (curr_se.value1 + >= mostprobableintrapredmode); + +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & MB_INFO_DUMP) + io_printf(" - ipredmode[%d] : %d\n", b8, dec); +#endif + + img->ipredmode[(1 + bi) * 2][(1 + bj) * 2] = dec; + img->ipredmode[(1 + bi) * 2 + 1][(1 + bj) * 2] = dec; + img->ipredmode[(1 + bi) * 2][(1 + bj) * 2 + 1] = dec; + img->ipredmode[(1 + bi) * 2 + 1][(1 + bj) * 2 + 1] = + dec; + + j2 = bj; + } + } else if (b8 == 4 && curr_mb->b8mode[b8 - 3] == IBLOCK) { + + curr_se.type = SE_INTRAPREDMODE; +#if TRACE + strncpy(curr_se.tracestring, + "Chroma intra pred mode", TRACESTRING_SIZE); +#endif + + if (1) { + dp = &(currslice->part_arr[0]); + curr_se.reading = read_cipredmode_aec; + dp->read_syntax_element(&curr_se, img, dp); + } else + + { + } + curr_mb->c_ipred_mode = curr_se.value1; + + push_es(UE[curr_se.value1][0], UE[curr_se.value1][1]); + +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & MB_INFO_DUMP) + io_printf(" * UE c_ipred_mode read : %d\n", + curr_mb->c_ipred_mode); +#endif + + if (curr_se.value1 < DC_PRED_8 || curr_se.value1 > PLANE_8) { +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & MB_INFO_DUMP) + io_printf("%d\n", img->current_mb_nr); +#endif + pr_info("illegal chroma intra pred mode!\n"); + } + } +} + +/*! + ************************************************************************ + * \brief + * This function is used to arithmetically decode the coded + * block pattern of a given MB. + ************************************************************************ + */ +void readcp_aec(struct syntaxelement *se, struct img_par *img, + struct decoding_environment_s *dep_dp) +{ + struct texture_info_contexts *ctx = img->current_slice->tex_ctx; + struct macroblock *curr_mb = &mb_data[img->current_mb_nr]; + + int mb_x, mb_y; + int a, b; + int curr_cbp_ctx, curr_cbp_idx; + int cbp = 0; + int cbp_bit; + int mask; + + for (mb_y = 0; mb_y < 4; mb_y += 2) { + for (mb_x = 0; mb_x < 4; mb_x += 2) { + if (curr_mb->b8mode[mb_y + (mb_x / 2)] == IBLOCK) + curr_cbp_idx = 0; + else + curr_cbp_idx = 1; + + if (mb_y == 0) { + if (curr_mb->mb_available_up == NULL) + b = 0; + else { + b = ((((curr_mb->mb_available_up)->cbp + & (1 << (2 + mb_x / 2))) + == 0) ? 1 : 0); + } + + } else + b = (((cbp & (1 << (mb_x / 2))) == 0) ? 1 : 0); + + if (mb_x == 0) { + if (curr_mb->mb_available_left == NULL) + a = 0; + else { + a = + ((((curr_mb->mb_available_left)->cbp + & (1 + << (2 + * (mb_y + / 2) + + 1))) + == 0) ? + 1 : 0); + } + } else + a = (((cbp & (1 << mb_y)) == 0) ? 1 : 0); + curr_cbp_ctx = a + 2 * b; + mask = (1 << (mb_y + mb_x / 2)); + cbp_bit = biari_decode_symbol(dep_dp, + ctx->cbp_contexts[0] + curr_cbp_ctx); + + if (cbp_bit) + cbp += mask; + } + } + curr_cbp_ctx = 0; + cbp_bit = biari_decode_symbol(dep_dp, + ctx->cbp_contexts[1] + curr_cbp_ctx); + + if (cbp_bit) { + curr_cbp_ctx = 1; + cbp_bit = biari_decode_symbol(dep_dp, + ctx->cbp_contexts[1] + curr_cbp_ctx); + if (cbp_bit) { + cbp += 48; + + } else { + curr_cbp_ctx = 1; + cbp_bit = biari_decode_symbol(dep_dp, + ctx->cbp_contexts[1] + curr_cbp_ctx); + cbp += (cbp_bit == 1) ? 32 : 16; + + } + } + + se->value1 = cbp; + if (!cbp) + last_dquant = 0; + + + +} + +/*! + ************************************************************************ + * \brief + * This function is used to arithmetically decode the delta qp + * of a given MB. + ************************************************************************ + */ +void readdquant_aec(struct syntaxelement *se, struct img_par *img, + struct decoding_environment_s *dep_dp) +{ + struct motion_info_contexts_s *ctx = img->current_slice->mot_ctx; + + int act_ctx; + int act_sym; + int dquant; + + + act_ctx = ((last_dquant != 0) ? 1 : 0); + + act_sym = 1 + - biari_decode_symbol(dep_dp, + ctx->delta_qp_contexts + act_ctx); + if (act_sym != 0) { + act_ctx = 2; + act_sym = unary_bin_decode(dep_dp, + ctx->delta_qp_contexts + act_ctx, 1); + act_sym++; + } + act_sym &= 0x3f; + push_es(UE[act_sym][0], UE[act_sym][1]); + + dquant = (act_sym + 1) / 2; + if ((act_sym & 0x01) == 0) + dquant = -dquant; + se->value1 = dquant; + + last_dquant = dquant; + +} + +int csyntax; + +#define CHECKDELTAQP {\ + if (img->qp+curr_mb->delta_quant > 63\ + || img->qp+curr_mb->delta_quant < 0) {\ + csyntax = 0;\ + transcoding_error_flag = 1;\ + io_printf("error(0) (%3d|%3d) @ MB%d\n",\ + curr_mb->delta_quant,\ + img->qp+curr_mb->delta_quant,\ + img->picture_structure == 0 \ + ? img->current_mb_nr_fld : img->current_mb_nr);\ + } } + +int dct_level[65]; +int dct_run[65]; +int pair_pos; +int dct_pairs = -1; +const int t_chr[5] = {0, 1, 2, 4, 3000}; + +void readrunlevel_aec_ref(struct syntaxelement *se, struct img_par *img, + struct decoding_environment_s *dep_dp) +{ + int pairs, rank, pos; + int run, level, abslevel, symbol; + int sign; + + if (dct_pairs < 0) { + struct bi_context_type_s (*primary)[NUM_MAP_CTX]; + struct bi_context_type_s *pctx; + struct bi_context_type_s *pCTX2; + int ctx, ctx2, offset; + + if (se->context == LUMA_8x8) { + if (img->picture_structure == 0) { + primary = + img->current_slice->tex_ctx->fld_map_contexts; + } else { + primary = + img->current_slice->tex_ctx->map_contexts; + } + } else { + if (img->picture_structure == 0) { + primary = + img->current_slice->tex_ctx->fld_last_contexts; + } else { + primary = + img->current_slice->tex_ctx->last_contexts; + } + } + + rank = 0; + pos = 0; + for (pairs = 0; pairs < 65; pairs++) { +#ifdef DECODING_SANITY_CHECK + /*max index is NUM_BLOCK_TYPES - 1*/ + pctx = primary[rank & 0x7]; +#else + pctx = primary[rank]; +#endif + if (rank > 0) { +#ifdef DECODING_SANITY_CHECK + /*max index is NUM_BLOCK_TYPES - 1*/ + pCTX2 = primary[(5 + (pos >> 5)) & 0x7]; +#else + pCTX2 = primary[5 + (pos >> 5)]; +#endif + ctx2 = (pos >> 1) & 0x0f; + ctx = 0; + + + if (biari_decode_symbolw(dep_dp, pctx + ctx, + pCTX2 + ctx2)) { + break; + } + } + + ctx = 1; + symbol = 0; + while (biari_decode_symbol(dep_dp, pctx + ctx) == 0) { + symbol += 1; + ctx++; + if (ctx >= 2) + ctx = 2; + } + abslevel = symbol + 1; + + if (biari_decode_symbol_eq_prob(dep_dp)) { + level = -abslevel; + sign = 1; + } else { + level = abslevel; + sign = 0; + } +#if TRACE + tracebits2("level", 1, level); +#endif + + if (abslevel == 1) + offset = 4; + else + offset = 6; + symbol = 0; + ctx = 0; + while (biari_decode_symbol(dep_dp, pctx + ctx + offset) + == 0) { + symbol += 1; + ctx++; + if (ctx >= 1) + ctx = 1; + } + run = symbol; + +#if TRACE + tracebits2("run", 1, run); +#endif + dct_level[pairs] = level; + dct_run[pairs] = run; + if (abslevel > t_chr[rank]) { + if (abslevel <= 2) + rank = abslevel; + else if (abslevel <= 4) + rank = 3; + else + rank = 4; + } + pos += (run + 1); + if (pos >= 64) + pos = 63; + } + dct_pairs = pairs; + pair_pos = dct_pairs; + } + + if (dct_pairs > 0) { + se->value1 = dct_level[pair_pos - 1]; + se->value2 = dct_run[pair_pos - 1]; + pair_pos--; + } else { + + se->value1 = se->value2 = 0; + } + + if ((dct_pairs--) == 0) + pair_pos = 0; +} + +int b8_ctr; +#if 0 +int curr_residual_chroma[4][16][16]; +int curr_residual_luma[16][16]; +#endif + +const int SCAN[2][64][2] = {{{0, 0}, {0, 1}, {0, 2}, {1, 0}, {0, 3}, {0, 4}, {1, + 1}, {1, 2}, {0, 5}, {0, 6}, {1, 3}, {2, 0}, {2, 1}, {0, 7}, {1, + 4}, {2, 2}, {3, 0}, {1, 5}, {1, 6}, {2, 3}, {3, 1}, {3, 2}, {4, + 0}, {1, 7}, {2, 4}, {4, 1}, {2, 5}, {3, 3}, {4, 2}, {2, 6}, {3, + 4}, {4, 3}, {5, 0}, {5, 1}, {2, 7}, {3, 5}, {4, 4}, {5, 2}, {6, + 0}, {5, 3}, {3, 6}, {4, 5}, {6, 1}, {6, 2}, {5, 4}, {3, 7}, {4, + 6}, {6, 3}, {5, 5}, {4, 7}, {6, 4}, {5, 6}, {6, 5}, {5, 7}, {6, + 6}, {7, 0}, {6, 7}, {7, 1}, {7, 2}, {7, 3}, {7, 4}, {7, 5}, {7, + 6}, {7, 7} }, {{0, 0}, {1, 0}, {0, 1}, {0, 2}, {1, 1}, {2, 0}, { + 3, 0}, {2, 1}, {1, 2}, {0, 3}, {0, 4}, {1, 3}, {2, 2}, {3, 1}, { + 4, 0}, {5, 0}, {4, 1}, {3, 2}, {2, 3}, {1, 4}, {0, 5}, {0, 6}, { + 1, 5}, {2, 4}, {3, 3}, {4, 2}, {5, 1}, {6, 0}, {7, 0}, {6, 1}, { + 5, 2}, {4, 3}, {3, 4}, {2, 5}, {1, 6}, {0, 7}, {1, 7}, {2, 6}, { + 3, 5}, {4, 4}, {5, 3}, {6, 2}, {7, 1}, {7, 2}, {6, 3}, {5, 4}, { + 4, 5}, {3, 6}, {2, 7}, {3, 7}, {4, 6}, {5, 5}, {6, 4}, {7, 3}, { + 7, 4}, {6, 5}, {5, 6}, {4, 7}, {5, 7}, {6, 6}, {7, 5}, {7, 6}, { + 6, 7}, {7, 7} } }; + +const int SCAN_4x4[16][2] = {{0, 0}, {1, 0}, {0, 1}, {0, 2}, {1, 1}, {2, 0}, {3, + 0}, {2, 1}, {1, 2}, {0, 3}, {1, 3}, {2, 2}, {3, 1}, {3, 2}, {2, + 3}, {3, 3} }; + +/* + ************************************************************************* + * Function: + * Input: + * Output: + * Return: + * Attention: + ************************************************************************* + */ + +void encode_golomb_word(unsigned int symbol, unsigned int grad0, + unsigned int max_levels, unsigned int *res_bits, + unsigned int *res_len) +{ + unsigned int level, res, numbits; + + res = 1UL << grad0; + level = 1UL; + numbits = 1UL + grad0; + + while (symbol >= res && level < max_levels) { + symbol -= res; + res = res << 1; + level++; + numbits += 2UL; + } + + if (level >= max_levels) { + if (symbol >= res) + symbol = res - 1UL; + } + + *res_bits = res | symbol; + *res_len = numbits; +} + +/* + ************************************************************************* + * Function: + * Input: + * Output: + * Return: + * Attention: + ************************************************************************* + */ + +void encode_multilayer_golomb_word(unsigned int symbol, + const unsigned int *grad, const unsigned int *max_levels, + unsigned int *res_bits, unsigned int *res_len) +{ + unsigned int accbits, acclen, bits, len, tmp; + + accbits = acclen = 0UL; + + while (1) { + encode_golomb_word(symbol, *grad, *max_levels, &bits, &len); + accbits = (accbits << len) | bits; + acclen += len; +#ifdef AVSP_LONG_CABAC +#else + assert(acclen <= 32UL); +#endif + tmp = *max_levels - 1UL; + + if (!((len == (tmp << 1) + (*grad)) + && (bits == (1UL << (tmp + *grad)) - 1UL))) + break; + + tmp = *max_levels; + symbol -= (((1UL << tmp) - 1UL) << (*grad)) - 1UL; + grad++; + max_levels++; + } + *res_bits = accbits; + *res_len = acclen; +} + +/* + ************************************************************************* + * Function: + * Input: + * Output: + * Return: + * Attention: + ************************************************************************* + */ + +int writesyntaxelement_golomb(struct syntaxelement *se, int write_to_stream) +{ + unsigned int bits, len, i; + unsigned int grad[4], max_lev[4]; + + if (!(se->golomb_maxlevels & ~0xFF)) + encode_golomb_word(se->value1, se->golomb_grad, + se->golomb_maxlevels, &bits, &len); + else { + for (i = 0UL; i < 4UL; i++) { + grad[i] = (se->golomb_grad >> (i << 3)) & 0xFFUL; + max_lev[i] = (se->golomb_maxlevels >> (i << 3)) + & 0xFFUL; + } + encode_multilayer_golomb_word(se->value1, grad, max_lev, &bits, + &len); + } + + se->len = len; + se->bitpattern = bits; + + if (write_to_stream) + push_es(bits, len); + return se->len; +} + +/* + ************************************************************************* + * Function:Get coded block pattern and coefficients (run/level) + from the bitstream + * Input: + * Output: + * Return: + * Attention: + ************************************************************************* + */ + +void read_cbpandcoeffsfrom_nal(struct img_par *img) +{ + + int tablenum; + int inumblk; + int inumcoeff; + int symbol2D; + int escape_level_diff; + const int (*AVS_2DVLC_table_intra)[26][27]; + const int (*AVS_2DVLC_table_chroma)[26][27]; + int write_to_stream; + struct syntaxelement currse_enc; + struct syntaxelement *e_currse = &currse_enc; + + int coeff_save[65][2]; + int coeff_ptr; + + int ii, jj; + int mb_nr = img->current_mb_nr; + + int m2, jg2; + struct macroblock *curr_mb = &mb_data[mb_nr]; + + int block8x8; + + int block_x, block_y; + + struct slice_s *currslice = img->current_slice; + int level, run, coef_ctr, len, k, i0, j0, uv, qp; + + int boff_x, boff_y, start_scan; + struct syntaxelement curr_se; + struct datapartition *dp; + + AVS_2DVLC_table_intra = AVS_2DVLC_INTRA; + AVS_2DVLC_table_chroma = AVS_2DVLC_CHROMA; + write_to_stream = 1; + + dct_pairs = -1; + + curr_mb->qp = img->qp; + qp = curr_mb->qp; + + + for (block_y = 0; block_y < 4; block_y += 2) {/* all modes */ + for (block_x = 0; block_x < 4; block_x += 2) { + block8x8 = 2 * (block_y / 2) + block_x / 2; + if (curr_mb->cbp & (1 << block8x8)) { + tablenum = 0; + inumblk = 1; + inumcoeff = 65; + coeff_save[0][0] = 0; + coeff_save[0][1] = 0; + coeff_ptr = 1; + + b8_ctr = block8x8; + + boff_x = (block8x8 % 2) << 3; + boff_y = (block8x8 / 2) << 3; + + img->subblock_x = boff_x >> 2; + img->subblock_y = boff_y >> 2; + + start_scan = 0; + coef_ctr = start_scan - 1; + level = 1; + img->is_v_block = 0; + img->is_intra_block = IS_INTRA(curr_mb); + for (k = start_scan; + (k < 65) && (level != 0); + k++) { + + curr_se.context = LUMA_8x8; + curr_se.type = + (IS_INTRA(curr_mb)) ? + SE_LUM_AC_INTRA : + SE_LUM_AC_INTER; + + dp = &(currslice->part_arr[0]); + curr_se.reading = + readrunlevel_aec_ref; + dp-> + read_syntax_element(&curr_se, + img, dp); + level = curr_se.value1; + run = curr_se.value2; + len = curr_se.len; + + if (level != 0) { + coeff_save[coeff_ptr][0] = + run; + coeff_save[coeff_ptr][1] = + level; + coeff_ptr++; + } + + + + if (level != 0) {/* leave if len = 1 */ + coef_ctr += run + 1; + if ((img->picture_structure + == FRAME)) { + ii = + SCAN[img->picture_structure] + [coef_ctr][0]; + jj = + SCAN[img->picture_structure] + [coef_ctr][1]; + } else { + ii = + SCAN[img->picture_structure] + [coef_ctr][0]; + jj = + SCAN[img->picture_structure] + [coef_ctr][1]; + } + + } + } + + while (coeff_ptr > 0) { + run = + coeff_save[coeff_ptr + - 1][0]; + level = + coeff_save[coeff_ptr + - 1][1]; + + coeff_ptr--; + + symbol2D = CODE2D_ESCAPE_SYMBOL; + if (level > -27 && level < 27 + && run < 26) { + if (tablenum == 0) + + symbol2D = + AVS_2DVLC_table_intra + [tablenum] + [run][abs( + level) + - 1]; + else + + symbol2D = + AVS_2DVLC_table_intra + [tablenum] + [run][abs( + level)]; + if (symbol2D >= 0 + && level + < 0) + symbol2D++; + if (symbol2D < 0) + + symbol2D = + (CODE2D_ESCAPE_SYMBOL + + (run + << 1) + + ((level + > 0) ? + 1 : + 0)); + } + + else { + + symbol2D = + (CODE2D_ESCAPE_SYMBOL + + (run + << 1) + + ((level + > 0) ? + 1 : + 0)); + } + + + + e_currse->type = SE_LUM_AC_INTER; + e_currse->value1 = symbol2D; + e_currse->value2 = 0; + + e_currse->golomb_grad = + vlc_golomb_order + [0][tablenum][0]; + e_currse->golomb_maxlevels = + vlc_golomb_order + [0][tablenum][1]; + + writesyntaxelement_golomb( + e_currse, + write_to_stream); + + if (symbol2D + >= CODE2D_ESCAPE_SYMBOL) { + + e_currse->type = + SE_LUM_AC_INTER; + e_currse->golomb_grad = + 1; + e_currse->golomb_maxlevels = + 11; + escape_level_diff = + abs( + level) + - ((run + > MaxRun[0][tablenum]) ? + 1 : + refabslevel[tablenum][run]); + e_currse->value1 = + escape_level_diff; + + writesyntaxelement_golomb( + e_currse, + write_to_stream); + + } + + if (abs(level) + > incvlc_intra[tablenum]) { + if (abs(level) <= 2) + tablenum = + abs( + level); + else if (abs(level) <= 4) + tablenum = 3; + else if (abs(level) <= 7) + tablenum = 4; + else if (abs(level) + <= 10) + tablenum = 5; + else + tablenum = 6; + } + } + + + } + } + } + + + + m2 = img->mb_x * 2; + jg2 = img->mb_y * 2; + + + uv = -1; + block_y = 4; +#if 0 + qp = QP_SCALE_CR[curr_mb->qp]; +#endif + for (block_x = 0; block_x < 4; block_x += 2) { + + uv++; + + + b8_ctr = (uv + 4); + if ((curr_mb->cbp >> (uv + 4)) & 0x1) { + + tablenum = 0; + inumblk = 1; + inumcoeff = 65; + coeff_save[0][0] = 0; + coeff_save[0][1] = 0; + coeff_ptr = 1; + + coef_ctr = -1; + level = 1; + img->subblock_x = 0; + img->subblock_y = 0; + curr_se.context = CHROMA_AC; + curr_se.type = (IS_INTRA(curr_mb) ? + SE_CHR_AC_INTRA : + SE_CHR_AC_INTER); + dp = &(currslice->part_arr[0]); + curr_se.reading = readrunlevel_aec_ref; + img->is_v_block = uv; + img->is_intra_block = IS_INTRA(curr_mb); + for (k = 0; (k < 65) && (level != 0); k++) { + + dp->read_syntax_element + (&curr_se, img, dp); + level = curr_se.value1; + run = curr_se.value2; + len = curr_se.len; + + if (level != 0) { + coeff_save[coeff_ptr][0] = run; + coeff_save[coeff_ptr][1] = + level; + coeff_ptr++; + } + + + if (level != 0) { + coef_ctr = coef_ctr + run + 1; + if ((img->picture_structure + == FRAME) + /*&& (!curr_mb->mb_field)*/) { + i0 = + SCAN[img->picture_structure] + [coef_ctr][0]; + j0 = + SCAN[img->picture_structure] + [coef_ctr][1]; + } else { + i0 = + SCAN[img->picture_structure] + [coef_ctr][0]; + j0 = + SCAN[img->picture_structure] + [coef_ctr][1]; + } + + } + } + + while (coeff_ptr > 0) { + + run = coeff_save[coeff_ptr - 1][0]; + level = coeff_save[coeff_ptr - 1][1]; + + coeff_ptr--; + + symbol2D = CODE2D_ESCAPE_SYMBOL; + if (level > -27 && level < 27 + && run < 26) { + if (tablenum == 0) + + symbol2D = + AVS_2DVLC_table_chroma + [tablenum][run][abs( + level) + - 1]; + else + symbol2D = + AVS_2DVLC_table_chroma + [tablenum][run][abs( + level)]; + if (symbol2D >= 0 + && level < 0) + symbol2D++; + if (symbol2D < 0) + symbol2D = + (CODE2D_ESCAPE_SYMBOL + + (run + << 1) + + ((level + > 0) ? + 1 : + 0)); + } + + else { + symbol2D = + (CODE2D_ESCAPE_SYMBOL + + (run + << 1) + + ((level + > 0) ? + 1 : + 0)); + } + + e_currse->type = SE_LUM_AC_INTER; + e_currse->value1 = symbol2D; + e_currse->value2 = 0; + e_currse->golomb_grad = + vlc_golomb_order[2] + [tablenum][0]; + e_currse->golomb_maxlevels = + vlc_golomb_order[2] + [tablenum][1]; + + writesyntaxelement_golomb(e_currse, + write_to_stream); + + /* + * if (write_to_stream) + * { + * bitCount[BITS_COEFF_UV_MB]+=e_currse->len; + * e_currse++; + * curr_mb->currSEnr++; + * } + * no_bits+=e_currse->len; + + + * if (icoef == 0) break; + */ + + if (symbol2D >= CODE2D_ESCAPE_SYMBOL) { + + e_currse->type = SE_LUM_AC_INTER; + e_currse->golomb_grad = 0; + e_currse->golomb_maxlevels = 11; + escape_level_diff = + abs(level) + - ((run + > MaxRun[2][tablenum]) ? + 1 : + refabslevel[tablenum + + 14][run]); + e_currse->value1 = + escape_level_diff; + + writesyntaxelement_golomb( + e_currse, + write_to_stream); + + } + + if (abs(level) + > incvlc_chroma[tablenum]) { + if (abs(level) <= 2) + tablenum = abs(level); + else if (abs(level) <= 4) + tablenum = 3; + else + tablenum = 4; + } + } + + } + } +} + +/* + ************************************************************************* + * Function:Get the syntax elements from the NAL + * Input: + * Output: + * Return: + * Attention: + ************************************************************************* + */ + +int read_one_macroblock(struct img_par *img) +{ + int i, j; + + struct syntaxelement curr_se; + struct macroblock *curr_mb = &mb_data[img->current_mb_nr]; + + int cabp_flag; + + int tempcbp; + int fixqp; + + struct slice_s *currslice = img->current_slice; + struct datapartition *dp; + + fixqp = (fixed_picture_qp || fixed_slice_qp); + + for (i = 0; i < 8; i++) + for (j = 0; j < 8; j++) { + img->m8[0][i][j] = 0; + img->m8[1][i][j] = 0; + img->m8[2][i][j] = 0; + img->m8[3][i][j] = 0; + } + + current_mb_skip = 0; + + curr_mb->qp = img->qp; + curr_se.type = SE_MBTYPE; + curr_se.mapping = linfo_ue; + + curr_mb->mb_type_2 = 0; + + if (img->type == I_IMG) + curr_mb->mb_type = 0; + + interpret_mb_mode_i(img); + + init_macroblock(img); + + if ((IS_INTRA(curr_mb)) && (img->abt_flag)) { + +#if TRACE + strncpy(curr_se.tracestring, "cabp_flag", TRACESTRING_SIZE); +#endif + + curr_se.len = 1; + curr_se.type = SE_CABP; + read_syntaxelement_flc(&curr_se); + cabp_flag = curr_se.value1; + if (cabp_flag == 0) { + curr_mb->CABP[0] = 0; + curr_mb->CABP[1] = 0; + curr_mb->CABP[2] = 0; + curr_mb->CABP[3] = 0; + } else { + for (i = 0; i < 4; i++) { + curr_se.len = 1; + curr_se.type = SE_CABP; + read_syntaxelement_flc(&curr_se); + curr_mb->CABP[i] = curr_se.value1; + } + } + + } else { + curr_mb->CABP[0] = 0; + curr_mb->CABP[1] = 0; + curr_mb->CABP[2] = 0; + curr_mb->CABP[3] = 0; + + } + + if (IS_INTRA(curr_mb)) { + for (i = 0; i < /*5*/(chroma_format + 4); i++) + + read_ipred_block_modes(img, i); + } + + curr_se.type = SE_CBP_INTRA; + curr_se.mapping = linfo_cbp_intra; + +#if TRACE + snprintf(curr_se.tracestring, TRACESTRING_SIZE, "CBP"); +#endif + + if (img->type == I_IMG || IS_INTER(curr_mb)) { + curr_se.golomb_maxlevels = 0; + + if (1) { + dp = &(currslice->part_arr[0]); + curr_se.reading = readcp_aec; + dp->read_syntax_element(&curr_se, img, dp); + } + + + curr_mb->cbp = curr_se.value1; + push_es(UE[NCBP[curr_se.value1][0]][0], + UE[NCBP[curr_se.value1][0]][1]); + + } + +# if 1 + if (curr_mb->cbp != 0) + tempcbp = 1; + else + tempcbp = 0; +#else + + if (chroma_format == 2) { +#if TRACE + snprintf(curr_se.tracestring, TRACESTRING_SIZE, "CBP422"); +#endif + curr_se.mapping = /*linfo_se*/linfo_ue; + curr_se.type = SE_CBP_INTRA; + readsyntaxelement_uvlc(&curr_se, inp); + curr_mb->cbp01 = curr_se.value1; + io_printf(" * UE cbp01 read : 0x%02X\n", curr_mb->cbp01); + } + + if (chroma_format == 2) { + if (curr_mb->cbp != 0 || curr_mb->cbp01 != 0) + tempcbp = 1; + else + tempcbp = 0; + + } else { + if (curr_mb->cbp != 0) + tempcbp = 1; + else + tempcbp = 0; + } + +#endif + + if (IS_INTRA(curr_mb) && (img->abt_flag) && (curr_mb->cbp & (0xF))) { + curr_mb->CABT[0] = curr_mb->CABP[0]; + curr_mb->CABT[1] = curr_mb->CABP[1]; + curr_mb->CABT[2] = curr_mb->CABP[2]; + curr_mb->CABT[3] = curr_mb->CABP[3]; + } else { + + curr_mb->CABT[0] = 0; + curr_mb->CABT[1] = 0; + curr_mb->CABT[2] = 0; + curr_mb->CABT[3] = 0; + + if (!fixqp && (tempcbp)) { + if (IS_INTER(curr_mb)) + curr_se.type = SE_DELTA_QUANT_INTER; + else + curr_se.type = SE_DELTA_QUANT_INTRA; + +#if TRACE + snprintf(curr_se.tracestring, + TRACESTRING_SIZE, "Delta quant "); +#endif + + if (1) { + dp = &(currslice->part_arr[0]); + curr_se.reading = readdquant_aec; + dp->read_syntax_element(&curr_se, img, dp); + } + + curr_mb->delta_quant = curr_se.value1; +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & MB_INFO_DUMP) { + io_printf(" * SE delta_quant read : %d\n", + curr_mb->delta_quant); + } +#endif + CHECKDELTAQP + + if (transcoding_error_flag) + return -1; + + img->qp = (img->qp - MIN_QP + curr_mb->delta_quant + + (MAX_QP - MIN_QP + 1)) + % (MAX_QP - MIN_QP + 1) + MIN_QP; + } + + if (fixqp) { + curr_mb->delta_quant = 0; + img->qp = (img->qp - MIN_QP + curr_mb->delta_quant + + (MAX_QP - MIN_QP + 1)) + % (MAX_QP - MIN_QP + 1) + MIN_QP; + + } +#ifdef DUMP_DEBUG + if (avs_get_debug_flag() & MB_INFO_DUMP) + io_printf(" - img->qp : %d\n", img->qp); +#endif + } + + read_cbpandcoeffsfrom_nal(img); + return DECODE_MB; +} + +/*! + ************************************************************************ + * \brief + * finding end of a slice in case this is not the end of a frame + * + * Unsure whether the "correction" below actually solves an off-by-one + * problem or whether it introduces one in some cases :-( Anyway, + * with this change the bit stream format works with AEC again. + * StW, 8.7.02 + ************************************************************************ + */ +int aec_startcode_follows(struct img_par *img, int eos_bit) +{ + struct slice_s *currslice = img->current_slice; + struct datapartition *dp; + unsigned int bit; + struct decoding_environment_s *dep_dp; + + dp = &(currslice->part_arr[0]); + dep_dp = &(dp->de_aec); + + if (eos_bit) + bit = biari_decode_final(dep_dp); + else + bit = 0; + + return bit == 1 ? 1 : 0; +} + +#ifdef AVSP_LONG_CABAC +int process_long_cabac(void) +#else +void main(void) +#endif +{ + int data32; + int current_header; + int i; + int tmp; + int ret; + + int byte_startposition; + int aec_mb_stuffing_bit; + struct slice_s *currslice; +#ifdef PERFORMANCE_DEBUG + pr_info("enter %s\r\n", __func__); +#endif + transcoding_error_flag = 0; + ret = 0; + es_buf = es_write_addr_virt; + + if (local_heap_init(MAX_CODED_FRAME_SIZE * 4) < 0) { + ret = -1; + goto End; + } + + img = (struct img_par *)local_alloc(1, sizeof(struct img_par)); + if (img == NULL) { + no_mem_exit("main: img"); + ret = -1; + goto End; + } + stat_bits_ptr = (struct stat_bits *)local_alloc(1, + sizeof(struct stat_bits)); + if (stat_bits_ptr == NULL) { + no_mem_exit("main: stat_bits"); + ret = -1; + goto End; + } + + curr_stream = alloc_bitstream(); + if (curr_stream == NULL) { + io_printf("alloc bitstream failed\n"); + ret = -1; + goto End; + } + + chroma_format = 1; + demulate_enable = 0; + img->seq_header_indicate = 1; + +#ifdef AVSP_LONG_CABAC + data32 = READ_VREG(LONG_CABAC_REQ); + progressive_sequence = (data32 >> 1) & 1; + fixed_picture_qp = (data32 >> 2) & 1; + img->picture_structure = (data32 >> 3) & 1; + img->type = (data32 >> 4) & 3; + skip_mode_flag = (data32 >> 6) & 1; + + src_start = READ_VREG(LONG_CABAC_SRC_ADDR); + des_start = READ_VREG(LONG_CABAC_DES_ADDR); + + data32 = READ_VREG(LONG_CABAC_PIC_SIZE); + horizontal_size = (data32 >> 0) & 0xffff; + vertical_size = (data32 >> 16) & 0xffff; + if (horizontal_size * vertical_size > 1920 * 1080) { + io_printf("pic size check failed: width = %d, height = %d\n", + horizontal_size, vertical_size); + ret = -1; + goto End; + } + + vld_mem_start_addr = READ_VREG(VLD_MEM_VIFIFO_START_PTR); + vld_mem_end_addr = READ_VREG(VLD_MEM_VIFIFO_END_PTR); + +#else + progressive_sequence = 0; + fixed_picture_qp = 0; + img->picture_structure = 0; + img->type = I_IMG; + skip_mode_flag = 1; + horizontal_size = 1920; + vertical_size = 1080; + + src_start = 0; +#endif + + if (horizontal_size % 16 != 0) + img->auto_crop_right = 16 - (horizontal_size % 16); + else + img->auto_crop_right = 0; + + if (!progressive_sequence) { + if (vertical_size % 32 != 0) + img->auto_crop_bottom = 32 - (vertical_size % 32); + else + img->auto_crop_bottom = 0; + } else { + if (vertical_size % 16 != 0) + img->auto_crop_bottom = 16 - (vertical_size % 16); + else + img->auto_crop_bottom = 0; + } + + img->width = (horizontal_size + img->auto_crop_right); + if (img->picture_structure) + img->height = (vertical_size + img->auto_crop_bottom); + else + img->height = (vertical_size + img->auto_crop_bottom) / 2; + img->width_cr = (img->width >> 1); + + img->pic_width_inmbs = img->width / MB_BLOCK_SIZE; + img->pic_height_inmbs = img->height / MB_BLOCK_SIZE; + img->pic_size_inmbs = img->pic_width_inmbs * img->pic_height_inmbs; + + io_printf( + "[LONG CABAC] Start Transcoding from 0x%x to 0x%x Size : %d x %d\r\n", + src_start, des_start, horizontal_size, vertical_size); +#if 0 + io_printf("VLD_MEM_VIFIFO_START_PTR %x\r\n", + READ_VREG(VLD_MEM_VIFIFO_START_PTR)); + io_printf("VLD_MEM_VIFIFO_CURR_PTR %x\r\n", + READ_VREG(VLD_MEM_VIFIFO_CURR_PTR)); + io_printf("VLD_MEM_VIFIFO_END_PTR %x\r\n", + READ_VREG(VLD_MEM_VIFIFO_END_PTR)); + io_printf("VLD_MEM_VIFIFO_WP %x\r\n", + READ_VREG(VLD_MEM_VIFIFO_WP)); + io_printf("VLD_MEM_VIFIFO_RP %x\r\n", + READ_VREG(VLD_MEM_VIFIFO_RP)); + io_printf("VLD_MEM_VBUF_RD_PTR %x\r\n", + READ_VREG(VLD_MEM_VBUF_RD_PTR)); + io_printf("VLD_MEM_VIFIFO_BUF_CNTL %x\r\n", + READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL)); +#endif + io_printf( + "[LONG CABAC] progressive_sequence : %d, fixed_picture_qp : %d, skip_mode_flag : %d\r\n", + progressive_sequence, fixed_picture_qp, skip_mode_flag); + io_printf("[LONG CABAC] picture_structure : %d, picture_type : %d\r\n", + img->picture_structure, img->type); + + open_irabs(p_irabs); + + + if (initial_decode() == 0) { + io_printf("initial_decode failed\n"); + ret = -1; + goto End; + } + + init_es(); + + current_header = header(); + io_printf("[LONG CABAC] header Return : %d\n", current_header); + + tmp = slice_header(temp_slice_buf, first_slice_startpos, + first_slice_length); + + init_contexts(img); + aec_new_slice(); + byte_startposition = (curr_stream->frame_bitoffset) / 8; + + currslice = img->current_slice; + + if (1) { + for (i = 0; i < 1; i++) { + img->current_slice->part_arr[i].read_syntax_element = + read_syntaxelement_aec; + img->current_slice->part_arr[i].bitstream = curr_stream; + } + curr_stream = currslice->part_arr[0].bitstream; + } + if ((curr_stream->frame_bitoffset) % 8 != 0) + byte_startposition++; + + arideco_start_decoding(&img->current_slice->part_arr[0].de_aec, + curr_stream->stream_buffer, (byte_startposition), + &(curr_stream->read_len), img->type); + + img->current_mb_nr = 0; + total_mb_count = 0; + while (img->current_mb_nr < img->pic_size_inmbs) + + { + start_macroblock(img); + if (-1 == read_one_macroblock(img)) { + ret = -1; + pr_info("macroblock trans failed, exit\n"); + goto End; + } + if (img->cod_counter <= 0) + aec_mb_stuffing_bit = aec_startcode_follows(img, 1); + img->current_mb_nr++; + } + + push_es(0xff, 8); + io_printf(" Total ES_LENGTH : %d\n", es_ptr); + +#ifdef AVSP_LONG_CABAC + push_es(0xff, 64); + if (es_buf_is_overflow) { + io_printf("fatal error: es_buf_is_overflow\n"); + ret = -1; + goto End; + } + + if (transcoding_error_flag == 0) { +#if 1 + dma_sync_single_for_device(amports_get_dma_device(), + es_write_addr_phy, + es_ptr, DMA_TO_DEVICE); + + wmb(); /**/ +#endif + } +#else + fclose(f_es); +#endif + +End: +#ifdef AVSP_LONG_CABAC + WRITE_VREG(LONG_CABAC_REQ, 0); +#endif + local_heap_uninit(); +#ifdef PERFORMANCE_DEBUG + pr_info("exit %s\r\n", __func__); +#endif + return ret; +} +#endif diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/avs2/Makefile b/drivers/amlogic/media_modules/frame_provider/decoder/avs2/Makefile new file mode 100644 index 000000000000..5fe856648dd2 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/avs2/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_AMLOGIC_MEDIA_VDEC_AVS2) += amvdec_avs2.o +amvdec_avs2-objs += vavs2.o avs2_bufmgr.o diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/avs2/avs2_bufmgr.c b/drivers/amlogic/media_modules/frame_provider/decoder/avs2/avs2_bufmgr.c new file mode 100644 index 000000000000..df2adbb7d775 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/avs2/avs2_bufmgr.c @@ -0,0 +1,2138 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../../stream_input/amports/amports_priv.h" +#include +#include "../utils/decoder_mmu_box.h" +#include "../utils/decoder_bmmu_box.h" +#include "avs2_global.h" + +#include +#include "../utils/vdec.h" +#include "../utils/amvdec.h" + +#undef pr_info +#define pr_info printk + +#define assert(chk_cond) {\ + if (!(chk_cond))\ + pr_info("error line %d\n", __LINE__);\ + while (!(chk_cond))\ + ;\ +} + +int16_t get_param(uint16_t value, int8_t *print_info) +{ + if (is_avs2_print_param()) + pr_info("%s = %x\n", print_info, value); + return (int16_t)value; +} + +void readAlfCoeff(struct avs2_decoder *avs2_dec, struct ALFParam_s *Alfp) +{ + int32_t pos; + union param_u *rpm_param = &avs2_dec->param; + + int32_t f = 0, symbol, pre_symbole; + const int32_t numCoeff = (int32_t)ALF_MAX_NUM_COEF; + + switch (Alfp->componentID) { + case ALF_Cb: + case ALF_Cr: { + for (pos = 0; pos < numCoeff; pos++) { + if (Alfp->componentID == ALF_Cb) + Alfp->coeffmulti[0][pos] = + get_param( + rpm_param->alf.alf_cb_coeffmulti[pos], + "Chroma ALF coefficients"); + else + Alfp->coeffmulti[0][pos] = + get_param( + rpm_param->alf.alf_cr_coeffmulti[pos], + "Chroma ALF coefficients"); +#if Check_Bitstream + if (pos <= 7) + assert(Alfp->coeffmulti[0][pos] >= -64 + && Alfp->coeffmulti[0][pos] <= 63); + if (pos == 8) + assert(Alfp->coeffmulti[0][pos] >= -1088 + && Alfp->coeffmulti[0][pos] <= 1071); +#endif + } + } + break; + case ALF_Y: { + int32_t region_distance_idx = 0; + Alfp->filters_per_group = + get_param(rpm_param->alf.alf_filters_num_m_1, + "ALF_filter_number_minus_1"); +#if Check_Bitstream + assert(Alfp->filters_per_group >= 0 + && Alfp->filters_per_group <= 15); +#endif + Alfp->filters_per_group = Alfp->filters_per_group + 1; + + memset(Alfp->filterPattern, 0, NO_VAR_BINS * sizeof(int32_t)); + pre_symbole = 0; + symbol = 0; + for (f = 0; f < Alfp->filters_per_group; f++) { + if (f > 0) { + if (Alfp->filters_per_group != 16) { + symbol = + get_param(rpm_param->alf.region_distance + [region_distance_idx++], + "Region distance"); + } else { + symbol = 1; + } + Alfp->filterPattern[symbol + pre_symbole] = 1; + pre_symbole = symbol + pre_symbole; + } + + for (pos = 0; pos < numCoeff; pos++) { + Alfp->coeffmulti[f][pos] = + get_param( + rpm_param->alf.alf_y_coeffmulti[f][pos], + "Luma ALF coefficients"); +#if Check_Bitstream + if (pos <= 7) + assert( + Alfp->coeffmulti[f][pos] + >= -64 && + Alfp->coeffmulti[f][pos] + <= 63); + if (pos == 8) + assert( + Alfp->coeffmulti[f][pos] + >= -1088 && + Alfp->coeffmulti[f][pos] + <= 1071); +#endif + + } + } + +#if Check_Bitstream + assert(pre_symbole >= 0 && pre_symbole <= 15); + +#endif + } + break; + default: { + pr_info("Not a legal component ID\n"); + assert(0); + return; /* exit(-1);*/ + } + } +} + +void Read_ALF_param(struct avs2_decoder *avs2_dec) +{ + struct inp_par *input = &avs2_dec->input; + struct ImageParameters_s *img = &avs2_dec->img; + union param_u *rpm_param = &avs2_dec->param; + int32_t compIdx; + if (input->alf_enable) { + img->pic_alf_on[0] = + get_param( + rpm_param->alf.picture_alf_enable_Y, + "alf_pic_flag_Y"); + img->pic_alf_on[1] = + get_param( + rpm_param->alf.picture_alf_enable_Cb, + "alf_pic_flag_Cb"); + img->pic_alf_on[2] = + get_param( + rpm_param->alf.picture_alf_enable_Cr, + "alf_pic_flag_Cr"); + + avs2_dec->m_alfPictureParam[ALF_Y].alf_flag + = img->pic_alf_on[ALF_Y]; + avs2_dec->m_alfPictureParam[ALF_Cb].alf_flag + = img->pic_alf_on[ALF_Cb]; + avs2_dec->m_alfPictureParam[ALF_Cr].alf_flag + = img->pic_alf_on[ALF_Cr]; + if (img->pic_alf_on[0] + || img->pic_alf_on[1] + || img->pic_alf_on[2]) { + for (compIdx = 0; + compIdx < NUM_ALF_COMPONENT; + compIdx++) { + if (img->pic_alf_on[compIdx]) { + readAlfCoeff( + avs2_dec, + &avs2_dec->m_alfPictureParam[compIdx]); + } + } + } + } + +} + +void Get_SequenceHeader(struct avs2_decoder *avs2_dec) +{ + struct inp_par *input = &avs2_dec->input; + struct ImageParameters_s *img = &avs2_dec->img; + struct Video_Com_data_s *hc = &avs2_dec->hc; + struct Video_Dec_data_s *hd = &avs2_dec->hd; + union param_u *rpm_param = &avs2_dec->param; + /*int32_t i, j;*/ + + /*fpr_info(stdout, "Sequence Header\n");*/ + /*memcpy(currStream->streamBuffer, buf, length);*/ + /*currStream->code_len = currStream->bitstream_length = length;*/ + /*currStream->read_len = currStream->frame_bitoffset = (startcodepos + + 1) * 8;*/ + + input->profile_id = + get_param(rpm_param->p.profile_id, "profile_id"); + input->level_id = + get_param(rpm_param->p.level_id, "level_id"); + hd->progressive_sequence = + get_param( + rpm_param->p.progressive_sequence, + "progressive_sequence"); +#if INTERLACE_CODING + hd->is_field_sequence = + get_param( + rpm_param->p.is_field_sequence, + "field_coded_sequence"); +#endif +#if HALF_PIXEL_COMPENSATION || HALF_PIXEL_CHROMA + img->is_field_sequence = hd->is_field_sequence; +#endif + hd->horizontal_size = + get_param(rpm_param->p.horizontal_size, "horizontal_size"); + hd->vertical_size = + get_param(rpm_param->p.vertical_size, "vertical_size"); + input->chroma_format = + get_param(rpm_param->p.chroma_format, "chroma_format"); + input->output_bit_depth = 8; + input->sample_bit_depth = 8; + hd->sample_precision = 1; + if (input->profile_id == BASELINE10_PROFILE) { /* 10bit profile (0x52)*/ + input->output_bit_depth = + get_param(rpm_param->p.sample_precision, + "sample_precision"); + input->output_bit_depth = + 6 + (input->output_bit_depth) * 2; + input->sample_bit_depth = + get_param(rpm_param->p.encoding_precision, + "encoding_precision"); + input->sample_bit_depth = + 6 + (input->sample_bit_depth) * 2; + } else { /* other profile*/ + hd->sample_precision = + get_param(rpm_param->p.sample_precision, + "sample_precision"); + } + hd->aspect_ratio_information = + get_param(rpm_param->p.aspect_ratio_information, + "aspect_ratio_information"); + hd->frame_rate_code = + get_param(rpm_param->p.frame_rate_code, "frame_rate_code"); + + hd->bit_rate_lower = + get_param(rpm_param->p.bit_rate_lower, "bit_rate_lower"); + /*hd->marker_bit = get_param(rpm_param->p.marker_bit, + * "marker bit");*/ + /*CHECKMARKERBIT*/ + hd->bit_rate_upper = + get_param(rpm_param->p.bit_rate_upper, "bit_rate_upper"); + hd->low_delay = + get_param(rpm_param->p.low_delay, "low_delay"); + /*hd->marker_bit = + get_param(rpm_param->p.marker_bit2, + "marker bit");*/ + /*CHECKMARKERBIT*/ +#if M3480_TEMPORAL_SCALABLE + hd->temporal_id_exist_flag = + get_param(rpm_param->p.temporal_id_exist_flag, + "temporal_id exist flag"); /*get + Extention Flag*/ +#endif + /*u_v(18, "bbv buffer size");*/ + input->g_uiMaxSizeInBit = + get_param(rpm_param->p.g_uiMaxSizeInBit, + "Largest Coding Block Size"); + + + /*hd->background_picture_enable = 0x01 ^ + (get_param(rpm_param->p.avs2_seq_flags, + "background_picture_disable") + >> BACKGROUND_PICTURE_DISABLE_BIT) & 0x1;*/ + /*rain???*/ + hd->background_picture_enable = 0x01 ^ + ((get_param(rpm_param->p.avs2_seq_flags, + "background_picture_disable") + >> BACKGROUND_PICTURE_DISABLE_BIT) & 0x1); + + + hd->b_dmh_enabled = 1; + + hd->b_mhpskip_enabled = + get_param(rpm_param->p.avs2_seq_flags >> B_MHPSKIP_ENABLED_BIT, + "mhpskip enabled") & 0x1; + hd->dhp_enabled = + get_param(rpm_param->p.avs2_seq_flags >> DHP_ENABLED_BIT, + "dhp enabled") & 0x1; + hd->wsm_enabled = + get_param(rpm_param->p.avs2_seq_flags >> WSM_ENABLED_BIT, + "wsm enabled") & 0x1; + + img->inter_amp_enable = + get_param(rpm_param->p.avs2_seq_flags >> INTER_AMP_ENABLE_BIT, + "Asymmetric Motion Partitions") & 0x1; + input->useNSQT = + get_param(rpm_param->p.avs2_seq_flags >> USENSQT_BIT, + "useNSQT") & 0x1; + input->useSDIP = + get_param(rpm_param->p.avs2_seq_flags >> USESDIP_BIT, + "useNSIP") & 0x1; + + hd->b_secT_enabled = + get_param(rpm_param->p.avs2_seq_flags >> B_SECT_ENABLED_BIT, + "secT enabled") & 0x1; + + input->sao_enable = + get_param(rpm_param->p.avs2_seq_flags >> SAO_ENABLE_BIT, + "SAO Enable Flag") & 0x1; + input->alf_enable = + get_param(rpm_param->p.avs2_seq_flags >> ALF_ENABLE_BIT, + "ALF Enable Flag") & 0x1; + hd->b_pmvr_enabled = + get_param(rpm_param->p.avs2_seq_flags >> B_PMVR_ENABLED_BIT, + "pmvr enabled") & 0x1; + + + hd->gop_size = get_param(rpm_param->p.num_of_RPS, + "num_of_RPS"); +#if Check_Bitstream + /*assert(hd->gop_size<=32);*/ +#endif + + if (hd->low_delay == 0) { + hd->picture_reorder_delay = + get_param(rpm_param->p.picture_reorder_delay, + "picture_reorder_delay"); + } + + input->crossSliceLoopFilter = + get_param(rpm_param->p.avs2_seq_flags + >> CROSSSLICELOOPFILTER_BIT, + "Cross Loop Filter Flag") & 0x1; + +#if BCBR + if ((input->profile_id == SCENE_PROFILE || + input->profile_id == SCENE10_PROFILE) && + hd->background_picture_enable) { + hd->bcbr_enable = u_v(1, + "block_composed_background_picture_enable"); + u_v(1, "reserved bits"); + } else { + hd->bcbr_enable = 0; + u_v(2, "reserved bits"); + } +#else + /*u_v(2, "reserved bits");*/ +#endif + + img->width = hd->horizontal_size; + img->height = hd->vertical_size; + img->width_cr = (img->width >> 1); + + if (input->chroma_format == 1) { + img->height_cr + = (img->height >> 1); + } + + img->PicWidthInMbs = img->width / MIN_CU_SIZE; + img->PicHeightInMbs = img->height / MIN_CU_SIZE; + img->PicSizeInMbs = img->PicWidthInMbs * img->PicHeightInMbs; + img->buf_cycle = input->buf_cycle + 1; + img->max_mb_nr = (img->width * img->height) + / (MIN_CU_SIZE * MIN_CU_SIZE); + +#ifdef AML +avs2_dec->lcu_size = + get_param(rpm_param->p.lcu_size, "lcu_size"); +avs2_dec->lcu_size = 1<<(avs2_dec->lcu_size); +#endif +hc->seq_header++; +} + + +void Get_I_Picture_Header(struct avs2_decoder *avs2_dec) +{ + struct ImageParameters_s *img = &avs2_dec->img; + struct Video_Dec_data_s *hd = &avs2_dec->hd; + union param_u *rpm_param = &avs2_dec->param; + +#if RD1501_FIX_BG /*//Longfei.Wang@mediatek.com*/ + hd->background_picture_flag = 0; + hd->background_picture_output_flag = 0; + img->typeb = 0; +#endif + + hd->time_code_flag = + get_param(rpm_param->p.time_code_flag, + "time_code_flag"); + + if (hd->time_code_flag) { + hd->time_code = + get_param(rpm_param->p.time_code, + "time_code"); + } + if (hd->background_picture_enable) { + hd->background_picture_flag = + get_param(rpm_param->p.background_picture_flag, + "background_picture_flag"); + + if (hd->background_picture_flag) { + img->typeb = + BACKGROUND_IMG; + } else { + img->typeb = 0; + } + + if (img->typeb == BACKGROUND_IMG) { + hd->background_picture_output_flag = + get_param( + rpm_param->p.background_picture_output_flag, + "background_picture_output_flag"); + } + } + + + { + img->coding_order = + get_param(rpm_param->p.coding_order, + "coding_order"); + + + +#if M3480_TEMPORAL_SCALABLE + if (hd->temporal_id_exist_flag == 1) { + hd->cur_layer = + get_param(rpm_param->p.cur_layer, + "temporal_id"); + } +#endif +#if RD1501_FIX_BG /*Longfei.Wang@mediatek.com*/ + if (hd->low_delay == 0 + && !(hd->background_picture_flag && + !hd->background_picture_output_flag)) { /*cdp*/ +#else + if (hd->low_delay == 0 && + !(hd->background_picture_enable && + !hd->background_picture_output_flag)) { /*cdp*/ +#endif + hd->displaydelay = + get_param(rpm_param->p.displaydelay, + "picture_output_delay"); + } + + } + { + int32_t RPS_idx;/* = (img->coding_order-1) % gop_size;*/ + int32_t predict; + int32_t j; + predict = + get_param(rpm_param->p.predict, + "use RCS in SPS"); + /*if (predict) {*/ + RPS_idx = + get_param(rpm_param->p.RPS_idx, + "predict for RCS"); + /* hd->curr_RPS = hd->decod_RPS[RPS_idx];*/ + /*} else {*/ + /*gop size16*/ + hd->curr_RPS.referd_by_others = + get_param(rpm_param->p.referd_by_others_cur, + "refered by others"); + hd->curr_RPS.num_of_ref = + get_param(rpm_param->p.num_of_ref_cur, + "num of reference picture"); + for (j = 0; j < hd->curr_RPS.num_of_ref; j++) { + hd->curr_RPS.ref_pic[j] = + get_param(rpm_param->p.ref_pic_cur[j], + "delta COI of ref pic"); + } + hd->curr_RPS.num_to_remove = + get_param(rpm_param->p.num_to_remove_cur, + "num of removed picture"); + for (j = 0; j < hd->curr_RPS.num_to_remove; j++) { + hd->curr_RPS.remove_pic[j] = + get_param( + rpm_param->p.remove_pic_cur[j], + "delta COI of removed pic"); + } + /*u_v(1, "marker bit");*/ + + /*}*/ + } + /*xyji 12.23*/ + if (hd->low_delay) { + /*ue_v( + "bbv check times");*/ + } + + hd->progressive_frame = + get_param(rpm_param->p.progressive_frame, + "progressive_frame"); + + if (!hd->progressive_frame) { + img->picture_structure = + get_param(rpm_param->p.picture_structure, + "picture_structure"); + } else { + img->picture_structure + = 1; + } + + hd->top_field_first = + get_param(rpm_param->p.top_field_first, + "top_field_first"); + hd->repeat_first_field = + get_param(rpm_param->p.repeat_first_field, + "repeat_first_field"); +#if INTERLACE_CODING + if (hd->is_field_sequence) { + hd->is_top_field = + get_param(rpm_param->p.is_top_field, + "is_top_field"); +#if HALF_PIXEL_COMPENSATION || HALF_PIXEL_CHROMA + img->is_top_field = hd->is_top_field; +#endif + } +#endif + + + img->qp = hd->picture_qp; + + img->type = I_IMG; + +} + +/* + * Function:pb picture header + * Input: + * Output: + * Return: + * Attention: + */ + +void Get_PB_Picture_Header(struct avs2_decoder *avs2_dec) +{ + struct ImageParameters_s *img = &avs2_dec->img; + struct Video_Dec_data_s *hd = &avs2_dec->hd; + union param_u *rpm_param = &avs2_dec->param; + + + /*u_v(32, "bbv delay");*/ + + hd->picture_coding_type = + get_param(rpm_param->p.picture_coding_type, + "picture_coding_type"); + + if (hd->background_picture_enable && + (hd->picture_coding_type == 1 || + hd->picture_coding_type == 3)) { + if (hd->picture_coding_type == 1) { + hd->background_pred_flag = + get_param( + rpm_param->p.background_pred_flag, + "background_pred_flag"); + } else { + hd->background_pred_flag = 0; + } + if (hd->background_pred_flag == 0) { + + hd->background_reference_enable = + get_param( + rpm_param-> + p.background_reference_enable, + "background_reference_enable"); + + } else { +#if RD170_FIX_BG + hd->background_reference_enable = 1; +#else + hd->background_reference_enable = 0; +#endif + } + + } else { + hd->background_pred_flag = 0; + hd->background_reference_enable = 0; + } + + + + if (hd->picture_coding_type == 1) { + img->type = + P_IMG; + } else if (hd->picture_coding_type == 3) { + img->type = + F_IMG; + } else { + img->type = + B_IMG; + } + + + if (hd->picture_coding_type == 1 && + hd->background_pred_flag) { + img->typeb = BP_IMG; + } else { + img->typeb = 0; + } + + + { + img->coding_order = + get_param( + rpm_param->p.coding_order, + "coding_order"); + + +#if M3480_TEMPORAL_SCALABLE + if (hd->temporal_id_exist_flag == 1) { + hd->cur_layer = + get_param(rpm_param->p.cur_layer, + "temporal_id"); + } +#endif + + if (hd->low_delay == 0) { + hd->displaydelay = + get_param(rpm_param->p.displaydelay, + "displaydelay"); + } + } + { + int32_t RPS_idx;/* = (img->coding_order-1) % gop_size;*/ + int32_t predict; + predict = + get_param(rpm_param->p.predict, + "use RPS in SPS"); + if (predict) { + RPS_idx = + get_param(rpm_param->p.RPS_idx, + "predict for RPS"); + hd->curr_RPS = hd->decod_RPS[RPS_idx]; + } /*else*/ + { + /*gop size16*/ + int32_t j; + hd->curr_RPS.referd_by_others = + get_param( + rpm_param->p.referd_by_others_cur, + "refered by others"); + hd->curr_RPS.num_of_ref = + get_param( + rpm_param->p.num_of_ref_cur, + "num of reference picture"); + for (j = 0; j < hd->curr_RPS.num_of_ref; j++) { + hd->curr_RPS.ref_pic[j] = + get_param( + rpm_param->p.ref_pic_cur[j], + "delta COI of ref pic"); + } + hd->curr_RPS.num_to_remove = + get_param( + rpm_param->p.num_to_remove_cur, + "num of removed picture"); + for (j = 0; + j < hd->curr_RPS.num_to_remove; j++) { + hd->curr_RPS.remove_pic[j] = + get_param( + rpm_param->p.remove_pic_cur[j], + "delta COI of removed pic"); + } + /*u_v(1, "marker bit");*/ + + } + } + /*xyji 12.23*/ + if (hd->low_delay) { + /*ue_v( + "bbv check times");*/ + } + + hd->progressive_frame = + get_param(rpm_param->p.progressive_frame, + "progressive_frame"); + + if (!hd->progressive_frame) { + img->picture_structure = + get_param(rpm_param->p.picture_structure, + "picture_structure"); + } else { + img->picture_structure = 1; + } + + hd->top_field_first = + get_param(rpm_param->p.top_field_first, + "top_field_first"); + hd->repeat_first_field = + get_param(rpm_param->p.repeat_first_field, + "repeat_first_field"); +#if INTERLACE_CODING + if (hd->is_field_sequence) { + hd->is_top_field = + get_param(rpm_param->p.is_top_field, + "is_top_field"); +#if HALF_PIXEL_COMPENSATION || HALF_PIXEL_CHROMA + img->is_top_field = hd->is_top_field; +#endif + /*u_v(1, "reserved bit for interlace coding");*/ + } +#endif + +#if Check_Bitstream + /*assert(hd->picture_qp>=0&&hd->picture_qp<=(63 + 8 * + (input->sample_bit_depth - 8)));*/ +#endif + + img->random_access_decodable_flag = + get_param(rpm_param->p.random_access_decodable_flag, + "random_access_decodable_flag"); + + img->qp = hd->picture_qp; +} + + + + +void calc_picture_distance(struct avs2_decoder *avs2_dec) +{ + struct ImageParameters_s *img = &avs2_dec->img; + struct Video_Com_data_s *hc = &avs2_dec->hc; + struct Video_Dec_data_s *hd = &avs2_dec->hd; + /* + union param_u *rpm_param = &avs2_dec->param; + + for POC mode 0: + uint32_t MaxPicDistanceLsb = (1 << 8); + */ + if (img->coding_order < img->PrevPicDistanceLsb) + + { + int32_t i, j; + + hc->total_frames++; + for (i = 0; i < avs2_dec->ref_maxbuffer; i++) { + if ( + avs2_dec->fref[i]->imgtr_fwRefDistance + >= 0) { + avs2_dec->fref[i]-> + imgtr_fwRefDistance -= 256; + avs2_dec->fref[i]-> + imgcoi_ref -= 256; + } +#if RD170_FIX_BG + for (j = 0; j < MAXREF; j++) { +#else + for (j = 0; j < 4; j++) { +#endif + avs2_dec->fref[i]->ref_poc[j] -= 256; + } + } + for (i = 0; i < avs2_dec->outprint.buffer_num; i++) { + avs2_dec->outprint.stdoutdata[i].framenum -= 256; + avs2_dec->outprint.stdoutdata[i].tr -= 256; + } + + hd->last_output -= 256; + hd->curr_IDRtr -= 256; + hd->curr_IDRcoi -= 256; + hd->next_IDRtr -= 256; + hd->next_IDRcoi -= 256; + } + if (hd->low_delay == 0) { + img->tr = img->coding_order + + hd->displaydelay - hd->picture_reorder_delay; + } else { + img->tr = + img->coding_order; + } + +#if REMOVE_UNUSED + img->pic_distance = img->tr; +#else + img->pic_distance = img->tr % 256; +#endif + hc->picture_distance = img->pic_distance; + +} + +int32_t avs2_init_global_buffers(struct avs2_decoder *avs2_dec) +{ + struct inp_par *input = &avs2_dec->input; + struct ImageParameters_s *img = &avs2_dec->img; + struct Video_Com_data_s *hc = &avs2_dec->hc; + + int32_t refnum; + + int32_t memory_size = 0; + /* +int32_t img_height = (hd->vertical_size + img->auto_crop_bottom); + */ + img->buf_cycle = input->buf_cycle + 1; + + img->buf_cycle *= 2; + + hc->background_ref = hc->backgroundReferenceFrame; + + for (refnum = 0; refnum < REF_MAXBUFFER; refnum++) { + avs2_dec->fref[refnum] = &avs2_dec->frm_pool[refnum]; + + /*//avs2_dec->fref[i] memory allocation*/ + if (is_avs2_print_bufmgr_detail()) + pr_info("[t] avs2_dec->fref[%d]@0x%p\n", + refnum, avs2_dec->fref[refnum]); + avs2_dec->fref[refnum]->imgcoi_ref = -257; + avs2_dec->fref[refnum]->is_output = -1; + avs2_dec->fref[refnum]->refered_by_others = -1; + avs2_dec->fref[refnum]-> + imgtr_fwRefDistance = -256; + init_frame_t(avs2_dec->fref[refnum]); +#ifdef AML + avs2_dec->fref[refnum]->index = refnum; +#endif + } +#ifdef AML + avs2_dec->f_bg = NULL; + + avs2_dec->m_bg = &avs2_dec->frm_pool[REF_MAXBUFFER]; + /*///avs2_dec->fref[i] memory allocation*/ + if (is_avs2_print_bufmgr_detail()) + pr_info("[t] avs2_dec->m_bg@0x%p\n", + avs2_dec->m_bg); + avs2_dec->m_bg->imgcoi_ref = -257; + avs2_dec->m_bg->is_output = -1; + avs2_dec->m_bg->refered_by_others = -1; + avs2_dec->m_bg->imgtr_fwRefDistance = -256; + init_frame_t(avs2_dec->m_bg); + avs2_dec->m_bg->index = refnum; +#endif + +#if BCBR + /*init BCBR related*/ + img->iNumCUsInFrame = + ((img->width + MAX_CU_SIZE - 1) / MAX_CU_SIZE) + * ((img->height + MAX_CU_SIZE - 1) + / MAX_CU_SIZE); + /*img->BLCUidx = (int32_t*) calloc( + img->iNumCUsInFrame, sizeof(int32_t));*/ + /*memset( img->BLCUidx, 0, img->iNumCUsInFrame);*/ +#endif + return memory_size; +} + +#ifdef AML +static void free_unused_buffers(struct avs2_decoder *avs2_dec) +{ + struct inp_par *input = &avs2_dec->input; + struct ImageParameters_s *img = &avs2_dec->img; + struct Video_Com_data_s *hc = &avs2_dec->hc; + + int32_t refnum; + + img->buf_cycle = input->buf_cycle + 1; + + img->buf_cycle *= 2; + + hc->background_ref = hc->backgroundReferenceFrame; + + for (refnum = 0; refnum < REF_MAXBUFFER; refnum++) { +#ifndef NO_DISPLAY + if (avs2_dec->fref[refnum]->vf_ref > 0 || + avs2_dec->fref[refnum]->to_prepare_disp) + continue; +#endif + if (is_avs2_print_bufmgr_detail()) + pr_info("%s[t] avs2_dec->fref[%d]@0x%p\n", + __func__, refnum, avs2_dec->fref[refnum]); + avs2_dec->fref[refnum]->imgcoi_ref = -257; + avs2_dec->fref[refnum]->is_output = -1; + avs2_dec->fref[refnum]->refered_by_others = -1; + avs2_dec->fref[refnum]-> + imgtr_fwRefDistance = -256; + memset(avs2_dec->fref[refnum]->ref_poc, 0, + sizeof(avs2_dec->fref[refnum]->ref_poc)); + } + avs2_dec->f_bg = NULL; + + if (is_avs2_print_bufmgr_detail()) + pr_info("%s[t] avs2_dec->m_bg@0x%p\n", + __func__, avs2_dec->m_bg); + avs2_dec->m_bg->imgcoi_ref = -257; + avs2_dec->m_bg->is_output = -1; + avs2_dec->m_bg->refered_by_others = -1; + avs2_dec->m_bg->imgtr_fwRefDistance = -256; + memset(avs2_dec->m_bg->ref_poc, 0, + sizeof(avs2_dec->m_bg->ref_poc)); + +#if BCBR + /*init BCBR related*/ + img->iNumCUsInFrame = + ((img->width + MAX_CU_SIZE - 1) / MAX_CU_SIZE) + * ((img->height + MAX_CU_SIZE - 1) + / MAX_CU_SIZE); + /*img->BLCUidx = (int32_t*) calloc( + img->iNumCUsInFrame, sizeof(int32_t));*/ + /*memset( img->BLCUidx, 0, img->iNumCUsInFrame);*/ +#endif +} +#endif + +void init_frame_t(struct avs2_frame_s *currfref) +{ + memset(currfref, 0, sizeof(struct avs2_frame_s)); + currfref->imgcoi_ref = -257; + currfref->is_output = -1; + currfref->refered_by_others = -1; + currfref->imgtr_fwRefDistance = -256; + memset(currfref->ref_poc, 0, sizeof(currfref->ref_poc)); +} + +void get_reference_list_info(struct avs2_decoder *avs2_dec, int8_t *str) +{ + struct ImageParameters_s *img = &avs2_dec->img; + struct Video_Com_data_s *hc = &avs2_dec->hc; + + int8_t str_tmp[16]; + int32_t i; + /* int32_t poc = hc->f_rec->imgtr_fwRefDistance; + fred.chiu@mediatek.com*/ + + if (img->num_of_references > 0) { + strcpy(str, "["); + for (i = 0; i < img->num_of_references; i++) { +#if RD1510_FIX_BG + if (img->type == B_IMG) { + sprintf(str_tmp, "%4d ", + hc->f_rec-> + ref_poc[ + img->num_of_references - 1 - i]); + } else { + sprintf(str_tmp, "%4d ", + hc->f_rec->ref_poc[i]); + } +#else + sprintf(str_tmp, "%4d ", + avs2_dec->fref[i]->imgtr_fwRefDistance); +#endif + + str_tmp[5] = '\0'; + strcat(str, str_tmp); + } + strcat(str, "]"); + } else { + str[0] = '\0'; + } +} + +void prepare_RefInfo(struct avs2_decoder *avs2_dec) +{ + struct ImageParameters_s *img = &avs2_dec->img; + struct Video_Com_data_s *hc = &avs2_dec->hc; + struct Video_Dec_data_s *hd = &avs2_dec->hd; + + int32_t i, j; + int32_t ii; + struct avs2_frame_s *tmp_fref; + + /*update IDR frame*/ + if (img->tr > hd->next_IDRtr && hd->curr_IDRtr != hd->next_IDRtr) { + hd->curr_IDRtr = hd->next_IDRtr; + hd->curr_IDRcoi = hd->next_IDRcoi; + } + /* re-order the ref buffer according to RPS*/ + img->num_of_references = hd->curr_RPS.num_of_ref; + +#if 1 + /*rain*/ + if (is_avs2_print_bufmgr_detail()) { + pr_info("%s: coding_order is %d, curr_IDRcoi is %d\n", + __func__, img->coding_order, hd->curr_IDRcoi); + for (ii = 0; ii < MAXREF; ii++) { + pr_info("ref_pic(%d)=%d\n", + ii, hd->curr_RPS.ref_pic[ii]); + } + for (ii = 0; ii < avs2_dec->ref_maxbuffer; ii++) { + pr_info( + "fref[%d]: index %d imgcoi_ref %d imgtr_fwRefDistance %d\n", + ii, avs2_dec->fref[ii]->index, + avs2_dec->fref[ii]->imgcoi_ref, + avs2_dec->fref[ii]->imgtr_fwRefDistance); + } + } +#endif + + for (i = 0; i < hd->curr_RPS.num_of_ref; i++) { + /*int32_t accumulate = 0;*/ + /* copy tmp_fref from avs2_dec->fref[i] */ + tmp_fref = avs2_dec->fref[i]; + +#if REMOVE_UNUSED + for (j = i; j < avs2_dec->ref_maxbuffer; j++) { + /*/////////////to be modified IDR*/ + if (avs2_dec->fref[j]->imgcoi_ref == + img->coding_order - + hd->curr_RPS.ref_pic[i]) { + break; + } + } +#else + + for (j = i; j < avs2_dec->ref_maxbuffer; j++) { + /*/////////////to be modified IDR*/ + int32_t k , tmp_tr; + for (k = 0; k < avs2_dec->ref_maxbuffer; k++) { + if (((int32_t)img->coding_order - + (int32_t)hd->curr_RPS.ref_pic[i]) == + avs2_dec->fref[k]->imgcoi_ref && + avs2_dec->fref[k]->imgcoi_ref >= -256) { + break; + } + } + if (k == avs2_dec->ref_maxbuffer) { + tmp_tr = + -1-1; + } else { + tmp_tr = + avs2_dec->fref[k]->imgtr_fwRefDistance; + } + if (tmp_tr < hd->curr_IDRtr) { + hd->curr_RPS.ref_pic[i] = + img->coding_order - hd->curr_IDRcoi; + + for (k = 0; k < i; k++) { + if (hd->curr_RPS.ref_pic[k] == + hd->curr_RPS.ref_pic[i]) { + accumulate++; + break; + } + } + } + if (avs2_dec->fref[j]->imgcoi_ref == + img->coding_order - hd->curr_RPS.ref_pic[i]) { + break; + } + } + if (j == avs2_dec->ref_maxbuffer || accumulate) + img->num_of_references--; +#endif + if (j != avs2_dec->ref_maxbuffer) { + /* copy avs2_dec->fref[i] from avs2_dec->fref[j] */ + avs2_dec->fref[i] = avs2_dec->fref[j]; + /* copy avs2_dec->fref[j] from ferf[tmp] */ + avs2_dec->fref[j] = tmp_fref; + if (is_avs2_print_bufmgr_detail()) { + pr_info("%s, switch %d %d: ", __func__, i, j); + for (ii = 0; ii < hd->curr_RPS.num_of_ref + || ii <= j; ii++) + pr_info("%d ", + avs2_dec->fref[ii]->index); + pr_info("\n"); + } + } + } + if (img->type == B_IMG && + (avs2_dec->fref[0]->imgtr_fwRefDistance <= img->tr + || avs2_dec->fref[1]->imgtr_fwRefDistance >= img->tr)) { + + pr_info("wrong reference configuration for B frame"); + pr_info( + "fref0 imgtr_fwRefDistance %d, fref1 imgtr_fwRefDistance %d, img->tr %d\n", + avs2_dec->fref[0]->imgtr_fwRefDistance, + avs2_dec->fref[1]->imgtr_fwRefDistance, + img->tr); + return; /* exit(-1);*/ + /*******************************************/ + } + +#if !FIX_PROFILE_LEVEL_DPB_RPS_1 + /* delete the frame that will never be used*/ + for (i = 0; i < hd->curr_RPS.num_to_remove; i++) { + for (j = 0; j < avs2_dec->ref_maxbuffer; j++) { + if (avs2_dec->fref[j]->imgcoi_ref >= -256 + && avs2_dec->fref[j]->imgcoi_ref + == img->coding_order - + hd->curr_RPS.remove_pic[i]) { + break; + } + } + if (j < avs2_dec->ref_maxbuffer && + j >= img->num_of_references) { + avs2_dec->fref[j]->imgcoi_ref = -257; +#if M3480_TEMPORAL_SCALABLE + avs2_dec->fref[j]->temporal_id = -1; +#endif + if (avs2_dec->fref[j]->is_output == -1) { + avs2_dec->fref[j]-> + imgtr_fwRefDistance = -256; + } + } + } +#endif + + /* add inter-view reference picture*/ + + /* add current frame to ref buffer*/ + for (i = 0; i < avs2_dec->ref_maxbuffer; i++) { + if ((avs2_dec->fref[i]->imgcoi_ref < -256 + || abs(avs2_dec->fref[i]-> + imgtr_fwRefDistance - img->tr) >= 128) + && avs2_dec->fref[i]->is_output == -1 + && avs2_dec->fref[i]->bg_flag == 0 +#ifndef NO_DISPLAY + && avs2_dec->fref[i]->vf_ref == 0 + && avs2_dec->fref[i]->to_prepare_disp ==0 +#endif + ) { + break; + } + } + if (i == avs2_dec->ref_maxbuffer) + i--; + + hc->f_rec = avs2_dec->fref[i]; + hc->currentFrame = hc->f_rec->ref; + hc->f_rec->imgtr_fwRefDistance = img->tr; + hc->f_rec->imgcoi_ref = img->coding_order; +#if M3480_TEMPORAL_SCALABLE + hc->f_rec->temporal_id = hd->cur_layer; +#endif + hc->f_rec->is_output = 1; + hc->f_rec->refered_by_others = hd->curr_RPS.referd_by_others; + if (is_avs2_print_bufmgr_detail()) + pr_info( + "%s, set f_rec (cur_pic) <= fref[%d] img->tr %d coding_order %d\n", + __func__, i, img->tr, img->coding_order); + + if (img->type != B_IMG) { + for (j = 0; + j < img->num_of_references; j++) { + hc->f_rec->ref_poc[j] = + avs2_dec->fref[j]->imgtr_fwRefDistance; + } + } else { + hc->f_rec->ref_poc[0] = + avs2_dec->fref[1]->imgtr_fwRefDistance; + hc->f_rec->ref_poc[1] = + avs2_dec->fref[0]->imgtr_fwRefDistance; + } + +#if M3480_TEMPORAL_SCALABLE + + for (j = img->num_of_references; + j < 4; j++) { + /**/ + hc->f_rec->ref_poc[j] = 0; + } + + if (img->type == INTRA_IMG) { + int32_t l; + for (l = 0; l < 4; l++) { + hc->f_rec->ref_poc[l] + = img->tr; + } + } + +#endif + +/*////////////////////////////////////////////////////////////////////////*/ + /* updata ref pointer*/ + + if (img->type != I_IMG) { + + img->imgtr_next_P = img->type == B_IMG ? + avs2_dec->fref[0]->imgtr_fwRefDistance : img->tr; + if (img->type == B_IMG) { + hd->trtmp = avs2_dec->fref[0]->imgtr_fwRefDistance; + avs2_dec->fref[0]->imgtr_fwRefDistance = + avs2_dec->fref[1]->imgtr_fwRefDistance; + } + } +#if 1 + /*rain*/ + if (is_avs2_print_bufmgr_detail()) { + for (ii = 0; ii < avs2_dec->ref_maxbuffer; ii++) { + pr_info( + "fref[%d]: index %d imgcoi_ref %d imgtr_fwRefDistance %d refered %d, is_out %d, bg %d, vf_ref %d ref_pos(%d,%d,%d,%d,%d,%d,%d)\n", + ii, avs2_dec->fref[ii]->index, + avs2_dec->fref[ii]->imgcoi_ref, + avs2_dec->fref[ii]->imgtr_fwRefDistance, + avs2_dec->fref[ii]->refered_by_others, + avs2_dec->fref[ii]->is_output, + avs2_dec->fref[ii]->bg_flag, + avs2_dec->fref[ii]->vf_ref, + avs2_dec->fref[ii]->ref_poc[0], + avs2_dec->fref[ii]->ref_poc[1], + avs2_dec->fref[ii]->ref_poc[2], + avs2_dec->fref[ii]->ref_poc[3], + avs2_dec->fref[ii]->ref_poc[4], + avs2_dec->fref[ii]->ref_poc[5], + avs2_dec->fref[ii]->ref_poc[6] + ); + } + } +#endif +} + +int32_t init_frame(struct avs2_decoder *avs2_dec) +{ + struct ImageParameters_s *img = &avs2_dec->img; + struct Video_Com_data_s *hc = &avs2_dec->hc; + struct Video_Dec_data_s *hd = &avs2_dec->hd; + + +#if RD1510_FIX_BG + if (img->type == I_IMG && + img->typeb == BACKGROUND_IMG) { /*G/GB frame*/ + img->num_of_references = 0; + } else if (img->type == P_IMG && img->typeb == BP_IMG) { + /* only one reference frame(G\GB) for S frame*/ + img->num_of_references = 1; + } +#endif + + if (img->typeb == BACKGROUND_IMG && + hd->background_picture_output_flag == 0) { + hc->currentFrame = hc->background_ref; +#ifdef AML + hc->cur_pic = avs2_dec->m_bg; +#endif + } else { + prepare_RefInfo(avs2_dec); +#ifdef AML + hc->cur_pic = hc->f_rec; +#endif + } + + +#ifdef FIX_CHROMA_FIELD_MV_BK_DIST + if (img->typeb == BACKGROUND_IMG + && img->is_field_sequence) { + avs2_dec->bk_img_is_top_field + = img->is_top_field; + } +#endif + return 0; +} + +void delete_trbuffer(struct outdata_s *data, int32_t pos) +{ + int32_t i; + for (i = pos; + i < data->buffer_num - 1; i++) { + data->stdoutdata[i] = + data->stdoutdata[i + 1]; + } + data->buffer_num--; +} + +#if RD170_FIX_BG +void flushDPB(struct avs2_decoder *avs2_dec) +{ + struct Video_Dec_data_s *hd = &avs2_dec->hd; + int j, tmp_min, i, pos = -1; + int search_times = avs2_dec->outprint.buffer_num; + + tmp_min = 1 << 20; + i = 0, j = 0; + pos = -1; + + for (j = 0; j < search_times; j++) { + pos = -1; + tmp_min = (1 << 20); + //search for min poi picture to display + for (i = 0; i < avs2_dec->outprint.buffer_num; i++) { + if (avs2_dec->outprint.stdoutdata[i].tr < tmp_min) { + pos = i; + tmp_min = avs2_dec->outprint.stdoutdata[i].tr; + } + } + + if (pos != -1) { + hd->last_output = avs2_dec->outprint.stdoutdata[pos].tr; + report_frame(avs2_dec, &avs2_dec->outprint, pos); + if (avs2_dec->outprint.stdoutdata[pos].typeb == BACKGROUND_IMG && avs2_dec->outprint.stdoutdata[pos].background_picture_output_flag == 0) { + /*write_GB_frame(hd->p_out_background);*/ + } + else { + write_frame(avs2_dec, avs2_dec->outprint.stdoutdata[pos].tr); + } + + delete_trbuffer(&avs2_dec->outprint, pos); + } + } + + // clear dpb info + for (j = 0; j < REF_MAXBUFFER; j++) + { + avs2_dec->fref[j]->imgtr_fwRefDistance = -256; + avs2_dec->fref[j]->imgcoi_ref = -257; + avs2_dec->fref[j]->temporal_id = -1; + avs2_dec->fref[j]->refered_by_others = 0; + } +} +#endif + + + +#if M3480_TEMPORAL_SCALABLE +void cleanRefMVBufRef(int pos) +{ +#if 0 + int k, x, y; + //re-init mvbuf + for (k = 0; k < 2; k++) { + for (y = 0; y < img->height / MIN_BLOCK_SIZE; y++) { + for (x = 0; x < img->width / MIN_BLOCK_SIZE; x++) { + fref[pos]->mvbuf[y][x][k] = 0; + } + } + } + //re-init refbuf + for (y = 0; y < img->height / MIN_BLOCK_SIZE; y++) { + for (x = 0; x < img->width / MIN_BLOCK_SIZE ; x++) { + fref[pos]->refbuf[y][x] = -1; + } + } +#endif +} +#endif + +static int frame_postprocessing(struct avs2_decoder *avs2_dec) +{ + struct ImageParameters_s *img = &avs2_dec->img; + struct Video_Com_data_s *hc = &avs2_dec->hc; + struct Video_Dec_data_s *hd = &avs2_dec->hd; + + int32_t pointer_tmp = avs2_dec->outprint.buffer_num; + int32_t i; + struct STDOUT_DATA_s *p_outdata; +#if RD160_FIX_BG + int32_t j, tmp_min, output_cur_dec_pic, pos = -1; + int32_t search_times = avs2_dec->outprint.buffer_num; +#endif + /*pic dist by Grandview Semi. @ [06-07-20 15:25]*/ + img->PrevPicDistanceLsb = (img->coding_order % 256); + + pointer_tmp = avs2_dec->outprint.buffer_num; + p_outdata = &avs2_dec->outprint.stdoutdata[pointer_tmp]; + + p_outdata->type = img->type; + p_outdata->typeb = img->typeb; + p_outdata->framenum = img->tr; + p_outdata->tr = img->tr; +#if 0 /*def ORI*/ + p_outdata->qp = img->qp; +#else + p_outdata->qp = 0; +#endif + /*p_outdata->snr_y = snr->snr_y;*/ + /*p_outdata->snr_u = snr->snr_u;*/ + /*p_outdata->snr_v = snr->snr_v;*/ + p_outdata->tmp_time = hd->tmp_time; + p_outdata->picture_structure = img->picture_structure; + /*p_outdata->curr_frame_bits = + StatBitsPtr->curr_frame_bits;*/ + /*p_outdata->emulate_bits = StatBitsPtr->emulate_bits;*/ +#if RD1501_FIX_BG + p_outdata->background_picture_output_flag + = hd->background_picture_output_flag; + /*Longfei.Wang@mediatek.com*/ +#endif + +#if RD160_FIX_BG + p_outdata->picture_reorder_delay = hd->picture_reorder_delay; +#endif + avs2_dec->outprint.buffer_num++; + +#if RD170_FIX_BG + search_times = avs2_dec->outprint.buffer_num; +#endif + /* record the reference list*/ + strcpy(p_outdata->str_reference_list, hc->str_list_reference); + +#if !REF_OUTPUT + #error "!!!REF_OUTPUT should be 1" + for (i = 0; i < avs2_dec->outprint.buffer_num; i++) { + min_tr(avs2_dec->outprint, &pos); + if (avs2_dec->outprint.stdoutdata[pos].tr < img->tr + || avs2_dec->outprint.stdoutdata[pos].tr + == (hd->last_output + 1)) { + hd->last_output = avs2_dec->outprint.stdoutdata[pos].tr; + report_frame(avs2_dec, &avs2_dec->outprint, pos); +#if 0 /*def ORI*/ + write_frame(hd->p_out, + avs2_dec->outprint.stdoutdata[pos].tr); +#endif + delete_trbuffer(&avs2_dec->outprint, pos); + i--; + } else { + break; + } + } +#else +#if RD160_FIX_BG /*Longfei.Wang@mediatek.com*/ + tmp_min = 1 << 20; + i = 0, j = 0; + output_cur_dec_pic = 0; + pos = -1; + for (j = 0; j < search_times; j++) { + pos = -1; + tmp_min = (1 << 20); + /*search for min poi picture to display*/ + for (i = 0; i < avs2_dec->outprint.buffer_num; i++) { + if ((avs2_dec->outprint.stdoutdata[i].tr < tmp_min) && + ((avs2_dec->outprint.stdoutdata[i].tr + + avs2_dec->outprint.stdoutdata[i]. + picture_reorder_delay) + <= (int32_t)img->coding_order)) { + pos = i; + tmp_min = avs2_dec->outprint.stdoutdata[i].tr; + } + } + + if ((0 == hd->displaydelay) && (0 == output_cur_dec_pic)) { + if (img->tr <= tmp_min) {/*fred.chiu@mediatek.com*/ + /*output current decode picture + right now*/ + pos = avs2_dec->outprint.buffer_num - 1; + output_cur_dec_pic = 1; + } + } + if (pos != -1) { + hd->last_output = avs2_dec->outprint.stdoutdata[pos].tr; + report_frame(avs2_dec, &avs2_dec->outprint, pos); +#if 1 /*def ORI*/ + if (avs2_dec->outprint.stdoutdata[pos].typeb + == BACKGROUND_IMG && + avs2_dec->outprint.stdoutdata[pos]. + background_picture_output_flag == 0) { + /**/ + /**/ + } else { + write_frame(avs2_dec, + avs2_dec->outprint.stdoutdata[pos].tr); + } +#endif + delete_trbuffer(&avs2_dec->outprint, pos); + } + + } + +#else + #error "!!!RD160_FIX_BG should be defined" + if (img->coding_order + + (uint32_t)hc->total_frames * 256 >= + (uint32_t)hd->picture_reorder_delay) { + int32_t tmp_min, pos = -1; + tmp_min = 1 << 20; + + for (i = 0; i < + avs2_dec->outprint.buffer_num; i++) { + if (avs2_dec->outprint.stdoutdata[i].tr + < tmp_min && + avs2_dec->outprint.stdoutdata[i].tr + >= hd->last_output) { + /*GB has the same "tr" with "last_output"*/ + pos = i; + tmp_min = + avs2_dec->outprint.stdoutdata[i].tr; + } + } + + if (pos != -1) { + hd->last_output = avs2_dec->outprint.stdoutdata[pos].tr; + report_frame(avs2_dec, &avs2_dec->outprint, pos); +#if RD1501_FIX_BG + if (avs2_dec->outprint.stdoutdata[pos].typeb + == BACKGROUND_IMG && avs2_dec-> + outprint.stdoutdata[pos]. + background_picture_output_flag == 0) { +#else + if (avs2_dec->outprint.stdoutdata[pos].typeb + == BACKGROUND_IMG && + hd->background_picture_output_flag + == 0) { +#endif + write_GB_frame( + hd->p_out_background); + } else { + write_frame(avs2_dec, + avs2_dec->outprint.stdoutdata[pos].tr); + } + delete_trbuffer(&avs2_dec->outprint, pos); + + } + + } +#endif +#endif + return pos; + + } + +void write_frame(struct avs2_decoder *avs2_dec, int32_t pos) +{ + int32_t j; + + if (is_avs2_print_bufmgr_detail()) + pr_info("%s(pos = %d)\n", __func__, pos); + + for (j = 0; j < avs2_dec->ref_maxbuffer; j++) { + if (avs2_dec->fref[j]->imgtr_fwRefDistance == pos) { + avs2_dec->fref[j]->is_output = -1; + avs2_dec->fref[j]->to_prepare_disp = + avs2_dec->to_prepare_disp_count++; + if (avs2_dec->fref[j]->refered_by_others == 0 + || avs2_dec->fref[j]->imgcoi_ref + == -257) { + avs2_dec->fref[j]->imgtr_fwRefDistance + = -256; + avs2_dec->fref[j]->imgcoi_ref = -257; +#if M3480_TEMPORAL_SCALABLE + avs2_dec->fref[j]->temporal_id = -1; +#endif + if (is_avs2_print_bufmgr_detail()) + pr_info("%s, fref index %d\n", __func__, j); + } + break; + } + } +} + +/*rain???, outdata *data*/ +void report_frame(struct avs2_decoder *avs2_dec, + struct outdata_s *data, int32_t pos) +{ + struct ImageParameters_s *img = &avs2_dec->img; + struct Video_Com_data_s *hc = &avs2_dec->hc; + struct Video_Dec_data_s *hd = &avs2_dec->hd; + + int8_t *Frmfld; + int8_t Frm[] = "FRM"; + int8_t Fld[] = "FLD"; + struct STDOUT_DATA_s *p_stdoutdata + = &data->stdoutdata[pos]; + const int8_t *typ; + +#if 0 + if (input->MD5Enable & 0x02) { + sprintf(MD5str, "%08X%08X%08X%08X\0", + p_stdoutdata->DecMD5Value[0], + p_stdoutdata->DecMD5Value[1], + p_stdoutdata->DecMD5Value[2], + p_stdoutdata->DecMD5Value[3]); + } else { + memset(MD5val, 0, 16); + memset(MD5str, 0, 33); + } +#endif + + if (p_stdoutdata-> + picture_structure) { + Frmfld = Frm; + } else { + Frmfld = Fld; + } +#if INTERLACE_CODING + if (img->is_field_sequence) { /*rcs??*/ + Frmfld = Fld; + } +#endif + if ((p_stdoutdata->tr + hc->total_frames * 256) + == hd->end_SeqTr) { /* I picture*/ + /*if ( img->new_sequence_flag == 1 )*/ + { + img->sequence_end_flag = 0; + /*fprintf(stdout, "Sequence + End\n\n");*/ + } + } + if ((p_stdoutdata->tr + hc->total_frames * 256) + == hd->next_IDRtr) { +#if !RD170_FIX_BG + if (hd->vec_flag) /**/ +#endif + { + hd->vec_flag = 0; + /*fprintf(stdout, "Video Edit + Code\n");*/ + } + } + + if (p_stdoutdata->typeb == BACKGROUND_IMG) { + typ = (hd->background_picture_output_flag != 0) ? "G" : "GB"; + } else { +#if REMOVE_UNUSED + typ = (p_stdoutdata->type == INTRA_IMG) + ? "I" : (p_stdoutdata->type == INTER_IMG) ? + ((p_stdoutdata->typeb == BP_IMG) ? "S" : "P") + : (p_stdoutdata->type == F_IMG ? "F" : "B"); +#else + typ = (p_stdoutdata->type == INTRA_IMG) ? "I" : + (p_stdoutdata->type == INTER_IMG) ? + ((p_stdoutdata->type == BP_IMG) ? "S" : "P") + : (p_stdoutdata->type == F_IMG ? "F" : "B"); +#endif + } + +#if 0 + /*rain???*/ + pr_info("%3d(%s) %3d %5d %7.4f %7.4f %7.4f %5d\t\t%s %8d %6d\t%s", + p_stdoutdata->framenum + hc->total_frames * 256, + typ, p_stdoutdata->tr + hc->total_frames * 256, + p_stdoutdata->qp, p_stdoutdata->snr_y, + p_stdoutdata->snr_u, p_stdoutdata->snr_v, + p_stdoutdata->tmp_time, Frmfld, + p_stdoutdata->curr_frame_bits, + p_stdoutdata->emulate_bits, + ""); +#endif + if (is_avs2_print_bufmgr_detail()) + pr_info(" %s\n", p_stdoutdata->str_reference_list); + + /*fflush(stdout);*/ + hd->FrameNum++; +} + +void avs2_prepare_header(struct avs2_decoder *avs2_dec, int32_t start_code) +{ + struct ImageParameters_s *img = &avs2_dec->img; + struct Video_Dec_data_s *hd = &avs2_dec->hd; + + switch (start_code) { + case SEQUENCE_HEADER_CODE: + img->new_sequence_flag = 1; + if (is_avs2_print_bufmgr_detail()) + pr_info("SEQUENCE\n"); +#ifdef TO_CHECK +#if SEQ_CHANGE_CHECKER + if (seq_checker_buf == NULL) { + seq_checker_buf = malloc(length); + seq_checker_length = length; + memcpy(seq_checker_buf, Buf, length); + } else { + if ((seq_checker_length != length) || + (memcmp(seq_checker_buf, Buf, length) != 0)) { + free(seq_checker_buf); + /*fprintf(stdout, + "Non-conformance + stream: sequence + header cannot change + !!\n");*/ +#if RD170_FIX_BG + seq_checker_buf = NULL; + seq_checker_length = 0; + seq_checker_buf = malloc(length); + seq_checker_length = length; + memcpy(seq_checker_buf, Buf, length); +#endif + } + + + } +#endif +#if RD170_FIX_BG + if (input->alf_enable + && alfParAllcoated == 1) { + ReleaseAlfGlobalBuffer(); + alfParAllcoated = 0; + } +#endif +/*TO_CHECK*/ +#endif +#if FIX_FLUSH_DPB_BY_LF + if (hd->vec_flag) { + int32_t k; + if (is_avs2_print_bufmgr_detail()) + pr_info("vec_flag is 1, flushDPB and reinit bugmgr\n"); + + flushDPB(avs2_dec); + for (k = 0; k < avs2_dec->ref_maxbuffer; k++) + cleanRefMVBufRef(k); + + hd->vec_flag = 0; +#ifdef AML + free_unused_buffers(avs2_dec); +#else + free_global_buffers(avs2_dec); +#endif + img->number = 0; + img->PrevPicDistanceLsb = 0; + } +#endif + +#if FIX_SEQ_END_FLUSH_DPB_BY_LF + if (img->new_sequence_flag + && img->sequence_end_flag) { + int32_t k; + if (is_avs2_print_bufmgr_detail()) + pr_info( + "new_sequence_flag after sequence_end_flag, flushDPB and reinit bugmgr\n"); + flushDPB(avs2_dec); + for (k = 0; k < avs2_dec->ref_maxbuffer; k++) + cleanRefMVBufRef(k); + +#ifdef AML + free_unused_buffers(avs2_dec); +#else + free_global_buffers(avs2_dec); +#endif + img->number = 0; + img->PrevPicDistanceLsb = 0; + } +#endif + img->seq_header_indicate = 1; + break; + case I_PICTURE_START_CODE: + if (is_avs2_print_bufmgr_detail()) + pr_info("PIC-I\n"); + Get_SequenceHeader(avs2_dec); + Get_I_Picture_Header(avs2_dec); + calc_picture_distance(avs2_dec); + Read_ALF_param(avs2_dec); + if (!img->seq_header_indicate) { + img->B_discard_flag = 1; + /*fprintf(stdout, " I + %3d\t\tDIDSCARD!!\n", + img->tr);*/ + break; + } + break; + case PB_PICTURE_START_CODE: + if (is_avs2_print_bufmgr_detail()) + pr_info("PIC-PB\n"); + Get_SequenceHeader(avs2_dec); + Get_PB_Picture_Header(avs2_dec); + calc_picture_distance(avs2_dec); + Read_ALF_param(avs2_dec); + /* xiaozhen zheng, 20071009*/ + if (!img->seq_header_indicate) { + img->B_discard_flag = 1; + + if (img->type == P_IMG) { + /*fprintf(stdout, " P + %3d\t\tDIDSCARD!!\n", + img->tr);*/ + } + if (img->type == F_IMG) { + /*fprintf(stdout, " F + %3d\t\tDIDSCARD!!\n", + img->tr);*/ + } else { + /*fprintf(stdout, " B + %3d\t\tDIDSCARD!!\n", + img->tr);*/ + } + + break; + } + + if (img->seq_header_indicate == 1 + && img->type != B_IMG) { + img->B_discard_flag = 0; + } + if (img->type == B_IMG && img->B_discard_flag == 1 + && !img->random_access_decodable_flag) { + /*fprintf(stdout, " B + %3d\t\tDIDSCARD!!\n", + img->tr);*/ + break; + } + + break; + case SEQUENCE_END_CODE: +#ifdef TO_CHECK +#if SEQ_CHANGE_CHECKER + if (seq_checker_buf != NULL) { + free(seq_checker_buf); + seq_checker_buf = NULL; + seq_checker_length = 0; + } +#endif +#endif +img->new_sequence_flag = 1; +img->sequence_end_flag = 1; +break; + case VIDEO_EDIT_CODE: + if (is_avs2_print_bufmgr_detail()) + pr_info("VIDEO_EDIT_CODE\n"); + /*video_edit_code_data(Buf, startcodepos, length);*/ + hd->vec_flag = 1; +#ifdef TO_CHECK +#if SEQ_CHANGE_CHECKER + if (seq_checker_buf != NULL) { + free(seq_checker_buf); + seq_checker_buf = NULL; + seq_checker_length = 0; + } +#endif +#endif + +break; + } +} + +#ifdef AML +static uint32_t log2i(uint32_t val) +{ + uint32_t ret = -1; + while (val != 0) { + val >>= 1; + ret++; + } + return ret; +} +#endif + +int32_t avs2_process_header(struct avs2_decoder *avs2_dec) +{ + struct inp_par *input = &avs2_dec->input; + struct ImageParameters_s *img = &avs2_dec->img; + struct Video_Dec_data_s *hd = &avs2_dec->hd; + int32_t lcu_x_num_div; + int32_t lcu_y_num_div; + + int32_t N8_SizeScale; + /*pr_info("%s\n", __func__);*/ + { + N8_SizeScale = 1; + + if (hd->horizontal_size % + (MIN_CU_SIZE * N8_SizeScale) != 0) { + img->auto_crop_right = + (MIN_CU_SIZE * N8_SizeScale) - + (hd->horizontal_size % + (MIN_CU_SIZE * N8_SizeScale)); + } else + img->auto_crop_right = 0; + +#if !INTERLACE_CODING + if (hd->progressive_sequence) /**/ +#endif + { + if (hd->vertical_size % + (MIN_CU_SIZE * N8_SizeScale) != 0) { + img->auto_crop_bottom = + (MIN_CU_SIZE * N8_SizeScale) - + (hd->vertical_size % + (MIN_CU_SIZE * N8_SizeScale)); + } else + img->auto_crop_bottom = 0; + } + + /* Reinit parameters (NOTE: need to do + before init_frame //*/ + img->width = + (hd->horizontal_size + img->auto_crop_right); + img->height = + (hd->vertical_size + img->auto_crop_bottom); + img->width_cr = (img->width >> 1); + + if (input->chroma_format == 1) + img->height_cr = (img->height >> 1); + + img->PicWidthInMbs = img->width / MIN_CU_SIZE; + img->PicHeightInMbs = img->height / MIN_CU_SIZE; + img->PicSizeInMbs = img->PicWidthInMbs * img->PicHeightInMbs; + img->max_mb_nr = (img->width * img->height) / + (MIN_CU_SIZE * MIN_CU_SIZE); + } + + if (img->new_sequence_flag && img->sequence_end_flag) { +#if 0/*RD170_FIX_BG //*/ + int32_t k; + flushDPB(); + for (k = 0; k < avs2_dec->ref_maxbuffer; k++) + cleanRefMVBufRef(k); + + free_global_buffers(); + img->number = 0; +#endif + hd->end_SeqTr = img->tr; + img->sequence_end_flag = 0; + } + if (img->new_sequence_flag) { + hd->next_IDRtr = img->tr; + hd->next_IDRcoi = img->coding_order; + img->new_sequence_flag = 0; + } +#if 0/*RD170_FIX_BG*/ + if (hd->vec_flag) { + int32_t k; + flushDPB(); + for (k = 0; k < avs2_dec->ref_maxbuffer; k++) + cleanRefMVBufRef(k); + + hd->vec_flag = 0; + free_global_buffers(); + img->number = 0; + } +#endif +/* allocate memory for frame buffers*/ +#if 0 +/* called in vavs2.c*/ + if (img->number == 0) + avs2_init_global_buffers(avs2_dec); +#endif + img->current_mb_nr = 0; + + init_frame(avs2_dec); + + img->types = img->type; /* jlzheng 7.15*/ + + if (img->type != B_IMG) { + hd->pre_img_type = img->type; + hd->pre_img_types = img->types; + } + +#ifdef AML + avs2_dec->lcu_size_log2 = log2i(avs2_dec->lcu_size); + lcu_x_num_div = (img->width/avs2_dec->lcu_size); + lcu_y_num_div = (img->height/avs2_dec->lcu_size); + avs2_dec->lcu_x_num = ((img->width % avs2_dec->lcu_size) == 0) ? + lcu_x_num_div : lcu_x_num_div+1; + avs2_dec->lcu_y_num = ((img->height % avs2_dec->lcu_size) == 0) ? + lcu_y_num_div : lcu_y_num_div+1; + avs2_dec->lcu_total = avs2_dec->lcu_x_num*avs2_dec->lcu_y_num; +#endif + return SOP; +} + +int avs2_post_process(struct avs2_decoder *avs2_dec) +{ + struct ImageParameters_s *img = &avs2_dec->img; + struct Video_Com_data_s *hc = &avs2_dec->hc; + struct Video_Dec_data_s *hd = &avs2_dec->hd; + int32_t i; + int ret; + if (img->typeb == BACKGROUND_IMG && hd->background_picture_enable) { +#ifdef AML + for (i = 0; i < avs2_dec->ref_maxbuffer; i++) { + if (avs2_dec->fref[i]->bg_flag != 0) { + avs2_dec->fref[i]->bg_flag = 0; + if (is_avs2_print_bufmgr_detail()) + pr_info( + "clear old BACKGROUND_IMG for index %d\r\n", + avs2_dec->fref[i]->index); + } + } + if (is_avs2_print_bufmgr_detail()) + pr_info( + "post_process: set BACKGROUND_IMG flag for %d\r\n", + hc->cur_pic->index); + avs2_dec->f_bg = hc->cur_pic; + hc->cur_pic->bg_flag = 1; +#endif + } + +#if BCBR + if (hd->background_picture_enable + && hd->bcbr_enable && img->number > 0) + updateBgReference(); +#endif + + if (img->typeb == BACKGROUND_IMG && + hd->background_picture_output_flag == 0) + hd->background_number++; + + if (img->type == B_IMG) { + avs2_dec->fref[0]->imgtr_fwRefDistance + = hd->trtmp; + } + + /* record the reference list information*/ + get_reference_list_info(avs2_dec, avs2_dec->hc.str_list_reference); + + /*pr_info("%s\n", __func__);*/ + ret = frame_postprocessing(avs2_dec); + +#if FIX_PROFILE_LEVEL_DPB_RPS_1 + /* delete the frame that will never be used*/ + { + int32_t i, j; + for (i = 0; i < hd->curr_RPS.num_to_remove; i++) { + for (j = 0; j < avs2_dec->ref_maxbuffer; j++) { + + if (avs2_dec->fref[j]->imgcoi_ref >= -256 + && avs2_dec->fref[j]->imgcoi_ref == + img->coding_order - + hd->curr_RPS.remove_pic[i]) + break; + } + if (j < avs2_dec->ref_maxbuffer) { /**/ +#if FIX_RPS_PICTURE_REMOVE +/* Label new frames as "un-referenced" */ + avs2_dec->fref[j]->refered_by_others = 0; + + /* remove frames which have been outputted */ + if (avs2_dec->fref[j]->is_output == -1) { + avs2_dec->fref[j]-> + imgtr_fwRefDistance = -256; + avs2_dec->fref[j]->imgcoi_ref = -257; + avs2_dec->fref[j]->temporal_id = -1; + + } +#else + avs2_dec->fref[j]->imgcoi_ref = -257; +#if M3480_TEMPORAL_SCALABLE + avs2_dec->fref[j]->temporal_id = -1; +#endif + if (avs2_dec->fref[j]->is_output == -1) { + avs2_dec->fref[j]->imgtr_fwRefDistance + = -256; + } +#endif + } + } + } +#endif + + + /*! TO 19.11.2001 Known Problem: for init_frame + * we have to know the picture type of the + * actual frame*/ + /*! in case the first slice of the P-Frame + * following the I-Frame was lost we decode this + * P-Frame but! do not write it because it + * was + * assumed to be an I-Frame in init_frame.So we + * force the decoder to*/ + /*! guess the right picture type. This is a hack + * a should be removed by the time there is a + * clean*/ + /*! solution where we do not have to know the + * picture type for the function init_frame.*/ + /*! End TO 19.11.2001//Lou*/ + + { + if (img->type == I_IMG || + img->type == P_IMG || + img->type == F_IMG) + img->number++; + else { + hc->Bframe_ctr++; /* B + pictures*/ + } + } + return ret; +} + +void init_avs2_decoder(struct avs2_decoder *avs2_dec) +{ + int32_t i, j, k; + + struct inp_par *input = &avs2_dec->input; + struct ImageParameters_s *img = &avs2_dec->img; + struct Video_Com_data_s *hc = &avs2_dec->hc; + struct Video_Dec_data_s *hd = &avs2_dec->hd; + if (is_avs2_print_bufmgr_detail()) + pr_info("[t] struct avs2_dec @0x%p\n", avs2_dec); + memset(avs2_dec, 0, sizeof(struct avs2_decoder)); +#ifdef AML + avs2_dec->to_prepare_disp_count = 1; +#endif + /* + * ALFParam init + */ + for (i = 0; i < 3; i++) { + avs2_dec->m_alfPictureParam[i].alf_flag = 0; /*1*/ + avs2_dec->m_alfPictureParam[i].num_coeff = 9; /*1*/ + avs2_dec->m_alfPictureParam[i].filters_per_group = 3; /*1*/ + avs2_dec->m_alfPictureParam[i].componentID = i; /*1*/ + for (j = 0; j < 16; j++) { + avs2_dec->m_alfPictureParam[i].filterPattern[j] = 0; + /*16*/ + } + for (j = 0; j < 16; j++) { + for (k = 0; k < 9; k++) { + avs2_dec-> + m_alfPictureParam[i].coeffmulti[j][k] = 0; + /*16*9*/ + } + } + } + + img->seq_header_indicate = 0; + img->B_discard_flag = 0; + + hd->eos = 0; + + if (input->ref_pic_order) { /*ref order*/ + hd->dec_ref_num = 0; + } + + /* + memset(g_log2size, -1, MAX_CU_SIZE + 1); + c = 2; + for (k = 4; k <= MAX_CU_SIZE; k *= 2) { + g_log2size[k] = c; + c++; + } + */ + + avs2_dec->outprint.buffer_num = 0; + + hd->last_output = -1; + hd->end_SeqTr = -1; + hd->curr_IDRtr = 0; + hd->curr_IDRcoi = 0; + hd->next_IDRtr = 0; + hd->next_IDRcoi = 0; + /* Allocate Slice data struct*/ + img->number = 0; + img->type = I_IMG; + + img->imgtr_next_P = 0; + + img->imgcoi_next_ref = 0; + + + img->num_of_references = 0; + hc->seq_header = 0; + + img->new_sequence_flag = 1; + + hd->vec_flag = 0; + + hd->FrameNum = 0; + + /* B pictures*/ + hc->Bframe_ctr = 0; + hc->total_frames = 0; + + /* time for total decoding session*/ + hc->tot_time = 0; + +} + diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/avs2/avs2_global.h b/drivers/amlogic/media_modules/frame_provider/decoder/avs2/avs2_global.h new file mode 100644 index 000000000000..7f9cca4971c7 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/avs2/avs2_global.h @@ -0,0 +1,1654 @@ +/* The copyright in this software is being made available under the BSD + * License, included below. This software may be subject to other third party + * and contributor rights, including patent rights, and no such rights are + * granted under this license. + * + * Copyright (c) 2002-2016, Audio Video coding Standard Workgroup of China + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * * Neither the name of Audio Video coding Standard Workgroup of China + * nor the names of its contributors maybe + * used to endorse or promote products + * derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + + + + +/* + * File name: global.h + * Function: global definitions for for AVS decoder. + * + */ + +#ifndef _GLOBAL_H_ +#define _GLOBAL_H_ + +/* #include //!< for FILE */ +/* #include */ + +#define AML +#undef NO_DISPLAY + +/* #include "define.h" */ +#define RD "19.2" +#define VERSION "19.2" + +#define RESERVED_PROFILE_ID 0x24 +#define BASELINE_PICTURE_PROFILE 18 +#define BASELINE_PROFILE 32 /* 0x20 */ +#define BASELINE10_PROFILE 34 /* 0x22 */ + + +#define SCENE_PROFILE 48 /* 0x21 */ +#define SCENE10_PROFILE 50 /* 0x23 */ + +#define TRACE 0 /* !< 0:Trace off 1:Trace on */ + + +/* Type definitions and file operation for Windows/Linux + * All file operations for windows are replaced with native (FILE *) operations + * Falei LUO (falei.luo@vipl.ict.ac.cn) + * */ + +#define _FILE_OFFSET_BITS 64 /* for 64 bit fseeko */ +#define fseek fseeko + +#define int16 int16_t +#define int64 int64_t + +/* ////////////////// bug fix ///////////////////////////// */ +#define ALFSliceFix 1 +#define WRITENBIT_FIX 1 +#define FIX_PROFILE_LEVEL_DPB_RPS_1 1 +#define FIX_PROFILE_LEVEL_DPB_RPS_2 1 +#define FIX_RPS_PICTURE_REMOVE 1 /* flluo@pku.edu.cn */ +#define Mv_Clip 1 /* yuquanhe@hisilicon.com */ +#define REMOVE_UNUSED 1 /* yuquanhe@hisilicon.com */ +#define SAO_Height_Fix 1 /* yuquanhe@hisilicon.com */ +#define B_BACKGROUND_Fix 1 /* yuquanhe@hisilicon.com */ +#define Check_Bitstream 1 /* yuquanhe@hisilicon.com */ +#define Wq_param_Clip 1 /* yuquanhe@hisilicon.com */ + /* luofalei flluo@pku.edu.cn , wlq15@mails.tsinghua.edu.cn , + Longfei.Wang@mediatek.com */ +#define RD1501_FIX_BG 1 + /* yuquanhe@hisilicon.com ; he-yuan.lin@mstarsemi.com */ +#define Mv_Rang 1 + /* Longfei.Wang@mediatek.com ;fred.chiu@mediatek.com + jie1222.chen@samsung.com */ +#define RD160_FIX_BG 1 + /* Y_K_Tu@novatek.com.tw, he-yuan.lin@mstarsemi.com, + victor.huang@montage-tech.com M4041 */ +#define RD1601_FIX_BG 1 +#define SEQ_CHANGE_CHECKER 1 /* he-yuan.lin@mstarsemi.com */ +#define M4140_END_OF_SLICE_CHECKER 1 /* he-yuan.lin@mstarsemi.com */ + /* wlq15@mails.tsinghua.edu.cn */ +#define Mv_check_bug 1 +#define SAO_ASSERTION_FIX 1 /* fred.chiu@mediatek.com */ +#define FIELD_HORI_MV_NO_SCALE_FIX 1 /* fred.chiu@mediatek.com */ +#define RD170_FIX_BG 1 +#define FIX_CHROMA_FIELD_MV_BK_DIST 1 +#define FIX_LUMA_FIELD_MV_BK_DIST 1 +#define FIX_CHROMA_FIELD_MV_CLIP 1 +#if 1 +#define FIX_FLUSH_DPB_BY_LF 1 /* fred.chiu@mediatek.com */ +#define FIX_SEQ_END_FLUSH_DPB_BY_LF 1 /* fred.chiu@mediatek.com */ +#else +#define FIX_FLUSH_DPB_BY_LF 0 /* fred.chiu@mediatek.com */ +#define FIX_SEQ_END_FLUSH_DPB_BY_LF 0 /* fred.chiu@mediatek.com */ +#endif +#define RD191_FIX_BUG 1 /* yuquanhe@hsilicon.com */ +#define SYM_MV_SCALE_FIX 1/* peisong.chen@broadcom.com */ +#define BUG_10BIT_REFINEQP 0 /* wangzhenyu */ + + + +#if RD191_FIX_BUG +#endif + +/************************ + * AVS2 macros start + **************************/ + +#define INTERLACE_CODING 1 +#if INTERLACE_CODING /* M3531: MV scaling compensation */ +/* Luma component */ +#define HALF_PIXEL_COMPENSATION 1 /* common functions definition */ +#define HALF_PIXEL_COMPENSATION_PMV 1 /* spacial MV prediction */ +#define HALF_PIXEL_COMPENSATION_DIRECT 1 /* B direct mode */ + /* MV derivation method 1, weighted P_skip mode */ +#define HALF_PIXEL_COMPENSATION_M1 1 + /* M1 related with mv-scaling function */ +#define HALF_PIXEL_COMPENSATION_M1_FUCTION 1 +#define HALF_PIXEL_COMPENSATION_MVD 1 /* MV scaling from FW->BW */ +/* Chroma components */ + /* chroma MV is scaled with luma MV for 4:2:0 format */ +#define HALF_PIXEL_CHROMA 1 + /* half pixel compensation for p skip/direct */ +#define HALF_PIXEL_PSKIP 1 +#define INTERLACE_CODING_FIX 1 /* HLS fix */ +#define OUTPUT_INTERLACE_MERGED_PIC 1 + +#endif +/* + ******************************* +AVS2 10bit/12bit profile + ******************************** + */ + +#define DBFIX_10bit 1 + +#define BUG_10bit 1 + +/* + *************************************** +AVS2 HIGH LEVEL SYNTAX + *************************************** + */ +#define AVS2_HDR_HLS 1 + /* AVS2 HDR technology //yuquanhe@hisilicon.com */ +#define AVS2_HDR_Tec 1 +#if AVS2_HDR_Tec +#define HDR_CHROMA_DELTA_QP 1 /* M3905 */ +#define HDR_ADPTIVE_UV_DELTA 1 +#endif +/* + ************************************* +AVS2 S2 + ************************************* + */ +#define AVS2_S2_FASTMODEDECISION 1 +#define RD1510_FIX_BG 1 /* 20160714, flluo@pku.edu.cn */ + + +/* ////////////////// prediction techniques ///////////////////////////// */ +#define LAM_2Level_TU 0.8 + + +#define DIRECTION 4 +#define DS_FORWARD 4 +#define DS_BACKWARD 2 +#define DS_SYM 3 +#define DS_BID 1 + +#define MH_PSKIP_NUM 4 +#define NUM_OFFSET 0 +#define BID_P_FST 1 +#define BID_P_SND 2 +#define FW_P_FST 3 +#define FW_P_SND 4 +#define WPM_NUM 3 + /* M3330 changes it to 2, the original value is 3 */ +#define MAX_MVP_CAND_NUM 2 + +#define DMH_MODE_NUM 5 /* Number of DMH mode */ +#define TH_ME 0 /* Threshold of ME */ + +#define MV_SCALE 1 + +/* ///// reference picture management // */ +#define FIX_MAX_REF 1 /* Falei LUO, flluo@pku.edu.cn */ +#if FIX_MAX_REF + /* maximum number of reference frame for each frame */ +#define MAXREF 7 +#define MAXGOP 32 +#endif + +/* #define REF_MAXBUFFER 7 */ +/* more bufferes for displaying and background */ +/* #define REF_MAXBUFFER 15 */ +#if 1 +#define REF_MAXBUFFER 23 +#define REF_BUFFER 16 +#else +#if RD170_FIX_BG +#define REF_MAXBUFFER 16 +#else +#define REF_MAXBUFFER 7 +#endif +#endif + +#ifdef TO_PORTING + /* block-composed background reference, fangdong@mail.ustc.edu.cn */ +#define BCBR 1 +#else +#define BCBR 0 +#endif +/* one more buffer for background when background_picture_output_flag is 0*/ +#define AVS2_MAX_BUFFER_NUM (REF_MAXBUFFER + 1) + +/* /////////////////Adaptive Loop Filter////////////////////////// */ +#define NUM_ALF_COEFF_CTX 1 +#define NUM_ALF_LCU_CTX 4 + +#define LAMBDA_SCALE_LUMA (1.0) +#define LAMBDA_SCALE_CHROMA (1.0) + + + +/* ////////////////// entropy coding ///////////////////////////// */ + /* M3090: Make sure rs1 will not overflow for 8-bit unsign char */ +#define NUN_VALUE_BOUND 254 +#define Encoder_BYPASS_Final 1 /* M3484 */ +#define Decoder_Bypass_Annex 0 /* M3484 */ +#define Decoder_Final_Annex 0 /* M3540 */ + + +/* ////////////////// coefficient coding ///// */ + /* M3035 size of an coefficient group, 4x4 */ +#define CG_SIZE 16 + +#define SWAP(x, y) {\ + (y) = (y) ^ (x);\ + (x) = (y) ^ (x);\ + (y) = (x) ^ (y);\ +} + +/* ////////////////// encoder optimization /////// */ +#define TH 2 + +#define M3624MDLOG /* reserved */ + +#define TDRDO 1 /* M3528 */ +/* #define FIX_TDRDO_BG 1 // flluo@pku.edu.cn, 20160318// */ +#define RATECONTROL 1 /* M3580 M3627 M3689 */ +#define AQPO 1 /* M3623 */ +#define AQPOM3694 0 +#define AQPOM4063 1 +#define AQPOM3762 1 +#define BGQPO 1 /* M4061 */ +#if BGQPO +#define LONGREFERENCE 32 +#endif + +/* #define REPORT */ +/* ////////////////// Quantization /////////////////////////////////////// */ + /* Adaptive frequency weighting quantization */ +#define FREQUENCY_WEIGHTING_QUANTIZATION 1 +#if FREQUENCY_WEIGHTING_QUANTIZATION +#define CHROMA_DELTA_QP 1 +#define AWQ_WEIGHTING 1 +#define AWQ_LARGE_BLOCK_ENABLE 1 +#define COUNT_BIT_OVERHEAD 0 +#define AWQ_LARGE_BLOCK_EXT_MAPPING 1 +#endif + +#define QuantClip 1 +#define QuantMatrixClipFix 1 /* 20160418, fllu@pku.edu.cn */ + +#define WQ_MATRIX_FCD 1 +#if !WQ_MATRIX_FCD +#define WQ_FLATBASE_INBIT 7 +#else +#define WQ_FLATBASE_INBIT 6 +#endif + + +#define REFINED_QP 1 + + +/* ////////////////// delta QP ///// */ + /* M3122: the minimum dQP unit is Macro block */ +#define MB_DQP 1 + /* M3122: 1 represents left prediction + and 0 represents previous prediction */ +#define LEFT_PREDICTION 1 + + +/* //////////////////////SAO///////// */ +#define NUM_BO_OFFSET 32 +#define MAX_NUM_SAO_CLASSES 32 +#define NUM_SAO_BO_CLASSES_LOG2 5 +#define NUM_SAO_BO_CLASSES_IN_BIT 5 +#define MAX_DOUBLE (1.7e + 308) +#define NUM_SAO_EO_TYPES_LOG2 2 +#define NUM_SAO_BO_CLASSES (1< (c) ? (c) : (a))) +#endif + + /* POC200301 moved from defines.h */ +#define LOG2_MAX_FRAME_NUM_MINUS4 4 + /* !< bytes for one frame */ +#define MAX_CODED_FRAME_SIZE 15000000 + +/* ----------------------- */ +/* FLAGS and DEFINES for new chroma intra prediction, Dzung Hoang */ +/* Threshold values to zero out quantized transform coefficients. */ +/* Recommend that _CHROMA_COEFF_COST_ be low to improve chroma quality */ +#define _LUMA_COEFF_COST_ 4 /* !< threshold for luma coeffs */ + /* !< Number of pixels padded around the reference frame (>=4) */ +#define IMG_PAD_SIZE 64 + +#define OUTSTRING_SIZE 255 + + /* !< abs macro, faster than procedure */ +#define absm(A) ((A) < (0) ? (-(A)) : (A)) + /* !< used for start value for some variables */ +#define MAX_VALUE 999999 + +#define Clip1(a) ((a) > 255 ? 255:((a) < 0 ? 0 : (a))) +#define Clip3(min, max, val) (((val) < (min)) ?\ + (min) : (((val) > (max)) ? (max) : (val))) + +/* --------------------------------------------- */ + +/* block size of block transformed by AVS */ +#define PSKIPDIRECT 0 +#define P2NX2N 1 +#define P2NXN 2 +#define PNX2N 3 +#define PHOR_UP 4 +#define PHOR_DOWN 5 +#define PVER_LEFT 6 +#define PVER_RIGHT 7 +#define PNXN 8 +#define I8MB 9 +#define I16MB 10 +#define IBLOCK 11 +#define InNxNMB 12 +#define INxnNMB 13 +#define MAXMODE 14 /* add yuqh 20130824 */ +#define LAMBDA_ACCURACY_BITS 16 +#define LAMBDA_FACTOR(lambda) ((int)((double)(1 << LAMBDA_ACCURACY_BITS)\ + * lambda + 0.5)) +#define WEIGHTED_COST(factor, bits) (((factor) * (bits))\ + >> LAMBDA_ACCURACY_BITS) +#define MV_COST(f, s, cx, cy, px, py) (WEIGHTED_COST(f, mvbits[((cx) << (s))\ + - px] + mvbits[((cy) << (s)) - py])) +#define REF_COST(f, ref) (WEIGHTED_COST(f, refbits[(ref)])) + +#define BWD_IDX(ref) (((ref) < 2) ? 1 - (ref) : (ref)) +#define REF_COST_FWD(f, ref) (WEIGHTED_COST(f,\ + ((img->num_ref_pic_active_fwd_minus1 == 0) ?\ + 0 : refbits[(ref)]))) +#define REF_COST_BWD(f, ef) (WEIGHTED_COST(f,\ + ((img->num_ref_pic_active_bwd_minus1 == 0) ?\ + 0 : BWD_IDX(refbits[ref])))) + +#define IS_INTRA(MB) ((MB)->cuType == I8MB ||\ + (MB)->cuType == I16MB ||\ + (MB)->cuType == InNxNMB || (MB)->cuType == INxnNMB) +#define IS_INTER(MB) ((MB)->cuType != I8MB &&\ + (MB)->cuType != I16MB && (MB)->cuType != InNxNMB\ + && (MB)->cuType != INxnNMB) +#define IS_INTERMV(MB) ((MB)->cuType != I8MB &&\ + (MB)->cuType != I16MB && (MB)->cuType != InNxNMB &&\ + (MB)->cuType != INxnNMB && (MB)->cuType != 0) + + +#define IS_DIRECT(MB) ((MB)->cuType == PSKIPDIRECT && (img->type == B_IMG)) +#define IS_P_SKIP(MB) ((MB)->cuType == PSKIPDIRECT &&\ + (((img->type == F_IMG)) || ((img->type == P_IMG)))) +#define IS_P8x8(MB) ((MB)->cuType == PNXN) + +/* Quantization parameter range */ +#define MIN_QP 0 +#define MAX_QP 63 +#define SHIFT_QP 11 + +/* Picture types */ +#define INTRA_IMG 0 /* !< I frame */ +#define INTER_IMG 1 /* !< P frame */ +#define B_IMG 2 /* !< B frame */ +#define I_IMG 0 /* !< I frame */ +#define P_IMG 1 /* !< P frame */ +#define F_IMG 4 /* !< F frame */ + +#define BACKGROUND_IMG 3 + +#define BP_IMG 5 + + +/* Direct Mode types */ +#define MIN_CU_SIZE 8 +#define MIN_BLOCK_SIZE 4 +#define MIN_CU_SIZE_IN_BIT 3 +#define MIN_BLOCK_SIZE_IN_BIT 2 +#define BLOCK_MULTIPLE (MIN_CU_SIZE/(MIN_BLOCK_SIZE)) +#define MAX_CU_SIZE 64 +#define MAX_CU_SIZE_IN_BIT 6 +#define B4X4_IN_BIT 2 +#define B8X8_IN_BIT 3 +#define B16X16_IN_BIT 4 +#define B32X32_IN_BIT 5 +#define B64X64_IN_BIT 6 + /* !< # luma intra prediction modes */ +#define NUM_INTRA_PMODE 33 + /* number of luma modes for full RD search */ +#define NUM_MODE_FULL_RD 9 + /* !< #chroma intra prediction modes */ +#define NUM_INTRA_PMODE_CHROMA 5 + +/* luma intra prediction modes */ + +#define DC_PRED 0 +#define PLANE_PRED 1 +#define BI_PRED 2 +#define VERT_PRED 12 +#define HOR_PRED 24 + + +/* chroma intra prediction modes */ +#define DM_PRED_C 0 +#define DC_PRED_C 1 +#define HOR_PRED_C 2 +#define VERT_PRED_C 3 +#define BI_PRED_C 4 + +#define EOS 1 /* !< End Of Sequence */ + /* !< Start Of Picture */ +#define SOP 2 + +#define DECODING_OK 0 +#define SEARCH_SYNC 1 +#define DECODE_MB 1 + +#ifndef max + /* !< Macro returning max value */ +#define max(a, b) ((a) > (b) ? (a) : (b)) + /* !< Macro returning min value */ +#define min(a, b) ((a) < (b) ? (a) : (b)) +#endif + + +#define XY_MIN_PMV 1 +#if XY_MIN_PMV +#define MVPRED_xy_MIN 0 +#else +#define MVPRED_MEDIAN 0 +#endif +#define MVPRED_L 1 +#define MVPRED_U 2 +#define MVPRED_UR 3 + +#define DUAL 4 +#define FORWARD 0 +#define BACKWARD 1 +#define SYM 2 +#define BID 3 +#define INTRA -1 + +#define BUF_CYCLE 5 + +#define ROI_M3264 1 /* ROI Information Encoding */ + +#define PicExtensionData 1 + + +#define REF_OUTPUT 1 /* M3337 */ + + +/* MV scaling 14 bit */ +#define MULTI 16384 +#define HALF_MULTI 8192 +#define OFFSET 14 +/* end of MV scaling */ + /* store the middle pixel's mv in a motion information unit */ +#define MV_DECIMATION_FACTOR 4 + +/* BUGFIX_AVAILABILITY_INTRA */ +#define NEIGHBOR_INTRA_LEFT 0 +#define NEIGHBOR_INTRA_UP 1 +#define NEIGHBOR_INTRA_UP_RIGHT 2 +#define NEIGHBOR_INTRA_UP_LEFT 3 +#define NEIGHBOR_INTRA_LEFT_DOWN 4 +/* end of BUGFIX_AVAILABILITY_INTRA */ + +/* end #include "define.h" */ + +/*#include "commonStructures.h"*/ + +/*typedef uint16_t byte;*/ /* !< byte type definition */ +#define byte uint16_t +#define pel_t byte + +enum BitCountType_e { + BITS_HEADER, + BITS_TOTAL_MB, + BITS_MB_MODE, + BITS_INTER_MB, + BITS_CBP_MB, + BITS_CBP01_MB, + BITS_COEFF_Y_MB, + BITS_COEFF_UV_MB, + BITS_DELTA_QUANT_MB, + BITS_SAO_MB, + MAX_BITCOUNTER_MB +}; + + +enum SAOEOClasses { +/* EO Groups, the assignments depended on +how you implement the edgeType calculation */ + SAO_CLASS_EO_FULL_VALLEY = 0, + SAO_CLASS_EO_HALF_VALLEY = 1, + SAO_CLASS_EO_PLAIN = 2, + SAO_CLASS_EO_HALF_PEAK = 3, + SAO_CLASS_EO_FULL_PEAK = 4, + SAO_CLASS_BO = 5, + NUM_SAO_EO_CLASSES = SAO_CLASS_BO, + NUM_SAO_OFFSET +}; + +struct SAOstatdata { + int32_t diff[MAX_NUM_SAO_CLASSES]; + int32_t count[MAX_NUM_SAO_CLASSES]; +}; + +struct CopyRight_s { + int32_t extension_id; + int32_t copyright_flag; + int32_t copyright_id; + int32_t original_or_copy; + int32_t reserved; + int32_t copyright_number; +}; + +struct CameraParamters_s { + int32_t reserved; + int32_t camera_id; + int32_t height_of_image_device; + int32_t focal_length; + int32_t f_number; + int32_t vertical_angle_of_view; + int32_t camera_position_x; + int32_t camera_position_y; + int32_t camera_position_z; + int32_t camera_direction_x; + int32_t camera_direction_y; + int32_t camera_direction_z; + int32_t image_plane_vertical_x; + int32_t image_plane_vertical_y; + int32_t image_plane_vertical_z; +}; + +/* ! SNRParameters */ +struct SNRParameters_s { + double snr_y; /* !< current Y SNR */ + double snr_u; /* !< current U SNR */ + double snr_v; /* !< current V SNR */ + double snr_y1; /* !< SNR Y(dB) first frame */ + double snr_u1; /* !< SNR U(dB) first frame */ + double snr_v1; /* !< SNR V(dB) first frame */ + double snr_ya; /* !< Average SNR Y(dB) remaining frames */ + double snr_ua; /* !< Average SNR U(dB) remaining frames */ + double snr_va; /* !< Average SNR V(dB) remaining frames */ +#if INTERLACE_CODING + double i_snr_ya; /* !< current Y SNR */ + double i_snr_ua; /* !< current U SNR */ + double i_snr_va; /* !< current V SNR */ +#endif +}; + +/* signal to noise ratio parameters */ + +/* ! codingUnit */ +struct codingUnit { + uint32_t ui_MbBitSize; + int32_t uiBitSize; /* size of MB */ + /* !< number of current syntax element */ + int32_t currSEnr; + int32_t slice_nr; + int32_t delta_quant; /* !< for rate control */ + int32_t delta_qp; + int32_t qp; + int32_t bitcounter[MAX_BITCOUNTER_MB]; + struct codingUnit + *mb_available[3][3]; /*!< pointer to neighboring MBs + in a 3x3 window of current MB, which is located at [1][1] \n + NULL pointer identifies neighboring MBs which are unavailable */ + /* some storage of codingUnit syntax elements for global access */ + int32_t cuType; + int32_t weighted_skipmode; + + int32_t md_directskip_mode; + + int32_t trans_size; + int + /* !< indices correspond to [forw,backw][block_y][block_x][x,y, dmh] */ + mvd[2][BLOCK_MULTIPLE][BLOCK_MULTIPLE][3]; + + int32_t intra_pred_modes[BLOCK_MULTIPLE * BLOCK_MULTIPLE]; + int32_t real_intra_pred_modes[BLOCK_MULTIPLE * BLOCK_MULTIPLE]; + int32_t l_ipred_mode; + int32_t cbp, cbp_blk; + uint32_t cbp_bits; + + int32_t b8mode[4]; + int32_t b8pdir[4]; + /* !< chroma intra prediction mode */ + int32_t c_ipred_mode; + + /* !< pointer to neighboring MB (AEC) */ + struct codingUnit *mb_available_up; + /* !< pointer to neighboring MB (AEC) */ + struct codingUnit *mb_available_left; + int32_t mbAddrA, mbAddrB, mbAddrC, mbAddrD; + /* ! +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../../stream_input/amports/amports_priv.h" +#include +#include "../utils/decoder_mmu_box.h" +#include "../utils/decoder_bmmu_box.h" +#include "avs2_global.h" + +#define MEM_NAME "codec_avs2" +/* #include */ +#include +#include "../utils/vdec.h" +#include "../utils/amvdec.h" + +#include +#include +#include "../utils/config_parser.h" +#include "../utils/firmware.h" + +#define MIX_STREAM_SUPPORT +#define SUPPORT_4K2K + +#define G12A_BRINGUP_DEBUG + +#include "vavs2.h" +#define HEVC_SHIFT_LENGTH_PROTECT 0x313a +#define HEVC_MPRED_CTRL9 0x325b +#define HEVC_DBLK_CFGD 0x350d + + +#define HEVC_CM_HEADER_START_ADDR 0x3628 +#define HEVC_DBLK_CFGB 0x350b +#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464 +#define HEVC_SAO_MMU_VH1_ADDR 0x363b +#define HEVC_SAO_MMU_VH0_ADDR 0x363a +#define HEVC_SAO_MMU_STATUS 0x3639 + +/* + * AVS2_DEC_STATUS define +*/ +/*internal*/ +#define AVS2_DEC_IDLE 0 +#define AVS2_SEQUENCE 1 +#define AVS2_I_PICTURE 2 +#define AVS2_PB_PICTURE 3 +#define AVS2_DISCARD_STARTCODE 4 +#define AVS2_DISCARD_NAL 4 + +#define AVS2_SLICE_DECODING 6 + +#define SWAP_IN_CMD 0x10 +#define SWAP_OUT_CMD 0x11 +#define SWAP_OUTIN_CMD 0x12 +#define SWAP_DONE 0x13 +#define SWAP_POST_INIT 0x14 + +/*head*/ +#define AVS2_HEAD_SEQ_READY 0x21 +#define AVS2_HEAD_PIC_I_READY 0x22 +#define AVS2_HEAD_PIC_PB_READY 0x23 +#define AVS2_HEAD_SEQ_END_READY 0x24 +#define AVS2_STARTCODE_SEARCH_DONE 0x25 + +/*pic done*/ +#define HEVC_DECPIC_DATA_DONE 0x30 +#define HEVC_DECPIC_DATA_ERROR 0x31 +#define HEVC_NAL_DECODE_DONE 0x32 +#define AVS2_DECODE_BUFEMPTY 0x33 +#define AVS2_DECODE_TIMEOUT 0x34 +#define AVS2_DECODE_OVER_SIZE 0x35 +#define AVS2_EOS 0x36 + +/*cmd*/ +#define AVS2_10B_DISCARD_NAL 0xf0 +#define AVS2_ACTION_ERROR 0xfe +#define HEVC_ACTION_ERROR 0xfe +#define AVS2_ACTION_DONE 0xff +/*AVS2_DEC_STATUS end*/ + + +#define VF_POOL_SIZE 32 + +#undef pr_info +#define pr_info printk + +#define DECODE_MODE_SINGLE (0 | (0x80 << 24)) +#define DECODE_MODE_MULTI_STREAMBASE (1 | (0x80 << 24)) +#define DECODE_MODE_MULTI_FRAMEBASE (2 | (0x80 << 24)) + + +#define VP9_TRIGGER_FRAME_DONE 0x100 +#define VP9_TRIGGER_FRAME_ENABLE 0x200 + +/*#define MV_MEM_UNIT 0x240*/ +#define MV_MEM_UNIT 0x200 +/*--------------------------------------------------- + Include "parser_cmd.h" +---------------------------------------------------*/ +#define PARSER_CMD_SKIP_CFG_0 0x0000090b + +#define PARSER_CMD_SKIP_CFG_1 0x1b14140f + +#define PARSER_CMD_SKIP_CFG_2 0x001b1910 + +#define PARSER_CMD_NUMBER 37 + +/*#define HEVC_PIC_STRUCT_SUPPORT*/ +/* to remove, fix build error */ + +/*#define CODEC_MM_FLAGS_FOR_VDECODER 0*/ + +#define MULTI_INSTANCE_SUPPORT +/* #define ERROR_HANDLE_DEBUG */ +#if 0 /* MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8B*/ +#undef SUPPORT_4K2K +#else +#define SUPPORT_4K2K +#endif + +#ifndef STAT_KTHREAD +#define STAT_KTHREAD 0x40 +#endif + +#ifdef MULTI_INSTANCE_SUPPORT +#define MAX_DECODE_INSTANCE_NUM 9 +#define MULTI_DRIVER_NAME "ammvdec_avs2" + +#define lock_buffer(dec, flags) \ + spin_lock_irqsave(&dec->buffer_lock, flags) + +#define unlock_buffer(dec, flags) \ + spin_unlock_irqrestore(&dec->buffer_lock, flags) + +static unsigned int max_decode_instance_num + = MAX_DECODE_INSTANCE_NUM; +static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM]; +static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM]; +static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM]; +static unsigned int run_count[MAX_DECODE_INSTANCE_NUM]; +static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM]; +static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM]; + +#ifdef G12A_BRINGUP_DEBUG +static u32 decode_timeout_val; +#else +static u32 decode_timeout_val = 200; +#endif +static int start_decode_buf_level = 0x8000; +#ifdef AVS2_10B_MMU +static u32 work_buf_size; /* = 24 * 1024 * 1024*/; +#else +static u32 work_buf_size = 32 * 1024 * 1024; +#endif + +static u32 mv_buf_margin; + +/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */ +/* double_write_mode: 0, no double write + 1, 1:1 ratio + 2, (1/4):(1/4) ratio + 4, (1/2):(1/2) ratio + 0x10, double write only +*/ +static u32 double_write_mode; + +#define DRIVER_NAME "amvdec_avs2" +#define MODULE_NAME "amvdec_avs2" +#define DRIVER_HEADER_NAME "amvdec_avs2_header" + + +#define PUT_INTERVAL (HZ/100) +#define ERROR_SYSTEM_RESET_COUNT 200 + +#define PTS_NORMAL 0 +#define PTS_NONE_REF_USE_DURATION 1 + +#define PTS_MODE_SWITCHING_THRESHOLD 3 +#define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3 + +#define DUR2PTS(x) ((x)*90/96) + +struct AVS2Decoder_s; +static int vavs2_vf_states(struct vframe_states *states, void *); +static struct vframe_s *vavs2_vf_peek(void *); +static struct vframe_s *vavs2_vf_get(void *); +static void vavs2_vf_put(struct vframe_s *, void *); +static int vavs2_event_cb(int type, void *data, void *private_data); +static void set_vframe(struct AVS2Decoder_s *dec, + struct vframe_s *vf, struct avs2_frame_s *pic, u8 dummy); + +static int vavs2_stop(struct AVS2Decoder_s *dec); +static s32 vavs2_init(struct vdec_s *vdec); +static void vavs2_prot_init(struct AVS2Decoder_s *dec); +static int vavs2_local_init(struct AVS2Decoder_s *dec); +static void vavs2_put_timer_func(unsigned long arg); +static void dump_data(struct AVS2Decoder_s *dec, int size); +static unsigned char get_data_check_sum + (struct AVS2Decoder_s *dec, int size); +static void dump_pic_list(struct AVS2Decoder_s *dec); + +static const char vavs2_dec_id[] = "vavs2-dev"; + +#define PROVIDER_NAME "decoder.avs2" +#define MULTI_INSTANCE_PROVIDER_NAME "vdec.avs2" + +static const struct vframe_operations_s vavs2_vf_provider = { + .peek = vavs2_vf_peek, + .get = vavs2_vf_get, + .put = vavs2_vf_put, + .event_cb = vavs2_event_cb, + .vf_states = vavs2_vf_states, +}; + +static struct vframe_provider_s vavs2_vf_prov; + +static u32 bit_depth_luma; +static u32 bit_depth_chroma; +static u32 frame_width; +static u32 frame_height; +static u32 video_signal_type; +static u32 pts_unstable; +static u32 on_no_keyframe_skiped; + + +#define PROB_SIZE (496 * 2 * 4) +#define PROB_BUF_SIZE (0x5000) +#define COUNT_BUF_SIZE (0x300 * 4 * 4) +/*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/ +#define MAX_FRAME_4K_NUM 0x1200 +#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4) + +static inline int div_r32(int64_t m, int n) +{ +/* +return (int)(m/n) +*/ +#ifndef CONFIG_ARM64 + do_div(m, n); + return (int)m; +#else + return (int)(m/n); +#endif +} + +enum vpx_bit_depth_t { + AVS2_BITS_8 = 8, /**< 8 bits */ + AVS2_BITS_10 = 10, /**< 10 bits */ + AVS2_BITS_12 = 12, /**< 12 bits */ +}; + +/*USE_BUF_BLOCK*/ +struct BUF_s { + int index; + unsigned int alloc_flag; + /*buffer */ + unsigned int cma_page_count; + unsigned long alloc_addr; + unsigned long start_adr; + unsigned int size; + + unsigned int free_start_adr; +} /*BUF_t */; + +struct MVBUF_s { + unsigned long start_adr; + unsigned int size; + int used_flag; +} /*MVBUF_t */; + + /* #undef BUFMGR_ONLY to enable hardware configuration */ + +/*#define TEST_WR_PTR_INC*/ +#define WR_PTR_INC_NUM 128 + +#define SIMULATION +#define DOS_PROJECT +#undef MEMORY_MAP_IN_REAL_CHIP + +/*#undef DOS_PROJECT*/ +/*#define MEMORY_MAP_IN_REAL_CHIP*/ + +/*#define BUFFER_MGR_ONLY*/ +/*#define CONFIG_HEVC_CLK_FORCED_ON*/ +/*#define ENABLE_SWAP_TEST*/ + +#ifdef AVS2_10B_NV21 +#define MEM_MAP_MODE 2 /* 0:linear 1:32x32 2:64x32*/ +#else +#define MEM_MAP_MODE 0 /* 0:linear 1:32x32 2:64x32*/ +#endif + +#ifdef AVS2_10B_NV21 +#else +#define LOSLESS_COMPRESS_MODE +#endif + +#define DOUBLE_WRITE_YSTART_TEMP 0x02000000 +#define DOUBLE_WRITE_CSTART_TEMP 0x02900000 + + + +typedef unsigned int u32; +typedef unsigned short u16; + +#define AVS2_DBG_BUFMGR 0x01 +#define AVS2_DBG_BUFMGR_MORE 0x02 +#define AVS2_DBG_BUFMGR_DETAIL 0x04 +#define AVS2_DBG_IRQ_EVENT 0x08 +#define AVS2_DBG_OUT_PTS 0x10 +#define AVS2_DBG_PRINT_SOURCE_LINE 0x20 +#define AVS2_DBG_PRINT_PARAM 0x40 +#define AVS2_DBG_SEND_PARAM_WITH_REG 0x100 +#define AVS2_DBG_MERGE 0x200 +#define AVS2_DBG_DBG_LF_PRINT 0x400 +#define AVS2_DBG_REG 0x800 +#define AVS2_DBG_DIS_LOC_ERROR_PROC 0x10000 +#define AVS2_DBG_DIS_SYS_ERROR_PROC 0x20000 +#define AVS2_DBG_DUMP_PIC_LIST 0x40000 +#define AVS2_DBG_TRIG_SLICE_SEGMENT_PROC 0x80000 +#define AVS2_DBG_HW_RESET 0x100000 +#define AVS2_DBG_LOAD_UCODE_FROM_FILE 0x200000 +#define AVS2_DBG_FORCE_SEND_AGAIN 0x400000 +#define AVS2_DBG_DUMP_DATA 0x800000 +#define AVS2_DBG_CACHE 0x1000000 +#define AVS2_DBG_CACHE_HIT_RATE 0x2000000 +#define IGNORE_PARAM_FROM_CONFIG 0x8000000 +/*MULTI_INSTANCE_SUPPORT*/ +#define PRINT_FLAG_ERROR 0 +#define PRINT_FLAG_VDEC_STATUS 0x20000000 +#define PRINT_FLAG_VDEC_DETAIL 0x40000000 +#define PRINT_FLAG_VDEC_DATA 0x80000000 + +#define PRINT_LINE() \ + if (debug & AVS2_DBG_PRINT_SOURCE_LINE)\ + pr_info("%s line %d\n", __func__, __LINE__) + +static u32 debug; + +bool is_avs2_print_param(void) +{ + bool ret = false; + if (debug & AVS2_DBG_PRINT_PARAM) + ret = true; + return ret; +} + +bool is_avs2_print_bufmgr_detail(void) +{ + bool ret = false; + if (debug & AVS2_DBG_BUFMGR_DETAIL) + ret = true; + return ret; +} +static bool is_reset; +/*for debug*/ +/* + udebug_flag: + bit 0, enable ucode print + bit 1, enable ucode detail print + bit [31:16] not 0, pos to dump lmem + bit 2, pop bits to lmem + bit [11:8], pre-pop bits for alignment (when bit 2 is 1) +*/ +static u32 udebug_flag; +/* + when udebug_flag[1:0] is not 0 + udebug_pause_pos not 0, + pause position +*/ +static u32 udebug_pause_pos; +/* + when udebug_flag[1:0] is not 0 + and udebug_pause_pos is not 0, + pause only when DEBUG_REG2 is equal to this val +*/ +static u32 udebug_pause_val; + +static u32 udebug_pause_decode_idx; + +static u32 force_disp_pic_index; + +#define DEBUG_REG +#ifdef DEBUG_REG +static void WRITE_VREG_DBG2(unsigned adr, unsigned val) +{ + if (debug & AVS2_DBG_REG) + pr_info("%s(%x, %x)\n", __func__, adr, val); + if (adr != 0) + WRITE_VREG(adr, val); +} + +#undef WRITE_VREG +#define WRITE_VREG WRITE_VREG_DBG2 +#endif + + +#ifdef AVS2_10B_MMU +#define MMU_COMPRESS_HEADER_SIZE 0x48000 +#endif + +#define INVALID_IDX -1 /* Invalid buffer index.*/ + + +#define FRAME_BUFFERS (AVS2_MAX_BUFFER_NUM) +#define HEADER_FRAME_BUFFERS (FRAME_BUFFERS) +#define MAX_BUF_NUM (FRAME_BUFFERS) + +#define FRAME_CONTEXTS_LOG2 2 +#define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2) +/*buffer + header buffer + workspace*/ +#ifdef MV_USE_FIXED_BUF +#define MAX_BMMU_BUFFER_NUM (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + 1) +#define VF_BUFFER_IDX(n) (n) +#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n) +#define WORK_SPACE_BUF_ID (FRAME_BUFFERS + HEADER_FRAME_BUFFERS) +#else +#define MAX_BMMU_BUFFER_NUM ((FRAME_BUFFERS * 2) + HEADER_FRAME_BUFFERS + 1) +#define VF_BUFFER_IDX(n) (n) +#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n) +#define MV_BUFFER_IDX(n) ((FRAME_BUFFERS * 2) + n) +#define WORK_SPACE_BUF_ID ((FRAME_BUFFERS * 2) + HEADER_FRAME_BUFFERS) +#endif +/* +static void set_canvas(struct AVS2Decoder_s *dec, + struct avs2_frame_s *pic); +int avs2_prepare_display_buf(struct AVS2Decoder_s *dec, + int pos); +*/ + + +struct buff_s { + u32 buf_start; + u32 buf_size; + u32 buf_end; +}; + +struct BuffInfo_s { + u32 max_width; + u32 max_height; + u32 start_adr; + u32 end_adr; + struct buff_s ipp; + struct buff_s sao_abv; + struct buff_s sao_vb; + struct buff_s short_term_rps; + struct buff_s rcs; + struct buff_s sps; + struct buff_s pps; + struct buff_s sao_up; + struct buff_s swap_buf; + struct buff_s swap_buf2; + struct buff_s scalelut; + struct buff_s dblk_para; + struct buff_s dblk_data; + struct buff_s dblk_data2; +#ifdef AVS2_10B_MMU + struct buff_s mmu_vbh; + struct buff_s cm_header; +#endif + struct buff_s mpred_above; +#ifdef MV_USE_FIXED_BUF + struct buff_s mpred_mv; +#endif + struct buff_s rpm; + struct buff_s lmem; +}; + +#define DEC_RESULT_NONE 0 +#define DEC_RESULT_DONE 1 +#define DEC_RESULT_AGAIN 2 +#define DEC_RESULT_CONFIG_PARAM 3 +#define DEC_RESULT_ERROR 4 +#define DEC_INIT_PICLIST 5 +#define DEC_UNINIT_PICLIST 6 +#define DEC_RESULT_GET_DATA 7 +#define DEC_RESULT_GET_DATA_RETRY 8 +#define DEC_RESULT_EOS 9 +#define DEC_RESULT_FORCE_EXIT 10 + +static void avs2_work(struct work_struct *work); +struct loop_filter_info_n; +struct loopfilter; +struct segmentation; + +struct AVS2Decoder_s { + int pic_list_init_flag; + unsigned char index; + spinlock_t buffer_lock; + struct device *cma_dev; + struct platform_device *platform_dev; + void (*vdec_cb)(struct vdec_s *, void *); + void *vdec_cb_arg; + struct vframe_chunk_s *chunk; + int dec_result; + struct work_struct work; + u32 start_shift_bytes; + + struct BuffInfo_s work_space_buf_store; + unsigned long buf_start; + u32 buf_size; + u32 cma_alloc_count; + unsigned long cma_alloc_addr; + uint8_t eos; + unsigned long int start_process_time; + unsigned last_lcu_idx; + int decode_timeout_count; + unsigned timeout_num; + + int double_write_mode; + + unsigned char m_ins_flag; + char *provider_name; + int frame_count; + u32 stat; + struct timer_list timer; + u32 frame_dur; + u32 frame_ar; + int fatal_error; + uint8_t init_flag; + uint8_t process_busy; +#define PROC_STATE_INIT 0 +#define PROC_STATE_DECODESLICE 1 +#define PROC_STATE_SENDAGAIN 2 + uint8_t process_state; + u32 ucode_pause_pos; + + int show_frame_num; +#ifndef AVS2_10B_MMU + struct buff_s mc_buf_spec; +#endif + struct dec_sysinfo vavs2_amstream_dec_info; + void *rpm_addr; + void *lmem_addr; + dma_addr_t rpm_phy_addr; + dma_addr_t lmem_phy_addr; + unsigned short *lmem_ptr; + unsigned short *debug_ptr; + +#if 1 + /*AVS2_10B_MMU*/ + void *frame_mmu_map_addr; + dma_addr_t frame_mmu_map_phy_addr; +#endif + unsigned int use_cma_flag; + + struct BUF_s m_BUF[MAX_BUF_NUM]; + struct MVBUF_s m_mv_BUF[MAX_BUF_NUM]; + u32 used_buf_num; + DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE); + DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE); + DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE); + struct vframe_s vfpool[VF_POOL_SIZE]; + u32 vf_pre_count; + u32 vf_get_count; + u32 vf_put_count; + int buf_num; + unsigned int losless_comp_body_size; + + u32 video_signal_type; + + int pts_mode; + int last_lookup_pts; + int last_pts; + u64 last_lookup_pts_us64; + u64 last_pts_us64; + u64 shift_byte_count; + u32 shift_byte_count_lo; + u32 shift_byte_count_hi; + int pts_mode_switching_count; + int pts_mode_recovery_count; + + bool get_frame_dur; + u32 saved_resolution; + + /**/ + int refresh_frame_flags; + uint8_t hold_ref_buf; + struct BuffInfo_s *work_space_buf; +#ifndef AVS2_10B_MMU + struct buff_s *mc_buf; +#endif + unsigned int frame_width; + unsigned int frame_height; + + unsigned short *rpm_ptr; + int init_pic_w; + int init_pic_h; + + int slice_type; + + int decode_idx; + int slice_idx; + uint8_t wait_buf; + uint8_t error_flag; + + /* bit 0, for decoding; bit 1, for displaying */ + uint8_t ignore_bufmgr_error; + int PB_skip_mode; + int PB_skip_count_after_decoding; + /*hw*/ + + /**/ + struct vdec_info *gvs; + + + unsigned int dec_status; + u32 last_put_idx; + int new_frame_displayed; + void *mmu_box; + void *bmmu_box; + struct vframe_master_display_colour_s vf_dp; + struct firmware_s *fw; +#ifdef AVS2_10B_MMU + int cur_fb_idx_mmu; + long used_4k_num; +#endif + struct avs2_decoder avs2_dec; +#define ALF_NUM_BIT_SHIFT 6 +#define NO_VAR_BINS 16 + int32_t m_filterCoeffSym[16][9]; + int32_t m_varIndTab[NO_VAR_BINS]; + + struct vframe_s vframe_dummy; + +}; + +static int compute_losless_comp_body_size( + struct AVS2Decoder_s *dec, int width, int height, + uint8_t is_bit_depth_10); + +static int avs2_print(struct AVS2Decoder_s *dec, + int flag, const char *fmt, ...) +{ +#define HEVC_PRINT_BUF 256 + unsigned char buf[HEVC_PRINT_BUF]; + int len = 0; + if (dec == NULL || + (flag == 0) || + (debug & flag)) { + va_list args; + va_start(args, fmt); + if (dec) + len = sprintf(buf, "[%d]", dec->index); + vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args); + pr_info("%s", buf); + va_end(args); + } + return 0; +} + +static int avs2_print_cont(struct AVS2Decoder_s *dec, + int flag, const char *fmt, ...) +{ + unsigned char buf[HEVC_PRINT_BUF]; + int len = 0; + if (dec == NULL || + (flag == 0) || + (debug & flag)) { + va_list args; + va_start(args, fmt); + vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args); + pr_info("%s", buf); + va_end(args); + } + return 0; +} + +static void reset_process_time(struct AVS2Decoder_s *dec) +{ + if (dec->start_process_time) { + unsigned process_time = + 1000 * (jiffies - dec->start_process_time) / HZ; + dec->start_process_time = 0; + if (process_time > max_process_time[dec->index]) + max_process_time[dec->index] = process_time; + } +} + +static void start_process_time(struct AVS2Decoder_s *dec) +{ + dec->start_process_time = jiffies; + dec->decode_timeout_count = 0; + dec->last_lcu_idx = 0; +} + +static void timeout_process(struct AVS2Decoder_s *dec) +{ + dec->timeout_num++; + amhevc_stop(); + avs2_print(dec, + 0, "%s decoder timeout\n", __func__); + + dec->dec_result = DEC_RESULT_DONE; + reset_process_time(dec); + vdec_schedule_work(&dec->work); +} + +static u32 get_valid_double_write_mode(struct AVS2Decoder_s *dec) +{ + return (dec->m_ins_flag && + ((double_write_mode & 0x80000000) == 0)) ? + dec->double_write_mode : + (double_write_mode & 0x7fffffff); +} + +static int get_double_write_mode(struct AVS2Decoder_s *dec) +{ + u32 valid_dw_mode = get_valid_double_write_mode(dec); + u32 dw; + if (valid_dw_mode == 0x100) { + int w = dec->avs2_dec.img.width; + int h = dec->avs2_dec.img.height; + if (w > 1920 && h > 1088) + dw = 0x4; /*1:2*/ + else + dw = 0x1; /*1:1*/ + + return dw; + } + + return valid_dw_mode; +} + +/* for double write buf alloc */ +static int get_double_write_mode_init(struct AVS2Decoder_s *dec) +{ + u32 valid_dw_mode = get_valid_double_write_mode(dec); + if (valid_dw_mode == 0x100) { + u32 dw; + int w = dec->init_pic_w; + int h = dec->init_pic_h; + if (w > 1920 && h > 1088) + dw = 0x4; /*1:2*/ + else + dw = 0x1; /*1:1*/ + + return dw; + } + return valid_dw_mode; +} + +static int get_double_write_ratio(struct AVS2Decoder_s *dec, + int dw_mode) +{ + int ratio = 1; + if ((dw_mode == 2) || + (dw_mode == 3)) + ratio = 4; + else if (dw_mode == 4) + ratio = 2; + return ratio; +} + +#define MAX_4K_NUM 0x1200 +#ifdef AVS2_10B_MMU +int avs2_alloc_mmu( + struct AVS2Decoder_s *dec, + int cur_buf_idx, + int pic_width, + int pic_height, + unsigned short bit_depth, + unsigned int *mmu_index_adr) +{ + int bit_depth_10 = (bit_depth == AVS2_BITS_10); + int picture_size; + int cur_mmu_4k_number; + + picture_size = compute_losless_comp_body_size( + dec, pic_width, pic_height, + bit_depth_10); + cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12); + if (cur_mmu_4k_number > MAX_4K_NUM) { + pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n", + cur_mmu_4k_number, pic_width, pic_height); + return -1; + } + return decoder_mmu_box_alloc_idx( + dec->mmu_box, + cur_buf_idx, + cur_mmu_4k_number, + mmu_index_adr); +} +#endif + +#ifndef MV_USE_FIXED_BUF +static void dealloc_mv_bufs(struct AVS2Decoder_s *dec) +{ + int i; + for (i = 0; i < FRAME_BUFFERS; i++) { + if (dec->m_mv_BUF[i].start_adr) { + if (debug) + pr_info( + "dealloc mv buf(%d) adr %ld size 0x%x used_flag %d\n", + i, dec->m_mv_BUF[i].start_adr, + dec->m_mv_BUF[i].size, + dec->m_mv_BUF[i].used_flag); + decoder_bmmu_box_free_idx( + dec->bmmu_box, + MV_BUFFER_IDX(i)); + dec->m_mv_BUF[i].start_adr = 0; + dec->m_mv_BUF[i].size = 0; + dec->m_mv_BUF[i].used_flag = 0; + } + } +} + +static int alloc_mv_buf(struct AVS2Decoder_s *dec, + int i, int size) +{ + int ret = 0; + if (decoder_bmmu_box_alloc_buf_phy + (dec->bmmu_box, + MV_BUFFER_IDX(i), size, + DRIVER_NAME, + &dec->m_mv_BUF[i].start_adr) < 0) { + dec->m_mv_BUF[i].start_adr = 0; + ret = -1; + } else { + dec->m_mv_BUF[i].size = size; + dec->m_mv_BUF[i].used_flag = 0; + ret = 0; + if (debug) { + pr_info( + "MV Buffer %d: start_adr %p size %x\n", + i, + (void *)dec->m_mv_BUF[i].start_adr, + dec->m_mv_BUF[i].size); + } + } + return ret; +} + +static int init_mv_buf_list(struct AVS2Decoder_s *dec) +{ + int i; + int ret = 0; + int count = FRAME_BUFFERS; + int pic_width = dec->init_pic_w; + int pic_height = dec->init_pic_h; + int lcu_size = 64; /*fixed 64*/ + int pic_width_64 = (pic_width + 63) & (~0x3f); + int pic_height_32 = (pic_height + 31) & (~0x1f); + int pic_width_lcu = (pic_width_64 % lcu_size) ? + pic_width_64 / lcu_size + 1 + : pic_width_64 / lcu_size; + int pic_height_lcu = (pic_height_32 % lcu_size) ? + pic_height_32 / lcu_size + 1 + : pic_height_32 / lcu_size; + int lcu_total = pic_width_lcu * pic_height_lcu; + int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) & + (~0xffff); + if (mv_buf_margin > 0) + count = dec->avs2_dec.ref_maxbuffer + mv_buf_margin; + for (i = 0; i < count; i++) { + if (alloc_mv_buf(dec, i, size) < 0) { + ret = -1; + break; + } + } + return ret; +} +#if 0 + +static int get_mv_buf(struct AVS2Decoder_s *dec, + struct avs2_frame_s *pic) +{ + int i; + int ret = -1; + for (i = 0; i < FRAME_BUFFERS; i++) { + if (dec->m_mv_BUF[i].start_adr && + dec->m_mv_BUF[i].used_flag == 0) { + dec->m_mv_BUF[i].used_flag = 1; + ret = i; + break; + } + } + + if (ret >= 0) { + pic->mv_buf_index = ret; + pic->mpred_mv_wr_start_addr = + (dec->m_mv_BUF[ret].start_adr + 0xffff) & + (~0xffff); + if (debug & AVS2_DBG_BUFMGR_MORE) + pr_info( + "%s => %d (%d) size 0x%x\n", + __func__, ret, + pic->mpred_mv_wr_start_addr, + dec->m_mv_BUF[ret].size); + } else { + pr_info( + "%s: Error, mv buf is not enough\n", + __func__); + } + return ret; +} + +static void put_mv_buf(struct AVS2Decoder_s *dec, + struct avs2_frame_s *pic) +{ + int i = pic->mv_buf_index; + if (i >= FRAME_BUFFERS) { + if (debug & AVS2_DBG_BUFMGR_MORE) + pr_info( + "%s: index %d beyond range\n", + __func__, i); + return; + } + if (debug & AVS2_DBG_BUFMGR_MORE) + pr_info( + "%s(%d): used_flag(%d)\n", + __func__, i, + dec->m_mv_BUF[i].used_flag); + + pic->mv_buf_index = -1; + if (dec->m_mv_BUF[i].start_adr && + dec->m_mv_BUF[i].used_flag) + dec->m_mv_BUF[i].used_flag = 0; +} + +static void put_un_used_mv_bufs(struct AVS2Decoder_s *dec) +{ + struct VP9_Common_s *const cm = &dec->common; + struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs; + int i; + for (i = 0; i < dec->used_buf_num; ++i) { + if ((frame_bufs[i].ref_count == 0) && + (frame_bufs[i].buf.index != -1) && + (frame_bufs[i].buf.mv_buf_index >= 0) + ) + put_mv_buf(dec, &frame_bufs[i].buf); + } +} +#endif + +#endif + +static int get_free_buf_count(struct AVS2Decoder_s *dec) +{ + struct avs2_decoder *avs2_dec = &dec->avs2_dec; + int i; + int count = 0; + for (i = 0; i < avs2_dec->ref_maxbuffer; i++) { + if ((avs2_dec->fref[i]->imgcoi_ref < -256 +#if 0 + || abs(avs2_dec->fref[i]-> + imgtr_fwRefDistance - img->tr) >= 128 +#endif + ) && avs2_dec->fref[i]->is_output == -1 + && avs2_dec->fref[i]->bg_flag == 0 +#ifndef NO_DISPLAY + && avs2_dec->fref[i]->vf_ref == 0 +#endif + ) { + count++; + } + } + + return count; +} + + +int avs2_bufmgr_init(struct AVS2Decoder_s *dec, struct BuffInfo_s *buf_spec_i, + struct buff_s *mc_buf_i) { + + dec->frame_count = 0; +#ifdef AVS2_10B_MMU + dec->used_4k_num = -1; + dec->cur_fb_idx_mmu = INVALID_IDX; +#endif + + + /* private init */ + dec->work_space_buf = buf_spec_i; +#ifndef AVS2_10B_MMU + dec->mc_buf = mc_buf_i; +#endif + dec->rpm_addr = NULL; + dec->lmem_addr = NULL; + + dec->use_cma_flag = 0; + dec->decode_idx = 0; + dec->slice_idx = 0; + /*int m_uiMaxCUWidth = 1<<7;*/ + /*int m_uiMaxCUHeight = 1<<7;*/ + dec->wait_buf = 0; + dec->error_flag = 0; + + dec->pts_mode = PTS_NORMAL; + dec->last_pts = 0; + dec->last_lookup_pts = 0; + dec->last_pts_us64 = 0; + dec->last_lookup_pts_us64 = 0; + dec->shift_byte_count = 0; + dec->shift_byte_count_lo = 0; + dec->shift_byte_count_hi = 0; + dec->pts_mode_switching_count = 0; + dec->pts_mode_recovery_count = 0; + + dec->buf_num = 0; + + return 0; +} + + + +#define HEVC_CM_BODY_START_ADDR 0x3626 +#define HEVC_CM_BODY_LENGTH 0x3627 +#define HEVC_CM_HEADER_LENGTH 0x3629 +#define HEVC_CM_HEADER_OFFSET 0x362b + +#define LOSLESS_COMPRESS_MODE + +/*#define DECOMP_HEADR_SURGENT*/ + +static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */ +static u32 enable_mem_saving = 1; +static u32 force_w_h; + +static u32 force_fps; + + +const u32 avs2_version = 201602101; +static u32 debug; +static u32 radr; +static u32 rval; +static u32 pop_shorts; +static u32 dbg_cmd; +static u32 dbg_skip_decode_index; +static u32 endian = 0xff0; +#ifdef ERROR_HANDLE_DEBUG +static u32 dbg_nal_skip_flag; + /* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */ +static u32 dbg_nal_skip_count; +#endif +/*for debug*/ +static u32 decode_pic_begin; +static uint slice_parse_begin; +static u32 step; +#ifdef MIX_STREAM_SUPPORT +#ifdef SUPPORT_4K2K +static u32 buf_alloc_width = 4096; +static u32 buf_alloc_height = 2304; +#else +static u32 buf_alloc_width = 1920; +static u32 buf_alloc_height = 1088; +#endif +static u32 dynamic_buf_num_margin; +#else +static u32 buf_alloc_width; +static u32 buf_alloc_height; +static u32 dynamic_buf_num_margin = 7; +#endif +static u32 buf_alloc_depth = 10; +static u32 buf_alloc_size; +/* +bit[0]: 0, + bit[1]: 0, always release cma buffer when stop + bit[1]: 1, never release cma buffer when stop +bit[0]: 1, when stop, release cma buffer if blackout is 1; +do not release cma buffer is blackout is not 1 + +bit[2]: 0, when start decoding, check current displayed buffer + (only for buffer decoded by vp9) if blackout is 0 + 1, do not check current displayed buffer + +bit[3]: 1, if blackout is not 1, do not release current + displayed cma buffer always. +*/ +/* set to 1 for fast play; + set to 8 for other case of "keep last frame" +*/ +static u32 buffer_mode = 1; +/* buffer_mode_dbg: debug only*/ +static u32 buffer_mode_dbg = 0xffff0000; +/**/ + +/* +bit 0, 1: only display I picture; +bit 1, 1: only decode I picture; +*/ +static u32 i_only_flag; + + +static u32 max_decoding_time; +/* +error handling +*/ +/*error_handle_policy: +bit 0: 0, auto skip error_skip_nal_count nals before error recovery; +1, skip error_skip_nal_count nals before error recovery; +bit 1 (valid only when bit0 == 1): +1, wait vps/sps/pps after error recovery; +bit 2 (valid only when bit0 == 0): +0, auto search after error recovery (avs2_recover() called); +1, manual search after error recovery +(change to auto search after get IDR: WRITE_VREG(NAL_SEARCH_CTL, 0x2)) + +bit 4: 0, set error_mark after reset/recover + 1, do not set error_mark after reset/recover +bit 5: 0, check total lcu for every picture + 1, do not check total lcu + +*/ + +static u32 error_handle_policy; +/*static u32 parser_sei_enable = 1;*/ + +static u32 max_buf_num = (REF_BUFFER + 1); + +static u32 run_ready_min_buf_num = 2; + +static DEFINE_MUTEX(vavs2_mutex); + +#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0 +#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1 +#define HEVC_SHORT_TERM_RPS HEVC_ASSIST_SCRATCH_2 +#define HEVC_RCS_BUFFER HEVC_ASSIST_SCRATCH_3 +#define HEVC_SPS_BUFFER HEVC_ASSIST_SCRATCH_4 +#define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5 +#define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6 +#ifdef AVS2_10B_MMU +#define AVS2_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_7 +#else +#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7 +#endif +#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8 +/* +#define VP9_PROB_SWAP_BUFFER HEVC_ASSIST_SCRATCH_9 +#define VP9_COUNT_SWAP_BUFFER HEVC_ASSIST_SCRATCH_A +#define VP9_SEG_MAP_BUFFER HEVC_ASSIST_SCRATCH_B +*/ +#define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D +#define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E +#define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F +#define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_9 +#define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L +/*!!!*/ +#define HEVC_DECODE_COUNT HEVC_ASSIST_SCRATCH_M +#define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N +#define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G +#define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H + + +/* +ucode parser/search control +bit 0: 0, header auto parse; 1, header manual parse +bit 1: 0, auto skip for noneseamless stream; 1, no skip +bit [3:2]: valid when bit1==0; +0, auto skip nal before first vps/sps/pps/idr; +1, auto skip nal before first vps/sps/pps +2, auto skip nal before first vps/sps/pps, + and not decode until the first I slice (with slice address of 0) + +3, auto skip before first I slice (nal_type >=16 && nal_type<=21) +bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) ) +bit [16]: for NAL_UNIT_EOS when bit0 is 0: + 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm +bit [17]: for NAL_SEI when bit0 is 0: + 0, do not parse SEI in ucode; 1, parse SEI in ucode +bit [31:20]: used by ucode for debug purpose +*/ +#define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I + /*set before start decoder*/ +#define DECODE_MODE HEVC_ASSIST_SCRATCH_J +#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K + + /*read only*/ +#define CUR_NAL_UNIT_TYPE HEVC_ASSIST_SCRATCH_J + +#define RPM_BUF_SIZE (0x400 * 2) +#define LMEM_BUF_SIZE (0x400 * 2) + +#define WORK_BUF_SPEC_NUM 2 +static struct BuffInfo_s amvavs2_workbuff_spec[WORK_BUF_SPEC_NUM] = { + { + /* 8M bytes */ + .max_width = 1920, + .max_height = 1088, + .ipp = { + /* IPP work space calculation : + 4096 * (Y+CbCr+Flags) = 12k, round to 16k */ + .buf_size = 0x4000, + }, + .sao_abv = { + .buf_size = 0x30000, + }, + .sao_vb = { + .buf_size = 0x30000, + }, + .short_term_rps = { + /* SHORT_TERM_RPS - Max 64 set, 16 entry every set, + total 64x16x2 = 2048 bytes (0x800) */ + .buf_size = 0x800, + }, + .rcs = { + /* RCS STORE AREA - Max 32 RCS, each has 32 bytes, + total 0x0400 bytes */ + .buf_size = 0x400, + }, + .sps = { + /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, + total 0x0800 bytes*/ + .buf_size = 0x800, + }, + .pps = { + /*PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, + total 0x2000 bytes*/ + .buf_size = 0x2000, + }, + .sao_up = { + /* SAO UP STORE AREA - Max 640(10240/16) LCU, + each has 16 bytes total 0x2800 bytes */ + .buf_size = 0x2800, + }, + .swap_buf = { + /* 256cyclex64bit = 2K bytes 0x800 + (only 144 cycles valid) */ + .buf_size = 0x800, + }, + .swap_buf2 = { + .buf_size = 0x800, + }, + .scalelut = { + /* support up to 32 SCALELUT 1024x32 = + 32Kbytes (0x8000) */ + .buf_size = 0x8000, + }, + .dblk_para = { + /* DBLK -> Max 256(4096/16) LCU, + each para 1024bytes(total:0x40000), + data 1024bytes(total:0x40000)*/ + .buf_size = 0x40000, + }, + .dblk_data = { + .buf_size = 0x40000, + }, + .dblk_data2 = { + .buf_size = 0x40000, + }, +#ifdef AVS2_10B_MMU + .mmu_vbh = { + .buf_size = 0x5000, /*2*16*(more than 2304)/4, 4K*/ + }, +#if 0 + .cm_header = { + /*add one for keeper.*/ + .buf_size = MMU_COMPRESS_HEADER_SIZE * + (FRAME_BUFFERS + 1), + /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */ + }, +#endif +#endif + .mpred_above = { + .buf_size = 0x8000, /* 2 * size of hevc*/ + }, +#ifdef MV_USE_FIXED_BUF + .mpred_mv = {/* 1080p, 0x40000 per buffer */ + .buf_size = 0x40000 * FRAME_BUFFERS, + }, +#endif + .rpm = { + .buf_size = RPM_BUF_SIZE, + }, + .lmem = { + .buf_size = 0x400 * 2, + } + }, + { + .max_width = 4096, + .max_height = 2304, + .ipp = { + /* IPP work space calculation : + 4096 * (Y+CbCr+Flags) = 12k, round to 16k */ + .buf_size = 0x4000, + }, + .sao_abv = { + .buf_size = 0x30000, + }, + .sao_vb = { + .buf_size = 0x30000, + }, + .short_term_rps = { + /* SHORT_TERM_RPS - Max 64 set, 16 entry every set, + total 64x16x2 = 2048 bytes (0x800) */ + .buf_size = 0x800, + }, + .rcs = { + /* RCS STORE AREA - Max 16 RCS, each has 32 bytes, + total 0x0400 bytes */ + .buf_size = 0x400, + }, + .sps = { + /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, + total 0x0800 bytes */ + .buf_size = 0x800, + }, + .pps = { + /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, + total 0x2000 bytes */ + .buf_size = 0x2000, + }, + .sao_up = { + /* SAO UP STORE AREA - Max 640(10240/16) LCU, + each has 16 bytes total 0x2800 bytes */ + .buf_size = 0x2800, + }, + .swap_buf = { + /* 256cyclex64bit = 2K bytes 0x800 + (only 144 cycles valid) */ + .buf_size = 0x800, + }, + .swap_buf2 = { + .buf_size = 0x800, + }, + .scalelut = { + /* support up to 32 SCALELUT 1024x32 = 32Kbytes + (0x8000) */ + .buf_size = 0x8000, + }, + .dblk_para = { + /* DBLK -> Max 256(4096/16) LCU, + each para 1024bytes(total:0x40000), + data 1024bytes(total:0x40000)*/ + .buf_size = 0x80000, + }, + .dblk_data = { + /*DBLK -> Max 256(4096/16) LCU, + each para 1024bytes(total:0x40000), + data 1024bytes(total:0x40000)*/ + .buf_size = 0x80000, + }, + .dblk_data2 = { + .buf_size = 0x80000, + }, +#ifdef AVS2_10B_MMU + .mmu_vbh = { + .buf_size = 0x5000,/*2*16*(more than 2304)/4, 4K*/ + }, +#if 0 + .cm_header = { + /*add one for keeper.*/ + .buf_size = MMU_COMPRESS_HEADER_SIZE * + (FRAME_BUFFERS + 1), + /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */ + }, +#endif +#endif + .mpred_above = { + .buf_size = 0x10000, /* 2 * size of hevc*/ + }, +#ifdef MV_USE_FIXED_BUF + .mpred_mv = { + /* .buf_size = 0x100000*16, + //4k2k , 0x100000 per buffer */ + /* 4096x2304 , 0x120000 per buffer */ + .buf_size = 0x120000 * FRAME_BUFFERS, + }, +#endif + .rpm = { + .buf_size = RPM_BUF_SIZE, + }, + .lmem = { + .buf_size = 0x400 * 2, + } + } +}; + + +/*Losless compression body buffer size 4K per 64x32 (jt)*/ +static int compute_losless_comp_body_size(struct AVS2Decoder_s *dec, + int width, int height, + uint8_t is_bit_depth_10) +{ + int width_x64; + int height_x32; + int bsize; + width_x64 = width + 63; + width_x64 >>= 6; + height_x32 = height + 31; + height_x32 >>= 5; +#ifdef AVS2_10B_MMU + bsize = (is_bit_depth_10 ? 4096 : 3200) + * width_x64 * height_x32; +#else + bsize = (is_bit_depth_10 ? 4096 : 3072) + * width_x64 * height_x32; +#endif + avs2_print(dec, AVS2_DBG_BUFMGR_MORE, + "%s(%d,%d,%d)=>%d\n", + __func__, width, height, + is_bit_depth_10, bsize); + + return bsize; +} + +/* Losless compression header buffer size 32bytes per 128x64 (jt)*/ +static int compute_losless_comp_header_size(struct AVS2Decoder_s *dec, + int width, int height) +{ + int width_x128; + int height_x64; + int hsize; + width_x128 = width + 127; + width_x128 >>= 7; + height_x64 = height + 63; + height_x64 >>= 6; + + hsize = 32 * width_x128 * height_x64; + avs2_print(dec, AVS2_DBG_BUFMGR_MORE, + "%s(%d,%d)=>%d\n", + __func__, width, height, + hsize); + + return hsize; +} + +static void init_buff_spec(struct AVS2Decoder_s *dec, + struct BuffInfo_s *buf_spec) +{ + void *mem_start_virt; + buf_spec->ipp.buf_start = buf_spec->start_adr; + buf_spec->sao_abv.buf_start = + buf_spec->ipp.buf_start + buf_spec->ipp.buf_size; + + buf_spec->sao_vb.buf_start = + buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size; + buf_spec->short_term_rps.buf_start = + buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size; + buf_spec->rcs.buf_start = + buf_spec->short_term_rps.buf_start + + buf_spec->short_term_rps.buf_size; + buf_spec->sps.buf_start = + buf_spec->rcs.buf_start + buf_spec->rcs.buf_size; + buf_spec->pps.buf_start = + buf_spec->sps.buf_start + buf_spec->sps.buf_size; + buf_spec->sao_up.buf_start = + buf_spec->pps.buf_start + buf_spec->pps.buf_size; + buf_spec->swap_buf.buf_start = + buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size; + buf_spec->swap_buf2.buf_start = + buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size; + buf_spec->scalelut.buf_start = + buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size; + buf_spec->dblk_para.buf_start = + buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size; + buf_spec->dblk_data.buf_start = + buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size; + buf_spec->dblk_data2.buf_start = + buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size; +#ifdef AVS2_10B_MMU + buf_spec->mmu_vbh.buf_start = + buf_spec->dblk_data2.buf_start + buf_spec->dblk_data2.buf_size; + buf_spec->mpred_above.buf_start = + buf_spec->mmu_vbh.buf_start + buf_spec->mmu_vbh.buf_size; +#else + buf_spec->mpred_above.buf_start = + buf_spec->dblk_data2.buf_start + buf_spec->dblk_data2.buf_size; +#endif +#ifdef MV_USE_FIXED_BUF + buf_spec->mpred_mv.buf_start = + buf_spec->mpred_above.buf_start + + buf_spec->mpred_above.buf_size; + + buf_spec->rpm.buf_start = + buf_spec->mpred_mv.buf_start + + buf_spec->mpred_mv.buf_size; +#else + buf_spec->rpm.buf_start = + buf_spec->mpred_above.buf_start + + buf_spec->mpred_above.buf_size; + +#endif + buf_spec->lmem.buf_start = + buf_spec->rpm.buf_start + + buf_spec->rpm.buf_size; + buf_spec->end_adr = + buf_spec->lmem.buf_start + + buf_spec->lmem.buf_size; + + if (dec) { + mem_start_virt = + codec_mm_phys_to_virt(buf_spec->dblk_para.buf_start); + if (mem_start_virt) { + memset(mem_start_virt, 0, buf_spec->dblk_para.buf_size); + codec_mm_dma_flush(mem_start_virt, + buf_spec->dblk_para.buf_size, + DMA_TO_DEVICE); + } else { + /*not virt for tvp playing, + may need clear on ucode.*/ + pr_err("mem_start_virt failed\n"); + } + if (debug) { + pr_info("%s workspace (%x %x) size = %x\n", __func__, + buf_spec->start_adr, buf_spec->end_adr, + buf_spec->end_adr - buf_spec->start_adr); + } + if (debug) { + pr_info("ipp.buf_start :%x\n", + buf_spec->ipp.buf_start); + pr_info("sao_abv.buf_start :%x\n", + buf_spec->sao_abv.buf_start); + pr_info("sao_vb.buf_start :%x\n", + buf_spec->sao_vb.buf_start); + pr_info("short_term_rps.buf_start :%x\n", + buf_spec->short_term_rps.buf_start); + pr_info("rcs.buf_start :%x\n", + buf_spec->rcs.buf_start); + pr_info("sps.buf_start :%x\n", + buf_spec->sps.buf_start); + pr_info("pps.buf_start :%x\n", + buf_spec->pps.buf_start); + pr_info("sao_up.buf_start :%x\n", + buf_spec->sao_up.buf_start); + pr_info("swap_buf.buf_start :%x\n", + buf_spec->swap_buf.buf_start); + pr_info("swap_buf2.buf_start :%x\n", + buf_spec->swap_buf2.buf_start); + pr_info("scalelut.buf_start :%x\n", + buf_spec->scalelut.buf_start); + pr_info("dblk_para.buf_start :%x\n", + buf_spec->dblk_para.buf_start); + pr_info("dblk_data.buf_start :%x\n", + buf_spec->dblk_data.buf_start); + pr_info("dblk_data2.buf_start :%x\n", + buf_spec->dblk_data2.buf_start); + #ifdef AVS2_10B_MMU + pr_info("mmu_vbh.buf_start :%x\n", + buf_spec->mmu_vbh.buf_start); + #endif + pr_info("mpred_above.buf_start :%x\n", + buf_spec->mpred_above.buf_start); +#ifdef MV_USE_FIXED_BUF + pr_info("mpred_mv.buf_start :%x\n", + buf_spec->mpred_mv.buf_start); +#endif + if ((debug & AVS2_DBG_SEND_PARAM_WITH_REG) == 0) { + pr_info("rpm.buf_start :%x\n", + buf_spec->rpm.buf_start); + } + } + } + +} + +static void uninit_mmu_buffers(struct AVS2Decoder_s *dec) +{ +#ifndef MV_USE_FIXED_BUF + dealloc_mv_bufs(dec); +#endif + decoder_mmu_box_free(dec->mmu_box); + dec->mmu_box = NULL; + + if (dec->bmmu_box) + decoder_bmmu_box_free(dec->bmmu_box); + dec->bmmu_box = NULL; +} + +#ifndef AVS2_10B_MMU +static void init_buf_list(struct AVS2Decoder_s *dec) +{ + int i; + int buf_size; + int mc_buffer_end = dec->mc_buf->buf_start + dec->mc_buf->buf_size; + dec->used_buf_num = max_buf_num; + + if (dec->used_buf_num > MAX_BUF_NUM) + dec->used_buf_num = MAX_BUF_NUM; + if (buf_alloc_size > 0) { + buf_size = buf_alloc_size; + avs2_print(dec, AVS2_DBG_BUFMGR, + "[Buffer Management] init_buf_list:\n"); + } else { + int pic_width = dec->init_pic_w; + int pic_height = dec->init_pic_h; + + /*SUPPORT_10BIT*/ + int losless_comp_header_size = compute_losless_comp_header_size + (dec, pic_width, pic_height); + int losless_comp_body_size = compute_losless_comp_body_size + (dec, pic_width, pic_height, buf_alloc_depth == 10); + int mc_buffer_size = losless_comp_header_size + + losless_comp_body_size; + int mc_buffer_size_h = (mc_buffer_size + 0xffff)>>16; + + int dw_mode = get_double_write_mode_init(dec); + + if (dw_mode) { + int pic_width_dw = pic_width / + get_double_write_ratio(dec, dw_mode); + int pic_height_dw = pic_height / + get_double_write_ratio(dec, dw_mode); + int lcu_size = 64; /*fixed 64*/ + int pic_width_64 = (pic_width_dw + 63) & (~0x3f); + int pic_height_32 = (pic_height_dw + 31) & (~0x1f); + int pic_width_lcu = + (pic_width_64 % lcu_size) ? pic_width_64 / lcu_size + + 1 : pic_width_64 / lcu_size; + int pic_height_lcu = + (pic_height_32 % lcu_size) ? pic_height_32 / lcu_size + + 1 : pic_height_32 / lcu_size; + int lcu_total = pic_width_lcu * pic_height_lcu; + int mc_buffer_size_u_v = lcu_total * lcu_size * lcu_size / 2; + int mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16; + /*64k alignment*/ + buf_size = ((mc_buffer_size_u_v_h << 16) * 3); + } else + buf_size = 0; + + if (mc_buffer_size & 0xffff) { /*64k alignment*/ + mc_buffer_size_h += 1; + } + if ((dw_mode & 0x10) == 0) + buf_size += (mc_buffer_size_h << 16); + avs2_print(dec, AVS2_DBG_BUFMGR, + "init_buf_list num %d (width %d height %d):\n", + dec->used_buf_num, pic_width, pic_height); + } + + for (i = 0; i < dec->used_buf_num; i++) { + if (((i + 1) * buf_size) > dec->mc_buf->buf_size) + dec->use_cma_flag = 1; +#ifndef AVS2_10B_MMU + dec->m_BUF[i].alloc_flag = 0; + dec->m_BUF[i].index = i; + + dec->use_cma_flag = 1; + if (dec->use_cma_flag) { + dec->m_BUF[i].cma_page_count = + PAGE_ALIGN(buf_size) / PAGE_SIZE; + if (decoder_bmmu_box_alloc_buf_phy(dec->bmmu_box, + VF_BUFFER_IDX(i), buf_size, DRIVER_NAME, + &dec->m_BUF[i].alloc_addr) < 0) { + dec->m_BUF[i].cma_page_count = 0; + if (i <= 5) { + dec->fatal_error |= + DECODER_FATAL_ERROR_NO_MEM; + } + break; + } + dec->m_BUF[i].start_adr = dec->m_BUF[i].alloc_addr; + } else { + dec->m_BUF[i].cma_page_count = 0; + dec->m_BUF[i].alloc_addr = 0; + dec->m_BUF[i].start_adr = + dec->mc_buf->buf_start + i * buf_size; + } + dec->m_BUF[i].size = buf_size; + dec->m_BUF[i].free_start_adr = dec->m_BUF[i].start_adr; + + if (((dec->m_BUF[i].start_adr + buf_size) > mc_buffer_end) + && (dec->m_BUF[i].alloc_addr == 0)) { + if (debug) { + avs2_print(dec, 0, + "Max mc buffer or mpred_mv buffer is used\n"); + } + break; + } + + avs2_print(dec, AVS2_DBG_BUFMGR, + "Buffer %d: start_adr %p size %x\n", i, + (void *)dec->m_BUF[i].start_adr, + dec->m_BUF[i].size); +#endif + } + dec->buf_num = i; +} +#endif + +static int config_pic(struct AVS2Decoder_s *dec, + struct avs2_frame_s *pic, int32_t lcu_size_log2) +{ + int ret = -1; + int i; + int pic_width = dec->init_pic_w; + int pic_height = dec->init_pic_h; + /*struct avs2_decoder *avs2_dec = &dec->avs2_dec; + int32_t lcu_size_log2 = avs2_dec->lcu_size_log2;*/ + int32_t lcu_size = 1 << lcu_size_log2; + int pic_width_64 = (pic_width + 63) & (~0x3f); + int pic_height_32 = (pic_height + 31) & (~0x1f); + int pic_width_lcu = (pic_width_64 % lcu_size) ? + pic_width_64 / lcu_size + 1 + : pic_width_64 / lcu_size; + int pic_height_lcu = (pic_height_32 % lcu_size) ? + pic_height_32 / lcu_size + 1 + : pic_height_32 / lcu_size; + int lcu_total = pic_width_lcu * pic_height_lcu; +#if 0 + int32_t MV_MEM_UNIT = + (lcu_size_log2 == 6) ? 0x200 : + ((lcu_size_log2 == 5) ? 0x80 : 0x20); +#endif +#ifdef MV_USE_FIXED_BUF + u32 mpred_mv_end = dec->work_space_buf->mpred_mv.buf_start + + dec->work_space_buf->mpred_mv.buf_size; +#endif + u32 y_adr = 0; + int buf_size = 0; + + int losless_comp_header_size = + compute_losless_comp_header_size( + dec, pic_width, pic_height); + int losless_comp_body_size = compute_losless_comp_body_size( + dec, pic_width, + pic_height, buf_alloc_depth == 10); + int mc_buffer_size = losless_comp_header_size + losless_comp_body_size; + int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16; + int mc_buffer_size_u_v = 0; + int mc_buffer_size_u_v_h = 0; + int dw_mode = get_double_write_mode_init(dec); + + if (dw_mode) { + int pic_width_dw = pic_width / + get_double_write_ratio(dec, dw_mode); + int pic_height_dw = pic_height / + get_double_write_ratio(dec, dw_mode); + int pic_width_64_dw = (pic_width_dw + 63) & (~0x3f); + int pic_height_32_dw = (pic_height_dw + 31) & (~0x1f); + int pic_width_lcu_dw = (pic_width_64_dw % lcu_size) ? + pic_width_64_dw / lcu_size + 1 + : pic_width_64_dw / lcu_size; + int pic_height_lcu_dw = (pic_height_32_dw % lcu_size) ? + pic_height_32_dw / lcu_size + 1 + : pic_height_32_dw / lcu_size; + int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw; + + mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2; + mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16; + /*64k alignment*/ + buf_size = ((mc_buffer_size_u_v_h << 16) * 3); + buf_size = ((buf_size + 0xffff) >> 16) << 16; + } + if (mc_buffer_size & 0xffff) /*64k alignment*/ + mc_buffer_size_h += 1; +#ifndef AVS2_10B_MMU + if ((dw_mode & 0x10) == 0) + buf_size += (mc_buffer_size_h << 16); +#endif + +#ifdef AVS2_10B_MMU + pic->header_adr = decoder_bmmu_box_get_phy_addr( + dec->bmmu_box, HEADER_BUFFER_IDX(pic->index)); + + avs2_print(dec, AVS2_DBG_BUFMGR_MORE, + "buf_size %d, MMU header_adr %d: %ld\n", + buf_size, pic->index, pic->header_adr); +#endif + + i = pic->index; +#ifdef MV_USE_FIXED_BUF +#ifdef G12A_BRINGUP_DEBUG + if (1) { +#else + if ((dec->work_space_buf->mpred_mv.buf_start + + (((i + 1) * lcu_total) * MV_MEM_UNIT)) + <= mpred_mv_end + ) { +#endif +#endif +#ifndef AVS2_10B_MMU + if (debug) { + pr_err("start %x .size=%d\n", + dec->mc_buf_spec.buf_start + i * buf_size, + buf_size); + } +#endif +#ifndef AVS2_10B_MMU + for (i = 0; i < dec->buf_num; i++) { + y_adr = ((dec->m_BUF[i].free_start_adr + + 0xffff) >> 16) << 16; + /*64k alignment*/ + if ((y_adr+buf_size) <= (dec->m_BUF[i].start_adr+ + dec->m_BUF[i].size)) { + dec->m_BUF[i].free_start_adr = + y_adr + buf_size; + break; + } + } + if (i < dec->buf_num) +#else + /*if ((dec->mc_buf->buf_start + (i + 1) * buf_size) < + dec->mc_buf->buf_end) + y_adr = dec->mc_buf->buf_start + i * buf_size; + else {*/ + if (buf_size > 0) { + ret = decoder_bmmu_box_alloc_buf_phy(dec->bmmu_box, + VF_BUFFER_IDX(i), + buf_size, DRIVER_NAME, + &pic->cma_alloc_addr); + if (ret < 0) { + avs2_print(dec, 0, + "decoder_bmmu_box_alloc_buf_phy idx %d size %d fail\n", + VF_BUFFER_IDX(i), + buf_size + ); + return ret; + } + + if (pic->cma_alloc_addr) + y_adr = pic->cma_alloc_addr; + else { + avs2_print(dec, 0, + "decoder_bmmu_box_alloc_buf_phy idx %d size %d return null\n", + VF_BUFFER_IDX(i), + buf_size + ); + return -1; + } + } +#endif + { + /*ensure get_pic_by_POC() + not get the buffer not decoded*/ + pic->BUF_index = i; + pic->lcu_total = lcu_total; + + pic->comp_body_size = losless_comp_body_size; + pic->buf_size = buf_size; +#ifndef AVS2_10B_MMU + pic->mc_y_adr = y_adr; +#endif + pic->mc_canvas_y = pic->index; + pic->mc_canvas_u_v = pic->index; +#ifndef AVS2_10B_MMU + if (dw_mode & 0x10) { + pic->mc_u_v_adr = y_adr + + ((mc_buffer_size_u_v_h << 16) << 1); + + pic->mc_canvas_y = + (pic->index << 1); + pic->mc_canvas_u_v = + (pic->index << 1) + 1; + + pic->dw_y_adr = y_adr; + pic->dw_u_v_adr = pic->mc_u_v_adr; + } else +#endif + if (dw_mode) { + pic->dw_y_adr = y_adr +#ifndef AVS2_10B_MMU + + (mc_buffer_size_h << 16) +#endif + ; + pic->dw_u_v_adr = pic->dw_y_adr + + ((mc_buffer_size_u_v_h << 16) << 1); +#ifdef AVS2_10B_MMU + pic->mc_y_adr = pic->dw_y_adr; + pic->mc_u_v_adr = pic->dw_u_v_adr; +#endif + } +#ifdef MV_USE_FIXED_BUF +#ifdef G12A_BRINGUP_DEBUG + pic->mpred_mv_wr_start_addr = + dec->work_space_buf->mpred_mv.buf_start + + (pic->index * 0x120000); +#else + pic->mpred_mv_wr_start_addr = + dec->work_space_buf->mpred_mv.buf_start + + ((pic->index * lcu_total) + * MV_MEM_UNIT); +#endif +#endif + if (debug) { + avs2_print(dec, AVS2_DBG_BUFMGR, + "%s index %d BUF_index %d mc_y_adr %x ", + __func__, pic->index, + pic->BUF_index, + pic->mc_y_adr); + avs2_print_cont(dec, AVS2_DBG_BUFMGR, + "comp_body_size %x comp_buf_size %x ", + pic->comp_body_size, + pic->buf_size); + avs2_print_cont(dec, AVS2_DBG_BUFMGR, + "mpred_mv_wr_start_adr %d\n", + pic->mpred_mv_wr_start_addr); + avs2_print_cont(dec, AVS2_DBG_BUFMGR, + "dw_y_adr %d, pic->dw_u_v_adr =%d\n", + pic->dw_y_adr, + pic->dw_u_v_adr); + } + ret = 0; + } +#ifdef MV_USE_FIXED_BUF + } else { + avs2_print(dec, 0, + "mv buffer alloc fail %x > %x\n", + dec->work_space_buf->mpred_mv.buf_start + + (((i + 1) * lcu_total) * MV_MEM_UNIT), + mpred_mv_end); + } +#endif + return ret; +} + +static void init_pic_list(struct AVS2Decoder_s *dec, + int32_t lcu_size_log2) +{ + int i; + struct avs2_decoder *avs2_dec = &dec->avs2_dec; + struct avs2_frame_s *pic; +#ifdef AVS2_10B_MMU + /*alloc AVS2 compress header first*/ + for (i = 0; i < dec->used_buf_num; i++) { + unsigned long buf_addr; + if (decoder_bmmu_box_alloc_buf_phy + (dec->bmmu_box, + HEADER_BUFFER_IDX(i), MMU_COMPRESS_HEADER_SIZE, + DRIVER_HEADER_NAME, + &buf_addr) < 0){ + avs2_print(dec, 0, + "%s malloc compress header failed %d\n", + DRIVER_HEADER_NAME, i); + dec->fatal_error |= DECODER_FATAL_ERROR_NO_MEM; + return; + } + } +#endif + for (i = 0; i < dec->used_buf_num; i++) { + if (i == (dec->used_buf_num - 1)) + pic = avs2_dec->m_bg; + else + pic = avs2_dec->fref[i]; + pic->index = i; + pic->BUF_index = -1; + pic->mv_buf_index = -1; + if (config_pic(dec, pic, lcu_size_log2) < 0) { + if (debug) + avs2_print(dec, 0, + "Config_pic %d fail\n", + pic->index); + pic->index = -1; + break; + } + pic->pic_w = avs2_dec->img.width; + pic->pic_h = avs2_dec->img.height; + } + for (; i < dec->used_buf_num; i++) { + if (i == (dec->used_buf_num - 1)) + pic = avs2_dec->m_bg; + else + pic = avs2_dec->fref[i]; + pic->index = -1; + pic->BUF_index = -1; + pic->mv_buf_index = -1; + } + avs2_print(dec, AVS2_DBG_BUFMGR, + "%s ok, used_buf_num = %d\n", + __func__, dec->used_buf_num); + dec->pic_list_init_flag = 1; +} + + +static void init_pic_list_hw(struct AVS2Decoder_s *dec) +{ + int i; + struct avs2_decoder *avs2_dec = &dec->avs2_dec; + struct avs2_frame_s *pic; + /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/ + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, + (0x1 << 1) | (0x1 << 2)); + +#ifdef DUAL_CORE_64 + WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, + (0x1 << 1) | (0x1 << 2)); +#endif + for (i = 0; i < dec->used_buf_num; i++) { + if (i == (dec->used_buf_num - 1)) + pic = avs2_dec->m_bg; + else + pic = avs2_dec->fref[i]; + if (pic->index < 0) + break; + +#ifdef AVS2_10B_MMU + /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, + pic->header_adr + | (pic->mc_canvas_y << 8)|0x1);*/ + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, pic->header_adr >> 5); +#else + /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, + pic->mc_y_adr + | (pic->mc_canvas_y << 8) | 0x1);*/ + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, pic->mc_y_adr >> 5); +#endif +#ifndef LOSLESS_COMPRESS_MODE + /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, + pic->mc_u_v_adr + | (pic->mc_canvas_u_v << 8)| 0x1);*/ + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, pic->mc_u_v_adr >> 5); +#endif +#ifdef DUAL_CORE_64 +#ifdef AVS2_10B_MMU + WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_DATA, + pic->header_adr >> 5); +#else + WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_DATA, + pic->mc_y_adr >> 5); +#endif +#ifndef LOSLESS_COMPRESS_MODE + WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_DATA, + pic->mc_u_v_adr >> 5); +#endif +/*DUAL_CORE_64*/ +#endif + } + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1); +#ifdef DUAL_CORE_64 + WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, + 0x1); +#endif + /*Zero out canvas registers in IPP -- avoid simulation X*/ + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (0 << 8) | (0 << 1) | 1); + for (i = 0; i < 32; i++) { + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0); +#ifdef DUAL_CORE_64 + WRITE_VREG(HEVC2_HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0); +#endif + } +} + + +static void dump_pic_list(struct AVS2Decoder_s *dec) +{ +#if 0 + struct avs2_decoder *avs2_dec = &dec->avs2_dec; + int i; + for (i = 0; i < FRAME_BUFFERS; i++) { + struct avs2_frame_s *pic = + avs2_dec->fref[i]; + if (pic == NULL) + continue; + avs2_print(dec, + 0, + "Buf(%d) index %d mv_buf_index %d vf_ref %d dec_idx %d slice_type %d w/h %d/%d adr%ld\n", + i, + pic->index, +#ifndef MV_USE_FIXED_BUF + pic->mv_buf_index, +#else + -1, +#endif + pic->vf_ref, + pic->decode_idx, + pic->slice_type, + pic->pic_w, + pic->pic_h, + pic->cma_alloc_addr + ); + } +#endif + return; +} + +static int config_mc_buffer(struct AVS2Decoder_s *dec) +{ + int32_t i; + struct avs2_decoder *avs2_dec = &dec->avs2_dec; + struct avs2_frame_s *pic; + /*if (avs2_dec->img.type == I_IMG) + return 0; + */ + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "Entered config_mc_buffer....\n"); + if (avs2_dec->f_bg != NULL) { + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "config_mc_buffer for background (canvas_y %d, canvas_u_v %d)\n", + avs2_dec->f_bg->mc_canvas_y, avs2_dec->f_bg->mc_canvas_u_v); + /*WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (7 << 8) | (0<<1) | 1); L0:BG */ + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (15 << 8) | (0<<1) | 1); /* L0:BG*/ + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, + (avs2_dec->f_bg->mc_canvas_u_v << 16) | + (avs2_dec->f_bg->mc_canvas_u_v << 8) | + avs2_dec->f_bg->mc_canvas_y); + /*WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (23 << 8) | (0<<1) | 1); L1:BG*/ + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (31 << 8) | (0<<1) | 1); /* L1:BG*/ + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, + (avs2_dec->f_bg->mc_canvas_u_v << 16) | + (avs2_dec->f_bg->mc_canvas_u_v << 8) | + avs2_dec->f_bg->mc_canvas_y); + } + + if (avs2_dec->img.type == I_IMG) + return 0; + + if (avs2_dec->img.type == P_IMG) { + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "config_mc_buffer for P_IMG, img type %d\n", + avs2_dec->img.type); + /*refer to prepare_RefInfo()*/ + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (0 << 8) | (0<<1) | 1); + for (i = 0; i < avs2_dec->img.num_of_references; i++) { + pic = avs2_dec->fref[i]; + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, + (pic->mc_canvas_u_v << 16) | + (pic->mc_canvas_u_v << 8) | + pic->mc_canvas_y); + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "refid %x mc_canvas_u_v %x mc_canvas_y %x\n", + i, pic->mc_canvas_u_v, pic->mc_canvas_y); + } + } else if (avs2_dec->img.type == F_IMG) { + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "config_mc_buffer for F_IMG, img type %d\n", + avs2_dec->img.type); + /*refer to prepare_RefInfo()*/ + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (0 << 8) | (0<<1) | 1); + for (i = 0; i < avs2_dec->img.num_of_references; i++) { + pic = avs2_dec->fref[i]; + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, + (pic->mc_canvas_u_v << 16) | + (pic->mc_canvas_u_v << 8) | + pic->mc_canvas_y); + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "refid %x mc_canvas_u_v %x mc_canvas_y %x\n", + i, pic->mc_canvas_u_v, pic->mc_canvas_y); + } + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (16 << 8) | (0<<1) | 1); + for (i = 0; i < avs2_dec->img.num_of_references; i++) { + pic = avs2_dec->fref[i]; + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, + (pic->mc_canvas_u_v << 16) | + (pic->mc_canvas_u_v << 8) | + pic->mc_canvas_y); + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "refid %x mc_canvas_u_v %x mc_canvas_y %x\n", + i, pic->mc_canvas_u_v, pic->mc_canvas_y); + } + } else { + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "config_mc_buffer for B_IMG\n"); + /*refer to prepare_RefInfo()*/ + pic = avs2_dec->fref[1]; + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (0 << 8) | (0<<1) | 1); + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, + (pic->mc_canvas_u_v << 16) | + (pic->mc_canvas_u_v << 8) | + pic->mc_canvas_y); + + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "refid %x mc_canvas_u_v %x mc_canvas_y %x\n", + 1, pic->mc_canvas_u_v, pic->mc_canvas_y); + + pic = avs2_dec->fref[0]; + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (16 << 8) | (0<<1) | 1); + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, + (pic->mc_canvas_u_v<<16) | + (pic->mc_canvas_u_v<<8) | + pic->mc_canvas_y); + + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "refid %x mc_canvas_u_v %x mc_canvas_y %x\n", + 0, pic->mc_canvas_u_v, pic->mc_canvas_y); + } + return 0; +} + + +static void config_mcrcc_axi_hw(struct AVS2Decoder_s *dec) +{ + uint32_t rdata32; + uint32_t rdata32_2; + struct avs2_decoder *avs2_dec = &dec->avs2_dec; + + WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc*/ + + if (avs2_dec->img.type == I_IMG) { /* I-PIC*/ + /* remove reset -- disables clock */ + WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0); + return; + } + + #if 0 + mcrcc_get_hitrate(); + decomp_get_hitrate(); + decomp_get_comprate(); + #endif + + if ((avs2_dec->img.type == B_IMG) || + (avs2_dec->img.type == F_IMG)) { /*B-PIC or F_PIC*/ + /*Programme canvas0 */ + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (0 << 8) | (0 << 1) | 0); + rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32 = rdata32 & 0xffff; + rdata32 = rdata32 | (rdata32 << 16); + WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32); + + /*Programme canvas1 */ + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (16 << 8) | (1 << 1) | 0); + rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32_2 = rdata32_2 & 0xffff; + rdata32_2 = rdata32_2 | (rdata32_2 << 16); + if (rdata32 == rdata32_2) { + rdata32_2 = + READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32_2 = rdata32_2 & 0xffff; + rdata32_2 = rdata32_2 | (rdata32_2 << 16); + } + WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2); + } else { /* P-PIC */ + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (0 << 8) | (1 << 1) | 0); + rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32 = rdata32 & 0xffff; + rdata32 = rdata32 | (rdata32 << 16); + WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32); + + /*Programme canvas1*/ + rdata32 = + READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32 = rdata32 & 0xffff; + rdata32 = rdata32 | (rdata32 << 16); + WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32); + } + /*enable mcrcc progressive-mode */ + WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); + return; +} + +static void config_mpred_hw(struct AVS2Decoder_s *dec) +{ + uint32_t data32; + struct avs2_decoder *avs2_dec = &dec->avs2_dec; + struct avs2_frame_s *cur_pic = avs2_dec->hc.cur_pic; + struct avs2_frame_s *col_pic = avs2_dec->fref[0]; + int32_t mpred_mv_rd_start_addr; + int32_t mpred_curr_lcu_x; + int32_t mpred_curr_lcu_y; + int32_t mpred_mv_rd_end_addr; + int32_t above_en; + int32_t mv_wr_en; + int32_t mv_rd_en; + int32_t col_isIntra; + int mv_mem_unit; + if (avs2_dec->img.type != I_IMG) { + above_en = 1; + mv_wr_en = 1; + mv_rd_en = 1; + col_isIntra = 0; + } else { + above_en = 1; + mv_wr_en = 1; + mv_rd_en = 0; + col_isIntra = 0; + } + + mpred_mv_rd_start_addr = + col_pic->mpred_mv_wr_start_addr; + data32 = READ_VREG(HEVC_MPRED_CURR_LCU); + mpred_curr_lcu_x = data32 & 0xffff; + mpred_curr_lcu_y = (data32 >> 16) & 0xffff; + + mv_mem_unit = avs2_dec->lcu_size_log2 == 6 ? + 0x200 : (avs2_dec->lcu_size_log2 == 5 ? + 0x80 : 0x20); + + mpred_mv_rd_end_addr = + mpred_mv_rd_start_addr + + ((avs2_dec->lcu_x_num * + avs2_dec->lcu_y_num) * mv_mem_unit); + + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "cur pic index %d col pic index %d\n", + cur_pic->index, col_pic->index); + + + WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR, + cur_pic->mpred_mv_wr_start_addr); + WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR, + col_pic->mpred_mv_wr_start_addr); + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "[MPRED CO_MV] write 0x%x read 0x%x\n", + cur_pic->mpred_mv_wr_start_addr, + col_pic->mpred_mv_wr_start_addr); + + data32 = + ((avs2_dec->bk_img_is_top_field) << 13) | + ((avs2_dec->hd.background_picture_enable & 1) << 12) | + ((avs2_dec->hd.curr_RPS.num_of_ref & 7) << 8) | + ((avs2_dec->hd.b_pmvr_enabled & 1) << 6) | + ((avs2_dec->img.is_top_field & 1) << 5) | + ((avs2_dec->img.is_field_sequence & 1) << 4) | + ((avs2_dec->img.typeb & 7) << 1) | + (avs2_dec->hd.background_reference_enable & 0x1); + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "HEVC_MPRED_CTRL9 <= 0x%x(num of ref %d)\n", + data32, avs2_dec->hd.curr_RPS.num_of_ref); + WRITE_VREG(HEVC_MPRED_CTRL9, data32); + + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "%s: dis %d %d %d %d %d %d %d fref0_ref_poc %d %d %d %d %d %d %d\n", + __func__, + avs2_dec->fref[0]->imgtr_fwRefDistance, + avs2_dec->fref[1]->imgtr_fwRefDistance, + avs2_dec->fref[2]->imgtr_fwRefDistance, + avs2_dec->fref[3]->imgtr_fwRefDistance, + avs2_dec->fref[4]->imgtr_fwRefDistance, + avs2_dec->fref[5]->imgtr_fwRefDistance, + avs2_dec->fref[6]->imgtr_fwRefDistance, + avs2_dec->fref[0]->ref_poc[0], + avs2_dec->fref[0]->ref_poc[1], + avs2_dec->fref[0]->ref_poc[2], + avs2_dec->fref[0]->ref_poc[3], + avs2_dec->fref[0]->ref_poc[4], + avs2_dec->fref[0]->ref_poc[5], + avs2_dec->fref[0]->ref_poc[6] + ); + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "pic_distance %d, imgtr_next_P %d\n", + avs2_dec->img.pic_distance, avs2_dec->img.imgtr_next_P); + + + WRITE_VREG(HEVC_MPRED_CUR_POC, avs2_dec->img.pic_distance); + WRITE_VREG(HEVC_MPRED_COL_POC, avs2_dec->img.imgtr_next_P); + + /*below MPRED Ref_POC_xx_Lx registers + must follow Ref_POC_xx_L0 -> + Ref_POC_xx_L1 in pair write order!!!*/ + WRITE_VREG(HEVC_MPRED_L0_REF00_POC, + avs2_dec->fref[0]->imgtr_fwRefDistance); + WRITE_VREG(HEVC_MPRED_L1_REF00_POC, + avs2_dec->fref[0]->ref_poc[0]); + + WRITE_VREG(HEVC_MPRED_L0_REF01_POC, + avs2_dec->fref[1]->imgtr_fwRefDistance); + WRITE_VREG(HEVC_MPRED_L1_REF01_POC, + avs2_dec->fref[0]->ref_poc[1]); + + WRITE_VREG(HEVC_MPRED_L0_REF02_POC, + avs2_dec->fref[2]->imgtr_fwRefDistance); + WRITE_VREG(HEVC_MPRED_L1_REF02_POC, + avs2_dec->fref[0]->ref_poc[2]); + + WRITE_VREG(HEVC_MPRED_L0_REF03_POC, + avs2_dec->fref[3]->imgtr_fwRefDistance); + WRITE_VREG(HEVC_MPRED_L1_REF03_POC, + avs2_dec->fref[0]->ref_poc[3]); + + WRITE_VREG(HEVC_MPRED_L0_REF04_POC, + avs2_dec->fref[4]->imgtr_fwRefDistance); + WRITE_VREG(HEVC_MPRED_L1_REF04_POC, + avs2_dec->fref[0]->ref_poc[4]); + + WRITE_VREG(HEVC_MPRED_L0_REF05_POC, + avs2_dec->fref[5]->imgtr_fwRefDistance); + WRITE_VREG(HEVC_MPRED_L1_REF05_POC, + avs2_dec->fref[0]->ref_poc[5]); + + WRITE_VREG(HEVC_MPRED_L0_REF06_POC, + avs2_dec->fref[6]->imgtr_fwRefDistance); + WRITE_VREG(HEVC_MPRED_L1_REF06_POC, + avs2_dec->fref[0]->ref_poc[6]); + + + WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, + mpred_mv_rd_end_addr); +} + +static void config_dblk_hw(struct AVS2Decoder_s *dec) +{ + /* + * Picture level de-block parameter configuration here + */ + struct avs2_decoder *avs2_dec = &dec->avs2_dec; + union param_u *rpm_param = &avs2_dec->param; + uint32_t data32; + + data32 = READ_VREG(HEVC_DBLK_CFG1); + data32 = (((data32 >> 20) & 0xfff) << 20) | + (((avs2_dec->input.sample_bit_depth == 10) + ? 0xa : 0x0) << 16) | /*[16 +: 4]: {luma_bd[1:0], + chroma_bd[1:0]}*/ + (((data32 >> 2) & 0x3fff) << 2) | + (((rpm_param->p.lcu_size == 6) + ? 0 : (rpm_param->p.lcu_size == 5) + ? 1 : 2) << 0);/*[ 0 +: 2]: lcu_size*/ + WRITE_VREG(HEVC_DBLK_CFG1, data32); + + data32 = (avs2_dec->img.height << 16) | + avs2_dec->img.width; + WRITE_VREG(HEVC_DBLK_CFG2, data32); + /* + [27 +: 1]: cross_slice_loopfilter_enable_flag + [26 +: 1]: loop_filter_disable + [25 +: 1]: useNSQT + [22 +: 3]: imgtype + [17 +: 5]: alpha_c_offset (-8~8) + [12 +: 5]: beta_offset (-8~8) + [ 6 +: 6]: chroma_quant_param_delta_u (-16~16) + [ 0 +: 6]: chroma_quant_param_delta_v (-16~16) + */ + data32 = ((avs2_dec->input.crossSliceLoopFilter + & 0x1) << 27) | + ((rpm_param->p.loop_filter_disable & 0x1) << 26) | + ((avs2_dec->input.useNSQT & 0x1) << 25) | + ((avs2_dec->img.type & 0x7) << 22) | + ((rpm_param->p.alpha_c_offset & 0x1f) << 17) | + ((rpm_param->p.beta_offset & 0x1f) << 12) | + ((rpm_param->p.chroma_quant_param_delta_cb & 0x3f) << 6) | + ((rpm_param->p.chroma_quant_param_delta_cr & 0x3f) << 0); + + WRITE_VREG(HEVC_DBLK_CFG9, data32); + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "[c] cfgDBLK: crossslice(%d),lfdisable(%d),bitDepth(%d),lcuSize(%d),NSQT(%d)\n", + avs2_dec->input.crossSliceLoopFilter, + rpm_param->p.loop_filter_disable, + avs2_dec->input.sample_bit_depth, + avs2_dec->lcu_size, + avs2_dec->input.useNSQT); + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "[c] cfgDBLK: alphaCOffset(%d),betaOffset(%d),quantDeltaCb(%d),quantDeltaCr(%d)\n", + rpm_param->p.alpha_c_offset, + rpm_param->p.beta_offset, + rpm_param->p.chroma_quant_param_delta_cb, + rpm_param->p.chroma_quant_param_delta_cr); + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "[c] cfgDBLK: .done.\n"); +} + +static void config_sao_hw(struct AVS2Decoder_s *dec) +{ + uint32_t data32; + struct avs2_decoder *avs2_dec = &dec->avs2_dec; + struct avs2_frame_s *cur_pic = avs2_dec->hc.cur_pic; + + int lcu_size = 64; + int mc_buffer_size_u_v = + cur_pic->lcu_total * lcu_size*lcu_size/2; + int mc_buffer_size_u_v_h = + (mc_buffer_size_u_v + 0xffff) >> 16;/*64k alignment*/ + + data32 = READ_VREG(HEVC_SAO_CTRL0); + data32 &= (~0xf); + data32 |= avs2_dec->lcu_size_log2; + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "%s, lcu_size_log2 = %d, config HEVC_SAO_CTRL0 0x%x\n", + __func__, + avs2_dec->lcu_size_log2, + data32); + + WRITE_VREG(HEVC_SAO_CTRL0, data32); + +#ifndef AVS2_10B_MMU + if ((get_double_write_mode(dec) & 0x10) == 0) + WRITE_VREG(HEVC_CM_BODY_START_ADDR, cur_pic->mc_y_adr); +#endif + if (get_double_write_mode(dec)) { + WRITE_VREG(HEVC_SAO_Y_START_ADDR, cur_pic->dw_y_adr); + WRITE_VREG(HEVC_SAO_C_START_ADDR, cur_pic->dw_u_v_adr); + WRITE_VREG(HEVC_SAO_Y_WPTR, cur_pic->dw_y_adr); + WRITE_VREG(HEVC_SAO_C_WPTR, cur_pic->dw_u_v_adr); + } else { + WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff); + WRITE_VREG(HEVC_SAO_C_START_ADDR, 0xffffffff); + } +#ifdef AVS2_10B_MMU + WRITE_VREG(HEVC_CM_HEADER_START_ADDR, cur_pic->header_adr); +#endif + data32 = (mc_buffer_size_u_v_h << 16) << 1; + /*pr_info("data32=%x,mc_buffer_size_u_v_h=%x,lcu_total=%x\n", + data32, mc_buffer_size_u_v_h, cur_pic->lcu_total);*/ + WRITE_VREG(HEVC_SAO_Y_LENGTH, data32); + + data32 = (mc_buffer_size_u_v_h << 16); + WRITE_VREG(HEVC_SAO_C_LENGTH, data32); + +#ifdef AVS2_10B_NV21 +#ifdef DOS_PROJECT + data32 = READ_VREG(HEVC_SAO_CTRL1); + data32 &= (~0x3000); + /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/ + data32 |= (MEM_MAP_MODE << 12); + data32 &= (~0x3); + data32 |= 0x1; /* [1]:dw_disable [0]:cm_disable*/ + WRITE_VREG(HEVC_SAO_CTRL1, data32); + /*[23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl + [17:16] dw_h0_ctrl*/ + data32 = READ_VREG(HEVC_SAO_CTRL5); + /*set them all 0 for H265_NV21 (no down-scale)*/ + data32 &= ~(0xff << 16); + WRITE_VREG(HEVC_SAO_CTRL5, data32); + ata32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG); + data32 &= (~0x30); + /*[5:4] address_format 00:linear 01:32x32 10:64x32*/ + data32 |= (MEM_MAP_MODE << 4); + WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32); +#else + /*m8baby test1902*/ + data32 = READ_VREG(HEVC_SAO_CTRL1); + data32 &= (~0x3000); + /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/ + data32 |= (MEM_MAP_MODE << 12); + data32 &= (~0xff0); + /*data32 |= 0x670;*/ /*Big-Endian per 64-bit*/ + data32 |= 0x880; /*.Big-Endian per 64-bit */ + data32 &= (~0x3); + data32 |= 0x1; /*[1]:dw_disable [0]:cm_disable*/ + WRITE_VREG(HEVC_SAO_CTRL1, data32); + /* [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl + [19:18] dw_h1_ctrl [17:16] dw_h0_ctrl*/ + data32 = READ_VREG(HEVC_SAO_CTRL5); + /* set them all 0 for H265_NV21 (no down-scale)*/ + data32 &= ~(0xff << 16); + WRITE_VREG(HEVC_SAO_CTRL5, data32); + + data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG); + data32 &= (~0x30); + /*[5:4] address_format 00:linear 01:32x32 10:64x32*/ + data32 |= (MEM_MAP_MODE << 4); + data32 &= (~0xF); + data32 |= 0x8; /*Big-Endian per 64-bit*/ + WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32); +#endif +#else + data32 = READ_VREG(HEVC_SAO_CTRL1); + data32 &= (~0x3000); + data32 |= (MEM_MAP_MODE << + 12); /* [13:12] axi_aformat, 0-Linear, + 1-32x32, 2-64x32 */ + data32 &= (~0xff0); + /* data32 |= 0x670; // Big-Endian per 64-bit */ + data32 |= endian; /* Big-Endian per 64-bit */ + data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/ +#if 0 + if (get_cpu_type() < MESON_CPU_MAJOR_ID_G12A) { + if (get_double_write_mode(dec) == 0) + data32 |= 0x2; /*disable double write*/ +#ifndef AVS2_10B_MMU + else + if (get_double_write_mode(dec) & 0x10) + data32 |= 0x1; /*disable cm*/ +#endif + } +#endif + WRITE_VREG(HEVC_SAO_CTRL1, data32); + + if (get_double_write_mode(dec) & 0x10) { + /* [23:22] dw_v1_ctrl + [21:20] dw_v0_ctrl + [19:18] dw_h1_ctrl + [17:16] dw_h0_ctrl + */ + data32 = READ_VREG(HEVC_SAO_CTRL5); + /*set them all 0 for H265_NV21 (no down-scale)*/ + data32 &= ~(0xff << 16); + WRITE_VREG(HEVC_SAO_CTRL5, data32); + } else { + data32 = READ_VREG(HEVC_SAO_CTRL5); + data32 &= (~(0xff << 16)); + if (get_double_write_mode(dec) == 2 || + get_double_write_mode(dec) == 3) + data32 |= (0xff<<16); + else if (get_double_write_mode(dec) == 4) + data32 |= (0x33<<16); + WRITE_VREG(HEVC_SAO_CTRL5, data32); + } + + data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG); + data32 &= (~0x30); + /* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */ + data32 |= (mem_map_mode << + 4); + data32 &= (~0xF); + data32 |= 0xf; /* valid only when double write only */ + /*data32 |= 0x8;*/ /* Big-Endian per 64-bit */ + WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32); +#endif +} + +static void reconstructCoefficients(struct AVS2Decoder_s *dec, + struct ALFParam_s *alfParam) +{ + int32_t g, sum, i, coeffPred; + for (g = 0; g < alfParam->filters_per_group; g++) { + sum = 0; + for (i = 0; i < alfParam->num_coeff - 1; i++) { + sum += (2 * alfParam->coeffmulti[g][i]); + dec->m_filterCoeffSym[g][i] = + alfParam->coeffmulti[g][i]; + /*pr_info("[t] dec->m_filterCoeffSym[%d][%d]=0x%x\n", + g, i, dec->m_filterCoeffSym[g][i]);*/ + } + coeffPred = (1 << ALF_NUM_BIT_SHIFT) - sum; + dec->m_filterCoeffSym[g][alfParam->num_coeff - 1] + = coeffPred + + alfParam->coeffmulti[g][alfParam->num_coeff - 1]; + /*pr_info("[t] dec->m_filterCoeffSym[%d][%d]=0x%x\n", + g, (alfParam->num_coeff - 1), + dec->m_filterCoeffSym[g][alfParam->num_coeff - 1]);*/ + } +} + +static void reconstructCoefInfo(struct AVS2Decoder_s *dec, + int32_t compIdx, struct ALFParam_s *alfParam) +{ + int32_t i; + if (compIdx == ALF_Y) { + if (alfParam->filters_per_group > 1) { + for (i = 1; i < NO_VAR_BINS; ++i) { + if (alfParam->filterPattern[i]) + dec->m_varIndTab[i] = + dec->m_varIndTab[i - 1] + 1; + else + dec->m_varIndTab[i] = + dec->m_varIndTab[i - 1]; + } + } + } + reconstructCoefficients(dec, alfParam); +} + +static void config_alf_hw(struct AVS2Decoder_s *dec) +{ + /* + * Picture level ALF parameter configuration here + */ + uint32_t data32; + int32_t i, j; + int32_t m_filters_per_group; + struct avs2_decoder *avs2_dec = &dec->avs2_dec; + struct ALFParam_s *m_alfPictureParam_y = + &avs2_dec->m_alfPictureParam[0]; + struct ALFParam_s *m_alfPictureParam_cb = + &avs2_dec->m_alfPictureParam[1]; + struct ALFParam_s *m_alfPictureParam_cr = + &avs2_dec->m_alfPictureParam[2]; + + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "[t]alfy,cidx(%d),flag(%d),filters_per_group(%d),filterPattern[0]=0x%x,[15]=0x%x\n", + m_alfPictureParam_y->componentID, + m_alfPictureParam_y->alf_flag, + m_alfPictureParam_y->filters_per_group, + m_alfPictureParam_y->filterPattern[0], + m_alfPictureParam_y->filterPattern[15]); + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "[t]alfy,num_coeff(%d),coeffmulti[0][0]=0x%x,[0][1]=0x%x,[1][0]=0x%x,[1][1]=0x%x\n", + m_alfPictureParam_y->num_coeff, + m_alfPictureParam_y->coeffmulti[0][0], + m_alfPictureParam_y->coeffmulti[0][1], + m_alfPictureParam_y->coeffmulti[1][0], + m_alfPictureParam_y->coeffmulti[1][1]); + + /*Cr*/ + for (i = 0; i < 16; i++) + dec->m_varIndTab[i] = 0; + for (j = 0; j < 16; j++) + for (i = 0; i < 9; i++) + dec->m_filterCoeffSym[j][i] = 0; + reconstructCoefInfo(dec, 2, m_alfPictureParam_cr); + data32 = + ((dec->m_filterCoeffSym[0][4] & 0xf) << 28) | + ((dec->m_filterCoeffSym[0][3] & 0x7f) << 21) | + ((dec->m_filterCoeffSym[0][2] & 0x7f) << 14) | + ((dec->m_filterCoeffSym[0][1] & 0x7f) << 7) | + ((dec->m_filterCoeffSym[0][0] & 0x7f) << 0); + WRITE_VREG(HEVC_DBLK_CFGD, data32); + data32 = + ((dec->m_filterCoeffSym[0][8] & 0x7f) << 24) | + ((dec->m_filterCoeffSym[0][7] & 0x7f) << 17) | + ((dec->m_filterCoeffSym[0][6] & 0x7f) << 10) | + ((dec->m_filterCoeffSym[0][5] & 0x7f) << 3) | + (((dec->m_filterCoeffSym[0][4] >> 4) & 0x7) << 0); + WRITE_VREG(HEVC_DBLK_CFGD, data32); + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "[c] pic_alf_on_cr(%d), alf_cr_coef(%d %d %d %d %d %d %d %d %d)\n", + m_alfPictureParam_cr->alf_flag, + dec->m_filterCoeffSym[0][0], + dec->m_filterCoeffSym[0][1], + dec->m_filterCoeffSym[0][2], + dec->m_filterCoeffSym[0][3], + dec->m_filterCoeffSym[0][4], + dec->m_filterCoeffSym[0][5], + dec->m_filterCoeffSym[0][6], + dec->m_filterCoeffSym[0][7], + dec->m_filterCoeffSym[0][8]); + + /* Cb*/ + for (j = 0; j < 16; j++) + for (i = 0; i < 9; i++) + dec->m_filterCoeffSym[j][i] = 0; + reconstructCoefInfo(dec, 1, m_alfPictureParam_cb); + data32 = + ((dec->m_filterCoeffSym[0][4] & 0xf) << 28) | + ((dec->m_filterCoeffSym[0][3] & 0x7f) << 21) | + ((dec->m_filterCoeffSym[0][2] & 0x7f) << 14) | + ((dec->m_filterCoeffSym[0][1] & 0x7f) << 7) | + ((dec->m_filterCoeffSym[0][0] & 0x7f) << 0); + WRITE_VREG(HEVC_DBLK_CFGD, data32); + data32 = + ((dec->m_filterCoeffSym[0][8] & 0x7f) << 24) | + ((dec->m_filterCoeffSym[0][7] & 0x7f) << 17) | + ((dec->m_filterCoeffSym[0][6] & 0x7f) << 10) | + ((dec->m_filterCoeffSym[0][5] & 0x7f) << 3) | + (((dec->m_filterCoeffSym[0][4] >> 4) & 0x7) << 0); + WRITE_VREG(HEVC_DBLK_CFGD, data32); + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "[c] pic_alf_on_cb(%d), alf_cb_coef(%d %d %d %d %d %d %d %d %d)\n", + m_alfPictureParam_cb->alf_flag, + dec->m_filterCoeffSym[0][0], + dec->m_filterCoeffSym[0][1], + dec->m_filterCoeffSym[0][2], + dec->m_filterCoeffSym[0][3], + dec->m_filterCoeffSym[0][4], + dec->m_filterCoeffSym[0][5], + dec->m_filterCoeffSym[0][6], + dec->m_filterCoeffSym[0][7], + dec->m_filterCoeffSym[0][8]); + + /* Y*/ + for (j = 0; j < 16; j++) + for (i = 0; i < 9; i++) + dec->m_filterCoeffSym[j][i] = 0; + reconstructCoefInfo(dec, 0, m_alfPictureParam_y); + data32 = + ((dec->m_varIndTab[7] & 0xf) << 28) | + ((dec->m_varIndTab[6] & 0xf) << 24) | + ((dec->m_varIndTab[5] & 0xf) << 20) | + ((dec->m_varIndTab[4] & 0xf) << 16) | + ((dec->m_varIndTab[3] & 0xf) << 12) | + ((dec->m_varIndTab[2] & 0xf) << 8) | + ((dec->m_varIndTab[1] & 0xf) << 4) | + ((dec->m_varIndTab[0] & 0xf) << 0); + WRITE_VREG(HEVC_DBLK_CFGD, data32); + data32 = ((dec->m_varIndTab[15] & 0xf) << 28) | + ((dec->m_varIndTab[14] & 0xf) << 24) | + ((dec->m_varIndTab[13] & 0xf) << 20) | + ((dec->m_varIndTab[12] & 0xf) << 16) | + ((dec->m_varIndTab[11] & 0xf) << 12) | + ((dec->m_varIndTab[10] & 0xf) << 8) | + ((dec->m_varIndTab[9] & 0xf) << 4) | + ((dec->m_varIndTab[8] & 0xf) << 0); + WRITE_VREG(HEVC_DBLK_CFGD, data32); + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "[c] pic_alf_on_y(%d), alf_y_tab(%d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d)\n", + m_alfPictureParam_y->alf_flag, + dec->m_varIndTab[0], + dec->m_varIndTab[1], + dec->m_varIndTab[2], + dec->m_varIndTab[3], + dec->m_varIndTab[4], + dec->m_varIndTab[5], + dec->m_varIndTab[6], + dec->m_varIndTab[7], + dec->m_varIndTab[8], + dec->m_varIndTab[9], + dec->m_varIndTab[10], + dec->m_varIndTab[11], + dec->m_varIndTab[12], + dec->m_varIndTab[13], + dec->m_varIndTab[14], + dec->m_varIndTab[15]); + + m_filters_per_group = + (m_alfPictureParam_y->alf_flag == 0) ? + 1 : m_alfPictureParam_y->filters_per_group; + for (i = 0; i < m_filters_per_group; i++) { + data32 = + ((dec->m_filterCoeffSym[i][4] & 0xf) << 28) | + ((dec->m_filterCoeffSym[i][3] & 0x7f) << 21) | + ((dec->m_filterCoeffSym[i][2] & 0x7f) << 14) | + ((dec->m_filterCoeffSym[i][1] & 0x7f) << 7) | + ((dec->m_filterCoeffSym[i][0] & 0x7f) << 0); + WRITE_VREG(HEVC_DBLK_CFGD, data32); + data32 = + /*[31] last indication*/ + ((i == m_filters_per_group-1) << 31) | + ((dec->m_filterCoeffSym[i][8] & 0x7f) << 24) | + ((dec->m_filterCoeffSym[i][7] & 0x7f) << 17) | + ((dec->m_filterCoeffSym[i][6] & 0x7f) << 10) | + ((dec->m_filterCoeffSym[i][5] & 0x7f) << 3) | + (((dec->m_filterCoeffSym[i][4] >> 4) & 0x7) << 0); + WRITE_VREG(HEVC_DBLK_CFGD, data32); + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "[c] alf_y_coef[%d](%d %d %d %d %d %d %d %d %d)\n", + i, dec->m_filterCoeffSym[i][0], + dec->m_filterCoeffSym[i][1], + dec->m_filterCoeffSym[i][2], + dec->m_filterCoeffSym[i][3], + dec->m_filterCoeffSym[i][4], + dec->m_filterCoeffSym[i][5], + dec->m_filterCoeffSym[i][6], + dec->m_filterCoeffSym[i][7], + dec->m_filterCoeffSym[i][8]); + } + avs2_print(dec, AVS2_DBG_BUFMGR_DETAIL, + "[c] cfgALF .done.\n"); +} + +static void config_other_hw(struct AVS2Decoder_s *dec) +{ + uint32_t data32; + struct avs2_decoder *avs2_dec = &dec->avs2_dec; + struct avs2_frame_s *cur_pic = avs2_dec->hc.cur_pic; + int bit_depth = cur_pic->bit_depth; + int losless_comp_header_size = + compute_losless_comp_header_size( + dec, cur_pic->pic_w, + cur_pic->pic_h); + int losless_comp_body_size = + compute_losless_comp_body_size( + dec, cur_pic->pic_w, + cur_pic->pic_h, (bit_depth == AVS2_BITS_10)); + cur_pic->comp_body_size = losless_comp_body_size; + +#ifdef LOSLESS_COMPRESS_MODE + data32 = READ_VREG(HEVC_SAO_CTRL5); + if (bit_depth == AVS2_BITS_10) + data32 &= ~(1 << 9); + else + data32 |= (1 << 9); + + WRITE_VREG(HEVC_SAO_CTRL5, data32); + +#ifdef AVS2_10B_MMU + /*bit[4] : paged_mem_mode*/ + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4)); +#else + /*bit[3] smem mdoe*/ + if (bit_depth == AVS2_BITS_10) + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0 << 3)); + else + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1 << 3)); +#endif + WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5)); + /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/ + WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size); + WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size); + WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size); +#else + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31); +#endif +} + +static void avs2_config_work_space_hw(struct AVS2Decoder_s *dec) +{ + struct BuffInfo_s *buf_spec = dec->work_space_buf; +#ifdef LOSLESS_COMPRESS_MODE + int losless_comp_header_size = + compute_losless_comp_header_size( + dec, dec->init_pic_w, + dec->init_pic_h); + int losless_comp_body_size = + compute_losless_comp_body_size(dec, + dec->init_pic_w, + dec->init_pic_h, buf_alloc_depth == 10); +#endif +#ifdef AVS2_10B_MMU + unsigned int data32; +#endif + if (debug && dec->init_flag == 0) + avs2_print(dec, 0, + "%s %x %x %x %x %x %x %x %x %x %x %x %x %x\n", + __func__, + buf_spec->ipp.buf_start, + buf_spec->start_adr, + buf_spec->short_term_rps.buf_start, + buf_spec->rcs.buf_start, + buf_spec->sps.buf_start, + buf_spec->pps.buf_start, + buf_spec->sao_up.buf_start, + buf_spec->swap_buf.buf_start, + buf_spec->swap_buf2.buf_start, + buf_spec->scalelut.buf_start, + buf_spec->dblk_para.buf_start, + buf_spec->dblk_data.buf_start, + buf_spec->dblk_data2.buf_start); + WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE, buf_spec->ipp.buf_start); + if ((debug & AVS2_DBG_SEND_PARAM_WITH_REG) == 0) + WRITE_VREG(HEVC_RPM_BUFFER, (u32)dec->rpm_phy_addr); + WRITE_VREG(HEVC_SHORT_TERM_RPS, buf_spec->short_term_rps.buf_start); + WRITE_VREG(HEVC_RCS_BUFFER, buf_spec->rcs.buf_start); + WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start); + WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start); + WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start); +#ifdef AVS2_10B_MMU + WRITE_VREG(AVS2_MMU_MAP_BUFFER, dec->frame_mmu_map_phy_addr); +#else + WRITE_VREG(HEVC_STREAM_SWAP_BUFFER, buf_spec->swap_buf.buf_start); +#endif + WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2, buf_spec->swap_buf2.buf_start); + WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start); + + /* cfg_p_addr */ + WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start); + /* cfg_d_addr */ + WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start); + + WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_data2.buf_start); + +#ifdef LOSLESS_COMPRESS_MODE + data32 = READ_VREG(HEVC_SAO_CTRL5); +#if 1 + data32 &= ~(1<<9); +#else + if (params->p.bit_depth != 0x00) + data32 &= ~(1<<9); + else + data32 |= (1<<9); +#endif + WRITE_VREG(HEVC_SAO_CTRL5, data32); +#ifdef AVS2_10B_MMU + /*bit[4] : paged_mem_mode*/ + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4)); + WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0); +#else + /* bit[3] smem mode*/ + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0<<3)); + + WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5)); +#endif + /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL2,(losless_comp_body_size >> 5));*/ + /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/ +/*8-bit mode */ + WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size); + WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size); + WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size); +#else + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31); +#endif + +#ifdef AVS2_10B_MMU + WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start); + WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, buf_spec->mmu_vbh.buf_start + + buf_spec->mmu_vbh.buf_size/2); + /*data32 = READ_VREG(HEVC_SAO_CTRL9);*/ + /*data32 |= 0x1;*/ + /*WRITE_VREG(HEVC_SAO_CTRL9, data32);*/ + + /* use HEVC_CM_HEADER_START_ADDR */ + data32 = READ_VREG(HEVC_SAO_CTRL5); + data32 |= (1<<10); + WRITE_VREG(HEVC_SAO_CTRL5, data32); + +#endif + + WRITE_VREG(LMEM_DUMP_ADR, (u32)dec->lmem_phy_addr); + +} + +static void avs2_init_decoder_hw(struct AVS2Decoder_s *dec) +{ + unsigned int data32; + int i; + const unsigned short parser_cmd[PARSER_CMD_NUMBER] = { + 0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423, + 0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE, + 0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A, + 0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408, + 0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D, + 0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00, + 0x7C00 + }; + const int32_t g_WqMDefault4x4[16] = { + 64, 64, 64, 68, + 64, 64, 68, 72, + 64, 68, 76, 80, + 72, 76, 84, 96 + }; + + const int32_t g_WqMDefault8x8[64] = { + 64, 64, 64, 64, 68, 68, 72, 76, + 64, 64, 64, 68, 72, 76, 84, 92, + 64, 64, 68, 72, 76, 80, 88, 100, + 64, 68, 72, 80, 84, 92, 100, 112, + 68, 72, 80, 84, 92, 104, 112, 128, + 76, 80, 84, 92, 104, 116, 132, 152, + 96, 100, 104, 116, 124, 140, 164, 188, + 104, 108, 116, 128, 152, 172, 192, 216 + }; + + /*if (debug & AVS2_DBG_BUFMGR_MORE) + pr_info("%s\n", __func__);*/ + data32 = READ_VREG(HEVC_PARSER_INT_CONTROL); +#if 1 + /* set bit 31~29 to 3 if HEVC_STREAM_FIFO_CTL[29] is 1 */ + data32 &= ~(7 << 29); + data32 |= (3 << 29); +#endif + data32 = data32 | + (1 << 24) |/*stream_buffer_empty_int_amrisc_enable*/ + (1 << 22) |/*stream_fifo_empty_int_amrisc_enable*/ + (1 << 7) |/*dec_done_int_cpu_enable*/ + (1 << 4) |/*startcode_found_int_cpu_enable*/ + (0 << 3) |/*startcode_found_int_amrisc_enable*/ + (1 << 0) /*parser_int_enable*/ + ; + WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32); + + data32 = READ_VREG(HEVC_SHIFT_STATUS); + data32 = data32 | + (0 << 1) |/*emulation_check_off VP9 + do not have emulation*/ + (1 << 0)/*startcode_check_on*/ + ; + WRITE_VREG(HEVC_SHIFT_STATUS, data32); + WRITE_VREG(HEVC_SHIFT_CONTROL, + (6 << 20) | /* emu_push_bits (6-bits for AVS2)*/ + (0 << 19) | /* emu_3_enable, maybe turned on in microcode*/ + (0 << 18) | /* emu_2_enable, maybe turned on in microcode*/ + (0 << 17) | /* emu_1_enable, maybe turned on in microcode*/ + (0 << 16) | /* emu_0_enable, maybe turned on in microcode*/ + (0 << 14) | /*disable_start_code_protect*/ + (3 << 6) | /* sft_valid_wr_position*/ + (2 << 4) | /* emulate_code_length_sub_1*/ + (2 << 1) | /* start_code_length_sub_1*/ + (1 << 0) /* stream_shift_enable*/ + ); + + WRITE_VREG(HEVC_SHIFT_LENGTH_PROTECT, + (0 << 30) | /*data_protect_fill_00_enable*/ + (1 << 29) /*data_protect_fill_ff_enable*/ + ); + WRITE_VREG(HEVC_CABAC_CONTROL, + (1 << 0)/*cabac_enable*/ + ); + + WRITE_VREG(HEVC_PARSER_CORE_CONTROL, + (1 << 0)/* hevc_parser_core_clk_en*/ + ); + + + WRITE_VREG(HEVC_DEC_STATUS_REG, 0); + + /*Initial IQIT_SCALELUT memory -- just to avoid X in simulation*/ + + WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);/*cfg_p_addr*/ + for (i = 0; i < 1024; i++) + WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0); + + +#ifdef ENABLE_SWAP_TEST + WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100); +#else + WRITE_VREG(HEVC_STREAM_SWAP_TEST, 0); +#endif + if (!dec->m_ins_flag) + WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE); + else if (vdec_frame_based(hw_to_vdec(dec))) + WRITE_VREG(DECODE_MODE, DECODE_MODE_MULTI_FRAMEBASE); + else + WRITE_VREG(DECODE_MODE, DECODE_MODE_MULTI_STREAMBASE); + WRITE_VREG(HEVC_DECODE_SIZE, 0); + WRITE_VREG(HEVC_DECODE_COUNT, 0); + + /*Send parser_cmd*/ + WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0)); + for (i = 0; i < PARSER_CMD_NUMBER; i++) + WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]); + WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0); + WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1); + WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2); + + + WRITE_VREG(HEVC_PARSER_IF_CONTROL, + (1 << 9) | /* parser_alf_if_en*/ + /* (1 << 8) |*/ /*sao_sw_pred_enable*/ + (1 << 5) | /*parser_sao_if_en*/ + (1 << 2) | /*parser_mpred_if_en*/ + (1 << 0) /*parser_scaler_if_en*/ + ); + /*Changed to Start MPRED in microcode*/ + /* + pr_info("[test.c] Start MPRED\n"); + WRITE_VREG(HEVC_MPRED_INT_STATUS, + (1<<31) + ); + */ + + /*AVS2 default seq_wq_matrix config*/ + + avs2_print(dec, AVS2_DBG_BUFMGR_MORE, + "Config AVS2 default seq_wq_matrix ...\n"); + /*4x4*/ + /* default seq_wq_matrix_4x4 begin address*/ + WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 64); + for (i = 0; i < 16; i++) + WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, g_WqMDefault4x4[i]); + + /*8x8*/ + /*default seq_wq_matrix_8x8 begin address*/ + WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0); + for (i = 0; i < 64; i++) + WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, g_WqMDefault8x8[i]); + + + WRITE_VREG(HEVCD_IPP_TOP_CNTL, + (0 << 1) | /*enable ipp*/ + (1 << 0) /*software reset ipp and mpp*/ + ); + WRITE_VREG(HEVCD_IPP_TOP_CNTL, + (1 << 1) | /*enable ipp*/ + (0 << 0) /*software reset ipp and mpp*/ + ); +#if 0 +/*AVS2_10B_NV21*/ + /*Enable NV21 reference read mode for MC*/ + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31); +#endif + /* Init dblk*/ + data32 = READ_VREG(HEVC_DBLK_CFGB); + data32 |= (2 << 0); + /* [3:0] cfg_video_type -> AVS2*/ + + data32 &= (~0x300); /*[8]:first write enable (compress) + [9]:double write enable (uncompress)*/ + if (get_double_write_mode(dec) == 0) + data32 |= (0x1 << 8); /*enable first write*/ + else if (get_double_write_mode(dec) == 0x10) + data32 |= (0x1 << 9); /*double write only*/ + else + data32 |= ((0x1 << 8) |(0x1 << 9)); + WRITE_VREG(HEVC_DBLK_CFGB, data32); + + WRITE_VREG(HEVC_DBLK_CFG0, (1 << 0)); /* [0] rst_sync*/ + avs2_print(dec, AVS2_DBG_BUFMGR_MORE, + "Bitstream level Init for DBLK .Done.\n"); + + return; +} + + +#ifdef CONFIG_HEVC_CLK_FORCED_ON +static void config_avs2_clk_forced_on(void) +{ + unsigned int rdata32; + /*IQIT*/ + rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL); + WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2)); + + /* DBLK*/ + rdata32 = READ_VREG(HEVC_DBLK_CFG0); + WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2)); + + /* SAO*/ + rdata32 = READ_VREG(HEVC_SAO_CTRL1); + WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2)); + + /*MPRED*/ + rdata32 = READ_VREG(HEVC_MPRED_CTRL1); + WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24)); + + /* PARSER*/ + rdata32 = READ_VREG(HEVC_STREAM_CONTROL); + WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15)); + rdata32 = READ_VREG(HEVC_SHIFT_CONTROL); + WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15)); + rdata32 = READ_VREG(HEVC_CABAC_CONTROL); + WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13)); + rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL); + WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15)); + rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL); + WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15)); + rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL); + WRITE_VREG(HEVC_PARSER_IF_CONTROL, + rdata32 | (0x1 << 6) | (0x1 << 3) | (0x1 << 1)); + + /*IPP*/ + rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG); + WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff); + + /* MCRCC*/ + rdata32 = READ_VREG(HEVCD_MCRCC_CTL1); + WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3)); +} +#endif + + + + + +static struct AVS2Decoder_s *gHevc; + +static void avs2_local_uninit(struct AVS2Decoder_s *dec) +{ + dec->rpm_ptr = NULL; + dec->lmem_ptr = NULL; + if (dec->rpm_addr) { + dma_unmap_single(amports_get_dma_device(), + dec->rpm_phy_addr, RPM_BUF_SIZE, + DMA_FROM_DEVICE); + kfree(dec->rpm_addr); + dec->rpm_addr = NULL; + } + if (dec->lmem_addr) { + if (dec->lmem_phy_addr) + dma_free_coherent(amports_get_dma_device(), + LMEM_BUF_SIZE, dec->lmem_addr, + dec->lmem_phy_addr); + dec->lmem_addr = NULL; + } + +#ifdef AVS2_10B_MMU + if (dec->frame_mmu_map_addr) { + if (dec->frame_mmu_map_phy_addr) + dma_free_coherent(amports_get_dma_device(), + FRAME_MMU_MAP_SIZE, dec->frame_mmu_map_addr, + dec->frame_mmu_map_phy_addr); + dec->frame_mmu_map_addr = NULL; + } +#endif + if (dec->gvs) + vfree(dec->gvs); + dec->gvs = NULL; +} + +static int avs2_local_init(struct AVS2Decoder_s *dec) +{ + int ret = -1; + /*int losless_comp_header_size, losless_comp_body_size;*/ + + struct BuffInfo_s *cur_buf_info = NULL; + + cur_buf_info = &dec->work_space_buf_store; +#ifdef SUPPORT_4K2K + if (vdec_is_support_4k()) + memcpy(cur_buf_info, &amvavs2_workbuff_spec[1], /* 4k */ + sizeof(struct BuffInfo_s)); + else + memcpy(cur_buf_info, &amvavs2_workbuff_spec[0],/* 1080p */ + sizeof(struct BuffInfo_s)); +#else + memcpy(cur_buf_info, &amvavs2_workbuff_spec[0], /* 1080p work space */ + sizeof(struct BuffInfo_s)); +#endif + cur_buf_info->start_adr = dec->buf_start; +#ifndef AVS2_10B_MMU + dec->mc_buf_spec.buf_end = dec->buf_start + dec->buf_size; +#endif + + init_buff_spec(dec, cur_buf_info); + + init_avs2_decoder(&dec->avs2_dec); + +#ifdef AVS2_10B_MMU + avs2_bufmgr_init(dec, cur_buf_info, NULL); +#else + dec->mc_buf_spec.buf_start = (cur_buf_info->end_adr + 0xffff) + & (~0xffff); + dec->mc_buf_spec.buf_size = (dec->mc_buf_spec.buf_end + - dec->mc_buf_spec.buf_start); + if (debug) { + pr_err("dec->mc_buf_spec.buf_start %x-%x\n", + dec->mc_buf_spec.buf_start, + dec->mc_buf_spec.buf_start + + dec->mc_buf_spec.buf_size); + } + avs2_bufmgr_init(dec, cur_buf_info, &dec->mc_buf_spec); +#endif + + if (!vdec_is_support_4k() + && (buf_alloc_width > 1920 && buf_alloc_height > 1088)) { + buf_alloc_width = 1920; + buf_alloc_height = 1088; + } + dec->init_pic_w = buf_alloc_width ? buf_alloc_width : + (dec->vavs2_amstream_dec_info.width ? + dec->vavs2_amstream_dec_info.width : + dec->work_space_buf->max_width); + dec->init_pic_h = buf_alloc_height ? buf_alloc_height : + (dec->vavs2_amstream_dec_info.height ? + dec->vavs2_amstream_dec_info.height : + dec->work_space_buf->max_height); +#ifndef MV_USE_FIXED_BUF + if (init_mv_buf_list(dec) < 0) { + pr_err("%s: init_mv_buf_list fail\n", __func__); + return -1; + } +#endif + +#ifndef AVS2_10B_MMU + init_buf_list(dec); +#else + dec->used_buf_num = max_buf_num; + if (dec->used_buf_num > MAX_BUF_NUM) + dec->used_buf_num = MAX_BUF_NUM; + if (dec->used_buf_num > FRAME_BUFFERS) + dec->used_buf_num = FRAME_BUFFERS; +#endif + dec->avs2_dec.ref_maxbuffer = dec->used_buf_num - 1; + /*init_pic_list(dec);*/ + + pts_unstable = ((unsigned long)(dec->vavs2_amstream_dec_info.param) + & 0x40) >> 6; + + if ((debug & AVS2_DBG_SEND_PARAM_WITH_REG) == 0) { + dec->rpm_addr = kmalloc(RPM_BUF_SIZE, GFP_KERNEL); + if (dec->rpm_addr == NULL) { + pr_err("%s: failed to alloc rpm buffer\n", __func__); + return -1; + } + + dec->rpm_phy_addr = dma_map_single(amports_get_dma_device(), + dec->rpm_addr, RPM_BUF_SIZE, DMA_FROM_DEVICE); + if (dma_mapping_error(amports_get_dma_device(), + dec->rpm_phy_addr)) { + pr_err("%s: failed to map rpm buffer\n", __func__); + kfree(dec->rpm_addr); + dec->rpm_addr = NULL; + return -1; + } + + dec->rpm_ptr = dec->rpm_addr; + } + + dec->lmem_addr = dma_alloc_coherent(amports_get_dma_device(), + LMEM_BUF_SIZE, + &dec->lmem_phy_addr, GFP_KERNEL); + if (dec->lmem_addr == NULL) { + pr_err("%s: failed to alloc lmem buffer\n", __func__); + return -1; + } +/* + dec->lmem_phy_addr = dma_map_single(amports_get_dma_device(), + dec->lmem_addr, LMEM_BUF_SIZE, DMA_BIDIRECTIONAL); + if (dma_mapping_error(amports_get_dma_device(), + dec->lmem_phy_addr)) { + pr_err("%s: failed to map lmem buffer\n", __func__); + kfree(dec->lmem_addr); + dec->lmem_addr = NULL; + return -1; + } +*/ + dec->lmem_ptr = dec->lmem_addr; + + +#ifdef AVS2_10B_MMU + dec->frame_mmu_map_addr = dma_alloc_coherent(amports_get_dma_device(), + FRAME_MMU_MAP_SIZE, + &dec->frame_mmu_map_phy_addr, GFP_KERNEL); + if (dec->frame_mmu_map_addr == NULL) { + pr_err("%s: failed to alloc count_buffer\n", __func__); + return -1; + } + memset(dec->frame_mmu_map_addr, 0, COUNT_BUF_SIZE); +/* dec->frame_mmu_map_phy_addr = dma_map_single(amports_get_dma_device(), + dec->frame_mmu_map_addr, FRAME_MMU_MAP_SIZE, DMA_BIDIRECTIONAL); + if (dma_mapping_error(amports_get_dma_device(), + dec->frame_mmu_map_phy_addr)) { + pr_err("%s: failed to map count_buffer\n", __func__); + kfree(dec->frame_mmu_map_addr); + dec->frame_mmu_map_addr = NULL; + return -1; + }*/ +#endif + + ret = 0; + return ret; +} + +/******************************************** + * Mailbox command + ********************************************/ +#define CMD_FINISHED 0 +#define CMD_ALLOC_VIEW 1 +#define CMD_FRAME_DISPLAY 3 +#define CMD_DEBUG 10 + + +#define DECODE_BUFFER_NUM_MAX 32 +#define DISPLAY_BUFFER_NUM 6 + +#define video_domain_addr(adr) (adr&0x7fffffff) +#define DECODER_WORK_SPACE_SIZE 0x800000 + +#define spec2canvas(x) \ + (((x)->uv_canvas_index << 16) | \ + ((x)->uv_canvas_index << 8) | \ + ((x)->y_canvas_index << 0)) + + +static void set_canvas(struct AVS2Decoder_s *dec, + struct avs2_frame_s *pic) +{ + int canvas_w = ALIGN(pic->pic_w, 64)/4; + int canvas_h = ALIGN(pic->pic_h, 32)/4; + int blkmode = mem_map_mode; + /*CANVAS_BLKMODE_64X32*/ + if (pic->double_write_mode) { + canvas_w = pic->pic_w / + get_double_write_ratio(dec, + pic->double_write_mode); + canvas_h = pic->pic_h / + get_double_write_ratio(dec, + pic->double_write_mode); + + if (mem_map_mode == 0) + canvas_w = ALIGN(canvas_w, 32); + else + canvas_w = ALIGN(canvas_w, 64); + canvas_h = ALIGN(canvas_h, 32); + + pic->y_canvas_index = 128 + pic->index * 2; + pic->uv_canvas_index = 128 + pic->index * 2 + 1; + + canvas_config_ex(pic->y_canvas_index, + pic->dw_y_adr, canvas_w, canvas_h, + CANVAS_ADDR_NOWRAP, blkmode, 0x7); + canvas_config_ex(pic->uv_canvas_index, + pic->dw_u_v_adr, canvas_w, canvas_h, + CANVAS_ADDR_NOWRAP, blkmode, 0x7); +#ifdef MULTI_INSTANCE_SUPPORT + pic->canvas_config[0].phy_addr = + pic->dw_y_adr; + pic->canvas_config[0].width = + canvas_w; + pic->canvas_config[0].height = + canvas_h; + pic->canvas_config[0].block_mode = + blkmode; + pic->canvas_config[0].endian = 7; + + pic->canvas_config[1].phy_addr = + pic->dw_u_v_adr; + pic->canvas_config[1].width = + canvas_w; + pic->canvas_config[1].height = + canvas_h; + pic->canvas_config[1].block_mode = + blkmode; + pic->canvas_config[1].endian = 7; +#endif + } else { + #ifndef AVS2_10B_MMU + pic->y_canvas_index = 128 + pic->index; + pic->uv_canvas_index = 128 + pic->index; + + canvas_config_ex(pic->y_canvas_index, + pic->mc_y_adr, canvas_w, canvas_h, + CANVAS_ADDR_NOWRAP, blkmode, 0x7); + canvas_config_ex(pic->uv_canvas_index, + pic->mc_u_v_adr, canvas_w, canvas_h, + CANVAS_ADDR_NOWRAP, blkmode, 0x7); + #endif + } +} + +static void set_frame_info(struct AVS2Decoder_s *dec, struct vframe_s *vf) +{ + unsigned int ar; + + vf->duration = dec->frame_dur; + vf->duration_pulldown = 0; + vf->flag = 0; + vf->prop.master_display_colour = dec->vf_dp; + vf->signal_type = dec->video_signal_type; + + ar = min_t(u32, dec->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX); + vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT); + + return; +} + +static int vavs2_vf_states(struct vframe_states *states, void *op_arg) +{ + struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)op_arg; + + states->vf_pool_size = VF_POOL_SIZE; + states->buf_free_num = kfifo_len(&dec->newframe_q); + states->buf_avail_num = kfifo_len(&dec->display_q); + + if (step == 2) + states->buf_avail_num = 0; + return 0; +} + +static struct vframe_s *vavs2_vf_peek(void *op_arg) +{ + struct vframe_s *vf; + struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)op_arg; + if (step == 2) + return NULL; + + if (force_disp_pic_index & 0x100) { + if (force_disp_pic_index & 0x200) + return NULL; + return &dec->vframe_dummy; + } + + if (kfifo_peek(&dec->display_q, &vf)) + return vf; + + return NULL; +} + +static struct avs2_frame_s *get_pic_by_index( + struct AVS2Decoder_s *dec, int index) +{ + int i; + struct avs2_frame_s *pic = NULL; + if (index == (dec->used_buf_num - 1)) + pic = dec->avs2_dec.m_bg; + else if (index >= 0 && index < dec->used_buf_num) { + for (i = 0; i < dec->used_buf_num; i++) { + if (dec->avs2_dec.fref[i]->index == index) + pic = dec->avs2_dec.fref[i]; + } + } + return pic; +} + +static struct vframe_s *vavs2_vf_get(void *op_arg) +{ + struct vframe_s *vf; + struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)op_arg; + if (step == 2) + return NULL; + else if (step == 1) + step = 2; + + if (force_disp_pic_index & 0x100) { + int idx = force_disp_pic_index & 0xff; + struct avs2_frame_s *pic = NULL; + if (idx >= 0 + && idx < dec->avs2_dec.ref_maxbuffer) + pic = get_pic_by_index(dec, idx); + if (pic == NULL) + return NULL; + if (force_disp_pic_index & 0x200) + return NULL; + + vf = &dec->vframe_dummy; + + set_vframe(dec, vf, pic, 1); + + force_disp_pic_index |= 0x200; + return vf; + } + + if (kfifo_get(&dec->display_q, &vf)) { + uint8_t index = vf->index & 0xff; + + if (index >= 0 && index < dec->used_buf_num) { + struct avs2_frame_s *pic = get_pic_by_index(dec, index); + dec->vf_get_count++; + avs2_print(dec, AVS2_DBG_BUFMGR, + "%s index 0x%x pos %d getcount %d type 0x%x w/h %d/%d, pts %d, %lld\n", + __func__, index, + pic->imgtr_fwRefDistance, + dec->vf_get_count, + vf->type, + vf->width, vf->height, + vf->pts, + vf->pts_us64); + return vf; + } + } + return NULL; +} + +static void vavs2_vf_put(struct vframe_s *vf, void *op_arg) +{ + struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)op_arg; + uint8_t index = vf->index & 0xff; + + if (vf == (&dec->vframe_dummy)) + return; + + kfifo_put(&dec->newframe_q, (const struct vframe_s *)vf); + dec->vf_put_count++; + avs2_print(dec, AVS2_DBG_BUFMGR, + "%s index putcount 0x%x %d\n", + __func__, vf->index, + dec->vf_put_count); + + if (index >= 0 + && index < dec->used_buf_num) { + unsigned long flags; + struct avs2_frame_s *pic; + + lock_buffer(dec, flags); + pic = get_pic_by_index(dec, index); + if (pic && pic->vf_ref > 0) + pic->vf_ref--; + else { + if (pic) + avs2_print(dec, 0, + "%s, error pic (index %d) vf_ref is %d\n", + __func__, index, pic->vf_ref); + else + avs2_print(dec, 0, + "%s, error pic (index %d) is NULL\n", + __func__, index); + } + if (dec->wait_buf) + WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, + 0x1); + dec->last_put_idx = index; + dec->new_frame_displayed++; + unlock_buffer(dec, flags); + } + +} + +static int vavs2_event_cb(int type, void *data, void *private_data) +{ + return 0; +} + +static struct avs2_frame_s *get_disp_pic(struct AVS2Decoder_s *dec) +{ + struct avs2_decoder *avs2_dec = &dec->avs2_dec; + struct avs2_frame_s *pic = NULL; + int32_t j; + int32_t pre_disp_count_min = 0x7fffffff; + for (j = 0; j < avs2_dec->ref_maxbuffer; j++) { + if (avs2_dec->fref[j]->to_prepare_disp && + avs2_dec->fref[j]->to_prepare_disp < + pre_disp_count_min) { + pre_disp_count_min = + avs2_dec->fref[j]->to_prepare_disp; + pic = avs2_dec->fref[j]; + } + } + if (pic) + pic->to_prepare_disp = 0; + + return pic; + +} + +static void set_vframe(struct AVS2Decoder_s *dec, + struct vframe_s *vf, struct avs2_frame_s *pic, u8 dummy) +{ + unsigned long flags; + int stream_offset; + stream_offset = pic->stream_offset; + avs2_print(dec, AVS2_DBG_BUFMGR, + "%s index = %d pos = %d\r\n", + __func__, pic->index, + pic->imgtr_fwRefDistance); + + if (pic->double_write_mode) + set_canvas(dec, pic); + + display_frame_count[dec->index]++; + + if (!dummy) { +#ifdef MULTI_INSTANCE_SUPPORT + if (vdec_frame_based(hw_to_vdec(dec))) { + vf->pts = pic->pts; + vf->pts_us64 = pic->pts64; + } else +#endif + /* if (pts_lookup_offset(PTS_TYPE_VIDEO, + stream_offset, &vf->pts, 0) != 0) { */ + if (pts_lookup_offset_us64 + (PTS_TYPE_VIDEO, stream_offset, &vf->pts, 0, + &vf->pts_us64) != 0) { +#ifdef DEBUG_PTS + dec->pts_missed++; +#endif + vf->pts = 0; + vf->pts_us64 = 0; + } +#ifdef DEBUG_PTS + else + dec->pts_hit++; +#endif + if (pts_unstable) + dec->pts_mode = PTS_NONE_REF_USE_DURATION; + + if ((dec->pts_mode == PTS_NORMAL) && (vf->pts != 0) + && dec->get_frame_dur) { + int pts_diff = (int)vf->pts - dec->last_lookup_pts; + + if (pts_diff < 0) { + dec->pts_mode_switching_count++; + dec->pts_mode_recovery_count = 0; + + if (dec->pts_mode_switching_count >= + PTS_MODE_SWITCHING_THRESHOLD) { + dec->pts_mode = + PTS_NONE_REF_USE_DURATION; + pr_info + ("HEVC: switch to n_d mode.\n"); + } + + } else { + int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD; + dec->pts_mode_recovery_count++; + if (dec->pts_mode_recovery_count > p) { + dec->pts_mode_switching_count = 0; + dec->pts_mode_recovery_count = 0; + } + } + } + + if (vf->pts != 0) + dec->last_lookup_pts = vf->pts; +#if 0 + if ((dec->pts_mode == PTS_NONE_REF_USE_DURATION) + && (slice_type != KEY_FRAME)) + vf->pts = dec->last_pts + DUR2PTS(dec->frame_dur); +#endif + dec->last_pts = vf->pts; + + if (vf->pts_us64 != 0) + dec->last_lookup_pts_us64 = vf->pts_us64; + +#if 0 + if ((dec->pts_mode == PTS_NONE_REF_USE_DURATION) + && (slice_type != KEY_FRAME)) { + vf->pts_us64 = + dec->last_pts_us64 + + (DUR2PTS(dec->frame_dur) * 100 / 9); + } +#endif + dec->last_pts_us64 = vf->pts_us64; + avs2_print(dec, AVS2_DBG_OUT_PTS, + "avs2 dec out pts: vf->pts=%d, vf->pts_us64 = %lld\n", + vf->pts, vf->pts_us64); + + } + + vf->index = 0xff00 | pic->index; + + if (pic->double_write_mode & 0x10) { + /* double write only */ + vf->compBodyAddr = 0; + vf->compHeadAddr = 0; + } else { +#ifdef AVS2_10B_MMU + vf->compBodyAddr = 0; + vf->compHeadAddr = pic->header_adr; +#else + vf->compBodyAddr = pic->mc_y_adr; /*body adr*/ + vf->compHeadAddr = pic->mc_y_adr + + pic->comp_body_size; + /*head adr*/ +#endif + } + if (pic->double_write_mode) { + vf->type = VIDTYPE_PROGRESSIVE | + VIDTYPE_VIU_FIELD; + vf->type |= VIDTYPE_VIU_NV21; + if (pic->double_write_mode == 3) { + vf->type |= VIDTYPE_COMPRESS; +#ifdef AVS2_10B_MMU + vf->type |= VIDTYPE_SCATTER; +#endif + } +#ifdef MULTI_INSTANCE_SUPPORT + if (dec->m_ins_flag) { + vf->canvas0Addr = vf->canvas1Addr = -1; + vf->plane_num = 2; + vf->canvas0_config[0] = + pic->canvas_config[0]; + vf->canvas0_config[1] = + pic->canvas_config[1]; + + vf->canvas1_config[0] = + pic->canvas_config[0]; + vf->canvas1_config[1] = + pic->canvas_config[1]; + + } else +#endif + vf->canvas0Addr = vf->canvas1Addr = + spec2canvas(pic); + } else { + vf->canvas0Addr = vf->canvas1Addr = 0; + vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD; +#ifdef AVS2_10B_MMU + vf->type |= VIDTYPE_SCATTER; +#endif + } + + switch (pic->bit_depth) { + case AVS2_BITS_8: + vf->bitdepth = BITDEPTH_Y8 | + BITDEPTH_U8 | BITDEPTH_V8; + break; + case AVS2_BITS_10: + case AVS2_BITS_12: + vf->bitdepth = BITDEPTH_Y10 | + BITDEPTH_U10 | BITDEPTH_V10; + break; + default: + vf->bitdepth = BITDEPTH_Y10 | + BITDEPTH_U10 | BITDEPTH_V10; + break; + } + if ((vf->type & VIDTYPE_COMPRESS) == 0) + vf->bitdepth = + BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8; + if (pic->bit_depth == AVS2_BITS_8) + vf->bitdepth |= BITDEPTH_SAVING_MODE; + + set_frame_info(dec, vf); + /* if((vf->width!=pic->width)| + (vf->height!=pic->height)) */ + /* pr_info("aaa: %d/%d, %d/%d\n", + vf->width,vf->height, pic->width, + pic->height); */ + vf->width = pic->pic_w / + get_double_write_ratio(dec, + pic->double_write_mode); + vf->height = pic->pic_h / + get_double_write_ratio(dec, + pic->double_write_mode); + if (force_w_h != 0) { + vf->width = (force_w_h >> 16) & 0xffff; + vf->height = force_w_h & 0xffff; + } + vf->compWidth = pic->pic_w; + vf->compHeight = pic->pic_h; + if (force_fps & 0x100) { + u32 rate = force_fps & 0xff; + if (rate) + vf->duration = 96000/rate; + else + vf->duration = 0; + } +#ifdef AVS2_10B_MMU + if (vf->type & VIDTYPE_SCATTER) { + vf->mem_handle = decoder_mmu_box_get_mem_handle( + dec->mmu_box, + pic->index); + vf->mem_head_handle = decoder_bmmu_box_get_mem_handle( + dec->bmmu_box, + HEADER_BUFFER_IDX(pic->index)); + } else { + vf->mem_handle = decoder_bmmu_box_get_mem_handle( + dec->bmmu_box, + VF_BUFFER_IDX(pic->index)); + vf->mem_head_handle = decoder_bmmu_box_get_mem_handle( + dec->bmmu_box, + HEADER_BUFFER_IDX(pic->index)); + } +#else + vf->mem_handle = decoder_bmmu_box_get_mem_handle( + dec->bmmu_box, + VF_BUFFER_IDX(pic->index)); +#endif + + if (!dummy) { + lock_buffer(dec, flags); + pic->vf_ref = 1; + unlock_buffer(dec, flags); + } + dec->vf_pre_count++; +} + +static int avs2_prepare_display_buf(struct AVS2Decoder_s *dec) +{ +#ifndef NO_DISPLAY + struct vframe_s *vf = NULL; + /*unsigned short slice_type;*/ + struct avs2_frame_s *pic; + while (1) { + pic = get_disp_pic(dec); + if (pic == NULL) + break; + + if (force_disp_pic_index & 0x100) { + /*recycle directly*/ + continue; + } + + if (kfifo_get(&dec->newframe_q, &vf) == 0) { + pr_info("fatal error, no available buffer slot."); + return -1; + } + + if (vf) { + set_vframe(dec, vf, pic, 0); + + kfifo_put(&dec->display_q, (const struct vframe_s *)vf); + + #ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + /*count info*/ + gvs->frame_dur = dec->frame_dur; + vdec_count_info(gvs, 0, stream_offset); + #endif + vf_notify_receiver(dec->provider_name, + VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL); + } + } +/*!NO_DISPLAY*/ +#endif + return 0; +} + +static void get_rpm_param(union param_u *params) +{ + int i; + unsigned int data32; + if (debug & AVS2_DBG_BUFMGR) + pr_info("enter %s\r\n", __func__); + for (i = 0; i < (RPM_END - RPM_BEGIN); i++) { + do { + data32 = READ_VREG(RPM_CMD_REG); + /*pr_info("%x\n", data32);*/ + } while ((data32 & 0x10000) == 0); + params->l.data[i] = data32&0xffff; + /*pr_info("%x\n", data32);*/ + WRITE_VREG(RPM_CMD_REG, 0); + } + if (debug & AVS2_DBG_BUFMGR) + pr_info("leave %s\r\n", __func__); +} +static void debug_buffer_mgr_more(struct AVS2Decoder_s *dec) +{ + int i; + if (!(debug & AVS2_DBG_BUFMGR_MORE)) + return; + pr_info("avs2_param: (%d)\n", dec->avs2_dec.img.number); + for (i = 0; i < (RPM_END-RPM_BEGIN); i++) { + pr_info("%04x ", dec->avs2_dec.param.l.data[i]); + if (((i + 1) & 0xf) == 0) + pr_info("\n"); + } +} + +#ifdef AVS2_10B_MMU +static void avs2_recycle_mmu_buf_tail(struct AVS2Decoder_s *dec) +{ + if (dec->cur_fb_idx_mmu != INVALID_IDX) { + if (dec->used_4k_num == -1) + dec->used_4k_num = + (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16); + decoder_mmu_box_free_idx_tail(dec->mmu_box, + dec->cur_fb_idx_mmu, dec->used_4k_num); + + dec->cur_fb_idx_mmu = INVALID_IDX; + dec->used_4k_num = -1; + } +} + +static void avs2_recycle_mmu_buf(struct AVS2Decoder_s *dec) +{ + if (dec->cur_fb_idx_mmu != INVALID_IDX) { + decoder_mmu_box_free_idx(dec->mmu_box, + dec->cur_fb_idx_mmu); + + dec->cur_fb_idx_mmu = INVALID_IDX; + dec->used_4k_num = -1; + } +} +#endif + +static void dec_again_process(struct AVS2Decoder_s *dec) +{ + amhevc_stop(); + dec->dec_result = DEC_RESULT_AGAIN; + if (dec->process_state == + PROC_STATE_DECODESLICE) { + dec->process_state = + PROC_STATE_SENDAGAIN; +#ifdef AVS2_10B_MMU + avs2_recycle_mmu_buf(dec); +#endif + } + reset_process_time(dec); + vdec_schedule_work(&dec->work); +} + +static uint32_t log2i(uint32_t val) +{ + uint32_t ret = -1; + while (val != 0) { + val >>= 1; + ret++; + } + return ret; +} + +static irqreturn_t vavs2_isr_thread_fn(int irq, void *data) +{ + struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)data; + unsigned int dec_status = dec->dec_status; + int i, ret; + int32_t start_code = 0; + + /*if (dec->wait_buf) + pr_info("set wait_buf to 0\r\n"); + */ + avs2_print(dec, AVS2_DBG_BUFMGR_MORE, + "%s %x\n", __func__, dec_status); +#ifndef G12A_BRINGUP_DEBUG + if (dec->eos) { + PRINT_LINE(); + dec->process_busy = 0; + return IRQ_HANDLED; + } +#endif + dec->wait_buf = 0; + if ((dec_status == HEVC_NAL_DECODE_DONE) || + (dec_status == AVS2_DECODE_TIMEOUT) || + (dec_status == AVS2_DECODE_BUFEMPTY) + ) { + PRINT_LINE(); + if (dec->m_ins_flag) { + reset_process_time(dec); + if (!vdec_frame_based(hw_to_vdec(dec))) + dec_again_process(dec); + else { + dec->dec_result = DEC_RESULT_GET_DATA; + vdec_schedule_work(&dec->work); + } + } + dec->process_busy = 0; + return IRQ_HANDLED; + } else if (dec_status == HEVC_DECPIC_DATA_DONE) { + PRINT_LINE(); + if (dec->m_ins_flag) { + reset_process_time(dec); + dec->dec_result = DEC_RESULT_DONE; + amhevc_stop(); + vdec_schedule_work(&dec->work); + } + + dec->process_busy = 0; + return IRQ_HANDLED; + } + PRINT_LINE(); + + if (dec_status == AVS2_EOS) { + if (dec->m_ins_flag) + reset_process_time(dec); + + avs2_print(dec, AVS2_DBG_BUFMGR, + "AVS2_EOS, flush buffer\r\n"); + + avs2_post_process(&dec->avs2_dec); + avs2_prepare_display_buf(dec); + + avs2_print(dec, AVS2_DBG_BUFMGR, + "send AVS2_10B_DISCARD_NAL\r\n"); + WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_10B_DISCARD_NAL); + dec->process_busy = 0; + if (dec->m_ins_flag) { + dec->dec_result = DEC_RESULT_DONE; + amhevc_stop(); + vdec_schedule_work(&dec->work); + } + return IRQ_HANDLED; + } else if (dec_status == AVS2_DECODE_OVER_SIZE) { + avs2_print(dec, 0, + "avs2 decode oversize !!\n"); + debug |= (AVS2_DBG_DIS_LOC_ERROR_PROC | + AVS2_DBG_DIS_SYS_ERROR_PROC); + dec->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW; + if (dec->m_ins_flag) + reset_process_time(dec); + dec->process_busy = 0; + return IRQ_HANDLED; + } + PRINT_LINE(); + + if (dec->m_ins_flag) + reset_process_time(dec); + + if ((dec_status == AVS2_HEAD_PIC_I_READY) + || (dec_status == AVS2_HEAD_PIC_PB_READY)) { + PRINT_LINE(); + + if (dec->avs2_dec.hc.cur_pic != NULL && + dec->process_state != PROC_STATE_SENDAGAIN) { + int32_t ii; +#ifdef AVS2_10B_MMU + avs2_recycle_mmu_buf_tail(dec); +#endif + avs2_post_process(&dec->avs2_dec); + avs2_prepare_display_buf(dec); + dec->avs2_dec.hc.cur_pic = NULL; +#ifdef AVS2_10B_MMU + for (ii = 0; ii < dec->avs2_dec.ref_maxbuffer; + ii++) { + if (dec->avs2_dec.fref[ii]-> + refered_by_others == 0 && + dec->avs2_dec.fref[ii]-> + bg_flag == 0 && + dec->avs2_dec.fref[ii]-> + is_output == -1 && + dec->avs2_dec.fref[ii]-> + mmu_alloc_flag && + dec->avs2_dec.fref[ii]-> + vf_ref == 0) { + dec->avs2_dec.fref[ii]-> + mmu_alloc_flag = 0; + /*release_buffer_4k( + dec->avs2_dec.fref[ii]->index);*/ + decoder_mmu_box_free_idx(dec->mmu_box, + dec->avs2_dec.fref[ii]->index); + } + } +#endif + } + + if (debug & AVS2_DBG_SEND_PARAM_WITH_REG) { + get_rpm_param( + &dec->avs2_dec.param); + } else { + PRINT_LINE(); + dma_sync_single_for_cpu( + amports_get_dma_device(), + dec->rpm_phy_addr, + RPM_BUF_SIZE, + DMA_FROM_DEVICE); + + for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) { + int ii; + for (ii = 0; ii < 4; ii++) + dec->avs2_dec.param.l.data[i + ii] = + dec->rpm_ptr[i + 3 - ii]; + } + } + PRINT_LINE(); + + debug_buffer_mgr_more(dec); + + } + + if (dec_status == AVS2_HEAD_SEQ_READY) + start_code = SEQUENCE_HEADER_CODE; + else if (dec_status == AVS2_HEAD_PIC_I_READY) + start_code = I_PICTURE_START_CODE; + else if (dec_status == AVS2_HEAD_PIC_PB_READY) + start_code = PB_PICTURE_START_CODE; + else if (dec_status == AVS2_HEAD_SEQ_END_READY) + start_code = SEQUENCE_END_CODE; + else if (dec_status == AVS2_STARTCODE_SEARCH_DONE) + start_code = READ_VREG(CUR_NAL_UNIT_TYPE); + + PRINT_LINE(); + avs2_prepare_header(&dec->avs2_dec, start_code); + + if (start_code == SEQUENCE_HEADER_CODE || + start_code == VIDEO_EDIT_CODE) + WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE); + else if (start_code == I_PICTURE_START_CODE || + start_code == PB_PICTURE_START_CODE) { + ret = 0; + if (dec->process_state != PROC_STATE_SENDAGAIN) { + if (dec->pic_list_init_flag == 0) { + int32_t lcu_size_log2 = + log2i(dec->avs2_dec.param.p.lcu_size); + + avs2_init_global_buffers(&dec->avs2_dec); + /*avs2_dec->m_bg->index is + set to dec->used_buf_num - 1*/ + init_pic_list(dec, lcu_size_log2); + init_pic_list_hw(dec); + } + ret = avs2_process_header(&dec->avs2_dec); + if (!dec->m_ins_flag) + dec->slice_idx++; + } + PRINT_LINE(); +#ifdef AVS2_10B_MMU + if (ret >= 0) { + ret = avs2_alloc_mmu(dec, + dec->avs2_dec.hc.cur_pic->index, + dec->avs2_dec.img.width, + dec->avs2_dec.img.height, + dec->avs2_dec.input.sample_bit_depth, + dec->frame_mmu_map_addr); + if (ret >= 0) { + dec->cur_fb_idx_mmu = + dec->avs2_dec.hc.cur_pic->index; + dec->avs2_dec.hc.cur_pic->mmu_alloc_flag = 1; + } else + pr_err("can't alloc need mmu1,idx %d ret =%d\n", + dec->avs2_dec.hc.cur_pic->index, + ret); + } +#endif + if (ret < 0) { + avs2_print(dec, AVS2_DBG_BUFMGR, + "avs2_bufmgr_process=> %d, AVS2_10B_DISCARD_NAL\r\n", + ret); + WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_10B_DISCARD_NAL); + dec->process_busy = 0; + #ifdef AVS2_10B_MMU + avs2_recycle_mmu_buf(dec); + #endif + if (dec->m_ins_flag) { + dec->dec_result = DEC_RESULT_DONE; + amhevc_stop(); + vdec_schedule_work(&dec->work); + } + + return IRQ_HANDLED; + } else { + PRINT_LINE(); + /* + struct PIC_BUFFER_CONFIG_s *cur_pic + = &cm->cur_frame->buf; + cur_pic->decode_idx = dec->frame_count; + */ + if (dec->process_state != PROC_STATE_SENDAGAIN) { + if (!dec->m_ins_flag) { + dec->frame_count++; + decode_frame_count[dec->index] + = dec->frame_count; + } + /*MULTI_INSTANCE_SUPPORT*/ + if (dec->chunk) { + dec->avs2_dec.hc.cur_pic->pts = + dec->chunk->pts; + dec->avs2_dec.hc.cur_pic->pts64 = + dec->chunk->pts64; + } + /**/ + } + dec->avs2_dec.hc.cur_pic->bit_depth + = dec->avs2_dec.input.sample_bit_depth; + dec->avs2_dec.hc.cur_pic->double_write_mode + = get_double_write_mode(dec); + + PRINT_LINE(); + config_mc_buffer(dec); + config_mcrcc_axi_hw(dec); + config_mpred_hw(dec); + config_dblk_hw(dec); + config_sao_hw(dec); + config_alf_hw(dec); + config_other_hw(dec); + + avs2_print(dec, AVS2_DBG_BUFMGR_MORE, + "=>fref0 imgtr_fwRefDistance %d, fref1 imgtr_fwRefDistance %d, dis2/dis3/dis4 %d %d %d img->tr %d\n", + dec->avs2_dec.fref[0]->imgtr_fwRefDistance, + dec->avs2_dec.fref[1]->imgtr_fwRefDistance, + dec->avs2_dec.fref[2]->imgtr_fwRefDistance, + dec->avs2_dec.fref[3]->imgtr_fwRefDistance, + dec->avs2_dec.fref[4]->imgtr_fwRefDistance, + dec->avs2_dec.img.tr); + + WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE); + + } + dec->process_busy = 0; + dec->process_state = PROC_STATE_DECODESLICE; + + if (dec->m_ins_flag) + start_process_time(dec); + } + dec->process_busy = 0; + PRINT_LINE(); + return IRQ_HANDLED; +} + +static irqreturn_t vavs2_isr(int irq, void *data) +{ + int i; + unsigned int dec_status; + struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)data; + uint debug_tag; + WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1); + + dec_status = READ_VREG(HEVC_DEC_STATUS_REG); + + if (!dec) + return IRQ_HANDLED; + if (dec->init_flag == 0) + return IRQ_HANDLED; + if (dec->process_busy)/*on process.*/ + return IRQ_HANDLED; + dec->dec_status = dec_status; + dec->process_busy = 1; + if (debug & AVS2_DBG_IRQ_EVENT) + avs2_print(dec, 0, + "avs2 isr dec status = 0x%x, lcu 0x%x shiftbyte 0x%x (%x %x lev %x, wr %x, rd %x)\n", + dec_status, READ_VREG(HEVC_PARSER_LCU_START), + READ_VREG(HEVC_SHIFT_BYTE_COUNT), + READ_VREG(HEVC_STREAM_START_ADDR), + READ_VREG(HEVC_STREAM_END_ADDR), + READ_VREG(HEVC_STREAM_LEVEL), + READ_VREG(HEVC_STREAM_WR_PTR), + READ_VREG(HEVC_STREAM_RD_PTR) + ); + + debug_tag = READ_HREG(DEBUG_REG1); + if (debug_tag & 0x10000) { + dma_sync_single_for_cpu( + amports_get_dma_device(), + dec->lmem_phy_addr, + LMEM_BUF_SIZE, + DMA_FROM_DEVICE); + + pr_info("LMEM:\n", READ_HREG(DEBUG_REG1)); + for (i = 0; i < 0x400; i += 4) { + int ii; + if ((i & 0xf) == 0) + pr_info("%03x: ", i); + for (ii = 0; ii < 4; ii++) { + pr_info("%04x ", + dec->lmem_ptr[i + 3 - ii]); + } + if (((i + ii) & 0xf) == 0) + pr_info("\n"); + } + + if (((udebug_pause_pos & 0xffff) + == (debug_tag & 0xffff)) && + (udebug_pause_decode_idx == 0 || + udebug_pause_decode_idx == dec->decode_idx) && + (udebug_pause_val == 0 || + udebug_pause_val == READ_HREG(DEBUG_REG2))) { + udebug_pause_pos &= 0xffff; + dec->ucode_pause_pos = udebug_pause_pos; + } else if (debug_tag & 0x20000) + dec->ucode_pause_pos = 0xffffffff; + if (dec->ucode_pause_pos) + reset_process_time(dec); + else + WRITE_HREG(DEBUG_REG1, 0); + } else if (debug_tag != 0) { + pr_info( + "dbg%x: %x lcu %x\n", READ_HREG(DEBUG_REG1), + READ_HREG(DEBUG_REG2), + READ_VREG(HEVC_PARSER_LCU_START)); + if (((udebug_pause_pos & 0xffff) + == (debug_tag & 0xffff)) && + (udebug_pause_decode_idx == 0 || + udebug_pause_decode_idx == dec->decode_idx) && + (udebug_pause_val == 0 || + udebug_pause_val == READ_HREG(DEBUG_REG2))) { + udebug_pause_pos &= 0xffff; + dec->ucode_pause_pos = udebug_pause_pos; + } + if (dec->ucode_pause_pos) + reset_process_time(dec); + else + WRITE_HREG(DEBUG_REG1, 0); + dec->process_busy = 0; + return IRQ_HANDLED; + } + + if (!dec->m_ins_flag) { + if (dec->error_flag == 1) { + dec->error_flag = 2; + dec->process_busy = 0; + return IRQ_HANDLED; + } else if (dec->error_flag == 3) { + dec->process_busy = 0; + return IRQ_HANDLED; + } + + if ((dec->pic_list_init_flag) && + get_free_buf_count(dec) <= 0) { + /* + if (dec->wait_buf == 0) + pr_info("set wait_buf to 1\r\n"); + */ + dec->wait_buf = 1; + dec->process_busy = 0; + if (debug & AVS2_DBG_IRQ_EVENT) + avs2_print(dec, 0, "wait_buf\n"); + return IRQ_HANDLED; + } else if (force_disp_pic_index) { + dec->process_busy = 0; + return IRQ_HANDLED; + } + } + return IRQ_WAKE_THREAD; +} + +static void vavs2_put_timer_func(unsigned long arg) +{ + struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)arg; + struct timer_list *timer = &dec->timer; + uint8_t empty_flag; + unsigned int buf_level; + + enum receviver_start_e state = RECEIVER_INACTIVE; + if (dec->m_ins_flag) { + if (hw_to_vdec(dec)->next_status + == VDEC_STATUS_DISCONNECTED) { + dec->dec_result = DEC_RESULT_FORCE_EXIT; + vdec_schedule_work(&dec->work); + avs2_print(dec, AVS2_DBG_BUFMGR, + "vdec requested to be disconnected\n"); + return; + } + } + if (dec->init_flag == 0) { + if (dec->stat & STAT_TIMER_ARM) { + timer->expires = jiffies + PUT_INTERVAL; + add_timer(&dec->timer); + } + return; + } + if (dec->m_ins_flag == 0) { + if (vf_get_receiver(dec->provider_name)) { + state = + vf_notify_receiver(dec->provider_name, + VFRAME_EVENT_PROVIDER_QUREY_STATE, + NULL); + if ((state == RECEIVER_STATE_NULL) + || (state == RECEIVER_STATE_NONE)) + state = RECEIVER_INACTIVE; + } else + state = RECEIVER_INACTIVE; + + empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1; + /* error watchdog */ + if (empty_flag == 0) { + /* decoder has input */ + if ((debug & AVS2_DBG_DIS_LOC_ERROR_PROC) == 0) { + + buf_level = READ_VREG(HEVC_STREAM_LEVEL); + /* receiver has no buffer to recycle */ + if ((state == RECEIVER_INACTIVE) && + (kfifo_is_empty(&dec->display_q) && + buf_level > 0x200) + ) { + WRITE_VREG + (HEVC_ASSIST_MBOX0_IRQ_REG, + 0x1); + } + } + + if ((debug & AVS2_DBG_DIS_SYS_ERROR_PROC) == 0) { + /* receiver has no buffer to recycle */ + /*if ((state == RECEIVER_INACTIVE) && + (kfifo_is_empty(&dec->display_q))) { + pr_info("avs2 something error,need reset\n"); + }*/ + } + } + } else { + if ( + (decode_timeout_val > 0) && + (dec->start_process_time > 0) && + ((1000 * (jiffies - dec->start_process_time) / HZ) + > decode_timeout_val) + ) { + int current_lcu_idx = + READ_VREG(HEVC_PARSER_LCU_START) + & 0xffffff; + if (dec->last_lcu_idx == current_lcu_idx) { + if (dec->decode_timeout_count > 0) + dec->decode_timeout_count--; + if (dec->decode_timeout_count == 0) { + if (input_frame_based( + hw_to_vdec(dec)) || + (READ_VREG(HEVC_STREAM_LEVEL) > 0x200)) + timeout_process(dec); + else { + avs2_print(dec, 0, + "timeout & empty, again\n"); + dec_again_process(dec); + } + } + } else { + start_process_time(dec); + dec->last_lcu_idx = current_lcu_idx; + } + } + } + + if ((dec->ucode_pause_pos != 0) && + (dec->ucode_pause_pos != 0xffffffff) && + udebug_pause_pos != dec->ucode_pause_pos) { + dec->ucode_pause_pos = 0; + WRITE_HREG(DEBUG_REG1, 0); + } + if (debug & AVS2_DBG_FORCE_SEND_AGAIN) { + pr_info( + "Force Send Again\r\n"); + debug &= ~AVS2_DBG_FORCE_SEND_AGAIN; + reset_process_time(dec); + dec->dec_result = DEC_RESULT_AGAIN; + if (dec->process_state == + PROC_STATE_DECODESLICE) { +#ifdef AVS2_10B_MMU + avs2_recycle_mmu_buf(dec); +#endif + dec->process_state = + PROC_STATE_SENDAGAIN; + } + amhevc_stop(); + + vdec_schedule_work(&dec->work); + } + + if (debug & AVS2_DBG_DUMP_DATA) { + debug &= ~AVS2_DBG_DUMP_DATA; + avs2_print(dec, 0, + "%s: chunk size 0x%x off 0x%x sum 0x%x\n", + __func__, + dec->chunk->size, + dec->chunk->offset, + get_data_check_sum(dec, dec->chunk->size) + ); + dump_data(dec, dec->chunk->size); + } + if (debug & AVS2_DBG_DUMP_PIC_LIST) { + dump_pic_list(dec); + debug &= ~AVS2_DBG_DUMP_PIC_LIST; + } + if (debug & AVS2_DBG_TRIG_SLICE_SEGMENT_PROC) { + WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1); + debug &= ~AVS2_DBG_TRIG_SLICE_SEGMENT_PROC; + } + /*if (debug & AVS2_DBG_HW_RESET) { + }*/ + + if (radr != 0) { + if (rval != 0) { + WRITE_VREG(radr, rval); + pr_info("WRITE_VREG(%x,%x)\n", radr, rval); + } else + pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr)); + rval = 0; + radr = 0; + } + if (pop_shorts != 0) { + int i; + u32 sum = 0; + pr_info("pop stream 0x%x shorts\r\n", pop_shorts); + for (i = 0; i < pop_shorts; i++) { + u32 data = + (READ_HREG(HEVC_SHIFTED_DATA) >> 16); + WRITE_HREG(HEVC_SHIFT_COMMAND, + (1<<7)|16); + if ((i & 0xf) == 0) + pr_info("%04x:", i); + pr_info("%04x ", data); + if (((i + 1) & 0xf) == 0) + pr_info("\r\n"); + sum += data; + } + pr_info("\r\nsum = %x\r\n", sum); + pop_shorts = 0; + } + if (dbg_cmd != 0) { + if (dbg_cmd == 1) { + u32 disp_laddr; + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB && + get_double_write_mode(dec) == 0) { + disp_laddr = + READ_VCBUS_REG(AFBC_BODY_BADDR) << 4; + } else { + struct canvas_s cur_canvas; + canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0) + & 0xff), &cur_canvas); + disp_laddr = cur_canvas.addr; + } + pr_info("current displayed buffer address %x\r\n", + disp_laddr); + } + dbg_cmd = 0; + } + /*don't changed at start.*/ + if (dec->get_frame_dur && dec->show_frame_num > 60 && + dec->frame_dur > 0 && dec->saved_resolution != + frame_width * frame_height * + (96000 / dec->frame_dur)) { + int fps = 96000 / dec->frame_dur; + if (hevc_source_changed(VFORMAT_AVS2, + frame_width, frame_height, fps) > 0) + dec->saved_resolution = frame_width * + frame_height * fps; + } + + timer->expires = jiffies + PUT_INTERVAL; + add_timer(timer); +} + + +int vavs2_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus) +{ + struct AVS2Decoder_s *dec = + (struct AVS2Decoder_s *)vdec->private; + vstatus->frame_width = frame_width; + vstatus->frame_height = frame_height; + if (dec->frame_dur != 0) + vstatus->frame_rate = 96000 / dec->frame_dur; + else + vstatus->frame_rate = -1; + vstatus->error_count = 0; + vstatus->status = dec->stat | dec->fatal_error; + vstatus->frame_dur = dec->frame_dur; +#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + vstatus->bit_rate = gvs->bit_rate; + vstatus->frame_data = gvs->frame_data; + vstatus->total_data = gvs->total_data; + vstatus->frame_count = gvs->frame_count; + vstatus->error_frame_count = gvs->error_frame_count; + vstatus->drop_frame_count = gvs->drop_frame_count; + vstatus->total_data = gvs->total_data; + vstatus->samp_cnt = gvs->samp_cnt; + vstatus->offset = gvs->offset; + snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name), + "%s", DRIVER_NAME); +#endif + return 0; +} + +int vavs2_set_isreset(struct vdec_s *vdec, int isreset) +{ + is_reset = isreset; + return 0; +} + +static void vavs2_prot_init(struct AVS2Decoder_s *dec) +{ + unsigned int data32; + + avs2_config_work_space_hw(dec); + if (dec->pic_list_init_flag) + init_pic_list_hw(dec); + + avs2_init_decoder_hw(dec); + +#if 1 + avs2_print(dec, AVS2_DBG_BUFMGR_MORE, + "%s\n", __func__); + data32 = READ_VREG(HEVC_STREAM_CONTROL); + data32 = data32 | + (1 << 0)/*stream_fetch_enable*/ + ; + WRITE_VREG(HEVC_STREAM_CONTROL, data32); +#if 0 + data32 = READ_VREG(HEVC_SHIFT_STARTCODE); + if (data32 != 0x00000100) { + pr_info("avs2 prot init error %d\n", __LINE__); + return; + } + data32 = READ_VREG(HEVC_SHIFT_EMULATECODE); + if (data32 != 0x00000300) { + pr_info("avs2 prot init error %d\n", __LINE__); + return; + } + WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678); + WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0); + data32 = READ_VREG(HEVC_SHIFT_STARTCODE); + if (data32 != 0x12345678) { + pr_info("avs2 prot init error %d\n", __LINE__); + return; + } + data32 = READ_VREG(HEVC_SHIFT_EMULATECODE); + if (data32 != 0x9abcdef0) { + pr_info("avs2 prot init error %d\n", __LINE__); + return; + } +#endif + WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x00000100); + WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000000); +#endif + + + + WRITE_VREG(HEVC_WAIT_FLAG, 1); + + /* WRITE_VREG(HEVC_MPSR, 1); */ + + /* clear mailbox interrupt */ + WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1); + + /* enable mailbox interrupt */ + WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1); + + /* disable PSCALE for hardware sharing */ + WRITE_VREG(HEVC_PSCALE_CTRL, 0); + + WRITE_VREG(DEBUG_REG1, 0x0); + /*check vps/sps/pps/i-slice in ucode*/ + WRITE_VREG(NAL_SEARCH_CTL, 0x8); + + WRITE_VREG(DECODE_STOP_POS, udebug_flag); + +} + +static int vavs2_local_init(struct AVS2Decoder_s *dec) +{ + int i; + int ret; + int width, height; + + dec->gvs = vzalloc(sizeof(struct vdec_info)); + if (NULL == dec->gvs) { + avs2_print(dec, 0, + "the struct of vdec status malloc failed.\n"); + return -1; + } +#ifdef DEBUG_PTS + dec->pts_missed = 0; + dec->pts_hit = 0; +#endif + dec->new_frame_displayed = 0; + dec->last_put_idx = -1; + dec->saved_resolution = 0; + dec->get_frame_dur = false; + on_no_keyframe_skiped = 0; + width = dec->vavs2_amstream_dec_info.width; + height = dec->vavs2_amstream_dec_info.height; + dec->frame_dur = + (dec->vavs2_amstream_dec_info.rate == + 0) ? 3600 : dec->vavs2_amstream_dec_info.rate; + if (width && height) + dec->frame_ar = height * 0x100 / width; +/* +TODO:FOR VERSION +*/ + avs2_print(dec, AVS2_DBG_BUFMGR, + "avs2: ver (%d,%d) decinfo: %dx%d rate=%d\n", avs2_version, + 0, width, height, dec->frame_dur); + + if (dec->frame_dur == 0) + dec->frame_dur = 96000 / 24; + + INIT_KFIFO(dec->display_q); + INIT_KFIFO(dec->newframe_q); + + + for (i = 0; i < VF_POOL_SIZE; i++) { + const struct vframe_s *vf = &dec->vfpool[i]; + dec->vfpool[i].index = -1; + kfifo_put(&dec->newframe_q, vf); + } + + + ret = avs2_local_init(dec); + + return ret; +} + + +static s32 vavs2_init(struct vdec_s *vdec) +{ + int size = -1; + int fw_size = 0x1000 * 16; + struct firmware_s *fw = NULL; + struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *)vdec->private; + init_timer(&dec->timer); + + dec->stat |= STAT_TIMER_INIT; + if (vavs2_local_init(dec) < 0) + return -EBUSY; + + fw = vmalloc(sizeof(struct firmware_s) + fw_size); + if (IS_ERR_OR_NULL(fw)) + return -ENOMEM; +#ifdef MULTI_INSTANCE_SUPPORT + if (tee_enabled()) { + size = 1; + pr_debug ("laod\n"); + } else +#endif + size = get_firmware_data(VIDEO_DEC_AVS2_MMU, fw->data); + if (size < 0) { + pr_err("get firmware fail.\n"); + vfree(fw); + return -1; + } + avs2_print(dec, AVS2_DBG_BUFMGR, + "firmware size %d\n", size); + fw->len = fw_size; + + if (dec->m_ins_flag) { + dec->timer.data = (ulong) dec; + dec->timer.function = vavs2_put_timer_func; + dec->timer.expires = jiffies + PUT_INTERVAL; + + /*add_timer(&dec->timer); + + dec->stat |= STAT_TIMER_ARM; + dec->stat |= STAT_ISR_REG;*/ + + INIT_WORK(&dec->work, avs2_work); + dec->fw = fw; + + return 0; + } + + amhevc_enable(); + if (size == 1) + pr_info ("tee load ok\n"); + + if (amhevc_loadmc_ex(VFORMAT_AVS2, NULL, fw->data) < 0) { + amhevc_disable(); + vfree(fw); + return -EBUSY; + } + avs2_print(dec, AVS2_DBG_BUFMGR, + "firmware size %d\n", size); + + vfree(fw); + dec->stat |= STAT_MC_LOAD; + + /* enable AMRISC side protocol */ + vavs2_prot_init(dec); + + if (vdec_request_threaded_irq(VDEC_IRQ_0, + vavs2_isr, + vavs2_isr_thread_fn, + IRQF_ONESHOT,/*run thread on this irq disabled*/ + "vavs2-irq", (void *)dec)) { + pr_info("vavs2 irq register error.\n"); + amhevc_disable(); + return -ENOENT; + } + + dec->stat |= STAT_ISR_REG; + + dec->provider_name = PROVIDER_NAME; + vf_provider_init(&vavs2_vf_prov, PROVIDER_NAME, + &vavs2_vf_provider, dec); + vf_reg_provider(&vavs2_vf_prov); + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL); + if (dec->frame_dur != 0) { + if (!is_reset) + vf_notify_receiver(dec->provider_name, + VFRAME_EVENT_PROVIDER_FR_HINT, + (void *) + ((unsigned long)dec->frame_dur)); + } + dec->stat |= STAT_VF_HOOK; + + dec->timer.data = (ulong)dec; + dec->timer.function = vavs2_put_timer_func; + dec->timer.expires = jiffies + PUT_INTERVAL; + + + add_timer(&dec->timer); + + dec->stat |= STAT_TIMER_ARM; + + /* dec->stat |= STAT_KTHREAD; */ + + amhevc_start(); + + dec->stat |= STAT_VDEC_RUN; + + dec->init_flag = 1; + dec->process_busy = 0; + avs2_print(dec, AVS2_DBG_BUFMGR_MORE, + "%d, vavs2_init, RP=0x%x\n", + __LINE__, READ_VREG(HEVC_STREAM_RD_PTR)); + return 0; +} + +static int vmavs2_stop(struct AVS2Decoder_s *dec) +{ + dec->init_flag = 0; + + if (dec->stat & STAT_TIMER_ARM) { + del_timer_sync(&dec->timer); + dec->stat &= ~STAT_TIMER_ARM; + } + + if (dec->stat & STAT_VF_HOOK) { + if (!is_reset) + vf_notify_receiver(dec->provider_name, + VFRAME_EVENT_PROVIDER_FR_END_HINT, + NULL); + + vf_unreg_provider(&vavs2_vf_prov); + dec->stat &= ~STAT_VF_HOOK; + } + avs2_local_uninit(dec); + reset_process_time(dec); + cancel_work_sync(&dec->work); + uninit_mmu_buffers(dec); + + return 0; +} + + +static int vavs2_stop(struct AVS2Decoder_s *dec) +{ + + dec->init_flag = 0; + + if (dec->stat & STAT_VDEC_RUN) { + amhevc_stop(); + dec->stat &= ~STAT_VDEC_RUN; + } + + if (dec->stat & STAT_ISR_REG) { + if (!dec->m_ins_flag) + WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0); + vdec_free_irq(VDEC_IRQ_0, (void *)dec); + dec->stat &= ~STAT_ISR_REG; + } + + if (dec->stat & STAT_TIMER_ARM) { + del_timer_sync(&dec->timer); + dec->stat &= ~STAT_TIMER_ARM; + } + + if (dec->stat & STAT_VF_HOOK) { + if (!is_reset) + vf_notify_receiver(dec->provider_name, + VFRAME_EVENT_PROVIDER_FR_END_HINT, + NULL); + + vf_unreg_provider(&vavs2_vf_prov); + dec->stat &= ~STAT_VF_HOOK; + } + avs2_local_uninit(dec); + + if (dec->m_ins_flag) + cancel_work_sync(&dec->work); + else + amhevc_disable(); + uninit_mmu_buffers(dec); + vfree(dec->fw); + dec->fw = NULL; + + return 0; +} + +static int amvdec_avs2_mmu_init(struct AVS2Decoder_s *dec) +{ + int tvp_flag = vdec_secure(hw_to_vdec(dec)) ? + CODEC_MM_FLAGS_TVP : 0; + +#ifdef AVS2_10B_MMU + dec->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME, + dec->index, FRAME_BUFFERS, + 48 * SZ_1M, + tvp_flag + ); + if (!dec->mmu_box) { + pr_err("avs2 alloc mmu box failed!!\n"); + return -1; + } +#endif + dec->bmmu_box = decoder_bmmu_box_alloc_box( + DRIVER_NAME, + dec->index, + MAX_BMMU_BUFFER_NUM, + 4 + PAGE_SHIFT, + CODEC_MM_FLAGS_CMA_CLEAR | + CODEC_MM_FLAGS_FOR_VDECODER | + tvp_flag); + if (!dec->bmmu_box) { + pr_err("avs2 alloc bmmu box failed!!\n"); + return -1; + } + return 0; +} + +static int amvdec_avs2_probe(struct platform_device *pdev) +{ + struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; + struct BUF_s BUF[MAX_BUF_NUM]; + struct AVS2Decoder_s *dec; + int ret; + pr_info("%s\n", __func__); + mutex_lock(&vavs2_mutex); + + dec = vmalloc(sizeof(struct AVS2Decoder_s)); + if (dec == NULL) { + pr_info("failed to vamlloc amvdec_avs2 dec struct\n"); + return -ENOMEM; + } + gHevc = dec; + memcpy(&BUF[0], &dec->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM); + memset(dec, 0, sizeof(struct AVS2Decoder_s)); + memcpy(&dec->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM); + + dec->init_flag = 0; + + dec->eos = 0; + dec->start_process_time = 0; + dec->timeout_num = 0; + dec->fatal_error = 0; + dec->show_frame_num = 0; + if (pdata == NULL) { + avs2_print(dec, 0, + "\namvdec_avs2 memory resource undefined.\n"); + vfree(dec); + mutex_unlock(&vavs2_mutex); + return -EFAULT; + } + dec->m_ins_flag = 0; + dec->platform_dev = pdev; + platform_set_drvdata(pdev, pdata); + + if (amvdec_avs2_mmu_init(dec) < 0) { + vfree(dec); + mutex_unlock(&vavs2_mutex); + pr_err("avs2 alloc bmmu box failed!!\n"); + return -1; + } + + ret = decoder_bmmu_box_alloc_buf_phy(dec->bmmu_box, WORK_SPACE_BUF_ID, + work_buf_size, DRIVER_NAME, &pdata->mem_start); + if (ret < 0) { + uninit_mmu_buffers(dec); + vfree(dec); + mutex_unlock(&vavs2_mutex); + return ret; + } + dec->buf_size = work_buf_size; + + dec->buf_start = pdata->mem_start; + + + if (debug) { + avs2_print(dec, 0, + "===AVS2 decoder mem resource 0x%lx size 0x%x\n", + pdata->mem_start, dec->buf_size); + } + + if (pdata->sys_info) + dec->vavs2_amstream_dec_info = *pdata->sys_info; + else { + dec->vavs2_amstream_dec_info.width = 0; + dec->vavs2_amstream_dec_info.height = 0; + dec->vavs2_amstream_dec_info.rate = 30; + } + dec->cma_dev = pdata->cma_dev; + + pdata->private = dec; + pdata->dec_status = vavs2_dec_status; + pdata->set_isreset = vavs2_set_isreset; + is_reset = 0; + if (vavs2_init(pdata) < 0) { + pr_info("\namvdec_avs2 init failed.\n"); + avs2_local_uninit(dec); + uninit_mmu_buffers(dec); + vfree(dec); + mutex_unlock(&vavs2_mutex); + return -ENODEV; + } + /*set the max clk for smooth playing...*/ + hevc_source_changed(VFORMAT_AVS2, + 4096, 2048, 60); + mutex_unlock(&vavs2_mutex); + + return 0; +} + +static int amvdec_avs2_remove(struct platform_device *pdev) +{ + struct AVS2Decoder_s *dec = gHevc; + if (debug) + pr_info("amvdec_avs2_remove\n"); + + mutex_lock(&vavs2_mutex); + + vavs2_stop(dec); + + + hevc_source_changed(VFORMAT_AVS2, 0, 0, 0); + + +#ifdef DEBUG_PTS + pr_info("pts missed %ld, pts hit %ld, duration %d\n", + dec->pts_missed, dec->pts_hit, dec->frame_dur); +#endif + + vfree(dec); + + mutex_unlock(&vavs2_mutex); + + return 0; +} + +/****************************************/ + +static struct platform_driver amvdec_avs2_driver = { + .probe = amvdec_avs2_probe, + .remove = amvdec_avs2_remove, +#ifdef CONFIG_PM + .suspend = amhevc_suspend, + .resume = amhevc_resume, +#endif + .driver = { + .name = DRIVER_NAME, + } +}; + +static struct codec_profile_t amvdec_avs2_profile = { + .name = "avs2", + .profile = "" +}; + +static unsigned char get_data_check_sum + (struct AVS2Decoder_s *dec, int size) +{ + int jj; + int sum = 0; + u8 *data = ((u8 *)dec->chunk->block->start_virt) + + dec->chunk->offset; + for (jj = 0; jj < size; jj++) + sum += data[jj]; + return sum; +} + +static void dump_data(struct AVS2Decoder_s *dec, int size) +{ + int jj; + u8 *data = ((u8 *)dec->chunk->block->start_virt) + + dec->chunk->offset; + int padding_size = dec->chunk->offset & + (VDEC_FIFO_ALIGN - 1); + avs2_print(dec, 0, "padding: "); + for (jj = padding_size; jj > 0; jj--) + avs2_print_cont(dec, + 0, + "%02x ", *(data - jj)); + avs2_print_cont(dec, 0, "data adr %p\n", + data); + + for (jj = 0; jj < size; jj++) { + if ((jj & 0xf) == 0) + avs2_print(dec, + 0, + "%06x:", jj); + avs2_print_cont(dec, + 0, + "%02x ", data[jj]); + if (((jj + 1) & 0xf) == 0) + avs2_print(dec, + 0, + "\n"); + } + avs2_print(dec, + 0, + "\n"); +} + +static void avs2_work(struct work_struct *work) +{ + struct AVS2Decoder_s *dec = container_of(work, + struct AVS2Decoder_s, work); + struct vdec_s *vdec = hw_to_vdec(dec); + /* finished decoding one frame or error, + * notify vdec core to switch context + */ + avs2_print(dec, PRINT_FLAG_VDEC_DETAIL, + "%s dec_result %d %x %x %x\n", + __func__, + dec->dec_result, + READ_VREG(HEVC_STREAM_LEVEL), + READ_VREG(HEVC_STREAM_WR_PTR), + READ_VREG(HEVC_STREAM_RD_PTR)); + + if (((dec->dec_result == DEC_RESULT_GET_DATA) || + (dec->dec_result == DEC_RESULT_GET_DATA_RETRY)) + && (hw_to_vdec(dec)->next_status != + VDEC_STATUS_DISCONNECTED)) { + if (!vdec_has_more_input(vdec)) { + dec->dec_result = DEC_RESULT_EOS; + vdec_schedule_work(&dec->work); + return; + } + + if (dec->dec_result == DEC_RESULT_GET_DATA) { + avs2_print(dec, PRINT_FLAG_VDEC_STATUS, + "%s DEC_RESULT_GET_DATA %x %x %x\n", + __func__, + READ_VREG(HEVC_STREAM_LEVEL), + READ_VREG(HEVC_STREAM_WR_PTR), + READ_VREG(HEVC_STREAM_RD_PTR)); + vdec_vframe_dirty(vdec, dec->chunk); + vdec_clean_input(vdec); + } + + if (get_free_buf_count(dec) >= + run_ready_min_buf_num) { + int r; + int decode_size; + r = vdec_prepare_input(vdec, &dec->chunk); + if (r < 0) { + dec->dec_result = DEC_RESULT_GET_DATA_RETRY; + + avs2_print(dec, + PRINT_FLAG_VDEC_DETAIL, + "amvdec_vh265: Insufficient data\n"); + + vdec_schedule_work(&dec->work); + return; + } + dec->dec_result = DEC_RESULT_NONE; + avs2_print(dec, PRINT_FLAG_VDEC_STATUS, + "%s: chunk size 0x%x sum 0x%x\n", + __func__, r, + (debug & PRINT_FLAG_VDEC_STATUS) ? + get_data_check_sum(dec, r) : 0 + ); + if (debug & PRINT_FLAG_VDEC_DATA) + dump_data(dec, dec->chunk->size); + + decode_size = dec->chunk->size + + (dec->chunk->offset & (VDEC_FIFO_ALIGN - 1)); + + WRITE_VREG(HEVC_DECODE_SIZE, + READ_VREG(HEVC_DECODE_SIZE) + decode_size); + + vdec_enable_input(vdec); + + WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE); + + start_process_time(dec); + + } else{ + dec->dec_result = DEC_RESULT_GET_DATA_RETRY; + + avs2_print(dec, PRINT_FLAG_VDEC_DETAIL, + "amvdec_vh265: Insufficient data\n"); + + vdec_schedule_work(&dec->work); + } + return; + } else if (dec->dec_result == DEC_RESULT_DONE) { + /* if (!dec->ctx_valid) + dec->ctx_valid = 1; */ + dec->slice_idx++; + dec->frame_count++; + dec->process_state = PROC_STATE_INIT; + decode_frame_count[dec->index] = dec->frame_count; + +#ifdef AVS2_10B_MMU + dec->used_4k_num = + (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16); +#endif + avs2_print(dec, PRINT_FLAG_VDEC_STATUS, + "%s (===> %d) dec_result %d %x %x %x shiftbytes 0x%x decbytes 0x%x\n", + __func__, + dec->frame_count, + dec->dec_result, + READ_VREG(HEVC_STREAM_LEVEL), + READ_VREG(HEVC_STREAM_WR_PTR), + READ_VREG(HEVC_STREAM_RD_PTR), + READ_VREG(HEVC_SHIFT_BYTE_COUNT), + READ_VREG(HEVC_SHIFT_BYTE_COUNT) - + dec->start_shift_bytes + ); + vdec_vframe_dirty(hw_to_vdec(dec), dec->chunk); + } else if (dec->dec_result == DEC_RESULT_AGAIN) { + /* + stream base: stream buf empty or timeout + frame base: vdec_prepare_input fail + */ + if (!vdec_has_more_input(vdec)) { + dec->dec_result = DEC_RESULT_EOS; + vdec_schedule_work(&dec->work); + return; + } + } else if (dec->dec_result == DEC_RESULT_EOS) { + avs2_print(dec, PRINT_FLAG_VDEC_STATUS, + "%s: end of stream\n", + __func__); + dec->eos = 1; + avs2_post_process(&dec->avs2_dec); + avs2_prepare_display_buf(dec); + vdec_vframe_dirty(hw_to_vdec(dec), dec->chunk); + } else if (dec->dec_result == DEC_RESULT_FORCE_EXIT) { + avs2_print(dec, PRINT_FLAG_VDEC_STATUS, + "%s: force exit\n", + __func__); + if (dec->stat & STAT_VDEC_RUN) { + amhevc_stop(); + dec->stat &= ~STAT_VDEC_RUN; + } + + if (dec->stat & STAT_ISR_REG) { + if (!dec->m_ins_flag) + WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0); + vdec_free_irq(VDEC_IRQ_0, (void *)dec); + dec->stat &= ~STAT_ISR_REG; + } + } + + if (dec->stat & STAT_TIMER_ARM) { + del_timer_sync(&dec->timer); + dec->stat &= ~STAT_TIMER_ARM; + } + /* mark itself has all HW resource released and input released */ + vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC); + + if (dec->vdec_cb) + dec->vdec_cb(hw_to_vdec(dec), dec->vdec_cb_arg); +} + +static int avs2_hw_ctx_restore(struct AVS2Decoder_s *dec) +{ + /* new to do ... */ + vavs2_prot_init(dec); + return 0; +} + +static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask) +{ + struct AVS2Decoder_s *dec = + (struct AVS2Decoder_s *)vdec->private; + bool ret = 0; + avs2_print(dec, + PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__); + if (dec->eos) + return ret; + + if ((dec->pic_list_init_flag == 0) || + get_free_buf_count(dec) >= + run_ready_min_buf_num) + ret = 1; + if (ret) + not_run_ready[dec->index] = 0; + else + not_run_ready[dec->index]++; + return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0; +} + +static void run(struct vdec_s *vdec, unsigned long mask, + void (*callback)(struct vdec_s *, void *), void *arg) +{ + struct AVS2Decoder_s *dec = + (struct AVS2Decoder_s *)vdec->private; + int r; + + run_count[dec->index]++; + dec->vdec_cb_arg = arg; + dec->vdec_cb = callback; + /* dec->chunk = vdec_prepare_input(vdec); */ + hevc_reset_core(vdec); + + r = vdec_prepare_input(vdec, &dec->chunk); + if (r < 0) { + input_empty[dec->index]++; + + dec->dec_result = DEC_RESULT_AGAIN; + + avs2_print(dec, PRINT_FLAG_VDEC_DETAIL, + "ammvdec_vh265: Insufficient data\n"); + + vdec_schedule_work(&dec->work); + return; + } + input_empty[dec->index] = 0; + dec->dec_result = DEC_RESULT_NONE; + dec->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT); + + if (debug & PRINT_FLAG_VDEC_STATUS) { + int ii; + avs2_print(dec, 0, + "%s (%d): size 0x%x (0x%x 0x%x) sum 0x%x (%x %x %x %x %x) bytes 0x%x", + __func__, + dec->frame_count, r, + dec->chunk ? dec->chunk->size : 0, + dec->chunk ? dec->chunk->offset : 0, + (vdec_frame_based(vdec) && + (debug & PRINT_FLAG_VDEC_STATUS)) ? + get_data_check_sum(dec, r) : 0, + READ_VREG(HEVC_STREAM_START_ADDR), + READ_VREG(HEVC_STREAM_END_ADDR), + READ_VREG(HEVC_STREAM_LEVEL), + READ_VREG(HEVC_STREAM_WR_PTR), + READ_VREG(HEVC_STREAM_RD_PTR), + dec->start_shift_bytes); + if (vdec_frame_based(vdec)) { + u8 *data = ((u8 *)dec->chunk->block->start_virt) + + dec->chunk->offset; + avs2_print_cont(dec, 0, "data adr %p:", + data); + for (ii = 0; ii < 8; ii++) + avs2_print_cont(dec, 0, "%02x ", + data[ii]); + } + avs2_print_cont(dec, 0, "\r\n"); + } + if (vdec->mc_loaded) { + /*firmware have load before, + and not changes to another. + ignore reload. + */ + } else if (amhevc_loadmc_ex(VFORMAT_AVS2, NULL, dec->fw->data) < 0) { + vdec->mc_loaded = 0; + amhevc_disable(); + avs2_print(dec, 0, + "%s: Error amvdec_loadmc fail\n", __func__); + return; + } else + vdec->mc_loaded = 1; + + + if (avs2_hw_ctx_restore(dec) < 0) { + vdec_schedule_work(&dec->work); + return; + } + + vdec_enable_input(vdec); + + WRITE_VREG(HEVC_DEC_STATUS_REG, AVS2_ACTION_DONE); + + if (vdec_frame_based(vdec)) { + if (debug & PRINT_FLAG_VDEC_DATA) + dump_data(dec, dec->chunk->size); + + WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0); + r = dec->chunk->size + + (dec->chunk->offset & (VDEC_FIFO_ALIGN - 1)); + } + + WRITE_VREG(HEVC_DECODE_SIZE, r); + WRITE_VREG(HEVC_DECODE_COUNT, dec->slice_idx); + dec->init_flag = 1; + + avs2_print(dec, PRINT_FLAG_VDEC_DETAIL, + "%s: start hevc (%x %x %x)\n", + __func__, + READ_VREG(HEVC_DEC_STATUS_REG), + READ_VREG(HEVC_MPC_E), + READ_VREG(HEVC_MPSR)); + + start_process_time(dec); + mod_timer(&dec->timer, jiffies); + dec->stat |= STAT_TIMER_ARM; + dec->stat |= STAT_ISR_REG; + amhevc_start(); + dec->stat |= STAT_VDEC_RUN; +} + +static void reset(struct vdec_s *vdec) +{ + + struct AVS2Decoder_s *dec = + (struct AVS2Decoder_s *)vdec->private; + + avs2_print(dec, + PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__); + +} + +static irqreturn_t avs2_irq_cb(struct vdec_s *vdec, int irq) +{ + struct AVS2Decoder_s *dec = + (struct AVS2Decoder_s *)vdec->private; + return vavs2_isr(0, dec); +} + +static irqreturn_t avs2_threaded_irq_cb(struct vdec_s *vdec, int irq) +{ + struct AVS2Decoder_s *dec = + (struct AVS2Decoder_s *)vdec->private; + return vavs2_isr_thread_fn(0, dec); +} + +static void avs2_dump_state(struct vdec_s *vdec) +{ + struct AVS2Decoder_s *dec = + (struct AVS2Decoder_s *)vdec->private; + int i; + avs2_print(dec, 0, "====== %s\n", __func__); + + avs2_print(dec, 0, + "width/height (%d/%d), used_buf_num %d\n", + dec->avs2_dec.img.width, + dec->avs2_dec.img.height, + dec->used_buf_num + ); + + avs2_print(dec, 0, + "is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d\n", + input_frame_based(vdec), + dec->eos, + dec->dec_result, + decode_frame_count[dec->index], + display_frame_count[dec->index], + run_count[dec->index], + not_run_ready[dec->index], + input_empty[dec->index] + ); + + if (vf_get_receiver(vdec->vf_provider_name)) { + enum receviver_start_e state = + vf_notify_receiver(vdec->vf_provider_name, + VFRAME_EVENT_PROVIDER_QUREY_STATE, + NULL); + avs2_print(dec, 0, + "\nreceiver(%s) state %d\n", + vdec->vf_provider_name, + state); + } + + avs2_print(dec, 0, + "%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), free_buf_count %d (min %d for run_ready)\n", + __func__, + kfifo_len(&dec->newframe_q), + VF_POOL_SIZE, + kfifo_len(&dec->display_q), + VF_POOL_SIZE, + dec->vf_pre_count, + dec->vf_get_count, + dec->vf_put_count, + get_free_buf_count(dec), + run_ready_min_buf_num + ); + + dump_pic_list(dec); + + for (i = 0; i < MAX_BUF_NUM; i++) { + avs2_print(dec, 0, + "mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n", + i, + dec->m_mv_BUF[i].start_adr, + dec->m_mv_BUF[i].size, + dec->m_mv_BUF[i].used_flag); + } + + avs2_print(dec, 0, + "HEVC_DEC_STATUS_REG=0x%x\n", + READ_VREG(HEVC_DEC_STATUS_REG)); + avs2_print(dec, 0, + "HEVC_MPC_E=0x%x\n", + READ_VREG(HEVC_MPC_E)); + avs2_print(dec, 0, + "DECODE_MODE=0x%x\n", + READ_VREG(DECODE_MODE)); + avs2_print(dec, 0, + "NAL_SEARCH_CTL=0x%x\n", + READ_VREG(NAL_SEARCH_CTL)); + avs2_print(dec, 0, + "HEVC_PARSER_LCU_START=0x%x\n", + READ_VREG(HEVC_PARSER_LCU_START)); + avs2_print(dec, 0, + "HEVC_DECODE_SIZE=0x%x\n", + READ_VREG(HEVC_DECODE_SIZE)); + avs2_print(dec, 0, + "HEVC_SHIFT_BYTE_COUNT=0x%x\n", + READ_VREG(HEVC_SHIFT_BYTE_COUNT)); + avs2_print(dec, 0, + "HEVC_STREAM_START_ADDR=0x%x\n", + READ_VREG(HEVC_STREAM_START_ADDR)); + avs2_print(dec, 0, + "HEVC_STREAM_END_ADDR=0x%x\n", + READ_VREG(HEVC_STREAM_END_ADDR)); + avs2_print(dec, 0, + "HEVC_STREAM_LEVEL=0x%x\n", + READ_VREG(HEVC_STREAM_LEVEL)); + avs2_print(dec, 0, + "HEVC_STREAM_WR_PTR=0x%x\n", + READ_VREG(HEVC_STREAM_WR_PTR)); + avs2_print(dec, 0, + "HEVC_STREAM_RD_PTR=0x%x\n", + READ_VREG(HEVC_STREAM_RD_PTR)); + avs2_print(dec, 0, + "PARSER_VIDEO_RP=0x%x\n", + READ_PARSER_REG(PARSER_VIDEO_RP)); + avs2_print(dec, 0, + "PARSER_VIDEO_WP=0x%x\n", + READ_PARSER_REG(PARSER_VIDEO_WP)); + + if (input_frame_based(vdec) && + (debug & PRINT_FLAG_VDEC_DATA) + ) { + int jj; + if (dec->chunk && dec->chunk->block && + dec->chunk->size > 0) { + u8 *data = + ((u8 *)dec->chunk->block->start_virt) + + dec->chunk->offset; + avs2_print(dec, 0, + "frame data size 0x%x\n", + dec->chunk->size); + for (jj = 0; jj < dec->chunk->size; jj++) { + if ((jj & 0xf) == 0) + avs2_print(dec, 0, + "%06x:", jj); + avs2_print_cont(dec, 0, + "%02x ", data[jj]); + if (((jj + 1) & 0xf) == 0) + avs2_print_cont(dec, 0, + "\n"); + } + } + } + +} + +static int ammvdec_avs2_probe(struct platform_device *pdev) +{ + struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; + int ret; + int config_val; + struct vframe_content_light_level_s content_light_level; + struct vframe_master_display_colour_s vf_dp; + + struct BUF_s BUF[MAX_BUF_NUM]; + struct AVS2Decoder_s *dec = NULL; + pr_info("%s\n", __func__); + if (pdata == NULL) { + pr_info("\nammvdec_avs2 memory resource undefined.\n"); + return -EFAULT; + } + /*dec = (struct AVS2Decoder_s *)devm_kzalloc(&pdev->dev, + sizeof(struct AVS2Decoder_s), GFP_KERNEL);*/ + memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s)); + dec = vmalloc(sizeof(struct AVS2Decoder_s)); + memset(dec, 0, sizeof(struct AVS2Decoder_s)); + if (dec == NULL) { + pr_info("\nammvdec_avs2 device data allocation failed\n"); + return -ENOMEM; + } + pdata->private = dec; + pdata->dec_status = vavs2_dec_status; + /* pdata->set_trickmode = set_trickmode; */ + pdata->run_ready = run_ready; + pdata->run = run; + pdata->reset = reset; + pdata->irq_handler = avs2_irq_cb; + pdata->threaded_irq_handler = avs2_threaded_irq_cb; + pdata->dump_state = avs2_dump_state; + + + + memcpy(&BUF[0], &dec->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM); + memset(dec, 0, sizeof(struct AVS2Decoder_s)); + memcpy(&dec->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM); + + dec->index = pdev->id; + + if (pdata->use_vfm_path) + snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE, + VFM_DEC_PROVIDER_NAME); + else + snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE, + MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff); + + vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name, + &vavs2_vf_provider, dec); + + dec->provider_name = pdata->vf_provider_name; + platform_set_drvdata(pdev, pdata); + + dec->platform_dev = pdev; + dec->video_signal_type = 0; + if (get_cpu_type() < MESON_CPU_MAJOR_ID_TXLX) + dec->stat |= VP9_TRIGGER_FRAME_ENABLE; +#if 1 + if ((debug & IGNORE_PARAM_FROM_CONFIG) == 0 && + pdata->config && pdata->config_len) { + /*use ptr config for doubel_write_mode, etc*/ + avs2_print(dec, 0, "pdata->config=%s\n", pdata->config); + if (get_config_int(pdata->config, "avs2_double_write_mode", + &config_val) == 0) + dec->double_write_mode = config_val; + else + dec->double_write_mode = double_write_mode; + if (get_config_int(pdata->config, "HDRStaticInfo", + &vf_dp.present_flag) == 0 + && vf_dp.present_flag == 1) { + get_config_int(pdata->config, "mG.x", + &vf_dp.primaries[0][0]); + get_config_int(pdata->config, "mG.y", + &vf_dp.primaries[0][1]); + get_config_int(pdata->config, "mB.x", + &vf_dp.primaries[1][0]); + get_config_int(pdata->config, "mB.y", + &vf_dp.primaries[1][1]); + get_config_int(pdata->config, "mR.x", + &vf_dp.primaries[2][0]); + get_config_int(pdata->config, "mR.y", + &vf_dp.primaries[2][1]); + get_config_int(pdata->config, "mW.x", + &vf_dp.white_point[0]); + get_config_int(pdata->config, "mW.y", + &vf_dp.white_point[1]); + get_config_int(pdata->config, "mMaxDL", + &vf_dp.luminance[0]); + get_config_int(pdata->config, "mMinDL", + &vf_dp.luminance[1]); + vf_dp.content_light_level.present_flag = 1; + get_config_int(pdata->config, "mMaxCLL", + &content_light_level.max_content); + get_config_int(pdata->config, "mMaxFALL", + &content_light_level.max_pic_average); + vf_dp.content_light_level = content_light_level; + dec->video_signal_type = (1 << 29) + | (5 << 26) /* unspecified */ + | (0 << 25) /* limit */ + | (1 << 24) /* color available */ + | (9 << 16) /* 2020 */ + | (16 << 8) /* 2084 */ + | (9 << 0); /* 2020 */ + } + dec->vf_dp = vf_dp; + } else +#endif + { + /*dec->vavs2_amstream_dec_info.width = 0; + dec->vavs2_amstream_dec_info.height = 0; + dec->vavs2_amstream_dec_info.rate = 30;*/ + dec->double_write_mode = double_write_mode; + } + video_signal_type = dec->video_signal_type; + +#if 0 + dec->buf_start = pdata->mem_start; + dec->buf_size = pdata->mem_end - pdata->mem_start + 1; +#else + if (amvdec_avs2_mmu_init(dec) < 0) { + pr_err("avs2 alloc bmmu box failed!!\n"); + /* devm_kfree(&pdev->dev, (void *)dec); */ + vfree((void *)dec); + return -1; + } + dec->cma_alloc_count = PAGE_ALIGN(work_buf_size) / PAGE_SIZE; + ret = decoder_bmmu_box_alloc_buf_phy(dec->bmmu_box, WORK_SPACE_BUF_ID, + dec->cma_alloc_count * PAGE_SIZE, DRIVER_NAME, + &dec->cma_alloc_addr); + if (ret < 0) { + uninit_mmu_buffers(dec); + /* devm_kfree(&pdev->dev, (void *)dec); */ + vfree((void *)dec); + return ret; + } + dec->buf_start = dec->cma_alloc_addr; + dec->buf_size = work_buf_size; +#endif + dec->m_ins_flag = 1; + + dec->init_flag = 0; + dec->fatal_error = 0; + dec->show_frame_num = 0; + if (pdata == NULL) { + pr_info("\namvdec_avs2 memory resource undefined.\n"); + uninit_mmu_buffers(dec); + /* devm_kfree(&pdev->dev, (void *)dec); */ + vfree((void *)dec); + return -EFAULT; + } + + if (debug) { + pr_info("===AVS2 decoder mem resource 0x%lx size 0x%x\n", + dec->buf_start, + dec->buf_size); + } + + if (pdata->sys_info) + dec->vavs2_amstream_dec_info = *pdata->sys_info; + else { + dec->vavs2_amstream_dec_info.width = 0; + dec->vavs2_amstream_dec_info.height = 0; + dec->vavs2_amstream_dec_info.rate = 30; + } + + dec->cma_dev = pdata->cma_dev; + if (vavs2_init(pdata) < 0) { + pr_info("\namvdec_avs2 init failed.\n"); + avs2_local_uninit(dec); + uninit_mmu_buffers(dec); + /* devm_kfree(&pdev->dev, (void *)dec); */ + vfree((void *)dec); + return -ENODEV; + } + vdec_set_prepare_level(pdata, start_decode_buf_level); + hevc_source_changed(VFORMAT_AVS2, + 4096, 2048, 60); + + vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC + | CORE_MASK_COMBINE); + + return 0; +} + +static int ammvdec_avs2_remove(struct platform_device *pdev) +{ + struct AVS2Decoder_s *dec = (struct AVS2Decoder_s *) + (((struct vdec_s *)(platform_get_drvdata(pdev)))->private); + if (debug) + pr_info("amvdec_avs2_remove\n"); + + vmavs2_stop(dec); + + vdec_core_release(hw_to_vdec(dec), CORE_MASK_HEVC); + + vdec_set_status(hw_to_vdec(dec), VDEC_STATUS_DISCONNECTED); + + +#ifdef DEBUG_PTS + pr_info("pts missed %ld, pts hit %ld, duration %d\n", + dec->pts_missed, dec->pts_hit, dec->frame_dur); +#endif + /* devm_kfree(&pdev->dev, (void *)dec); */ + vfree((void *)dec); + return 0; +} + +static struct platform_driver ammvdec_avs2_driver = { + .probe = ammvdec_avs2_probe, + .remove = ammvdec_avs2_remove, +#ifdef CONFIG_PM + .suspend = amvdec_suspend, + .resume = amvdec_resume, +#endif + .driver = { + .name = MULTI_DRIVER_NAME, + } +}; +#endif +static struct mconfig avs2_configs[] = { + MC_PU32("bit_depth_luma", &bit_depth_luma), + MC_PU32("bit_depth_chroma", &bit_depth_chroma), + MC_PU32("frame_width", &frame_width), + MC_PU32("frame_height", &frame_height), + MC_PU32("debug", &debug), + MC_PU32("radr", &radr), + MC_PU32("rval", &rval), + MC_PU32("pop_shorts", &pop_shorts), + MC_PU32("dbg_cmd", &dbg_cmd), + MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index), + MC_PU32("endian", &endian), + MC_PU32("step", &step), + MC_PU32("udebug_flag", &udebug_flag), + MC_PU32("decode_pic_begin", &decode_pic_begin), + MC_PU32("slice_parse_begin", &slice_parse_begin), + MC_PU32("i_only_flag", &i_only_flag), + MC_PU32("error_handle_policy", &error_handle_policy), + MC_PU32("buf_alloc_width", &buf_alloc_width), + MC_PU32("buf_alloc_height", &buf_alloc_height), + MC_PU32("buf_alloc_depth", &buf_alloc_depth), + MC_PU32("buf_alloc_size", &buf_alloc_size), + MC_PU32("buffer_mode", &buffer_mode), + MC_PU32("buffer_mode_dbg", &buffer_mode_dbg), + MC_PU32("max_buf_num", &max_buf_num), + MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin), + MC_PU32("mem_map_mode", &mem_map_mode), + MC_PU32("double_write_mode", &double_write_mode), + MC_PU32("enable_mem_saving", &enable_mem_saving), + MC_PU32("force_w_h", &force_w_h), + MC_PU32("force_fps", &force_fps), + MC_PU32("max_decoding_time", &max_decoding_time), + MC_PU32("on_no_keyframe_skiped", &on_no_keyframe_skiped), + MC_PU32("start_decode_buf_level", &start_decode_buf_level), + MC_PU32("decode_timeout_val", &decode_timeout_val), +}; +static struct mconfig_node avs2_node; + +static int __init amvdec_avs2_driver_init_module(void) +{ + +#ifdef AVS2_10B_MMU + + struct BuffInfo_s *p_buf_info; +#ifdef SUPPORT_4K2K + if (vdec_is_support_4k()) + p_buf_info = &amvavs2_workbuff_spec[1]; + else + p_buf_info = &amvavs2_workbuff_spec[0]; +#else + p_buf_info = &amvavs2_workbuff_spec[0]; +#endif + init_buff_spec(NULL, p_buf_info); + work_buf_size = + (p_buf_info->end_adr - p_buf_info->start_adr + + 0xffff) & (~0xffff); + +#endif + pr_debug("amvdec_avs2 module init\n"); + + error_handle_policy = 0; + +#ifdef ERROR_HANDLE_DEBUG + dbg_nal_skip_flag = 0; + dbg_nal_skip_count = 0; +#endif + udebug_flag = 0; + decode_pic_begin = 0; + slice_parse_begin = 0; + step = 0; + buf_alloc_size = 0; + if (platform_driver_register(&ammvdec_avs2_driver)) + pr_err("failed to register ammvdec_avs2 driver\n"); + + if (platform_driver_register(&amvdec_avs2_driver)) { + pr_err("failed to register amvdec_avs2 driver\n"); + return -ENODEV; + } + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL + /*&& get_cpu_type() != MESON_CPU_MAJOR_ID_GXLX*/) { + if (vdec_is_support_4k()) + amvdec_avs2_profile.profile = + "4k, 10bit, dwrite, compressed"; + else + amvdec_avs2_profile.profile = + "10bit, dwrite, compressed"; + } else { + amvdec_avs2_profile.name = "avs2_unsupport"; + } + + vcodec_profile_register(&amvdec_avs2_profile); + INIT_REG_NODE_CONFIGS("media.decoder", &avs2_node, + "avs2", avs2_configs, CONFIG_FOR_RW); + + return 0; +} + +static void __exit amvdec_avs2_driver_remove_module(void) +{ + pr_debug("amvdec_avs2 module remove.\n"); + platform_driver_unregister(&ammvdec_avs2_driver); + platform_driver_unregister(&amvdec_avs2_driver); +} + +/****************************************/ + +module_param(bit_depth_luma, uint, 0664); +MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_avs2 bit_depth_luma\n"); + +module_param(bit_depth_chroma, uint, 0664); +MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_avs2 bit_depth_chroma\n"); + +module_param(frame_width, uint, 0664); +MODULE_PARM_DESC(frame_width, "\n amvdec_avs2 frame_width\n"); + +module_param(frame_height, uint, 0664); +MODULE_PARM_DESC(frame_height, "\n amvdec_avs2 frame_height\n"); + +module_param(debug, uint, 0664); +MODULE_PARM_DESC(debug, "\n amvdec_avs2 debug\n"); + +module_param(radr, uint, 0664); +MODULE_PARM_DESC(radr, "\nradr\n"); + +module_param(rval, uint, 0664); +MODULE_PARM_DESC(rval, "\nrval\n"); + +module_param(pop_shorts, uint, 0664); +MODULE_PARM_DESC(pop_shorts, "\nrval\n"); + +module_param(dbg_cmd, uint, 0664); +MODULE_PARM_DESC(dbg_cmd, "\ndbg_cmd\n"); + +module_param(dbg_skip_decode_index, uint, 0664); +MODULE_PARM_DESC(dbg_skip_decode_index, "\ndbg_skip_decode_index\n"); + +module_param(endian, uint, 0664); +MODULE_PARM_DESC(endian, "\nrval\n"); + +module_param(step, uint, 0664); +MODULE_PARM_DESC(step, "\n amvdec_avs2 step\n"); + +module_param(decode_pic_begin, uint, 0664); +MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_avs2 decode_pic_begin\n"); + +module_param(slice_parse_begin, uint, 0664); +MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_avs2 slice_parse_begin\n"); + +module_param(i_only_flag, uint, 0664); +MODULE_PARM_DESC(i_only_flag, "\n amvdec_avs2 i_only_flag\n"); + +module_param(error_handle_policy, uint, 0664); +MODULE_PARM_DESC(error_handle_policy, "\n amvdec_avs2 error_handle_policy\n"); + +module_param(buf_alloc_width, uint, 0664); +MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n"); + +module_param(buf_alloc_height, uint, 0664); +MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n"); + +module_param(buf_alloc_depth, uint, 0664); +MODULE_PARM_DESC(buf_alloc_depth, "\n buf_alloc_depth\n"); + +module_param(buf_alloc_size, uint, 0664); +MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n"); + +module_param(buffer_mode, uint, 0664); +MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n"); + +module_param(buffer_mode_dbg, uint, 0664); +MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n"); +/*USE_BUF_BLOCK*/ +module_param(max_buf_num, uint, 0664); +MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n"); + +module_param(dynamic_buf_num_margin, uint, 0664); +MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n"); + +module_param(mv_buf_margin, uint, 0664); +MODULE_PARM_DESC(mv_buf_margin, "\n mv_buf_margin\n"); + +module_param(run_ready_min_buf_num, uint, 0664); +MODULE_PARM_DESC(run_ready_min_buf_num, "\n run_ready_min_buf_num\n"); + +/**/ + +module_param(mem_map_mode, uint, 0664); +MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n"); + +module_param(double_write_mode, uint, 0664); +MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n"); + +module_param(enable_mem_saving, uint, 0664); +MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n"); + +module_param(force_w_h, uint, 0664); +MODULE_PARM_DESC(force_w_h, "\n force_w_h\n"); + +module_param(force_fps, uint, 0664); +MODULE_PARM_DESC(force_fps, "\n force_fps\n"); + +module_param(max_decoding_time, uint, 0664); +MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n"); + +module_param(on_no_keyframe_skiped, uint, 0664); +MODULE_PARM_DESC(on_no_keyframe_skiped, "\n on_no_keyframe_skiped\n"); + + +module_param(start_decode_buf_level, int, 0664); +MODULE_PARM_DESC(start_decode_buf_level, + "\n avs2 start_decode_buf_level\n"); + +module_param(decode_timeout_val, uint, 0664); +MODULE_PARM_DESC(decode_timeout_val, + "\n avs2 decode_timeout_val\n"); + +module_param_array(decode_frame_count, uint, + &max_decode_instance_num, 0664); + +module_param_array(display_frame_count, uint, + &max_decode_instance_num, 0664); + +module_param_array(max_process_time, uint, + &max_decode_instance_num, 0664); + +module_param_array(run_count, uint, + &max_decode_instance_num, 0664); + +module_param_array(input_empty, uint, + &max_decode_instance_num, 0664); + +module_param_array(not_run_ready, uint, + &max_decode_instance_num, 0664); + +module_param(udebug_flag, uint, 0664); +MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n"); + +module_param(udebug_pause_pos, uint, 0664); +MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n"); + +module_param(udebug_pause_val, uint, 0664); +MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n"); + +module_param(udebug_pause_decode_idx, uint, 0664); +MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n"); + +module_param(force_disp_pic_index, int, 0664); +MODULE_PARM_DESC(force_disp_pic_index, + "\n amvdec_h265 force_disp_pic_index\n"); + +module_init(amvdec_avs2_driver_init_module); +module_exit(amvdec_avs2_driver_remove_module); + +MODULE_DESCRIPTION("AMLOGIC avs2 Video Decoder Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Tim Yao "); diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/avs2/vavs2.h b/drivers/amlogic/media_modules/frame_provider/decoder/avs2/vavs2.h new file mode 100644 index 000000000000..6b51f612e10b --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/avs2/vavs2.h @@ -0,0 +1,26 @@ +/* + * drivers/amlogic/amports/vavs2.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * +*/ + +#ifndef VAVS2_H +#define VAVS2_H + +#define AVS2_10B_MMU +#define MV_USE_FIXED_BUF + +void adapt_coef_probs(int pic_count, int prev_kf, int cur_kf, int pre_fc, +unsigned int *prev_prob, unsigned int *cur_prob, unsigned int *count); +#endif diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/h264/Makefile b/drivers/amlogic/media_modules/frame_provider/decoder/h264/Makefile new file mode 100644 index 000000000000..b7c85ee130d7 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/h264/Makefile @@ -0,0 +1,6 @@ +obj-$(CONFIG_AMLOGIC_MEDIA_VDEC_H264) += amvdec_h264.o +amvdec_h264-objs += vh264.o + +obj-$(CONFIG_AMLOGIC_MEDIA_VDEC_H264_MVC) += amvdec_h264mvc.o +amvdec_h264mvc-objs += vh264_mvc.o + diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/h264/vh264.c b/drivers/amlogic/media_modules/frame_provider/decoder/h264/vh264.c new file mode 100644 index 000000000000..40c7bbdc8dd2 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/h264/vh264.c @@ -0,0 +1,3216 @@ +/* + * drivers/amlogic/media/frame_provider/decoder/h264/vh264.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#define DEBUG +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../../stream_input/amports/amports_priv.h" +#include + +#include "../utils/vdec.h" +#include +#include "../utils/amvdec.h" +#include "vh264.h" +#include "../../../stream_input/parser/streambuf.h" +#include +#include +#include +#include +#include "../utils/decoder_mmu_box.h" +#include "../utils/decoder_bmmu_box.h" +#include +#include +#include "../utils/firmware.h" +#include + +#define DRIVER_NAME "amvdec_h264" +#define MODULE_NAME "amvdec_h264" +#define MEM_NAME "codec_264" +#define HANDLE_H264_IRQ + +#if 0 +/* currently, only iptv supports this function*/ +#define SUPPORT_BAD_MACRO_BLOCK_REDUNDANCY +#endif + +/* #define DEBUG_PTS */ +#if 0 /* MESON_CPU_TYPE <= MESON_CPU_TYPE_MESON6TV */ +#define DROP_B_FRAME_FOR_1080P_50_60FPS +#endif +#define RATE_MEASURE_NUM 8 +#define RATE_CORRECTION_THRESHOLD 5 +#define RATE_24_FPS 4004 /* 23.97 */ +#define RATE_25_FPS 3840 /* 25 */ +#define DUR2PTS(x) ((x)*90/96) +#define PTS2DUR(x) ((x)*96/90) +#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96) +#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2 +#define VDEC_CLOCK_ADJUST_FRAME 50 + +static inline bool close_to(int a, int b, int m) +{ + return (abs(a - b) < m) ? true : false; +} + +static DEFINE_MUTEX(vh264_mutex); +#define DEF_BUF_START_ADDR 0x1000000 +#define V_BUF_ADDR_OFFSET_NEW (0x1ee000) +#define V_BUF_ADDR_OFFSET (0x13e000) + +#define PIC_SINGLE_FRAME 0 +#define PIC_TOP_BOT_TOP 1 +#define PIC_BOT_TOP_BOT 2 +#define PIC_DOUBLE_FRAME 3 +#define PIC_TRIPLE_FRAME 4 +#define PIC_TOP_BOT 5 +#define PIC_BOT_TOP 6 +#define PIC_INVALID 7 + +#define EXTEND_SAR 0xff + +#define VF_POOL_SIZE 64 +#define VF_BUF_NUM 24 +#define WORKSPACE_BUF_NUM 2 +#define PUT_INTERVAL (HZ/100) +#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL) + +#define SWITCHING_STATE_OFF 0 +#define SWITCHING_STATE_ON_CMD3 1 +#define SWITCHING_STATE_ON_CMD1 2 +#define SWITCHING_STATE_ON_CMD1_PENDING 3 + + +#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001 +#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002 +#define DEC_CONTROL_FLAG_DISABLE_FAST_POC 0x0004 + +#define INCPTR(p) ptr_atomic_wrap_inc(&p) + +#define SLICE_TYPE_I 2 +#define SLICE_TYPE_P 5 +#define SLICE_TYPE_B 6 + +struct buffer_spec_s { + unsigned int y_addr; + unsigned int u_addr; + unsigned int v_addr; + + int y_canvas_index; + int u_canvas_index; + int v_canvas_index; + + unsigned int y_canvas_width; + unsigned int u_canvas_width; + unsigned int v_canvas_width; + + unsigned int y_canvas_height; + unsigned int u_canvas_height; + unsigned int v_canvas_height; + + unsigned long phy_addr; + int alloc_count; +}; + +#define spec2canvas(x) \ + (((x)->v_canvas_index << 16) | \ + ((x)->u_canvas_index << 8) | \ + ((x)->y_canvas_index << 0)) + +static struct vframe_s *vh264_vf_peek(void *); +static struct vframe_s *vh264_vf_get(void *); +static void vh264_vf_put(struct vframe_s *, void *); +static int vh264_vf_states(struct vframe_states *states, void *); +static int vh264_event_cb(int type, void *data, void *private_data); + +static void vh264_prot_init(void); +static int vh264_local_init(void); +static void vh264_put_timer_func(unsigned long arg); +static void stream_switching_done(void); + +static const char vh264_dec_id[] = "vh264-dev"; + +#define PROVIDER_NAME "decoder.h264" + +static const struct vframe_operations_s vh264_vf_provider_ops = { + .peek = vh264_vf_peek, + .get = vh264_vf_get, + .put = vh264_vf_put, + .event_cb = vh264_event_cb, + .vf_states = vh264_vf_states, +}; + +static struct vframe_provider_s vh264_vf_prov; +/*TODO irq*/ +#if 1 +static u32 frame_width, frame_height, frame_dur, frame_prog, frame_packing_type, + last_duration; +static u32 saved_resolution; +static u32 last_mb_width, last_mb_height; +#else +static u32 frame_buffer_size; +static u32 frame_width, frame_height, frame_dur, frame_prog, last_duration; +static u32 last_mb_width, last_mb_height; +static u32 frame_packing_type; +#endif +static DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE); +static DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE); +static DECLARE_KFIFO(recycle_q, struct vframe_s *, VF_POOL_SIZE); +static DECLARE_KFIFO(delay_display_q, struct vframe_s *, VF_POOL_SIZE); + +static struct vframe_s vfpool[VF_POOL_SIZE]; +static s32 vfbuf_use[VF_BUF_NUM]; +static struct buffer_spec_s buffer_spec[VF_BUF_NUM]; +static struct buffer_spec_s fense_buffer_spec[2]; +/* disp buf + keep buf+ fense buf + workspace */ + +#define MAX_BLK_BUFFERS (VF_BUF_NUM + 2 + WORKSPACE_BUF_NUM) +#define VF_BUFFER_IDX(n) (WORKSPACE_BUF_NUM + n) +#define FENSE_BUFFER_IDX(n) (WORKSPACE_BUF_NUM + VF_BUF_NUM + n) + +#define USER_DATA_RUND_SIZE (USER_DATA_SIZE + 4096) +static struct vframe_s fense_vf[2]; + +static struct timer_list recycle_timer; +static u32 stat; +static s32 buf_offset; +static u32 pts_outside; +static u32 sync_outside; +static u32 dec_control; +static u32 vh264_ratio; +static u32 vh264_rotation; +static u32 use_idr_framerate; +static u32 high_bandwidth; + +static u32 seq_info; +static u32 timing_info_present_flag; +static u32 fixed_frame_rate_flag; +static u32 fixed_frame_rate_check_count; +static u32 aspect_ratio_info; +static u32 num_units_in_tick; +static u32 time_scale; +static u32 h264_ar; +static u32 decoder_debug_flag; +static u32 dpb_size_adj = 6; +static u32 fr_hint_status; + +#ifdef DROP_B_FRAME_FOR_1080P_50_60FPS +static u32 last_interlaced; +#endif +static bool is_4k; +static unsigned char h264_first_pts_ready; +static bool h264_first_valid_pts_ready; +static u32 h264pts1, h264pts2; +static u32 h264_pts_count, duration_from_pts_done, duration_on_correcting; +static u32 vh264_error_count; +static u32 vh264_no_disp_count; +static u32 fatal_error_flag; +static u32 fatal_error_reset; +static u32 max_refer_buf = 1; +static u32 decoder_force_reset; +static unsigned int no_idr_error_count; +static unsigned int no_idr_error_max = 60; +#ifdef SUPPORT_BAD_MACRO_BLOCK_REDUNDANCY +/* 0~128*/ +static u32 bad_block_scale; +#endif + +static unsigned int enable_switch_fense = 1; +#define EN_SWITCH_FENCE() (enable_switch_fense && !is_4k) +#if 0 +static u32 vh264_no_disp_wd_count; +#endif +static u32 vh264_running; +static s32 vh264_stream_switching_state; +static s32 vh264_eos; +static struct vframe_s *p_last_vf; +static s32 iponly_early_mode; +static void *mm_blk_handle; +static int tvp_flag; +static bool is_reset; + +/*TODO irq*/ +#if 1 +static u32 last_pts, last_pts_remainder; +#else +static u32 last_pts; +#endif +static bool check_pts_discontinue; +static u32 wait_buffer_counter; +static u32 video_signal_from_vui; + +static uint error_recovery_mode; +static uint error_recovery_mode_in = 3; +static uint error_recovery_mode_use = 3; + +static uint mb_total = 0, mb_width = 0, mb_height; +static uint saved_idc_level; +#define UCODE_IP_ONLY 2 +#define UCODE_IP_ONLY_PARAM 1 +static uint ucode_type; + +#ifdef DEBUG_PTS +static unsigned long pts_missed, pts_hit; +#endif +static uint debugfirmware; + +static atomic_t vh264_active = ATOMIC_INIT(0); +static int vh264_reset; +static struct work_struct error_wd_work; +static struct work_struct stream_switching_work; +static struct work_struct set_parameter_work; +static struct work_struct notify_work; +static struct work_struct set_clk_work; +static struct work_struct userdata_push_work; + + + +static struct dec_sysinfo vh264_amstream_dec_info; +static dma_addr_t mc_dma_handle; +static void *mc_cpu_addr; +static u32 first_offset; +static u32 first_pts; +static u64 first_pts64; +static bool first_pts_cached; +static void *sei_data_buffer; +static dma_addr_t sei_data_buffer_phys; +static int clk_adj_frame_count; + +#define MC_OFFSET_HEADER 0x0000 +#define MC_OFFSET_DATA 0x1000 +#define MC_OFFSET_MMCO 0x2000 +#define MC_OFFSET_LIST 0x3000 +#define MC_OFFSET_SLICE 0x4000 + +#define MC_TOTAL_SIZE (20*SZ_1K) +#define MC_SWAP_SIZE (4*SZ_1K) + +#define MODE_ERROR 0 +#define MODE_FULL 1 + +static DEFINE_SPINLOCK(lock); +static DEFINE_SPINLOCK(prepare_lock); +static DEFINE_SPINLOCK(recycle_lock); + +static bool block_display_q; +static int vh264_stop(int mode); +static s32 vh264_init(void); + +#define DFS_HIGH_THEASHOLD 3 + +static bool pts_discontinue; + +static struct ge2d_context_s *ge2d_videoh264_context; + +static struct vdec_info *gvs; + +static int ge2d_videoh264task_init(void) +{ + if (ge2d_videoh264_context == NULL) + ge2d_videoh264_context = create_ge2d_work_queue(); + + if (ge2d_videoh264_context == NULL) { + pr_info("create_ge2d_work_queue video task failed\n"); + return -1; + } + return 0; +} + +static int ge2d_videoh264task_release(void) +{ + if (ge2d_videoh264_context) { + destroy_ge2d_work_queue(ge2d_videoh264_context); + ge2d_videoh264_context = NULL; + } + return 0; +} + +static int ge2d_canvas_dup(struct canvas_s *srcy, struct canvas_s *srcu, + struct canvas_s *des, int format, u32 srcindex, + u32 desindex) +{ + + struct config_para_ex_s ge2d_config; + /* pr_info("[%s]h264 ADDR srcy[0x%lx] srcu[0x%lx] des[0x%lx]\n", + * __func__, srcy->addr, srcu->addr, des->addr); + */ + memset(&ge2d_config, 0, sizeof(struct config_para_ex_s)); + + ge2d_config.alu_const_color = 0; + ge2d_config.bitmask_en = 0; + ge2d_config.src1_gb_alpha = 0; + + ge2d_config.src_planes[0].addr = srcy->addr; + ge2d_config.src_planes[0].w = srcy->width; + ge2d_config.src_planes[0].h = srcy->height; + + ge2d_config.src_planes[1].addr = srcu->addr; + ge2d_config.src_planes[1].w = srcu->width; + ge2d_config.src_planes[1].h = srcu->height; + + ge2d_config.dst_planes[0].addr = des->addr; + ge2d_config.dst_planes[0].w = des->width; + ge2d_config.dst_planes[0].h = des->height; + + ge2d_config.src_para.canvas_index = srcindex; + ge2d_config.src_para.mem_type = CANVAS_TYPE_INVALID; + ge2d_config.src_para.format = format; + ge2d_config.src_para.fill_color_en = 0; + ge2d_config.src_para.fill_mode = 0; + ge2d_config.src_para.color = 0; + ge2d_config.src_para.top = 0; + ge2d_config.src_para.left = 0; + ge2d_config.src_para.width = srcy->width; + ge2d_config.src_para.height = srcy->height; + + ge2d_config.dst_para.canvas_index = desindex; + ge2d_config.dst_para.mem_type = CANVAS_TYPE_INVALID; + ge2d_config.dst_para.format = format; + ge2d_config.dst_para.fill_color_en = 0; + ge2d_config.dst_para.fill_mode = 0; + ge2d_config.dst_para.color = 0; + ge2d_config.dst_para.top = 0; + ge2d_config.dst_para.left = 0; + ge2d_config.dst_para.width = srcy->width; + ge2d_config.dst_para.height = srcy->height; + + if (ge2d_context_config_ex(ge2d_videoh264_context, &ge2d_config) < 0) { + pr_info("ge2d_context_config_ex failed\n"); + return -1; + } + + stretchblt_noalpha(ge2d_videoh264_context, 0, 0, srcy->width, + srcy->height, 0, 0, srcy->width, srcy->height); + + return 0; +} + +static inline int fifo_level(void) +{ + return VF_POOL_SIZE - kfifo_len(&newframe_q); +} + + +void spec_set_canvas(struct buffer_spec_s *spec, + unsigned int width, unsigned int height) +{ + canvas_config(spec->y_canvas_index, + spec->y_addr, + width, height, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); + + canvas_config(spec->u_canvas_index, + spec->u_addr, + width, height / 2, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); + return; +} + +static void vh264_notify_work(struct work_struct *work) +{ + pr_info("frame duration changed %d\n", frame_dur); + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_FR_HINT, + (void *)((unsigned long)frame_dur)); + + return; +} + +static void prepare_display_q(void) +{ + unsigned long flags; + int count; + + spin_lock_irqsave(&prepare_lock, flags); + + if (block_display_q) { + spin_unlock_irqrestore(&prepare_lock, flags); + return; + } + + spin_unlock_irqrestore(&prepare_lock, flags); + + count = (int)VF_POOL_SIZE - + kfifo_len(&delay_display_q) - + kfifo_len(&display_q) - + kfifo_len(&recycle_q) - + kfifo_len(&newframe_q); + + if ((vh264_stream_switching_state != SWITCHING_STATE_OFF) + || !EN_SWITCH_FENCE()) + count = 0; + else + count = (count < 2) ? 0 : 2; + + while (kfifo_len(&delay_display_q) > count) { + struct vframe_s *vf; + + if (kfifo_get(&delay_display_q, &vf)) { + kfifo_put(&display_q, + (const struct vframe_s *)vf); + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL); + } + } +} + +static struct vframe_s *vh264_vf_peek(void *op_arg) +{ + struct vframe_s *vf; + + if (kfifo_peek(&display_q, &vf)) + return vf; + + return NULL; +} + +static struct vframe_s *vh264_vf_get(void *op_arg) +{ + struct vframe_s *vf; + + if (kfifo_get(&display_q, &vf)) + return vf; + + return NULL; +} + +static void vh264_vf_put(struct vframe_s *vf, void *op_arg) +{ + unsigned long flags; + + spin_lock_irqsave(&recycle_lock, flags); + + if ((vf != &fense_vf[0]) && (vf != &fense_vf[1])) + kfifo_put(&recycle_q, (const struct vframe_s *)vf); + + spin_unlock_irqrestore(&recycle_lock, flags); +} + +static int vh264_event_cb(int type, void *data, void *private_data) +{ + if (type & VFRAME_EVENT_RECEIVER_RESET) { + unsigned long flags; + + amvdec_stop(); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_light_unreg_provider(&vh264_vf_prov); +#endif + spin_lock_irqsave(&lock, flags); + vh264_local_init(); + vh264_prot_init(); + spin_unlock_irqrestore(&lock, flags); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_reg_provider(&vh264_vf_prov); +#endif + amvdec_start(); + } + return 0; +} + +static int vh264_vf_states(struct vframe_states *states, void *op_arg) +{ + unsigned long flags; + + spin_lock_irqsave(&lock, flags); + + states->vf_pool_size = VF_POOL_SIZE; + states->buf_free_num = kfifo_len(&newframe_q); + states->buf_avail_num = kfifo_len(&display_q) + + kfifo_len(&delay_display_q); + states->buf_recycle_num = kfifo_len(&recycle_q); + + spin_unlock_irqrestore(&lock, flags); + + return 0; +} + +#if 0 +static tvin_trans_fmt_t convert_3d_format(u32 type) +{ + const tvin_trans_fmt_t conv_tab[] = { + 0, /* checkerboard */ + 0, /* column alternation */ + TVIN_TFMT_3D_LA, /* row alternation */ + TVIN_TFMT_3D_LRH_OLER, /* side by side */ + TVIN_TFMT_3D_FA /* top bottom */ + }; + + return (type <= 4) ? conv_tab[type] : 0; +} +#endif + + +#ifdef DEBUG_CC_USER_DATA +static int vbi_to_ascii(int c) +{ + if (c < 0) + return '?'; + + c &= 0x7F; + + if (c < 0x20 || c >= 0x7F) + return '.'; + + return c; +} + +static void dump_cc_ascii(const uint8_t *buf, int poc) +{ + int cc_flag; + int cc_count; + int i; + int szAscii[32]; + int index = 0; + + cc_flag = buf[1] & 0x40; + if (!cc_flag) { + pr_info("### cc_flag is invalid\n"); + return; + } + cc_count = buf[1] & 0x1f; + + for (i = 0; i < cc_count; ++i) { + unsigned int b0; + unsigned int cc_valid; + unsigned int cc_type; + unsigned char cc_data1; + unsigned char cc_data2; + + b0 = buf[3 + i * 3]; + cc_valid = b0 & 4; + cc_type = b0 & 3; + cc_data1 = buf[4 + i * 3]; + cc_data2 = buf[5 + i * 3]; + + + if (cc_type == 0) { + /* NTSC pair, Line 21 */ + szAscii[index++] = vbi_to_ascii(cc_data1); + szAscii[index++] = vbi_to_ascii(cc_data2); + if ((!cc_valid) || (i >= 3)) + break; + } + } + switch (index) { + case 8: + pr_info("push poc:%d : %c %c %c %c %c %c %c %c\n", + poc, + szAscii[0], szAscii[1], szAscii[2], szAscii[3], + szAscii[4], szAscii[5], szAscii[6], szAscii[7]); + break; + case 7: + pr_info("push poc:%d : %c %c %c %c %c %c %c\n", + poc, + szAscii[0], szAscii[1], szAscii[2], szAscii[3], + szAscii[4], szAscii[5], szAscii[6]); + break; + case 6: + pr_info("push poc:%d : %c %c %c %c %c %c\n", poc, + szAscii[0], szAscii[1], szAscii[2], szAscii[3], + szAscii[4], szAscii[5]); + break; + case 5: + pr_info("push poc:%d : %c %c %c %c %c\n", poc, + szAscii[0], szAscii[1], szAscii[2], szAscii[3], + szAscii[4]); + break; + case 4: + pr_info("push poc:%d : %c %c %c %c\n", poc, + szAscii[0], szAscii[1], szAscii[2], szAscii[3]); + break; + case 3: + pr_info("push poc:%d : %c %c %c\n", poc, + szAscii[0], szAscii[1], szAscii[2]); + break; + case 2: + pr_info("push poc:%d : %c %c\n", poc, + szAscii[0], szAscii[1]); + break; + case 1: + pr_info("push poc:%d : %c\n", poc, szAscii[0]); + break; + default: + pr_info("push poc:%d and no CC data: index = %d\n", + poc, index); + break; + } +} + +/* +#define DUMP_USER_DATA_HEX +*/ + +#ifdef DUMP_USER_DATA_HEX +static void print_data(unsigned char *pdata, int len) +{ + int nLeft; + + nLeft = len; + + while (nLeft >= 8) { + pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n", + pdata[0], pdata[1], pdata[2], pdata[3], + pdata[4], pdata[5], pdata[6], pdata[7]); + nLeft -= 8; + pdata += 8; + } +} +#endif + +static void aml_swap_data(uint8_t *user_data, int ud_size) +{ + int swap_blocks, i, j, k, m; + unsigned char c_temp; + + /* swap byte order */ + swap_blocks = ud_size / 8; + for (i = 0; i < swap_blocks; i++) { + j = i * 8; + k = j + 7; + for (m = 0; m < 4; m++) { + c_temp = user_data[j]; + user_data[j++] = user_data[k]; + user_data[k--] = c_temp; + } + } +} + +static void dump_data(unsigned int user_data_wp, + unsigned int user_data_length, + int poc) +{ + unsigned char *pdata; + int user_data_len; + int wp_start; + int nLeft; + unsigned char szBuf[256]; + int nOffset; + + dma_sync_single_for_cpu(amports_get_dma_device(), + sei_data_buffer_phys, USER_DATA_SIZE, + DMA_FROM_DEVICE); + + if (user_data_length & 0x07) + user_data_len = (user_data_length + 8) & 0xFFFFFFF8; + else + user_data_len = user_data_length; + + if (user_data_wp >= user_data_len) { + wp_start = user_data_wp - user_data_len; + + pdata = (unsigned char *)sei_data_buffer; + pdata += wp_start; + nLeft = user_data_len; + + memset(szBuf, 0, 256); + memcpy(szBuf, pdata, user_data_len); + } else { + wp_start = user_data_wp + + USER_DATA_SIZE - user_data_len; + + pdata = (unsigned char *)sei_data_buffer; + pdata += wp_start; + nLeft = USER_DATA_SIZE - wp_start; + + memset(szBuf, 0, 256); + memcpy(szBuf, pdata, nLeft); + nOffset = nLeft; + + pdata = (unsigned char *)sei_data_buffer; + nLeft = user_data_wp; + memcpy(szBuf+nOffset, pdata, nLeft); + } + + aml_swap_data(szBuf, user_data_len); +#ifdef DUMP_USER_DATA_HEX + print_data(szBuf, user_data_len); +#endif + dump_cc_ascii(szBuf+7, poc); +} +#endif + + +static void userdata_push_do_work(struct work_struct *work) +{ + unsigned int sei_itu35_flags; + unsigned int sei_itu35_wp; + unsigned int sei_itu35_data_length; + struct userdata_poc_info_t user_data_poc; + + sei_itu35_flags = READ_VREG(AV_SCRATCH_J); + sei_itu35_wp = (sei_itu35_flags >> 16) & 0xffff; + sei_itu35_data_length = sei_itu35_flags & 0x7fff; + +#if 0 + pr_info("pocinfo 0x%x, top poc %d, wp 0x%x, length %d\n", + READ_VREG(AV_SCRATCH_L), + READ_VREG(AV_SCRATCH_M), + sei_itu35_wp, sei_itu35_data_length); +#endif + user_data_poc.poc_info = READ_VREG(AV_SCRATCH_L); + user_data_poc.poc_number = READ_VREG(AV_SCRATCH_M); +#ifdef DEBUG_CC_USER_DATA + dump_data(sei_itu35_wp, sei_itu35_data_length, + user_data_poc.poc_number); +#endif + WRITE_VREG(AV_SCRATCH_J, 0); + wakeup_userdata_poll(user_data_poc, sei_itu35_wp, + (unsigned long)sei_data_buffer, + USER_DATA_SIZE, sei_itu35_data_length); +} + + +static void set_frame_info(struct vframe_s *vf) +{ + vf->width = frame_width; + vf->height = frame_height; + vf->duration = frame_dur; + vf->ratio_control = + (min(h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) << + DISP_RATIO_ASPECT_RATIO_BIT; + vf->orientation = vh264_rotation; + vf->flag = 0; + +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER_3D_PROCESS + vf->trans_fmt = 0; + if ((vf->trans_fmt == TVIN_TFMT_3D_LRF) || + (vf->trans_fmt == TVIN_TFMT_3D_LA)) { + vf->left_eye.start_x = 0; + vf->left_eye.start_y = 0; + vf->left_eye.width = frame_width / 2; + vf->left_eye.height = frame_height; + + vf->right_eye.start_x = 0; + vf->right_eye.start_y = 0; + vf->right_eye.width = frame_width / 2; + vf->right_eye.height = frame_height; + } else if ((vf->trans_fmt == TVIN_TFMT_3D_LRH_OLER) || + (vf->trans_fmt == TVIN_TFMT_3D_TB)) { + vf->left_eye.start_x = 0; + vf->left_eye.start_y = 0; + vf->left_eye.width = frame_width / 2; + vf->left_eye.height = frame_height; + + vf->right_eye.start_x = 0; + vf->right_eye.start_y = 0; + vf->right_eye.width = frame_width / 2; + vf->right_eye.height = frame_height; + } +#endif + +} + +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER +static void vh264_ppmgr_reset(void) +{ + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_RESET, NULL); + + vh264_local_init(); + + pr_info("vh264dec: vf_ppmgr_reset\n"); +} +#endif + +static int get_max_dpb_size(int level_idc, int mb_width, int mb_height) +{ + int size, r; + + switch (level_idc) { + case 10: + r = 1485; + break; + case 11: + r = 3375; + break; + case 12: + case 13: + case 20: + r = 8910; + break; + case 21: + r = 17820; + break; + case 22: + case 30: + r = 30375; + break; + case 31: + r = 67500; + break; + case 32: + r = 76800; + break; + case 40: + case 41: + case 42: + r = 122880; + break; + case 50: + r = 414000; + break; + case 51: + case 52: + r = 691200; + break; + default: + return 0; + } + size = (mb_width * mb_height + + (mb_width * mb_height / 2)) * 256 * 10; + r = (r * 1024 + size-1) / size; + r = min(r, 16); + /*pr_info("max_dpb %d size:%d\n", r, size);*/ + return r; +} +static void vh264_set_params(struct work_struct *work) +{ + int aspect_ratio_info_present_flag, aspect_ratio_idc; + int max_dpb_size, actual_dpb_size, max_reference_size; + int i, mb_mv_byte, ret; + unsigned long addr; + unsigned int post_canvas, buf_size; + unsigned int frame_mbs_only_flag; + unsigned int chroma_format_idc, chroma444, video_signal; + unsigned int crop_infor, crop_bottom, crop_right, level_idc; + if (!atomic_read(&vh264_active)) + return; + mutex_lock(&vh264_mutex); + if (vh264_stream_switching_state == SWITCHING_STATE_ON_CMD1) + vh264_stream_switching_state = SWITCHING_STATE_ON_CMD1_PENDING; + post_canvas = get_post_canvas(); + clk_adj_frame_count = 0; + /* set to max decoder clock rate at the beginning */ + vdec_source_changed(VFORMAT_H264, 3840, 2160, 60); + timing_info_present_flag = 0; + mb_width = READ_VREG(AV_SCRATCH_1); + seq_info = READ_VREG(AV_SCRATCH_2); + aspect_ratio_info = READ_VREG(AV_SCRATCH_3); + num_units_in_tick = READ_VREG(AV_SCRATCH_4); + time_scale = READ_VREG(AV_SCRATCH_5); + level_idc = READ_VREG(AV_SCRATCH_A); + if (level_idc > 0) + saved_idc_level = level_idc; + else if (saved_idc_level > 0) + level_idc = saved_idc_level; + video_signal = READ_VREG(AV_SCRATCH_H); + video_signal_from_vui = + ((video_signal & 0xffff) << 8) | + ((video_signal & 0xff0000) >> 16) | + ((video_signal & 0x3f000000)); +/* + * pr_info("video_signal_type_present_flag 0x%x\n", + * (video_signal_from_vui >> 29) & 1); + * pr_info("video_format 0x%x\n", + * (video_signal_from_vui >> 26) & 7); + * pr_info("video_full_range_flag 0x%x\n", + * (video_signal_from_vui >> 25) & 1); + * pr_info("color_description_present_flag 0x%x\n", + * (video_signal_from_vui >> 24) & 1); + * pr_info("color_primaries 0x%x\n", + * (video_signal_from_vui >> 16) & 0xff); + * pr_info("transfer_characteristic 0x%x\n", + * (video_signal_from_vui >> 8) & 0xff); + * pr_info("matrix_coefficient 0x%x\n", + * video_signal_from_vui & 0xff); + */ + + mb_total = (mb_width >> 8) & 0xffff; + max_reference_size = (mb_width >> 24) & 0x7f; + mb_mv_byte = (mb_width & 0x80000000) ? 24 : 96; + if (ucode_type == UCODE_IP_ONLY_PARAM) + mb_mv_byte = 96; + mb_width = mb_width & 0xff; + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { + if (!mb_width && mb_total) + mb_width = 256; + } + mb_height = mb_total / mb_width; + last_duration = 0; + /* AV_SCRATCH_2 + * bit 15: frame_mbs_only_flag + * bit 13-14: chroma_format_idc + */ + frame_mbs_only_flag = (seq_info >> 15) & 0x01; + chroma_format_idc = (seq_info >> 13) & 0x03; + chroma444 = (chroma_format_idc == 3) ? 1 : 0; + + /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1 + * @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) << + * (2 - frame_mbs_only_flag) + */ + crop_infor = READ_VREG(AV_SCRATCH_6); + crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag); + crop_right = ((crop_infor >> 16) & 0xff) >> (2 - frame_mbs_only_flag); + + /* if width or height from outside is not equal to mb, then use mb */ + /* add: for seeking stream with other resolution */ + if ((last_mb_width && (last_mb_width != mb_width)) + || (mb_width != ((frame_width + 15) >> 4))) + frame_width = 0; + if ((last_mb_height && (last_mb_height != mb_height)) + || (mb_height != ((frame_height + 15) >> 4))) + frame_height = 0; + last_mb_width = mb_width; + last_mb_height = mb_height; + + if ((frame_width == 0) || (frame_height == 0) || crop_infor) { + frame_width = mb_width << 4; + frame_height = mb_height << 4; + if (frame_mbs_only_flag) { + frame_height = + frame_height - (2 >> chroma444) * + min(crop_bottom, + (unsigned int)((8 << chroma444) - 1)); + frame_width = + frame_width - (2 >> chroma444) * min(crop_right, + (unsigned + int)((8 << chroma444) - 1)); + } else { + frame_height = + frame_height - (4 >> chroma444) * + min(crop_bottom, + (unsigned int)((8 << chroma444) + - 1)); + frame_width = + frame_width - (4 >> chroma444) * min(crop_right, + (unsigned + int)((8 << + chroma444) + - 1)); + } +#if 0 + pr_info + ("frame_mbs_only_flag %d, crop_bottom %d, frame_height %d, ", + frame_mbs_only_flag, crop_bottom, frame_height); + pr_info + ("mb_height %d,crop_right %d, frame_width %d, mb_width %d\n", + mb_height, crop_right, frame_width, mb_width); +#endif + if (frame_height == 1088) + frame_height = 1080; + } + + mb_width = (mb_width + 3) & 0xfffffffc; + mb_height = (mb_height + 3) & 0xfffffffc; + mb_total = mb_width * mb_height; + + /*max_reference_size <= max_dpb_size <= actual_dpb_size*/ + is_4k = (mb_total > 8160) ? true:false; + + + max_dpb_size = get_max_dpb_size(level_idc, mb_width, mb_height); + if (max_dpb_size < max_reference_size) + max_dpb_size = max_reference_size; + if (max_dpb_size > 15 + && get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB + && (codec_mm_get_total_size() < 80 * SZ_1M)) { + actual_dpb_size + = max_reference_size + dpb_size_adj; + if (actual_dpb_size > VF_BUF_NUM) + actual_dpb_size = VF_BUF_NUM; + } else { + actual_dpb_size = max_dpb_size + dpb_size_adj; + actual_dpb_size = min(actual_dpb_size, VF_BUF_NUM); + } + max_reference_size++; + pr_info("actual_dpb_size %d max_dpb_size %d max_ref %d\n", + actual_dpb_size, max_dpb_size, + max_reference_size); + buf_size = mb_total * mb_mv_byte * max_reference_size; + + ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, 1, + buf_size, DRIVER_NAME, &addr); + + if (ret < 0) { + fatal_error_flag = + DECODER_FATAL_ERROR_NO_MEM; + vh264_running = 0; + mutex_unlock(&vh264_mutex); + return; + } + + WRITE_VREG(AV_SCRATCH_1, addr); + WRITE_VREG(AV_SCRATCH_3, post_canvas); + WRITE_VREG(AV_SCRATCH_4, addr + buf_size); + + if (!(READ_VREG(AV_SCRATCH_F) & 0x1)) { + for (i = 0; i < actual_dpb_size; i++) { +#ifdef DOUBLE_WRITE + int page_count = + PAGE_ALIGN((mb_total << 8) + (mb_total + << 7) + (mb_total << 6) + + (mb_total << 5)) / PAGE_SIZE; +#else + int page_count = + PAGE_ALIGN((mb_total << 8) + + (mb_total << 7)) / PAGE_SIZE; +#endif + + ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, + VF_BUFFER_IDX(i), + page_count << PAGE_SHIFT, + DRIVER_NAME, &buffer_spec[i].phy_addr); + + if (ret < 0) { + buffer_spec[i].alloc_count = 0; + fatal_error_flag = + DECODER_FATAL_ERROR_NO_MEM; + vh264_running = 0; + mutex_unlock(&vh264_mutex); + return; + } + + addr = buffer_spec[i].phy_addr; + buffer_spec[i].alloc_count = page_count; + + if (i <= 21) { + buffer_spec[i].y_addr = addr; + addr += mb_total << 8; + buffer_spec[i].u_addr = addr; + buffer_spec[i].v_addr = addr; + addr += mb_total << 7; + vfbuf_use[i] = 0; + + buffer_spec[i].y_canvas_index = 128 + i * 2; + buffer_spec[i].u_canvas_index = 128 + i * 2 + 1; + buffer_spec[i].v_canvas_index = 128 + i * 2 + 1; + + buffer_spec[i].y_canvas_width = mb_width << 4; + buffer_spec[i].y_canvas_height = mb_height << 4; + buffer_spec[i].u_canvas_width = mb_width << 4; + buffer_spec[i].u_canvas_height = mb_height << 4; + buffer_spec[i].v_canvas_width = mb_width << 4; + buffer_spec[i].v_canvas_height = mb_height << 4; + + canvas_config(128 + i * 2, + buffer_spec[i].y_addr, + mb_width << 4, mb_height << 4, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_32X32); + canvas_config(128 + i * 2 + 1, + buffer_spec[i].u_addr, + mb_width << 4, mb_height << 3, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_32X32); + WRITE_VREG(ANC0_CANVAS_ADDR + i, + spec2canvas(&buffer_spec[i])); + } else { + buffer_spec[i].y_canvas_index = + 2 * (i - 21) + 4; + buffer_spec[i].y_addr = addr; + addr += mb_total << 8; + buffer_spec[i].u_canvas_index = + 2 * (i - 21) + 5; + buffer_spec[i].v_canvas_index = + 2 * (i - 21) + 5; + buffer_spec[i].u_addr = addr; + addr += mb_total << 7; + vfbuf_use[i] = 0; + + buffer_spec[i].y_canvas_width = mb_width << 4; + buffer_spec[i].y_canvas_height = mb_height << 4; + buffer_spec[i].u_canvas_width = mb_width << 4; + buffer_spec[i].u_canvas_height = mb_height << 4; + buffer_spec[i].v_canvas_width = mb_width << 4; + buffer_spec[i].v_canvas_height = mb_height << 4; + + spec_set_canvas(&buffer_spec[i] + , mb_width << 4, mb_height << 4); + WRITE_VREG(ANC0_CANVAS_ADDR + i + , spec2canvas(&buffer_spec[i])); + } + } + } else { + fatal_error_flag = + DECODER_FATAL_ERROR_NO_MEM; + vh264_running = 0; + mutex_unlock(&vh264_mutex); + pr_err("never be here!!\n"); + return; + } + + timing_info_present_flag = seq_info & 0x2; + fixed_frame_rate_flag = 0; + aspect_ratio_info_present_flag = seq_info & 0x1; + aspect_ratio_idc = (seq_info >> 16) & 0xff; + + if (timing_info_present_flag) { + fixed_frame_rate_flag = seq_info & 0x40; + + if (((num_units_in_tick * 120) >= time_scale + && ((!sync_outside) || (!frame_dur))) && + num_units_in_tick + && time_scale) { + if (use_idr_framerate || !frame_dur + || !duration_from_pts_done || vh264_running) { + u32 frame_dur_es = + div_u64(96000ULL * 2 * + num_units_in_tick, + time_scale); + + /* hack to avoid use ES frame duration + * when it's half of the rate from + * system info + */ + /* sometimes the encoder is given a wrong + * frame rate but the system side information + *is more reliable + */ + if ((frame_dur * 2) != frame_dur_es) { + frame_dur = frame_dur_es; + if (fr_hint_status == VDEC_NEED_HINT) { + schedule_work(¬ify_work); + fr_hint_status = VDEC_HINTED; + } + } + } + } + } else + pr_info("H.264: timing_info not present\n"); + + if (aspect_ratio_info_present_flag) { + if (aspect_ratio_idc == EXTEND_SAR) { + h264_ar = + div_u64(256ULL * (aspect_ratio_info >> 16) * + frame_height, + (aspect_ratio_info & 0xffff) * + frame_width); + } else { + /* pr_info("v264dec: aspect_ratio_idc = %d\n", + * aspect_ratio_idc); + */ + + switch (aspect_ratio_idc) { + case 1: + h264_ar = 0x100 * frame_height / frame_width; + break; + case 2: + h264_ar = 0x100 * frame_height * 11 / + (frame_width * 12); + break; + case 3: + h264_ar = 0x100 * frame_height * 11 / + (frame_width * 10); + break; + case 4: + h264_ar = 0x100 * frame_height * 11 / + (frame_width * 16); + break; + case 5: + h264_ar = 0x100 * frame_height * 33 / + (frame_width * 40); + break; + case 6: + h264_ar = 0x100 * frame_height * 11 / + (frame_width * 24); + break; + case 7: + h264_ar = 0x100 * frame_height * 11 / + (frame_width * 20); + break; + case 8: + h264_ar = 0x100 * frame_height * 11 / + (frame_width * 32); + break; + case 9: + h264_ar = 0x100 * frame_height * 33 / + (frame_width * 80); + break; + case 10: + h264_ar = 0x100 * frame_height * 11 / + (frame_width * 18); + break; + case 11: + h264_ar = 0x100 * frame_height * 11 / + (frame_width * 15); + break; + case 12: + h264_ar = 0x100 * frame_height * 33 / + (frame_width * 64); + break; + case 13: + h264_ar = 0x100 * frame_height * 99 / + (frame_width * 160); + break; + case 14: + h264_ar = 0x100 * frame_height * 3 / + (frame_width * 4); + break; + case 15: + h264_ar = 0x100 * frame_height * 2 / + (frame_width * 3); + break; + case 16: + h264_ar = 0x100 * frame_height * 1 / + (frame_width * 2); + break; + default: + if (vh264_ratio >> 16) { + h264_ar = (frame_height * + (vh264_ratio & 0xffff) * + 0x100 + + ((vh264_ratio >> 16) * + frame_width / 2)) / + ((vh264_ratio >> 16) * + frame_width); + } else { + h264_ar = frame_height * 0x100 / + frame_width; + } + break; + } + } + } else { + pr_info("v264dec: aspect_ratio not available from source\n"); + if (vh264_ratio >> 16) { + /* high 16 bit is width, low 16 bit is height */ + h264_ar = + ((vh264_ratio & 0xffff) * frame_height * 0x100 + + (vh264_ratio >> 16) * frame_width / 2) / + ((vh264_ratio >> 16) * frame_width); + } else + h264_ar = frame_height * 0x100 / frame_width; + } + + WRITE_VREG(AV_SCRATCH_0, + (max_reference_size << 24) | (actual_dpb_size << 16) | + (max_dpb_size << 8)); + if (vh264_stream_switching_state != SWITCHING_STATE_OFF) { + vh264_stream_switching_state = SWITCHING_STATE_OFF; + pr_info("Leaving switching mode.\n"); + } + mutex_unlock(&vh264_mutex); +} + +static unsigned int pts_inc_by_duration( + unsigned int *new_pts, unsigned int *new_pts_rem) +{ + unsigned int r, rem; + + r = last_pts + DUR2PTS(frame_dur); + rem = last_pts_remainder + DUR2PTS_REM(frame_dur); + + if (rem >= 96) { + r++; + rem -= 96; + } + + if (new_pts) + *new_pts = r; + if (new_pts_rem) + *new_pts_rem = rem; + + return r; +} +static inline bool vh264_isr_parser(struct vframe_s *vf, + unsigned int pts_valid, unsigned int buffer_index, + unsigned int pts) +{ + unsigned int pts_duration = 0; + + if (h264_first_pts_ready == 0) { + if (pts_valid == 0) { + vfbuf_use[buffer_index]++; + vf->index = buffer_index; + kfifo_put(&recycle_q, + (const struct vframe_s *)vf); + return false; + } + + h264pts1 = pts; + h264_pts_count = 0; + h264_first_pts_ready = 1; + } else { + if (pts < h264pts1) { + if (h264_pts_count > 24) { + pr_info("invalid h264pts1, reset\n"); + h264pts1 = pts; + h264_pts_count = 0; + } + } + if (pts_valid && (pts > h264pts1) && (h264_pts_count > 24) + && (duration_from_pts_done == 0)) { + unsigned int + old_duration = frame_dur; + h264pts2 = pts; + + pts_duration = (h264pts2 - h264pts1) * 16 / + (h264_pts_count * 15); + + if ((pts_duration != frame_dur) + && (!pts_outside)) { + if (use_idr_framerate) { + bool pts_c_24 = close_to(pts_duration, + RATE_24_FPS, + RATE_CORRECTION_THRESHOLD); + bool frm_c_25 = close_to(frame_dur, + RATE_25_FPS, + RATE_CORRECTION_THRESHOLD); + bool pts_c_25 = close_to(pts_duration, + RATE_25_FPS, + RATE_CORRECTION_THRESHOLD); + bool frm_c_24 = close_to(frame_dur, + RATE_24_FPS, + RATE_CORRECTION_THRESHOLD); + if ((pts_c_24 && frm_c_25) + || (pts_c_25 && frm_c_24)) { + pr_info + ("H.264:Correct frame dur "); + pr_info + (" from %d to duration based ", + frame_dur); + pr_info + ("on PTS %d ---\n", + pts_duration); + frame_dur = pts_duration; + duration_from_pts_done = 1; + } else if (((frame_dur < 96000 / 240) + && (pts_duration > 96000 / 240)) + || (!duration_on_correcting && + !frm_c_25 && !frm_c_24)) { + /* fft: if the frame rate is + * not regular, use the + * calculate rate insteadof. + */ + pr_info + ("H.264:Correct frame dur "); + pr_info + (" from %d to duration based ", + frame_dur); + pr_info + ("on PTS %d ---\n", + pts_duration); + frame_dur = pts_duration; + duration_on_correcting = 1; + } + } else { + if (close_to(pts_duration, + frame_dur, 2000)) { + frame_dur = pts_duration; + pr_info + ("used calculate frame rate,"); + pr_info("on duration =%d\n", + frame_dur); + } else { + pr_info + ("don't use calculate frame "); + pr_info + ("rate pts_duration =%d\n", + pts_duration); + } + } + } + + if (duration_from_pts_done == 0) { + if (close_to + (pts_duration, + old_duration, + RATE_CORRECTION_THRESHOLD)) { + pr_info + ("finished correct frame dur"); + pr_info + (" new=%d,old_duration=%d,cnt=%d\n", + pts_duration, + old_duration, + h264_pts_count); + duration_from_pts_done = 1; + } else { /*not the same,redo it. */ + if (!close_to(pts_duration, + old_duration, 1000) && + !close_to(pts_duration, + frame_dur, 1000) && + close_to(pts_duration, + last_duration, 200)) { + /* yangle: frame_dur must + * wrong,recover it. + */ + frame_dur = pts_duration; + } + + pr_info + ("restart correct frame duration "); + pr_info + ("new=%d,old_duration=%d,cnt=%d\n", + pts_duration, + old_duration, + h264_pts_count); + h264pts1 = h264pts2; + h264_pts_count = 0; + duration_from_pts_done = 0; + } + } + last_duration = pts_duration; + } + } + return true; +} +#ifdef HANDLE_H264_IRQ +static irqreturn_t vh264_isr(int irq, void *dev_id) +#else +static void vh264_isr(void) +#endif +{ + unsigned int buffer_index; + struct vframe_s *vf; + unsigned int cpu_cmd; + unsigned int pts, pts_lookup_save, pts_valid_save, pts_valid = 0; + unsigned int pts_us64_valid = 0; + u64 pts_us64; + bool force_interlaced_frame = false; + unsigned int sei_itu35_flags; + static const unsigned int idr_num = + FIX_FRAME_RATE_CHECK_IDRFRAME_NUM; + static const unsigned int flg_1080_itl = + DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE; + static const unsigned int flg_576_itl = + DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE; + + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + if (0 == (stat & STAT_VDEC_RUN)) { + pr_info("decoder is not running\n"); +#ifdef HANDLE_H264_IRQ + return IRQ_HANDLED; +#else + return; +#endif + } + + cpu_cmd = READ_VREG(AV_SCRATCH_0); + +#ifdef DROP_B_FRAME_FOR_1080P_50_60FPS + if ((frame_dur < 2004) && + (frame_width >= 1400) && + (frame_height >= 1000) && (last_interlaced == 0)) + SET_VREG_MASK(AV_SCRATCH_F, 0x8); +#endif + if ((decoder_force_reset == 1) + || ((error_recovery_mode != 1) + && (no_idr_error_count >= no_idr_error_max) + && (ucode_type != UCODE_IP_ONLY_PARAM))) { + vh264_running = 0; + pr_info("force reset decoder %d!!!\n", no_idr_error_count); + schedule_work(&error_wd_work); + decoder_force_reset = 0; + no_idr_error_count = 0; + } else if ((cpu_cmd & 0xff) == 1) { + if (unlikely + (vh264_running + && (kfifo_len(&newframe_q) != VF_POOL_SIZE))) { + /* a cmd 1 sent during decoding w/o getting a cmd 3. */ + /* should not happen but the original code has such + * case, do the same process + */ + if ((READ_VREG(AV_SCRATCH_1) & 0xff) + == 1) {/*invalid mb_width*/ + vh264_running = 0; + fatal_error_flag = DECODER_FATAL_ERROR_UNKNOWN; + /* this is fatal error, need restart */ + pr_info("cmd 1 fatal error happened\n"); + schedule_work(&error_wd_work); + } else { + vh264_stream_switching_state = SWITCHING_STATE_ON_CMD1; + pr_info("Enter switching mode cmd1.\n"); + schedule_work(&stream_switching_work); + } + return IRQ_HANDLED; + } + pr_info("Enter set parameter cmd1.\n"); + schedule_work(&set_parameter_work); + return IRQ_HANDLED; + } else if ((cpu_cmd & 0xff) == 2) { + int frame_mb_only, pic_struct_present, pic_struct, prog_frame, + poc_sel, idr_flag, eos, error; + int i, status, num_frame, b_offset; + int current_error_count, slice_type; + + vh264_running = 1; + vh264_no_disp_count = 0; + num_frame = (cpu_cmd >> 8) & 0xff; + frame_mb_only = seq_info & 0x8000; + pic_struct_present = seq_info & 0x10; + + current_error_count = READ_VREG(AV_SCRATCH_D); + if (vh264_error_count != current_error_count) { + /* pr_info("decoder error happened, count %d\n", + * current_error_count); + */ + vh264_error_count = current_error_count; + } + + for (i = 0; (i < num_frame) && (!vh264_eos); i++) { + status = READ_VREG(AV_SCRATCH_1 + i); + buffer_index = status & 0x1f; + error = status & 0x200; + slice_type = (READ_VREG(AV_SCRATCH_H) >> (i * 4)) & 0xf; + + if ((error_recovery_mode_use & 2) && error) + check_pts_discontinue = true; + if (ucode_type == UCODE_IP_ONLY_PARAM + && iponly_early_mode) + continue; + if ((p_last_vf != NULL) + && (p_last_vf->index == buffer_index)) + continue; + + if (buffer_index >= VF_BUF_NUM) + continue; + + pic_struct = (status >> 5) & 0x7; + prog_frame = status & 0x100; + poc_sel = status & 0x200; + idr_flag = status & 0x400; + frame_packing_type = (status >> 12) & 0x7; + eos = (status >> 15) & 1; + + if (eos) + vh264_eos = 1; + + b_offset = (status >> 16) & 0xffff; + + if (error) + no_idr_error_count++; + if (idr_flag || + (!error && (slice_type != SLICE_TYPE_I))) + no_idr_error_count = 0; + + if (decoder_debug_flag) { + pr_info + ("slice_type %x idr %x error %x count %d", + slice_type, idr_flag, error, + no_idr_error_count); + pr_info(" prog %x pic_struct %x offset %x\n", + prog_frame, pic_struct, b_offset); + } +#ifdef DROP_B_FRAME_FOR_1080P_50_60FPS + last_interlaced = prog_frame ? 0 : 1; +#endif + if (kfifo_get(&newframe_q, &vf) == 0) { + pr_info + ("fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + + if (clk_adj_frame_count < VDEC_CLOCK_ADJUST_FRAME) + clk_adj_frame_count++; + + set_frame_info(vf); + + switch (i) { + case 0: + b_offset |= + (READ_VREG(AV_SCRATCH_A) & 0xffff) + << 16; + break; + case 1: + b_offset |= + READ_VREG(AV_SCRATCH_A) & 0xffff0000; + break; + case 2: + b_offset |= + (READ_VREG(AV_SCRATCH_B) & 0xffff) + << 16; + break; + case 3: + b_offset |= + READ_VREG(AV_SCRATCH_B) & 0xffff0000; + break; + case 4: + b_offset |= + (READ_VREG(AV_SCRATCH_C) & 0xffff) + << 16; + break; + case 5: + b_offset |= + READ_VREG(AV_SCRATCH_C) & 0xffff0000; + break; + default: + break; + } + + if (error) + gvs->drop_frame_count++; + + /* add 64bit pts us ; */ + if (unlikely + ((b_offset == first_offset) + && (first_pts_cached))) { + pts = first_pts; + pts_us64 = first_pts64; + first_pts_cached = false; + pts_valid = 1; + pts_us64_valid = 1; +#ifdef DEBUG_PTS + pts_hit++; +#endif + } else if (pts_lookup_offset_us64 + (PTS_TYPE_VIDEO, b_offset, &pts, 0, + &pts_us64) == 0) { + pts_valid = 1; + pts_us64_valid = 1; +#ifdef DEBUG_PTS + pts_hit++; +#endif + } else { + pts_valid = 0; + pts_us64_valid = 0; +#ifdef DEBUG_PTS + pts_missed++; +#endif + } + + /* on second IDR frame,check the diff between pts + * compute from duration and pts from lookup , + * if large than frame_dur,we think it is uncorrect. + */ + pts_lookup_save = pts; + pts_valid_save = pts_valid; + if (fixed_frame_rate_flag + && (fixed_frame_rate_check_count <= + idr_num)) { + if (idr_flag && pts_valid) { + fixed_frame_rate_check_count++; + /* pr_info("diff:%d\n", + * last_pts - pts_lookup_save); + */ + if ((fixed_frame_rate_check_count == + idr_num) && + (abs(pts - (last_pts + + DUR2PTS(frame_dur))) > + DUR2PTS(frame_dur))) { + fixed_frame_rate_flag = 0; + pr_info("pts sync mode play\n"); + } + + if (fixed_frame_rate_flag + && (fixed_frame_rate_check_count + > idr_num)) { + pr_info + ("fix_frame_rate mode play\n"); + } + } + } + + if (READ_VREG(AV_SCRATCH_F) & 2) { + /* for I only mode, ignore the PTS information + * and only uses frame duration for each I + * frame decoded + */ + if (p_last_vf) + pts_valid = 0; + /* also skip frame duration calculation + * based on PTS + */ + duration_from_pts_done = 1; + /* and add a default duration for 1/30 second + * if there is no valid frame + * duration available + */ + if (frame_dur == 0) + frame_dur = 96000 / 30; + } + + if (sync_outside == 0) { + if (!vh264_isr_parser(vf, + pts_valid, buffer_index, pts)) + continue; + + h264_pts_count++; + } else { + if (!idr_flag) + pts_valid = 0; + } + + if (pts_valid && !pts_discontinue) { + pts_discontinue = + (abs(last_pts - pts) >= + tsync_vpts_discontinuity_margin()); + } + /* if use_idr_framerate or fixed frame rate, only + * use PTS for IDR frames except for pts discontinue + */ + if (timing_info_present_flag && + frame_dur && + (use_idr_framerate || + (fixed_frame_rate_flag != 0)) + && pts_valid && h264_first_valid_pts_ready + && (!pts_discontinue)) { + pts_valid = + (slice_type == SLICE_TYPE_I) ? 1 : 0; + } + + if (!h264_first_valid_pts_ready && pts_valid) { + h264_first_valid_pts_ready = true; + last_pts = pts - DUR2PTS(frame_dur); + last_pts_remainder = 0; + } + /* calculate PTS of next frame and smooth + * PTS for fixed rate source + */ + if (pts_valid) { + if ((fixed_frame_rate_flag) && + (!pts_discontinue) && + (abs(pts_inc_by_duration(NULL, NULL) + - pts) + < DUR2PTS(frame_dur))) { + pts = pts_inc_by_duration(&pts, + &last_pts_remainder); + } else + last_pts_remainder = 0; + + } else { + if (fixed_frame_rate_flag && !pts_discontinue && + (fixed_frame_rate_check_count > idr_num) && + pts_valid_save && (sync_outside == 0) && + (abs(pts_inc_by_duration(NULL, NULL) - pts) + > DUR2PTS(frame_dur))) { + duration_from_pts_done = 0; + pr_info("recalc frame_dur\n"); + } else + pts = pts_inc_by_duration(&pts, + &last_pts_remainder); + pts_valid = 1; + } + + if ((dec_control & + flg_1080_itl) + && (frame_width == 1920) + && (frame_height >= 1080) + && (vf->duration == 3203)) + force_interlaced_frame = true; + else if ((dec_control & + flg_576_itl) + && (frame_width == 720) + && (frame_height == 576) + && (vf->duration == 3840)) + force_interlaced_frame = true; + + /* for frames with PTS, check if there is PTS + * discontinue based on previous frames + * (including error frames), + * force no VPTS discontinue reporting if we saw + *errors earlier but only once. + */ + + /*count info*/ + gvs->frame_dur = frame_dur; + vdec_count_info(gvs, error, b_offset); + + if ((pts_valid) && (check_pts_discontinue) + && (!error)) { + if (pts_discontinue) { + vf->flag = 0; + check_pts_discontinue = false; + } else if ((pts - last_pts) < 90000) { + vf->flag = VFRAME_FLAG_NO_DISCONTINUE; + check_pts_discontinue = false; + } + } + + last_pts = pts; + + if (fixed_frame_rate_flag + && (fixed_frame_rate_check_count <= + idr_num) + && (sync_outside == 0) + && pts_valid_save) + pts = pts_lookup_save; + + if (pic_struct_present) { + if ((pic_struct == PIC_TOP_BOT) + || (pic_struct == PIC_BOT_TOP)) + prog_frame = 0; + } + + if ((!force_interlaced_frame) + && (prog_frame + || (pic_struct_present + && pic_struct + <= PIC_TRIPLE_FRAME))) { + if (pic_struct_present) { + if (pic_struct == PIC_TOP_BOT_TOP + || pic_struct + == PIC_BOT_TOP_BOT) { + vf->duration += + vf->duration >> 1; + } else if (pic_struct == + PIC_DOUBLE_FRAME) + vf->duration += vf->duration; + else if (pic_struct == + PIC_TRIPLE_FRAME) { + vf->duration += + vf->duration << 1; + } + } + + last_pts = + last_pts + DUR2PTS(vf->duration - + frame_dur); + + vf->index = buffer_index; + vf->type = + VIDTYPE_PROGRESSIVE | + VIDTYPE_VIU_FIELD | + VIDTYPE_VIU_NV21; + vf->duration_pulldown = 0; + vf->signal_type = video_signal_from_vui; + vf->index = buffer_index; + vf->pts = (pts_valid) ? pts : 0; + if (pts_us64_valid == 1) + vf->pts_us64 = pts_us64; + else + vf->pts_us64 = div64_u64(((u64)vf->pts)*100, 9); + vf->canvas0Addr = vf->canvas1Addr = + spec2canvas(&buffer_spec[buffer_index]); + vf->type_original = vf->type; + vfbuf_use[buffer_index]++; + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + VF_BUFFER_IDX(buffer_index)); + if ((error_recovery_mode_use & 2) && error) { + kfifo_put(&recycle_q, + (const struct vframe_s *)vf); + } else { + p_last_vf = vf; + pts_discontinue = false; + kfifo_put(&delay_display_q, + (const struct vframe_s *)vf); + } + } else { + if (pic_struct_present + && pic_struct == PIC_TOP_BOT) + vf->type = VIDTYPE_INTERLACE_TOP; + else if (pic_struct_present + && pic_struct == PIC_BOT_TOP) + vf->type = VIDTYPE_INTERLACE_BOTTOM; + else { + vf->type = + poc_sel ? + VIDTYPE_INTERLACE_BOTTOM : + VIDTYPE_INTERLACE_TOP; + } + vf->type |= VIDTYPE_VIU_NV21; + vf->type |= VIDTYPE_INTERLACE_FIRST; + + high_bandwidth |= + ((codec_mm_get_total_size() < 80 * SZ_1M) + & ((READ_VREG(AV_SCRATCH_N) & 0xf) == 3) + & ((frame_width * frame_height) >= 1920*1080)); + if (high_bandwidth) + vf->flag |= VFRAME_FLAG_HIGH_BANDWIDTH; + + vf->duration >>= 1; + vf->duration_pulldown = 0; + vf->signal_type = video_signal_from_vui; + vf->index = buffer_index; + vf->pts = (pts_valid) ? pts : 0; + if (pts_us64_valid == 1) + vf->pts_us64 = pts_us64; + else + vf->pts_us64 = div64_u64(((u64)vf->pts)*100, 9); + vf->canvas0Addr = vf->canvas1Addr = + spec2canvas(&buffer_spec[buffer_index]); + vf->type_original = vf->type; + vfbuf_use[buffer_index]++; + vf->ready_jiffies64 = jiffies_64; + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + VF_BUFFER_IDX(buffer_index)); + if ((error_recovery_mode_use & 2) && error) { + kfifo_put(&recycle_q, + (const struct vframe_s *)vf); + continue; + } else { + pts_discontinue = false; + kfifo_put(&delay_display_q, + (const struct vframe_s *)vf); + } + + if (READ_VREG(AV_SCRATCH_F) & 2) + continue; + + if (kfifo_get(&newframe_q, &vf) == 0) { + pr_info + ("fatal error, no avail buffer slot."); + return IRQ_HANDLED; + } + + set_frame_info(vf); + + if (pic_struct_present + && pic_struct == PIC_TOP_BOT) + vf->type = VIDTYPE_INTERLACE_BOTTOM; + else if (pic_struct_present + && pic_struct == PIC_BOT_TOP) + vf->type = VIDTYPE_INTERLACE_TOP; + else { + vf->type = + poc_sel ? + VIDTYPE_INTERLACE_TOP : + VIDTYPE_INTERLACE_BOTTOM; + } + + vf->type |= VIDTYPE_VIU_NV21; + vf->duration >>= 1; + vf->duration_pulldown = 0; + vf->signal_type = video_signal_from_vui; + vf->index = buffer_index; + vf->pts = 0; + vf->pts_us64 = 0; + vf->canvas0Addr = vf->canvas1Addr = + spec2canvas(&buffer_spec[buffer_index]); + vf->type_original = vf->type; + vfbuf_use[buffer_index]++; + if (high_bandwidth) + vf->flag |= VFRAME_FLAG_HIGH_BANDWIDTH; + + p_last_vf = vf; + vf->ready_jiffies64 = jiffies_64; + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + VF_BUFFER_IDX(buffer_index)); + kfifo_put(&delay_display_q, + (const struct vframe_s *)vf); + } + } + + WRITE_VREG(AV_SCRATCH_0, 0); + } else if ((cpu_cmd & 0xff) == 3) { + vh264_running = 1; + vh264_stream_switching_state = SWITCHING_STATE_ON_CMD3; + + pr_info("Enter switching mode cmd3.\n"); + schedule_work(&stream_switching_work); + + } else if ((cpu_cmd & 0xff) == 4) { + vh264_running = 1; + /* reserved for slice group */ + WRITE_VREG(AV_SCRATCH_0, 0); + } else if ((cpu_cmd & 0xff) == 5) { + vh264_running = 1; + /* reserved for slice group */ + WRITE_VREG(AV_SCRATCH_0, 0); + } else if ((cpu_cmd & 0xff) == 6) { + vh264_running = 0; + fatal_error_flag = DECODER_FATAL_ERROR_UNKNOWN; + /* this is fatal error, need restart */ + pr_info("fatal error happend\n"); + amvdec_stop(); + if (!fatal_error_reset) + schedule_work(&error_wd_work); + } else if ((cpu_cmd & 0xff) == 7) { + vh264_running = 0; + frame_width = (READ_VREG(AV_SCRATCH_1) + 1) * 16; + pr_info("Over decoder supported size, width = %d\n", + frame_width); + fatal_error_flag = DECODER_FATAL_ERROR_SIZE_OVERFLOW; + } else if ((cpu_cmd & 0xff) == 8) { + vh264_running = 0; + frame_height = (READ_VREG(AV_SCRATCH_1) + 1) * 16; + pr_info("Over decoder supported size, height = %d\n", + frame_height); + fatal_error_flag = DECODER_FATAL_ERROR_SIZE_OVERFLOW; + } else if ((cpu_cmd & 0xff) == 9) { + first_offset = READ_VREG(AV_SCRATCH_1); + if (pts_lookup_offset_us64 + (PTS_TYPE_VIDEO, first_offset, &first_pts, 0, + &first_pts64) == 0) + first_pts_cached = true; + WRITE_VREG(AV_SCRATCH_0, 0); + } else if ((cpu_cmd & 0xff) == 0xa) { + int b_offset; + + b_offset = READ_VREG(AV_SCRATCH_2); + buffer_index = READ_VREG(AV_SCRATCH_1); + /*pr_info("iponly output %d b_offset %x\n", + * buffer_index,b_offset); + */ + if (kfifo_get(&newframe_q, &vf) == 0) { + WRITE_VREG(AV_SCRATCH_0, 0); + pr_info + ("fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + if (pts_lookup_offset_us64 (PTS_TYPE_VIDEO, b_offset, + &pts, 0, &pts_us64) != 0) + vf->pts_us64 = vf->pts = 0; + else { + vf->pts_us64 = pts_us64; + vf->pts = pts; + } + set_frame_info(vf); + vf->type = VIDTYPE_PROGRESSIVE | + VIDTYPE_VIU_FIELD | + VIDTYPE_VIU_NV21; + vf->duration_pulldown = 0; + vf->signal_type = video_signal_from_vui; + vf->index = buffer_index; + vf->canvas0Addr = vf->canvas1Addr = + spec2canvas(&buffer_spec[buffer_index]); + vf->type_original = vf->type; + vf->mem_handle = decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + VF_BUFFER_IDX(buffer_index)); + vfbuf_use[buffer_index]++; + p_last_vf = vf; + pts_discontinue = false; + iponly_early_mode = 1; + kfifo_put(&delay_display_q, + (const struct vframe_s *)vf); + WRITE_VREG(AV_SCRATCH_0, 0); + } + + sei_itu35_flags = READ_VREG(AV_SCRATCH_J); + if (sei_itu35_flags & (1 << 15)) { /* data ready */ + schedule_work(&userdata_push_work); + } +#ifdef HANDLE_H264_IRQ + return IRQ_HANDLED; +#else + return; +#endif +} + +static void vh264_set_clk(struct work_struct *work) +{ + if (ucode_type != UCODE_IP_ONLY_PARAM && + (clk_adj_frame_count > VDEC_CLOCK_ADJUST_FRAME) && + frame_dur > 0 && saved_resolution != + frame_width * frame_height * (96000 / frame_dur)) { + int fps = 96000 / frame_dur; + + if (frame_dur < 10) /*dur is too small ,think it errors fps*/ + fps = 60; + saved_resolution = frame_width * frame_height * fps; + vdec_source_changed(VFORMAT_H264, + frame_width, frame_height, fps); + } +} + +static void vh264_put_timer_func(unsigned long arg) +{ + struct timer_list *timer = (struct timer_list *)arg; + unsigned int wait_buffer_status; + unsigned int wait_i_pass_frames; + unsigned int reg_val; + + enum receviver_start_e state = RECEIVER_INACTIVE; + + if (vh264_reset) { + pr_info("operation forbidden in timer !\n"); + goto exit; + } + + prepare_display_q(); + + if (vf_get_receiver(PROVIDER_NAME)) { + state = + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_QUREY_STATE, + NULL); + if ((state == RECEIVER_STATE_NULL) + || (state == RECEIVER_STATE_NONE)) { + /* receiver has no event_cb or receiver's + * event_cb does not process this event + */ + state = RECEIVER_INACTIVE; + } + } else + state = RECEIVER_INACTIVE; +#ifndef HANDLE_H264_IRQ + vh264_isr(); +#endif + + if (vh264_stream_switching_state != SWITCHING_STATE_OFF) + wait_buffer_counter = 0; + else { + reg_val = READ_VREG(AV_SCRATCH_9); + wait_buffer_status = reg_val & (1 << 31); + wait_i_pass_frames = reg_val & 0xff; + if (wait_buffer_status) { + if (kfifo_is_empty(&display_q) && + kfifo_is_empty(&delay_display_q) && + kfifo_is_empty(&recycle_q) && + (state == RECEIVER_INACTIVE)) { + pr_info("$$$$decoder is waiting for buffer\n"); + if (++wait_buffer_counter > 4) { + amvdec_stop(); + schedule_work(&error_wd_work); + } + } else + wait_buffer_counter = 0; + } else if (wait_i_pass_frames > 1000) { + pr_info("i passed frames > 1000\n"); + amvdec_stop(); + schedule_work(&error_wd_work); + } + } + +#if 0 + if (!wait_buffer_status) { + if (vh264_no_disp_count++ > NO_DISP_WD_COUNT) { + pr_info("$$$decoder did not send frame out\n"); + amvdec_stop(); +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vh264_ppmgr_reset(); +#else + vf_light_unreg_provider(PROVIDER_NAME); + vh264_local_init(); + vf_reg_provider(vh264_vf_prov); +#endif + vh264_prot_init(); + amvdec_start(); + + vh264_no_disp_count = 0; + vh264_no_disp_wd_count++; + } + } +#endif + + while (!kfifo_is_empty(&recycle_q) && + ((READ_VREG(AV_SCRATCH_7) == 0) + || (READ_VREG(AV_SCRATCH_8) == 0)) + && (vh264_stream_switching_state == SWITCHING_STATE_OFF)) { + struct vframe_s *vf; + + if (kfifo_get(&recycle_q, &vf)) { + if ((vf->index >= 0) && (vf->index < VF_BUF_NUM)) { + if (--vfbuf_use[vf->index] == 0) { + if (READ_VREG(AV_SCRATCH_7) == 0) { + WRITE_VREG(AV_SCRATCH_7, + vf->index + 1); + } else { + WRITE_VREG(AV_SCRATCH_8, + vf->index + 1); + } + } + + vf->index = VF_BUF_NUM; + kfifo_put(&newframe_q, + (const struct vframe_s *)vf); + } + } + } + + if (vh264_stream_switching_state != SWITCHING_STATE_OFF) { + while (!kfifo_is_empty(&recycle_q)) { + struct vframe_s *vf; + + if (kfifo_get(&recycle_q, &vf)) { + if ((vf->index >= 0 && + (vf->index < VF_BUF_NUM))) { + vf->index = VF_BUF_NUM; + kfifo_put(&newframe_q, + (const struct vframe_s *)vf); + } + } + } + + WRITE_VREG(AV_SCRATCH_7, 0); + WRITE_VREG(AV_SCRATCH_8, 0); + + if (kfifo_len(&newframe_q) == VF_POOL_SIZE) + stream_switching_done(); + } + + schedule_work(&set_clk_work); + +exit: + timer->expires = jiffies + PUT_INTERVAL; + + add_timer(timer); +} + +int vh264_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus) +{ + vstatus->frame_width = frame_width; + vstatus->frame_height = frame_height; + if (frame_dur != 0) + vstatus->frame_rate = 96000 / frame_dur; + else + vstatus->frame_rate = -1; + vstatus->error_count = READ_VREG(AV_SCRATCH_D); + vstatus->status = stat; + if (fatal_error_reset) + vstatus->status |= fatal_error_flag; + vstatus->bit_rate = gvs->bit_rate; + vstatus->frame_dur = frame_dur; + vstatus->frame_data = gvs->frame_data; + vstatus->total_data = gvs->total_data; + vstatus->frame_count = gvs->frame_count; + vstatus->error_frame_count = gvs->error_frame_count; + vstatus->drop_frame_count = gvs->drop_frame_count; + vstatus->total_data = gvs->total_data; + vstatus->samp_cnt = gvs->samp_cnt; + vstatus->offset = gvs->offset; + snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name), + "%s", DRIVER_NAME); + + return 0; +} + +static int vh264_vdec_info_init(void) +{ + gvs = kzalloc(sizeof(struct vdec_info), GFP_KERNEL); + if (NULL == gvs) { + pr_info("the struct of vdec status malloc failed.\n"); + return -ENOMEM; + } + return 0; +} + +int vh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode) +{ + if (trickmode == TRICKMODE_I) { + WRITE_VREG(AV_SCRATCH_F, + (READ_VREG(AV_SCRATCH_F) & 0xfffffffc) | 2); + trickmode_i = 1; + } else if (trickmode == TRICKMODE_NONE) { + WRITE_VREG(AV_SCRATCH_F, READ_VREG(AV_SCRATCH_F) & 0xfffffffc); + trickmode_i = 0; + } + + return 0; +} + +int vh264_set_isreset(struct vdec_s *vdec, int isreset) +{ + is_reset = isreset; + return 0; +} + +static void vh264_prot_init(void) +{ + + while (READ_VREG(DCAC_DMA_CTRL) & 0x8000) + ; + while (READ_VREG(LMEM_DMA_CTRL) & 0x8000) + ; /* reg address is 0x350 */ + +#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ + WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4)); + WRITE_VREG(DOS_SW_RESET0, 0); + + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + + WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4)); + WRITE_VREG(DOS_SW_RESET0, 0); + + WRITE_VREG(DOS_SW_RESET0, (1 << 9) | (1 << 8)); + WRITE_VREG(DOS_SW_RESET0, 0); + + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + +#else + WRITE_RESET_REG(RESET0_REGISTER, + RESET_IQIDCT | RESET_MC | RESET_VLD_PART); + READ_RESET_REG(RESET0_REGISTER); + WRITE_RESET_REG(RESET0_REGISTER, + RESET_IQIDCT | RESET_MC | RESET_VLD_PART); + + WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK); +#endif + + WRITE_VREG(POWER_CTL_VLD, + READ_VREG(POWER_CTL_VLD) | + (0 << 10) | (1 << 9) | (1 << 6)); + + /* disable PSCALE for hardware sharing */ + WRITE_VREG(PSCALE_CTRL, 0); + + WRITE_VREG(AV_SCRATCH_0, 0); + WRITE_VREG(AV_SCRATCH_1, buf_offset); + if (!tee_enabled()) + WRITE_VREG(AV_SCRATCH_G, mc_dma_handle); + WRITE_VREG(AV_SCRATCH_7, 0); + WRITE_VREG(AV_SCRATCH_8, 0); + WRITE_VREG(AV_SCRATCH_9, 0); + WRITE_VREG(AV_SCRATCH_N, 0); + +#ifdef SUPPORT_BAD_MACRO_BLOCK_REDUNDANCY + if (bad_block_scale > 128) + bad_block_scale = 128; + WRITE_VREG(AV_SCRATCH_A, bad_block_scale); +#endif + + error_recovery_mode_use = + (error_recovery_mode != + 0) ? error_recovery_mode : error_recovery_mode_in; + WRITE_VREG(AV_SCRATCH_F, + (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) | + (READ_VREG(AV_SCRATCH_F) & 0xffffff43) | + ((error_recovery_mode_use & 0x1) << 4)); + if (dec_control & DEC_CONTROL_FLAG_DISABLE_FAST_POC) + SET_VREG_MASK(AV_SCRATCH_F, 1 << 7); + /* clear mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + /* enable mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_MASK, 1); + + SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17); + if (ucode_type == UCODE_IP_ONLY_PARAM) + SET_VREG_MASK(AV_SCRATCH_F, 1 << 6); + else + CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6); + + WRITE_VREG(AV_SCRATCH_I, (u32)(sei_data_buffer_phys - buf_offset)); + WRITE_VREG(AV_SCRATCH_J, 0); + /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ + if ((get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) && !is_meson_mtvd_cpu()) { + /* pr_info("vh264 meson8 prot init\n"); */ + WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa); + } + /* #endif */ +} + +static int vh264_local_init(void) +{ + int i, ret; + u32 size; + unsigned long buf_start; + vh264_ratio = vh264_amstream_dec_info.ratio; + /* vh264_ratio = 0x100; */ + + vh264_rotation = (((unsigned long) vh264_amstream_dec_info.param) + >> 16) & 0xffff; + + frame_prog = 0; + frame_width = vh264_amstream_dec_info.width; + frame_height = vh264_amstream_dec_info.height; + frame_dur = vh264_amstream_dec_info.rate; + pts_outside = ((unsigned long) vh264_amstream_dec_info.param) & 0x01; + sync_outside = ((unsigned long) vh264_amstream_dec_info.param & 0x02) + >> 1; + use_idr_framerate = ((unsigned long) vh264_amstream_dec_info.param + & 0x04) >> 2; + max_refer_buf = !(((unsigned long) vh264_amstream_dec_info.param + & 0x10) >> 4); + if (!vh264_reset) { + if (mm_blk_handle) { + decoder_bmmu_box_free(mm_blk_handle); + mm_blk_handle = NULL; + } + + mm_blk_handle = decoder_bmmu_box_alloc_box( + DRIVER_NAME, + 0, + MAX_BLK_BUFFERS, + 4 + PAGE_SHIFT, + CODEC_MM_FLAGS_CMA_CLEAR | + CODEC_MM_FLAGS_FOR_VDECODER | + tvp_flag); + } + pr_info + ("H264 sysinfo: %dx%d duration=%d, pts_outside=%d \n", + frame_width, frame_height, frame_dur, pts_outside); + pr_debug("sync_outside=%d, use_idr_framerate=%d\n", + sync_outside, use_idr_framerate); + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) + size = V_BUF_ADDR_OFFSET_NEW; + else + size = V_BUF_ADDR_OFFSET; + + ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, 0, + size, DRIVER_NAME, &buf_start); + if (ret < 0) + return ret; + + buf_offset = buf_start - DEF_BUF_START_ADDR; + + if ((unsigned long) vh264_amstream_dec_info.param & 0x08) + ucode_type = UCODE_IP_ONLY_PARAM; + else + ucode_type = 0; + + if ((unsigned long) vh264_amstream_dec_info.param & 0x20) + error_recovery_mode_in = 1; + else + error_recovery_mode_in = 3; + + if (!vh264_running) { + last_mb_width = 0; + last_mb_height = 0; + } + + for (i = 0; i < VF_BUF_NUM; i++) + vfbuf_use[i] = 0; + + INIT_KFIFO(display_q); + INIT_KFIFO(delay_display_q); + INIT_KFIFO(recycle_q); + INIT_KFIFO(newframe_q); + + for (i = 0; i < VF_POOL_SIZE; i++) { + const struct vframe_s *vf = &vfpool[i]; + + vfpool[i].index = VF_BUF_NUM; + vfpool[i].bufWidth = 1920; + kfifo_put(&newframe_q, vf); + } + +#ifdef DROP_B_FRAME_FOR_1080P_50_60FPS + last_interlaced = 1; +#endif + h264_first_pts_ready = 0; + h264_first_valid_pts_ready = false; + h264pts1 = 0; + h264pts2 = 0; + h264_pts_count = 0; + duration_from_pts_done = 0; + vh264_error_count = READ_VREG(AV_SCRATCH_D); + + p_last_vf = NULL; + check_pts_discontinue = false; + last_pts = 0; + wait_buffer_counter = 0; + vh264_no_disp_count = 0; + fatal_error_flag = 0; + high_bandwidth = 0; + vh264_stream_switching_state = SWITCHING_STATE_OFF; +#ifdef DEBUG_PTS + pts_missed = 0; + pts_hit = 0; +#endif + pts_discontinue = false; + no_idr_error_count = 0; + + reset_userdata_fifo(1); + + if (enable_switch_fense) { + for (i = 0; i < ARRAY_SIZE(fense_buffer_spec); i++) { + struct buffer_spec_s *s = &fense_buffer_spec[i]; + s->alloc_count = 3 * SZ_1M / PAGE_SIZE; + ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, + FENSE_BUFFER_IDX(i), + 3 * SZ_1M, DRIVER_NAME, &s->phy_addr); + + if (ret < 0) { + fatal_error_flag = + DECODER_FATAL_ERROR_NO_MEM; + vh264_running = 0; + return ret; + } + s->y_canvas_index = 2 * i; + s->u_canvas_index = 2 * i + 1; + s->v_canvas_index = 2 * i + 1; + } + } + return 0; +} + +static s32 vh264_init(void) +{ + int ret = 0; + int trickmode_fffb = 0; + int firmwareloaded = 0; + + /* pr_info("\nvh264_init\n"); */ + init_timer(&recycle_timer); + + stat |= STAT_TIMER_INIT; + + vh264_running = 0;/* init here to reset last_mb_width&last_mb_height */ + vh264_eos = 0; + duration_on_correcting = 0; + first_pts = 0; + first_pts64 = 0; + first_offset = 0; + first_pts_cached = false; + fixed_frame_rate_check_count = 0; + fr_hint_status = VDEC_NO_NEED_HINT; + saved_resolution = 0; + iponly_early_mode = 0; + saved_idc_level = 0; + + /*init vdec status*/ + ret = vh264_vdec_info_init(); + if (0 != ret) + return -ret; + + ret = vh264_local_init(); + if (ret < 0) + return ret; + query_video_status(0, &trickmode_fffb); + + amvdec_enable(); + if (!firmwareloaded && tee_enabled()) { + if (tee_load_video_fw((u32)VIDEO_DEC_H264, 0) != 0) { + amvdec_disable(); + return -1; + } + } else { + /* -- ucode loading (amrisc and swap code) */ + mc_cpu_addr = + dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE, + &mc_dma_handle, GFP_KERNEL); + if (!mc_cpu_addr) { + amvdec_disable(); + del_timer_sync(&recycle_timer); + pr_err("vh264_init: Can not allocate mc memory.\n"); + return -ENOMEM; + } + + pr_debug("264 ucode swap area: phyaddr %p, cpu vaddr %p\n", + (void *)mc_dma_handle, mc_cpu_addr); + if (debugfirmware) { + int r0, r1, r2, r3, r4, r5; + char firmwarename[32]; + + pr_debug("start load debug %d firmware ...\n", debugfirmware); + + snprintf(firmwarename, 32, "%s%d", "vh264_mc", debugfirmware); + r0 = amvdec_loadmc_ex(VFORMAT_H264, firmwarename, NULL); + +#define DEBUGGET_FW(t, name, buf, size, ret)\ + do {\ + snprintf(firmwarename, 32, "%s%d", name,\ + debugfirmware);\ + ret = get_decoder_firmware_data(t,\ + firmwarename, buf, size);\ + } while (0) + /*memcpy((u8 *) mc_cpu_addr + MC_OFFSET_HEADER, vh264_header_mc, + *MC_SWAP_SIZE); + */ + DEBUGGET_FW(VFORMAT_H264, "vh264_header_mc", + (u8 *) mc_cpu_addr + MC_OFFSET_HEADER, + MC_SWAP_SIZE, r1); + + /*memcpy((u8 *) mc_cpu_addr + MC_OFFSET_DATA, vh264_data_mc, + *MC_SWAP_SIZE); + */ + DEBUGGET_FW(VFORMAT_H264, "vh264_data_mc", + (u8 *) mc_cpu_addr + MC_OFFSET_DATA, MC_SWAP_SIZE, r2); + /*memcpy((u8 *) mc_cpu_addr + MC_OFFSET_MMCO, vh264_mmco_mc, + *MC_SWAP_SIZE); + */ + DEBUGGET_FW(VFORMAT_H264, "vh264_mmco_mc", + (u8 *) mc_cpu_addr + MC_OFFSET_MMCO, MC_SWAP_SIZE, r3); + /*memcpy((u8 *) mc_cpu_addr + MC_OFFSET_LIST, vh264_list_mc, + *MC_SWAP_SIZE); + */ + DEBUGGET_FW(VFORMAT_H264, "vh264_list_mc", + (u8 *) mc_cpu_addr + MC_OFFSET_LIST, MC_SWAP_SIZE, r4); + /*memcpy((u8 *) mc_cpu_addr + MC_OFFSET_SLICE, vh264_slice_mc, + *MC_SWAP_SIZE); + */ + DEBUGGET_FW(VFORMAT_H264, "vh264_slice_mc", + (u8 *) mc_cpu_addr + MC_OFFSET_SLICE, MC_SWAP_SIZE, r5); + + if (r0 < 0 || r1 < 0 || r2 < 0 || r3 < 0 || r4 < 0 || r5 < 0) { + pr_err("264 load debugfirmware err %d,%d,%d,%d,%d,%d\n", + r0, r1, r2, r3, r4, r5); + amvdec_disable(); + if (mc_cpu_addr) { + dma_free_coherent(amports_get_dma_device(), + MC_TOTAL_SIZE, mc_cpu_addr, + mc_dma_handle); + mc_cpu_addr = NULL; + } + return -EBUSY; + } + firmwareloaded = 1; + } else { + int ret = -1, size = -1; + char *buf = vmalloc(0x1000 * 16); + + if (IS_ERR_OR_NULL(buf)) + return -ENOMEM; + + size = get_firmware_data(VIDEO_DEC_H264, buf); + if (size < 0) { + pr_err("get firmware fail."); + vfree(buf); + return -1; + } + + ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf); + memcpy((u8 *) mc_cpu_addr + MC_OFFSET_HEADER, + buf + 0x4000, MC_SWAP_SIZE); + memcpy((u8 *) mc_cpu_addr + MC_OFFSET_DATA, + buf + 0x2000, MC_SWAP_SIZE); + memcpy((u8 *) mc_cpu_addr + MC_OFFSET_MMCO, + buf + 0x6000, MC_SWAP_SIZE); + memcpy((u8 *) mc_cpu_addr + MC_OFFSET_LIST, + buf + 0x3000, MC_SWAP_SIZE); + memcpy((u8 *) mc_cpu_addr + MC_OFFSET_SLICE, + buf + 0x5000, MC_SWAP_SIZE); + + vfree(buf); + + if (ret < 0) { + pr_err("h264 load orignal firmware error %d.\n", ret); + amvdec_disable(); + if (mc_cpu_addr) { + dma_free_coherent(amports_get_dma_device(), + MC_TOTAL_SIZE, mc_cpu_addr, + mc_dma_handle); + mc_cpu_addr = NULL; + } + return -EBUSY; + } + } + } + + stat |= STAT_MC_LOAD; + + /* enable AMRISC side protocol */ + vh264_prot_init(); + +#ifdef HANDLE_H264_IRQ + /*TODO irq */ + + if (vdec_request_irq(VDEC_IRQ_1, vh264_isr, + "vh264-irq", (void *)vh264_dec_id)) { + pr_err("vh264 irq register error.\n"); + amvdec_disable(); + return -ENOENT; + } +#endif + + stat |= STAT_ISR_REG; + +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_provider_init(&vh264_vf_prov, PROVIDER_NAME, &vh264_vf_provider_ops, + NULL); + vf_reg_provider(&vh264_vf_prov); + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL); +#else + vf_provider_init(&vh264_vf_prov, PROVIDER_NAME, &vh264_vf_provider_ops, + NULL); + vf_reg_provider(&vh264_vf_prov); +#endif + + if (frame_dur != 0) { + if (!is_reset) + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_FR_HINT, + (void *)((unsigned long)frame_dur)); + fr_hint_status = VDEC_HINTED; + } else + fr_hint_status = VDEC_NEED_HINT; + + stat |= STAT_VF_HOOK; + + recycle_timer.data = (ulong) &recycle_timer; + recycle_timer.function = vh264_put_timer_func; + recycle_timer.expires = jiffies + PUT_INTERVAL; + + add_timer(&recycle_timer); + + stat |= STAT_TIMER_ARM; + + vh264_stream_switching_state = SWITCHING_STATE_OFF; + + stat |= STAT_VDEC_RUN; + wmb(); /* Ensure fetchbuf contents visible */ + + /* -- start decoder */ + amvdec_start(); + + init_userdata_fifo(); + + return 0; +} + +static int vh264_stop(int mode) +{ + + + if (stat & STAT_VDEC_RUN) { + amvdec_stop(); + stat &= ~STAT_VDEC_RUN; + } + + if (stat & STAT_ISR_REG) { + WRITE_VREG(ASSIST_MBOX1_MASK, 0); + /*TODO irq */ + + vdec_free_irq(VDEC_IRQ_1, (void *)vh264_dec_id); + + stat &= ~STAT_ISR_REG; + } + + if (stat & STAT_TIMER_ARM) { + del_timer_sync(&recycle_timer); + stat &= ~STAT_TIMER_ARM; + } + + if (stat & STAT_VF_HOOK) { + if (mode == MODE_FULL) { + if (fr_hint_status == VDEC_HINTED && !is_reset) + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_FR_END_HINT, + NULL); + fr_hint_status = VDEC_NO_NEED_HINT; + } + + vf_unreg_provider(&vh264_vf_prov); + stat &= ~STAT_VF_HOOK; + } + + if (stat & STAT_MC_LOAD) { + if (mc_cpu_addr != NULL) { + dma_free_coherent(amports_get_dma_device(), + MC_TOTAL_SIZE, mc_cpu_addr, + mc_dma_handle); + mc_cpu_addr = NULL; + } + } + if (sei_data_buffer != NULL) { + dma_free_coherent( + amports_get_dma_device(), + USER_DATA_RUND_SIZE, + sei_data_buffer, + sei_data_buffer_phys); + sei_data_buffer = NULL; + sei_data_buffer_phys = 0; + } + amvdec_disable(); + if (mm_blk_handle) { + decoder_bmmu_box_free(mm_blk_handle); + mm_blk_handle = NULL; + } + memset(&fense_buffer_spec, 0, sizeof(fense_buffer_spec)); + memset(&buffer_spec, 0, sizeof(buffer_spec)); + return 0; +} + +static void error_do_work(struct work_struct *work) +{ + mutex_lock(&vh264_mutex); + + /* + * we need to lock vh264_stop/vh264_init. + * because we will call amvdec_h264_remove on this step; + * then we may call more than once on + * free_irq/deltimer/..and some other. + */ + if (atomic_read(&vh264_active)) { + amvdec_stop(); + do { + msleep(20); + } while (vh264_stream_switching_state != SWITCHING_STATE_OFF); + vh264_reset = 1; +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vh264_ppmgr_reset(); +#else + vf_light_unreg_provider(&vh264_vf_prov); + + vh264_local_init(); + + vf_reg_provider(&vh264_vf_prov); +#endif + msleep(30); + vh264_prot_init(); + + amvdec_start(); + vh264_reset = 0; + } + + mutex_unlock(&vh264_mutex); +} + +static void stream_switching_done(void) +{ + int state = vh264_stream_switching_state; + + WRITE_VREG(AV_SCRATCH_7, 0); + WRITE_VREG(AV_SCRATCH_8, 0); + WRITE_VREG(AV_SCRATCH_9, 0); + + if (state == SWITCHING_STATE_ON_CMD1) { + pr_info("Enter set parameter cmd1 switching_state %x.\n", + vh264_stream_switching_state); + schedule_work(&set_parameter_work); + return; + } else if (state == SWITCHING_STATE_ON_CMD1_PENDING) + return; + + vh264_stream_switching_state = SWITCHING_STATE_OFF; + + wmb(); /* Ensure fetchbuf contents visible */ + + if (state == SWITCHING_STATE_ON_CMD3) + WRITE_VREG(AV_SCRATCH_0, 0); + + pr_info("Leaving switching mode.\n"); +} + +/* construt a new frame as a copy of last frame so frame receiver can + * release all buffer resources to decoder. + */ +static void stream_switching_do(struct work_struct *work) +{ + int mb_total_num, mb_width_num, mb_height_num, i = 0; + struct vframe_s *vf = NULL; + u32 y_index, u_index, src_index, des_index, y_desindex, u_desindex; + struct canvas_s csy, csu, cyd; + unsigned long flags; + bool delay = true; + + if (!atomic_read(&vh264_active)) + return; + + if (vh264_stream_switching_state == SWITCHING_STATE_OFF) + return; + + spin_lock_irqsave(&prepare_lock, flags); + + block_display_q = true; + + spin_unlock_irqrestore(&prepare_lock, flags); + + mb_total_num = mb_total; + mb_width_num = mb_width; + mb_height_num = mb_height; + + while (is_4k || kfifo_len(&delay_display_q) > 2) { + if (kfifo_get(&delay_display_q, &vf)) { + kfifo_put(&display_q, + (const struct vframe_s *)vf); + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL); + } else + break; + } + + if (!kfifo_get(&delay_display_q, &vf)) { + vf = p_last_vf; + delay = false; + } + + while (vf) { + int buffer_index; + + buffer_index = vf->index & 0xff; + + /* construct a clone of the frame from last frame */ + +#if 0 + + pr_info("src yaddr[0x%x] index[%d] width[%d] heigth[%d]\n", + buffer_spec[buffer_index].y_addr, + buffer_spec[buffer_index].y_canvas_index, + buffer_spec[buffer_index].y_canvas_width, + buffer_spec[buffer_index].y_canvas_height); + + pr_info("src uaddr[0x%x] index[%d] width[%d] heigth[%d]\n", + buffer_spec[buffer_index].u_addr, + buffer_spec[buffer_index].u_canvas_index, + buffer_spec[buffer_index].u_canvas_width, + buffer_spec[buffer_index].u_canvas_height); +#endif + if (EN_SWITCH_FENCE()) { + y_index = buffer_spec[buffer_index].y_canvas_index; + u_index = buffer_spec[buffer_index].u_canvas_index; + + canvas_read(y_index, &csy); + canvas_read(u_index, &csu); + + canvas_config(fense_buffer_spec[i].y_canvas_index, + fense_buffer_spec[i].phy_addr, + mb_width_num << 4, mb_height_num << 4, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + canvas_config(fense_buffer_spec[i].u_canvas_index, + fense_buffer_spec[i].phy_addr + + (mb_total_num << 8), + mb_width_num << 4, mb_height_num << 3, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + + y_desindex = fense_buffer_spec[i].y_canvas_index; + u_desindex = fense_buffer_spec[i].u_canvas_index; + + canvas_read(y_desindex, &cyd); + + src_index = ((y_index & 0xff) | + ((u_index << 8) & 0x0000ff00)); + des_index = ((y_desindex & 0xff) | + ((u_desindex << 8) & 0x0000ff00)); + + ge2d_canvas_dup(&csy, &csu, &cyd, + GE2D_FORMAT_M24_NV21, + src_index, + des_index); + } + vf->mem_handle = decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + FENSE_BUFFER_IDX(i)); + fense_vf[i] = *vf; + fense_vf[i].index = -1; + + if (EN_SWITCH_FENCE()) + fense_vf[i].canvas0Addr = + spec2canvas(&fense_buffer_spec[i]); + else + fense_vf[i].flag |= VFRAME_FLAG_SWITCHING_FENSE; + + /* send clone to receiver */ + kfifo_put(&display_q, + (const struct vframe_s *)&fense_vf[i]); + + /* early recycle frames for last session */ + if (delay) + vh264_vf_put(vf, NULL); + + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL); + + i++; + + if (!kfifo_get(&delay_display_q, &vf)) + break; + } + + block_display_q = false; + + pr_info("Switching fense frame post\n"); +} + +static int amvdec_h264_probe(struct platform_device *pdev) +{ + struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; + + mutex_lock(&vh264_mutex); + + if (pdata == NULL) { + pr_info("\namvdec_h264 memory resource undefined.\n"); + mutex_unlock(&vh264_mutex); + return -EFAULT; + } + tvp_flag = vdec_secure(pdata) ? CODEC_MM_FLAGS_TVP : 0; + if (pdata->sys_info) + vh264_amstream_dec_info = *pdata->sys_info; + if (sei_data_buffer == NULL) { + sei_data_buffer = + dma_alloc_coherent(amports_get_dma_device(), + USER_DATA_RUND_SIZE, + &sei_data_buffer_phys, GFP_KERNEL); + if (!sei_data_buffer) { + pr_info("%s: Can not allocate sei_data_buffer\n", + __func__); + mutex_unlock(&vh264_mutex); + return -ENOMEM; + } + /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n", + * sei_data_buffer, sei_data_buffer_phys, + * (u32)sei_data_buffer_remap); + */ + } + pdata->dec_status = vh264_dec_status; + pdata->set_trickmode = vh264_set_trickmode; + pdata->set_isreset = vh264_set_isreset; + is_reset = 0; + + if (vh264_init() < 0) { + pr_info("\namvdec_h264 init failed.\n"); + kfree(gvs); + gvs = NULL; + mutex_unlock(&vh264_mutex); + return -ENODEV; + } + + INIT_WORK(&error_wd_work, error_do_work); + INIT_WORK(&stream_switching_work, stream_switching_do); + INIT_WORK(&set_parameter_work, vh264_set_params); + INIT_WORK(¬ify_work, vh264_notify_work); + INIT_WORK(&set_clk_work, vh264_set_clk); + INIT_WORK(&userdata_push_work, userdata_push_do_work); + + atomic_set(&vh264_active, 1); + + mutex_unlock(&vh264_mutex); + + return 0; +} + +static int amvdec_h264_remove(struct platform_device *pdev) +{ + atomic_set(&vh264_active, 0); + cancel_work_sync(&set_parameter_work); + cancel_work_sync(&error_wd_work); + cancel_work_sync(&stream_switching_work); + cancel_work_sync(¬ify_work); + cancel_work_sync(&set_clk_work); + cancel_work_sync(&userdata_push_work); + + mutex_lock(&vh264_mutex); + vh264_stop(MODE_FULL); + vdec_source_changed(VFORMAT_H264, 0, 0, 0); + atomic_set(&vh264_active, 0); +#ifdef DEBUG_PTS + pr_info + ("pts missed %ld, pts hit %ld, pts_outside %d, duration %d, ", + pts_missed, pts_hit, pts_outside, frame_dur); + pr_info("sync_outside %d, use_idr_framerate %d\n", + sync_outside, use_idr_framerate); +#endif + kfree(gvs); + gvs = NULL; + mutex_unlock(&vh264_mutex); + return 0; +} + +/****************************************/ + +static struct platform_driver amvdec_h264_driver = { + .probe = amvdec_h264_probe, + .remove = amvdec_h264_remove, +#ifdef CONFIG_PM + .suspend = amvdec_suspend, + .resume = amvdec_resume, +#endif + .driver = { + .name = DRIVER_NAME, + } +}; + +static struct codec_profile_t amvdec_h264_profile = { + .name = "h264", + .profile = "" +}; + + +static struct mconfig h264_configs[] = { + MC_PU32("stat", &stat), + MC_PU32("error_recovery_mode", &error_recovery_mode), + MC_PU32("sync_outside", &sync_outside), + MC_PU32("dec_control", &dec_control), + MC_PU32("fatal_error_reset", &fatal_error_reset), + MC_PU32("max_refer_buf", &max_refer_buf), + MC_PU32("ucode_type", &ucode_type), + MC_PU32("debugfirmware", &debugfirmware), + MC_PU32("fixed_frame_rate_flag", &fixed_frame_rate_flag), + MC_PU32("decoder_debug_flag", &decoder_debug_flag), + MC_PU32("dpb_size_adj", &dpb_size_adj), + MC_PU32("decoder_force_reset", &decoder_force_reset), + MC_PU32("no_idr_error_max", &no_idr_error_max), + MC_PU32("enable_switch_fense", &enable_switch_fense), +}; +static struct mconfig_node h264_node; + + +static int __init amvdec_h264_driver_init_module(void) +{ + pr_debug("amvdec_h264 module init\n"); + + ge2d_videoh264task_init(); + + if (platform_driver_register(&amvdec_h264_driver)) { + pr_err("failed to register amvdec_h264 driver\n"); + return -ENODEV; + } + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB + && (codec_mm_get_total_size() > 80 * SZ_1M)) { + amvdec_h264_profile.profile = "4k"; + } + vcodec_profile_register(&amvdec_h264_profile); + INIT_REG_NODE_CONFIGS("media.decoder", &h264_node, + "h264", h264_configs, CONFIG_FOR_RW); + return 0; +} + +static void __exit amvdec_h264_driver_remove_module(void) +{ + pr_debug("amvdec_h264 module remove.\n"); + + platform_driver_unregister(&amvdec_h264_driver); + + ge2d_videoh264task_release(); +} + +/****************************************/ + +module_param(stat, uint, 0664); +MODULE_PARM_DESC(stat, "\n amvdec_h264 stat\n"); +module_param(error_recovery_mode, uint, 0664); +MODULE_PARM_DESC(error_recovery_mode, "\n amvdec_h264 error_recovery_mode\n"); +module_param(sync_outside, uint, 0664); +MODULE_PARM_DESC(sync_outside, "\n amvdec_h264 sync_outside\n"); +module_param(dec_control, uint, 0664); +MODULE_PARM_DESC(dec_control, "\n amvdec_h264 decoder control\n"); +module_param(fatal_error_reset, uint, 0664); +MODULE_PARM_DESC(fatal_error_reset, + "\n amvdec_h264 decoder reset when fatal error happens\n"); +module_param(max_refer_buf, uint, 0664); +MODULE_PARM_DESC(max_refer_buf, + "\n amvdec_h264 dec buffering or not for reference frame\n"); +module_param(ucode_type, uint, 0664); +MODULE_PARM_DESC(ucode_type, + "\n amvdec_h264 dec buffering or not for reference frame\n"); +module_param(debugfirmware, uint, 0664); +MODULE_PARM_DESC(debugfirmware, "\n amvdec_h264 debug load firmware\n"); +module_param(fixed_frame_rate_flag, uint, 0664); +MODULE_PARM_DESC(fixed_frame_rate_flag, + "\n amvdec_h264 fixed_frame_rate_flag\n"); +module_param(decoder_debug_flag, uint, 0664); +MODULE_PARM_DESC(decoder_debug_flag, + "\n amvdec_h264 decoder_debug_flag\n"); + +module_param(dpb_size_adj, uint, 0664); +MODULE_PARM_DESC(dpb_size_adj, + "\n amvdec_h264 dpb_size_adj\n"); + + +module_param(decoder_force_reset, uint, 0664); +MODULE_PARM_DESC(decoder_force_reset, + "\n amvdec_h264 decoder force reset\n"); +module_param(no_idr_error_max, uint, 0664); +MODULE_PARM_DESC(no_idr_error_max, + "\n print no_idr_error_max\n"); +module_param(enable_switch_fense, uint, 0664); +MODULE_PARM_DESC(enable_switch_fense, + "\n enable switch fense\n"); + +#ifdef SUPPORT_BAD_MACRO_BLOCK_REDUNDANCY +module_param(bad_block_scale, uint, 0664); +MODULE_PARM_DESC(bad_block_scale, + "\n print bad_block_scale\n"); +#endif + +module_init(amvdec_h264_driver_init_module); +module_exit(amvdec_h264_driver_remove_module); + +MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Chen Zhang "); diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/h264/vh264.h b/drivers/amlogic/media_modules/frame_provider/decoder/h264/vh264.h new file mode 100644 index 000000000000..6c8e4ad684a6 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/h264/vh264.h @@ -0,0 +1,27 @@ +/* + * drivers/amlogic/media/frame_provider/decoder/h264/vh264.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef VH264_H +#define VH264_H + +extern int query_video_status(int type, int *value); + +/* extern s32 vh264_init(void); */ + +extern s32 vh264_release(void); + +#endif /* VMPEG4_H */ diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/h264/vh264_4k2k.c b/drivers/amlogic/media_modules/frame_provider/decoder/h264/vh264_4k2k.c new file mode 100644 index 000000000000..9363bcf9c377 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/h264/vh264_4k2k.c @@ -0,0 +1,1806 @@ +/* + * drivers/amlogic/amports/vh264_4k2k.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "../utils/firmware.h" + +#define MEM_NAME "codec_264_4k" + +/* #include */ +#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ + +#include +#endif + +#include +#include "../../../stream_input/amports/amports_priv.h" +#include "../utils/vdec.h" +#include "../utils/amvdec.h" +#include "../utils/decoder_mmu_box.h" +#include "../utils/decoder_bmmu_box.h" +#include +#include + +#if 0 /* MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6TVD */ +#define DOUBLE_WRITE +#endif + +#define DRIVER_NAME "amvdec_h264_4k2k" +#define MODULE_NAME "amvdec_h264_4k2k" + +#define PUT_INTERVAL (HZ/100) +#define ERROR_RESET_COUNT 500 +#define DECODE_BUFFER_NUM_MAX 32 +#define DISPLAY_BUFFER_NUM 6 +#define MAX_BMMU_BUFFER_NUM (DECODE_BUFFER_NUM_MAX + DISPLAY_BUFFER_NUM) +#define VF_BUFFER_IDX(n) (2 + n) +#define DECODER_WORK_SPACE_SIZE 0x800000 + + +#if 1 /* MESON_CPU_TYPE == MESON_CPU_TYPE_MESONG9TV */ +#define H264_4K2K_SINGLE_CORE 1 +#else +#define H264_4K2K_SINGLE_CORE IS_MESON_M8M2_CPU +#endif + +#define SLICE_TYPE_I 2 + +static int vh264_4k2k_vf_states(struct vframe_states *states, void *); +static struct vframe_s *vh264_4k2k_vf_peek(void *); +static struct vframe_s *vh264_4k2k_vf_get(void *); +static void vh264_4k2k_vf_put(struct vframe_s *, void *); +static int vh264_4k2k_event_cb(int type, void *data, void *private_data); + +static void vh264_4k2k_prot_init(void); +static int vh264_4k2k_local_init(void); +static void vh264_4k2k_put_timer_func(unsigned long arg); + +static const char vh264_4k2k_dec_id[] = "vh264_4k2k-dev"; +static const char vh264_4k2k_dec_id2[] = "vh264_4k2k-vdec2-dev"; + +#define PROVIDER_NAME "decoder.h264_4k2k" + +static const struct vframe_operations_s vh264_4k2k_vf_provider = { + .peek = vh264_4k2k_vf_peek, + .get = vh264_4k2k_vf_get, + .put = vh264_4k2k_vf_put, + .event_cb = vh264_4k2k_event_cb, + .vf_states = vh264_4k2k_vf_states, +}; +static void *mm_blk_handle; +static struct vframe_provider_s vh264_4k2k_vf_prov; + +static u32 mb_width_old, mb_height_old; +static u32 frame_width, frame_height, frame_dur, frame_ar; +static u32 saved_resolution; +static struct timer_list recycle_timer; +static u32 stat; +static u32 error_watchdog_count; +static uint error_recovery_mode; +static u32 sync_outside; +static u32 vh264_4k2k_rotation; +static u32 first_i_received; +static struct vframe_s *p_last_vf; +static struct work_struct set_clk_work; + +#ifdef DEBUG_PTS +static unsigned long pts_missed, pts_hit; +#endif + +static struct dec_sysinfo vh264_4k2k_amstream_dec_info; +static dma_addr_t mc_dma_handle; +static void *mc_cpu_addr; + +#define AMVDEC_H264_4K2K_CANVAS_INDEX 0x80 +#define AMVDEC_H264_4K2K_CANVAS_MAX 0xc6 +static DEFINE_SPINLOCK(lock); +static int fatal_error; + +static atomic_t vh264_4k2k_active = ATOMIC_INIT(0); + +static DEFINE_MUTEX(vh264_4k2k_mutex); + +static void (*probe_callback)(void); +static void (*remove_callback)(void); +static struct device *cma_dev; + +/* bit[3:0] command : */ +/* 0 - command finished */ +/* (DATA0 - {level_idc_mmco, max_reference_frame_num, width, height} */ +/* 1 - alloc view_0 display_buffer and reference_data_area */ +/* 2 - alloc view_1 display_buffer and reference_data_area */ +#define MAILBOX_COMMAND AV_SCRATCH_0 +#define MAILBOX_DATA_0 AV_SCRATCH_1 +#define MAILBOX_DATA_1 AV_SCRATCH_2 +#define MAILBOX_DATA_2 AV_SCRATCH_3 +#define MAILBOX_DATA_3 AV_SCRATCH_4 +#define MAILBOX_DATA_4 AV_SCRATCH_5 +#define CANVAS_START AV_SCRATCH_6 +#define BUFFER_RECYCLE AV_SCRATCH_7 +#define PICTURE_COUNT AV_SCRATCH_9 +#define DECODE_STATUS AV_SCRATCH_A +#define SPS_STATUS AV_SCRATCH_B +#define PPS_STATUS AV_SCRATCH_C +#define MS_ID AV_SCRATCH_D +#define WORKSPACE_START AV_SCRATCH_E +#define DECODED_PIC_NUM AV_SCRATCH_F +#define DECODE_ERROR_CNT AV_SCRATCH_G +#define CURRENT_UCODE AV_SCRATCH_H +/* bit[15:9]-SPS, bit[8:0]-PPS */ +#define CURRENT_SPS_PPS AV_SCRATCH_I +#define DECODE_SKIP_PICTURE AV_SCRATCH_J +#define DECODE_MODE AV_SCRATCH_K +#define RESERVED_REG_L AV_SCRATCH_L +#define REF_START_VIEW_0 AV_SCRATCH_M +#define REF_START_VIEW_1 AV_SCRATCH_N + +#define VDEC2_MAILBOX_COMMAND VDEC2_AV_SCRATCH_0 +#define VDEC2_MAILBOX_DATA_0 VDEC2_AV_SCRATCH_1 +#define VDEC2_MAILBOX_DATA_1 VDEC2_AV_SCRATCH_2 +#define VDEC2_MAILBOX_DATA_2 VDEC2_AV_SCRATCH_3 +#define VDEC2_MAILBOX_DATA_3 VDEC2_AV_SCRATCH_4 +#define VDEC2_MAILBOX_DATA_4 VDEC2_AV_SCRATCH_5 +#define VDEC2_CANVAS_START VDEC2_AV_SCRATCH_6 +#define VDEC2_BUFFER_RECYCLE VDEC2_AV_SCRATCH_7 +#define VDEC2_PICTURE_COUNT VDEC2_AV_SCRATCH_9 +#define VDEC2_DECODE_STATUS VDEC2_AV_SCRATCH_A +#define VDEC2_SPS_STATUS VDEC2_AV_SCRATCH_B +#define VDEC2_PPS_STATUS VDEC2_AV_SCRATCH_C +#define VDEC2_MS_ID VDEC2_AV_SCRATCH_D +#define VDEC2_WORKSPACE_START VDEC2_AV_SCRATCH_E +#define VDEC2_DECODED_PIC_NUM VDEC2_AV_SCRATCH_F +#define VDEC2_DECODE_ERROR_CNT VDEC2_AV_SCRATCH_G +#define VDEC2_CURRENT_UCODE VDEC2_AV_SCRATCH_H +/* bit[15:9]-SPS, bit[8:0]-PPS */ +#define VDEC2_CURRENT_SPS_PPS VDEC2_AV_SCRATCH_I +#define VDEC2_DECODE_SKIP_PICTURE VDEC2_AV_SCRATCH_J +#define VDEC2_RESERVED_REG_K VDEC2_AV_SCRATCH_K +#define VDEC2_RESERVED_REG_L VDEC2_AV_SCRATCH_L +#define VDEC2_REF_START_VIEW_0 VDEC2_AV_SCRATCH_M +#define VDEC2_REF_START_VIEW_1 VDEC2_AV_SCRATCH_N + +/******************************************** + * DECODE_STATUS Define + ******************************************* + */ +#define DECODE_IDLE 0 +#define DECODE_START_HEADER 1 +#define DECODE_HEADER 2 +#define DECODE_START_MMCO 3 +#define DECODE_MMCO 4 +#define DECODE_START_SLICE 5 +#define DECODE_SLICE 6 +#define DECODE_WAIT_BUFFER 7 + +/******************************************** + * Dual Core Communication + ******************************************** + */ +#define FATAL_ERROR DOS_SCRATCH16 +#define PRE_MASTER_UPDATE_TIMES DOS_SCRATCH20 +/* bit[31] - REQUEST */ +/* bit[30:0] - MASTER_UPDATE_TIMES */ +#define SLAVE_WAIT_DPB_UPDATE DOS_SCRATCH21 +/* [15:8] - current_ref, [7:0] current_dpb (0x80 means no buffer found) */ +#define SLAVE_REF_DPB DOS_SCRATCH22 +#define SAVE_MVC_ENTENSION_0 DOS_SCRATCH23 +#define SAVE_I_POC DOS_SCRATCH24 +/* bit[31:30] - core_status 0-idle, 1-mmco, 2-decoding, 3-finished */ +/* bit[29:0] - core_pic_count */ +#define CORE_STATUS_M DOS_SCRATCH25 +#define CORE_STATUS_S DOS_SCRATCH26 +#define SAVE_ref_status_view_0 DOS_SCRATCH27 +#define SAVE_ref_status_view_1 DOS_SCRATCH28 +#define ALLOC_INFO_0 DOS_SCRATCH29 +#define ALLOC_INFO_1 DOS_SCRATCH30 + +/******************************************** + * Mailbox command + ********************************************/ +#define CMD_FINISHED 0 +#define CMD_ALLOC_VIEW 1 +#define CMD_FRAME_DISPLAY 3 +#define CMD_DEBUG 10 + +#define MC_TOTAL_SIZE (28*SZ_1K) +#define MC_SWAP_SIZE (4*SZ_1K) + +static unsigned long work_space_adr, ref_start_addr; +static unsigned long reserved_buffer; + + +#define video_domain_addr(adr) (adr&0x7fffffff) + + +struct buffer_spec_s { + unsigned int y_addr; + unsigned int uv_addr; +#ifdef DOUBLE_WRITE + unsigned int y_dw_addr; + unsigned int uv_dw_addr; +#endif + + int y_canvas_index; + int uv_canvas_index; +#ifdef DOUBLE_WRITE + int y_dw_canvas_index; + int uv_dw_canvas_index; +#endif + + struct page *alloc_pages; + unsigned long phy_addr; + int alloc_count; +}; + +static struct buffer_spec_s buffer_spec[MAX_BMMU_BUFFER_NUM]; + +#ifdef DOUBLE_WRITE +#define spec2canvas(x) \ + (((x)->uv_dw_canvas_index << 16) | \ + ((x)->uv_dw_canvas_index << 8) | \ + ((x)->y_dw_canvas_index << 0)) +#else +#define spec2canvas(x) \ + (((x)->uv_canvas_index << 16) | \ + ((x)->uv_canvas_index << 8) | \ + ((x)->y_canvas_index << 0)) +#endif + +#define VF_POOL_SIZE 32 + +static DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE); +static DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE); +static DECLARE_KFIFO(recycle_q, struct vframe_s *, VF_POOL_SIZE); + +static s32 vfbuf_use[DECODE_BUFFER_NUM_MAX]; +static struct vframe_s vfpool[VF_POOL_SIZE]; + +static struct work_struct alloc_work; +static struct vdec_info *gvs; + +static void set_frame_info(struct vframe_s *vf) +{ + unsigned int ar; + +#ifdef DOUBLE_WRITE + vf->width = frame_width / 2; + vf->height = frame_height / 2; +#else + vf->width = frame_width; + vf->height = frame_height; +#endif + vf->duration = frame_dur; + vf->duration_pulldown = 0; + vf->flag = 0; + + ar = min_t(u32, frame_ar, DISP_RATIO_ASPECT_RATIO_MAX); + vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT); + vf->orientation = vh264_4k2k_rotation; + +} + +static int vh264_4k2k_vf_states(struct vframe_states *states, void *op_arg) +{ + unsigned long flags; + + spin_lock_irqsave(&lock, flags); + + states->vf_pool_size = VF_POOL_SIZE; + states->buf_free_num = kfifo_len(&newframe_q); + states->buf_avail_num = kfifo_len(&display_q); + states->buf_recycle_num = kfifo_len(&recycle_q); + + spin_unlock_irqrestore(&lock, flags); + return 0; +} + +static struct vframe_s *vh264_4k2k_vf_peek(void *op_arg) +{ + struct vframe_s *vf; + + if (kfifo_peek(&display_q, &vf)) + return vf; + + return NULL; +} + +static struct vframe_s *vh264_4k2k_vf_get(void *op_arg) +{ + struct vframe_s *vf; + + if (kfifo_get(&display_q, &vf)) + return vf; + + return NULL; +} + +static void vh264_4k2k_vf_put(struct vframe_s *vf, void *op_arg) +{ + kfifo_put(&recycle_q, (const struct vframe_s *)vf); +} + +static int vh264_4k2k_event_cb(int type, void *data, void *private_data) +{ + if (type & VFRAME_EVENT_RECEIVER_RESET) { + unsigned long flags; + + amvdec_stop(); + + if (!H264_4K2K_SINGLE_CORE) + amvdec2_stop(); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_light_unreg_provider(&vh264_4k2k_vf_prov); +#endif + spin_lock_irqsave(&lock, flags); + vh264_4k2k_local_init(); + vh264_4k2k_prot_init(); + spin_unlock_irqrestore(&lock, flags); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_reg_provider(&vh264_4k2k_vf_prov); +#endif + amvdec_start(); + + if (!H264_4K2K_SINGLE_CORE) + amvdec2_start(); + } + + return 0; +} + +static int init_canvas(int refbuf_size, long dpb_size, int dpb_number, + int mb_width, int mb_height, + struct buffer_spec_s *buffer_spec) +{ + unsigned long addr; + int i, j, ret = -1; + int mb_total; + int canvas_addr = ANC0_CANVAS_ADDR; + int vdec2_canvas_addr = VDEC2_ANC0_CANVAS_ADDR; + int index = AMVDEC_H264_4K2K_CANVAS_INDEX; + + mb_total = mb_width * mb_height; + mutex_lock(&vh264_4k2k_mutex); + + for (j = 0; j < (dpb_number + 1); j++) { + int page_count; + if (j == 0) { + ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, 1, + refbuf_size, DRIVER_NAME, &ref_start_addr); + if (ret < 0) { + mutex_unlock(&vh264_4k2k_mutex); + return ret; + } + continue; + } + + WRITE_VREG(canvas_addr++, index | ((index + 1) << 8) | + ((index + 1) << 16)); + if (!H264_4K2K_SINGLE_CORE) { + WRITE_VREG(vdec2_canvas_addr++, + index | ((index + 1) << 8) | + ((index + 1) << 16)); + } + + i = j - 1; +#ifdef DOUBLE_WRITE + page_count = + PAGE_ALIGN((mb_total << 8) + (mb_total << 7) + + (mb_total << 6) + (mb_total << 5)) / PAGE_SIZE; +#else + page_count = + PAGE_ALIGN((mb_total << 8) + (mb_total << 7)) / PAGE_SIZE; +#endif + + ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, + VF_BUFFER_IDX(i), page_count << PAGE_SHIFT, + DRIVER_NAME, &buffer_spec[i].phy_addr); + + if (ret < 0) { + buffer_spec[i].alloc_count = 0; + mutex_unlock(&vh264_4k2k_mutex); + return ret; + } + addr = buffer_spec[i].phy_addr; + buffer_spec[i].alloc_count = page_count; + buffer_spec[i].y_addr = addr; + buffer_spec[i].y_canvas_index = index; + canvas_config(index, + addr, + mb_width << 4, + mb_height << 4, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); + + addr += mb_total << 8; + index++; + + buffer_spec[i].uv_addr = addr; + buffer_spec[i].uv_canvas_index = index; + canvas_config(index, + addr, + mb_width << 4, + mb_height << 3, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); + + addr += mb_total << 7; + index++; + +#ifdef DOUBLE_WRITE + buffer_spec[i].y_dw_addr = addr; + buffer_spec[i].y_dw_canvas_index = index; + canvas_config(index, + addr, + mb_width << 3, + mb_height << 3, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); + + addr += mb_total << 6; + index++; + + buffer_spec[i].uv_dw_addr = addr; + buffer_spec[i].uv_dw_canvas_index = index; + canvas_config(index, + addr, + mb_width << 3, + mb_height << 2, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); + + index++; +#endif + } + + mutex_unlock(&vh264_4k2k_mutex); + + pr_info + ("H264 4k2k decoder canvas allocation successful, "); + + return 0; +} + +static int get_max_dec_frame_buf_size(int level_idc, + int max_reference_frame_num, int mb_width, + int mb_height) +{ + int pic_size = mb_width * mb_height * 384; + + int size = 0; + + switch (level_idc) { + case 9: + size = 152064; + break; + case 10: + size = 152064; + break; + case 11: + size = 345600; + break; + case 12: + size = 912384; + break; + case 13: + size = 912384; + break; + case 20: + size = 912384; + break; + case 21: + size = 1824768; + break; + case 22: + size = 3110400; + break; + case 30: + size = 3110400; + break; + case 31: + size = 6912000; + break; + case 32: + size = 7864320; + break; + case 40: + size = 12582912; + break; + case 41: + size = 12582912; + break; + case 42: + size = 13369344; + break; + case 50: + size = 42393600; + break; + case 51: + case 52: + default: + size = 70778880; + break; + } + + size /= pic_size; + size = size + 1; /* need one more buffer */ + + if (max_reference_frame_num > size) + size = max_reference_frame_num; + + if (size > DECODE_BUFFER_NUM_MAX) + size = DECODE_BUFFER_NUM_MAX; + + return size; +} + +static void do_alloc_work(struct work_struct *work) +{ + int level_idc, max_reference_frame_num, mb_width, mb_height, + frame_mbs_only_flag; + int dpb_size, ref_size, refbuf_size; + int max_dec_frame_buffering, + total_dec_frame_buffering; + unsigned int chroma444; + unsigned int crop_infor, crop_bottom, crop_right; + int ret = READ_VREG(MAILBOX_COMMAND); + + + ret = READ_VREG(MAILBOX_DATA_0); + /* MAILBOX_DATA_1 : + * bit15 : frame_mbs_only_flag + * bit 0-7 : chroma_format_idc + * MAILBOX_DATA_2: + * bit31-16: (left << 8 | right ) << 1 + * bit15-0 : (top << 8 | bottom ) << (2 - frame_mbs_only_flag) + */ + frame_mbs_only_flag = READ_VREG(MAILBOX_DATA_1); + crop_infor = READ_VREG(MAILBOX_DATA_2); + level_idc = (ret >> 24) & 0xff; + max_reference_frame_num = (ret >> 16) & 0xff; + mb_width = (ret >> 8) & 0xff; + if (mb_width == 0) + mb_width = 256; + mb_height = (ret >> 0) & 0xff; + max_dec_frame_buffering = + get_max_dec_frame_buf_size(level_idc, max_reference_frame_num, + mb_width, mb_height); + total_dec_frame_buffering = + max_dec_frame_buffering + DISPLAY_BUFFER_NUM; + + chroma444 = ((frame_mbs_only_flag&0xffff) == 3) ? 1 : 0; + frame_mbs_only_flag = (frame_mbs_only_flag >> 16) & 0x01; + crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag); + crop_right = ((crop_infor >> 16) & 0xff) >> 1; + pr_info("crop_right = 0x%x crop_bottom = 0x%x chroma_format_idc = 0x%x\n", + crop_right, crop_bottom, chroma444); + + if ((frame_width == 0) || (frame_height == 0) || crop_infor || + mb_width != mb_width_old || + mb_height != mb_height_old) { + frame_width = mb_width << 4; + frame_height = mb_height << 4; + mb_width_old = mb_width; + mb_height_old = mb_height; + if (frame_mbs_only_flag) { + frame_height -= (2 >> chroma444) * + min(crop_bottom, + (unsigned int)((8 << chroma444) - 1)); + frame_width -= (2 >> chroma444) * + min(crop_right, + (unsigned int)((8 << chroma444) - 1)); + } else { + frame_height -= (4 >> chroma444) * + min(crop_bottom, + (unsigned int)((8 << chroma444) - 1)); + frame_width -= (4 >> chroma444) * + min(crop_right, + (unsigned int)((8 << chroma444) - 1)); + } + pr_info("frame_mbs_only_flag %d, crop_bottom %d frame_height %d, mb_height %d crop_right %d, frame_width %d, mb_width %d\n", + frame_mbs_only_flag, crop_bottom, frame_height, + mb_height, crop_right, frame_width, mb_height); + } + + mb_width = (mb_width + 3) & 0xfffffffc; + mb_height = (mb_height + 3) & 0xfffffffc; + + dpb_size = mb_width * mb_height * 384; + ref_size = mb_width * mb_height * 96; + refbuf_size = ref_size * (max_reference_frame_num + 1) * 2; + + + pr_info("mb_width=%d, mb_height=%d\n", + mb_width, mb_height); + + ret = init_canvas(refbuf_size, dpb_size, + total_dec_frame_buffering, mb_width, mb_height, + buffer_spec); + + if (ret == -1) { + pr_info(" Un-expected memory alloc problem\n"); + return; + } + + if (frame_width == 0) + frame_width = mb_width << 4; + if (frame_height == 0) + frame_height = mb_height << 4; + + WRITE_VREG(REF_START_VIEW_0, video_domain_addr(ref_start_addr)); + if (!H264_4K2K_SINGLE_CORE) { + WRITE_VREG(VDEC2_REF_START_VIEW_0, + video_domain_addr(ref_start_addr)); + } + + WRITE_VREG(MAILBOX_DATA_0, + (max_dec_frame_buffering << 8) | + (total_dec_frame_buffering << 0)); + WRITE_VREG(MAILBOX_DATA_1, ref_size); + WRITE_VREG(MAILBOX_COMMAND, CMD_FINISHED); + + /* ///////////// FAKE FIRST PIC */ + +} + +static irqreturn_t vh264_4k2k_isr(int irq, void *dev_id) +{ + int drop_status, display_buff_id, display_POC, slice_type, error; + unsigned int stream_offset; + struct vframe_s *vf = NULL; + int ret = READ_VREG(MAILBOX_COMMAND); + + switch (ret & 0xff) { + case CMD_ALLOC_VIEW: + schedule_work(&alloc_work); + break; + + case CMD_FRAME_DISPLAY: + ret >>= 8; + display_buff_id = (ret >> 0) & 0x3f; + drop_status = (ret >> 8) & 0x1; + slice_type = (ret >> 9) & 0x7; + error = (ret >> 12) & 0x1; + display_POC = READ_VREG(MAILBOX_DATA_0); + stream_offset = READ_VREG(MAILBOX_DATA_1); + + smp_rmb();/* rmb smp */ + + WRITE_VREG(MAILBOX_COMMAND, CMD_FINISHED); + + if (kfifo_get(&newframe_q, &vf) == 0) { + pr_info("fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + + if (vf) { + vfbuf_use[display_buff_id]++; + + vf->pts = 0; + vf->pts_us64 = 0; + + if ((!sync_outside) + || (sync_outside && + (slice_type == SLICE_TYPE_I))) { + ret = pts_lookup_offset_us64(PTS_TYPE_VIDEO, + stream_offset, + &vf->pts, + 0, + &vf->pts_us64); + if (ret != 0) + pr_debug(" vpts lookup failed\n"); + } +#ifdef H264_4K2K_SINGLE_CORE + if (READ_VREG(DECODE_MODE) & 1) { + /* for I only mode, ignore the PTS information + * and only uses 10fps for each + * I frame decoded + */ + if (p_last_vf) { + vf->pts = 0; + vf->pts_us64 = 0; + } + frame_dur = 96000 / 10; + } +#endif + vf->signal_type = 0; + vf->index = display_buff_id; + vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD; + vf->type |= VIDTYPE_VIU_NV21; + vf->canvas0Addr = vf->canvas1Addr = + spec2canvas(&buffer_spec[display_buff_id]); + set_frame_info(vf); + + if (error) + gvs->drop_frame_count++; + + gvs->frame_dur = frame_dur; + vdec_count_info(gvs, error, stream_offset); + + if (((error_recovery_mode & 2) && error) + || (!first_i_received + && (slice_type != SLICE_TYPE_I))) { + kfifo_put(&recycle_q, + (const struct vframe_s *)vf); + } else { + p_last_vf = vf; + first_i_received = 1; + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + VF_BUFFER_IDX(display_buff_id)); + kfifo_put(&display_q, + (const struct vframe_s *)vf); + + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + } + } + break; + + case CMD_DEBUG: + pr_info("M: core_status 0x%08x 0x%08x; ", + READ_VREG(CORE_STATUS_M), READ_VREG(CORE_STATUS_S)); + switch (READ_VREG(MAILBOX_DATA_0)) { + case 1: + pr_info("H264_BUFFER_INFO_INDEX = 0x%x\n", + READ_VREG(MAILBOX_DATA_1)); + WRITE_VREG(MAILBOX_COMMAND, CMD_FINISHED); + break; + case 2: + pr_info("H264_BUFFER_INFO_DATA = 0x%x\n", + READ_VREG(MAILBOX_DATA_1)); + WRITE_VREG(MAILBOX_COMMAND, CMD_FINISHED); + break; + case 3: + pr_info("REC_CANVAS_ADDR = 0x%x\n", + READ_VREG(MAILBOX_DATA_1)); + WRITE_VREG(MAILBOX_COMMAND, CMD_FINISHED); + break; + case 4: + pr_info("after DPB_MMCO\n"); + WRITE_VREG(MAILBOX_COMMAND, CMD_FINISHED); + break; + case 5: + pr_info("MBY = 0x%x, S_MBXY = 0x%x\n", + READ_VREG(MAILBOX_DATA_1), + READ_VREG(0x2c07)); + WRITE_VREG(MAILBOX_COMMAND, CMD_FINISHED); + break; + case 6: + pr_info("after FIFO_OUT_FRAME\n"); + WRITE_VREG(MAILBOX_COMMAND, CMD_FINISHED); + break; + case 7: + pr_info("after RELEASE_EXCEED_REF_BUFF\n"); + WRITE_VREG(MAILBOX_COMMAND, CMD_FINISHED); + break; + case 0x5a: + pr_info("\n"); + break; + default: + pr_info("\n"); + break; + } + break; + + default: + break; + } + + return IRQ_HANDLED; +} + +#if 1 /*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8*/ +static irqreturn_t vh264_4k2k_vdec2_isr(int irq, void *dev_id) +{ + int ret = READ_VREG(VDEC2_MAILBOX_COMMAND); + + switch (ret & 0xff) { + case CMD_DEBUG: + pr_info("S: core_status 0x%08x 0x%08x; ", + READ_VREG(CORE_STATUS_M), READ_VREG(CORE_STATUS_S)); + switch (READ_VREG(VDEC2_MAILBOX_DATA_0)) { + case 1: + pr_info("H264_BUFFER_INFO_INDEX = 0x%x\n", + READ_VREG(VDEC2_MAILBOX_DATA_1)); + WRITE_VREG(VDEC2_MAILBOX_COMMAND, CMD_FINISHED); + break; + case 2: + pr_info("H264_BUFFER_INFO_DATA = 0x%x\n", + READ_VREG(VDEC2_MAILBOX_DATA_1)); + WRITE_VREG(VDEC2_MAILBOX_COMMAND, CMD_FINISHED); + break; + case 3: + pr_info("REC_CANVAS_ADDR = 0x%x\n", + READ_VREG(VDEC2_MAILBOX_DATA_1)); + WRITE_VREG(VDEC2_MAILBOX_COMMAND, CMD_FINISHED); + break; + case 4: + pr_info("after DPB_MMCO\n"); + WRITE_VREG(VDEC2_MAILBOX_COMMAND, CMD_FINISHED); + break; + case 5: + pr_info("MBY = 0x%x, M/S_MBXY = 0x%x-0x%x\n", + READ_VREG(VDEC2_MAILBOX_DATA_1), + READ_VREG(0xc07), READ_VREG(0x2c07)); + WRITE_VREG(VDEC2_MAILBOX_COMMAND, CMD_FINISHED); + break; + case 6: + pr_info("after FIFO_OUT_FRAME\n"); + WRITE_VREG(VDEC2_MAILBOX_COMMAND, CMD_FINISHED); + break; + case 7: + pr_info("after RELEASE_EXCEED_REF_BUFF\n"); + WRITE_VREG(VDEC2_MAILBOX_COMMAND, CMD_FINISHED); + break; + case 0x5a: + pr_info("\n"); + break; + default: + pr_info("\n"); + break; + } + break; + + default: + break; + } + + return IRQ_HANDLED; +} +#endif + +static void vh264_4k2k_set_clk(struct work_struct *work) +{ + if (first_i_received &&/*do switch after first i frame ready.*/ + frame_dur > 0 && saved_resolution != + frame_width * frame_height * (96000 / frame_dur)) { + int fps = 96000 / frame_dur; + + pr_info("H264 4k2k resolution changed!!\n"); + if (vdec_source_changed(VFORMAT_H264_4K2K, + frame_width, frame_height, fps) > 0)/*changed clk ok*/ + saved_resolution = frame_width * frame_height * fps; + } +} + +static void vh264_4k2k_put_timer_func(unsigned long arg) +{ + struct timer_list *timer = (struct timer_list *)arg; + enum receviver_start_e state = RECEIVER_INACTIVE; + + if (vf_get_receiver(PROVIDER_NAME)) { + state = vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_QUREY_STATE, NULL); + if ((state == RECEIVER_STATE_NULL) + || (state == RECEIVER_STATE_NONE)) + state = RECEIVER_INACTIVE; + } else + state = RECEIVER_INACTIVE; + + /* error watchdog */ + if (((READ_VREG(VLD_MEM_VIFIFO_CONTROL) & 0x100) == 0) &&/* dec has in*/ + (state == RECEIVER_INACTIVE) && /* rec has no buf to recycle */ + (kfifo_is_empty(&display_q)) && /* no buf in display queue */ + (kfifo_is_empty(&recycle_q)) && /* no buf to recycle */ + (READ_VREG(MS_ID) & 0x100) +#ifdef CONFIG_H264_2K4K_SINGLE_CORE + && (READ_VREG(VDEC2_MS_ID) & 0x100) + +/* with both decoder + * have started decoding + */ +#endif + && first_i_received) { + if (++error_watchdog_count == ERROR_RESET_COUNT) { + /* and it lasts for a while */ + pr_info("H264 4k2k decoder fatal error watchdog.\n"); + fatal_error = DECODER_FATAL_ERROR_UNKNOWN; + } + } else + error_watchdog_count = 0; + + if (READ_VREG(FATAL_ERROR) != 0) { + pr_info("H264 4k2k decoder ucode fatal error.\n"); + fatal_error = DECODER_FATAL_ERROR_UNKNOWN; + WRITE_VREG(FATAL_ERROR, 0); + } + + while (!kfifo_is_empty(&recycle_q) && + (READ_VREG(BUFFER_RECYCLE) == 0)) { + struct vframe_s *vf; + + if (kfifo_get(&recycle_q, &vf)) { + if ((vf->index >= 0) + && (vf->index < DECODE_BUFFER_NUM_MAX) + && (--vfbuf_use[vf->index] == 0)) { + WRITE_VREG(BUFFER_RECYCLE, vf->index + 1); + vf->index = DECODE_BUFFER_NUM_MAX; + } + + kfifo_put(&newframe_q, (const struct vframe_s *)vf); + } + } + + schedule_work(&set_clk_work); + + timer->expires = jiffies + PUT_INTERVAL; + + add_timer(timer); +} + +int vh264_4k2k_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus) +{ + vstatus->frame_width = frame_width; + vstatus->frame_height = frame_height; + if (frame_dur != 0) + vstatus->frame_rate = 96000 / frame_dur; + else + vstatus->frame_rate = -1; + vstatus->error_count = 0; + vstatus->status = stat | fatal_error; + vstatus->frame_dur = frame_dur; + vstatus->frame_data = gvs->frame_data; + vstatus->total_data = gvs->total_data; + vstatus->frame_count = gvs->frame_count; + vstatus->error_frame_count = gvs->error_frame_count; + vstatus->drop_frame_count = gvs->drop_frame_count; + vstatus->total_data = gvs->total_data; + vstatus->samp_cnt = gvs->samp_cnt; + vstatus->offset = gvs->offset; + snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name), + "%s", DRIVER_NAME); + + return 0; +} + +static int vh264_4k2k_vdec_info_init(void) +{ + gvs = kzalloc(sizeof(struct vdec_info), GFP_KERNEL); + if (NULL == gvs) { + pr_info("the struct of vdec status malloc failed.\n"); + return -ENOMEM; + } + return 0; +} + +int vh264_4k2k_set_trickmode(struct vdec_s *vdec, unsigned long trickmode) +{ + if (trickmode == TRICKMODE_I) { + WRITE_VREG(DECODE_MODE, 1); + trickmode_i = 1; + } else if (trickmode == TRICKMODE_NONE) { + WRITE_VREG(DECODE_MODE, 0); + trickmode_i = 0; + } + + return 0; +} + +static void H264_DECODE_INIT(void) +{ + int i; + + WRITE_VREG(GCLK_EN, 0x3ff); + + WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4)); + WRITE_VREG(DOS_SW_RESET0, 0); + + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + + WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4)); + WRITE_VREG(DOS_SW_RESET0, 0); + + WRITE_VREG(DOS_SW_RESET0, (1 << 9) | (1 << 8)); + WRITE_VREG(DOS_SW_RESET0, 0); + + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + + /* fill_weight_pred */ + WRITE_VREG(MC_MPORT_CTRL, 0x0300); + for (i = 0; i < 192; i++) + WRITE_VREG(MC_MPORT_DAT, 0x100); + WRITE_VREG(MC_MPORT_CTRL, 0); + + WRITE_VREG(MB_WIDTH, 0xff); /* invalid mb_width */ + + /* set slice start to 0x000000 or 0x000001 for check more_rbsp_data */ + WRITE_VREG(SLICE_START_BYTE_01, 0x00000000); + WRITE_VREG(SLICE_START_BYTE_23, 0x01010000); + /* set to mpeg2 to enable mismatch logic */ + WRITE_VREG(MPEG1_2_REG, 1); + WRITE_VREG(VLD_ERROR_MASK, + 0x1011); + + /* Config MCPU Amrisc interrupt */ + WRITE_VREG(ASSIST_AMR1_INT0, 0x1); /* viu_vsync_int */ + WRITE_VREG(ASSIST_AMR1_INT1, 0x5); /* mbox_isr */ + WRITE_VREG(ASSIST_AMR1_INT2, 0x8); /* vld_isr */ + /* WRITE_VREG(ASSIST_AMR1_INT3, 0x15); // vififo_empty */ + WRITE_VREG(ASSIST_AMR1_INT4, 0xd); /* rv_ai_mb_finished_int */ + WRITE_VREG(ASSIST_AMR1_INT7, 0x14); /* dcac_dma_done */ + WRITE_VREG(ASSIST_AMR1_INT8, 0x15); /* vififo_empty */ + + /* Config MCPU Amrisc interrupt */ + WRITE_VREG(ASSIST_AMR1_INT5, 0x9); /* MCPU interrupt */ + WRITE_VREG(ASSIST_AMR1_INT6, 0x17); /* CCPU interrupt */ + + WRITE_VREG(CPC_P, 0xc00); /* CCPU Code will start from 0xc00 */ + WRITE_VREG(CINT_VEC_BASE, (0xc20 >> 5)); + WRITE_VREG(POWER_CTL_VLD, (1 << 10) | /* disable cabac_step_2 */ + (1 << 9) | /* viff_drop_flag_en */ + (1 << 6)); /* h264_000003_en */ + WRITE_VREG(M4_CONTROL_REG, (1 << 13)); /* H264_DECODE_INFO - h264_en */ + + WRITE_VREG(CANVAS_START, AMVDEC_H264_4K2K_CANVAS_INDEX); + /* Start Address of Workspace (UCODE, temp_data...) */ + WRITE_VREG(WORKSPACE_START, + video_domain_addr(work_space_adr)); + /* Clear all sequence parameter set available */ + WRITE_VREG(SPS_STATUS, 0); + /* Clear all picture parameter set available */ + WRITE_VREG(PPS_STATUS, 0); + /* Set current microcode to NULL */ + WRITE_VREG(CURRENT_UCODE, 0xff); + /* Set current SPS/PPS to NULL */ + WRITE_VREG(CURRENT_SPS_PPS, 0xffff); + /* Set decode status to DECODE_START_HEADER */ + WRITE_VREG(DECODE_STATUS, 1); +} + +static void H264_DECODE2_INIT(void) +{ + int i; + + WRITE_VREG(VDEC2_GCLK_EN, 0x3ff); + + WRITE_VREG(DOS_SW_RESET2, (1 << 7) | (1 << 6) | (1 << 4)); + WRITE_VREG(DOS_SW_RESET2, 0); + + READ_VREG(DOS_SW_RESET2); + READ_VREG(DOS_SW_RESET2); + READ_VREG(DOS_SW_RESET2); + + WRITE_VREG(DOS_SW_RESET2, (1 << 7) | (1 << 6) | (1 << 4)); + WRITE_VREG(DOS_SW_RESET2, 0); + + WRITE_VREG(DOS_SW_RESET2, (1 << 9) | (1 << 8)); + WRITE_VREG(DOS_SW_RESET2, 0); + + READ_VREG(DOS_SW_RESET2); + READ_VREG(DOS_SW_RESET2); + READ_VREG(DOS_SW_RESET2); + + /* fill_weight_pred */ + WRITE_VREG(VDEC2_MC_MPORT_CTRL, 0x0300); + for (i = 0; i < 192; i++) + WRITE_VREG(VDEC2_MC_MPORT_DAT, 0x100); + WRITE_VREG(VDEC2_MC_MPORT_CTRL, 0); + + WRITE_VREG(VDEC2_MB_WIDTH, 0xff); /* invalid mb_width */ + + /* set slice start to 0x000000 or 0x000001 for check more_rbsp_data */ + WRITE_VREG(VDEC2_SLICE_START_BYTE_01, 0x00000000); + WRITE_VREG(VDEC2_SLICE_START_BYTE_23, 0x01010000); + /* set to mpeg2 to enable mismatch logic */ + WRITE_VREG(VDEC2_MPEG1_2_REG, 1); + /* disable COEF_GT_64 , error_m4_table and voff_rw_err */ + WRITE_VREG(VDEC2_VLD_ERROR_MASK, + 0x1011); + + /* Config MCPU Amrisc interrupt */ + WRITE_VREG(VDEC2_ASSIST_AMR1_INT0, 0x1);/* viu_vsync_int */ + WRITE_VREG(VDEC2_ASSIST_AMR1_INT1, 0x5);/* mbox_isr */ + WRITE_VREG(VDEC2_ASSIST_AMR1_INT2, 0x8);/* vld_isr */ + /* WRITE_VREG(VDEC2_ASSIST_AMR1_INT3, 0x15); // vififo_empty */ + WRITE_VREG(VDEC2_ASSIST_AMR1_INT4, 0xd);/* rv_ai_mb_finished_int */ + WRITE_VREG(VDEC2_ASSIST_AMR1_INT7, 0x14);/* dcac_dma_done */ + WRITE_VREG(VDEC2_ASSIST_AMR1_INT8, 0x15);/* vififo_empty */ + + /* Config MCPU Amrisc interrupt */ + WRITE_VREG(VDEC2_ASSIST_AMR1_INT5, 0x9);/* MCPU interrupt */ + WRITE_VREG(VDEC2_ASSIST_AMR1_INT6, 0x17);/* CCPU interrupt */ + + WRITE_VREG(VDEC2_CPC_P, 0xc00); /* CCPU Code will start from 0xc00 */ + WRITE_VREG(VDEC2_CINT_VEC_BASE, (0xc20 >> 5)); + WRITE_VREG(VDEC2_POWER_CTL_VLD, (1 << 10) |/* disable cabac_step_2 */ + (1 << 9) | /* viff_drop_flag_en */ + (1 << 6)); /* h264_000003_en */ + /* H264_DECODE_INFO - h264_en */ + WRITE_VREG(VDEC2_M4_CONTROL_REG, (1 << 13)); + + WRITE_VREG(VDEC2_CANVAS_START, AMVDEC_H264_4K2K_CANVAS_INDEX); + /* Start Address of Workspace (UCODE, temp_data...) */ + WRITE_VREG(VDEC2_WORKSPACE_START, + video_domain_addr(work_space_adr)); + /* Clear all sequence parameter set available */ + WRITE_VREG(VDEC2_SPS_STATUS, 0); + /* Clear all picture parameter set available */ + WRITE_VREG(VDEC2_PPS_STATUS, 0); + /* Set current microcode to NULL */ + WRITE_VREG(VDEC2_CURRENT_UCODE, 0xff); + /* Set current SPS/PPS to NULL */ + WRITE_VREG(VDEC2_CURRENT_SPS_PPS, 0xffff); + /* Set decode status to DECODE_START_HEADER */ + WRITE_VREG(VDEC2_DECODE_STATUS, 1); +} + +static void vh264_4k2k_prot_init(void) +{ + /* clear mailbox interrupt */ +#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ + if (!H264_4K2K_SINGLE_CORE) + WRITE_VREG(VDEC2_ASSIST_MBOX0_CLR_REG, 1); +#endif + WRITE_VREG(VDEC_ASSIST_MBOX1_CLR_REG, 1); + + /* enable mailbox interrupt */ +#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ + if (!H264_4K2K_SINGLE_CORE) + WRITE_VREG(VDEC2_ASSIST_MBOX0_MASK, 1); +#endif + WRITE_VREG(VDEC_ASSIST_MBOX1_MASK, 1); + + /* disable PSCALE for hardware sharing */ + WRITE_VREG(PSCALE_CTRL, 0); + + H264_DECODE_INIT(); + if (!H264_4K2K_SINGLE_CORE) + H264_DECODE2_INIT(); + + WRITE_VREG(DOS_SW_RESET0, (1 << 11)); + WRITE_VREG(DOS_SW_RESET0, 0); + + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + + if (!H264_4K2K_SINGLE_CORE) { + WRITE_VREG(DOS_SW_RESET2, (1 << 11)); + WRITE_VREG(DOS_SW_RESET2, 0); + + READ_VREG(DOS_SW_RESET2); + READ_VREG(DOS_SW_RESET2); + READ_VREG(DOS_SW_RESET2); + } + + WRITE_VREG(MAILBOX_COMMAND, 0); + WRITE_VREG(BUFFER_RECYCLE, 0); + + if (!H264_4K2K_SINGLE_CORE) { + WRITE_VREG(VDEC2_MAILBOX_COMMAND, 0); + WRITE_VREG(VDEC2_BUFFER_RECYCLE, 0); + } + + CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17); + if (!H264_4K2K_SINGLE_CORE) + CLEAR_VREG_MASK(VDEC2_MDEC_PIC_DC_CTRL, 1 << 17); + + /* set VDEC Master/ID 0 */ + WRITE_VREG(MS_ID, (1 << 7) | (0 << 0)); + if (!H264_4K2K_SINGLE_CORE) { + /* set VDEC2 Slave/ID 0 */ + WRITE_VREG(VDEC2_MS_ID, (0 << 7) | (1 << 0)); + } + WRITE_VREG(DECODE_SKIP_PICTURE, 0); + if (!H264_4K2K_SINGLE_CORE) + WRITE_VREG(VDEC2_DECODE_SKIP_PICTURE, 0); + + WRITE_VREG(PRE_MASTER_UPDATE_TIMES, 0); + WRITE_VREG(SLAVE_WAIT_DPB_UPDATE, 0); + WRITE_VREG(SLAVE_REF_DPB, 0); + WRITE_VREG(SAVE_MVC_ENTENSION_0, 0); + WRITE_VREG(SAVE_I_POC, 0); + WRITE_VREG(CORE_STATUS_M, 0); + WRITE_VREG(CORE_STATUS_S, 0); + WRITE_VREG(SAVE_ref_status_view_0, 0); + WRITE_VREG(SAVE_ref_status_view_1, 0); + WRITE_VREG(ALLOC_INFO_0, 0); + WRITE_VREG(ALLOC_INFO_1, 0); + WRITE_VREG(FATAL_ERROR, 0); + + SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17); + if (!H264_4K2K_SINGLE_CORE) + SET_VREG_MASK(VDEC2_MDEC_PIC_DC_CTRL, 1 << 17); + + WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa); + if (!H264_4K2K_SINGLE_CORE) { + WRITE_VREG(VDEC2_MDEC_PIC_DC_THRESH, 0x404038aa); + } +#ifdef DOUBLE_WRITE + WRITE_VREG(MDEC_DOUBLEW_CFG0, (0 << 31) | /* half y address */ + (1 << 30) | /* 0:No Merge 1:Automatic Merge */ + (0 << 28) | + +/* Field Picture, 0x:no skip + * 10:top only + * 11:bottom only + */ + (0 << 27) | /* Source from, 1:MCW 0:DBLK */ + (0 << 24) | /* Endian Control for Chroma */ + (0 << 18) | /* DMA ID */ + (0 << 12) | /* DMA Burst Number */ + (0 << 11) | /* DMA Urgent */ + (0 << 10) | /* 1:Round 0:Truncation */ + (1 << 9) | + +/* Size by vertical, 0:original size + * 1: 1/2 shrunken size + */ + (1 << 8) | + +/* Size by horizontal, 0:original size + * 1: 1/2 shrunken size + */ + (0 << 6) | + +/* Pixel sel by vertical, 0x:1/2 + * 10:up + * 11:down + */ + (0 << 4) | + +/* Pixel sel by horizontal, 0x:1/2 + * 10:left + * 11:right + */ + (0 << 1) | /* Endian Control for Luma */ + (1 << 0)); /* Double Write Enable */ + if (!H264_4K2K_SINGLE_CORE) { + WRITE_VREG(VDEC2_MDEC_DOUBLEW_CFG0, + (0 << 31) | /* half y address */ + (1 << 30) | + +/* 0:No Merge + * 1:Automatic Merge + */ + (0 << 28) | + +/* Field Picture, 0x:no skip + * 10:top only + * 11:bottom only + */ + (0 << 27) | /* Source from, 1:MCW 0:DBLK */ + (0 << 24) | /* Endian Control for Chroma */ + (0 << 18) | /* DMA ID */ + (0 << 12) | /* DMA Burst Number */ + (0 << 11) | /* DMA Urgent */ + (0 << 10) | /* 1:Round 0:Truncation */ + (1 << 9) | + +/* Size by vertical, + * 0:original size + * 1: 1/2 shrunken size + */ + (1 << 8) | + +/* Size by horizontal, + * 0:original size + * 1: 1/2 shrunken size + */ + (0 << 6) | + +/* Pixel sel by vertical, + * 0x:1/2 + * 10:up + * 11:down + */ + (0 << 4) | + +/* Pixel sel by horizontal, + * 0x:1/2 + * 10:left + * 11:right + */ + (0 << 1) | /* Endian Control for Luma */ + (1 << 0)); /* Double Write Enable */ + } +#endif +} + +static int vh264_4k2k_local_init(void) +{ + int i, size, ret; + +#ifdef DEBUG_PTS + pts_missed = 0; + pts_hit = 0; +#endif + mb_width_old = 0; + mb_height_old = 0; + saved_resolution = 0; + vh264_4k2k_rotation = + (((unsigned long) vh264_4k2k_amstream_dec_info.param) >> 16) + & 0xffff; + frame_width = vh264_4k2k_amstream_dec_info.width; + frame_height = vh264_4k2k_amstream_dec_info.height; + frame_dur = + (vh264_4k2k_amstream_dec_info.rate == + 0) ? 3600 : vh264_4k2k_amstream_dec_info.rate; + if (frame_width && frame_height) + frame_ar = frame_height * 0x100 / frame_width; + sync_outside = ((unsigned long) vh264_4k2k_amstream_dec_info.param + & 0x02) >> 1; + error_watchdog_count = 0; + + pr_info("H264_4K2K: decinfo: %dx%d rate=%d\n", + frame_width, frame_height, + frame_dur); + + if (frame_dur == 0) + frame_dur = 96000 / 24; + + INIT_KFIFO(display_q); + INIT_KFIFO(recycle_q); + INIT_KFIFO(newframe_q); + + for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) + vfbuf_use[i] = 0; + + for (i = 0; i < VF_POOL_SIZE; i++) { + const struct vframe_s *vf = &vfpool[i]; + + vfpool[i].index = DECODE_BUFFER_NUM_MAX; + kfifo_put(&newframe_q, vf); + } + + reserved_buffer = 0; + p_last_vf = NULL; + first_i_received = 0; + INIT_WORK(&alloc_work, do_alloc_work); + + if (mm_blk_handle) { + decoder_bmmu_box_free(mm_blk_handle); + mm_blk_handle = NULL; + } + + mm_blk_handle = decoder_bmmu_box_alloc_box( + DRIVER_NAME, + 0, + MAX_BMMU_BUFFER_NUM, + 4 + PAGE_SHIFT, + CODEC_MM_FLAGS_CMA_CLEAR | + CODEC_MM_FLAGS_FOR_VDECODER); + + size = DECODER_WORK_SPACE_SIZE; + ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, 0, + size, DRIVER_NAME, &work_space_adr); + return ret; +} + +static s32 vh264_4k2k_init(void) +{ + int ret = -1, size = -1; + char *buf = vmalloc(0x1000 * 16); + + if (IS_ERR_OR_NULL(buf)) + return -ENOMEM; + + pr_info("\nvh264_4k2k_init\n"); + + init_timer(&recycle_timer); + + stat |= STAT_TIMER_INIT; + + ret = vh264_4k2k_local_init(); + if (ret < 0) + return ret; + amvdec_enable(); + + /* -- ucode loading (amrisc and swap code) */ + mc_cpu_addr = dma_alloc_coherent(amports_get_dma_device(), + MC_TOTAL_SIZE, &mc_dma_handle, GFP_KERNEL); + if (!mc_cpu_addr) { + amvdec_disable(); + vfree(buf); + pr_err("vh264_4k2k init: Can not allocate mc memory.\n"); + return -ENOMEM; + } + + WRITE_VREG(AV_SCRATCH_L, mc_dma_handle); + if (!H264_4K2K_SINGLE_CORE) + WRITE_VREG(VDEC2_AV_SCRATCH_L, mc_dma_handle); + + if (H264_4K2K_SINGLE_CORE) + size = get_firmware_data(VIDEO_DEC_H264_4k2K_SINGLE, buf); + + else + size = get_firmware_data(VIDEO_DEC_H264_4k2K, buf); + + if (size < 0) { + pr_err("get firmware fail."); + vfree(buf); + return -1; + } + + if (amvdec_loadmc_ex(VFORMAT_H264_4K2K, NULL, buf) < 0) { + amvdec_disable(); + dma_free_coherent(amports_get_dma_device(), + MC_TOTAL_SIZE, mc_cpu_addr, mc_dma_handle); + mc_cpu_addr = NULL; + return -EBUSY; + } + + if (!H264_4K2K_SINGLE_CORE) { + amvdec2_enable(); + + if (amvdec2_loadmc_ex(VFORMAT_H264_4K2K, NULL, buf) < 0) { + amvdec_disable(); + amvdec2_disable(); + dma_free_coherent(amports_get_dma_device(), + MC_TOTAL_SIZE, mc_cpu_addr, mc_dma_handle); + mc_cpu_addr = NULL; + return -EBUSY; + } + } + + /*header*/ + memcpy((u8 *) mc_cpu_addr, buf + 0x1000, 0x1000); + + /*mmco*/ + memcpy((u8 *) mc_cpu_addr + 0x1000, buf + 0x2000, 0x2000); + + /*slice*/ + memcpy((u8 *) mc_cpu_addr + 0x3000, buf + 0x4000, 0x3000); + + if (ret < 0) { + amvdec_disable(); + if (!H264_4K2K_SINGLE_CORE) + amvdec2_disable(); + pr_info("vh264_4k2k load firmware error.\n"); + if (mc_cpu_addr) { + dma_free_coherent(amports_get_dma_device(), + MC_TOTAL_SIZE, mc_cpu_addr, mc_dma_handle); + mc_cpu_addr = NULL; + } + + return -EBUSY; + } + stat |= STAT_MC_LOAD; + + /* enable AMRISC side protocol */ + vh264_4k2k_prot_init(); + + if (vdec_request_irq(VDEC_IRQ_1, vh264_4k2k_isr, + "vh264_4k2k-irq", (void *)vh264_4k2k_dec_id)) { + pr_info("vh264_4k2k irq register error.\n"); + amvdec_disable(); + if (!H264_4K2K_SINGLE_CORE) + amvdec2_disable(); + + return -ENOENT; + } +#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ + if (!H264_4K2K_SINGLE_CORE) { + if (vdec_request_irq(VDEC_IRQ_0, vh264_4k2k_vdec2_isr, + "vh264_4k2k-vdec2-irq", + (void *)vh264_4k2k_dec_id2)) { + pr_info("vh264_4k2k irq register error.\n"); + vdec_free_irq(VDEC_IRQ_1, (void *)vh264_4k2k_dec_id); + amvdec_disable(); + amvdec2_disable(); + return -ENOENT; + } + } +#endif + + stat |= STAT_ISR_REG; + + vf_provider_init(&vh264_4k2k_vf_prov, PROVIDER_NAME, + &vh264_4k2k_vf_provider, NULL); + vf_reg_provider(&vh264_4k2k_vf_prov); + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL); + + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_FR_HINT, + (void *)((unsigned long) + vh264_4k2k_amstream_dec_info.rate)); + + stat |= STAT_VF_HOOK; + + recycle_timer.data = (ulong) (&recycle_timer); + recycle_timer.function = vh264_4k2k_put_timer_func; + recycle_timer.expires = jiffies + PUT_INTERVAL; + + add_timer(&recycle_timer); + + stat |= STAT_TIMER_ARM; + + amvdec_start(); + if (!H264_4K2K_SINGLE_CORE) + amvdec2_start(); + + stat |= STAT_VDEC_RUN; + + ret = vh264_4k2k_vdec_info_init(); + if (0 != ret) + return -ret; + + return 0; +} + +static int vh264_4k2k_stop(void) +{ + + if (stat & STAT_VDEC_RUN) { + amvdec_stop(); + if (!H264_4K2K_SINGLE_CORE) + amvdec2_stop(); + stat &= ~STAT_VDEC_RUN; + } + + if (stat & STAT_ISR_REG) { + WRITE_VREG(VDEC_ASSIST_MBOX1_MASK, 0); + if (!H264_4K2K_SINGLE_CORE) + WRITE_VREG(VDEC2_ASSIST_MBOX0_MASK, 0); + + vdec_free_irq(VDEC_IRQ_1, (void *)vh264_4k2k_dec_id); +#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ + if (!H264_4K2K_SINGLE_CORE) + vdec_free_irq(VDEC_IRQ_0, (void *)vh264_4k2k_dec_id2); +#endif + stat &= ~STAT_ISR_REG; + } + + if (stat & STAT_TIMER_ARM) { + del_timer_sync(&recycle_timer); + stat &= ~STAT_TIMER_ARM; + } + + if (stat & STAT_VF_HOOK) { + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_FR_END_HINT, NULL); + + vf_unreg_provider(&vh264_4k2k_vf_prov); + stat &= ~STAT_VF_HOOK; + } +#ifdef DOUBLE_WRITE + WRITE_VREG(MDEC_DOUBLEW_CFG0, 0); + if (!H264_4K2K_SINGLE_CORE) + WRITE_VREG(VDEC2_MDEC_DOUBLEW_CFG0, 0); +#endif + + if (stat & STAT_MC_LOAD) { + if (mc_cpu_addr != NULL) { + dma_free_coherent(amports_get_dma_device(), + MC_TOTAL_SIZE, mc_cpu_addr, mc_dma_handle); + mc_cpu_addr = NULL; + } + + stat &= ~STAT_MC_LOAD; + } + + amvdec_disable(); + if (!H264_4K2K_SINGLE_CORE) + amvdec2_disable(); +#ifdef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA + msleep(100); +#endif + if (mm_blk_handle) { + decoder_bmmu_box_free(mm_blk_handle); + mm_blk_handle = NULL; + } + + return 0; +} + +void vh264_4k_free_cmabuf(void) +{ + int i; + + if (atomic_read(&vh264_4k2k_active)) + return; + mutex_lock(&vh264_4k2k_mutex); + for (i = 0; i < ARRAY_SIZE(buffer_spec); i++) { + if (buffer_spec[i].phy_addr) { + codec_mm_free_for_dma(MEM_NAME, + buffer_spec[i].phy_addr); + buffer_spec[i].phy_addr = 0; + buffer_spec[i].alloc_pages = NULL; + buffer_spec[i].alloc_count = 0; + pr_info("force free CMA buffer %d\n", i); + } + } + mutex_unlock(&vh264_4k2k_mutex); +} + +static int amvdec_h264_4k2k_probe(struct platform_device *pdev) +{ + struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; + + pr_info("amvdec_h264_4k2k probe start.\n"); + + mutex_lock(&vh264_4k2k_mutex); + + fatal_error = 0; + + if (pdata == NULL) { + pr_info("\namvdec_h264_4k2k memory resource undefined.\n"); + mutex_unlock(&vh264_4k2k_mutex); + return -EFAULT; + } + + if (pdata->sys_info) + vh264_4k2k_amstream_dec_info = *pdata->sys_info; + cma_dev = pdata->cma_dev; + + pr_info(" sysinfo: %dx%d, rate = %d, param = 0x%lx\n", + vh264_4k2k_amstream_dec_info.width, + vh264_4k2k_amstream_dec_info.height, + vh264_4k2k_amstream_dec_info.rate, + (unsigned long) vh264_4k2k_amstream_dec_info.param); + + if (!H264_4K2K_SINGLE_CORE) { + if (vdec_on(VDEC_2)) { /* ++++ */ + vdec_poweroff(VDEC_2); /* ++++ */ + mdelay(10); + } + vdec_poweron(VDEC_2); + } + + + if (!H264_4K2K_SINGLE_CORE) + vdec2_power_mode(1); + + pdata->dec_status = vh264_4k2k_dec_status; + if (H264_4K2K_SINGLE_CORE) + pdata->set_trickmode = vh264_4k2k_set_trickmode; + + if (vh264_4k2k_init() < 0) { + pr_info("\namvdec_h264_4k2k init failed.\n"); + mutex_unlock(&vh264_4k2k_mutex); + kfree(gvs); + gvs = NULL; + + return -ENODEV; + } +#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8*/ + request_vpu_clk_vmod(360000000, VPU_VIU_VD1); +#endif + + if (probe_callback) + probe_callback(); + /*set the max clk for smooth playing...*/ + vdec_source_changed(VFORMAT_H264_4K2K, + 4096, 2048, 30); + INIT_WORK(&set_clk_work, vh264_4k2k_set_clk); + + atomic_set(&vh264_4k2k_active, 1); + mutex_unlock(&vh264_4k2k_mutex); + + return 0; +} + +static int amvdec_h264_4k2k_remove(struct platform_device *pdev) +{ + cancel_work_sync(&alloc_work); + cancel_work_sync(&set_clk_work); + mutex_lock(&vh264_4k2k_mutex); + atomic_set(&vh264_4k2k_active, 0); + + vh264_4k2k_stop(); + + vdec_source_changed(VFORMAT_H264_4K2K, 0, 0, 0); + + if (!H264_4K2K_SINGLE_CORE) { + vdec_poweroff(VDEC_2); + } +#ifdef DEBUG_PTS + pr_info("pts missed %ld, pts hit %ld, duration %d\n", + pts_missed, pts_hit, frame_dur); +#endif + + if (remove_callback) + remove_callback(); + + mutex_unlock(&vh264_4k2k_mutex); + + kfree(gvs); + gvs = NULL; + + pr_info("amvdec_h264_4k2k_remove\n"); + return 0; +} + +void vh264_4k2k_register_module_callback(void (*enter_func)(void), + void (*remove_func)(void)) +{ + probe_callback = enter_func; + remove_callback = remove_func; +} +EXPORT_SYMBOL(vh264_4k2k_register_module_callback); + +/****************************************/ + +static struct platform_driver amvdec_h264_4k2k_driver = { + .probe = amvdec_h264_4k2k_probe, + .remove = amvdec_h264_4k2k_remove, +#ifdef CONFIG_PM + .suspend = amvdec_suspend, + .resume = amvdec_resume, +#endif + .driver = { + .name = DRIVER_NAME, + } +}; + +static struct codec_profile_t amvdec_h264_4k2k_profile = { + .name = "h264_4k2k", + .profile = "" +}; +static struct mconfig h264_4k2k_configs[] = { + MC_PU32("stat", &stat), + MC_PU32("error_recovery_mode", &error_recovery_mode), +}; +static struct mconfig_node h264_4k2k_node; + +static int __init amvdec_h264_4k2k_driver_init_module(void) +{ + pr_debug("amvdec_h264_4k2k module init\n"); + + if (platform_driver_register(&amvdec_h264_4k2k_driver)) { + pr_err("failed to register amvdec_h264_4k2k driver\n"); + return -ENODEV; + } + if (get_cpu_type() < MESON_CPU_MAJOR_ID_GXTVBB) + vcodec_profile_register(&amvdec_h264_4k2k_profile); + INIT_REG_NODE_CONFIGS("media.decoder", &h264_4k2k_node, + "h264_4k2k", h264_4k2k_configs, CONFIG_FOR_RW); + return 0; +} + +static void __exit amvdec_h264_4k2k_driver_remove_module(void) +{ + pr_debug("amvdec_h264_4k2k module remove.\n"); + + platform_driver_unregister(&amvdec_h264_4k2k_driver); +} + +/****************************************/ + +module_param(stat, uint, 0664); +MODULE_PARM_DESC(stat, "\n amvdec_h264_4k2k stat\n"); + +module_param(error_recovery_mode, uint, 0664); +MODULE_PARM_DESC(error_recovery_mode, "\n amvdec_h264 error_recovery_mode\n"); + +module_init(amvdec_h264_4k2k_driver_init_module); +module_exit(amvdec_h264_4k2k_driver_remove_module); + +MODULE_DESCRIPTION("AMLOGIC h264_4k2k Video Decoder Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Tim Yao "); diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/h264/vh264_mvc.c b/drivers/amlogic/media_modules/frame_provider/decoder/h264/vh264_mvc.c new file mode 100644 index 000000000000..9ca073f99326 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/h264/vh264_mvc.c @@ -0,0 +1,1719 @@ +/* + * drivers/amlogic/amports/vh264mvc.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include "../../../stream_input/amports/amports_priv.h" +#include "../utils/vdec.h" +#include "../utils/amvdec.h" +#include "../utils/decoder_mmu_box.h" +#include "../utils/decoder_bmmu_box.h" +#include +#include +#include "../utils/firmware.h" +#include + +#define TIME_TASK_PRINT_ENABLE 0x100 +#define PUT_PRINT_ENABLE 0x200 + +#define DRIVER_NAME "amvdec_h264mvc" +#define MODULE_NAME "amvdec_h264mvc" + +#define HANDLE_h264mvc_IRQ + +#define DEBUG_PTS +#define DEBUG_SKIP + +#define PUT_INTERVAL (HZ/100) + +#define STAT_TIMER_INIT 0x01 +#define STAT_MC_LOAD 0x02 +#define STAT_ISR_REG 0x04 +#define STAT_VF_HOOK 0x08 +#define STAT_TIMER_ARM 0x10 +#define STAT_VDEC_RUN 0x20 + +#define DROPPING_THREAD_HOLD 4 +#define DROPPING_FIRST_WAIT 16 +#define DISPLAY_INVALID_POS -65536 + +#define INIT_DROP_FRAME_CNT 8 + +static int vh264mvc_vf_states(struct vframe_states *states, void *); +static struct vframe_s *vh264mvc_vf_peek(void *); +static struct vframe_s *vh264mvc_vf_get(void *); +static void vh264mvc_vf_put(struct vframe_s *, void *); +static int vh264mvc_event_cb(int type, void *data, void *private_data); + +static void vh264mvc_prot_init(void); +static int vh264mvc_local_init(void); +static void vh264mvc_put_timer_func(unsigned long arg); + +static const char vh264mvc_dec_id[] = "vh264mvc-dev"; + +#define PROVIDER_NAME "decoder.h264mvc" + +static struct vdec_info *gvs; +static struct work_struct alloc_work; +static struct work_struct set_clk_work; + +static DEFINE_MUTEX(vh264_mvc_mutex); + +static const struct vframe_operations_s vh264mvc_vf_provider = { + .peek = vh264mvc_vf_peek, + .get = vh264mvc_vf_get, + .put = vh264mvc_vf_put, + .event_cb = vh264mvc_event_cb, + .vf_states = vh264mvc_vf_states, +}; + +static struct vframe_provider_s vh264mvc_vf_prov; + +static u32 frame_width, frame_height, frame_dur; +static u32 saved_resolution; +static struct timer_list recycle_timer; +static u32 stat; +static u32 pts_outside; +static u32 sync_outside; +static u32 vh264mvc_ratio; +static u32 h264mvc_ar; +static u32 no_dropping_cnt; +static s32 init_drop_cnt; + +#ifdef DEBUG_SKIP +static unsigned long view_total, view_dropped; +#endif + +#ifdef DEBUG_PTS +static unsigned long pts_missed, pts_hit; +#endif + +static atomic_t vh264mvc_active = ATOMIC_INIT(0); +static struct work_struct error_wd_work; + +static struct dec_sysinfo vh264mvc_amstream_dec_info; +static dma_addr_t mc_dma_handle; +static void *mc_cpu_addr; + +static DEFINE_SPINLOCK(lock); + +static int vh264mvc_stop(void); +static s32 vh264mvc_init(void); + +/*************************** + * new + ************************** + */ + +/* bit[3:0] command : */ +/* 0 - command finished */ +/* (DATA0 - {level_idc_mmco, max_reference_frame_num, width, height} */ +/* 1 - alloc view_0 display_buffer and reference_data_area */ +/* 2 - alloc view_1 display_buffer and reference_data_area */ +#define MAILBOX_COMMAND AV_SCRATCH_0 +#define MAILBOX_DATA_0 AV_SCRATCH_1 +#define MAILBOX_DATA_1 AV_SCRATCH_2 +#define MAILBOX_DATA_2 AV_SCRATCH_3 +#define CANVAS_START AV_SCRATCH_6 +#define BUFFER_RECYCLE AV_SCRATCH_7 +#define DROP_CONTROL AV_SCRATCH_8 +#define PICTURE_COUNT AV_SCRATCH_9 +#define DECODE_STATUS AV_SCRATCH_A +#define SPS_STATUS AV_SCRATCH_B +#define PPS_STATUS AV_SCRATCH_C +#define SIM_RESERV_D AV_SCRATCH_D +#define WORKSPACE_START AV_SCRATCH_E +#define SIM_RESERV_F AV_SCRATCH_F +#define DECODE_ERROR_CNT AV_SCRATCH_G +#define CURRENT_UCODE AV_SCRATCH_H +#define CURRENT_SPS_PPS AV_SCRATCH_I/* bit[15:9]-SPS, bit[8:0]-PPS */ +#define DECODE_SKIP_PICTURE AV_SCRATCH_J +#define UCODE_START_ADDR AV_SCRATCH_K +#define SIM_RESERV_L AV_SCRATCH_L +#define REF_START_VIEW_0 AV_SCRATCH_M +#define REF_START_VIEW_1 AV_SCRATCH_N + +/******************************************** + * Mailbox command + ********************************************/ +#define CMD_FINISHED 0 +#define CMD_ALLOC_VIEW_0 1 +#define CMD_ALLOC_VIEW_1 2 +#define CMD_FRAME_DISPLAY 3 +#define CMD_FATAL_ERROR 4 + +#define CANVAS_INDEX_START 0x78 +/* /AMVDEC_H264MVC_CANVAS_INDEX */ + +#define MC_TOTAL_SIZE (28*SZ_1K) +#define MC_SWAP_SIZE (4*SZ_1K) + +unsigned int DECODE_BUFFER_START = 0x00200000; +unsigned int DECODE_BUFFER_END = 0x05000000; + +#define DECODE_BUFFER_NUM_MAX 16 +#define DISPLAY_BUFFER_NUM 4 +#define MAX_BMMU_BUFFER_NUM (DECODE_BUFFER_NUM_MAX + DISPLAY_BUFFER_NUM) +#define TOTAL_BMMU_BUFF_NUM (MAX_BMMU_BUFFER_NUM * 2 + 3) +#define VF_BUFFER_IDX(n) (2 + n) + +#define DECODER_WORK_SPACE_SIZE 0xa0000 + + +static unsigned int ANC_CANVAS_ADDR; +static unsigned int index; +static unsigned long ref_start_addr[2]; +static unsigned int max_dec_frame_buffering[2]; +static unsigned int total_dec_frame_buffering[2]; + +static unsigned int dpb_size, ref_size; + +static int display_buff_id; +static int display_view_id; +static int display_POC; +static int stream_offset; + +#define video_domain_addr(adr) (adr&0x7fffffff) +static unsigned long work_space_adr; + +struct buffer_spec_s { + unsigned int y_addr; + unsigned int u_addr; + unsigned int v_addr; + + int y_canvas_index; + int u_canvas_index; + int v_canvas_index; + + struct page *alloc_pages; + unsigned long phy_addr; + int alloc_count; +}; +static struct buffer_spec_s buffer_spec0[MAX_BMMU_BUFFER_NUM]; +static struct buffer_spec_s buffer_spec1[MAX_BMMU_BUFFER_NUM]; +static void *mm_blk_handle; + +/* + * dbg_mode: + * bit 0: 1, print debug information + * bit 4: 1, recycle buffer without displaying; + * bit 5: 1, buffer single frame step , set dbg_cmd to 1 to step + * + */ +static int dbg_mode; +static int dbg_cmd; +static int view_mode = + 3; /* 0, left; 1 ,right ; 2, left<->right 3, right<->left */ +static int drop_rate = 2; +static int drop_thread_hold; +/**/ + +struct mvc_buf_s { + struct list_head list; + struct vframe_s vframe; + int display_POC; + int view0_buff_id; + int view1_buff_id; + int view0_drop; + int view1_drop; + int stream_offset; + unsigned int pts; +} /*mvc_buf_t */; + +#define spec2canvas(x) \ + (((x)->v_canvas_index << 16) | \ + ((x)->u_canvas_index << 8) | \ + ((x)->y_canvas_index << 0)) + +#define to_mvcbuf(vf) \ + container_of(vf, struct mvc_buf_s, vframe) + +static int vf_buf_init_flag; + +static void init_vf_buf(void) +{ + + vf_buf_init_flag = 1; +} + +static void uninit_vf_buf(void) +{ + +} + +/* #define QUEUE_SUPPORT */ + +struct mvc_info_s { + int view0_buf_id; + int view1_buf_id; + int view0_drop; + int view1_drop; + int display_pos; + int used; + int slot; + unsigned int stream_offset; +}; + +#define VF_POOL_SIZE 20 +static struct vframe_s vfpool[VF_POOL_SIZE]; +static struct mvc_info_s vfpool_idx[VF_POOL_SIZE]; +static s32 view0_vfbuf_use[DECODE_BUFFER_NUM_MAX]; +static s32 view1_vfbuf_use[DECODE_BUFFER_NUM_MAX]; + +static s32 fill_ptr, get_ptr, putting_ptr, put_ptr; +static s32 dirty_frame_num; +static s32 enable_recycle; + +static s32 init_drop_frame_id[INIT_DROP_FRAME_CNT]; +#define INCPTR(p) ptr_atomic_wrap_inc(&p) +static inline void ptr_atomic_wrap_inc(u32 *ptr) +{ + u32 i = *ptr; + + i++; + + if (i >= VF_POOL_SIZE) + i = 0; + + *ptr = i; +} + +static void set_frame_info(struct vframe_s *vf) +{ + unsigned int ar = 0; + + vf->width = frame_width; + vf->height = frame_height; + vf->duration = frame_dur; + vf->duration_pulldown = 0; + + if (vh264mvc_ratio == 0) { + /* always stretch to 16:9 */ + vf->ratio_control |= (0x90 << + DISP_RATIO_ASPECT_RATIO_BIT); + } else { + /* h264mvc_ar = ((float)frame_height/frame_width) + *customer_ratio; + */ + ar = min_t(u32, h264mvc_ar, DISP_RATIO_ASPECT_RATIO_MAX); + + vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT); + } +} + +static int vh264mvc_vf_states(struct vframe_states *states, void *op_arg) +{ + unsigned long flags; + int i; + + spin_lock_irqsave(&lock, flags); + states->vf_pool_size = VF_POOL_SIZE; + + i = put_ptr - fill_ptr; + if (i < 0) + i += VF_POOL_SIZE; + states->buf_free_num = i; + + i = putting_ptr - put_ptr; + if (i < 0) + i += VF_POOL_SIZE; + states->buf_recycle_num = i; + + i = fill_ptr - get_ptr; + if (i < 0) + i += VF_POOL_SIZE; + states->buf_avail_num = i; + + spin_unlock_irqrestore(&lock, flags); + return 0; +} + +void send_drop_cmd(void) +{ + int ready_cnt = 0; + int temp_get_ptr = get_ptr; + int temp_fill_ptr = fill_ptr; + + while (temp_get_ptr != temp_fill_ptr) { + if ((vfpool_idx[temp_get_ptr].view0_buf_id >= 0) + && (vfpool_idx[temp_get_ptr].view1_buf_id >= 0) + && (vfpool_idx[temp_get_ptr].view0_drop == 0) + && (vfpool_idx[temp_get_ptr].view1_drop == 0)) + ready_cnt++; + INCPTR(temp_get_ptr); + } + if (dbg_mode & 0x40) { + pr_info("ready_cnt is %d ; no_dropping_cnt is %d\n", ready_cnt, + no_dropping_cnt); + } + if ((no_dropping_cnt >= DROPPING_FIRST_WAIT) + && (ready_cnt < drop_thread_hold)) + WRITE_VREG(DROP_CONTROL, (1 << 31) | (drop_rate)); + else + WRITE_VREG(DROP_CONTROL, 0); +} + +#if 0 +int get_valid_frame(void) +{ + int ready_cnt = 0; + int temp_get_ptr = get_ptr; + int temp_fill_ptr = fill_ptr; + + while (temp_get_ptr != temp_fill_ptr) { + if ((vfpool_idx[temp_get_ptr].view0_buf_id >= 0) + && (vfpool_idx[temp_get_ptr].view1_buf_id >= 0) + && (vfpool_idx[temp_get_ptr].view0_drop == 0) + && (vfpool_idx[temp_get_ptr].view1_drop == 0)) + ready_cnt++; + INCPTR(temp_get_ptr); + } + return ready_cnt; +} +#endif +static struct vframe_s *vh264mvc_vf_peek(void *op_arg) +{ + + if (get_ptr == fill_ptr) + return NULL; + send_drop_cmd(); + return &vfpool[get_ptr]; + +} + +static struct vframe_s *vh264mvc_vf_get(void *op_arg) +{ + + struct vframe_s *vf; + int view0_buf_id; + int view1_buf_id; + + if (get_ptr == fill_ptr) + return NULL; + + view0_buf_id = vfpool_idx[get_ptr].view0_buf_id; + view1_buf_id = vfpool_idx[get_ptr].view1_buf_id; + vf = &vfpool[get_ptr]; + + if ((view0_buf_id >= 0) && (view1_buf_id >= 0)) { + if (view_mode == 0 || view_mode == 1) { + vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD; + vf->canvas0Addr = vf->canvas1Addr = + (view_mode == + 0) ? spec2canvas(&buffer_spec0[view0_buf_id]) : + spec2canvas(&buffer_spec1[view1_buf_id]); + } else { + vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_MVC; + + vf->left_eye.start_x = 0; + vf->left_eye.start_y = 0; + vf->left_eye.width = vf->width; + vf->left_eye.height = vf->height; + vf->right_eye.start_x = 0; + vf->right_eye.start_y = 0; + vf->right_eye.width = vf->width; + vf->right_eye.height = vf->height; + vf->trans_fmt = TVIN_TFMT_3D_TB; + + if (view_mode == 2) { + vf->canvas0Addr = + spec2canvas(&buffer_spec1[ + view1_buf_id]); + vf->canvas1Addr = + spec2canvas(&buffer_spec0[ + view0_buf_id]); + } else { + vf->canvas0Addr = + spec2canvas(&buffer_spec0[ + view0_buf_id]); + vf->canvas1Addr = + spec2canvas(&buffer_spec1[ + view1_buf_id]); + } + } + } + vf->type_original = vf->type; + if (((vfpool_idx[get_ptr].view0_drop != 0) + || (vfpool_idx[get_ptr].view1_drop != 0)) + && ((no_dropping_cnt >= DROPPING_FIRST_WAIT))) + vf->frame_dirty = 1; + else + vf->frame_dirty = 0; + + INCPTR(get_ptr); + + if (vf) { + if (frame_width == 0) + frame_width = vh264mvc_amstream_dec_info.width; + if (frame_height == 0) + frame_height = vh264mvc_amstream_dec_info.height; + + vf->width = frame_width; + vf->height = frame_height; + } + if ((no_dropping_cnt < DROPPING_FIRST_WAIT) && (vf->frame_dirty == 0)) + no_dropping_cnt++; + return vf; + +} + +static void vh264mvc_vf_put(struct vframe_s *vf, void *op_arg) +{ + + if (vf_buf_init_flag == 0) + return; + if (vf->frame_dirty) { + + vf->frame_dirty = 0; + dirty_frame_num++; + enable_recycle = 0; + if (dbg_mode & PUT_PRINT_ENABLE) { + pr_info("invalid: dirty_frame_num is !!! %d\n", + dirty_frame_num); + } + } else { + INCPTR(putting_ptr); + while (dirty_frame_num > 0) { + INCPTR(putting_ptr); + dirty_frame_num--; + } + enable_recycle = 1; + if (dbg_mode & PUT_PRINT_ENABLE) { + pr_info("valid: dirty_frame_num is @@@ %d\n", + dirty_frame_num); + } + /* send_drop_cmd(); */ + } + +} + +static int vh264mvc_event_cb(int type, void *data, void *private_data) +{ + if (type & VFRAME_EVENT_RECEIVER_RESET) { + unsigned long flags; + + amvdec_stop(); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_light_unreg_provider(&vh264mvc_vf_prov); +#endif + spin_lock_irqsave(&lock, flags); + vh264mvc_local_init(); + vh264mvc_prot_init(); + spin_unlock_irqrestore(&lock, flags); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_reg_provider(&vh264mvc_vf_prov); +#endif + amvdec_start(); + } + return 0; +} + +/**/ +static long init_canvas(int view_index, int refbuf_size, long dpb_size, + int dpb_number, int mb_width, int mb_height, + struct buffer_spec_s *buffer_spec) +{ + + unsigned long addr; + int i, j, bmmu_index; + int mb_total, ret = -1; + /* cav_con canvas; */ + mb_total = mb_width * mb_height; + mutex_lock(&vh264_mvc_mutex); + + for (j = 0; j < (dpb_number + 1); j++) { + int page_count; + if (j == 0) { + if (!view_index) + bmmu_index = 1; + else + bmmu_index = dpb_number + 2; + + ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, + bmmu_index, refbuf_size, DRIVER_NAME, + &ref_start_addr[view_index]); + + if (ret < 0) { + mutex_unlock(&vh264_mvc_mutex); + return ret; + } + + continue; + } + /* canvas buf */ + WRITE_VREG(ANC_CANVAS_ADDR, + index | ((index + 1) << 8) | + ((index + 2) << 16)); + ANC_CANVAS_ADDR++; + + i = j - 1; + if (!view_index) + bmmu_index = VF_BUFFER_IDX(i); + else + bmmu_index = VF_BUFFER_IDX(i) + dpb_number + 1; +#ifdef DOUBLE_WRITE + page_count = PAGE_ALIGN((mb_total << 8) + (mb_total << 7) + + (mb_total << 6) + (mb_total << 5)) / PAGE_SIZE; +#else + page_count = PAGE_ALIGN((mb_total << 8) + + (mb_total << 7)) / PAGE_SIZE; +#endif + + ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, + bmmu_index, page_count << PAGE_SHIFT, + DRIVER_NAME, &buffer_spec[i].phy_addr); + + if (ret < 0) { + buffer_spec[i].alloc_count = 0; + mutex_unlock(&vh264_mvc_mutex); + return ret; + } + + addr = buffer_spec[i].phy_addr; + buffer_spec[i].alloc_count = page_count; + buffer_spec[i].y_addr = addr; + buffer_spec[i].y_canvas_index = index; + canvas_config(index, addr, + mb_width << 4, mb_height << 4, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); + + addr += mb_total << 8; + index++; + buffer_spec[i].u_addr = addr; + buffer_spec[i].u_canvas_index = index; + canvas_config(index, addr, mb_width << 3, mb_height << 3, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); + + addr += mb_total << 6; + index++; + buffer_spec[i].v_addr = addr; + buffer_spec[i].v_canvas_index = index; + canvas_config(index, addr, mb_width << 3, mb_height << 3, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); + + index++; + } + mutex_unlock(&vh264_mvc_mutex); + return 0; +} + +static int get_max_dec_frame_buf_size(int level_idc, + int max_reference_frame_num, int mb_width, + int mb_height) +{ + int pic_size = mb_width * mb_height * 384; + + int size = 0; + + switch (level_idc) { + case 9: + size = 152064; + break; + case 10: + size = 152064; + break; + case 11: + size = 345600; + break; + case 12: + size = 912384; + break; + case 13: + size = 912384; + break; + case 20: + size = 912384; + break; + case 21: + size = 1824768; + break; + case 22: + size = 3110400; + break; + case 30: + size = 3110400; + break; + case 31: + size = 6912000; + break; + case 32: + size = 7864320; + break; + case 40: + size = 12582912; + break; + case 41: + size = 12582912; + break; + case 42: + size = 13369344; + break; + case 50: + size = 42393600; + break; + case 51: + size = 70778880; + break; + default: + break; + } + + size /= pic_size; + size = size + 1; /* For MVC need onr more buffer */ + if (max_reference_frame_num > size) + size = max_reference_frame_num; + if (size > DECODE_BUFFER_NUM_MAX) + size = DECODE_BUFFER_NUM_MAX; + + return size; +} + +int check_in_list(int pos, int *slot) +{ + int i; + int ret = 0; + + for (i = 0; i < VF_POOL_SIZE; i++) { + if ((vfpool_idx[i].display_pos == pos) + && (vfpool_idx[i].used == 0)) { + ret = 1; + *slot = vfpool_idx[i].slot; + break; + } + } + return ret; +} + +static void do_alloc_work(struct work_struct *work) +{ + int level_idc, max_reference_frame_num, mb_width, mb_height; + int refbuf_size; + int ret = READ_VREG(MAILBOX_COMMAND); + + switch (ret & 0xff) { + case CMD_ALLOC_VIEW_0: + if (dbg_mode & 0x1) { + pr_info + ("Start H264 display buffer for view 0\n"); + } + + ret = READ_VREG(MAILBOX_DATA_0); + level_idc = (ret >> 24) & 0xff; + max_reference_frame_num = (ret >> 16) & 0xff; + mb_width = (ret >> 8) & 0xff; + mb_height = (ret >> 0) & 0xff; + max_dec_frame_buffering[0] = + get_max_dec_frame_buf_size(level_idc, + max_reference_frame_num, + mb_width, mb_height); + + total_dec_frame_buffering[0] = + max_dec_frame_buffering[0] + DISPLAY_BUFFER_NUM; + + mb_width = (mb_width + 3) & 0xfffffffc; + mb_height = (mb_height + 3) & 0xfffffffc; + + dpb_size = mb_width * mb_height * 384; + ref_size = mb_width * mb_height * 96; + + if (dbg_mode & 0x1) { + pr_info("dpb_size: 0x%x\n", dpb_size); + pr_info("ref_size: 0x%x\n", ref_size); + pr_info("total_dec_frame_buffering[0] : 0x%x\n", + total_dec_frame_buffering[0]); + pr_info("max_reference_frame_num: 0x%x\n", + max_reference_frame_num); + } + refbuf_size + = ref_size * (max_reference_frame_num + 1) * 2; + + index = CANVAS_INDEX_START; + ANC_CANVAS_ADDR = ANC0_CANVAS_ADDR; + + ret = + init_canvas(0, refbuf_size, dpb_size, + total_dec_frame_buffering[0], mb_width, + mb_height, buffer_spec0); + + if (ret < 0) { + pr_info(" Un-expected memory alloc problem\n"); + return; + } + + WRITE_VREG(REF_START_VIEW_0, + video_domain_addr(ref_start_addr[0])); + WRITE_VREG(MAILBOX_DATA_0, + (max_dec_frame_buffering[0] << 8) | + (total_dec_frame_buffering[0] << 0)); + WRITE_VREG(MAILBOX_DATA_1, ref_size); + WRITE_VREG(MAILBOX_COMMAND, CMD_FINISHED); + + if (dbg_mode & 0x1) { + pr_info + ("End H264 display buffer for view 0\n"); + } + if (frame_width == 0) { + if (vh264mvc_amstream_dec_info.width) + frame_width = vh264mvc_amstream_dec_info.width; + else + frame_width = mb_width << 4; + } + if (frame_height == 0) { + frame_height = mb_height << 4; + if (frame_height == 1088) + frame_height = 1080; + } + break; + case CMD_ALLOC_VIEW_1: + if (dbg_mode & 0x1) { + pr_info + ("Start H264 display buffer for view 1\n"); + } + + ret = READ_VREG(MAILBOX_DATA_0); + level_idc = (ret >> 24) & 0xff; + max_reference_frame_num = (ret >> 16) & 0xff; + mb_width = (ret >> 8) & 0xff; + mb_height = (ret >> 0) & 0xff; + max_dec_frame_buffering[1] = + get_max_dec_frame_buf_size(level_idc, + max_reference_frame_num, + mb_width, mb_height); + if (max_dec_frame_buffering[1] != max_dec_frame_buffering[0]) { + pr_info + (" Warning: view0/1 max_dec_frame_buffering "); + pr_info("different : 0x%x/0x%x, Use View0\n", + max_dec_frame_buffering[0], + max_dec_frame_buffering[1]); + max_dec_frame_buffering[1] = max_dec_frame_buffering[0]; + } + + total_dec_frame_buffering[1] = + max_dec_frame_buffering[1] + DISPLAY_BUFFER_NUM; + + mb_width = (mb_width + 3) & 0xfffffffc; + mb_height = (mb_height + 3) & 0xfffffffc; + + dpb_size = mb_width * mb_height * 384; + ref_size = mb_width * mb_height * 96; + refbuf_size = ref_size * (max_reference_frame_num + 1) * 2; + if (dbg_mode & 0x1) { + pr_info("dpb_size: 0x%x\n", dpb_size); + pr_info("ref_size: 0x%x\n", ref_size); + pr_info("total_dec_frame_buffering[1] : 0x%x\n", + total_dec_frame_buffering[1]); + pr_info("max_reference_frame_num: 0x%x\n", + max_reference_frame_num); + } + + index = CANVAS_INDEX_START + total_dec_frame_buffering[0] * 3; + ANC_CANVAS_ADDR = + ANC0_CANVAS_ADDR + total_dec_frame_buffering[0]; + + ret = init_canvas(1, refbuf_size, dpb_size, + total_dec_frame_buffering[1], mb_width, + mb_height, buffer_spec1); + + if (ret < 0) { + pr_info(" Un-expected memory alloc problem\n"); + return; + } + + WRITE_VREG(REF_START_VIEW_1, + video_domain_addr(ref_start_addr[1])); + WRITE_VREG(MAILBOX_DATA_0, + (max_dec_frame_buffering[1] << 8) | + (total_dec_frame_buffering[1] << 0)); + WRITE_VREG(MAILBOX_DATA_1, ref_size); + WRITE_VREG(MAILBOX_COMMAND, CMD_FINISHED); + + if (dbg_mode & 0x1) { + pr_info + ("End H264 buffer allocation for view 1\n"); + } + if (frame_width == 0) { + if (vh264mvc_amstream_dec_info.width) + frame_width = vh264mvc_amstream_dec_info.width; + else + frame_width = mb_width << 4; + } + if (frame_height == 0) { + frame_height = mb_height << 4; + if (frame_height == 1088) + frame_height = 1080; + } + break; + } + +} + + +#ifdef HANDLE_h264mvc_IRQ +static irqreturn_t vh264mvc_isr(int irq, void *dev_id) +#else +static void vh264mvc_isr(void) +#endif +{ + int drop_status; + struct vframe_s *vf; + unsigned int pts, pts_valid = 0; + u64 pts_us64; + int ret = READ_VREG(MAILBOX_COMMAND); + /* pr_info("vh264mvc_isr, cmd =%x\n", ret); */ + switch (ret & 0xff) { + case CMD_ALLOC_VIEW_0: + case CMD_ALLOC_VIEW_1: + schedule_work(&alloc_work); + break; + case CMD_FRAME_DISPLAY: + ret = READ_VREG(MAILBOX_DATA_0); + display_buff_id = (ret >> 0) & 0x3f; + display_view_id = (ret >> 6) & 0x3; + drop_status = (ret >> 8) & 0x1; + display_POC = READ_VREG(MAILBOX_DATA_1); + stream_offset = READ_VREG(MAILBOX_DATA_2); + /* if (display_view_id == 0) */ + WRITE_VREG(MAILBOX_COMMAND, CMD_FINISHED); + +#ifdef DEBUG_SKIP + view_total++; + if (drop_status) + view_dropped++; +#endif + if (dbg_mode & 0x1) { + pr_info + (" H264 display frame ready - View : %x, Buffer : %x\n", + display_view_id, display_buff_id); + pr_info + (" H264 display frame POC -- Buffer : %x, POC : %x\n", + display_buff_id, display_POC); + pr_info("H264 display frame ready\n"); + } + if (dbg_mode & 0x10) { + if ((dbg_mode & 0x20) == 0) { + while (READ_VREG(BUFFER_RECYCLE) != 0) + ; + WRITE_VREG(BUFFER_RECYCLE, + (display_view_id << 8) | + (display_buff_id + 1)); + display_buff_id = -1; + display_view_id = -1; + display_POC = -1; + } + } else { + unsigned char in_list_flag = 0; + + int slot = 0; + + in_list_flag = check_in_list(display_POC, &slot); + + if ((dbg_mode & 0x40) && (drop_status)) { + pr_info + ("drop_status:%dview_id=%d,buff_id=%d,", + drop_status, display_view_id, display_buff_id); + pr_info + ("offset=%d, display_POC = %d,fill_ptr=0x%x\n", + stream_offset, display_POC, fill_ptr); + } + + if ((in_list_flag) && (stream_offset != 0)) { + pr_info + ("error case ,display_POC is %d, slot is %d\n", + display_POC, slot); + in_list_flag = 0; + } + if (!in_list_flag) { + if (display_view_id == 0) { + vfpool_idx[fill_ptr].view0_buf_id = + display_buff_id; + view0_vfbuf_use[display_buff_id]++; + vfpool_idx[fill_ptr].stream_offset = + stream_offset; + vfpool_idx[fill_ptr].view0_drop = + drop_status; + } + if (display_view_id == 1) { + vfpool_idx[fill_ptr].view1_buf_id = + display_buff_id; + vfpool_idx[fill_ptr].view1_drop = + drop_status; + view1_vfbuf_use[display_buff_id]++; + } + vfpool_idx[fill_ptr].slot = fill_ptr; + vfpool_idx[fill_ptr].display_pos = display_POC; + + } else { + if (display_view_id == 0) { + vfpool_idx[slot].view0_buf_id = + display_buff_id; + view0_vfbuf_use[display_buff_id]++; + vfpool_idx[slot].stream_offset = + stream_offset; + vfpool_idx[slot].view0_drop = + drop_status; + + } + if (display_view_id == 1) { + vfpool_idx[slot].view1_buf_id = + display_buff_id; + view1_vfbuf_use[display_buff_id]++; + vfpool_idx[slot].view1_drop = + drop_status; + } + vf = &vfpool[slot]; + + if (display_view_id == 0) { + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + VF_BUFFER_IDX(display_buff_id)); + + } else if (display_view_id == 1) { + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + VF_BUFFER_IDX(display_buff_id) + + total_dec_frame_buffering[0] + + 1); + } + + + + if (vfpool_idx[slot].stream_offset == 0) { + pr_info + ("error case, invalid stream offset\n"); + } + if (pts_lookup_offset_us64 + (PTS_TYPE_VIDEO, + vfpool_idx[slot].stream_offset, &pts, + 0x10000, &pts_us64) == 0) + pts_valid = 1; + else + pts_valid = 0; + vf->pts = (pts_valid) ? pts : 0; + vf->pts_us64 = (pts_valid) ? pts_us64 : 0; + /* vf->pts = vf->pts_us64 ? vf->pts_us64 + * : vf->pts ; + */ + /* vf->pts = vf->pts_us64; */ + if (dbg_mode & 0x80) + pr_info("vf->pts:%d\n", vf->pts); + vfpool_idx[slot].used = 1; + INCPTR(fill_ptr); + set_frame_info(vf); + + gvs->frame_dur = frame_dur; + vdec_count_info(gvs, 0, + vfpool_idx[slot].stream_offset); + + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + + } + } + break; + case CMD_FATAL_ERROR: + pr_info("fatal error !!!\n"); + schedule_work(&error_wd_work); + break; + default: + break; + } +#ifdef HANDLE_h264mvc_IRQ + return IRQ_HANDLED; +#else + return; +#endif +} + +static void vh264_mvc_set_clk(struct work_struct *work) +{ + if (frame_dur > 0 && saved_resolution != + frame_width * frame_height * (96000 / frame_dur)) { + int fps = 96000 / frame_dur; + + saved_resolution = frame_width * frame_height * fps; + vdec_source_changed(VFORMAT_H264MVC, + frame_width, frame_height, fps * 2); + } +} + +static void vh264mvc_put_timer_func(unsigned long arg) +{ + struct timer_list *timer = (struct timer_list *)arg; + + int valid_frame = 0; + + if (enable_recycle == 0) { + if (dbg_mode & TIME_TASK_PRINT_ENABLE) { + /* valid_frame = get_valid_frame(); */ + pr_info("dirty_frame_num is %d , valid frame is %d\n", + dirty_frame_num, valid_frame); + + } + /* goto RESTART; */ + } + + while ((putting_ptr != put_ptr) && (READ_VREG(BUFFER_RECYCLE) == 0)) { + int view0_buf_id = vfpool_idx[put_ptr].view0_buf_id; + int view1_buf_id = vfpool_idx[put_ptr].view1_buf_id; + + if ((view0_buf_id >= 0) && + (view0_vfbuf_use[view0_buf_id] == 1)) { + if (dbg_mode & 0x100) { + pr_info + ("round 0: put_ptr is %d ;view0_buf_id is %d\n", + put_ptr, view0_buf_id); + } + WRITE_VREG(BUFFER_RECYCLE, + (0 << 8) | (view0_buf_id + 1)); + view0_vfbuf_use[view0_buf_id] = 0; + vfpool_idx[put_ptr].view0_buf_id = -1; + vfpool_idx[put_ptr].view0_drop = 0; + } else if ((view1_buf_id >= 0) + && (view1_vfbuf_use[view1_buf_id] == 1)) { + if (dbg_mode & 0x100) { + pr_info + ("round 1: put_ptr is %d ;view1_buf_id %d==\n", + put_ptr, view1_buf_id); + } + WRITE_VREG(BUFFER_RECYCLE, + (1 << 8) | (view1_buf_id + 1)); + view1_vfbuf_use[view1_buf_id] = 0; + vfpool_idx[put_ptr].display_pos = DISPLAY_INVALID_POS; + vfpool_idx[put_ptr].view1_buf_id = -1; + vfpool_idx[put_ptr].view1_drop = 0; + vfpool_idx[put_ptr].used = 0; + INCPTR(put_ptr); + } + } + + schedule_work(&set_clk_work); + + /* RESTART: */ + timer->expires = jiffies + PUT_INTERVAL; + + add_timer(timer); +} + +int vh264mvc_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus) +{ + vstatus->frame_width = frame_width; + vstatus->frame_height = frame_height; + if (frame_dur != 0) + vstatus->frame_rate = 96000 / frame_dur; + else + vstatus->frame_rate = -1; + vstatus->error_count = READ_VREG(AV_SCRATCH_D); + vstatus->status = stat; + vstatus->bit_rate = gvs->bit_rate; + vstatus->frame_dur = frame_dur; + vstatus->frame_data = gvs->frame_data; + vstatus->total_data = gvs->total_data; + vstatus->frame_count = gvs->frame_count; + vstatus->error_frame_count = gvs->error_frame_count; + vstatus->drop_frame_count = gvs->drop_frame_count; + vstatus->total_data = gvs->total_data; + vstatus->samp_cnt = gvs->samp_cnt; + vstatus->offset = gvs->offset; + snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name), + "%s", DRIVER_NAME); + + return 0; +} + +static int vh264mvc_vdec_info_init(void) +{ + gvs = kzalloc(sizeof(struct vdec_info), GFP_KERNEL); + if (NULL == gvs) { + pr_info("the struct of vdec status malloc failed.\n"); + return -ENOMEM; + } + return 0; +} + +int vh264mvc_set_trickmode(struct vdec_s *vdec, unsigned long trickmode) +{ + if (trickmode == TRICKMODE_I) { + WRITE_VREG(AV_SCRATCH_F, + (READ_VREG(AV_SCRATCH_F) & 0xfffffffc) | 2); + trickmode_i = 1; + } else if (trickmode == TRICKMODE_NONE) { + WRITE_VREG(AV_SCRATCH_F, READ_VREG(AV_SCRATCH_F) & 0xfffffffc); + trickmode_i = 0; + } + + return 0; +} + +static void H264_DECODE_INIT(void) +{ + int i; + + i = READ_VREG(DECODE_SKIP_PICTURE); + +#if 1 /* /MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ + WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4)); + WRITE_VREG(DOS_SW_RESET0, 0); + + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + + WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4)); + WRITE_VREG(DOS_SW_RESET0, 0); + + WRITE_VREG(DOS_SW_RESET0, (1 << 9) | (1 << 8)); + WRITE_VREG(DOS_SW_RESET0, 0); + + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + +#else + WRITE_RESET_REG(RESET0_REGISTER, + RESET_IQIDCT | RESET_MC | RESET_VLD_PART); + READ_RESET_REG(RESET0_REGISTER); + WRITE_RESET_REG(RESET0_REGISTER, + RESET_IQIDCT | RESET_MC | RESET_VLD_PART); + WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK); +#endif + + /* Wait for some time for RESET */ + READ_VREG(DECODE_SKIP_PICTURE); + READ_VREG(DECODE_SKIP_PICTURE); + + WRITE_VREG(DECODE_SKIP_PICTURE, i); + + /* fill_weight_pred */ + WRITE_VREG(MC_MPORT_CTRL, 0x0300); + for (i = 0; i < 192; i++) + WRITE_VREG(MC_MPORT_DAT, 0x100); + WRITE_VREG(MC_MPORT_CTRL, 0); + + WRITE_VREG(MB_WIDTH, 0xff); /* invalid mb_width */ + + /* set slice start to 0x000000 or 0x000001 for check more_rbsp_data */ + WRITE_VREG(SLICE_START_BYTE_01, 0x00000000); + WRITE_VREG(SLICE_START_BYTE_23, 0x01010000); + /* set to mpeg2 to enable mismatch logic */ + WRITE_VREG(MPEG1_2_REG, 1); + /* disable COEF_GT_64 , error_m4_table and voff_rw_err */ + WRITE_VREG(VLD_ERROR_MASK, 0x1011); + + /* Config MCPU Amrisc interrupt */ + WRITE_VREG(ASSIST_AMR1_INT0, 0x1); /* viu_vsync_int */ + WRITE_VREG(ASSIST_AMR1_INT1, 0x5); /* mbox_isr */ + WRITE_VREG(ASSIST_AMR1_INT2, 0x8); /* vld_isr */ + WRITE_VREG(ASSIST_AMR1_INT3, 0x15); /* vififo_empty */ + WRITE_VREG(ASSIST_AMR1_INT4, 0xd); /* rv_ai_mb_finished_int */ + WRITE_VREG(ASSIST_AMR1_INT7, 0x14); /* dcac_dma_done */ + + /* Config MCPU Amrisc interrupt */ + WRITE_VREG(ASSIST_AMR1_INT5, 0x9); /* MCPU interrupt */ + WRITE_VREG(ASSIST_AMR1_INT6, 0x17); /* CCPU interrupt */ + + WRITE_VREG(CPC_P, 0xc00); /* CCPU Code will start from 0xc00 */ + WRITE_VREG(CINT_VEC_BASE, (0xc20 >> 5)); +#if 0 + WRITE_VREG(POWER_CTL_VLD, + READ_VREG(POWER_CTL_VLD) | (0 << 10) | + (1 << 9) | (1 << 6)); +#else + WRITE_VREG(POWER_CTL_VLD, ((1 << 10) | /* disable cabac_step_2 */ + (1 << 9) | /* viff_drop_flag_en */ + (1 << 6) /* h264_000003_en */ + ) + ); +#endif + WRITE_VREG(M4_CONTROL_REG, (1 << 13)); /* H264_DECODE_INFO - h264_en */ + + WRITE_VREG(CANVAS_START, CANVAS_INDEX_START); +#if 1 + /* Start Address of Workspace (UCODE, temp_data...) */ + WRITE_VREG(WORKSPACE_START, + video_domain_addr(work_space_adr)); +#else + /* Start Address of Workspace (UCODE, temp_data...) */ + WRITE_VREG(WORKSPACE_START, + 0x05000000); +#endif + /* Clear all sequence parameter set available */ + WRITE_VREG(SPS_STATUS, 0); + /* Clear all picture parameter set available */ + WRITE_VREG(PPS_STATUS, 0); + /* Set current microcode to NULL */ + WRITE_VREG(CURRENT_UCODE, 0xff); + /* Set current SPS/PPS to NULL */ + WRITE_VREG(CURRENT_SPS_PPS, 0xffff); + /* Set decode status to DECODE_START_HEADER */ + WRITE_VREG(DECODE_STATUS, 1); +} + +static void vh264mvc_prot_init(void) +{ + while (READ_VREG(DCAC_DMA_CTRL) & 0x8000) + ; + while (READ_VREG(LMEM_DMA_CTRL) & 0x8000) + ; /* reg address is 0x350 */ + /* clear mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + /* enable mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_MASK, 1); + + /* disable PSCALE for hardware sharing */ + WRITE_VREG(PSCALE_CTRL, 0); + + H264_DECODE_INIT(); + +#if 1 /* /MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ + WRITE_VREG(DOS_SW_RESET0, (1 << 11)); + WRITE_VREG(DOS_SW_RESET0, 0); + + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + +#else + WRITE_RESET_REG(RESET0_REGISTER, 0x80); /* RESET MCPU */ +#endif + + WRITE_VREG(MAILBOX_COMMAND, 0); + WRITE_VREG(BUFFER_RECYCLE, 0); + WRITE_VREG(DROP_CONTROL, 0); + CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17); +#if 1 /* /MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ + WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa); +#endif +} + +static int vh264mvc_local_init(void) +{ + int i, size, ret; + display_buff_id = -1; + display_view_id = -1; + display_POC = -1; + no_dropping_cnt = 0; + init_drop_cnt = INIT_DROP_FRAME_CNT; + + for (i = 0; i < INIT_DROP_FRAME_CNT; i++) + init_drop_frame_id[i] = 0; + +#ifdef DEBUG_PTS + pts_missed = 0; + pts_hit = 0; +#endif + +#ifdef DEBUG_SKIP + view_total = 0; + view_dropped = 0; +#endif + + /* vh264mvc_ratio = vh264mvc_amstream_dec_info.ratio; */ + vh264mvc_ratio = 0x100; + + /* frame_width = vh264mvc_amstream_dec_info.width; */ + /* frame_height = vh264mvc_amstream_dec_info.height; */ + frame_dur = vh264mvc_amstream_dec_info.rate; + if (frame_dur == 0) + frame_dur = 96000 / 24; + + pts_outside = ((unsigned long) vh264mvc_amstream_dec_info.param) & 0x01; + sync_outside = ((unsigned long) vh264mvc_amstream_dec_info.param & 0x02) + >> 1; + INIT_WORK(&alloc_work, do_alloc_work); + + max_dec_frame_buffering[0] = -1; + max_dec_frame_buffering[1] = -1; + fill_ptr = get_ptr = put_ptr = putting_ptr = 0; + dirty_frame_num = 0; + for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) { + view0_vfbuf_use[i] = 0; + view1_vfbuf_use[i] = 0; + } + + for (i = 0; i < VF_POOL_SIZE; i++) { + vfpool_idx[i].display_pos = -1; + vfpool_idx[i].view0_buf_id = DISPLAY_INVALID_POS; + vfpool_idx[i].view1_buf_id = -1; + vfpool_idx[i].view0_drop = 0; + vfpool_idx[i].view1_drop = 0; + vfpool_idx[i].used = 0; + } + for (i = 0; i < VF_POOL_SIZE; i++) + memset(&vfpool[i], 0, sizeof(struct vframe_s)); + init_vf_buf(); + + if (mm_blk_handle) { + decoder_bmmu_box_free(mm_blk_handle); + mm_blk_handle = NULL; + } + + mm_blk_handle = decoder_bmmu_box_alloc_box( + DRIVER_NAME, + 0, + TOTAL_BMMU_BUFF_NUM, + 4 + PAGE_SHIFT, + CODEC_MM_FLAGS_CMA_CLEAR | + CODEC_MM_FLAGS_FOR_VDECODER); + + size = DECODER_WORK_SPACE_SIZE; + ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, 0, + size, DRIVER_NAME, &work_space_adr); + + return ret; +} + +static s32 vh264mvc_init(void) +{ + int ret = -1, size = -1; + char *buf = vmalloc(0x1000 * 16); + + if (IS_ERR_OR_NULL(buf)) + return -ENOMEM; + + pr_info("\nvh264mvc_init\n"); + init_timer(&recycle_timer); + + stat |= STAT_TIMER_INIT; + + ret = vh264mvc_vdec_info_init(); + if (0 != ret) + return -ret; + + ret = vh264mvc_local_init(); + if (ret < 0) + return ret; + + amvdec_enable(); + + if (tee_enabled()) { + pr_info("the video fw from the teeload.\n"); + ret = tee_load_video_fw((u32)VIDEO_DEC_H264_MVC, 0); + if (ret != 0) { + amvdec_disable(); + return -1; + } + } else { + /* -- ucode loading (amrisc and swap code) */ + mc_cpu_addr = dma_alloc_coherent(amports_get_dma_device(), + MC_TOTAL_SIZE, &mc_dma_handle, GFP_KERNEL); + if (!mc_cpu_addr) { + amvdec_disable(); + vfree(buf); + pr_err("vh264_mvc init: Can not allocate mc memory.\n"); + return -ENOMEM; + } + + WRITE_VREG(UCODE_START_ADDR, mc_dma_handle); + + size = get_firmware_data(VIDEO_DEC_H264_MVC, buf); + if (size < 0) { + pr_err("get firmware fail."); + vfree(buf); + return -1; + } + + ret = amvdec_loadmc_ex(VFORMAT_H264MVC, NULL, buf); + + /*header*/ + memcpy((u8 *) mc_cpu_addr, buf + 0x1000, 0x1000); + /*mmco*/ + memcpy((u8 *) mc_cpu_addr + 0x1000, buf + 0x2000, 0x2000); + /*slice*/ + memcpy((u8 *) mc_cpu_addr + 0x3000, buf + 0x4000, 0x3000); + + vfree(buf); + + if (ret < 0) { + amvdec_disable(); + + dma_free_coherent(amports_get_dma_device(), + MC_TOTAL_SIZE, + mc_cpu_addr, mc_dma_handle); + mc_cpu_addr = NULL; + return -EBUSY; + } + } + stat |= STAT_MC_LOAD; + + /* enable AMRISC side protocol */ + vh264mvc_prot_init(); + +#ifdef HANDLE_h264mvc_IRQ + if (vdec_request_irq(VDEC_IRQ_1, vh264mvc_isr, + "vh264mvc-irq", (void *)vh264mvc_dec_id)) { + pr_info("vh264mvc irq register error.\n"); + amvdec_disable(); + return -ENOENT; + } +#endif + + stat |= STAT_ISR_REG; + + vf_provider_init(&vh264mvc_vf_prov, PROVIDER_NAME, + &vh264mvc_vf_provider, NULL); + vf_reg_provider(&vh264mvc_vf_prov); + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL); + + stat |= STAT_VF_HOOK; + + recycle_timer.data = (ulong) (&recycle_timer); + recycle_timer.function = vh264mvc_put_timer_func; + recycle_timer.expires = jiffies + PUT_INTERVAL; + + add_timer(&recycle_timer); + + stat |= STAT_TIMER_ARM; + + amvdec_start(); + + stat |= STAT_VDEC_RUN; + + return 0; +} + +static int vh264mvc_stop(void) +{ + if (stat & STAT_VDEC_RUN) { + amvdec_stop(); + stat &= ~STAT_VDEC_RUN; + } + + if (stat & STAT_ISR_REG) { + WRITE_VREG(ASSIST_MBOX1_MASK, 0); +#ifdef HANDLE_h264mvc_IRQ + vdec_free_irq(VDEC_IRQ_1, (void *)vh264mvc_dec_id); +#endif + stat &= ~STAT_ISR_REG; + } + + if (stat & STAT_TIMER_ARM) { + del_timer_sync(&recycle_timer); + stat &= ~STAT_TIMER_ARM; + } + + if (stat & STAT_VF_HOOK) { + ulong flags; + + spin_lock_irqsave(&lock, flags); + spin_unlock_irqrestore(&lock, flags); + vf_unreg_provider(&vh264mvc_vf_prov); + stat &= ~STAT_VF_HOOK; + } + + if (stat & STAT_MC_LOAD) { + if (mc_cpu_addr != NULL) { + dma_free_coherent(amports_get_dma_device(), + MC_TOTAL_SIZE, mc_cpu_addr, mc_dma_handle); + mc_cpu_addr = NULL; + } + + stat &= ~STAT_MC_LOAD; + } + + amvdec_disable(); + + if (mm_blk_handle) { + decoder_bmmu_box_free(mm_blk_handle); + mm_blk_handle = NULL; + } + uninit_vf_buf(); + return 0; +} + +static void error_do_work(struct work_struct *work) +{ + if (atomic_read(&vh264mvc_active)) { + vh264mvc_stop(); + vh264mvc_init(); + } +} + +static int amvdec_h264mvc_probe(struct platform_device *pdev) +{ + struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; + + pr_info("amvdec_h264mvc probe start.\n"); + mutex_lock(&vh264_mvc_mutex); + +#if 0 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + pr_info("\namvdec_h264mvc memory resource undefined.\n"); + return -EFAULT; + } +#endif + + if (pdata == NULL) { + mutex_unlock(&vh264_mvc_mutex); + pr_info("\namvdec_h264mvc memory resource undefined.\n"); + return -EFAULT; + } + + if (pdata->sys_info) + vh264mvc_amstream_dec_info = *pdata->sys_info; + + pdata->dec_status = vh264mvc_dec_status; + /* pdata->set_trickmode = vh264mvc_set_trickmode; */ + + if (vh264mvc_init() < 0) { + pr_info("\namvdec_h264mvc init failed.\n"); + kfree(gvs); + gvs = NULL; + mutex_unlock(&vh264_mvc_mutex); + return -ENODEV; + } + + INIT_WORK(&error_wd_work, error_do_work); + INIT_WORK(&set_clk_work, vh264_mvc_set_clk); + + atomic_set(&vh264mvc_active, 1); + + mutex_unlock(&vh264_mvc_mutex); + + pr_info("amvdec_h264mvc probe end.\n"); + + return 0; +} + +static int amvdec_h264mvc_remove(struct platform_device *pdev) +{ + pr_info("amvdec_h264mvc_remove\n"); + cancel_work_sync(&alloc_work); + cancel_work_sync(&error_wd_work); + cancel_work_sync(&set_clk_work); + vh264mvc_stop(); + frame_width = 0; + frame_height = 0; + vdec_source_changed(VFORMAT_H264MVC, 0, 0, 0); + atomic_set(&vh264mvc_active, 0); + +#ifdef DEBUG_PTS + pr_info + ("pts missed %ld, pts hit %ld, pts_outside %d, ", + pts_missed, pts_hit, pts_outside); + pr_info("duration %d, sync_outside %d\n", + frame_dur, sync_outside); +#endif + +#ifdef DEBUG_SKIP + pr_info("view_total = %ld, dropped %ld\n", view_total, view_dropped); +#endif + kfree(gvs); + gvs = NULL; + + return 0; +} + +/****************************************/ + +static struct platform_driver amvdec_h264mvc_driver = { + .probe = amvdec_h264mvc_probe, + .remove = amvdec_h264mvc_remove, +#ifdef CONFIG_PM + .suspend = amvdec_suspend, + .resume = amvdec_resume, +#endif + .driver = { + .name = DRIVER_NAME, + } +}; + +static struct codec_profile_t amvdec_hmvc_profile = { + .name = "hmvc", + .profile = "" +}; +static struct mconfig h264mvc_configs[] = { + MC_PU32("stat", &stat), + MC_PU32("dbg_mode", &dbg_mode), + MC_PU32("view_mode", &view_mode), + MC_PU32("dbg_cmd", &dbg_cmd), + MC_PU32("drop_rate", &drop_rate), + MC_PU32("drop_thread_hold", &drop_thread_hold), +}; +static struct mconfig_node h264mvc_node; + +static int __init amvdec_h264mvc_driver_init_module(void) +{ + pr_debug("amvdec_h264mvc module init\n"); + + if (platform_driver_register(&amvdec_h264mvc_driver)) { + pr_err("failed to register amvdec_h264mvc driver\n"); + return -ENODEV; + } + + vcodec_profile_register(&amvdec_hmvc_profile); + INIT_REG_NODE_CONFIGS("media.decoder", &h264mvc_node, + "h264mvc", h264mvc_configs, CONFIG_FOR_RW); + return 0; +} + +static void __exit amvdec_h264mvc_driver_remove_module(void) +{ + pr_debug("amvdec_h264mvc module remove.\n"); + + platform_driver_unregister(&amvdec_h264mvc_driver); +} + +/****************************************/ + +module_param(stat, uint, 0664); +MODULE_PARM_DESC(stat, "\n amvdec_h264mvc stat\n"); + +module_param(dbg_mode, uint, 0664); +MODULE_PARM_DESC(dbg_mode, "\n amvdec_h264mvc dbg mode\n"); + +module_param(view_mode, uint, 0664); +MODULE_PARM_DESC(view_mode, "\n amvdec_h264mvc view mode\n"); + +module_param(dbg_cmd, uint, 0664); +MODULE_PARM_DESC(dbg_mode, "\n amvdec_h264mvc cmd mode\n"); + +module_param(drop_rate, uint, 0664); +MODULE_PARM_DESC(dbg_mode, "\n amvdec_h264mvc drop rate\n"); + +module_param(drop_thread_hold, uint, 0664); +MODULE_PARM_DESC(dbg_mode, "\n amvdec_h264mvc drop thread hold\n"); +module_init(amvdec_h264mvc_driver_init_module); +module_exit(amvdec_h264mvc_driver_remove_module); + +MODULE_DESCRIPTION("AMLOGIC h264mvc Video Decoder Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Chen Zhang "); diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/h264_multi/Makefile b/drivers/amlogic/media_modules/frame_provider/decoder/h264_multi/Makefile new file mode 100644 index 000000000000..21dfb6abb5b9 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/h264_multi/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_AMLOGIC_MEDIA_VDEC_H264_MULTI) += amvdec_mh264.o +amvdec_mh264-objs += vmh264.o h264_dpb.o diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/h264_multi/h264_dpb.c b/drivers/amlogic/media_modules/frame_provider/decoder/h264_multi/h264_dpb.c new file mode 100644 index 000000000000..3ec89d64509d --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/h264_multi/h264_dpb.c @@ -0,0 +1,5788 @@ +#define DEBUG +#include +#include +#include + +#include +#include "../utils/vdec.h" +#include "../utils/amvdec.h" + +#include "h264_dpb.h" + +#undef pr_info +#define pr_info printk +int dpb_print(int index, int debug_flag, const char *fmt, ...) +{ + if (((h264_debug_flag & debug_flag) && + ((1 << index) & h264_debug_mask)) + || (debug_flag == PRINT_FLAG_ERROR)) { + unsigned char buf[512]; + int len = 0; + va_list args; + + va_start(args, fmt); + len = sprintf(buf, "%d: ", index); + vsnprintf(buf + len, 512-len, fmt, args); + pr_debug("%s", buf); + va_end(args); + } + return 0; +} + +int dpb_print_cont(int index, int debug_flag, const char *fmt, ...) +{ + if (((h264_debug_flag & debug_flag) && + ((1 << index) & h264_debug_mask)) + || (debug_flag == PRINT_FLAG_ERROR)) { + unsigned char buf[512]; + int len = 0; + va_list args; + va_start(args, fmt); + vsnprintf(buf + len, 512-len, fmt, args); + pr_info("%s", buf); + va_end(args); + } + return 0; +} + +unsigned char dpb_is_debug(int index, int debug_flag) +{ + if (((h264_debug_flag & debug_flag) && + ((1 << index) & h264_debug_mask)) + || (debug_flag == PRINT_FLAG_ERROR)) + return 1; + return 0; +} + +#define CHECK_VALID(list_size, mark) {\ + if (list_size > MAX_LIST_SIZE || list_size < 0) { \ + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_ERROR, \ + "%s(%d): listXsize[%d] %d is larger than max size\r\n",\ + __func__, __LINE__, mark, list_size);\ + list_size = 0; \ + p_H264_Dpb->dpb_error_flag = __LINE__;\ + } \ + } + +static struct DecRefPicMarking_s + dummy_dec_ref_pic_marking_buffer + [DEC_REF_PIC_MARKING_BUFFER_NUM_MAX]; +static struct StorablePicture dummy_pic; +static struct FrameStore dummy_fs; +static struct StorablePicture *get_new_pic( + struct h264_dpb_stru *p_H264_Dpb, + enum PictureStructure structure, unsigned char is_output); + +static void init_dummy_fs(void) +{ + dummy_fs.frame = &dummy_pic; + dummy_fs.top_field = &dummy_pic; + dummy_fs.bottom_field = &dummy_pic; + + dummy_pic.top_field = &dummy_pic; + dummy_pic.bottom_field = &dummy_pic; + dummy_pic.frame = &dummy_pic; + + dummy_pic.dec_ref_pic_marking_buffer = + &dummy_dec_ref_pic_marking_buffer[0]; +} + +enum { + LIST_0 = 0, + LIST_1 = 1, + BI_PRED = 2, + BI_PRED_L0 = 3, + BI_PRED_L1 = 4 +}; + +void ref_pic_list_reordering(struct h264_dpb_stru *p_H264_Dpb, + struct Slice *currSlice) +{ + /* struct VideoParameters *p_Vid = currSlice->p_Vid; + * byte dP_nr = assignSE2partition[currSlice->dp_mode][SE_HEADER]; + * DataPartition *partition = &(currSlice->partArr[dP_nr]); + * Bitstream *currStream = partition->bitstream; + */ + int i, j, val; + unsigned short *reorder_cmd = + &p_H264_Dpb->dpb_param.mmco.l0_reorder_cmd[0]; + /* alloc_ref_pic_list_reordering_buffer(currSlice); */ + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s\n", __func__); + if (currSlice->slice_type != I_SLICE && + currSlice->slice_type != SI_SLICE) { + /* val = currSlice->ref_pic_list_reordering_flag[LIST_0] = + * read_u_1 ("SH: ref_pic_list_reordering_flag_l0", + * currStream, &p_Dec->UsedBits); + */ + if (reorder_cmd[0] != 3) { + val = currSlice-> + ref_pic_list_reordering_flag[LIST_0] = 1; + } else { + val = currSlice-> + ref_pic_list_reordering_flag[LIST_0] = 0; + } + if (val) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "%s, ref_pic_list_reordering_flag[LIST_0] is 1\n", + __func__); + + j = 0; + i = 0; + do { + val = currSlice-> + modification_of_pic_nums_idc[LIST_0][i] = + reorder_cmd[j++]; + /* read_ue_v( + * "SH: modification_of_pic_nums_idc_l0", + * currStream, &p_Dec->UsedBits); + */ + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "%d(%d):val %x\n", i, j, val); + if (j >= 66) { + currSlice-> + ref_pic_list_reordering_flag[LIST_0] = + 0; /* by rain */ + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_ERROR, + "%s error\n", __func__); + break; + } + if (val == 0 || val == 1) { + currSlice-> + abs_diff_pic_num_minus1[LIST_0][i] = + reorder_cmd[j++]; + /* read_ue_v("SH: " + *"abs_diff_pic_num_minus1_l0", + *currStream, &p_Dec->UsedBits); + */ + } else { + if (val == 2) { + currSlice-> + long_term_pic_idx[LIST_0][i] = + reorder_cmd[j++]; + /* read_ue_v( + *"SH: long_term_pic_idx_l0", + *currStream, + *&p_Dec->UsedBits); + */ + } + } + i++; + /* assert (i>currSlice-> + * num_ref_idx_active[LIST_0]); + */ + if ( + +/* + * i>currSlice->num_ref_idx_active[LIST_0] || + */ + i >= REORDERING_COMMAND_MAX_SIZE) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_ERROR, + "%s error %d %d\n", + __func__, i, + currSlice-> + num_ref_idx_active[LIST_0]); + currSlice-> + ref_pic_list_reordering_flag[LIST_0] = + 0; /* by rain */ + break; + } + if (j >= 66) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_ERROR, "%s error\n", + __func__); + currSlice-> + ref_pic_list_reordering_flag[LIST_0] = + 0; /* by rain */ + break; + } + + } while (val != 3); + } + } + + if (currSlice->slice_type == B_SLICE) { + reorder_cmd = &p_H264_Dpb->dpb_param.mmco.l1_reorder_cmd[0]; + /* val = currSlice->ref_pic_list_reordering_flag[LIST_1] + *= read_u_1 ("SH: ref_pic_list_reordering_flag_l1", + *currStream, + *&p_Dec->UsedBits); + */ + + if (reorder_cmd[0] != 3) { + val = + currSlice->ref_pic_list_reordering_flag[LIST_1] = 1; + } else { + val = + currSlice->ref_pic_list_reordering_flag[LIST_1] = 0; + } + + if (val) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "%s, ref_pic_list_reordering_flag[LIST_1] is 1\n", + __func__); + + j = 0; + i = 0; + do { + val = currSlice-> + modification_of_pic_nums_idc[LIST_1][i] = + reorder_cmd[j++]; + /* read_ue_v( + *"SH: modification_of_pic_nums_idc_l1", + *currStream, + *&p_Dec->UsedBits); + */ + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "%d(%d):val %x\n", + i, j, val); + if (j >= 66) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_ERROR, "%s error\n", + __func__); + currSlice-> + ref_pic_list_reordering_flag[LIST_1] = + 0; /* by rain */ + break; + } + if (val == 0 || val == 1) { + currSlice-> + abs_diff_pic_num_minus1[LIST_1][i] = + reorder_cmd[j++]; + /* read_ue_v( + *"SH: abs_diff_pic_num_minus1_l1", + *currStream, &p_Dec->UsedBits); + */ + } else { + if (val == 2) { + currSlice-> + long_term_pic_idx[LIST_1][i] = + reorder_cmd[j++]; + /* read_ue_v( + *"SH: long_term_pic_idx_l1", + *currStream, + *&p_Dec->UsedBits); + */ + } + } + i++; + /* assert(i>currSlice-> + * num_ref_idx_active[LIST_1]); + */ + if ( + /*i>currSlice->num_ref_idx_active[LIST_1] || */ + i >= REORDERING_COMMAND_MAX_SIZE) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_ERROR, + "%s error %d %d\n", + __func__, i, + currSlice-> + num_ref_idx_active[LIST_0]); + currSlice-> + ref_pic_list_reordering_flag[LIST_1] = + 0; /* by rain */ + break; + } + if (j >= 66) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_ERROR, + "%s error\n", __func__); + break; + } + } while (val != 3); + } + } + + /* set reference index of redundant slices. */ + /* + *if (currSlice->redundant_pic_cnt && + *(currSlice->slice_type != I_SLICE)) + *{ + * currSlice->redundant_slice_ref_idx = + * currSlice->abs_diff_pic_num_minus1[LIST_0][0] + 1; + *} + */ +} + +void slice_prepare(struct h264_dpb_stru *p_H264_Dpb, + struct DecodedPictureBuffer *p_Dpb, + struct VideoParameters *p_Vid, + struct SPSParameters *sps, struct Slice *pSlice) +{ + int i, j; + /* p_Vid->active_sps = sps; */ + unsigned short *mmco_cmd = &p_H264_Dpb->dpb_param.mmco.mmco_cmd[0]; + /* for decode_poc */ + sps->pic_order_cnt_type = + p_H264_Dpb->dpb_param.l.data[PIC_ORDER_CNT_TYPE]; + sps->log2_max_pic_order_cnt_lsb_minus4 = + p_H264_Dpb->dpb_param.l.data[LOG2_MAX_PIC_ORDER_CNT_LSB] - 4; + sps->num_ref_frames_in_pic_order_cnt_cycle = + p_H264_Dpb-> + dpb_param.l.data[NUM_REF_FRAMES_IN_PIC_ORDER_CNT_CYCLE]; + for (i = 0; i < 128; i++) + sps->offset_for_ref_frame[i] = + (short) p_H264_Dpb-> + dpb_param.mmco.offset_for_ref_frame_base[i]; + sps->offset_for_non_ref_pic = + (short) p_H264_Dpb->dpb_param.l.data[OFFSET_FOR_NON_REF_PIC]; + sps->offset_for_top_to_bottom_field = + (short) p_H264_Dpb->dpb_param.l.data + [OFFSET_FOR_TOP_TO_BOTTOM_FIELD]; + + pSlice->frame_num = p_H264_Dpb->dpb_param.dpb.frame_num; + pSlice->idr_flag = + (p_H264_Dpb->dpb_param.dpb.NAL_info_mmco & 0x1f) + == 5 ? 1 : 0; + pSlice->nal_reference_idc = + (p_H264_Dpb->dpb_param.dpb.NAL_info_mmco >> 5) + & 0x3; + pSlice->pic_order_cnt_lsb = + p_H264_Dpb->dpb_param.dpb.pic_order_cnt_lsb; + pSlice->field_pic_flag = 0; + pSlice->bottom_field_flag = 0; + pSlice->delta_pic_order_cnt_bottom = val( + p_H264_Dpb->dpb_param.dpb.delta_pic_order_cnt_bottom); + pSlice->delta_pic_order_cnt[0] = val( + p_H264_Dpb->dpb_param.dpb.delta_pic_order_cnt_0); + pSlice->delta_pic_order_cnt[1] = val( + p_H264_Dpb->dpb_param.dpb.delta_pic_order_cnt_1); + + p_Vid->last_has_mmco_5 = 0; + /* last memory_management_control_operation is 5 */ + p_Vid->last_pic_bottom_field = 0; + p_Vid->max_frame_num = 1 << + (p_H264_Dpb->dpb_param.l.data[LOG2_MAX_FRAME_NUM]); + + /**/ + pSlice->structure = (p_H264_Dpb-> + dpb_param.l.data[NEW_PICTURE_STRUCTURE] == 3) ? + FRAME : p_H264_Dpb->dpb_param.l.data[NEW_PICTURE_STRUCTURE]; + sps->num_ref_frames = p_H264_Dpb-> + dpb_param.l.data[MAX_REFERENCE_FRAME_NUM]; + sps->profile_idc = + (p_H264_Dpb->dpb_param.l.data[PROFILE_IDC_MMCO] >> 8) & 0xff; + /*sps->max_dpb_size = p_H264_Dpb->dpb_param.l.data[MAX_DPB_SIZE];*/ + if (pSlice->idr_flag) { + pSlice->long_term_reference_flag = mmco_cmd[0] & 1; + pSlice->no_output_of_prior_pics_flag = (mmco_cmd[0] >> 1) & 1; + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "IDR: long_term_reference_flag %d no_output_of_prior_pics_flag %d\r\n", + pSlice->long_term_reference_flag, + pSlice->no_output_of_prior_pics_flag); + + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "idr set pre_frame_num(%d) to frame_num (%d)\n", + p_Vid->pre_frame_num, pSlice->frame_num); + + p_Vid->pre_frame_num = pSlice->frame_num; + } else if (p_H264_Dpb->mDPB.first_pic_done == 0) { + /* by rain + handle the case when first slice is I instead of IDR + */ + p_Vid->pre_frame_num = pSlice->frame_num; + } + /* pSlice->adaptive_ref_pic_buffering_flag; */ + sps->log2_max_frame_num_minus4 = + p_H264_Dpb->dpb_param.l.data[LOG2_MAX_FRAME_NUM] - 4; + + p_Vid->non_conforming_stream = + p_H264_Dpb->dpb_param.l.data[NON_CONFORMING_STREAM]; + p_Vid->recovery_point = + p_H264_Dpb->dpb_param.l.data[RECOVERY_POINT]; + switch (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE]) { + case I_Slice: + pSlice->slice_type = I_SLICE; + break; + case P_Slice: + pSlice->slice_type = P_SLICE; + break; + case B_Slice: + pSlice->slice_type = B_SLICE; + break; + default: + pSlice->slice_type = NUM_SLICE_TYPES; + break; + } + + pSlice->num_ref_idx_active[LIST_0] = + p_H264_Dpb->dpb_param.dpb.num_ref_idx_l0_active_minus1 + + 1; + /* p_H264_Dpb->dpb_param.l.data[PPS_NUM_REF_IDX_L0_ACTIVE_MINUS1]; */ + pSlice->num_ref_idx_active[LIST_1] = + p_H264_Dpb->dpb_param.dpb.num_ref_idx_l1_active_minus1 + + 1; + /* p_H264_Dpb->dpb_param.l.data[PPS_NUM_REF_IDX_L1_ACTIVE_MINUS1]; */ + + pSlice->p_Vid = p_Vid; + pSlice->p_Dpb = p_Dpb; + /* + p_H264_Dpb->colocated_buf_size = + p_H264_Dpb->dpb_param.l.data[FRAME_SIZE_IN_MB] * 96;*/ + pSlice->first_mb_in_slice = + p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE]; + pSlice->mode_8x8_flags = p_H264_Dpb->dpb_param.l.data[MODE_8X8_FLAGS]; + pSlice->picture_structure_mmco = + p_H264_Dpb->dpb_param.dpb.picture_structure_mmco; + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s slice_type is %d, num_ref_idx_active[0,1]=%d,%d nal_reference_idc %d pic struct 0x%x(mmco stru 0x%x)\n", + __func__, pSlice->slice_type, + pSlice->num_ref_idx_active[LIST_0], + pSlice->num_ref_idx_active[LIST_1], + pSlice->nal_reference_idc, + pSlice->structure, + pSlice->picture_structure_mmco); +#ifdef ERROR_CHECK + if (pSlice->num_ref_idx_active[LIST_0] >= MAX_LIST_SIZE) { + pSlice->num_ref_idx_active[LIST_0] = MAX_LIST_SIZE - 1; + p_H264_Dpb->dpb_error_flag = __LINE__; + } + if (pSlice->num_ref_idx_active[LIST_1] >= MAX_LIST_SIZE) { + pSlice->num_ref_idx_active[LIST_1] = MAX_LIST_SIZE - 1; + p_H264_Dpb->dpb_error_flag = __LINE__; + } +#endif + +#if 1 + /* dec_ref_pic_marking_buffer */ + pSlice->adaptive_ref_pic_buffering_flag = 0; + if (pSlice->nal_reference_idc) { + for (i = 0, j = 0; i < 44; j++) { + unsigned short val; + struct DecRefPicMarking_s *tmp_drpm = + &pSlice->dec_ref_pic_marking_buffer[j]; + memset(tmp_drpm, 0, sizeof(struct DecRefPicMarking_s)); + val = tmp_drpm-> + memory_management_control_operation = + mmco_cmd[i++]; + tmp_drpm->Next = NULL; + if (j > 0) { + pSlice-> + dec_ref_pic_marking_buffer[j - 1].Next = + tmp_drpm; + } + if (val == 0 || i >= 44) + break; + pSlice->adaptive_ref_pic_buffering_flag = 1; + if ((val == 1) || (val == 3)) { + tmp_drpm->difference_of_pic_nums_minus1 = + mmco_cmd[i++]; + } + if (val == 2) + tmp_drpm->long_term_pic_num = mmco_cmd[i++]; + if (i >= 44) + break; + if ((val == 3) || (val == 6)) + tmp_drpm->long_term_frame_idx = mmco_cmd[i++]; + if (val == 4) { + tmp_drpm->max_long_term_frame_idx_plus1 = + mmco_cmd[i++]; + } + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "dec_ref_pic_marking_buffer[%d]:operation %x diff_pic_minus1 %x long_pic_num %x long_frame_idx %x max_long_frame_idx_plus1 %x\n", + j, + tmp_drpm->memory_management_control_operation, + tmp_drpm->difference_of_pic_nums_minus1, + tmp_drpm->long_term_pic_num, + tmp_drpm->long_term_frame_idx, + tmp_drpm->max_long_term_frame_idx_plus1); + } + } + + ref_pic_list_reordering(p_H264_Dpb, pSlice); +#endif + + /*VUI*/ + p_H264_Dpb->vui_status = p_H264_Dpb->dpb_param.l.data[VUI_STATUS]; + p_H264_Dpb->aspect_ratio_idc = + p_H264_Dpb->dpb_param.l.data[ASPECT_RATIO_IDC]; + p_H264_Dpb->aspect_ratio_sar_width = + p_H264_Dpb->dpb_param.l.data[ASPECT_RATIO_SAR_WIDTH]; + p_H264_Dpb->aspect_ratio_sar_height = + p_H264_Dpb->dpb_param.l.data[ASPECT_RATIO_SAR_HEIGHT]; + + p_H264_Dpb->fixed_frame_rate_flag = p_H264_Dpb->dpb_param.l.data[ + FIXED_FRAME_RATE_FLAG]; + p_H264_Dpb->num_units_in_tick = + p_H264_Dpb->dpb_param.l.data[NUM_UNITS_IN_TICK]; + p_H264_Dpb->time_scale = p_H264_Dpb->dpb_param.l.data[TIME_SCALE] | + (p_H264_Dpb->dpb_param.l.data[TIME_SCALE + 1] << 16); + /**/ + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s return\n", __func__); +} + +static void decode_poc(struct VideoParameters *p_Vid, struct Slice *pSlice) +{ + struct h264_dpb_stru *p_H264_Dpb = container_of(p_Vid, + struct h264_dpb_stru, mVideo); + struct SPSParameters *active_sps = p_Vid->active_sps; + int i; + /* for POC mode 0: */ + unsigned int MaxPicOrderCntLsb = (1 << + (active_sps->log2_max_pic_order_cnt_lsb_minus4 + 4)); + + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DEBUG_POC, + "%s:pic_order_cnt_type %d, idr_flag %d last_has_mmco_5 %d last_pic_bottom_field %d pic_order_cnt_lsb %d PrevPicOrderCntLsb %d\r\n", + __func__, + active_sps->pic_order_cnt_type, + pSlice->idr_flag, + p_Vid->last_has_mmco_5, + p_Vid->last_pic_bottom_field, + pSlice->pic_order_cnt_lsb, + p_Vid->PrevPicOrderCntLsb + ); + + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DEBUG_POC, + "%s:field_pic_flag %d, bottom_field_flag %d frame_num %d PreviousFrameNum %d PreviousFrameNumOffset %d ax_frame_num %d num_ref_frames_in_pic_order_cnt_cycle %d offset_for_non_ref_pic %d\r\n", + __func__, + pSlice->field_pic_flag, + pSlice->bottom_field_flag, + pSlice->frame_num, + p_Vid->PreviousFrameNum, + p_Vid->PreviousFrameNumOffset, + p_Vid->max_frame_num, + active_sps->num_ref_frames_in_pic_order_cnt_cycle, + active_sps->offset_for_non_ref_pic + ); + + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DEBUG_POC, + "%s: delta_pic_order_cnt %d %d nal_reference_idc %d\r\n", + __func__, + pSlice->delta_pic_order_cnt[0], pSlice->delta_pic_order_cnt[1], + pSlice->nal_reference_idc + ); + + + switch (active_sps->pic_order_cnt_type) { + case 0: /* POC MODE 0 */ + /* 1st */ + if (pSlice->idr_flag) { + p_Vid->PrevPicOrderCntMsb = 0; + p_Vid->PrevPicOrderCntLsb = 0; + } else { + if (p_Vid->last_has_mmco_5) { + if (p_Vid->last_pic_bottom_field) { + p_Vid->PrevPicOrderCntMsb = 0; + p_Vid->PrevPicOrderCntLsb = 0; + } else { + p_Vid->PrevPicOrderCntMsb = 0; + p_Vid->PrevPicOrderCntLsb = + pSlice->toppoc; + } + } + } + /* Calculate the MSBs of current picture */ + if (pSlice->pic_order_cnt_lsb < p_Vid->PrevPicOrderCntLsb && + (p_Vid->PrevPicOrderCntLsb - pSlice->pic_order_cnt_lsb) >= + (MaxPicOrderCntLsb / 2)) + pSlice->PicOrderCntMsb = p_Vid->PrevPicOrderCntMsb + + MaxPicOrderCntLsb; + else if (pSlice->pic_order_cnt_lsb > + p_Vid->PrevPicOrderCntLsb && + (pSlice->pic_order_cnt_lsb - + p_Vid->PrevPicOrderCntLsb) > + (MaxPicOrderCntLsb / 2)) + pSlice->PicOrderCntMsb = p_Vid->PrevPicOrderCntMsb - + MaxPicOrderCntLsb; + else + pSlice->PicOrderCntMsb = p_Vid->PrevPicOrderCntMsb; + + /* 2nd */ + if (pSlice->field_pic_flag == 0) { + /* frame pix */ + pSlice->toppoc = pSlice->PicOrderCntMsb + + pSlice->pic_order_cnt_lsb; + pSlice->bottompoc = pSlice->toppoc + + pSlice->delta_pic_order_cnt_bottom; + pSlice->ThisPOC = pSlice->framepoc = + (pSlice->toppoc < pSlice->bottompoc) ? + pSlice->toppoc : pSlice->bottompoc; + /* POC200301 */ + } else if (pSlice->bottom_field_flag == FALSE) { + /* top field */ + pSlice->ThisPOC = pSlice->toppoc = + pSlice->PicOrderCntMsb + + pSlice->pic_order_cnt_lsb; + } else { + /* bottom field */ + pSlice->ThisPOC = pSlice->bottompoc = + pSlice->PicOrderCntMsb + + pSlice->pic_order_cnt_lsb; + } + pSlice->framepoc = pSlice->ThisPOC; + + p_Vid->ThisPOC = pSlice->ThisPOC; + + /* if ( pSlice->frame_num != p_Vid->PreviousFrameNum) + * Seems redundant + */ + p_Vid->PreviousFrameNum = pSlice->frame_num; + + if (pSlice->nal_reference_idc) { + p_Vid->PrevPicOrderCntLsb = pSlice->pic_order_cnt_lsb; + p_Vid->PrevPicOrderCntMsb = pSlice->PicOrderCntMsb; + } + + break; + + case 1: /* POC MODE 1 */ + /* 1st */ + if (pSlice->idr_flag) { + p_Vid->FrameNumOffset = 0; /* first pix of IDRGOP */ + if (pSlice->frame_num) + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "frame_num not equal to zero in IDR picture %d", + -1020); + } else { + if (p_Vid->last_has_mmco_5) { + p_Vid->PreviousFrameNumOffset = 0; + p_Vid->PreviousFrameNum = 0; + } + if (pSlice->frame_num < p_Vid->PreviousFrameNum) { + /* not first pix of IDRGOP */ + p_Vid->FrameNumOffset = + p_Vid->PreviousFrameNumOffset + + p_Vid->max_frame_num; + } else { + p_Vid->FrameNumOffset = + p_Vid->PreviousFrameNumOffset; + } + } + + /* 2nd */ + if (active_sps->num_ref_frames_in_pic_order_cnt_cycle) + pSlice->AbsFrameNum = + p_Vid->FrameNumOffset + pSlice->frame_num; + else + pSlice->AbsFrameNum = 0; + if ((!pSlice->nal_reference_idc) && pSlice->AbsFrameNum > 0) + pSlice->AbsFrameNum--; + + /* 3rd */ + p_Vid->ExpectedDeltaPerPicOrderCntCycle = 0; + + if (active_sps->num_ref_frames_in_pic_order_cnt_cycle) + for (i = 0; i < (int) active_sps-> + num_ref_frames_in_pic_order_cnt_cycle; i++) { + p_Vid->ExpectedDeltaPerPicOrderCntCycle += + active_sps->offset_for_ref_frame[i]; + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DEBUG_POC, + "%s: offset_for_ref_frame %d\r\n", + __func__, + active_sps-> + offset_for_ref_frame[i]); + } + + if (pSlice->AbsFrameNum) { + p_Vid->PicOrderCntCycleCnt = + (pSlice->AbsFrameNum - 1) / + active_sps-> + num_ref_frames_in_pic_order_cnt_cycle; + p_Vid->FrameNumInPicOrderCntCycle = + (pSlice->AbsFrameNum - 1) % + active_sps-> + num_ref_frames_in_pic_order_cnt_cycle; + p_Vid->ExpectedPicOrderCnt = + p_Vid->PicOrderCntCycleCnt * + p_Vid->ExpectedDeltaPerPicOrderCntCycle; + for (i = 0; i <= (int)p_Vid-> + FrameNumInPicOrderCntCycle; i++) { + p_Vid->ExpectedPicOrderCnt += + active_sps->offset_for_ref_frame[i]; + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DEBUG_POC, + "%s: offset_for_ref_frame %d\r\n", + __func__, + active_sps-> + offset_for_ref_frame[i]); + } + } else + p_Vid->ExpectedPicOrderCnt = 0; + + if (!pSlice->nal_reference_idc) + p_Vid->ExpectedPicOrderCnt += + active_sps->offset_for_non_ref_pic; + + if (pSlice->field_pic_flag == 0) { + /* frame pix */ + pSlice->toppoc = p_Vid->ExpectedPicOrderCnt + + pSlice->delta_pic_order_cnt[0]; + pSlice->bottompoc = pSlice->toppoc + + active_sps->offset_for_top_to_bottom_field + + pSlice->delta_pic_order_cnt[1]; + pSlice->ThisPOC = pSlice->framepoc = + (pSlice->toppoc < pSlice->bottompoc) ? + pSlice->toppoc : pSlice->bottompoc; + /* POC200301 */ + } else if (pSlice->bottom_field_flag == FALSE) { + /* top field */ + pSlice->ThisPOC = pSlice->toppoc = + p_Vid->ExpectedPicOrderCnt + + pSlice->delta_pic_order_cnt[0]; + } else { + /* bottom field */ + pSlice->ThisPOC = pSlice->bottompoc = + p_Vid->ExpectedPicOrderCnt + + active_sps->offset_for_top_to_bottom_field + + pSlice->delta_pic_order_cnt[0]; + } + pSlice->framepoc = pSlice->ThisPOC; + + p_Vid->PreviousFrameNum = pSlice->frame_num; + p_Vid->PreviousFrameNumOffset = p_Vid->FrameNumOffset; + + break; + + + case 2: /* POC MODE 2 */ + if (pSlice->idr_flag) { /* IDR picture */ + p_Vid->FrameNumOffset = 0; /* first pix of IDRGOP */ + pSlice->ThisPOC = pSlice->framepoc = pSlice->toppoc = + pSlice->bottompoc = 0; + if (pSlice->frame_num) + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "frame_num not equal to zero in IDR picture %d", + -1020); + } else { + if (p_Vid->last_has_mmco_5) { + p_Vid->PreviousFrameNum = 0; + p_Vid->PreviousFrameNumOffset = 0; + } + if (pSlice->frame_num < p_Vid->PreviousFrameNum) + p_Vid->FrameNumOffset = + p_Vid->PreviousFrameNumOffset + + p_Vid->max_frame_num; + else + p_Vid->FrameNumOffset = + p_Vid->PreviousFrameNumOffset; + + pSlice->AbsFrameNum = p_Vid->FrameNumOffset + + pSlice->frame_num; + if (!pSlice->nal_reference_idc) + pSlice->ThisPOC = + (2 * pSlice->AbsFrameNum - 1); + else + pSlice->ThisPOC = (2 * pSlice->AbsFrameNum); + + if (pSlice->field_pic_flag == 0) + pSlice->toppoc = pSlice->bottompoc = + pSlice->framepoc = pSlice->ThisPOC; + else if (pSlice->bottom_field_flag == FALSE) + pSlice->toppoc = pSlice->framepoc = + pSlice->ThisPOC; + else + pSlice->bottompoc = pSlice->framepoc = + pSlice->ThisPOC; + } + + p_Vid->PreviousFrameNum = pSlice->frame_num; + p_Vid->PreviousFrameNumOffset = p_Vid->FrameNumOffset; + break; + + + default: + /* error must occurs */ + /* assert( 1==0 ); */ + break; + } +} + +void fill_frame_num_gap(struct VideoParameters *p_Vid, struct Slice *currSlice) +{ + struct h264_dpb_stru *p_H264_Dpb = + container_of(p_Vid, struct h264_dpb_stru, mVideo); + struct SPSParameters *active_sps = p_Vid->active_sps; + int CurrFrameNum; + int UnusedShortTermFrameNum; + struct StorablePicture *picture = NULL; + int tmp1 = currSlice->delta_pic_order_cnt[0]; + int tmp2 = currSlice->delta_pic_order_cnt[1]; + int ret; + + currSlice->delta_pic_order_cnt[0] = + currSlice->delta_pic_order_cnt[1] = 0; + + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "A gap in frame number is found, try to fill it.(pre_frame_num %d, max_frame_num %d\n", + p_Vid->pre_frame_num, p_Vid->max_frame_num + ); + + UnusedShortTermFrameNum = (p_Vid->pre_frame_num + 1) + % p_Vid->max_frame_num; + CurrFrameNum = currSlice->frame_num; /*p_Vid->frame_num;*/ + + while (CurrFrameNum != UnusedShortTermFrameNum) { + /*picture = alloc_storable_picture + *(p_Vid, FRAME, p_Vid->width, + *p_Vid->height, + *p_Vid->width_cr, + *p_Vid->height_cr, 1); + */ + picture = get_new_pic(p_H264_Dpb, + p_H264_Dpb->mSlice.structure, + /*p_Vid->width, p_Vid->height, + *p_Vid->width_cr, + p_Vid->height_cr,*/ 1); + + if (picture == NULL) { + struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB; + + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_ERROR, + "%s Error: get_new_pic return NULL\r\n", + __func__); + /*h264_debug_flag |= PRINT_FLAG_DUMP_DPB;*/ + dump_dpb(p_Dpb, 0); + return; + } + + picture->colocated_buf_index = -1; + picture->buf_spec_num = -1; + picture->buf_spec_is_alloced = 0; + + picture->coded_frame = 1; + picture->pic_num = UnusedShortTermFrameNum; + picture->frame_num = UnusedShortTermFrameNum; + picture->non_existing = 1; + picture->is_output = 1; + picture->used_for_reference = 1; + picture->adaptive_ref_pic_buffering_flag = 0; + #if (MVC_EXTENSION_ENABLE) + picture->view_id = currSlice->view_id; + #endif + + currSlice->frame_num = UnusedShortTermFrameNum; + if (active_sps->pic_order_cnt_type != 0) { + /*decode_poc(p_Vid, p_Vid->ppSliceList[0]);*/ + decode_poc(&p_H264_Dpb->mVideo, &p_H264_Dpb->mSlice); + } + picture->top_poc = currSlice->toppoc; + picture->bottom_poc = currSlice->bottompoc; + picture->frame_poc = currSlice->framepoc; + picture->poc = currSlice->framepoc; + + ret = store_picture_in_dpb(p_H264_Dpb, picture, 0); + if (ret == -1) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_ERROR, + "%s Error: store_picture_in_dpb failed, break\n", + __func__); + release_picture(p_H264_Dpb, picture); + bufmgr_force_recover(p_H264_Dpb); + return; + } + + picture = NULL; + p_Vid->pre_frame_num = UnusedShortTermFrameNum; + UnusedShortTermFrameNum = + (UnusedShortTermFrameNum + 1) % + p_Vid->max_frame_num; + } + currSlice->delta_pic_order_cnt[0] = tmp1; + currSlice->delta_pic_order_cnt[1] = tmp2; + currSlice->frame_num = CurrFrameNum; +} + +void dpb_init_global(struct h264_dpb_stru *p_H264_Dpb, + int id, int actual_dpb_size, int max_reference_size) +{ + int i; + + init_dummy_fs(); + + memset(&p_H264_Dpb->mDPB, 0, sizeof(struct DecodedPictureBuffer)); + + memset(&p_H264_Dpb->mSlice, 0, sizeof(struct Slice)); + memset(&p_H264_Dpb->mVideo, 0, sizeof(struct VideoParameters)); + memset(&p_H264_Dpb->mSPS, 0, sizeof(struct SPSParameters)); + + for (i = 0; i < DPB_SIZE_MAX; i++) { + memset(&(p_H264_Dpb->mFrameStore[i]), 0, + sizeof(struct FrameStore)); + } + + for (i = 0; i < MAX_PIC_BUF_NUM; i++) { + memset(&(p_H264_Dpb->m_PIC[i]), 0, + sizeof(struct StorablePicture)); + p_H264_Dpb->m_PIC[i].index = i; + } + p_H264_Dpb->decoder_index = id; + + /* make sure dpb_init_global + *can be called during decoding + *(in DECODE_STATE_IDLE or DECODE_STATE_READY state) + */ + p_H264_Dpb->mDPB.size = actual_dpb_size; + p_H264_Dpb->max_reference_size = max_reference_size; + p_H264_Dpb->poc_even_odd_flag = 0; +} + +static void init_picture(struct h264_dpb_stru *p_H264_Dpb, + struct Slice *currSlice, + struct StorablePicture *dec_picture) +{ + /* struct VideoParameters *p_Vid = &(p_H264_Dpb->mVideo); */ + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s dec_picture %p\n", __func__, dec_picture); + dec_picture->top_poc = currSlice->toppoc; + dec_picture->bottom_poc = currSlice->bottompoc; + dec_picture->frame_poc = currSlice->framepoc; + switch (currSlice->structure) { + case TOP_FIELD: { + dec_picture->poc = currSlice->toppoc; + /* p_Vid->number *= 2; */ + break; + } + case BOTTOM_FIELD: { + dec_picture->poc = currSlice->bottompoc; + /* p_Vid->number = p_Vid->number * 2 + 1; */ + break; + } + case FRAME: { + dec_picture->poc = currSlice->framepoc; + break; + } + default: + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "p_Vid->structure not initialized %d\n", 235); + } + + /* dec_picture->slice_type = p_Vid->type; */ + dec_picture->used_for_reference = (currSlice->nal_reference_idc != 0); + dec_picture->idr_flag = currSlice->idr_flag; + dec_picture->no_output_of_prior_pics_flag = + currSlice->no_output_of_prior_pics_flag; + dec_picture->long_term_reference_flag = + currSlice->long_term_reference_flag; +#if 1 + dec_picture->adaptive_ref_pic_buffering_flag = + currSlice->adaptive_ref_pic_buffering_flag; + dec_picture->dec_ref_pic_marking_buffer = + &currSlice->dec_ref_pic_marking_buffer[0]; +#endif + /* currSlice->dec_ref_pic_marking_buffer = NULL; */ + + /* dec_picture->mb_aff_frame_flag = currSlice->mb_aff_frame_flag; */ + /* dec_picture->PicWidthInMbs = p_Vid->PicWidthInMbs; */ + + /* p_Vid->get_mb_block_pos = + * dec_picture->mb_aff_frame_flag ? get_mb_block_pos_mbaff : + * get_mb_block_pos_normal; + */ + /* p_Vid->getNeighbour = + * dec_picture->mb_aff_frame_flag ? getAffNeighbour : + * getNonAffNeighbour; + */ + + dec_picture->pic_num = currSlice->frame_num; + dec_picture->frame_num = currSlice->frame_num; + + /* dec_picture->recovery_frame = + * (unsigned int) ((int) currSlice->frame_num == + * p_Vid->recovery_frame_num); + */ + + dec_picture->coded_frame = (currSlice->structure == FRAME); + + /* dec_picture->chroma_format_idc = active_sps->chroma_format_idc; */ + + /* dec_picture->frame_mbs_only_flag = + * active_sps->frame_mbs_only_flag; + */ + /* dec_picture->frame_cropping_flag = + * active_sps->frame_cropping_flag; + */ + + if ((currSlice->picture_structure_mmco & 0x3) == 3) { + dec_picture->mb_aff_frame_flag = 1; + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s, picture_structure_mmco is %x, set mb_aff_frame_flag to 1\n", + __func__, + currSlice->picture_structure_mmco); + } + +} + +void dump_pic(struct h264_dpb_stru *p_H264_Dpb) +{ + int ii; + struct StorablePicture *pic; + for (ii = 0; ii < MAX_PIC_BUF_NUM; ii++) { + pic = &(p_H264_Dpb->m_PIC[ii]); + if (pic->is_used) { + dpb_print(p_H264_Dpb->decoder_index, 0, + "pic(%d,%d) poc %d is_used %d bufspec %d colbuf %d for_ref %d long_term %d pre_out %d output %d nonexist %d data_flag 0x%x\n", + ii, pic->index, + pic->poc, + pic->is_used, + pic->buf_spec_num, + pic->colocated_buf_index, + pic->used_for_reference, + pic->is_long_term, + pic->pre_output, + pic->is_output, + pic->non_existing, + pic->data_flag); + } + } +} + +/* +static void is_pic_used_by_dpb(struct h264_dpb_stru *p_H264_Dpb, + struct StorablePicture *pic) +{ + struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB; + unsigned i; + for (i = 0; i < p_Dpb->used_size; i++) { + if (p_Dpb->fs[i]->top_field == pic || + p_Dpb->fs[i]->bottom_field == pic || + p_Dpb->fs[i]->frame == pic + ) + break; + } + if (i < p_Dpb->used_size) + return 1; + return 0; +} +*/ + +static struct StorablePicture *get_new_pic(struct h264_dpb_stru *p_H264_Dpb, + enum PictureStructure structure, unsigned char is_output) +{ + struct StorablePicture *s = NULL; + struct StorablePicture *pic; + struct VideoParameters *p_Vid = &(p_H264_Dpb->mVideo); + /* recycle un-used pic */ + int ii = 0; + + for (ii = 0; ii < MAX_PIC_BUF_NUM; ii++) { + pic = &(p_H264_Dpb->m_PIC[ii]); + if (pic->is_used == 0) { + pic->is_used = 1; + s = pic; + break; + } + } + + if (s) { + s->buf_spec_is_alloced = 0; + s->pic_num = 0; + s->frame_num = 0; + s->long_term_frame_idx = 0; + s->long_term_pic_num = 0; + s->used_for_reference = 0; + s->is_long_term = 0; + s->non_existing = 0; + s->is_output = 0; + s->pre_output = 0; + s->max_slice_id = 0; + s->data_flag &= ~(ERROR_FLAG | NODISP_FLAG | MAYBE_ERROR_FLAG); +#if (MVC_EXTENSION_ENABLE) + s->view_id = -1; +#endif + + s->structure = structure; + +#if 0 + s->size_x = size_x; + s->size_y = size_y; + s->size_x_cr = size_x_cr; + s->size_y_cr = size_y_cr; + s->size_x_m1 = size_x - 1; + s->size_y_m1 = size_y - 1; + s->size_x_cr_m1 = size_x_cr - 1; + s->size_y_cr_m1 = size_y_cr - 1; + + s->top_field = p_Vid->no_reference_picture; + s->bottom_field = p_Vid->no_reference_picture; + s->frame = p_Vid->no_reference_picture; +#endif + /* s->dec_ref_pic_marking_buffer = NULL; */ + + s->coded_frame = 0; + s->mb_aff_frame_flag = 0; + + s->top_poc = s->bottom_poc = s->poc = 0; + s->seiHasTone_mapping = 0; + s->frame_mbs_only_flag = p_Vid->active_sps->frame_mbs_only_flag; + + if (!p_Vid->active_sps->frame_mbs_only_flag && + structure != FRAME) { + int i, j; + + for (j = 0; j < MAX_NUM_SLICES; j++) { + for (i = 0; i < 2; i++) { + /* s->listX[j][i] = + *calloc(MAX_LIST_SIZE, + *sizeof (struct StorablePicture *)); + *+1 for reordering ??? + + *if (NULL == s->listX[j][i]) + *no_mem_exit("alloc_storable_picture: + *s->listX[i]"); + */ + } + } + } + } else + p_H264_Dpb->buf_alloc_fail = 1; + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s %p\n", __func__, s); + return s; +} + +static void free_picture(struct h264_dpb_stru *p_H264_Dpb, + struct StorablePicture *pic) +{ + if (pic == NULL || pic->index < 0 || + pic->index >= MAX_PIC_BUF_NUM) + return; + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s %p %d\n", __func__, pic, pic->index); + /* assert(pic->indexm_PIC[pic->index].is_used = 0; +} + +static void gen_field_ref_ids(struct VideoParameters *p_Vid, + struct StorablePicture *p) +{ + int i, j; + struct h264_dpb_stru *p_H264_Dpb = container_of(p_Vid, + struct h264_dpb_stru, mVideo); + /* ! Generate Frame parameters from field information. */ + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s\n", __func__); + + /* copy the list; */ + for (j = 0; j < p_Vid->iSliceNumOfCurrPic; j++) { + if (p->listX[j][LIST_0]) { + p->listXsize[j][LIST_0] = + p_Vid->ppSliceList[j]->listXsize[LIST_0]; + for (i = 0; i < p->listXsize[j][LIST_0]; i++) + p->listX[j][LIST_0][i] = + p_Vid->ppSliceList[j]->listX[LIST_0][i]; + } + if (p->listX[j][LIST_1]) { + p->listXsize[j][LIST_1] = + p_Vid->ppSliceList[j]->listXsize[LIST_1]; + for (i = 0; i < p->listXsize[j][LIST_1]; i++) + p->listX[j][LIST_1][i] = + p_Vid->ppSliceList[j]->listX[LIST_1][i]; + } + } +} + +static void init_dpb(struct h264_dpb_stru *p_H264_Dpb, int type) +{ + unsigned int i; + struct VideoParameters *p_Vid = &p_H264_Dpb->mVideo; + struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB; + struct SPSParameters *active_sps = &p_H264_Dpb->mSPS; + + p_Vid->active_sps = active_sps; + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s\n", __func__); + + p_Dpb->p_Vid = p_Vid; + if (p_Dpb->init_done) { + /* free_dpb(p_Dpb); */ + if (p_Vid->no_reference_picture) { + free_picture(p_H264_Dpb, p_Vid->no_reference_picture); + p_Vid->no_reference_picture = NULL; + } + p_Dpb->init_done = 0; + } + + /* p_Dpb->size = 10; //active_sps->max_dpb_size; //16; + * getDpbSize(p_Vid, active_sps) + + * p_Vid->p_Inp->dpb_plus[type==2? 1: 0]; + * p_Dpb->size = active_sps->max_dpb_size; //16; + * getDpbSize(p_Vid, active_sps) + + * p_Vid->p_Inp->dpb_plus[type==2? 1: 0]; + * p_Dpb->size initialzie in vh264.c + */ + p_Dpb->num_ref_frames = active_sps->num_ref_frames; + /* p_Dpb->num_ref_frames initialzie in vh264.c */ + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s dpb_size is %d num_ref_frames = %d (%d)\n", + __func__, p_Dpb->size, + p_Dpb->num_ref_frames, + active_sps->num_ref_frames); + if (active_sps->num_ref_frames == 0xffff) { + dpb_print(p_H264_Dpb->decoder_index, 0, + "!!!Warning, num_ref_frames = %d is invalid\n", + active_sps->num_ref_frames); + } + +#if 0 + /* ??? */ +#if (MVC_EXTENSION_ENABLE) + if ((unsigned int)active_sps->max_dec_frame_buffering < + active_sps->num_ref_frames) { +#else + if (p_Dpb->size < active_sps->num_ref_frames) { +#endif + error( + "DPB size at specified level is smaller than the specified number of reference frames. This is not allowed.\n", + 1000); + } +#endif + + p_Dpb->used_size = 0; + p_Dpb->last_picture = NULL; + + p_Dpb->ref_frames_in_buffer = 0; + p_Dpb->ltref_frames_in_buffer = 0; + +#if 0 + p_Dpb->fs = calloc(p_Dpb->size, sizeof(struct FrameStore *)); + if (NULL == p_Dpb->fs) + no_mem_exit("init_dpb: p_Dpb->fs"); + + p_Dpb->fs_ref = calloc(p_Dpb->size, sizeof(struct FrameStore *)); + if (NULL == p_Dpb->fs_ref) + no_mem_exit("init_dpb: p_Dpb->fs_ref"); + + p_Dpb->fs_ltref = calloc(p_Dpb->size, sizeof(struct FrameStore *)); + if (NULL == p_Dpb->fs_ltref) + no_mem_exit("init_dpb: p_Dpb->fs_ltref"); +#endif + +#if (MVC_EXTENSION_ENABLE) + p_Dpb->fs_ilref = calloc(1, sizeof(struct FrameStore *)); + if (NULL == p_Dpb->fs_ilref) + no_mem_exit("init_dpb: p_Dpb->fs_ilref"); +#endif + + for (i = 0; i < p_Dpb->size; i++) { + p_Dpb->fs[i] = &(p_H264_Dpb->mFrameStore[i]); + /* alloc_frame_store(); */ + p_Dpb->fs[i]->index = i; + p_Dpb->fs_ref[i] = NULL; + p_Dpb->fs_ltref[i] = NULL; + p_Dpb->fs[i]->layer_id = 0; /* MVC_INIT_VIEW_ID; */ +#if (MVC_EXTENSION_ENABLE) + p_Dpb->fs[i]->view_id = MVC_INIT_VIEW_ID; + p_Dpb->fs[i]->inter_view_flag[0] = + p_Dpb->fs[i]->inter_view_flag[1] = 0; + p_Dpb->fs[i]->anchor_pic_flag[0] = + p_Dpb->fs[i]->anchor_pic_flag[1] = 0; +#endif + } +#if (MVC_EXTENSION_ENABLE) + if (type == 2) { + p_Dpb->fs_ilref[0] = alloc_frame_store(); + /* These may need some cleanups */ + p_Dpb->fs_ilref[0]->view_id = MVC_INIT_VIEW_ID; + p_Dpb->fs_ilref[0]->inter_view_flag[0] = + p_Dpb->fs_ilref[0]->inter_view_flag[1] = 0; + p_Dpb->fs_ilref[0]->anchor_pic_flag[0] = + p_Dpb->fs_ilref[0]->anchor_pic_flag[1] = 0; + /* given that this is in a different buffer, + * do we even need proc_flag anymore? + */ + } else + p_Dpb->fs_ilref[0] = NULL; +#endif + + /* + *for (i = 0; i < 6; i++) + *{ + *currSlice->listX[i] = + * calloc(MAX_LIST_SIZE, sizeof (struct StorablePicture *)); + * +1 for reordering + *if (NULL == currSlice->listX[i]) + *no_mem_exit("init_dpb: currSlice->listX[i]"); + *} + */ + /* allocate a dummy storable picture */ + if (!p_Vid->no_reference_picture) { + p_Vid->no_reference_picture = get_new_pic(p_H264_Dpb, + FRAME, + /*p_Vid->width, p_Vid->height, + *p_Vid->width_cr, p_Vid->height_cr, + */ + 1); + p_Vid->no_reference_picture->top_field = + p_Vid->no_reference_picture; + p_Vid->no_reference_picture->bottom_field = + p_Vid->no_reference_picture; + p_Vid->no_reference_picture->frame = + p_Vid->no_reference_picture; + } + p_Dpb->last_output_poc = INT_MIN; + +#if (MVC_EXTENSION_ENABLE) + p_Dpb->last_output_view_id = -1; +#endif + + p_Vid->last_has_mmco_5 = 0; + + init_colocate_buf(p_H264_Dpb, p_H264_Dpb->max_reference_size); + + p_Dpb->init_done = 1; + +#if 0 +/* ??? */ + /* picture error concealment */ + if (p_Vid->conceal_mode != 0 && !p_Vid->last_out_fs) + p_Vid->last_out_fs = alloc_frame_store(); +#endif +} + +static void dpb_split_field(struct h264_dpb_stru *p_H264_Dpb, + struct FrameStore *fs) +{ + struct StorablePicture *fs_top = NULL, *fs_btm = NULL; + struct StorablePicture *frame = fs->frame; + + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s %p %p\n", __func__, fs, frame); + + fs->poc = frame->poc; + + if (!frame->frame_mbs_only_flag) { + fs_top = fs->top_field = get_new_pic(p_H264_Dpb, + TOP_FIELD, + /* frame->size_x, frame->size_y, + *frame->size_x_cr, frame->size_y_cr, + */ + 1); + fs_btm = fs->bottom_field = get_new_pic(p_H264_Dpb, + BOTTOM_FIELD, + /*frame->size_x, frame->size_y, + *frame->size_x_cr, frame->size_y_cr, + */ + 1); + if (fs_top == NULL || fs_btm == NULL) + return; +#if 1 +/* rain */ + fs_top->buf_spec_num = frame->buf_spec_num; + fs_btm->buf_spec_num = frame->buf_spec_num; + + fs_top->colocated_buf_index = frame->colocated_buf_index; + fs_btm->colocated_buf_index = frame->colocated_buf_index; + + fs_top->data_flag = frame->data_flag; + fs_btm->data_flag = frame->data_flag; +#endif + fs_top->poc = frame->top_poc; + fs_btm->poc = frame->bottom_poc; + +#if (MVC_EXTENSION_ENABLE) + fs_top->view_id = frame->view_id; + fs_btm->view_id = frame->view_id; +#endif + + fs_top->frame_poc = frame->frame_poc; + + fs_top->bottom_poc = fs_btm->bottom_poc = frame->bottom_poc; + fs_top->top_poc = fs_btm->top_poc = frame->top_poc; + fs_btm->frame_poc = frame->frame_poc; + + fs_top->used_for_reference = fs_btm->used_for_reference + = frame->used_for_reference; + fs_top->is_long_term = fs_btm->is_long_term + = frame->is_long_term; + fs->long_term_frame_idx = fs_top->long_term_frame_idx + = fs_btm->long_term_frame_idx + = frame->long_term_frame_idx; + + fs_top->coded_frame = fs_btm->coded_frame = 1; + fs_top->mb_aff_frame_flag = fs_btm->mb_aff_frame_flag + = frame->mb_aff_frame_flag; + + frame->top_field = fs_top; + frame->bottom_field = fs_btm; + frame->frame = frame; + fs_top->bottom_field = fs_btm; + fs_top->frame = frame; + fs_top->top_field = fs_top; + fs_btm->top_field = fs_top; + fs_btm->frame = frame; + fs_btm->bottom_field = fs_btm; + +#if (MVC_EXTENSION_ENABLE) + fs_top->view_id = fs_btm->view_id = fs->view_id; + fs_top->inter_view_flag = fs->inter_view_flag[0]; + fs_btm->inter_view_flag = fs->inter_view_flag[1]; +#endif + + fs_top->chroma_format_idc = fs_btm->chroma_format_idc = + frame->chroma_format_idc; + fs_top->iCodingType = fs_btm->iCodingType = frame->iCodingType; + } else { + fs->top_field = NULL; + fs->bottom_field = NULL; + frame->top_field = NULL; + frame->bottom_field = NULL; + frame->frame = frame; + } + +} + + +static void dpb_combine_field(struct h264_dpb_stru *p_H264_Dpb, + struct FrameStore *fs) +{ + + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s\n", __func__); + + if (!fs->frame) { + fs->frame = get_new_pic(p_H264_Dpb, + FRAME, + /* fs->top_field->size_x, fs->top_field->size_y*2, + *fs->top_field->size_x_cr, fs->top_field->size_y_cr*2, + */ + 1); + } + if (!fs->frame) + return; +#if 1 +/* rain */ + fs->frame->buf_spec_num = fs->top_field->buf_spec_num; + fs->frame->colocated_buf_index = fs->top_field->colocated_buf_index; + fs->frame->data_flag = fs->top_field->data_flag; + if (fs->bottom_field) + fs->frame->data_flag |= (fs->bottom_field->data_flag & 0xf0); +#endif + + + fs->poc = fs->frame->poc = fs->frame->frame_poc = imin( + fs->top_field->poc, fs->bottom_field->poc); + + fs->bottom_field->frame_poc = fs->top_field->frame_poc = fs->frame->poc; + + fs->bottom_field->top_poc = fs->frame->top_poc = fs->top_field->poc; + fs->top_field->bottom_poc = fs->frame->bottom_poc = + fs->bottom_field->poc; + + fs->frame->used_for_reference = (fs->top_field->used_for_reference && + fs->bottom_field->used_for_reference); + fs->frame->is_long_term = (fs->top_field->is_long_term && + fs->bottom_field->is_long_term); + + if (fs->frame->is_long_term) + fs->frame->long_term_frame_idx = fs->long_term_frame_idx; + + fs->frame->top_field = fs->top_field; + fs->frame->bottom_field = fs->bottom_field; + fs->frame->frame = fs->frame; + + fs->frame->coded_frame = 0; + + fs->frame->chroma_format_idc = fs->top_field->chroma_format_idc; + fs->frame->frame_cropping_flag = fs->top_field->frame_cropping_flag; + if (fs->frame->frame_cropping_flag) { + fs->frame->frame_crop_top_offset = + fs->top_field->frame_crop_top_offset; + fs->frame->frame_crop_bottom_offset = + fs->top_field->frame_crop_bottom_offset; + fs->frame->frame_crop_left_offset = + fs->top_field->frame_crop_left_offset; + fs->frame->frame_crop_right_offset = + fs->top_field->frame_crop_right_offset; + } + + fs->top_field->frame = fs->bottom_field->frame = fs->frame; + fs->top_field->top_field = fs->top_field; + fs->top_field->bottom_field = fs->bottom_field; + fs->bottom_field->top_field = fs->top_field; + fs->bottom_field->bottom_field = fs->bottom_field; + + /**/ +#if (MVC_EXTENSION_ENABLE) + fs->frame->view_id = fs->view_id; +#endif + fs->frame->iCodingType = fs->top_field->iCodingType; + /* FIELD_CODING ;*/ +} + +static void calculate_frame_no(struct VideoParameters *p_Vid, + struct StorablePicture *p) +{ +#if 0 +/* ??? */ + InputParameters *p_Inp = p_Vid->p_Inp; + /* calculate frame number */ + int psnrPOC = p_Vid->active_sps->mb_adaptive_frame_field_flag ? + p->poc / (p_Inp->poc_scale) : p->poc / (p_Inp->poc_scale); + + if (psnrPOC == 0) { /* && p_Vid->psnr_number) */ + p_Vid->idr_psnr_number = + p_Vid->g_nFrame * p_Vid->ref_poc_gap / (p_Inp->poc_scale); + } + p_Vid->psnr_number = imax(p_Vid->psnr_number, + p_Vid->idr_psnr_number + psnrPOC); + + p_Vid->frame_no = p_Vid->idr_psnr_number + psnrPOC; +#endif +} + +static void insert_picture_in_dpb(struct h264_dpb_stru *p_H264_Dpb, + struct FrameStore *fs, + struct StorablePicture *p, + unsigned char data_flag) +{ + struct VideoParameters *p_Vid = &p_H264_Dpb->mVideo; + /* InputParameters *p_Inp = p_Vid->p_Inp; + * dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + * "insert (%s) pic with frame_num #%d, poc %d\n", + * (p->structure == FRAME)?"FRAME": + * (p->structure == TOP_FIELD)?"TOP_FIELD": + * "BOTTOM_FIELD", p->pic_num, p->poc); + * assert (p!=NULL); + * assert (fs!=NULL); + */ + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s %p %p\n", __func__, fs, p); +#if 1 +/* rain */ +/* p->buf_spec_num = fs->index; */ + p->data_flag = data_flag; + fs->data_flag |= data_flag; + fs->buf_spec_num = p->buf_spec_num; + fs->colocated_buf_index = p->colocated_buf_index; +#endif + switch (p->structure) { + case FRAME: + fs->frame = p; + fs->is_used = 3; + if (p->used_for_reference) { + fs->is_reference = 3; + fs->is_orig_reference = 3; + if (p->is_long_term) { + fs->is_long_term = 3; + fs->long_term_frame_idx = + p->long_term_frame_idx; + } + } + fs->layer_id = p->layer_id; +#if (MVC_EXTENSION_ENABLE) + fs->view_id = p->view_id; + fs->inter_view_flag[0] = fs->inter_view_flag[1] = + p->inter_view_flag; + fs->anchor_pic_flag[0] = fs->anchor_pic_flag[1] = + p->anchor_pic_flag; +#endif + /* generate field views */ + /* return; */ + dpb_split_field(p_H264_Dpb, fs); + /* return; */ + break; + case TOP_FIELD: + fs->top_field = p; + fs->is_used |= 1; + fs->layer_id = p->layer_id; +#if (MVC_EXTENSION_ENABLE) + fs->view_id = p->view_id; + fs->inter_view_flag[0] = p->inter_view_flag; + fs->anchor_pic_flag[0] = p->anchor_pic_flag; +#endif + if (p->used_for_reference) { + fs->is_reference |= 1; + fs->is_orig_reference |= 1; + if (p->is_long_term) { + fs->is_long_term |= 1; + fs->long_term_frame_idx = + p->long_term_frame_idx; + } + } + if (fs->is_used == 3) { + /* generate frame view */ + dpb_combine_field(p_H264_Dpb, fs); + } else { + fs->poc = p->poc; + } + gen_field_ref_ids(p_Vid, p); + break; + case BOTTOM_FIELD: + fs->bottom_field = p; + fs->is_used |= 2; + fs->layer_id = p->layer_id; +#if (MVC_EXTENSION_ENABLE) + fs->view_id = p->view_id; + fs->inter_view_flag[1] = p->inter_view_flag; + fs->anchor_pic_flag[1] = p->anchor_pic_flag; +#endif + if (p->used_for_reference) { + fs->is_reference |= 2; + fs->is_orig_reference |= 2; + if (p->is_long_term) { + fs->is_long_term |= 2; + fs->long_term_frame_idx = + p->long_term_frame_idx; + } + } + if (fs->is_used == 3) { + /* generate frame view */ + dpb_combine_field(p_H264_Dpb, fs); + } else { + fs->poc = p->poc; + } + gen_field_ref_ids(p_Vid, p); + break; + } + fs->frame_num = p->pic_num; + fs->recovery_frame = p->recovery_frame; + + fs->is_output = p->is_output; + fs->pre_output = p->pre_output; + + if (fs->is_used == 3) { + calculate_frame_no(p_Vid, p); +#if 0 +/* ??? */ + if (-1 != p_Vid->p_ref && !p_Inp->silent) + find_snr(p_Vid, fs->frame, &p_Vid->p_ref); +#endif + } + + fs->pts = p->pts; + fs->pts64 = p->pts64; +} + +void reset_frame_store(struct h264_dpb_stru *p_H264_Dpb, + struct FrameStore *f) +{ + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s\n", __func__); + + if (f) { + if (f->frame) { + free_picture(p_H264_Dpb, f->frame); + f->frame = NULL; + } + if (f->top_field) { + free_picture(p_H264_Dpb, f->top_field); + f->top_field = NULL; + } + if (f->bottom_field) { + free_picture(p_H264_Dpb, f->bottom_field); + f->bottom_field = NULL; + } + + /**/ + f->is_used = 0; + f->is_reference = 0; + f->is_long_term = 0; + f->is_orig_reference = 0; + + f->is_output = 0; + f->pre_output = 0; + + f->frame = NULL; + f->top_field = NULL; + f->bottom_field = NULL; + + /* free(f); */ + } +} + +static void unmark_for_reference(struct DecodedPictureBuffer *p_Dpb, + struct FrameStore *fs) +{ + struct h264_dpb_stru *p_H264_Dpb = container_of(p_Dpb, + struct h264_dpb_stru, mDPB); + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s %p %p %p %p\n", __func__, + fs, fs->frame, fs->top_field, fs->bottom_field); + /* return; */ + if (fs->is_used & 1) { + if (fs->top_field) + fs->top_field->used_for_reference = 0; + } + if (fs->is_used & 2) { + if (fs->bottom_field) + fs->bottom_field->used_for_reference = 0; + } + if (fs->is_used == 3) { + if (fs->top_field && fs->bottom_field) { + fs->top_field->used_for_reference = 0; + fs->bottom_field->used_for_reference = 0; + } + fs->frame->used_for_reference = 0; + } + + fs->is_reference = 0; + +} + +int get_long_term_flag_by_buf_spec_num(struct h264_dpb_stru *p_H264_Dpb, + int buf_spec_num) +{ + struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB; + unsigned int i; + + for (i = 0; i < p_Dpb->used_size; i++) { + if (p_Dpb->fs[i]->buf_spec_num == buf_spec_num) + return p_Dpb->fs[i]->is_long_term; + } + return -1; +} + +static void update_pic_num(struct h264_dpb_stru *p_H264_Dpb) +{ + unsigned int i; + struct Slice *currSlice = &p_H264_Dpb->mSlice; + struct VideoParameters *p_Vid = currSlice->p_Vid; + struct DecodedPictureBuffer *p_Dpb = currSlice->p_Dpb; + struct SPSParameters *active_sps = p_Vid->active_sps; + int add_top = 0, add_bottom = 0; + int max_frame_num = 1 << (active_sps->log2_max_frame_num_minus4 + 4); + + if (currSlice->structure == FRAME) { + for (i = 0; i < p_Dpb->ref_frames_in_buffer; i++) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i] == NULL || + p_Dpb->fs_ref[i]->frame == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p_Dpb->fs_ref[i]->is_used == 3) { + if ((p_Dpb->fs_ref[i]->frame-> + used_for_reference) && + (!p_Dpb->fs_ref[i]->frame-> + is_long_term)) { + if (p_Dpb->fs_ref[i]->frame_num > + currSlice->frame_num) { + p_Dpb->fs_ref[i]-> + frame_num_wrap = + p_Dpb->fs_ref[i]->frame_num + - max_frame_num; + } else { + p_Dpb->fs_ref[i]-> + frame_num_wrap = + p_Dpb->fs_ref[i]->frame_num; + } + p_Dpb->fs_ref[i]->frame->pic_num = + p_Dpb->fs_ref[i]->frame_num_wrap; + } + } + } + /* update long_term_pic_num */ + for (i = 0; i < p_Dpb->ltref_frames_in_buffer; i++) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ltref[i] == NULL || + p_Dpb->fs_ltref[i]->frame == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p_Dpb->fs_ltref[i]->is_used == 3) { + if (p_Dpb->fs_ltref[i]->frame->is_long_term) { + p_Dpb->fs_ltref[i]->frame-> + long_term_pic_num = + p_Dpb->fs_ltref[i]->frame-> + long_term_frame_idx; + } + } + } + } else { + if (currSlice->structure == TOP_FIELD) { + add_top = 1; + add_bottom = 0; + } else { + add_top = 0; + add_bottom = 1; + } + + for (i = 0; i < p_Dpb->ref_frames_in_buffer; i++) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i] == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p_Dpb->fs_ref[i]->is_reference) { + if (p_Dpb->fs_ref[i]->frame_num > currSlice-> + frame_num) { + p_Dpb->fs_ref[i]->frame_num_wrap = + p_Dpb->fs_ref[i]->frame_num - + max_frame_num; + } else { + p_Dpb->fs_ref[i]->frame_num_wrap = + p_Dpb->fs_ref[i]->frame_num; + } + if (p_Dpb->fs_ref[i]->is_reference & 1) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i]->top_field + == NULL) { + p_H264_Dpb->dpb_error_flag = + __LINE__; + continue; + } +#endif + p_Dpb->fs_ref[i]->top_field-> + pic_num = (2 * p_Dpb->fs_ref[i]-> + frame_num_wrap) + add_top; + } + if (p_Dpb->fs_ref[i]->is_reference & 2) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i]->bottom_field + == NULL) { + p_H264_Dpb->dpb_error_flag = + __LINE__; + continue; + } +#endif + p_Dpb->fs_ref[i]->bottom_field-> + pic_num = (2 * p_Dpb->fs_ref[i]-> + frame_num_wrap) + add_bottom; + } + } + } + /* update long_term_pic_num */ + for (i = 0; i < p_Dpb->ltref_frames_in_buffer; i++) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ltref[i] == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p_Dpb->fs_ltref[i]->is_long_term & 1) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ltref[i]->top_field == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + p_Dpb->fs_ltref[i]->top_field-> + long_term_pic_num = 2 * + p_Dpb->fs_ltref[i]->top_field-> + long_term_frame_idx + add_top; + } + if (p_Dpb->fs_ltref[i]->is_long_term & 2) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ltref[i]->bottom_field == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + p_Dpb->fs_ltref[i]->bottom_field-> + long_term_pic_num = 2 * + p_Dpb->fs_ltref[i]->bottom_field-> + long_term_frame_idx + add_bottom; + } + } + } +} + +static void remove_frame_from_dpb(struct h264_dpb_stru *p_H264_Dpb, int pos) +{ + struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB; + struct FrameStore *fs = p_Dpb->fs[pos]; + struct FrameStore *tmp; + unsigned int i; + + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s pos %d %p\n", __func__, pos, fs); + + /* dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + * "remove frame with frame_num #%d\n", fs->frame_num); + */ + switch (fs->is_used) { + case 3: + free_picture(p_H264_Dpb, fs->frame); + free_picture(p_H264_Dpb, fs->top_field); + free_picture(p_H264_Dpb, fs->bottom_field); + fs->frame = NULL; + fs->top_field = NULL; + fs->bottom_field = NULL; + break; + case 2: + free_picture(p_H264_Dpb, fs->bottom_field); + fs->bottom_field = NULL; + break; + case 1: + free_picture(p_H264_Dpb, fs->top_field); + fs->top_field = NULL; + break; + case 0: + break; + default: + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "invalid frame store type %x", 500); + } + fs->data_flag = 0; + fs->is_used = 0; + fs->is_long_term = 0; + fs->is_reference = 0; + fs->is_orig_reference = 0; + + /* move empty framestore to end of buffer */ + tmp = p_Dpb->fs[pos]; + + for (i = pos; i < p_Dpb->used_size - 1; i++) + p_Dpb->fs[i] = p_Dpb->fs[i + 1]; + p_Dpb->fs[p_Dpb->used_size - 1] = tmp; + p_Dpb->used_size--; +} + +static int is_used_for_reference(struct FrameStore *fs) +{ + if (fs->is_reference) + return 1; + + if (fs->is_used == 3) { /* frame */ + if (fs->frame->used_for_reference) + return 1; + } + + if (fs->is_used & 1) { /* top field */ + if (fs->top_field) { + if (fs->top_field->used_for_reference) + return 1; + } + } + + if (fs->is_used & 2) { /* bottom field */ + if (fs->bottom_field) { + if (fs->bottom_field->used_for_reference) + return 1; + } + } + return 0; +} + +static int remove_unused_frame_from_dpb(struct h264_dpb_stru *p_H264_Dpb) +{ + unsigned int i; + struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB; + /* check for frames that were already output and no longer + * used for reference + */ + for (i = 0; i < p_Dpb->used_size; i++) { + if ((!is_used_for_reference(p_Dpb->fs[i])) && + (p_Dpb->fs[i]->colocated_buf_index >= 0)) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "release_colocate_buf[%d] for fs[%d]\n", + p_Dpb->fs[i]->colocated_buf_index, i); + + release_colocate_buf(p_H264_Dpb, + p_Dpb->fs[i]->colocated_buf_index); /* rain */ + p_Dpb->fs[i]->colocated_buf_index = -1; + } + } + + for (i = 0; i < p_Dpb->used_size; i++) { + if (p_Dpb->fs[i]->is_output && + (!is_used_for_reference(p_Dpb->fs[i]))) { + release_buf_spec_num(p_H264_Dpb->vdec, + p_Dpb->fs[i]->buf_spec_num); + p_Dpb->fs[i]->buf_spec_num = -1; + remove_frame_from_dpb(p_H264_Dpb, i); + + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "%s[%d]\n", + __func__, i); + + return 1; + } + } + return 0; +} + +static int unmark_one_error_out_frame(struct h264_dpb_stru *p_H264_Dpb) +{ + int ret = 0; + unsigned i; + struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB; + + for (i = 0; i < p_Dpb->used_size; i++) { + if (p_Dpb->fs[i]->is_output && + ((p_Dpb->fs[i]->data_flag & ERROR_FLAG) || + (p_Dpb->fs[i]->data_flag & NULL_FLAG)) + ) { + unmark_for_reference(p_Dpb, p_Dpb->fs[i]); + + ret = 1; + } + } + return ret; +} + +static int unmark_one_out_frame(struct h264_dpb_stru *p_H264_Dpb) +{ + int ret = 0; + unsigned i; + struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB; + + for (i = 0; i < p_Dpb->used_size; i++) { + if (p_Dpb->fs[i]->is_output) { + unmark_for_reference(p_Dpb, p_Dpb->fs[i]); + + ret = 1; + } + } + return ret; +} +/* + force_flag, + 1, remove one error buf (is_out is 1) if there is no un-used buf + 2, remove one buf (is_out is 1) if there is no un-used buf +*/ +void bufmgr_h264_remove_unused_frame(struct h264_dpb_stru *p_H264_Dpb, + u8 force_flag) +{ + struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB; + int ret = 0; + unsigned char removed_flag = 0; + do { + ret = remove_unused_frame_from_dpb(p_H264_Dpb); + if (ret != 0) + removed_flag = 1; + } while (ret != 0); + if (removed_flag) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "%s\r\n", __func__); + dump_dpb(p_Dpb, 0); + } else if (force_flag == 2) { + if (unmark_one_out_frame(p_H264_Dpb)) { + dpb_print(p_H264_Dpb->decoder_index, + 0, "%s, Warnning, force unmark one frame\r\n", + __func__); + remove_unused_frame_from_dpb(p_H264_Dpb); + dump_dpb(p_Dpb, 0); + } + } else if (force_flag == 1) { + if (unmark_one_error_out_frame(p_H264_Dpb)) { + dpb_print(p_H264_Dpb->decoder_index, + 0, "%s, unmark error frame\r\n", + __func__); + remove_unused_frame_from_dpb(p_H264_Dpb); + dump_dpb(p_Dpb, 0); + } + } +} + +#ifdef OUTPUT_BUFFER_IN_C +int is_there_unused_frame_from_dpb(struct DecodedPictureBuffer *p_Dpb) +{ + unsigned int i; + + /* check for frames that were already output and no longer + * used for reference + */ + for (i = 0; i < p_Dpb->used_size; i++) { + if (p_Dpb->fs[i]->is_output && + (!is_used_for_reference(p_Dpb->fs[i]))) { + return 1; + } + } + return 0; +} +#endif + +static void get_smallest_poc(struct DecodedPictureBuffer *p_Dpb, int *poc, + int *pos) +{ + unsigned int i; + struct h264_dpb_stru *p_H264_Dpb = container_of(p_Dpb, + struct h264_dpb_stru, mDPB); + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "%s\n", __func__); + if (p_Dpb->used_size < 1) { + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "Cannot determine smallest POC, DPB empty. %d\n", + 150); + } + + *pos = -1; + *poc = INT_MAX; + for (i = 0; i < p_Dpb->used_size; i++) { +#ifdef OUTPUT_BUFFER_IN_C + /* rain */ + if ((*poc > p_Dpb->fs[i]->poc) && + (!p_Dpb->fs[i]->is_output) && + (!p_Dpb->fs[i]->pre_output)) { +#else + if ((*poc > p_Dpb->fs[i]->poc) && (!p_Dpb->fs[i]->is_output)) { +#endif + *poc = p_Dpb->fs[i]->poc; + *pos = i; + } + } +} + +int output_frames(struct h264_dpb_stru *p_H264_Dpb, unsigned char flush_flag) +{ + int poc, pos; + struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB; + int i; + int none_displayed_num = 0; + unsigned char fast_output_flag = 0; + if (!flush_flag) { + for (i = 0; i < p_Dpb->used_size; i++) { + if ((!p_Dpb->fs[i]->is_output) && + (!p_Dpb->fs[i]->pre_output)) { + none_displayed_num++; + /*check poc even/odd*/ + if (p_H264_Dpb->poc_even_odd_flag == 0 && + p_H264_Dpb->decode_pic_count >= 3) + p_H264_Dpb->poc_even_odd_flag = 2; + if (p_Dpb->fs[i]->poc & 0x1) + p_H264_Dpb->poc_even_odd_flag = 1; + /**/ + + if ((p_H264_Dpb->fast_output_enable & 0x1) && + (p_Dpb->fs[i]->data_flag & IDR_FLAG)) + fast_output_flag = 1; + if (p_H264_Dpb->fast_output_enable & 0x6 + && p_H264_Dpb->poc_even_odd_flag + && p_Dpb->last_output_poc == INT_MIN) + fast_output_flag = 1; + if ((p_H264_Dpb->fast_output_enable & 0x2) && + ((p_Dpb->fs[i]->poc - + p_Dpb->last_output_poc) + == 1)) + fast_output_flag = 1; + if ((p_H264_Dpb->fast_output_enable & 0x4) && + (p_H264_Dpb->poc_even_odd_flag == 2) && + ((p_Dpb->fs[i]->poc - + p_Dpb->last_output_poc) + == 2)) + fast_output_flag = 1; + } + } + if (fast_output_flag) + ; + else if (none_displayed_num < + p_H264_Dpb->reorder_pic_num) + return 0; + } + + get_smallest_poc(p_Dpb, &poc, &pos); + + if (pos == -1) + return 0; +#if 0 + if (is_used_for_reference(p_Dpb->fs[pos])) + return 0; +#endif + if (prepare_display_buf(p_H264_Dpb->vdec, p_Dpb->fs[pos]) >= 0) + p_Dpb->fs[pos]->pre_output = 1; + else { + if (h264_debug_flag & PRINT_FLAG_DPB_DETAIL) { + dpb_print(p_H264_Dpb->decoder_index, 0, + "%s[%d] poc:%d last_output_poc:%d poc_even_odd_flag:%d\n", + __func__, pos, poc, + p_Dpb->last_output_poc, + p_H264_Dpb->poc_even_odd_flag); + dump_dpb(p_Dpb, 1); + } + return 0; + } + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s[%d] poc %d last_output_poc %d poc_even_odd_flag %d\n", + __func__, pos, poc, + p_Dpb->last_output_poc, + p_H264_Dpb->poc_even_odd_flag); + + p_Dpb->last_output_poc = poc; + return 1; + +} + + +void flush_dpb(struct h264_dpb_stru *p_H264_Dpb) +{ + /* struct VideoParameters *p_Vid = p_Dpb->p_Vid; */ + struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB; + unsigned int i; + + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s\n", __func__); + + /* diagnostics */ + /* dpb_print(p_H264_Dpb->decoder_index, + *PRINT_FLAG_DPB_DETAIL, + *"Flush remaining frames from the dpb." + *"p_Dpb->size = %d, p_Dpb->used_size = %d\n", + *p_Dpb->size, p_Dpb->used_size); + */ + + if (!p_Dpb->init_done) + return; +/* if(p_Vid->conceal_mode == 0) */ +#if 0 +/* ??? */ + if (p_Vid->conceal_mode != 0) + conceal_non_ref_pics(p_Dpb, 0); +#endif + /* mark all frames unused */ + for (i = 0; i < p_Dpb->used_size; i++) { +#if MVC_EXTENSION_ENABLE + assert(p_Dpb->fs[i]->view_id == p_Dpb->layer_id); +#endif + unmark_for_reference(p_Dpb, p_Dpb->fs[i]); + + } + + while (remove_unused_frame_from_dpb(p_H264_Dpb)) + ; + + /* output frames in POC order */ + while (output_frames(p_H264_Dpb, 1)) + ; + + + p_Dpb->last_output_poc = INT_MIN; +} + +static int is_short_term_reference(struct DecodedPictureBuffer *p_Dpb, + struct FrameStore *fs) +{ + struct h264_dpb_stru *p_H264_Dpb = container_of(p_Dpb, + struct h264_dpb_stru, mDPB); + if (fs->is_used == 3) { /* frame */ + if ((fs->frame->used_for_reference) && + (!fs->frame->is_long_term)) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "[[%s 1]]", + __func__); + return 1; + } + } + + if (fs->is_used & 1) { /* top field */ + if (fs->top_field) { + if ((fs->top_field->used_for_reference) && + (!fs->top_field->is_long_term)) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "[[%s 2]]", + __func__); + return 1; + } + } + } + + if (fs->is_used & 2) { /* bottom field */ + if (fs->bottom_field) { + if ((fs->bottom_field->used_for_reference) && + (!fs->bottom_field->is_long_term)) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "[[%s 3]]", + __func__); + return 1; + } + } + } + return 0; +} + +static int is_long_term_reference(struct FrameStore *fs) +{ + + if (fs->is_used == 3) { /* frame */ + if ((fs->frame->used_for_reference) && + (fs->frame->is_long_term)) { + return 1; + } + } + + if (fs->is_used & 1) { /* top field */ + if (fs->top_field) { + if ((fs->top_field->used_for_reference) && + (fs->top_field->is_long_term)) { + return 1; + } + } + } + + if (fs->is_used & 2) { /* bottom field */ + if (fs->bottom_field) { + if ((fs->bottom_field->used_for_reference) && + (fs->bottom_field->is_long_term)) { + return 1; + } + } + } + return 0; +} + +static void update_ref_list(struct DecodedPictureBuffer *p_Dpb) +{ + unsigned int i, j; + + struct h264_dpb_stru *p_H264_Dpb = container_of(p_Dpb, + struct h264_dpb_stru, mDPB); + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s (%d, %d)\n", __func__, p_Dpb->size, p_Dpb->used_size); + for (i = 0, j = 0; i < p_Dpb->used_size; i++) { +#if 1 + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "fs[%d]: fs %p frame %p is_reference %d %d %d\n", + i, p_Dpb->fs[i], p_Dpb->fs[i]->frame, + p_Dpb->fs[i]->frame != NULL ? + p_Dpb->fs[i]->frame->used_for_reference : 0, + p_Dpb->fs[i]->top_field != NULL ? + p_Dpb->fs[i]->top_field->used_for_reference : + 0, + p_Dpb->fs[i]->bottom_field != NULL ? + p_Dpb->fs[i]->bottom_field->used_for_reference : 0); +#endif + if (is_short_term_reference(p_Dpb, p_Dpb->fs[i])) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "fs_ref[%d]=fs[%d]: fs %p\n", j, i, p_Dpb->fs[i]); + p_Dpb->fs_ref[j++] = p_Dpb->fs[i]; + } + } + + p_Dpb->ref_frames_in_buffer = j; + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s dpb size is %d, %d\n", __func__, p_Dpb->size, j); + while (j < p_Dpb->size) { + /* dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + *"fs_ref[%d]=null\n", j); + */ + p_Dpb->fs_ref[j++] = NULL; + } +#ifdef ERROR_CHECK + for (i = 0; i < DPB_SIZE_MAX; i++) { + if (p_Dpb->fs_ref[i] == NULL) + p_Dpb->fs_ref[i] = &dummy_fs; + } +#endif +} + +static void update_ltref_list(struct DecodedPictureBuffer *p_Dpb) +{ + unsigned int i, j; + struct h264_dpb_stru *p_H264_Dpb = container_of(p_Dpb, + struct h264_dpb_stru, mDPB); + + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s\n", __func__); + for (i = 0, j = 0; i < p_Dpb->used_size; i++) { + if (is_long_term_reference(p_Dpb->fs[i])) + p_Dpb->fs_ltref[j++] = p_Dpb->fs[i]; + } + + p_Dpb->ltref_frames_in_buffer = j; + + while (j < p_Dpb->size) + p_Dpb->fs_ltref[j++] = NULL; +#ifdef ERROR_CHECK + for (i = 0; i < DPB_SIZE_MAX; i++) { + if (p_Dpb->fs_ltref[i] == NULL) + p_Dpb->fs_ltref[i] = &dummy_fs; + } +#endif +} + +static void idr_memory_management(struct h264_dpb_stru *p_H264_Dpb, + struct StorablePicture *p) +{ + struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB; + + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s ref_frames_in_buffer %d ltref_frames_in_buffer %d\n", + __func__, p_Dpb->ref_frames_in_buffer, + p_Dpb->ltref_frames_in_buffer); + + + if (p->no_output_of_prior_pics_flag) { +#if 0 + /*???*/ + /* free all stored pictures */ + int i; + + for (i = 0; i < p_Dpb->used_size; i++) { + /* reset all reference settings + * free_frame_store(p_Dpb->fs[i]); + * p_Dpb->fs[i] = alloc_frame_store(); + */ + reset_frame_store(p_H264_Dpb, p_Dpb->fs[i]); /* ??? */ + } + for (i = 0; i < p_Dpb->ref_frames_in_buffer; i++) + p_Dpb->fs_ref[i] = NULL; + for (i = 0; i < p_Dpb->ltref_frames_in_buffer; i++) + p_Dpb->fs_ltref[i] = NULL; + p_Dpb->used_size = 0; +#endif + } else { + flush_dpb(p_H264_Dpb); + } + p_Dpb->last_picture = NULL; + + update_ref_list(p_Dpb); + update_ltref_list(p_Dpb); + p_Dpb->last_output_poc = INT_MIN; + + if (p->long_term_reference_flag) { + p_Dpb->max_long_term_pic_idx = 0; + p->is_long_term = 1; + p->long_term_frame_idx = 0; + } else { + p_Dpb->max_long_term_pic_idx = -1; + p->is_long_term = 0; + } + +#if (MVC_EXTENSION_ENABLE) + p_Dpb->last_output_view_id = -1; +#endif + +} + +static void sliding_window_memory_management( + struct DecodedPictureBuffer *p_Dpb, + struct StorablePicture *p) +{ + unsigned int i; + struct h264_dpb_stru *p_H264_Dpb = container_of(p_Dpb, + struct h264_dpb_stru, mDPB); + unsigned char slide_flag = 0; + unsigned int sliding_margin = imax( + 1, p_Dpb->num_ref_frames) - p_Dpb->ltref_frames_in_buffer; + /* assert (!p->idr_flag); */ + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s ref_frames_in_buffer %d ltref_frames_in_buffer %d\n", + __func__, p_Dpb->ref_frames_in_buffer, + p_Dpb->ltref_frames_in_buffer); + /* if this is a reference pic with sliding window, + unmark first ref frame */ + if (p_Dpb->ref_frames_in_buffer == sliding_margin) + slide_flag = 1; + /*else if ((h264_error_proc_policy & 0x8) && + (p_Dpb->ref_frames_in_buffer > sliding_margin)) + slide_flag = 1;*/ + + if (slide_flag) { + for (i = 0; i < p_Dpb->used_size; i++) { + if (p_Dpb->fs[i]->is_reference && + (!(p_Dpb->fs[i]->is_long_term))) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "unmark %d\n", i); + unmark_for_reference(p_Dpb, p_Dpb->fs[i]); + update_ref_list(p_Dpb); + break; + } + } + } + + p->is_long_term = 0; +} + +static void check_num_ref(struct DecodedPictureBuffer *p_Dpb) +{ + if ((int)(p_Dpb->ltref_frames_in_buffer + + p_Dpb->ref_frames_in_buffer) > + imax(1, p_Dpb->num_ref_frames)) { + struct h264_dpb_stru *p_H264_Dpb = container_of(p_Dpb, + struct h264_dpb_stru, mDPB); + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "Max. number of reference frames exceeded. Invalid stream. lt %d ref %d mum_ref %d\n", + p_Dpb->ltref_frames_in_buffer, + p_Dpb->ref_frames_in_buffer, + p_Dpb->num_ref_frames); + } +} + +void dump_dpb(struct DecodedPictureBuffer *p_Dpb, u8 force) +{ + unsigned i; + struct h264_dpb_stru *p_H264_Dpb = + container_of(p_Dpb, struct h264_dpb_stru, mDPB); + if ((h264_debug_flag & PRINT_FLAG_DUMP_DPB) == 0 && + force == 0) + return; + for (i = 0; i < p_Dpb->used_size; i++) { + dpb_print(p_H264_Dpb->decoder_index, + 0, + "("); + dpb_print_cont(p_H264_Dpb->decoder_index, + 0, + "fn=%d is_used %d ", + p_Dpb->fs[i]->frame_num, + p_Dpb->fs[i]->is_used); + if (p_Dpb->fs[i]->is_used & 1) { + if (p_Dpb->fs[i]->top_field) + dpb_print_cont(p_H264_Dpb->decoder_index, + 0, + "T: poc=%d pic_num=%d ", + p_Dpb->fs[i]->top_field->poc, + p_Dpb->fs[i]->top_field->pic_num); + else + dpb_print_cont(p_H264_Dpb->decoder_index, + 0, + "T: poc=%d ", + p_Dpb->fs[i]->frame->top_poc); + } + if (p_Dpb->fs[i]->is_used & 2) { + if (p_Dpb->fs[i]->bottom_field) + dpb_print_cont(p_H264_Dpb->decoder_index, + 0, + "B: poc=%d pic_num=%d ", + p_Dpb->fs[i]->bottom_field->poc, + p_Dpb->fs[i]->bottom_field->pic_num); + else + dpb_print_cont(p_H264_Dpb->decoder_index, + 0, + "B: poc=%d ", + p_Dpb->fs[i]->frame->bottom_poc); + } + if (p_Dpb->fs[i]->is_used == 3) + dpb_print_cont(p_H264_Dpb->decoder_index, + 0, + "F: poc=%d pic_num=%d ", + p_Dpb->fs[i]->frame->poc, + p_Dpb->fs[i]->frame->pic_num); + dpb_print_cont(p_H264_Dpb->decoder_index, + 0, + "G: poc=%d) ", p_Dpb->fs[i]->poc); + if (p_Dpb->fs[i]->is_reference) + dpb_print_cont(p_H264_Dpb->decoder_index, + 0, + "ref (%d) ", p_Dpb->fs[i]->is_reference); + if (p_Dpb->fs[i]->is_long_term) + dpb_print_cont(p_H264_Dpb->decoder_index, + 0, + "lt_ref (%d) ", p_Dpb->fs[i]->is_reference); + if (p_Dpb->fs[i]->is_output) + dpb_print_cont(p_H264_Dpb->decoder_index, + 0, + "out(displayed) "); + if (p_Dpb->fs[i]->pre_output) + dpb_print_cont(p_H264_Dpb->decoder_index, + 0, + "pre_output(in dispq or displaying) "); + if (p_Dpb->fs[i]->is_used == 3) { + if (p_Dpb->fs[i]->frame->non_existing) + dpb_print_cont(p_H264_Dpb->decoder_index, + 0, + "non_existing "); + } +#if (MVC_EXTENSION_ENABLE) + if (p_Dpb->fs[i]->is_reference) + dpb_print_cont(p_H264_Dpb->decoder_index, + 0, + "view_id (%d) ", p_Dpb->fs[i]->view_id); +#endif + if (p_Dpb->fs[i]->data_flag) { + dpb_print_cont(p_H264_Dpb->decoder_index, + 0, + "data_flag(0x%x)", + p_Dpb->fs[i]->data_flag); + } + dpb_print_cont(p_H264_Dpb->decoder_index, + 0, + " bufspec %d\n", + p_Dpb->fs[i]->buf_spec_num); + } +} + +/*! + ************************************************************************ + * \brief + * adaptive memory management + * + ************************************************************************ + */ + +static int get_pic_num_x(struct StorablePicture *p, + int difference_of_pic_nums_minus1) +{ + int currPicNum; + + if (p->structure == FRAME) + currPicNum = p->frame_num; + else + currPicNum = 2 * p->frame_num + 1; + + return currPicNum - (difference_of_pic_nums_minus1 + 1); +} + +/*! + ************************************************************************ + * \brief + * Adaptive Memory Management: Mark short term picture unused + ************************************************************************ + */ +static void mm_unmark_short_term_for_reference(struct DecodedPictureBuffer + *p_Dpb, struct StorablePicture *p, + int difference_of_pic_nums_minus1) +{ + struct h264_dpb_stru *p_H264_Dpb = + container_of(p_Dpb, struct h264_dpb_stru, mDPB); + int picNumX; + + unsigned int i; + + picNumX = get_pic_num_x(p, difference_of_pic_nums_minus1); + + for (i = 0; i < p_Dpb->ref_frames_in_buffer; i++) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i] == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p->structure == FRAME) { + if ((p_Dpb->fs_ref[i]->is_reference == 3) && + (p_Dpb->fs_ref[i]->is_long_term == 0)) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i]->frame == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p_Dpb->fs_ref[i]->frame->pic_num == + picNumX) { + unmark_for_reference(p_Dpb, + p_Dpb->fs_ref[i]); + return; + } + } + } else { + if ((p_Dpb->fs_ref[i]->is_reference & 1) && + (!(p_Dpb->fs_ref[i]->is_long_term & 1))) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i]->top_field == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p_Dpb->fs_ref[i]->top_field->pic_num == + picNumX) { + p_Dpb->fs_ref[i]-> + top_field->used_for_reference = 0; + p_Dpb->fs_ref[i]->is_reference &= 2; + if ((p_Dpb->fs_ref[i]->is_used == 3) +#ifdef ERROR_CHECK + && p_Dpb->fs_ref[i]->frame +#endif + ) { + p_Dpb->fs_ref[i]->frame-> + used_for_reference = 0; + } + return; + } + } + if ((p_Dpb->fs_ref[i]->is_reference & 2) && + (!(p_Dpb->fs_ref[i]->is_long_term & 2))) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i]->bottom_field == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p_Dpb->fs_ref[i]->bottom_field->pic_num == + picNumX) { + p_Dpb->fs_ref[i]->bottom_field-> + used_for_reference = 0; + p_Dpb->fs_ref[i]->is_reference &= 1; + if ((p_Dpb->fs_ref[i]->is_used == 3) +#ifdef ERROR_CHECK + && p_Dpb->fs_ref[i]->frame +#endif + ) { + p_Dpb->fs_ref[i]->frame-> + used_for_reference = 0; + } + return; + } + } + } + } +} + +static void unmark_for_long_term_reference(struct FrameStore *fs) +{ + if (fs->is_used & 1) { + if (fs->top_field) { + fs->top_field->used_for_reference = 0; + fs->top_field->is_long_term = 0; + } + } + if (fs->is_used & 2) { + if (fs->bottom_field) { + fs->bottom_field->used_for_reference = 0; + fs->bottom_field->is_long_term = 0; + } + } + if (fs->is_used == 3) { + if (fs->top_field && fs->bottom_field) { + fs->top_field->used_for_reference = 0; + fs->top_field->is_long_term = 0; + fs->bottom_field->used_for_reference = 0; + fs->bottom_field->is_long_term = 0; + } + fs->frame->used_for_reference = 0; + fs->frame->is_long_term = 0; + } + + fs->is_reference = 0; + fs->is_long_term = 0; +} + +/*! + ************************************************************************ + * \brief + * Adaptive Memory Management: Mark long term picture unused + ************************************************************************ + */ +static void mm_unmark_long_term_for_reference(struct DecodedPictureBuffer + *p_Dpb, struct StorablePicture *p, int long_term_pic_num) +{ + unsigned int i; + + for (i = 0; i < p_Dpb->ltref_frames_in_buffer; i++) { + if (p->structure == FRAME) { + if ((p_Dpb->fs_ltref[i]->is_reference == 3) && + (p_Dpb->fs_ltref[i]->is_long_term == 3)) { + if (p_Dpb->fs_ltref[i]->frame-> + long_term_pic_num == + long_term_pic_num) { + unmark_for_long_term_reference( + p_Dpb->fs_ltref[i]); + } + } + } else { + if ((p_Dpb->fs_ltref[i]->is_reference & 1) && + ((p_Dpb->fs_ltref[i]->is_long_term & 1))) { + if (p_Dpb->fs_ltref[i]->top_field-> + long_term_pic_num == + long_term_pic_num) { + p_Dpb->fs_ltref[i]->top_field-> + used_for_reference = 0; + p_Dpb->fs_ltref[i]->top_field-> + is_long_term = 0; + p_Dpb->fs_ltref[i]->is_reference &= 2; + p_Dpb->fs_ltref[i]->is_long_term &= 2; + if (p_Dpb->fs_ltref[i]->is_used == 3) { + p_Dpb->fs_ltref[i]->frame-> + used_for_reference = 0; + p_Dpb->fs_ltref[i]->frame-> + is_long_term = 0; + } + return; + } + } + if ((p_Dpb->fs_ltref[i]->is_reference & 2) && + ((p_Dpb->fs_ltref[i]->is_long_term & 2))) { + if (p_Dpb->fs_ltref[i]->bottom_field-> + long_term_pic_num == + long_term_pic_num) { + p_Dpb->fs_ltref[i]->bottom_field-> + used_for_reference = 0; + p_Dpb->fs_ltref[i]->bottom_field-> + is_long_term = 0; + p_Dpb->fs_ltref[i]->is_reference &= 1; + p_Dpb->fs_ltref[i]->is_long_term &= 1; + if (p_Dpb->fs_ltref[i]->is_used == 3) { + p_Dpb->fs_ltref[i]->frame-> + used_for_reference = 0; + p_Dpb->fs_ltref[i]->frame-> + is_long_term = 0; + } + return; + } + } + } + } +} + + +/*! + ************************************************************************ + * \brief + * Mark a long-term reference frame or complementary + * field pair unused for referemce + ************************************************************************ + */ +static void unmark_long_term_frame_for_reference_by_frame_idx( + struct DecodedPictureBuffer *p_Dpb, int long_term_frame_idx) +{ + unsigned int i; + + for (i = 0; i < p_Dpb->ltref_frames_in_buffer; i++) { + if (p_Dpb->fs_ltref[i]->long_term_frame_idx == + long_term_frame_idx) + unmark_for_long_term_reference(p_Dpb->fs_ltref[i]); + } +} + + +static void unmark1(struct DecodedPictureBuffer *p_Dpb, + unsigned int curr_frame_num, int i) +{ + if (p_Dpb->last_picture) { + if ((p_Dpb->last_picture != p_Dpb->fs_ltref[i]) || + p_Dpb->last_picture->frame_num != curr_frame_num) { + unmark_for_long_term_reference(p_Dpb->fs_ltref[i]); + } else { + unmark_for_long_term_reference(p_Dpb->fs_ltref[i]); + } + } +} + +static void unmark2(struct DecodedPictureBuffer *p_Dpb, + int curr_pic_num, int i) +{ + if ((p_Dpb->fs_ltref[i]->frame_num) != + (unsigned int)(curr_pic_num >> 1)) + unmark_for_long_term_reference(p_Dpb->fs_ltref[i]); +} + +static void unmark3_top(struct DecodedPictureBuffer *p_Dpb, + unsigned int curr_frame_num, int curr_pic_num, int mark_current, int i) +{ + if (p_Dpb->fs_ltref[i]->is_long_term == 3) { + unmark_for_long_term_reference(p_Dpb->fs_ltref[i]); + } else { + if (p_Dpb->fs_ltref[i]->is_long_term == 1) { + unmark_for_long_term_reference(p_Dpb->fs_ltref[i]); + } else { + if (mark_current) + unmark1(p_Dpb, curr_frame_num, i); + else + unmark2(p_Dpb, curr_pic_num, i); + } + } +} + +static void unmark3_bottom(struct DecodedPictureBuffer *p_Dpb, + unsigned int curr_frame_num, int curr_pic_num, int mark_current, int i) +{ + if (p_Dpb->fs_ltref[i]->is_long_term == 2) { + unmark_for_long_term_reference(p_Dpb->fs_ltref[i]); + } else { + if (mark_current) + unmark1(p_Dpb, curr_frame_num, i); + else + unmark2(p_Dpb, curr_pic_num, i); + } +} + +static void unmark_long_term_field_for_reference_by_frame_idx( + struct DecodedPictureBuffer *p_Dpb, enum PictureStructure structure, + int long_term_frame_idx, int mark_current, unsigned int curr_frame_num, + int curr_pic_num) +{ + struct VideoParameters *p_Vid = p_Dpb->p_Vid; + unsigned int i; + + /* assert(structure!=FRAME); */ + if (curr_pic_num < 0) + curr_pic_num += (2 * p_Vid->max_frame_num); + + for (i = 0; i < p_Dpb->ltref_frames_in_buffer; i++) { + if (p_Dpb->fs_ltref[i]->long_term_frame_idx == + long_term_frame_idx) { + if (structure == TOP_FIELD) + unmark3_top(p_Dpb, curr_frame_num, + curr_pic_num, mark_current, i); + + if (structure == BOTTOM_FIELD) + unmark3_bottom(p_Dpb, curr_frame_num, + curr_pic_num, mark_current, i); + } + } +} + +/*! + ************************************************************************ + * \brief + * mark a picture as long-term reference + ************************************************************************ + */ +static void mark_pic_long_term(struct DecodedPictureBuffer *p_Dpb, + struct StorablePicture *p, + int long_term_frame_idx, int picNumX) +{ + struct h264_dpb_stru *p_H264_Dpb = container_of(p_Dpb, + struct h264_dpb_stru, mDPB); + unsigned int i; + int add_top, add_bottom; + + if (p->structure == FRAME) { + for (i = 0; i < p_Dpb->ref_frames_in_buffer; i++) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i] == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p_Dpb->fs_ref[i]->is_reference == 3) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i]->frame == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if ((!p_Dpb->fs_ref[i]->frame-> + is_long_term) && + (p_Dpb->fs_ref[i]->frame->pic_num == + picNumX)) { + p_Dpb->fs_ref[i]-> + long_term_frame_idx = + p_Dpb->fs_ref[i]->frame-> + long_term_frame_idx = + long_term_frame_idx; + p_Dpb->fs_ref[i]->frame-> + long_term_pic_num = + long_term_frame_idx; + p_Dpb->fs_ref[i]->frame-> + is_long_term = 1; + + if (p_Dpb->fs_ref[i]->top_field && + p_Dpb->fs_ref[i]->bottom_field) { + p_Dpb->fs_ref[i]->top_field-> + long_term_frame_idx = + p_Dpb->fs_ref[i]-> + bottom_field-> + long_term_frame_idx = + long_term_frame_idx; + p_Dpb->fs_ref[i]->top_field-> + long_term_pic_num = + long_term_frame_idx; + p_Dpb->fs_ref[i]-> + bottom_field-> + long_term_pic_num = + long_term_frame_idx; + + p_Dpb->fs_ref[i]->top_field-> + is_long_term = + p_Dpb->fs_ref[i]-> + bottom_field-> + is_long_term + = 1; + + } + p_Dpb->fs_ref[i]->is_long_term = 3; + return; + } + } + } + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "Warning: reference frame for long term marking not found\n"); + } else { + if (p->structure == TOP_FIELD) { + add_top = 1; + add_bottom = 0; + } else { + add_top = 0; + add_bottom = 1; + } + for (i = 0; i < p_Dpb->ref_frames_in_buffer; i++) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i] == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p_Dpb->fs_ref[i]->is_reference & 1) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i]->top_field == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if ((!p_Dpb->fs_ref[i]->top_field-> + is_long_term) && + (p_Dpb->fs_ref[i]->top_field->pic_num == + picNumX)) { + if ((p_Dpb->fs_ref[i]-> + is_long_term) && + (p_Dpb->fs_ref[i]-> + long_term_frame_idx != + long_term_frame_idx)) { + dpb_print(p_H264_Dpb-> + decoder_index, + PRINT_FLAG_DPB_DETAIL, + "Warning: assigning long_term_frame_idx different from other field\n"); + } + + p_Dpb->fs_ref[i]-> + long_term_frame_idx = + p_Dpb->fs_ref[i]->top_field-> + long_term_frame_idx + = long_term_frame_idx; + p_Dpb->fs_ref[i]->top_field-> + long_term_pic_num = + 2 * long_term_frame_idx + + add_top; + p_Dpb->fs_ref[i]->top_field-> + is_long_term = 1; + p_Dpb->fs_ref[i]->is_long_term |= 1; + if ((p_Dpb->fs_ref[i]->is_long_term + == 3) +#ifdef ERROR_CHECK + && p_Dpb->fs_ref[i]->frame +#endif + ) { + p_Dpb->fs_ref[i]->frame-> + is_long_term = 1; + p_Dpb->fs_ref[i]->frame-> + long_term_frame_idx = + p_Dpb->fs_ref[i]-> + frame-> + long_term_pic_num = + long_term_frame_idx; + } + return; + } + } + if (p_Dpb->fs_ref[i]->is_reference & 2) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i]->bottom_field == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if ((!p_Dpb->fs_ref[i]->bottom_field-> + is_long_term) && + (p_Dpb->fs_ref[i]->bottom_field->pic_num + == picNumX)) { + if ((p_Dpb->fs_ref[i]-> + is_long_term) && + (p_Dpb->fs_ref[i]-> + long_term_frame_idx != + long_term_frame_idx)) { + dpb_print(p_H264_Dpb-> + decoder_index, + PRINT_FLAG_DPB_DETAIL, + "Warning: assigning long_term_frame_idx different from other field\n"); + } + + p_Dpb->fs_ref[i]-> + long_term_frame_idx = + p_Dpb->fs_ref[i]->bottom_field + ->long_term_frame_idx + = long_term_frame_idx; + p_Dpb->fs_ref[i]->bottom_field-> + long_term_pic_num = 2 * + long_term_frame_idx + + add_bottom; + p_Dpb->fs_ref[i]->bottom_field-> + is_long_term = 1; + p_Dpb->fs_ref[i]->is_long_term |= 2; + if ((p_Dpb->fs_ref[i]-> + is_long_term == 3) +#ifdef ERROR_CHECK + && p_Dpb->fs_ref[i]->frame +#endif + ) { + p_Dpb->fs_ref[i]->frame-> + is_long_term = 1; + p_Dpb->fs_ref[i]->frame-> + long_term_frame_idx = + p_Dpb->fs_ref[i]-> + frame-> + long_term_pic_num = + long_term_frame_idx; + } + return; + } + } + } + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "Warning: reference field for long term marking not found\n"); + } +} + + +/*! + ************************************************************************ + * \brief + * Assign a long term frame index to a short term picture + ************************************************************************ + */ +static void mm_assign_long_term_frame_idx(struct DecodedPictureBuffer *p_Dpb, + struct StorablePicture *p, int difference_of_pic_nums_minus1, + int long_term_frame_idx) +{ + struct h264_dpb_stru *p_H264_Dpb = container_of(p_Dpb, + struct h264_dpb_stru, mDPB); + int picNumX = get_pic_num_x(p, difference_of_pic_nums_minus1); + + /* remove frames/fields with same long_term_frame_idx */ + if (p->structure == FRAME) { + unmark_long_term_frame_for_reference_by_frame_idx(p_Dpb, + long_term_frame_idx); + } else { + unsigned int i; + enum PictureStructure structure = FRAME; + + for (i = 0; i < p_Dpb->ref_frames_in_buffer; i++) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i] == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p_Dpb->fs_ref[i]->is_reference & 1) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i]->top_field == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p_Dpb->fs_ref[i]->top_field-> + pic_num == picNumX) { + structure = TOP_FIELD; + break; + } + } + if (p_Dpb->fs_ref[i]->is_reference & 2) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i]->bottom_field == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p_Dpb->fs_ref[i]->bottom_field-> + pic_num == picNumX) { + structure = BOTTOM_FIELD; + break; + } + } + } + if (structure == FRAME) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "field for long term marking not found %d", + 200); + } + + unmark_long_term_field_for_reference_by_frame_idx(p_Dpb, + structure, + long_term_frame_idx, 0, 0, picNumX); + } + + mark_pic_long_term(p_Dpb, p, long_term_frame_idx, picNumX); +} + +/*! + ************************************************************************ + * \brief + * Set new max long_term_frame_idx + ************************************************************************ + */ +static void mm_update_max_long_term_frame_idx(struct DecodedPictureBuffer + *p_Dpb, int max_long_term_frame_idx_plus1) +{ + unsigned int i; + + p_Dpb->max_long_term_pic_idx = max_long_term_frame_idx_plus1 - 1; + + /* check for invalid frames */ + for (i = 0; i < p_Dpb->ltref_frames_in_buffer; i++) { + if (p_Dpb->fs_ltref[i]->long_term_frame_idx > + p_Dpb->max_long_term_pic_idx) { + unmark_for_long_term_reference(p_Dpb->fs_ltref[i]); + } + } +} + + +/*! + ************************************************************************ + * \brief + * Mark all long term reference pictures unused for reference + ************************************************************************ + */ +static void mm_unmark_all_long_term_for_reference(struct DecodedPictureBuffer + *p_Dpb) +{ + mm_update_max_long_term_frame_idx(p_Dpb, 0); +} + +/*! + ************************************************************************ + * \brief + * Mark all short term reference pictures unused for reference + ************************************************************************ + */ +static void mm_unmark_all_short_term_for_reference(struct DecodedPictureBuffer + *p_Dpb) +{ + unsigned int i; + + for (i = 0; i < p_Dpb->ref_frames_in_buffer; i++) + unmark_for_reference(p_Dpb, p_Dpb->fs_ref[i]); + update_ref_list(p_Dpb); +} + + +/*! + ************************************************************************ + * \brief + * Mark the current picture used for long term reference + ************************************************************************ + */ +static void mm_mark_current_picture_long_term(struct DecodedPictureBuffer + *p_Dpb, struct StorablePicture *p, int long_term_frame_idx) +{ + /* remove long term pictures with same long_term_frame_idx */ + if (p->structure == FRAME) { + unmark_long_term_frame_for_reference_by_frame_idx(p_Dpb, + long_term_frame_idx); + } else { + unmark_long_term_field_for_reference_by_frame_idx(p_Dpb, + p->structure, long_term_frame_idx, + 1, p->pic_num, 0); + } + + p->is_long_term = 1; + p->long_term_frame_idx = long_term_frame_idx; +} + +static void adaptive_memory_management(struct h264_dpb_stru *p_H264_Dpb, + struct StorablePicture *p) +{ + struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB; + struct DecRefPicMarking_s *tmp_drpm; + struct VideoParameters *p_Vid = p_Dpb->p_Vid; + + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s\n", __func__); + p_Vid->last_has_mmco_5 = 0; + + /* assert (!p->idr_flag); */ + /* assert (p->adaptive_ref_pic_buffering_flag); */ + + while (p->dec_ref_pic_marking_buffer) { + tmp_drpm = p->dec_ref_pic_marking_buffer; + switch (tmp_drpm->memory_management_control_operation) { + case 0: + if (tmp_drpm->Next != NULL) + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_ERROR, + "error, memory_management_control_operation = 0 not last operation in buffer\n"); + break; + case 1: + mm_unmark_short_term_for_reference(p_Dpb, p, + tmp_drpm->difference_of_pic_nums_minus1); + update_ref_list(p_Dpb); + break; + case 2: + mm_unmark_long_term_for_reference(p_Dpb, p, + tmp_drpm->long_term_pic_num); + update_ltref_list(p_Dpb); + break; + case 3: + mm_assign_long_term_frame_idx(p_Dpb, p, + tmp_drpm->difference_of_pic_nums_minus1, + tmp_drpm->long_term_frame_idx); + update_ref_list(p_Dpb); + update_ltref_list(p_Dpb); + break; + case 4: + mm_update_max_long_term_frame_idx(p_Dpb, + tmp_drpm->max_long_term_frame_idx_plus1); + update_ltref_list(p_Dpb); + break; + case 5: + mm_unmark_all_short_term_for_reference(p_Dpb); + mm_unmark_all_long_term_for_reference(p_Dpb); + p_Vid->last_has_mmco_5 = 1; + break; + case 6: + mm_mark_current_picture_long_term(p_Dpb, p, + tmp_drpm->long_term_frame_idx); + check_num_ref(p_Dpb); + break; + default: + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_ERROR, + "error, invalid memory_management_control_operation in buffer\n"); + } + p->dec_ref_pic_marking_buffer = tmp_drpm->Next; + /* free (tmp_drpm); */ + } + if (p_Vid->last_has_mmco_5) { + p->pic_num = p->frame_num = 0; + + switch (p->structure) { + case TOP_FIELD: { + /* p->poc = p->top_poc = p_Vid->toppoc =0; */ + p->poc = p->top_poc = 0; + break; + } + case BOTTOM_FIELD: { + /* p->poc = p->bottom_poc = p_Vid->bottompoc = 0; */ + p->poc = p->bottom_poc = 0; + break; + } + case FRAME: { + p->top_poc -= p->poc; + p->bottom_poc -= p->poc; + + /* p_Vid->toppoc = p->top_poc; */ + /* p_Vid->bottompoc = p->bottom_poc; */ + + p->poc = imin(p->top_poc, p->bottom_poc); + /* p_Vid->framepoc = p->poc; */ + break; + } + } + /* currSlice->ThisPOC = p->poc; */ +#if (MVC_EXTENSION_ENABLE) + if (p->view_id == 0) { + flush_dpb(p_Vid->p_Dpb_layer[0]); + flush_dpb(p_Vid->p_Dpb_layer[1]); + } else { + flush_dpb(p_Dpb); + } +#else + flush_dpb(p_H264_Dpb); +#endif + } +} + + +int store_picture_in_dpb(struct h264_dpb_stru *p_H264_Dpb, + struct StorablePicture *p, + unsigned char data_flag) +{ + /* struct VideoParameters *p_Vid = p_Dpb->p_Vid; */ + struct VideoParameters *p_Vid = &p_H264_Dpb->mVideo; + struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB; + unsigned int i; +#if 0 + int poc, pos; +#endif + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s p_Vid %p\n", __func__, p_Vid); + + /* picture error concealment */ + + /* diagnostics */ + /* dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + * "Storing (%s) non-ref pic with frame_num #%d\n", + * (p->type == FRAME)?"FRAME":(p->type == TOP_FIELD)? + * "TOP_FIELD":"BOTTOM_FIELD", p->pic_num); + */ + /* if frame, check for new store, */ + /* assert (p!=NULL); */ + + p_Vid->last_has_mmco_5 = 0; + p_Vid->last_pic_bottom_field = (p->structure == BOTTOM_FIELD); + if (p->idr_flag) { + idr_memory_management(p_H264_Dpb, p); +#if 0 +/* ??? */ + /* picture error concealment */ + memset(p_Vid->pocs_in_dpb, 0, sizeof(int) * 100); +#endif + } else { +#if 1 +/* ??? */ + /* adaptive memory management */ + if (p->used_for_reference && + (p->adaptive_ref_pic_buffering_flag)) + adaptive_memory_management(p_H264_Dpb, p); +#endif + } + + if ((p->structure == TOP_FIELD) || (p->structure == BOTTOM_FIELD)) { + /* check for frame store with same pic_number */ + if (p_Dpb->last_picture) { + if ((int)p_Dpb->last_picture->frame_num == + p->pic_num) { + if (((p->structure == TOP_FIELD) && + (p_Dpb->last_picture->is_used == 2)) || + ((p->structure == BOTTOM_FIELD) && + (p_Dpb->last_picture->is_used == 1))) { + if ((p->used_for_reference && + (p_Dpb->last_picture-> + is_orig_reference != 0)) || + (!p->used_for_reference && + (p_Dpb->last_picture-> + is_orig_reference == 0))) { + insert_picture_in_dpb( + p_H264_Dpb, + p_Dpb->last_picture, + p, data_flag); + update_ref_list(p_Dpb); + update_ltref_list(p_Dpb); + dump_dpb(p_Dpb, 0); + p_Dpb->last_picture = NULL; + return 0; + } + } + } + } + } + /* this is a frame or a field which has no stored + * complementary field + */ + + /* sliding window, if necessary */ + if ((!p->idr_flag) && (p->used_for_reference && + (!p->adaptive_ref_pic_buffering_flag))) { + sliding_window_memory_management(p_Dpb, p); + } + + /* picture error concealment */ + if (p_Vid->conceal_mode != 0) { + for (i = 0; i < p_Dpb->size; i++) + if (p_Dpb->fs[i]->is_reference) + p_Dpb->fs[i]->concealment_reference = 1; + } + + while (remove_unused_frame_from_dpb(p_H264_Dpb)) + ; + + while (output_frames(p_H264_Dpb, 0)) + ; + + /* check for duplicate frame number in short term reference buffer */ + if ((p->used_for_reference) && (!p->is_long_term)) { + for (i = 0; i < p_Dpb->ref_frames_in_buffer; i++) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i] == NULL) + continue; +#endif + if (p_Dpb->fs_ref[i]->frame_num == p->frame_num) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "duplicate frame_num in short-term reference picture buffer %d\n", + 500); + } + } + } + /* store at end of buffer */ + + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s p_Dpb->used_size %d\n", __func__, p_Dpb->used_size); + if (p_Dpb->used_size >= p_Dpb->size) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_ERROR, + "%s Error: used_sizd %d is large than dpb size\r\n", + __func__, p_Dpb->used_size); + /*h264_debug_flag |= PRINT_FLAG_DUMP_DPB;*/ + dump_dpb(p_Dpb, 0); + return -1; + } + + insert_picture_in_dpb(p_H264_Dpb, p_Dpb->fs[p_Dpb->used_size], + p, data_flag); + + /* picture error concealment */ + if (p->idr_flag) + p_Vid->earlier_missing_poc = 0; + + if (p->structure != FRAME) + p_Dpb->last_picture = p_Dpb->fs[p_Dpb->used_size]; + else + p_Dpb->last_picture = NULL; + + p_Dpb->used_size++; +#if 0 +/* ??? */ + if (p_Vid->conceal_mode != 0) + p_Vid->pocs_in_dpb[p_Dpb->used_size - 1] = p->poc; +#endif + update_ref_list(p_Dpb); + update_ltref_list(p_Dpb); + + check_num_ref(p_Dpb); + + dump_dpb(p_Dpb, 0); + p_Dpb->first_pic_done = 1; /*by rain*/ + + return 0; +} + +void bufmgr_post(struct h264_dpb_stru *p_H264_Dpb) +{ + /*VideoParameters *p_Vid = p_Dpb->p_Vid;*/ + struct VideoParameters *p_Vid = &p_H264_Dpb->mVideo; + + if (p_Vid->last_has_mmco_5) + p_Vid->pre_frame_num = 0; +} +/********************************** + * + * Initialize reference lists + ********************************** + */ +#define __COMPARE(context, p1, p2) comp(p1, p2) +#define __SHORTSORT(lo, hi, width, comp, context) \ + shortsort(lo, hi, width, comp) +#define CUTOFF 8 /* testing shows that this is good value */ +#define STKSIZ (8*sizeof(void *) - 2) + +#undef swap +static void swap( + char *a, + char *b, + size_t width +) +{ + char tmp; + + if (a != b) + /* Do the swap one character at a time to avoid potential + * alignment problems. + */ + while (width--) { + tmp = *a; + *a++ = *b; + *b++ = tmp; + } +} + +static void shortsort( + char *lo, + char *hi, + size_t width, + int (*comp)(const void *, const void *) +) +{ + char *p, *max; + + /* Note: in assertions below, i and j are alway inside original + * bound of array to sort. + */ + + while (hi > lo) { + /* A[i] <= A[j] for i <= j, j > hi */ + max = lo; + for (p = lo + width; p <= hi; p += width) { + /* A[i] <= A[max] for lo <= i < p */ + if (__COMPARE(context, p, max) > 0) + max = p; + /* A[i] <= A[max] for lo <= i <= p */ + } + + /* A[i] <= A[max] for lo <= i <= hi */ + + swap(max, hi, width); + + /* A[i] <= A[hi] for i <= hi, so A[i] <= A[j] for i <= j, + * j >= hi + */ + + hi -= width; + + /* A[i] <= A[j] for i <= j, j > hi, loop top condition + * established + */ + } + /* A[i] <= A[j] for i <= j, j > lo, which implies A[i] <= A[j] + * for i < j, so array is sorted + */ +} + +static void qsort( + void *base, + size_t num, + size_t width, + int (*comp)(const void *, const void *) +) +{ + char *lo, *hi; /* ends of sub-array currently sorting */ + char *mid; /* points to middle of subarray */ + char *loguy, *higuy; /* traveling pointers for partition step */ + size_t size; /* size of the sub-array */ + char *lostk[STKSIZ], *histk[STKSIZ]; + int stkptr; + +/* stack for saving sub-array to be + * processed + */ +#if 0 + /* validation section */ + _VALIDATE_RETURN_VOID(base != NULL || num == 0, EINVAL); + _VALIDATE_RETURN_VOID(width > 0, EINVAL); + _VALIDATE_RETURN_VOID(comp != NULL, EINVAL); +#endif + if (num < 2) + return; /* nothing to do */ + + stkptr = 0; /* initialize stack */ + + lo = (char *)base; + hi = (char *)base + width * (num - 1); /* initialize limits */ + + /* this entry point is for pseudo-recursion calling: setting + * lo and hi and jumping to here is like recursion, but stkptr is + * preserved, locals aren't, so we preserve stuff on the stack + */ +recurse: + + size = (hi - lo) / width + 1; /* number of el's to sort */ + + /* below a certain size, it is faster to use a O(n^2) sorting method */ + if (size <= CUTOFF) { + __SHORTSORT(lo, hi, width, comp, context); + } else { + /* First we pick a partitioning element. The efficiency of + * the algorithm demands that we find one that is approximately + * the median of the values, but also that we select one fast. + * We choose the median of the first, middle, and last + * elements, to avoid bad performance in the face of already + * sorted data, or data that is made up of multiple sorted + * runs appended together. Testing shows that a + * median-of-three algorithm provides better performance than + * simply picking the middle element for the latter case. + */ + + mid = lo + (size / 2) * width; /* find middle element */ + + /* Sort the first, middle, last elements into order */ + if (__COMPARE(context, lo, mid) > 0) + swap(lo, mid, width); + if (__COMPARE(context, lo, hi) > 0) + swap(lo, hi, width); + if (__COMPARE(context, mid, hi) > 0) + swap(mid, hi, width); + + /* We now wish to partition the array into three pieces, one + * consisting of elements <= partition element, one of elements + * equal to the partition element, and one of elements > than + * it. This is done below; comments indicate conditions + * established at every step. + */ + + loguy = lo; + higuy = hi; + + /* Note that higuy decreases and loguy increases on every + * iteration, so loop must terminate. + */ + for (;;) { + /* lo <= loguy < hi, lo < higuy <= hi, + * A[i] <= A[mid] for lo <= i <= loguy, + * A[i] > A[mid] for higuy <= i < hi, + * A[hi] >= A[mid] + */ + + /* The doubled loop is to avoid calling comp(mid,mid), + * since some existing comparison funcs don't work + * when passed the same value for both pointers. + */ + + if (mid > loguy) { + do { + loguy += width; + } while (loguy < mid && + __COMPARE(context, loguy, mid) <= 0); + } + if (mid <= loguy) { + do { + loguy += width; + } while (loguy <= hi && + __COMPARE(context, loguy, mid) <= 0); + } + + /* lo < loguy <= hi+1, A[i] <= A[mid] for + * lo <= i < loguy, + * either loguy > hi or A[loguy] > A[mid] + */ + + do { + higuy -= width; + } while (higuy > mid && + __COMPARE(context, higuy, mid) > 0); + + /* lo <= higuy < hi, A[i] > A[mid] for higuy < i < hi, + * either higuy == lo or A[higuy] <= A[mid] + */ + + if (higuy < loguy) + break; + + /* if loguy > hi or higuy == lo, then we would have + * exited, so A[loguy] > A[mid], A[higuy] <= A[mid], + * loguy <= hi, higuy > lo + */ + + swap(loguy, higuy, width); + + /* If the partition element was moved, follow it. + * Only need to check for mid == higuy, since before + * the swap, A[loguy] > A[mid] implies loguy != mid. + */ + + if (mid == higuy) + mid = loguy; + + /* A[loguy] <= A[mid], A[higuy] > A[mid]; so condition + * at top of loop is re-established + */ + } + + /* A[i] <= A[mid] for lo <= i < loguy, + * A[i] > A[mid] for higuy < i < hi, + * A[hi] >= A[mid] + * higuy < loguy + * implying: + * higuy == loguy-1 + * or higuy == hi - 1, loguy == hi + 1, A[hi] == A[mid] + */ + + /* Find adjacent elements equal to the partition element. The + * doubled loop is to avoid calling comp(mid,mid), since some + * existing comparison funcs don't work when passed the same + * value for both pointers. + */ + + higuy += width; + if (mid < higuy) { + do { + higuy -= width; + } while (higuy > mid && + __COMPARE(context, higuy, mid) == 0); + } + if (mid >= higuy) { + do { + higuy -= width; + } while (higuy > lo && + __COMPARE(context, higuy, mid) == 0); + } + + /* OK, now we have the following: + * higuy < loguy + * lo <= higuy <= hi + * A[i] <= A[mid] for lo <= i <= higuy + * A[i] == A[mid] for higuy < i < loguy + * A[i] > A[mid] for loguy <= i < hi + * A[hi] >= A[mid] + */ + + /* We've finished the partition, now we want to sort the + * subarrays [lo, higuy] and [loguy, hi]. + * We do the smaller one first to minimize stack usage. + * We only sort arrays of length 2 or more. + */ + + if (higuy - lo >= hi - loguy) { + if (lo < higuy) { + lostk[stkptr] = lo; + histk[stkptr] = higuy; + ++stkptr; + } /* save big recursion for later */ + + if (loguy < hi) { + lo = loguy; + goto recurse; /* do small recursion */ + } + } else { + if (loguy < hi) { + lostk[stkptr] = loguy; + histk[stkptr] = hi; + ++stkptr; /* save big recursion for later */ + } + + if (lo < higuy) { + hi = higuy; + goto recurse; /* do small recursion */ + } + } + } + + /* We have sorted the array, except for any pending sorts on the stack. + * Check if there are any, and do them. + */ + + --stkptr; + if (stkptr >= 0) { + lo = lostk[stkptr]; + hi = histk[stkptr]; + goto recurse; /* pop subarray from stack */ + } else + return; /* all subarrays done */ +} + +/*! + ************************************************************************ + * \brief + * compares two stored pictures by picture number for qsort in + * descending order + * + ************************************************************************ + */ +static inline int compare_pic_by_pic_num_desc(const void *arg1, + const void *arg2) +{ + int pic_num1 = (*(struct StorablePicture **)arg1)->pic_num; + int pic_num2 = (*(struct StorablePicture **)arg2)->pic_num; + + if (pic_num1 < pic_num2) + return 1; + if (pic_num1 > pic_num2) + return -1; + else + return 0; +} + +/*! + ************************************************************************ + * \brief + * compares two stored pictures by picture number for qsort in + * descending order + * + ************************************************************************ + */ +static inline int compare_pic_by_lt_pic_num_asc(const void *arg1, + const void *arg2) +{ + int long_term_pic_num1 = + (*(struct StorablePicture **)arg1)->long_term_pic_num; + int long_term_pic_num2 = + (*(struct StorablePicture **)arg2)->long_term_pic_num; + + if (long_term_pic_num1 < long_term_pic_num2) + return -1; + if (long_term_pic_num1 > long_term_pic_num2) + return 1; + else + return 0; +} + +/*! + ************************************************************************ + * \brief + * compares two frame stores by pic_num for qsort in descending order + * + ************************************************************************ + */ +static inline int compare_fs_by_frame_num_desc(const void *arg1, + const void *arg2) +{ + int frame_num_wrap1 = (*(struct FrameStore **)arg1)->frame_num_wrap; + int frame_num_wrap2 = (*(struct FrameStore **)arg2)->frame_num_wrap; + + if (frame_num_wrap1 < frame_num_wrap2) + return 1; + if (frame_num_wrap1 > frame_num_wrap2) + return -1; + else + return 0; +} + + +/*! + ************************************************************************ + * \brief + * compares two frame stores by lt_pic_num for qsort in descending order + * + ************************************************************************ + */ +static inline int compare_fs_by_lt_pic_idx_asc(const void *arg1, + const void *arg2) +{ + int long_term_frame_idx1 = + (*(struct FrameStore **)arg1)->long_term_frame_idx; + int long_term_frame_idx2 = + (*(struct FrameStore **)arg2)->long_term_frame_idx; + + if (long_term_frame_idx1 < long_term_frame_idx2) + return -1; + else if (long_term_frame_idx1 > long_term_frame_idx2) + return 1; + else + return 0; +} + + +/*! + ************************************************************************ + * \brief + * compares two stored pictures by poc for qsort in ascending order + * + ************************************************************************ + */ +static inline int compare_pic_by_poc_asc(const void *arg1, const void *arg2) +{ + int poc1 = (*(struct StorablePicture **)arg1)->poc; + int poc2 = (*(struct StorablePicture **)arg2)->poc; + + if (poc1 < poc2) + return -1; + else if (poc1 > poc2) + return 1; + else + return 0; +} + + +/*! + ************************************************************************ + * \brief + * compares two stored pictures by poc for qsort in descending order + * + ************************************************************************ + */ +static inline int compare_pic_by_poc_desc(const void *arg1, const void *arg2) +{ + int poc1 = (*(struct StorablePicture **)arg1)->poc; + int poc2 = (*(struct StorablePicture **)arg2)->poc; + + if (poc1 < poc2) + return 1; + else if (poc1 > poc2) + return -1; + else + return 0; +} + + +/*! + ************************************************************************ + * \brief + * compares two frame stores by poc for qsort in ascending order + * + ************************************************************************ + */ +static inline int compare_fs_by_poc_asc(const void *arg1, const void *arg2) +{ + int poc1 = (*(struct FrameStore **)arg1)->poc; + int poc2 = (*(struct FrameStore **)arg2)->poc; + + if (poc1 < poc2) + return -1; + else if (poc1 > poc2) + return 1; + else + return 0; +} + + +/*! + ************************************************************************ + * \brief + * compares two frame stores by poc for qsort in descending order + * + ************************************************************************ + */ +static inline int compare_fs_by_poc_desc(const void *arg1, const void *arg2) +{ + int poc1 = (*(struct FrameStore **)arg1)->poc; + int poc2 = (*(struct FrameStore **)arg2)->poc; + + if (poc1 < poc2) + return 1; + else if (poc1 > poc2) + return -1; + else + return 0; +} + +/*! + ************************************************************************ + * \brief + * returns true, if picture is short term reference picture + * + ************************************************************************ + */ +static inline int is_short_ref(struct StorablePicture *s) +{ +#ifdef ERROR_CHECK + return (s && + (s->used_for_reference) && (!(s->is_long_term))); +#else + return (s->used_for_reference) && (!(s->is_long_term)); +#endif +} + + +/*! + ************************************************************************ + * \brief + * returns true, if picture is long term reference picture + * + ************************************************************************ + */ +static inline int is_long_ref(struct StorablePicture *s) +{ +#ifdef ERROR_CHECK + return (s && + s->used_for_reference) && (s->is_long_term); +#else + return (s->used_for_reference) && (s->is_long_term); +#endif +} + +/*! + ************************************************************************ + * \brief + * Initialize reference lists for a P Slice + * + ************************************************************************ + */ +/*! + ************************************************************************ + * \brief + * Generates a alternating field list from a given FrameStore list + * + ************************************************************************ + */ +static void gen_pic_list_from_frame_list(enum PictureStructure currStructure, + struct FrameStore **fs_list, int list_idx, + struct StorablePicture **list, + char *list_size, int long_term) +{ + int top_idx = 0; + int bot_idx = 0; + + int (*is_ref)(struct StorablePicture *s) = (long_term) ? is_long_ref : + is_short_ref; + + + if (currStructure == TOP_FIELD) { + while ((top_idx < list_idx) || (bot_idx < list_idx)) { + for (; top_idx < list_idx; top_idx++) { + if (fs_list[top_idx]->is_used & 1) { + if (is_ref(fs_list[top_idx]-> + top_field)) { + /* short term ref pic */ + list[(short) *list_size] = + fs_list[top_idx]->top_field; + (*list_size)++; + top_idx++; + break; + } + } + } + for (; bot_idx < list_idx; bot_idx++) { + if (fs_list[bot_idx]->is_used & 2) { + if (is_ref(fs_list[bot_idx]-> + bottom_field)) { + /* short term ref pic */ + list[(short) *list_size] = + fs_list[bot_idx]->bottom_field; + (*list_size)++; + bot_idx++; + break; + } + } + } + } + } + if (currStructure == BOTTOM_FIELD) { + while ((top_idx < list_idx) || (bot_idx < list_idx)) { + for (; bot_idx < list_idx; bot_idx++) { + if (fs_list[bot_idx]->is_used & 2) { + if (is_ref(fs_list[bot_idx]-> + bottom_field)) { + /* short term ref pic */ + list[(short) *list_size] = + fs_list[bot_idx]->bottom_field; + (*list_size)++; + bot_idx++; + break; + } + } + } + for (; top_idx < list_idx; top_idx++) { + if (fs_list[top_idx]->is_used & 1) { + if (is_ref(fs_list[top_idx]-> + top_field)) { + /* short term ref pic */ + list[(short) *list_size] = + fs_list[top_idx]->top_field; + (*list_size)++; + top_idx++; + break; + } + } + } + } + } +} + +static void init_lists_p_slice(struct Slice *currSlice) +{ + struct VideoParameters *p_Vid = currSlice->p_Vid; + struct DecodedPictureBuffer *p_Dpb = currSlice->p_Dpb; + struct h264_dpb_stru *p_H264_Dpb = container_of(p_Dpb, + struct h264_dpb_stru, mDPB); + + unsigned int i; + + int list0idx = 0; + int listltidx = 0; + + struct FrameStore **fs_list0; + struct FrameStore **fs_listlt; + +#if (MVC_EXTENSION_ENABLE) + currSlice->listinterviewidx0 = 0; + currSlice->listinterviewidx1 = 0; +#endif + + if (currSlice->structure == FRAME) { + for (i = 0; i < p_Dpb->ref_frames_in_buffer; i++) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i] == NULL || + p_Dpb->fs_ref[i]->frame == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p_Dpb->fs_ref[i]->is_used == 3) { + if ((p_Dpb->fs_ref[i]->frame-> + used_for_reference) && + (!p_Dpb->fs_ref[i]->frame-> + is_long_term)) { + currSlice->listX[0][list0idx++] = + p_Dpb->fs_ref[i]->frame; + } + } + } + /* order list 0 by PicNum */ + qsort((void *)currSlice->listX[0], list0idx, + sizeof(struct StorablePicture *), + compare_pic_by_pic_num_desc); + currSlice->listXsize[0] = (char) list0idx; + CHECK_VALID(currSlice->listXsize[0], 0); + if (h264_debug_flag & PRINT_FLAG_DPB_DETAIL) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "listX[0] (PicNum): "); + for (i = 0; i < list0idx; i++) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "%d ", + currSlice->listX[0][i]->pic_num); + } + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "\n"); + } + /* long term handling */ + for (i = 0; i < p_Dpb->ltref_frames_in_buffer; i++) { + if (p_Dpb->fs_ltref[i]->is_used == 3) { + if (p_Dpb->fs_ltref[i]->frame->is_long_term) { + currSlice->listX[0][list0idx++] = + p_Dpb->fs_ltref[i]->frame; + } + } + } + qsort((void *)&currSlice->listX[0][ + (short) currSlice->listXsize[0]], + list0idx - currSlice->listXsize[0], + sizeof(struct StorablePicture *), + compare_pic_by_lt_pic_num_asc); + currSlice->listXsize[0] = (char) list0idx; + CHECK_VALID(currSlice->listXsize[0], 0); + } else { +#if 0 + fs_list0 = calloc(p_Dpb->size, sizeof(struct FrameStore *)); + if (fs_list0 == NULL) + no_mem_exit("init_lists: fs_list0"); + fs_listlt = calloc(p_Dpb->size, sizeof(struct FrameStore *)); + if (fs_listlt == NULL) + no_mem_exit("init_lists: fs_listlt"); +#else + fs_list0 = &(p_Dpb->fs_list0[0]); + fs_listlt = &(p_Dpb->fs_listlt[0]); +#endif + for (i = 0; i < p_Dpb->ref_frames_in_buffer; i++) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i] == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p_Dpb->fs_ref[i]->is_reference) + fs_list0[list0idx++] = p_Dpb->fs_ref[i]; + } + + qsort((void *)fs_list0, list0idx, sizeof(struct FrameStore *), + compare_fs_by_frame_num_desc); + + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "fs_list0 (FrameNum): "); + for (i = 0; i < list0idx; i++) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "%d ", + fs_list0[i]->frame_num_wrap); + } + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "\n"); + + currSlice->listXsize[0] = 0; + gen_pic_list_from_frame_list(currSlice->structure, fs_list0, + list0idx, currSlice->listX[0], + &currSlice->listXsize[0], 0); + + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "listX[0] (PicNum): "); + for (i = 0; i < currSlice->listXsize[0]; i++) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "%d ", + currSlice->listX[0][i]->pic_num); + } + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "\n"); + + /* long term handling */ + for (i = 0; i < p_Dpb->ltref_frames_in_buffer; i++) + fs_listlt[listltidx++] = p_Dpb->fs_ltref[i]; + + qsort((void *)fs_listlt, listltidx, sizeof(struct FrameStore *), + compare_fs_by_lt_pic_idx_asc); + + gen_pic_list_from_frame_list(currSlice->structure, fs_listlt, + listltidx, currSlice->listX[0], + &currSlice->listXsize[0], 1); + + /* free(fs_list0); */ + /* free(fs_listlt); */ + } + currSlice->listXsize[1] = 0; + + + /* set max size */ + currSlice->listXsize[0] = (char) imin(currSlice->listXsize[0], + currSlice->num_ref_idx_active[LIST_0]); + currSlice->listXsize[1] = (char) imin(currSlice->listXsize[1], + currSlice->num_ref_idx_active[LIST_1]); + CHECK_VALID(currSlice->listXsize[0], 0); + CHECK_VALID(currSlice->listXsize[1], 1); + + /* set the unused list entries to NULL */ + for (i = currSlice->listXsize[0]; i < (MAX_LIST_SIZE); i++) + currSlice->listX[0][i] = p_Vid->no_reference_picture; + for (i = currSlice->listXsize[1]; i < (MAX_LIST_SIZE); i++) + currSlice->listX[1][i] = p_Vid->no_reference_picture; + +#if PRINTREFLIST +#if (MVC_EXTENSION_ENABLE) + /* print out for h264_debug_flag purpose */ + if ((p_Vid->profile_idc == MVC_HIGH || + p_Vid->profile_idc == STEREO_HIGH) && + currSlice->current_slice_nr == 0) { + if (currSlice->listXsize[0] > 0) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "\n"); + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + " ** (CurViewID:%d %d) %s Ref Pic List 0 ****\n", + currSlice->view_id, + currSlice->ThisPOC, + currSlice->structure == FRAME ? "FRM" : + (currSlice->structure == TOP_FIELD ? + "TOP" : "BOT")); + for (i = 0; i < (unsigned int)(currSlice-> + listXsize[0]); i++) { /* ref list 0 */ + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + " %2d -> POC: %4d PicNum: %4d ViewID: %d\n", + i, + currSlice->listX[0][i]->poc, + currSlice->listX[0][i]->pic_num, + currSlice->listX[0][i]->view_id); + } + } + } +#endif +#endif +} + + +/*! + ************************************************************************ + * \brief + * Initialize reference lists + * + ************************************************************************ + */ +static void init_mbaff_lists(struct h264_dpb_stru *p_H264_Dpb, + struct Slice *currSlice) +{ + unsigned int j; + int i; + struct VideoParameters *p_Vid = &p_H264_Dpb->mVideo; + for (i = 2; i < 6; i++) { + for (j = 0; j < MAX_LIST_SIZE; j++) + currSlice->listX[i][j] = p_Vid->no_reference_picture; + currSlice->listXsize[i] = 0; + } + + for (i = 0; i < currSlice->listXsize[0]; i++) { +#ifdef ERROR_CHECK + if (currSlice->listX[0][i] == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + pr_info( + "error currSlice->listX[0][%d] is NULL\r\n", i); + break; + } +#endif + currSlice->listX[2][2 * i] = + currSlice->listX[0][i]->top_field; + currSlice->listX[2][2 * i + 1] = + currSlice->listX[0][i]->bottom_field; + currSlice->listX[4][2 * i] = + currSlice->listX[0][i]->bottom_field; + currSlice->listX[4][2 * i + 1] = + currSlice->listX[0][i]->top_field; + } + currSlice->listXsize[2] = currSlice->listXsize[4] = + currSlice->listXsize[0] * 2; + + for (i = 0; i < currSlice->listXsize[1]; i++) { +#ifdef ERROR_CHECK + if (currSlice->listX[1][i] == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + pr_info( + "error currSlice->listX[1][%d] is NULL\r\n", i); + break; + } +#endif + currSlice->listX[3][2 * i] = + currSlice->listX[1][i]->top_field; + currSlice->listX[3][2 * i + 1] = + currSlice->listX[1][i]->bottom_field; + currSlice->listX[5][2 * i] = + currSlice->listX[1][i]->bottom_field; + currSlice->listX[5][2 * i + 1] = + currSlice->listX[1][i]->top_field; + } + currSlice->listXsize[3] = currSlice->listXsize[5] = + currSlice->listXsize[1] * 2; +} + + + +static void init_lists_i_slice(struct Slice *currSlice) +{ + +#if (MVC_EXTENSION_ENABLE) + currSlice->listinterviewidx0 = 0; + currSlice->listinterviewidx1 = 0; +#endif + + currSlice->listXsize[0] = 0; + currSlice->listXsize[1] = 0; +} + +static void init_lists_b_slice(struct Slice *currSlice) +{ + struct VideoParameters *p_Vid = currSlice->p_Vid; + struct DecodedPictureBuffer *p_Dpb = currSlice->p_Dpb; + struct h264_dpb_stru *p_H264_Dpb = container_of(p_Dpb, + struct h264_dpb_stru, mDPB); + + unsigned int i; + int j; + + int list0idx = 0; + int list0idx_1 = 0; + int listltidx = 0; + + struct FrameStore **fs_list0; + struct FrameStore **fs_list1; + struct FrameStore **fs_listlt; + +#if (MVC_EXTENSION_ENABLE) + currSlice->listinterviewidx0 = 0; + currSlice->listinterviewidx1 = 0; +#endif + + { + /* B-Slice */ + if (currSlice->structure == FRAME) { + for (i = 0; i < p_Dpb->ref_frames_in_buffer; i++) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i] == NULL || + p_Dpb->fs_ref[i]->frame == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if ((p_Dpb->fs_ref[i]->is_used == 3) && + ((p_Dpb->fs_ref[i]->frame-> + used_for_reference) && + (!p_Dpb->fs_ref[i]->frame-> + is_long_term)) && + (currSlice->framepoc >= + p_Dpb->fs_ref[i]->frame->poc)) { + /* !KS use >= for error + * concealment + */ + currSlice->listX[0][list0idx++] = + p_Dpb->fs_ref[i]->frame; + } + } + qsort((void *)currSlice->listX[0], list0idx, + sizeof(struct StorablePicture *), + compare_pic_by_poc_desc); + + /* get the backward reference picture + * (POC>current POC) in list0; + */ + list0idx_1 = list0idx; + for (i = 0; i < p_Dpb->ref_frames_in_buffer; i++) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i] == NULL || + p_Dpb->fs_ref[i]->frame == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if ((p_Dpb->fs_ref[i]->is_used == 3) && + ((p_Dpb->fs_ref[i]->frame-> + used_for_reference) && + (!p_Dpb->fs_ref[i]->frame-> + is_long_term)) && + (currSlice->framepoc < + p_Dpb->fs_ref[i]->frame->poc)) { + currSlice-> + listX[0][list0idx++] = + p_Dpb->fs_ref[i]->frame; + } + } + qsort((void *)&currSlice->listX[0][list0idx_1], + list0idx - list0idx_1, + sizeof(struct StorablePicture *), + compare_pic_by_poc_asc); + + for (j = 0; j < list0idx_1; j++) { + currSlice-> + listX[1][list0idx - list0idx_1 + j] = + currSlice->listX[0][j]; + } + for (j = list0idx_1; j < list0idx; j++) { + currSlice->listX[1][j - list0idx_1] = + currSlice->listX[0][j]; + } + + currSlice->listXsize[0] = currSlice->listXsize[1] = + (char) list0idx; + CHECK_VALID(currSlice->listXsize[0], 0); + CHECK_VALID(currSlice->listXsize[1], 1); + + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "listX[0] (PicNum): "); + for (i = 0; i < currSlice->listXsize[0]; i++) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "%d ", + currSlice->listX[0][i]->pic_num); + } + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "\n"); + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "listX[1] (PicNum): "); + for (i = 0; i < currSlice->listXsize[1]; i++) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "%d ", + currSlice->listX[1][i]->pic_num); + } + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "\n"); + /* dpb_print(p_H264_Dpb->decoder_index, + * PRINT_FLAG_DPB_DETAIL, + * "currSlice->listX[0] currPoc=%d (Poc): ", + * p_Vid->framepoc); + * for (i=0; ilistXsize[0]; i++) { + * dpb_print(p_H264_Dpb->decoder_index, + * PRINT_FLAG_DPB_DETAIL, + * "%d ", currSlice->listX[0][i]->poc); + * } + * dpb_print(p_H264_Dpb->decoder_index, + * PRINT_FLAG_DPB_DETAIL, "\n"); + * dpb_print(p_H264_Dpb->decoder_index, + * PRINT_FLAG_DPB_DETAIL, + * "currSlice->listX[1] currPoc=%d (Poc): ", + * p_Vid->framepoc); + * for (i=0; ilistXsize[1]; i++) { + * dpb_print(p_H264_Dpb->decoder_index, + * PRINT_FLAG_DPB_DETAIL, + * "%d ", + * currSlice->listX[1][i]->poc); + * } + * dpb_print(p_H264_Dpb->decoder_index, + * PRINT_FLAG_DPB_DETAIL, "\n"); + */ + + /* long term handling */ + for (i = 0; i < p_Dpb->ltref_frames_in_buffer; i++) { + if (p_Dpb->fs_ltref[i]->is_used == 3) { + if (p_Dpb->fs_ltref[i]->frame-> + is_long_term) { + currSlice-> + listX[0][list0idx] = + p_Dpb->fs_ltref[i]->frame; + currSlice-> + listX[1][list0idx++] = + p_Dpb->fs_ltref[i]->frame; + } + } + } + qsort((void *)&currSlice-> + listX[0][(short) currSlice->listXsize[0]], + list0idx - currSlice->listXsize[0], + sizeof(struct StorablePicture *), + compare_pic_by_lt_pic_num_asc); + qsort((void *)&currSlice-> + listX[1][(short) currSlice->listXsize[0]], + list0idx - currSlice->listXsize[0], + sizeof(struct StorablePicture *), + compare_pic_by_lt_pic_num_asc); + currSlice->listXsize[0] = currSlice->listXsize[1] = + (char) list0idx; + CHECK_VALID(currSlice->listXsize[0], 0); + CHECK_VALID(currSlice->listXsize[1], 1); + } else { +#if 0 + fs_list0 = calloc(p_Dpb->size, + sizeof(struct FrameStore *)); + if (fs_list0 == NULL) + no_mem_exit("init_lists: fs_list0"); + fs_list1 = calloc(p_Dpb->size, + sizeof(struct FrameStore *)); + if (fs_list1 == NULL) + no_mem_exit("init_lists: fs_list1"); + fs_listlt = calloc(p_Dpb->size, + sizeof(struct FrameStore *)); + if (fs_listlt == NULL) + no_mem_exit("init_lists: fs_listlt"); +#else + fs_list0 = &(p_Dpb->fs_list0[0]); + fs_list1 = &(p_Dpb->fs_list1[0]); + fs_listlt = &(p_Dpb->fs_listlt[0]); + +#endif + currSlice->listXsize[0] = 0; + currSlice->listXsize[1] = 1; + + for (i = 0; i < p_Dpb->ref_frames_in_buffer; i++) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i] == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p_Dpb->fs_ref[i]->is_used) { + if (currSlice->ThisPOC >= + p_Dpb->fs_ref[i]->poc) { + fs_list0[list0idx++] = + p_Dpb->fs_ref[i]; + } + } + } + qsort((void *)fs_list0, list0idx, + sizeof(struct FrameStore *), + compare_fs_by_poc_desc); + list0idx_1 = list0idx; + for (i = 0; i < p_Dpb->ref_frames_in_buffer; i++) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i] == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p_Dpb->fs_ref[i]->is_used) { + if (currSlice->ThisPOC < + p_Dpb->fs_ref[i]->poc) { + fs_list0[list0idx++] = + p_Dpb->fs_ref[i]; + } + } + } + qsort((void *)&fs_list0[list0idx_1], + list0idx - list0idx_1, + sizeof(struct FrameStore *), + compare_fs_by_poc_asc); + + for (j = 0; j < list0idx_1; j++) { + fs_list1[list0idx - list0idx_1 + j] = + fs_list0[j]; + } + for (j = list0idx_1; j < list0idx; j++) + fs_list1[j - list0idx_1] = fs_list0[j]; + + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "fs_list0 currPoc=%d (Poc): ", + currSlice->ThisPOC); + for (i = 0; i < list0idx; i++) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "%d ", + fs_list0[i]->poc); + } + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "\n"); + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "fs_list1 currPoc=%d (Poc): ", + currSlice->ThisPOC); + for (i = 0; i < list0idx; i++) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "%d ", + fs_list1[i]->poc); + } + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "\n"); + + currSlice->listXsize[0] = 0; + currSlice->listXsize[1] = 0; + gen_pic_list_from_frame_list(currSlice->structure, + fs_list0, list0idx, + currSlice->listX[0], + &currSlice->listXsize[0], 0); + gen_pic_list_from_frame_list(currSlice->structure, + fs_list1, list0idx, + currSlice->listX[1], + &currSlice->listXsize[1], 0); + + /* dpb_print(p_H264_Dpb->decoder_index, + * PRINT_FLAG_DPB_DETAIL, + * "currSlice->listX[0] currPoc=%d (Poc): ", + * p_Vid->framepoc); + * for (i=0; ilistXsize[0]; i++) { + * dpb_print(p_H264_Dpb->decoder_index, + * PRINT_FLAG_DPB_DETAIL, "%d ", + * currSlice->listX[0][i]->poc); + * } + * dpb_print(p_H264_Dpb->decoder_index, + * PRINT_FLAG_DPB_DETAIL, "\n"); + */ + /* dpb_print(p_H264_Dpb->decoder_index, + * PRINT_FLAG_DPB_DETAIL, + * "currSlice->listX[1] currPoc=%d (Poc): ", + * p_Vid->framepoc); + * for (i=0; ilistXsize[1]; i++) { + * dpb_print(p_H264_Dpb->decoder_index, + * PRINT_FLAG_DPB_DETAIL, "%d ", + * currSlice->listX[1][i]->poc); + * } + * dpb_print(p_H264_Dpb->decoder_index, + * PRINT_FLAG_DPB_DETAIL, + * "\n"); + */ + + /* long term handling */ + for (i = 0; i < p_Dpb->ltref_frames_in_buffer; i++) + fs_listlt[listltidx++] = p_Dpb->fs_ltref[i]; + + qsort((void *)fs_listlt, listltidx, + sizeof(struct FrameStore *), + compare_fs_by_lt_pic_idx_asc); + + gen_pic_list_from_frame_list(currSlice->structure, + fs_listlt, listltidx, + currSlice->listX[0], + &currSlice->listXsize[0], 1); + gen_pic_list_from_frame_list(currSlice->structure, + fs_listlt, listltidx, + currSlice->listX[1], + &currSlice->listXsize[1], 1); + + /* free(fs_list0); */ + /* free(fs_list1); */ + /* free(fs_listlt); */ + } + } + + if ((currSlice->listXsize[0] == currSlice->listXsize[1]) && + (currSlice->listXsize[0] > 1)) { + /* check if lists are identical, + *if yes swap first two elements of currSlice->listX[1] + */ + int diff = 0; + + for (j = 0; j < currSlice->listXsize[0]; j++) { + if (currSlice->listX[0][j] != + currSlice->listX[1][j]) { + diff = 1; + break; + } + } + if (!diff) { + struct StorablePicture *tmp_s = + currSlice->listX[1][0]; + currSlice->listX[1][0] = currSlice->listX[1][1]; + currSlice->listX[1][1] = tmp_s; + } + } + + /* set max size */ + currSlice->listXsize[0] = (char) imin(currSlice->listXsize[0], + currSlice->num_ref_idx_active[LIST_0]); + currSlice->listXsize[1] = (char) imin(currSlice->listXsize[1], + currSlice->num_ref_idx_active[LIST_1]); + CHECK_VALID(currSlice->listXsize[0], 0); + CHECK_VALID(currSlice->listXsize[1], 1); + + /* set the unused list entries to NULL */ + for (i = currSlice->listXsize[0]; i < (MAX_LIST_SIZE); i++) + currSlice->listX[0][i] = p_Vid->no_reference_picture; + for (i = currSlice->listXsize[1]; i < (MAX_LIST_SIZE); i++) + currSlice->listX[1][i] = p_Vid->no_reference_picture; + +#if PRINTREFLIST +#if (MVC_EXTENSION_ENABLE) + /* print out for h264_debug_flag purpose */ + if ((p_Vid->profile_idc == MVC_HIGH || + p_Vid->profile_idc == STEREO_HIGH) && + currSlice->current_slice_nr == 0) { + if ((currSlice->listXsize[0] > 0) || + (currSlice->listXsize[1] > 0)) + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "\n"); + if (currSlice->listXsize[0] > 0) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + " ** (CurViewID:%d %d) %s Ref Pic List 0 ****\n", + currSlice->view_id, + currSlice->ThisPOC, + currSlice->structure == FRAME ? "FRM" : + (currSlice->structure == TOP_FIELD ? + "TOP" : "BOT")); + for (i = 0; i < (unsigned int)(currSlice-> + listXsize[0]); i++) { /* ref list 0 */ + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + " %2d -> POC: %4d PicNum: %4d ViewID: %d\n", + i, + currSlice->listX[0][i]->poc, + currSlice->listX[0][i]->pic_num, + currSlice->listX[0][i]->view_id); + } + } + if (currSlice->listXsize[1] > 0) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + " ** (CurViewID:%d %d) %s Ref Pic List 1 ****\n", + currSlice->view_id, + currSlice->ThisPOC, + currSlice->structure == FRAME ? "FRM" : + (currSlice->structure == TOP_FIELD ? "TOP" : + "BOT")); + for (i = 0; i < (unsigned int)(currSlice-> + listXsize[1]); i++) { /* ref list 1 */ + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + " %2d -> POC: %4d PicNum: %4d ViewID: %d\n", + i, + currSlice->listX[1][i]->poc, + currSlice->listX[1][i]->pic_num, + currSlice->listX[1][i]->view_id); + } + } + } +#endif +#endif +} + +static struct StorablePicture *get_short_term_pic(struct Slice *currSlice, + struct DecodedPictureBuffer *p_Dpb, int picNum) +{ + unsigned int i; + struct h264_dpb_stru *p_H264_Dpb = container_of(p_Dpb, + struct h264_dpb_stru, mDPB); + for (i = 0; i < p_Dpb->ref_frames_in_buffer; i++) { + if (currSlice->structure == FRAME) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i] == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p_Dpb->fs_ref[i]->is_reference == 3) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i]->frame == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if ((!p_Dpb->fs_ref[i]->frame-> + is_long_term) && + (p_Dpb->fs_ref[i]->frame-> + pic_num == picNum)) + return p_Dpb->fs_ref[i]->frame; + } + } else { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i] == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if (p_Dpb->fs_ref[i]->is_reference & 1) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i]->top_field == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if ((!p_Dpb->fs_ref[i]->top_field-> + is_long_term) && + (p_Dpb->fs_ref[i]->top_field-> + pic_num == picNum)) + return p_Dpb->fs_ref[i]->top_field; + } + if (p_Dpb->fs_ref[i]->is_reference & 2) { +#ifdef ERROR_CHECK + if (p_Dpb->fs_ref[i]->bottom_field == NULL) { + p_H264_Dpb->dpb_error_flag = __LINE__; + continue; + } +#endif + if ((!p_Dpb->fs_ref[i]->bottom_field-> + is_long_term) && + (p_Dpb->fs_ref[i]->bottom_field-> + pic_num == picNum)) + return p_Dpb->fs_ref[i]->bottom_field; + } + } + } + + return currSlice->p_Vid->no_reference_picture; +} + + +static void reorder_short_term(struct Slice *currSlice, int cur_list, + int num_ref_idx_lX_active_minus1, + int picNumLX, int *refIdxLX) +{ + struct h264_dpb_stru *p_H264_Dpb = container_of(currSlice->p_Vid, + struct h264_dpb_stru, mVideo); + + struct StorablePicture **RefPicListX = currSlice->listX[cur_list]; + int cIdx, nIdx; + + struct StorablePicture *picLX; + + picLX = get_short_term_pic(currSlice, currSlice->p_Dpb, picNumLX); + + for (cIdx = num_ref_idx_lX_active_minus1 + 1; cIdx > *refIdxLX; + cIdx--) { + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s: RefPicListX[ %d ] = RefPicListX[ %d ]\n", + __func__, cIdx, cIdx - 1); + RefPicListX[cIdx] = RefPicListX[cIdx - 1]; + } + + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s: RefPicListX[ %d ] = pic %x (%d)\n", __func__, + *refIdxLX, picLX, picNumLX); + + RefPicListX[(*refIdxLX)++] = picLX; + + nIdx = *refIdxLX; + + for (cIdx = *refIdxLX; cIdx <= num_ref_idx_lX_active_minus1 + 1; + cIdx++) { + if (RefPicListX[cIdx]) + if ((RefPicListX[cIdx]->is_long_term) || + (RefPicListX[cIdx]->pic_num != picNumLX)) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "%s: RefPicListX[ %d ] = RefPicListX[ %d ]\n", + __func__, nIdx, cIdx); + RefPicListX[nIdx++] = RefPicListX[cIdx]; + } + } +} + + +static struct StorablePicture *get_long_term_pic(struct Slice *currSlice, + struct DecodedPictureBuffer *p_Dpb, int LongtermPicNum) +{ + unsigned int i; + + for (i = 0; i < p_Dpb->ltref_frames_in_buffer; i++) { + if (currSlice->structure == FRAME) { + if (p_Dpb->fs_ltref[i]->is_reference == 3) + if ((p_Dpb->fs_ltref[i]->frame-> + is_long_term) && + (p_Dpb->fs_ltref[i]->frame-> + long_term_pic_num == + LongtermPicNum)) + return p_Dpb->fs_ltref[i]->frame; + } else { + if (p_Dpb->fs_ltref[i]->is_reference & 1) + if ((p_Dpb->fs_ltref[i]->top_field-> + is_long_term) && + (p_Dpb->fs_ltref[i]->top_field-> + long_term_pic_num == LongtermPicNum)) + return p_Dpb->fs_ltref[i]->top_field; + if (p_Dpb->fs_ltref[i]->is_reference & 2) + if ((p_Dpb->fs_ltref[i]->bottom_field-> + is_long_term) && + (p_Dpb->fs_ltref[i]->bottom_field-> + long_term_pic_num == + LongtermPicNum)) + return p_Dpb->fs_ltref[i]-> + bottom_field; + } + } + return NULL; +} + +/*! + ************************************************************************ + * \brief + * Reordering process for long-term reference pictures + * + ************************************************************************ + */ +static void reorder_long_term(struct Slice *currSlice, + struct StorablePicture **RefPicListX, + int num_ref_idx_lX_active_minus1, + int LongTermPicNum, int *refIdxLX) +{ + int cIdx, nIdx; + + struct StorablePicture *picLX; + + picLX = get_long_term_pic(currSlice, currSlice->p_Dpb, LongTermPicNum); + + for (cIdx = num_ref_idx_lX_active_minus1 + 1; cIdx > *refIdxLX; cIdx--) + RefPicListX[cIdx] = RefPicListX[cIdx - 1]; + + RefPicListX[(*refIdxLX)++] = picLX; + + nIdx = *refIdxLX; + + for (cIdx = *refIdxLX; cIdx <= num_ref_idx_lX_active_minus1 + 1; + cIdx++) { + if (RefPicListX[cIdx]) { + if ((!RefPicListX[cIdx]->is_long_term) || + (RefPicListX[cIdx]->long_term_pic_num != + LongTermPicNum)) + RefPicListX[nIdx++] = RefPicListX[cIdx]; + } + } +} + +static void reorder_ref_pic_list(struct Slice *currSlice, int cur_list) +{ + int *modification_of_pic_nums_idc = + currSlice->modification_of_pic_nums_idc[cur_list]; + int *abs_diff_pic_num_minus1 = + currSlice->abs_diff_pic_num_minus1[cur_list]; + int *long_term_pic_idx = currSlice->long_term_pic_idx[cur_list]; + int num_ref_idx_lX_active_minus1 = + currSlice->num_ref_idx_active[cur_list] - 1; + + struct VideoParameters *p_Vid = currSlice->p_Vid; + int i; + + int maxPicNum, currPicNum, picNumLXNoWrap, picNumLXPred, picNumLX; + int refIdxLX = 0; + + if (currSlice->structure == FRAME) { + maxPicNum = p_Vid->max_frame_num; + currPicNum = currSlice->frame_num; + } else { + maxPicNum = 2 * p_Vid->max_frame_num; + currPicNum = 2 * currSlice->frame_num + 1; + } + + picNumLXPred = currPicNum; + + for (i = 0; i < REORDERING_COMMAND_MAX_SIZE && + modification_of_pic_nums_idc[i] != 3; i++) { + if (modification_of_pic_nums_idc[i] > 3) { + struct h264_dpb_stru *p_H264_Dpb = + container_of(p_Vid, struct h264_dpb_stru, mVideo); + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_ERROR, + "error, Invalid modification_of_pic_nums_idc command\n"); + /*h264_debug_flag = 0x1f;*/ + break; + } + if (modification_of_pic_nums_idc[i] < 2) { + if (modification_of_pic_nums_idc[i] == 0) { + if (picNumLXPred - (abs_diff_pic_num_minus1[i] + + 1) < 0) + picNumLXNoWrap = picNumLXPred - + (abs_diff_pic_num_minus1[i] + 1) + + maxPicNum; + else + picNumLXNoWrap = picNumLXPred - + (abs_diff_pic_num_minus1[i] + 1); + } else { /* (modification_of_pic_nums_idc[i] == 1) */ + if (picNumLXPred + (abs_diff_pic_num_minus1[i] + + 1) >= maxPicNum) + picNumLXNoWrap = picNumLXPred + + (abs_diff_pic_num_minus1[i] + 1) - + maxPicNum; + else + picNumLXNoWrap = picNumLXPred + + (abs_diff_pic_num_minus1[i] + 1); + } + picNumLXPred = picNumLXNoWrap; + + if (picNumLXNoWrap > currPicNum) + picNumLX = picNumLXNoWrap - maxPicNum; + else + picNumLX = picNumLXNoWrap; + +#if (MVC_EXTENSION_ENABLE) + reorder_short_term(currSlice, cur_list, + num_ref_idx_lX_active_minus1, picNumLX, + &refIdxLX, -1); +#else + reorder_short_term(currSlice, cur_list, + num_ref_idx_lX_active_minus1, picNumLX, + &refIdxLX); +#endif + } else { /* (modification_of_pic_nums_idc[i] == 2) */ +#if (MVC_EXTENSION_ENABLE) + reorder_long_term(currSlice, currSlice->listX[cur_list], + num_ref_idx_lX_active_minus1, + long_term_pic_idx[i], &refIdxLX, -1); +#else + reorder_long_term(currSlice, currSlice->listX[cur_list], + num_ref_idx_lX_active_minus1, + long_term_pic_idx[i], &refIdxLX); +#endif + } + + } + /* that's a definition */ + currSlice->listXsize[cur_list] = + (char)(num_ref_idx_lX_active_minus1 + 1); +} + +static void reorder_lists(struct Slice *currSlice) +{ + struct VideoParameters *p_Vid = currSlice->p_Vid; + struct h264_dpb_stru *p_H264_Dpb = container_of(p_Vid, + struct h264_dpb_stru, mVideo); + int i; + + if ((currSlice->slice_type != I_SLICE) && + (currSlice->slice_type != SI_SLICE)) { + if (currSlice->ref_pic_list_reordering_flag[LIST_0]) + reorder_ref_pic_list(currSlice, LIST_0); + if (p_Vid->no_reference_picture == + currSlice-> + listX[0][currSlice->num_ref_idx_active[LIST_0] - 1]) { + if (p_Vid->non_conforming_stream) + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "RefPicList0[ %d ] is equal to 'no reference picture'\n", + currSlice-> + num_ref_idx_active[LIST_0] - 1); + else + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "RefPicList0 [ num_ref_idx_l0_active_minus1 ] is equal to 'no reference picture', invalid bitstream %d\n", + 500); + } + /* that's a definition */ + currSlice->listXsize[0] = + (char)currSlice->num_ref_idx_active[LIST_0]; + CHECK_VALID(currSlice->listXsize[0], 0); + if (h264_debug_flag & PRINT_FLAG_DPB_DETAIL) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "listX[0] reorder (PicNum): "); + for (i = 0; i < currSlice->listXsize[0]; i++) { + dpb_print_cont(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "%d ", + currSlice->listX[0][i]->pic_num); + } + dpb_print_cont(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "\n"); + } + } + + if (currSlice->slice_type == B_SLICE) { + if (currSlice->ref_pic_list_reordering_flag[LIST_1]) + reorder_ref_pic_list(currSlice, LIST_1); + if (p_Vid->no_reference_picture == + currSlice->listX[1][currSlice-> + num_ref_idx_active[LIST_1] - 1]) { + if (p_Vid->non_conforming_stream) + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "RefPicList1[ %d ] is equal to 'no reference picture'\n", + currSlice-> + num_ref_idx_active[LIST_1] - 1); + else + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "RefPicList1 [ num_ref_idx_l1_active_minus1 ] is equal to 'no reference picture', invalid bitstream %d\n", + 500); + } + /* that's a definition */ + currSlice->listXsize[1] = + (char)currSlice->num_ref_idx_active[LIST_1]; + if (h264_debug_flag & PRINT_FLAG_DPB_DETAIL) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "listX[1] reorder (PicNum): "); + for (i = 0; i < currSlice->listXsize[1]; i++) { + dpb_print_cont(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "%d ", + currSlice->listX[1][i]->pic_num); + } + dpb_print_cont(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "\n"); + } + } + + /* free_ref_pic_list_reordering_buffer(currSlice); */ + + if (currSlice->slice_type == P_SLICE) { +#if PRINTREFLIST + unsigned int i; +#if (MVC_EXTENSION_ENABLE) + /* print out for h264_debug_flag purpose */ + if ((p_Vid->profile_idc == MVC_HIGH || + p_Vid->profile_idc == STEREO_HIGH) && + currSlice->current_slice_nr == 0) { + if (currSlice->listXsize[0] > 0 + && (h264_debug_flag & PRINT_FLAG_DPB_DETAIL)) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "\n"); + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + " ** (FinalViewID:%d) %s Ref Pic List 0 ****\n", + currSlice->view_id, + currSlice->structure == FRAME ? + "FRM" : + (currSlice->structure == TOP_FIELD ? + "TOP" : "BOT")); + for (i = 0; i < (unsigned int)(currSlice-> + listXsize[0]); i++) { /* ref list 0 */ + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + " %2d -> POC: %4d PicNum: %4d ViewID: %d\n", + i, + currSlice->listX[0][i]->poc, + currSlice->listX[0][i]-> + pic_num, + currSlice->listX[0][i]-> + view_id); + } + } + } +#endif +#endif + } else if (currSlice->slice_type == B_SLICE) { +#if PRINTREFLIST + unsigned int i; +#if (MVC_EXTENSION_ENABLE) + /* print out for h264_debug_flag purpose */ + if ((p_Vid->profile_idc == MVC_HIGH || + p_Vid->profile_idc == STEREO_HIGH) && + currSlice->current_slice_nr == 0) { + if ((currSlice->listXsize[0] > 0) || + (currSlice->listXsize[1] > 0)) + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, "\n"); + if (currSlice->listXsize[0] > 0 + && (h264_debug_flag & PRINT_FLAG_DPB_DETAIL)) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + " ** (FinalViewID:%d) %s Ref Pic List 0 ****\n", + currSlice->view_id, + currSlice->structure == FRAME ? + "FRM" : + (currSlice->structure == TOP_FIELD ? + "TOP" : "BOT")); + for (i = 0; i < (unsigned int)(currSlice-> + listXsize[0]); i++) { /* ref list 0 */ + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + " %2d -> POC: %4d PicNum: %4d ViewID: %d\n", + i, + currSlice->listX[0][i]->poc, + currSlice->listX[0][i]-> + pic_num, + currSlice->listX[0][i]-> + view_id); + } + } + if (currSlice->listXsize[1] > 0 + && (h264_debug_flag & PRINT_FLAG_DPB_DETAIL)) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + " ** (FinalViewID:%d) %s Ref Pic List 1 ****\n", + currSlice->view_id, + currSlice->structure == FRAME ? + "FRM" : + (currSlice->structure == TOP_FIELD ? + "TOP" : "BOT")); + for (i = 0; i < (unsigned int)(currSlice-> + listXsize[1]); i++) { /* ref list 1 */ + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + " %2d -> POC: %4d PicNum: %4d ViewID: %d\n", + i, + currSlice->listX[1][i]->poc, + currSlice->listX[1][i]-> + pic_num, + currSlice->listX[1][i]-> + view_id); + } + } + } +#endif + +#endif + } +} + +void init_colocate_buf(struct h264_dpb_stru *p_H264_Dpb, int count) +{ + p_H264_Dpb->colocated_buf_map = 0; + p_H264_Dpb->colocated_buf_count = count; +} + +int allocate_colocate_buf(struct h264_dpb_stru *p_H264_Dpb) +{ + int i; + + for (i = 0; i < p_H264_Dpb->colocated_buf_count; i++) { + if (((p_H264_Dpb->colocated_buf_map >> i) & 0x1) == 0) { + p_H264_Dpb->colocated_buf_map |= (1 << i); + break; + } + } + if (i == p_H264_Dpb->colocated_buf_count) { + i = -1; + p_H264_Dpb->buf_alloc_fail = 1; + } + return i; +} + +int release_colocate_buf(struct h264_dpb_stru *p_H264_Dpb, int index) +{ + if (index >= 0) { + if (index >= p_H264_Dpb->colocated_buf_count) { + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_ERROR, + "%s error, index %d is bigger than buf count %d\n", + __func__, index, + p_H264_Dpb->colocated_buf_count); + } else { + if (((p_H264_Dpb->colocated_buf_map >> + index) & 0x1) == 0x1) { + p_H264_Dpb->colocated_buf_map &= + (~(1 << index)); + } else { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_ERROR, + "%s error, index %d is not allocated\n", + __func__, index); + } + } + } + return 0; +} + +void set_frame_output_flag(struct h264_dpb_stru *p_H264_Dpb, int index) +{ + struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB; + + p_H264_Dpb->mFrameStore[index].is_output = 1; + p_H264_Dpb->mFrameStore[index].pre_output = 0; + dump_dpb(p_Dpb, 0); +} + +#if 0 +void init_old_slice(OldSliceParams *p_old_slice) +{ + p_old_slice->field_pic_flag = 0; + p_old_slice->pps_id = INT_MAX; + p_old_slice->frame_num = INT_MAX; + p_old_slice->nal_ref_idc = INT_MAX; + p_old_slice->idr_flag = FALSE; + + p_old_slice->pic_oder_cnt_lsb = UINT_MAX; + p_old_slice->delta_pic_oder_cnt_bottom = INT_MAX; + + p_old_slice->delta_pic_order_cnt[0] = INT_MAX; + p_old_slice->delta_pic_order_cnt[1] = INT_MAX; +} + + +void copy_slice_info(struct Slice *currSlice, OldSliceParams *p_old_slice) +{ + struct VideoParameters *p_Vid = currSlice->p_Vid; + + p_old_slice->pps_id = currSlice->pic_parameter_set_id; + p_old_slice->frame_num = currSlice->frame_num; + /* p_Vid->frame_num; */ + p_old_slice->field_pic_flag = + currSlice->field_pic_flag; + /* p_Vid->field_pic_flag; */ + + if (currSlice->field_pic_flag) + p_old_slice->bottom_field_flag = currSlice->bottom_field_flag; + + p_old_slice->nal_ref_idc = currSlice->nal_reference_idc; + p_old_slice->idr_flag = (byte) currSlice->idr_flag; + + if (currSlice->idr_flag) + p_old_slice->idr_pic_id = currSlice->idr_pic_id; + + if (p_Vid->active_sps->pic_order_cnt_type == 0) { + p_old_slice->pic_oder_cnt_lsb = + currSlice->pic_order_cnt_lsb; + p_old_slice->delta_pic_oder_cnt_bottom = + currSlice->delta_pic_order_cnt_bottom; + } + + if (p_Vid->active_sps->pic_order_cnt_type == 1) { + p_old_slice->delta_pic_order_cnt[0] = + currSlice->delta_pic_order_cnt[0]; + p_old_slice->delta_pic_order_cnt[1] = + currSlice->delta_pic_order_cnt[1]; + } +#if (MVC_EXTENSION_ENABLE) + p_old_slice->view_id = currSlice->view_id; + p_old_slice->inter_view_flag = currSlice->inter_view_flag; + p_old_slice->anchor_pic_flag = currSlice->anchor_pic_flag; +#endif + p_old_slice->layer_id = currSlice->layer_id; +} + +int is_new_picture(StorablePicture *dec_picture, struct Slice *currSlice, + OldSliceParams *p_old_slice) +{ + struct VideoParameters *p_Vid = currSlice->p_Vid; + + int result = 0; + + result |= (dec_picture == NULL); + + result |= (p_old_slice->pps_id != currSlice->pic_parameter_set_id); + + result |= (p_old_slice->frame_num != currSlice->frame_num); + + result |= (p_old_slice->field_pic_flag != currSlice->field_pic_flag); + + if (currSlice->field_pic_flag && p_old_slice->field_pic_flag) { + result |= (p_old_slice->bottom_field_flag != + currSlice->bottom_field_flag); + } + + result |= (p_old_slice->nal_ref_idc != + currSlice->nal_reference_idc) && + ((p_old_slice->nal_ref_idc == 0) || + (currSlice->nal_reference_idc == 0)); + result |= (p_old_slice->idr_flag != currSlice->idr_flag); + + if (currSlice->idr_flag && p_old_slice->idr_flag) + result |= (p_old_slice->idr_pic_id != currSlice->idr_pic_id); + + if (p_Vid->active_sps->pic_order_cnt_type == 0) { + result |= (p_old_slice->pic_oder_cnt_lsb != + currSlice->pic_order_cnt_lsb); + if (p_Vid->active_pps-> + bottom_field_pic_order_in_frame_present_flag == 1 && + !currSlice->field_pic_flag) { + result |= (p_old_slice->delta_pic_oder_cnt_bottom != + currSlice->delta_pic_order_cnt_bottom); + } + } + + if (p_Vid->active_sps->pic_order_cnt_type == 1) { + if (!p_Vid->active_sps->delta_pic_order_always_zero_flag) { + result |= (p_old_slice->delta_pic_order_cnt[0] != + currSlice->delta_pic_order_cnt[0]); + if (p_Vid->active_pps-> + bottom_field_pic_order_in_frame_present_flag == 1 && + !currSlice->field_pic_flag) { + result |= (p_old_slice-> + delta_pic_order_cnt[1] != + currSlice->delta_pic_order_cnt[1]); + } + } + } + +#if (MVC_EXTENSION_ENABLE) + result |= (currSlice->view_id != p_old_slice->view_id); + result |= (currSlice->inter_view_flag != p_old_slice->inter_view_flag); + result |= (currSlice->anchor_pic_flag != p_old_slice->anchor_pic_flag); +#endif + result |= (currSlice->layer_id != p_old_slice->layer_id); + return result; +} +#else +int is_new_picture(struct StorablePicture *dec_picture, + struct h264_dpb_stru *p_H264_Dpb, + struct OldSliceParams *p_old_slice) +{ + int ret = 0; + + if (p_H264_Dpb->dpb_param.l.data[FIRST_MB_IN_SLICE] == 0) + ret = 1; + return ret; +} + +#endif + +/* +* release bufspec and pic for picture not in dpb buf +*/ +int release_picture(struct h264_dpb_stru *p_H264_Dpb, + struct StorablePicture *pic) +{ + struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB; + + if (p_Dpb->last_picture == NULL) { + if (pic->colocated_buf_index >= 0) { + release_colocate_buf(p_H264_Dpb, + pic->colocated_buf_index); + pic->colocated_buf_index = -1; + } + release_buf_spec_num(p_H264_Dpb->vdec, pic->buf_spec_num); + } else { + if (pic->buf_spec_is_alloced == 1) + release_buf_spec_num(p_H264_Dpb->vdec, + pic->buf_spec_num); + } + + free_picture(p_H264_Dpb, pic); + return 0; +} + +#ifdef ERROR_HANDLE_TEST +/* +* remove all pictures in dpb and release bufspec/pic of them +*/ +void remove_dpb_pictures(struct h264_dpb_stru *p_H264_Dpb) +{ + /* struct VideoParameters *p_Vid = p_Dpb->p_Vid; */ + struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB; + struct Slice *currSlice = &p_H264_Dpb->mSlice; + unsigned i, j; + + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "%s\n", __func__); + + if (!p_Dpb->init_done) + return; + + for (i = 0; i < p_Dpb->used_size; i++) { + if (p_Dpb->fs[i]->colocated_buf_index >= 0) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "release_colocate_buf[%d] for fs[%d]\n", + p_Dpb->fs[i]->colocated_buf_index, i); + + release_colocate_buf(p_H264_Dpb, + p_Dpb->fs[i]->colocated_buf_index); /* rain */ + p_Dpb->fs[i]->colocated_buf_index = -1; + } + if (!p_Dpb->fs[i]->pre_output) { + release_buf_spec_num(p_H264_Dpb->vdec, + p_Dpb->fs[i]->buf_spec_num); + p_Dpb->fs[i]->buf_spec_num = -1; + } + remove_frame_from_dpb(p_H264_Dpb, i); + } + + for (i = 0; i < p_Dpb->used_size; i++) { + p_Dpb->fs_ref[i] = NULL; + p_Dpb->fs_ltref[i] = NULL; + p_Dpb->fs_list0[i] = NULL; + p_Dpb->fs_list1[i] = NULL; + p_Dpb->fs_listlt[i] = NULL; + } + for (i = 0; i < 2; i++) { + currSlice->listXsize[i] = 0; + for (j = 0; j < (MAX_LIST_SIZE * 2); j++) + currSlice->listX[i][j] = NULL; + } + p_Dpb->ref_frames_in_buffer = 0; + p_Dpb->ltref_frames_in_buffer = 0; + p_Dpb->last_output_poc = INT_MIN; +} +#endif + +static void check_frame_store_same_pic_num(struct DecodedPictureBuffer *p_Dpb, + struct StorablePicture *p, struct Slice *currSlice) +{ + if (p_Dpb->last_picture) { + if ((int)p_Dpb->last_picture->frame_num == p->pic_num) { + if (((p->structure == TOP_FIELD) && + (p_Dpb->last_picture->is_used == 2)) || + ((p->structure == BOTTOM_FIELD) && + (p_Dpb->last_picture->is_used == 1))) { + if ((p->used_for_reference && + (p_Dpb->last_picture-> + is_orig_reference != 0)) || + (!p->used_for_reference && + (p_Dpb->last_picture-> + is_orig_reference == 0))) { + p->buf_spec_num = + p_Dpb->last_picture-> + buf_spec_num; + p->buf_spec_is_alloced = 0; + p->colocated_buf_index = p_Dpb-> + last_picture-> + colocated_buf_index; + if (currSlice->structure == + TOP_FIELD) { + p->bottom_poc = + p_Dpb->last_picture-> + bottom_field->poc; + } else { + p->top_poc = + p_Dpb->last_picture-> + top_field->poc; + } + p->frame_poc = imin(p->bottom_poc, + p->top_poc); + } + } + } + } +} + +int h264_slice_header_process(struct h264_dpb_stru *p_H264_Dpb) +{ + + int new_pic_flag = 0; + struct Slice *currSlice = &p_H264_Dpb->mSlice; + struct VideoParameters *p_Vid = &p_H264_Dpb->mVideo; + struct DecodedPictureBuffer *p_Dpb = + &p_H264_Dpb->mDPB; +#if 0 + new_pic_flag = is_new_picture(p_H264_Dpb->mVideo.dec_picture, + p_H264_Dpb, + &p_H264_Dpb->mVideo.old_slice); + + if (new_pic_flag) { /* new picture */ + if (p_H264_Dpb->mVideo.dec_picture) { + store_picture_in_dpb(p_H264_Dpb, + p_H264_Dpb->mVideo.dec_picture); + /* dump_dpb(&p_H264_Dpb->mDPB); */ + } + } +#else + new_pic_flag = (p_H264_Dpb->mVideo.dec_picture == NULL); +#endif + p_H264_Dpb->buf_alloc_fail = 0; + p_H264_Dpb->dpb_error_flag = 0; + slice_prepare(p_H264_Dpb, &p_H264_Dpb->mDPB, &p_H264_Dpb->mVideo, + &p_H264_Dpb->mSPS, &p_H264_Dpb->mSlice); + + if (p_Dpb->num_ref_frames != p_H264_Dpb->mSPS.num_ref_frames) { + dpb_print(p_H264_Dpb->decoder_index, 0, + "num_ref_frames change from %d to %d\r\n", + p_Dpb->num_ref_frames, p_H264_Dpb->mSPS.num_ref_frames); + p_Dpb->num_ref_frames = p_H264_Dpb->mSPS.num_ref_frames; + } + /* if (p_Vid->active_sps != sps) { */ + if (p_H264_Dpb->mDPB.init_done == 0) { + /*init_global_buffers(p_Vid, 0); + * ** * *if (!p_Vid->no_output_of_prior_pics_flag) + ** * *{ + ** * * flush_dpb(p_Vid->p_Dpb_layer[0]); + ** * *} + ** * *init_dpb(p_Vid, p_Vid->p_Dpb_layer[0], 0); + */ + init_dpb(p_H264_Dpb, 0); + } + + + if (new_pic_flag) { /* new picture */ + dpb_print(p_H264_Dpb->decoder_index, PRINT_FLAG_DPB_DETAIL, + "check frame_num gap: cur frame_num %d pre_frame_num %d max_frmae_num %d\r\n", + currSlice->frame_num, + p_Vid->pre_frame_num, + p_Vid->max_frame_num); + if (p_Vid->recovery_point == 0 && + currSlice->frame_num != p_Vid->pre_frame_num && + currSlice->frame_num != + (p_Vid->pre_frame_num + 1) % p_Vid->max_frame_num) { + /*if (active_sps-> + *gaps_in_frame_num_value_allowed_flag + *== 0) { + * error("An unintentional + * loss of pictures occurs! Exit\n", + * 100); + *} + *if (p_Vid->conceal_mode == 0) + */ + fill_frame_num_gap(p_Vid, currSlice); + } + + if (currSlice->nal_reference_idc) { + dpb_print(p_H264_Dpb->decoder_index, + PRINT_FLAG_DPB_DETAIL, + "nal_reference_idc not 0, set pre_frame_num(%d) to frame_num (%d)\n", + p_Vid->pre_frame_num, currSlice->frame_num); + p_Vid->pre_frame_num = currSlice->frame_num; + } + + decode_poc(&p_H264_Dpb->mVideo, &p_H264_Dpb->mSlice); + p_H264_Dpb->mVideo.dec_picture = get_new_pic(p_H264_Dpb, + p_H264_Dpb->mSlice.structure, + /*p_Vid->width, p_Vid->height, + * p_Vid->width_cr, + * p_Vid->height_cr, + */ + 1); + if (p_H264_Dpb->mVideo.dec_picture) { + struct DecodedPictureBuffer *p_Dpb = + &p_H264_Dpb->mDPB; + struct StorablePicture *p = + p_H264_Dpb->mVideo.dec_picture; + init_picture(p_H264_Dpb, &p_H264_Dpb->mSlice, + p_H264_Dpb->mVideo.dec_picture); +#if 1 + /* rain */ + p_H264_Dpb->mVideo.dec_picture->offset_delimiter_lo = + p_H264_Dpb->dpb_param.l.data[OFFSET_DELIMITER_LO]; + p_H264_Dpb->mVideo.dec_picture->offset_delimiter_hi = + p_H264_Dpb->dpb_param.l.data[OFFSET_DELIMITER_HI]; + + p_H264_Dpb->mVideo.dec_picture->buf_spec_num = -1; + p_H264_Dpb->mVideo.dec_picture-> + colocated_buf_index = -1; + update_pic_num(p_H264_Dpb); + + if ((currSlice->structure == TOP_FIELD) || + (currSlice->structure == BOTTOM_FIELD)) { + /* check for frame store with same + * pic_number + */ + check_frame_store_same_pic_num(p_Dpb, p, + currSlice); + } + + if (p_H264_Dpb->mVideo.dec_picture->buf_spec_num == + -1) { + p_H264_Dpb->mVideo.dec_picture->buf_spec_num = + get_free_buf_idx(p_H264_Dpb->vdec); + if (p_H264_Dpb->mVideo.dec_picture->buf_spec_num + < 0) { + p_H264_Dpb->buf_alloc_fail = 1; + p_H264_Dpb->mVideo.dec_picture-> + buf_spec_is_alloced = 0; + } else + p_H264_Dpb->mVideo.dec_picture-> + buf_spec_is_alloced = 1; + + if (p_H264_Dpb->mVideo.dec_picture-> + used_for_reference) { + p_H264_Dpb->mVideo.dec_picture-> + colocated_buf_index = + allocate_colocate_buf( + p_H264_Dpb); + } + } +#endif + } + } + + if (p_H264_Dpb->mSlice.slice_type == P_SLICE) + init_lists_p_slice(&p_H264_Dpb->mSlice); + else if (p_H264_Dpb->mSlice.slice_type == B_SLICE) + init_lists_b_slice(&p_H264_Dpb->mSlice); + else + init_lists_i_slice(&p_H264_Dpb->mSlice); + + reorder_lists(&p_H264_Dpb->mSlice); + + if (p_H264_Dpb->mSlice.structure == FRAME) + init_mbaff_lists(p_H264_Dpb, &p_H264_Dpb->mSlice); + + if (new_pic_flag) + return 1; + + return 0; +} + +enum PictureStructure get_cur_slice_picture_struct( + struct h264_dpb_stru *p_H264_Dpb) +{ + struct Slice *currSlice = &p_H264_Dpb->mSlice; + return currSlice->structure; +} + +static unsigned char is_pic_in_dpb(struct h264_dpb_stru *p_H264_Dpb, + struct StorablePicture *pic) +{ + unsigned char ret = 0; + int i; + struct DecodedPictureBuffer *p_Dpb = + &p_H264_Dpb->mDPB; + for (i = 0; i < p_Dpb->used_size; i++) { + if (p_Dpb->fs[i]->top_field == pic || + p_Dpb->fs[i]->bottom_field == pic || + p_Dpb->fs[i]->frame == pic) { + ret = 1; + break; + } + } + return ret; +} + +int dpb_check_ref_list_error( + struct h264_dpb_stru *p_H264_Dpb) +{ + int i; + /*int j;*/ + struct Slice *currSlice = &p_H264_Dpb->mSlice; + if ((currSlice->slice_type != I_SLICE) && + (currSlice->slice_type != SI_SLICE)) { + for (i = 0; i < currSlice->listXsize[0]; i++) { + /*for (j = i + 1; j < currSlice->listXsize[0]; j++) { + if(currSlice->listX[0][i]->pic_num == + currSlice->listX[0][j]->pic_num) + return 1; + }*/ + if (currSlice->listX[0][i] == NULL) + return 5; + if (!is_pic_in_dpb(p_H264_Dpb, + currSlice->listX[0][i])) + return 1; + if (currSlice->listX[0][i]->frame && + currSlice->listX[0][i]->frame->non_existing) + return 3; + } + } + + if (currSlice->slice_type == B_SLICE) { + for (i = 0; i < currSlice->listXsize[1]; i++) { + /*for (j = i + 1; j < currSlice->listXsize[1]; j++) { + if(currSlice->listX[1][i]->pic_num == + currSlice->listX[1][j]->pic_num) + return 2; + } + for (j = 0; j < currSlice->listXsize[0]; j++) { + if(currSlice->listX[1][i]->pic_num == + currSlice->listX[0][j]->pic_num) + return 3; + }*/ + if (currSlice->listX[1][i] == NULL) + return 6; + if (!is_pic_in_dpb(p_H264_Dpb, + currSlice->listX[1][i])) + return 2; + if (currSlice->listX[1][i]->frame && + currSlice->listX[1][i]->frame->non_existing) + return 4; +#if 0 + if (currSlice->listXsize[0] == 1 && + currSlice->listXsize[1] == 1 && + currSlice->listX[1][0] == + currSlice->listX[0][0]) + return 3; +#endif + } + } + return 0; +} + diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/h264_multi/h264_dpb.h b/drivers/amlogic/media_modules/frame_provider/decoder/h264_multi/h264_dpb.h new file mode 100644 index 000000000000..dc3824f451a5 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/h264_multi/h264_dpb.h @@ -0,0 +1,860 @@ +#ifndef H264_DPB_H_ +#define H264_DPB_H_ + +#define ERROR_CHECK + +#define OUTPUT_BUFFER_IN_C + +#define PRINT_FLAG_ERROR 0x0 +#define PRINT_FLAG_VDEC_STATUS 0X0001 +#define PRINT_FLAG_UCODE_EVT 0x0002 +#define PRINT_FLAG_MMU_DETAIL 0x0004 +#define PRINT_FLAG_ERRORFLAG_DBG 0x0008 +#define PRINT_FLAG_DPB_DETAIL 0x0010 +#define PRINT_FLAG_DEC_DETAIL 0x0020 +#define PRINT_FLAG_VDEC_DETAIL 0x0040 +#define PRINT_FLAG_DUMP_DPB 0x0080 +#define PRINT_FRAMEBASE_DATA 0x0100 +#define PRINT_FLAG_DEBUG_POC 0x0200 +#define RRINT_FLAG_RPM 0x0400 +#define DEBUG_DISABLE_RUNREADY_RMBUF 0x0800 +#define PRINT_FLAG_DUMP_BUFSPEC 0x1000 +#define DISABLE_ERROR_HANDLE 0x10000 +#define DEBUG_DUMP_STAT 0x80000 + + +#define MVC_EXTENSION_ENABLE 0 +#define PRINTREFLIST 0 + +#define MAX_LIST_SIZE 33 + +#define FALSE 0 + +#define H264_SLICE_HEAD_DONE 0x01 +#define H264_PIC_DATA_DONE 0x02 +/*#define H264_SPS_DONE 0x03*/ +/*#define H264_PPS_DONE 0x04*/ +/*#define H264_SLICE_DATA_DONE 0x05*/ +/*#define H264_DATA_END 0x06*/ + +#define H264_CONFIG_REQUEST 0x11 +#define H264_DATA_REQUEST 0x12 +#define H264_WRRSP_REQUEST 0x13 +#define H264_WRRSP_DONE 0x14 + +#define H264_DECODE_BUFEMPTY 0x20 +#define H264_DECODE_TIMEOUT 0x21 +#define H264_SEARCH_BUFEMPTY 0x22 +#define H264_DECODE_OVER_SIZE 0x23 + +#define H264_FIND_NEXT_PIC_NAL 0x50 +#define H264_FIND_NEXT_DVEL_NAL 0x51 +#define H264_AUX_DATA_READY 0x52 + + /* 0x8x, search state*/ +#define H264_STATE_SEARCH_AFTER_SPS 0x80 +#define H264_STATE_SEARCH_AFTER_PPS 0x81 +#define H264_STATE_PARSE_SLICE_HEAD 0x82 +#define H264_STATE_SEARCH_HEAD 0x83 + /**/ +#define H264_ACTION_SEARCH_HEAD 0xf0 +#define H264_ACTION_DECODE_SLICE 0xf1 +#define H264_ACTION_CONFIG_DONE 0xf2 +#define H264_ACTION_DECODE_NEWPIC 0xf3 +#define H264_ACTION_DECODE_START 0xff + +#define RPM_BEGIN 0x0 +#define RPM_END 0x400 + +#define val(s) (s[0]|(s[1]<<16)) + +#define FRAME_IN_DPB 24 +#define DPB_OFFSET 0x100 +#define MMCO_OFFSET 0x200 +union param { +#if 0 +#define H_TIME_STAMP_START 0X00 +#define H_TIME_STAMP_END 0X17 +#define PTS_ZERO_0 0X18 +#define PTS_ZERO_1 0X19 +#endif +#define FIXED_FRAME_RATE_FLAG 0X21 + +#define OFFSET_DELIMITER_LO 0x2f +#define OFFSET_DELIMITER_HI 0x30 + + +#define SLICE_IPONLY_BREAK 0X5C +#define PREV_MAX_REFERENCE_FRAME_NUM 0X5D +#define EOS 0X5E +#define FRAME_PACKING_TYPE 0X5F +#define OLD_POC_PAR_1 0X60 +#define OLD_POC_PAR_2 0X61 +#define PREV_MBX 0X62 +#define PREV_MBY 0X63 +#define ERROR_SKIP_MB_NUM 0X64 +#define ERROR_MB_STATUS 0X65 +#define L0_PIC0_STATUS 0X66 +#define TIMEOUT_COUNTER 0X67 +#define BUFFER_SIZE 0X68 +#define BUFFER_SIZE_HI 0X69 +#define CROPPING_LEFT_RIGHT 0X6A +#define CROPPING_TOP_BOTTOM 0X6B +#define POC_SELECT_NEED_SWAP 0X6C +#define POC_SELECT_SWAP 0X6D +#define MAX_BUFFER_FRAME 0X6E + +#define NON_CONFORMING_STREAM 0X70 +#define RECOVERY_POINT 0X71 +#define POST_CANVAS 0X72 +#define POST_CANVAS_H 0X73 +#define SKIP_PIC_COUNT 0X74 +#define TARGET_NUM_SCALING_LIST 0X75 +#define FF_POST_ONE_FRAME 0X76 +#define PREVIOUS_BIT_CNT 0X77 +#define MB_NOT_SHIFT_COUNT 0X78 +#define PIC_STATUS 0X79 +#define FRAME_COUNTER 0X7A +#define NEW_SLICE_TYPE 0X7B +#define NEW_PICTURE_STRUCTURE 0X7C +#define NEW_FRAME_NUM 0X7D +#define NEW_IDR_PIC_ID 0X7E +#define IDR_PIC_ID 0X7F + +/* h264 LOCAL */ +#define NAL_UNIT_TYPE 0X80 +#define NAL_REF_IDC 0X81 +#define SLICE_TYPE 0X82 +#define LOG2_MAX_FRAME_NUM 0X83 +#define FRAME_MBS_ONLY_FLAG 0X84 +#define PIC_ORDER_CNT_TYPE 0X85 +#define LOG2_MAX_PIC_ORDER_CNT_LSB 0X86 +#define PIC_ORDER_PRESENT_FLAG 0X87 +#define REDUNDANT_PIC_CNT_PRESENT_FLAG 0X88 +#define PIC_INIT_QP_MINUS26 0X89 +#define DEBLOCKING_FILTER_CONTROL_PRESENT_FLAG 0X8A +#define NUM_SLICE_GROUPS_MINUS1 0X8B +#define MODE_8X8_FLAGS 0X8C +#define ENTROPY_CODING_MODE_FLAG 0X8D +#define SLICE_QUANT 0X8E +#define TOTAL_MB_HEIGHT 0X8F +#define PICTURE_STRUCTURE 0X90 +#define TOP_INTRA_TYPE 0X91 +#define RV_AI_STATUS 0X92 +#define AI_READ_START 0X93 +#define AI_WRITE_START 0X94 +#define AI_CUR_BUFFER 0X95 +#define AI_DMA_BUFFER 0X96 +#define AI_READ_OFFSET 0X97 +#define AI_WRITE_OFFSET 0X98 +#define AI_WRITE_OFFSET_SAVE 0X99 +#define RV_AI_BUFF_START 0X9A +#define I_PIC_MB_COUNT 0X9B +#define AI_WR_DCAC_DMA_CTRL 0X9C +#define SLICE_MB_COUNT 0X9D +#define PICTYPE 0X9E +#define SLICE_GROUP_MAP_TYPE 0X9F +#define MB_TYPE 0XA0 +#define MB_AFF_ADDED_DMA 0XA1 +#define PREVIOUS_MB_TYPE 0XA2 +#define WEIGHTED_PRED_FLAG 0XA3 +#define WEIGHTED_BIPRED_IDC 0XA4 +/* bit 3:2 - PICTURE_STRUCTURE + * bit 1 - MB_ADAPTIVE_FRAME_FIELD_FLAG + * bit 0 - FRAME_MBS_ONLY_FLAG + */ +#define MBFF_INFO 0XA5 +#define TOP_INTRA_TYPE_TOP 0XA6 + +#define RV_AI_BUFF_INC 0xa7 + +#define DEFAULT_MB_INFO_LO 0xa8 + +/* 0 -- no need to read + * 1 -- need to wait Left + * 2 -- need to read Intra + * 3 -- need to read back MV + */ +#define NEED_READ_TOP_INFO 0xa9 +/* 0 -- idle + * 1 -- wait Left + * 2 -- reading top Intra + * 3 -- reading back MV + */ +#define READ_TOP_INFO_STATE 0xaa +#define DCAC_MBX 0xab +#define TOP_MB_INFO_OFFSET 0xac +#define TOP_MB_INFO_RD_IDX 0xad +#define TOP_MB_INFO_WR_IDX 0xae + +#define VLD_NO_WAIT 0 +#define VLD_WAIT_BUFFER 1 +#define VLD_WAIT_HOST 2 +#define VLD_WAIT_GAP 3 + +#define VLD_WAITING 0xaf + +#define MB_X_NUM 0xb0 +/* #define MB_WIDTH 0xb1 */ +#define MB_HEIGHT 0xb2 +#define MBX 0xb3 +#define TOTAL_MBY 0xb4 +#define INTR_MSK_SAVE 0xb5 + +/* #define has_time_stamp 0xb6 */ +#define NEED_DISABLE_PPE 0xb6 +#define IS_NEW_PICTURE 0XB7 +#define PREV_NAL_REF_IDC 0XB8 +#define PREV_NAL_UNIT_TYPE 0XB9 +#define FRAME_MB_COUNT 0XBA +#define SLICE_GROUP_UCODE 0XBB +#define SLICE_GROUP_CHANGE_RATE 0XBC +#define SLICE_GROUP_CHANGE_CYCLE_LEN 0XBD +#define DELAY_LENGTH 0XBE +#define PICTURE_STRUCT 0XBF +/* #define pre_picture_struct 0xc0 */ +#define DCAC_PREVIOUS_MB_TYPE 0xc1 + +#define TIME_STAMP 0XC2 +#define H_TIME_STAMP 0XC3 +#define VPTS_MAP_ADDR 0XC4 +#define H_VPTS_MAP_ADDR 0XC5 + +/*#define MAX_DPB_SIZE 0XC6*/ +#define PIC_INSERT_FLAG 0XC7 + +#define TIME_STAMP_START 0XC8 +#define TIME_STAMP_END 0XDF + +#define OFFSET_FOR_NON_REF_PIC 0XE0 +#define OFFSET_FOR_TOP_TO_BOTTOM_FIELD 0XE2 +#define MAX_REFERENCE_FRAME_NUM 0XE4 +#define FRAME_NUM_GAP_ALLOWED 0XE5 +#define NUM_REF_FRAMES_IN_PIC_ORDER_CNT_CYCLE 0XE6 +#define PROFILE_IDC_MMCO 0XE7 +#define LEVEL_IDC_MMCO 0XE8 +#define FRAME_SIZE_IN_MB 0XE9 +#define DELTA_PIC_ORDER_ALWAYS_ZERO_FLAG 0XEA +#define PPS_NUM_REF_IDX_L0_ACTIVE_MINUS1 0XEB +#define PPS_NUM_REF_IDX_L1_ACTIVE_MINUS1 0XEC +#define CURRENT_SPS_ID 0XED +#define CURRENT_PPS_ID 0XEE +/* bit 0 - sequence parameter set may change + * bit 1 - picture parameter set may change + * bit 2 - new dpb just inited + * bit 3 - IDR picture not decoded yet + * bit 5:4 - 0: mb level code loaded 1: picture + * level code loaded 2: slice level code loaded + */ +#define DECODE_STATUS 0XEF +#define FIRST_MB_IN_SLICE 0XF0 +#define PREV_MB_WIDTH 0XF1 +#define PREV_FRAME_SIZE_IN_MB 0XF2 +/*#define MAX_REFERENCE_FRAME_NUM_IN_MEM 0XF3*/ +/* bit 0 - aspect_ratio_info_present_flag + * bit 1 - timing_info_present_flag + * bit 2 - nal_hrd_parameters_present_flag + * bit 3 - vcl_hrd_parameters_present_flag + * bit 4 - pic_struct_present_flag + * bit 5 - bitstream_restriction_flag + */ +#define VUI_STATUS 0XF4 +#define ASPECT_RATIO_IDC 0XF5 +#define ASPECT_RATIO_SAR_WIDTH 0XF6 +#define ASPECT_RATIO_SAR_HEIGHT 0XF7 +#define NUM_UNITS_IN_TICK 0XF8 +#define TIME_SCALE 0XFA +#define CURRENT_PIC_INFO 0XFC +#define DPB_BUFFER_INFO 0XFD +#define REFERENCE_POOL_INFO 0XFE +#define REFERENCE_LIST_INFO 0XFF + struct{ + unsigned short data[RPM_END-RPM_BEGIN]; + } l; + struct{ + unsigned short dump[DPB_OFFSET]; + unsigned short dpb_base[FRAME_IN_DPB<<3]; + + unsigned short dpb_max_buffer_frame; + unsigned short actual_dpb_size; + + unsigned short colocated_buf_status; + + unsigned short num_forward_short_term_reference_pic; + unsigned short num_short_term_reference_pic; + unsigned short num_reference_pic; + + unsigned short current_dpb_index; + unsigned short current_decoded_frame_num; + unsigned short current_reference_frame_num; + + unsigned short l0_size; + unsigned short l1_size; + + /* [6:5] : nal_ref_idc */ + /* [4:0] : nal_unit_type */ + unsigned short NAL_info_mmco; + + /* [1:0] : 00 - top field, 01 - bottom field, + * 10 - frame, 11 - mbaff frame + */ + unsigned short picture_structure_mmco; + + unsigned short frame_num; + unsigned short pic_order_cnt_lsb; + + unsigned short num_ref_idx_l0_active_minus1; + unsigned short num_ref_idx_l1_active_minus1; + + unsigned short PrevPicOrderCntLsb; + unsigned short PreviousFrameNum; + + /* 32 bits variables */ + unsigned short delta_pic_order_cnt_bottom[2]; + unsigned short delta_pic_order_cnt_0[2]; + unsigned short delta_pic_order_cnt_1[2]; + + unsigned short PrevPicOrderCntMsb[2]; + unsigned short PrevFrameNumOffset[2]; + + unsigned short frame_pic_order_cnt[2]; + unsigned short top_field_pic_order_cnt[2]; + unsigned short bottom_field_pic_order_cnt[2]; + + unsigned short colocated_mv_addr_start[2]; + unsigned short colocated_mv_addr_end[2]; + unsigned short colocated_mv_wr_addr[2]; + } dpb; + struct { + unsigned short dump[MMCO_OFFSET]; + + /* array base address for offset_for_ref_frame */ + unsigned short offset_for_ref_frame_base[128]; + + /* 0 - Index in DPB + * 1 - Picture Flag + * [ 2] : 0 - short term reference, + * 1 - long term reference + * [ 1] : bottom field + * [ 0] : top field + * 2 - Picture Number (short term or long term) low 16 bits + * 3 - Picture Number (short term or long term) high 16 bits + */ + unsigned short reference_base[128]; + + /* command and parameter, until command is 3 */ + unsigned short l0_reorder_cmd[66]; + unsigned short l1_reorder_cmd[66]; + + /* command and parameter, until command is 0 */ + unsigned short mmco_cmd[44]; + + unsigned short l0_base[40]; + unsigned short l1_base[40]; + } mmco; + struct { + /* from ucode lmem, do not change this struct */ + } p; +}; + + +struct StorablePicture; +struct VideoParameters; +struct DecodedPictureBuffer; + +/* New enum for field processing */ +enum PictureStructure { + FRAME, + TOP_FIELD, + BOTTOM_FIELD +}; + +#define I_Slice 2 +#define P_Slice 5 +#define B_Slice 6 +#define P_Slice_0 0 +#define B_Slice_1 1 +#define I_Slice_7 7 + +enum SliceType { + P_SLICE = 0, + B_SLICE = 1, + I_SLICE = 2, + SP_SLICE = 3, + SI_SLICE = 4, + NUM_SLICE_TYPES = 5 +}; + +enum ProfileIDC { + FREXT_CAVLC444 = 44, /*!< YUV 4:4:4/14 "CAVLC 4:4:4"*/ + BASELINE = 66, /*!< YUV 4:2:0/8 "Baseline"*/ + MAIN = 77, /*!< YUV 4:2:0/8 "Main"*/ + EXTENDED = 88, /*!< YUV 4:2:0/8 "Extended"*/ + FREXT_HP = 100, /*!< YUV 4:2:0/8 "High"*/ + FREXT_Hi10P = 110, /*!< YUV 4:2:0/10 "High 10"*/ + FREXT_Hi422 = 122, /*!< YUV 4:2:2/10 "High 4:2:2"*/ + FREXT_Hi444 = 244, /*!< YUV 4:4:4/14 "High 4:4:4"*/ + MVC_HIGH = 118, /*!< YUV 4:2:0/8 "Multiview High"*/ + STEREO_HIGH = 128 /*!< YUV 4:2:0/8 "Stereo High"*/ +}; + +struct SPSParameters { + unsigned int profile_idc; + int pic_order_cnt_type; + int log2_max_pic_order_cnt_lsb_minus4; + int num_ref_frames_in_pic_order_cnt_cycle; + short offset_for_ref_frame[128]; + short offset_for_non_ref_pic; + short offset_for_top_to_bottom_field; + + /**/ + int frame_mbs_only_flag; + int num_ref_frames; + int max_dpb_size; + + int log2_max_frame_num_minus4; +}; + +#define DEC_REF_PIC_MARKING_BUFFER_NUM_MAX 45 +struct DecRefPicMarking_s { + int memory_management_control_operation; + int difference_of_pic_nums_minus1; + int long_term_pic_num; + int long_term_frame_idx; + int max_long_term_frame_idx_plus1; + struct DecRefPicMarking_s *Next; +}; + +#define REORDERING_COMMAND_MAX_SIZE 33 +struct Slice { + int first_mb_in_slice; + int mode_8x8_flags; + int picture_structure_mmco; + + int frame_num; + int idr_flag; + int toppoc; + int bottompoc; + int framepoc; + int pic_order_cnt_lsb; + int PicOrderCntMsb; + unsigned char field_pic_flag; + unsigned char bottom_field_flag; + int ThisPOC; + int nal_reference_idc; + int AbsFrameNum; + int delta_pic_order_cnt_bottom; + int delta_pic_order_cnt[2]; + + /**/ + char listXsize[6]; + struct StorablePicture *listX[6][MAX_LIST_SIZE * 2]; + + /**/ + enum PictureStructure structure; + int long_term_reference_flag; + int no_output_of_prior_pics_flag; + int adaptive_ref_pic_buffering_flag; + + struct VideoParameters *p_Vid; + struct DecodedPictureBuffer *p_Dpb; + int num_ref_idx_active[2]; /* number of available list references */ + + /*modification*/ + int slice_type; /* slice type */ + int ref_pic_list_reordering_flag[2]; + int modification_of_pic_nums_idc[2][REORDERING_COMMAND_MAX_SIZE]; + int abs_diff_pic_num_minus1[2][REORDERING_COMMAND_MAX_SIZE]; + int long_term_pic_idx[2][REORDERING_COMMAND_MAX_SIZE]; + /**/ + unsigned char dec_ref_pic_marking_buffer_valid; + struct DecRefPicMarking_s + dec_ref_pic_marking_buffer[DEC_REF_PIC_MARKING_BUFFER_NUM_MAX]; +}; + +struct OldSliceParams { + unsigned int field_pic_flag; + unsigned int frame_num; + int nal_ref_idc; + unsigned int pic_oder_cnt_lsb; + int delta_pic_oder_cnt_bottom; + int delta_pic_order_cnt[2]; + unsigned char bottom_field_flag; + unsigned char idr_flag; + int idr_pic_id; + int pps_id; +#if (MVC_EXTENSION_ENABLE) + int view_id; + int inter_view_flag; + int anchor_pic_flag; +#endif + int layer_id; +}; + +struct VideoParameters { + int PrevPicOrderCntMsb; + int PrevPicOrderCntLsb; + unsigned char last_has_mmco_5; + unsigned char last_pic_bottom_field; + int ThisPOC; + int PreviousFrameNum; + int FrameNumOffset; + int PreviousFrameNumOffset; + int max_frame_num; + unsigned int pre_frame_num; + int ExpectedDeltaPerPicOrderCntCycle; + int PicOrderCntCycleCnt; + int FrameNumInPicOrderCntCycle; + int ExpectedPicOrderCnt; + + /**/ + struct SPSParameters *active_sps; + struct Slice **ppSliceList; + int iSliceNumOfCurrPic; + int conceal_mode; + int earlier_missing_poc; + int pocs_in_dpb[100]; + + struct OldSliceParams old_slice; + /**/ + struct StorablePicture *dec_picture; + struct StorablePicture *no_reference_picture; + + /*modification*/ + int non_conforming_stream; + int recovery_point; +}; + +static inline int imin(int a, int b) +{ + return ((a) < (b)) ? (a) : (b); +} + +static inline int imax(int a, int b) +{ + return ((a) > (b)) ? (a) : (b); +} + +#define MAX_PIC_BUF_NUM 128 +#define MAX_NUM_SLICES 50 + +struct StorablePicture { +/**/ + int width; + int height; + + int y_canvas_index; + int u_canvas_index; + int v_canvas_index; +/**/ + int index; + unsigned char is_used; + + enum PictureStructure structure; + + int poc; + int top_poc; + int bottom_poc; + int frame_poc; + unsigned int frame_num; + unsigned int recovery_frame; + + int pic_num; + int buf_spec_num; + int buf_spec_is_alloced; + int colocated_buf_index; + int long_term_pic_num; + int long_term_frame_idx; + + unsigned char is_long_term; + int used_for_reference; + int is_output; +#if 1 + /* rain */ + int pre_output; +#endif + int non_existing; + int separate_colour_plane_flag; + + short max_slice_id; + + int size_x, size_y, size_x_cr, size_y_cr; + int size_x_m1, size_y_m1, size_x_cr_m1, size_y_cr_m1; + int coded_frame; + int mb_aff_frame_flag; + unsigned int PicWidthInMbs; + unsigned int PicSizeInMbs; + int iLumaPadY, iLumaPadX; + int iChromaPadY, iChromaPadX; + + /* for mb aff, if frame for referencing the top field */ + struct StorablePicture *top_field; + /* for mb aff, if frame for referencing the bottom field */ + struct StorablePicture *bottom_field; + /* for mb aff, if field for referencing the combined frame */ + struct StorablePicture *frame; + + int slice_type; + int idr_flag; + int no_output_of_prior_pics_flag; + int long_term_reference_flag; + int adaptive_ref_pic_buffering_flag; + + int chroma_format_idc; + int frame_mbs_only_flag; + int frame_cropping_flag; + int frame_crop_left_offset; + int frame_crop_right_offset; + int frame_crop_top_offset; + int frame_crop_bottom_offset; + int qp; + int chroma_qp_offset[2]; + int slice_qp_delta; + /* stores the memory management control operations */ + struct DecRefPicMarking_s *dec_ref_pic_marking_buffer; + + /* picture error concealment */ + /*indicates if this is a concealed picture */ + int concealed_pic; + + /* variables for tone mapping */ + int seiHasTone_mapping; + int tone_mapping_model_id; + int tonemapped_bit_depth; + /* imgpel* tone_mapping_lut; tone mapping look up table */ + + int proc_flag; +#if (MVC_EXTENSION_ENABLE) + int view_id; + int inter_view_flag; + int anchor_pic_flag; +#endif + int iLumaStride; + int iChromaStride; + int iLumaExpandedHeight; + int iChromaExpandedHeight; + /* imgpel **cur_imgY; for more efficient get_block_luma */ + int no_ref; + int iCodingType; + + char listXsize[MAX_NUM_SLICES][2]; + struct StorablePicture **listX[MAX_NUM_SLICES][2]; + int layer_id; + + int offset_delimiter_lo; + int offset_delimiter_hi; + + u32 pts; + u64 pts64; + unsigned char data_flag; +}; + +struct FrameStore { + /* rain */ + int buf_spec_num; + /* rain */ + int colocated_buf_index; + + /* 0=empty; 1=top; 2=bottom; 3=both fields (or frame) */ + int is_used; + /* 0=not used for ref; 1=top used; 2=bottom used; + * 3=both fields (or frame) used + */ + int is_reference; + /* 0=not used for ref; 1=top used; 2=bottom used; + * 3=both fields (or frame) used + */ + int is_long_term; + /* original marking by nal_ref_idc: 0=not used for ref; 1=top used; + * 2=bottom used; 3=both fields (or frame) used + */ + int is_orig_reference; + + int is_non_existent; + + unsigned int frame_num; + unsigned int recovery_frame; + + int frame_num_wrap; + int long_term_frame_idx; + int is_output; +#if 1 + /* rain */ + int pre_output; + /* index in gFrameStore */ + int index; +#define I_FLAG 0x01 +#define IDR_FLAG 0x02 +#define ERROR_FLAG 0x10 +#define NULL_FLAG 0x20 +#define MAYBE_ERROR_FLAG 0x40 +#define NODISP_FLAG 0x80 + unsigned char data_flag; +#endif + int poc; + + /* picture error concealment */ + int concealment_reference; + + struct StorablePicture *frame; + struct StorablePicture *top_field; + struct StorablePicture *bottom_field; + +#if (MVC_EXTENSION_ENABLE) + int view_id; + int inter_view_flag[2]; + int anchor_pic_flag[2]; +#endif + int layer_id; + + u32 pts; + u64 pts64; +}; + + +/* #define DPB_SIZE_MAX 16 */ +#define DPB_SIZE_MAX 32 +struct DecodedPictureBuffer { + struct VideoParameters *p_Vid; + /* InputParameters *p_Inp; ??? */ + struct FrameStore *fs[DPB_SIZE_MAX]; + struct FrameStore *fs_ref[DPB_SIZE_MAX]; + struct FrameStore *fs_ltref[DPB_SIZE_MAX]; + /* inter-layer reference (for multi-layered codecs) */ + struct FrameStore *fs_ilref[DPB_SIZE_MAX]; + /**/ + struct FrameStore *fs_list0[DPB_SIZE_MAX]; + struct FrameStore *fs_list1[DPB_SIZE_MAX]; + struct FrameStore *fs_listlt[DPB_SIZE_MAX]; + + /**/ + unsigned int size; + unsigned int used_size; + unsigned int ref_frames_in_buffer; + unsigned int ltref_frames_in_buffer; + int last_output_poc; +#if (MVC_EXTENSION_ENABLE) + int last_output_view_id; +#endif + int max_long_term_pic_idx; + + + int init_done; + int first_pic_done; /*by rain*/ + int num_ref_frames; + + struct FrameStore *last_picture; + unsigned int used_size_il; + int layer_id; + + /* DPB related function; */ +}; + +struct h264_dpb_stru { + struct vdec_s *vdec; + int decoder_index; + + union param dpb_param; + + int decode_idx; + int buf_num; + int curr_POC; + int reorder_pic_num; + u8 fast_output_enable; + /*poc_even_flag: + 0, init; 1, odd; 2, even*/ + u8 poc_even_odd_flag; + u32 decode_pic_count; + /**/ + unsigned int max_reference_size; + + unsigned int colocated_buf_map; + unsigned int colocated_buf_count; + unsigned int colocated_mv_addr_start; + unsigned int colocated_mv_addr_end; + unsigned int colocated_buf_size; + + struct DecodedPictureBuffer mDPB; + struct Slice mSlice; + struct VideoParameters mVideo; + struct SPSParameters mSPS; + + struct StorablePicture m_PIC[MAX_PIC_BUF_NUM]; + struct FrameStore mFrameStore[DPB_SIZE_MAX]; + + /*vui*/ + unsigned int vui_status; + unsigned int num_units_in_tick; + unsigned int time_scale; + unsigned int fixed_frame_rate_flag; + unsigned int aspect_ratio_idc; + unsigned int aspect_ratio_sar_width; + unsigned int aspect_ratio_sar_height; + + unsigned int dec_dpb_status; + unsigned char buf_alloc_fail; + unsigned int dpb_error_flag; +}; + + +extern unsigned int h264_debug_flag; +extern unsigned int h264_debug_mask; + +int dpb_print(int indext, int debug_flag, const char *fmt, ...); + +int dpb_print_cont(int index, int debug_flag, const char *fmt, ...); + +unsigned char dpb_is_debug(int index, int debug_flag); + +int prepare_display_buf(struct vdec_s *vdec, struct FrameStore *frame); + +int release_buf_spec_num(struct vdec_s *vdec, int buf_spec_num); + +void set_frame_output_flag(struct h264_dpb_stru *p_H264_Dpb, int index); + +int is_there_unused_frame_from_dpb(struct DecodedPictureBuffer *p_Dpb); + +int h264_slice_header_process(struct h264_dpb_stru *p_H264_Dpb); + +void dpb_init_global(struct h264_dpb_stru *p_H264_Dpb, + int id, int actual_dpb_size, int max_reference_size); + +void init_colocate_buf(struct h264_dpb_stru *p_H264_Dpb, int count); + +int release_colocate_buf(struct h264_dpb_stru *p_H264_Dpb, int index); + +int get_free_buf_idx(struct vdec_s *vdec); + +int store_picture_in_dpb(struct h264_dpb_stru *p_H264_Dpb, + struct StorablePicture *p, unsigned char data_flag); + +int release_picture(struct h264_dpb_stru *p_H264_Dpb, + struct StorablePicture *pic); + +void remove_dpb_pictures(struct h264_dpb_stru *p_H264_Dpb); + +void bufmgr_post(struct h264_dpb_stru *p_H264_Dpb); + +void bufmgr_force_recover(struct h264_dpb_stru *p_H264_Dpb); + +int get_long_term_flag_by_buf_spec_num(struct h264_dpb_stru *p_H264_Dpb, + int buf_spec_num); + +void bufmgr_h264_remove_unused_frame(struct h264_dpb_stru *p_H264_Dpb, + u8 force_flag); + +void flush_dpb(struct h264_dpb_stru *p_H264_Dpb); + +void print_pic_info(int decindex, const char *info, + struct StorablePicture *pic, + int slice_type); +void dump_dpb(struct DecodedPictureBuffer *p_Dpb, u8 force); + +void dump_pic(struct h264_dpb_stru *p_H264_Dpb); + +enum PictureStructure get_cur_slice_picture_struct( + struct h264_dpb_stru *p_H264_Dpb); + +int dpb_check_ref_list_error( + struct h264_dpb_stru *p_H264_Dpb); +#endif diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/h264_multi/vmh264.c b/drivers/amlogic/media_modules/frame_provider/decoder/h264_multi/vmh264.c new file mode 100644 index 000000000000..690c04c3ba35 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/h264_multi/vmh264.c @@ -0,0 +1,7315 @@ +/* + * drivers/amlogic/amports/vh264.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#define DEBUG +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../../stream_input/amports/amports_priv.h" +#include + +#include "../utils/vdec_input.h" +#include + +#include +#include "../utils/vdec.h" +#include "../utils/amvdec.h" +#include "../h264/vh264.h" +#include "../../../stream_input/parser/streambuf.h" +#include +#include +#include "../utils/decoder_mmu_box.h" +#include "../utils/decoder_bmmu_box.h" +#include "../utils/firmware.h" +#include +#include +#include "../utils/config_parser.h" + +#undef pr_info +#define pr_info printk + +#define DEBUG_UCODE +#define MEM_NAME "codec_m264" +#define MULTI_INSTANCE_FRAMEWORK +/* #define ONE_COLOCATE_BUF_PER_DECODE_BUF */ +#include "h264_dpb.h" +/* #define SEND_PARAM_WITH_REG */ + +#define DRIVER_NAME "ammvdec_h264" +#define MODULE_NAME "ammvdec_h264" +#define DRIVER_HEADER_NAME "ammvdec_h264_header" + +#define CHECK_INTERVAL (HZ/100) + +#define SEI_ITU_DATA_SIZE (4*1024) + +#define RATE_MEASURE_NUM 8 +#define RATE_CORRECTION_THRESHOLD 5 +#define RATE_2397_FPS 4004 /* 23.97 */ +#define RATE_25_FPS 3840 /* 25 */ +#define RATE_2997_FPS 3203 /* 29.97 */ +#define DUR2PTS(x) ((x)*90/96) +#define PTS2DUR(x) ((x)*96/90) +#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96) +#define FIX_FRAME_RATE_CHECK_IFRAME_NUM 2 + +#define FIX_FRAME_RATE_OFF 0 +#define FIX_FRAME_RATE_ON 1 +#define FIX_FRAME_RATE_SMOOTH_CHECKING 2 + +#define DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE 0x0001 +#define DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE 0x0002 +#define DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE 0x0010 +#define DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE 0x0020 + +#define DECODE_ID(hw) (hw_to_vdec(hw)->id) + +#define RATE_MEASURE_NUM 8 +#define RATE_CORRECTION_THRESHOLD 5 +#define RATE_24_FPS 4004 /* 23.97 */ +#define RATE_25_FPS 3840 /* 25 */ +#define DUR2PTS(x) ((x)*90/96) +#define PTS2DUR(x) ((x)*96/90) +#define DUR2PTS_REM(x) (x*90 - DUR2PTS(x)*96) +#define FIX_FRAME_RATE_CHECK_IDRFRAME_NUM 2 + +#define H264_DEV_NUM 9 + +#define H264_MMU +static int mmu_enable; +static int force_enable_mmu = 1; +unsigned int h264_debug_flag; /* 0xa0000000; */ +unsigned int h264_debug_mask = 0xff; + /* + *h264_debug_cmd: + * 0x1xx, force decoder id of xx to be disconnected + */ +unsigned int h264_debug_cmd; +static unsigned int dec_control; +static unsigned int force_rate_streambase; +static unsigned int force_rate_framebase; +static unsigned int force_disp_bufspec_num; +static unsigned int fixed_frame_rate_mode; +static unsigned int error_recovery_mode_in; +static int start_decode_buf_level = 0x8000; +static int pre_decode_buf_level = 0x1000; +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION +/*to make reorder size difference of bl and el not too big*/ +static unsigned int reorder_dpb_size_margin_dv = 16; +#endif +static unsigned int reorder_dpb_size_margin = 6; +static unsigned int reference_buf_margin = 4; + +static unsigned int max_alloc_buf_count; +static unsigned int decode_timeout_val = 100; +static unsigned int errordata_timeout_val = 50; +static unsigned int get_data_timeout_val = 2000; +#if 1 +/* H264_DATA_REQUEST does not work, disable it, +decode has error for data in none continuous address +*/ +static unsigned int frame_max_data_packet; +#else +static unsigned int frame_max_data_packet = 8; +#endif +static unsigned int radr; +static unsigned int rval; +static u32 endian = 0xff0; + +/* + udebug_flag: + bit 0, enable ucode print + bit 1, enable ucode detail print + bit 3, disable ucode watchdog + bit [31:16] not 0, pos to dump lmem + bit 2, pop bits to lmem + bit [11:8], pre-pop bits for alignment (when bit 2 is 1) +*/ +static u32 udebug_flag; +/* + when udebug_flag[1:0] is not 0 + udebug_pause_pos not 0, + pause position +*/ +static u32 udebug_pause_pos; +/* + when udebug_flag[1:0] is not 0 + and udebug_pause_pos is not 0, + pause only when DEBUG_REG2 is equal to this val +*/ +static u32 udebug_pause_val; + +static u32 udebug_pause_decode_idx; + +static unsigned int disp_vframe_valve_level; + +static unsigned int max_decode_instance_num = H264_DEV_NUM; +static unsigned int decode_frame_count[H264_DEV_NUM]; +static unsigned int display_frame_count[H264_DEV_NUM]; +static unsigned int max_process_time[H264_DEV_NUM]; +static unsigned int max_get_frame_interval[H264_DEV_NUM]; +static unsigned int run_count[H264_DEV_NUM]; +static unsigned int input_empty[H264_DEV_NUM]; +static unsigned int not_run_ready[H264_DEV_NUM]; + /* bit[3:0]: + *0, run ; 1, pause; 3, step + *bit[4]: + *1, schedule run + */ +static unsigned int step[H264_DEV_NUM]; + +#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf)) +static u32 prefix_aux_buf_size = (16 * 1024); +static u32 suffix_aux_buf_size; + +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION +static u32 dv_toggle_prov_name; + +static u32 dolby_meta_with_el; +#endif + +/* + bit[8] + 0: use sys_info[bit 3] + not 0:use i_only_flag[7:0] + bit[7:0]: + bit 0, 1: only display I picture; + bit 1, 1: only decode I picture; +*/ +static unsigned int i_only_flag; + +/* + error_proc_policy: + bit[0] send_error_frame_flag; + (valid when bit[31] is 1, otherwise use sysinfo) + bit[1] do not decode if config_decode_buf() fail + bit[2] force release buf if in deadlock + bit[3] force sliding window ref_frames_in_buffer > num_ref_frames + bit[4] check inactive of receiver + bit[5] reset buffmgr if in deadlock + bit[6] reset buffmgr if bufspec, collocate buf, pic alloc fail + bit[7] reset buffmgr if dpb error + + bit[8] check total mbx/mby of decoded frame + bit[9] check ERROR_STATUS_REG + bit[10] check reference list + bit[11] mark error if dpb error + + bit[12] i_only when error happen +*/ +static unsigned int error_proc_policy = 0x1f36; /*0x1f14*/ + +/* + error_skip_count: + bit[11:0] error skip frame count + bit[15:12] error skip i picture count +*/ +static unsigned int error_skip_count = (0x2 << 12) | 0x40; + +static unsigned int force_sliding_margin; +/* + bit[1:0]: + 0, start playing from any frame + 1, start playing from I frame + bit[15:8]: the count of skip frames after first I + 2, start playing from second I frame (decode from the first I) + bit[15:8]: the max count of skip frames after first I + 3, start playing from IDR +*/ +static unsigned int first_i_policy = (15 << 8) | 2; + +/* + fast_output_enable: + bit [0], output frame if there is IDR in list + bit [1], output frame if the current poc is 1 big than the previous poc + bit [2], if even poc only, output frame ifthe cuurent poc + is 2 big than the previous poc +*/ +static unsigned int fast_output_enable = 4; + +static unsigned int enable_itu_t35 = 1; + +//static unsigned int frmbase_cont_bitlevel = 0x40;//DEBUG_TMP +static unsigned int frmbase_cont_bitlevel; + +static unsigned int frmbase_cont_bitlevel2 = 0x1; + + +#define MH264_USERDATA_ENABLE + +/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */ +/* hevc->double_write_mode: + 0, no double write + 1, 1:1 ratio + 2, (1/4):(1/4) ratio + 3, (1/4):(1/4) ratio, with both compressed frame included + 4, (1/2):(1/2) ratio + 0x10, double write only +*/ +static u32 double_write_mode; + +static void vmh264_dump_state(struct vdec_s *vdec); + +#define is_in_parsing_state(status) \ + ((status == H264_ACTION_SEARCH_HEAD) || \ + ((status & 0xf0) == 0x80)) + +#define is_interlace(frame) \ + (frame->frame &&\ + frame->top_field &&\ + frame->bottom_field &&\ + (!frame->frame->coded_frame)) +static inline bool close_to(int a, int b, int m) +{ + return (abs(a - b) < m) ? true : false; +} + +#if 0 +#define h264_alloc_hw_stru(dev, size, opt) devm_kzalloc(dev, size, opt) +#define h264_free_hw_stru(dev, hw) devm_kfree(dev, hw) +#else +#define h264_alloc_hw_stru(dev, size, opt) vzalloc(size) +#define h264_free_hw_stru(dev, hw) vfree(hw) +#endif + +/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ +#define NV21 +/* #endif */ + +/* 12M for L41 */ +#define MAX_DPB_BUFF_SIZE (12*1024*1024) +#define DEFAULT_MEM_SIZE (32*1024*1024) +#define AVIL_DPB_BUFF_SIZE 0x01ec2000 + +#define DEF_BUF_START_ADDR 0x01000000 +#define mem_sps_base 0x011c3c00 +#define mem_pps_base 0x011cbc00 +/*#define V_BUF_ADDR_OFFSET (0x13e000)*/ +u32 V_BUF_ADDR_OFFSET = 0x200000; +#define DCAC_READ_MARGIN (64 * 1024) +#define PIC_SINGLE_FRAME 0 +#define PIC_TOP_BOT_TOP 1 +#define PIC_BOT_TOP_BOT 2 +#define PIC_DOUBLE_FRAME 3 +#define PIC_TRIPLE_FRAME 4 +#define PIC_TOP_BOT 5 +#define PIC_BOT_TOP 6 +#define PIC_INVALID 7 + +#define EXTEND_SAR 0xff + +#define BUFSPEC_POOL_SIZE 64 +#define VF_POOL_SIZE 64 +#define VF_POOL_NUM 2 +#define MAX_VF_BUF_NUM 27 +#define BMMU_MAX_BUFFERS (BUFSPEC_POOL_SIZE + 3) +#define BMMU_REF_IDX (BUFSPEC_POOL_SIZE) +#define BMMU_DPB_IDX (BUFSPEC_POOL_SIZE + 1) +#define BMMU_EXTIF_IDX (BUFSPEC_POOL_SIZE + 2) +#define EXTIF_BUF_SIZE 0x10000 + +#define HEADER_BUFFER_IDX(n) (n) +#define VF_BUFFER_IDX(n) (n) + + +#define PUT_INTERVAL (HZ/100) +#define NO_DISP_WD_COUNT (3 * HZ / PUT_INTERVAL) + +#define MMU_MAX_BUFFERS BUFSPEC_POOL_SIZE +#define SWITCHING_STATE_OFF 0 +#define SWITCHING_STATE_ON_CMD3 1 +#define SWITCHING_STATE_ON_CMD1 2 + + + +#define INCPTR(p) ptr_atomic_wrap_inc(&p) + +#define SLICE_TYPE_I 2 +#define SLICE_TYPE_P 5 +#define SLICE_TYPE_B 6 + +struct buffer_spec_s { + /* + used: + -1, none allocated + 0, allocated, free + 1, used by dpb + 2, in disp queue; + 3, in disp queue, isolated, + do not use for dpb when vf_put; + 4, to release + 5, in disp queue, isolated (but not to release) + do not use for dpb when vf_put; + */ + unsigned int used; + unsigned int info0; + unsigned int info1; + unsigned int info2; + unsigned int y_addr; + unsigned int u_addr; + unsigned int v_addr; + + int y_canvas_index; + int u_canvas_index; + int v_canvas_index; + +#ifdef NV21 + struct canvas_config_s canvas_config[2]; +#else + struct canvas_config_s canvas_config[3]; +#endif + unsigned long cma_alloc_addr; + unsigned int buf_adr; +#ifdef H264_MMU + unsigned long alloc_header_addr; +#endif + char *aux_data_buf; + int aux_data_size; +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + unsigned char dv_enhance_exist; +#endif + int canvas_pos; + int vf_ref; + /*unsigned int comp_body_size;*/ + unsigned int dw_y_adr; + unsigned int dw_u_v_adr; +}; + +#define AUX_DATA_SIZE(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_size) +#define AUX_DATA_BUF(pic) (hw->buffer_spec[pic->buf_spec_num].aux_data_buf) +#define DEL_EXIST(h, p) (h->buffer_spec[p->buf_spec_num].dv_enhance_exist) + +#define spec2canvas(x) \ + (((x)->v_canvas_index << 16) | \ + ((x)->u_canvas_index << 8) | \ + ((x)->y_canvas_index << 0)) + +#define FRAME_INDEX(vf_index) (vf_index & 0xff) +#define BUFSPEC_INDEX(vf_index) ((vf_index >> 8) & 0xff) +#define VF_INDEX(frm_idx, bufspec_idx) (frm_idx | (bufspec_idx << 8)) + +static struct vframe_s *vh264_vf_peek(void *); +static struct vframe_s *vh264_vf_get(void *); +static void vh264_vf_put(struct vframe_s *, void *); +static int vh264_vf_states(struct vframe_states *states, void *); +static int vh264_event_cb(int type, void *data, void *private_data); +static void vh264_work(struct work_struct *work); +static void vh264_notify_work(struct work_struct *work); +static void user_data_push_work(struct work_struct *work); +#ifdef MH264_USERDATA_ENABLE +static void user_data_ready_notify_work(struct work_struct *work); +#endif + +static const char vh264_dec_id[] = "vh264-dev"; + +#define PROVIDER_NAME "vdec.h264" + +static const struct vframe_operations_s vf_provider_ops = { + .peek = vh264_vf_peek, + .get = vh264_vf_get, + .put = vh264_vf_put, + .event_cb = vh264_event_cb, + .vf_states = vh264_vf_states, +}; + +#define DEC_RESULT_NONE 0 +#define DEC_RESULT_DONE 1 +#define DEC_RESULT_AGAIN 2 +#define DEC_RESULT_CONFIG_PARAM 3 +#define DEC_RESULT_GET_DATA 4 +#define DEC_RESULT_GET_DATA_RETRY 5 +#define DEC_RESULT_ERROR 6 +#define DEC_RESULT_EOS 7 +#define DEC_RESULT_FORCE_EXIT 8 + +/* + *static const char *dec_result_str[] = { + * "DEC_RESULT_NONE ", + * "DEC_RESULT_DONE ", + * "DEC_RESULT_AGAIN ", + * "DEC_RESULT_CONFIG_PARAM", + * "DEC_RESULT_GET_DATA ", + * "DEC_RESULT_GET_DA_RETRY", + * "DEC_RESULT_ERROR ", + *}; + */ + +#define UCODE_IP_ONLY 2 +#define UCODE_IP_ONLY_PARAM 1 + +#define MC_OFFSET_HEADER 0x0000 +#define MC_OFFSET_DATA 0x1000 +#define MC_OFFSET_MMCO 0x2000 +#define MC_OFFSET_LIST 0x3000 +#define MC_OFFSET_SLICE 0x4000 +#define MC_OFFSET_MAIN 0x5000 + +#define MC_TOTAL_SIZE ((20+16)*SZ_1K) +#define MC_SWAP_SIZE (4*SZ_1K) +#define MODE_ERROR 0 +#define MODE_FULL 1 + +#define DFS_HIGH_THEASHOLD 3 + +#define INIT_FLAG_REG AV_SCRATCH_2 +#define HEAD_PADING_REG AV_SCRATCH_3 +#define UCODE_WATCHDOG_REG AV_SCRATCH_7 +#define LMEM_DUMP_ADR AV_SCRATCH_L +#define DEBUG_REG1 AV_SCRATCH_M +#define DEBUG_REG2 AV_SCRATCH_N +#define FRAME_COUNTER_REG AV_SCRATCH_I +#define RPM_CMD_REG AV_SCRATCH_A +#define H264_DECODE_SIZE AV_SCRATCH_E +#define H264_DECODE_MODE AV_SCRATCH_4 +#define H264_DECODE_SEQINFO AV_SCRATCH_5 +#define H264_AUX_ADR AV_SCRATCH_C +#define H264_AUX_DATA_SIZE AV_SCRATCH_H + +#define H264_DECODE_INFO M4_CONTROL_REG /* 0xc29 */ +#define DPB_STATUS_REG AV_SCRATCH_J +#define ERROR_STATUS_REG AV_SCRATCH_9 + /* + NAL_SEARCH_CTL: bit 0, enable itu_t35 + NAL_SEARCH_CTL: bit 1, enable mmu + */ +#define NAL_SEARCH_CTL AV_SCRATCH_9 +#define MBY_MBX MB_MOTION_MODE /*0xc07*/ + +#define DECODE_MODE_SINGLE 0x0 +#define DECODE_MODE_MULTI_FRAMEBASE 0x1 +#define DECODE_MODE_MULTI_STREAMBASE 0x2 +#define DECODE_MODE_MULTI_DVBAL 0x3 +#define DECODE_MODE_MULTI_DVENL 0x4 +static DEFINE_MUTEX(vmh264_mutex); + + + +#ifdef MH264_USERDATA_ENABLE + +struct mh264_userdata_record_t { + struct userdata_meta_info_t meta_info; + u32 rec_start; + u32 rec_len; +}; + +struct mh264_ud_record_wait_node_t { + struct list_head list; + struct mh264_userdata_record_t ud_record; +}; +#define USERDATA_FIFO_NUM 256 +#define MAX_FREE_USERDATA_NODES 5 + +struct mh264_userdata_info_t { + struct mh264_userdata_record_t records[USERDATA_FIFO_NUM]; + u8 *data_buf; + u8 *data_buf_end; + u32 buf_len; + u32 read_index; + u32 write_index; + u32 last_wp; +}; + + +#endif + +struct vdec_h264_hw_s { + spinlock_t lock; + spinlock_t bufspec_lock; + int id; + struct platform_device *platform_dev; + unsigned long cma_alloc_addr; + /* struct page *collocate_cma_alloc_pages; */ + unsigned long collocate_cma_alloc_addr; + + u32 prefix_aux_size; + u32 suffix_aux_size; + void *aux_addr; + dma_addr_t aux_phy_addr; + /* buffer for storing one itu35 recored */ + void *sei_itu_data_buf; + u32 sei_itu_data_len; + + /* recycle buffer for user data storing all itu35 records */ + void *sei_user_data_buffer; + u32 sei_user_data_wp; + int sei_poc; + struct work_struct user_data_work; +#ifdef MH264_USERDATA_ENABLE + struct work_struct user_data_ready_work; +#endif + struct StorablePicture *last_dec_picture; + + ulong lmem_addr; + dma_addr_t lmem_addr_remap; + + void *bmmu_box; +#ifdef H264_MMU + void *mmu_box; + void *frame_mmu_map_addr; + dma_addr_t frame_mmu_map_phy_addr; + u32 hevc_cur_buf_idx; + u32 losless_comp_body_size; + u32 losless_comp_body_size_sao; + u32 losless_comp_header_size; + u32 mc_buffer_size_u_v; + u32 mc_buffer_size_u_v_h; + u32 is_idr_frame; + u32 is_new_pic; + u32 frame_done; + u32 frame_busy; + unsigned long extif_addr; + int double_write_mode; + int mmu_enable; +#endif + + DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE); + DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE); + + int cur_pool; + struct vframe_s vfpool[VF_POOL_NUM][VF_POOL_SIZE]; + struct buffer_spec_s buffer_spec[BUFSPEC_POOL_SIZE]; + struct vframe_s switching_fense_vf; + struct h264_dpb_stru dpb; + u8 init_flag; + u8 has_i_frame; + u8 config_bufmgr_done; + u32 max_reference_size; + u32 decode_pic_count; + int start_search_pos; + u32 reg_iqidct_control; + u32 reg_vcop_ctrl_reg; + u32 reg_rv_ai_mb_count; + u32 vld_dec_control; + struct vframe_s vframe_dummy; + + unsigned char buffer_empty_flag; + + u32 frame_width; + u32 frame_height; + u32 frame_dur; + u32 frame_prog; + u32 frame_packing_type; + + struct vframe_chunk_s *chunk; + + u32 stat; + unsigned long buf_start; + u32 buf_offset; + u32 buf_size; + /* u32 ucode_map_start; */ + u32 pts_outside; + u32 sync_outside; + u32 vh264_ratio; + u32 vh264_rotation; + u32 use_idr_framerate; + + u32 seq_info; + u32 seq_info2; + u32 video_signal_from_vui; /*to do .. */ + u32 timing_info_present_flag; + u32 fixed_frame_rate_flag; + u32 iframe_count; + u32 aspect_ratio_info; + u32 num_units_in_tick; + u32 time_scale; + u32 h264_ar; + bool h264_first_valid_pts_ready; + u32 h264pts1; + u32 h264pts2; + u32 pts_duration; + u32 h264_pts_count; + u32 duration_from_pts_done; + u32 pts_unstable; + u32 last_checkout_pts; + u32 max_refer_buf; + + s32 vh264_stream_switching_state; + struct vframe_s *p_last_vf; + u32 last_pts; + u32 last_pts_remainder; + u32 last_duration; + u32 last_mb_width, last_mb_height; + bool check_pts_discontinue; + bool pts_discontinue; + u32 wait_buffer_counter; + u32 first_offset; + u32 first_pts; + u64 first_pts64; + bool first_pts_cached; + +#if 0 + void *sei_data_buffer; + dma_addr_t sei_data_buffer_phys; +#endif + + uint error_recovery_mode; + uint mb_total; + uint mb_width; + uint mb_height; + + uint i_only; + int skip_frame_count; + bool no_poc_reorder_flag; + bool send_error_frame_flag; + dma_addr_t mc_dma_handle; + void *mc_cpu_addr; + int vh264_reset; + + atomic_t vh264_active; + + struct dec_sysinfo vh264_amstream_dec_info; + + int dec_result; + struct work_struct work; + struct work_struct notify_work; + + void (*vdec_cb)(struct vdec_s *, void *); + void *vdec_cb_arg; + + struct timer_list check_timer; + + /**/ + unsigned int last_frame_time; + u32 vf_pre_count; + u32 vf_get_count; + u32 vf_put_count; + + /* timeout handle */ + unsigned long int start_process_time; + unsigned int last_mby_mbx; + unsigned int last_vld_level; + unsigned int decode_timeout_count; + unsigned int timeout_num; + unsigned int search_dataempty_num; + unsigned int decode_timeout_num; + unsigned int decode_dataempty_num; + unsigned int buffer_empty_recover_num; + + unsigned get_data_count; + unsigned get_data_start_time; + /**/ + + /*log*/ + unsigned int packet_write_success_count; + unsigned int packet_write_EAGAIN_count; + unsigned int packet_write_ENOMEM_count; + unsigned int packet_write_EFAULT_count; + unsigned int total_read_size_pre; + unsigned int total_read_size; + unsigned int frame_count_pre; +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + u8 switch_dvlayer_flag; + u8 got_valid_nal; +#endif + u8 eos; + u8 data_flag; + u32 no_error_count; + u32 no_error_i_count; + /* + NODISP_FLAG + */ + u8 dec_flag; + + u32 ucode_pause_pos; + + u8 reset_bufmgr_flag; + u32 reset_bufmgr_count; + u32 cfg_param1; + u32 cfg_param2; + u32 cfg_param3; + u32 cfg_param4; + int valve_count; + u8 next_again_flag; + u32 pre_parser_wr_ptr; + struct firmware_s *fw; + struct firmware_s *fw_mmu; +#ifdef MH264_USERDATA_ENABLE + /*user data*/ + struct mutex userdata_mutex; + struct mh264_userdata_info_t userdata_info; + struct list_head frame_uds; /*user data records list waiting for vpts*/ + struct list_head free_uds_wait_nodes; /*free user data records list*/ + struct mh264_ud_record_wait_node_t free_nodes[MAX_FREE_USERDATA_NODES]; + int wait_for_udr_send; +#endif +}; + +static u32 again_threshold = 0x40; + +static void dump_bufspec(struct vdec_h264_hw_s *hw, + const char *caller); +static void h264_reconfig(struct vdec_h264_hw_s *hw); +static void h264_reset_bufmgr(struct vdec_s *vdec); +static void vh264_local_init(struct vdec_h264_hw_s *hw); +static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw); +static int vh264_stop(struct vdec_h264_hw_s *hw); +static s32 vh264_init(struct vdec_h264_hw_s *hw); +static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf, + u32 index); +static void release_aux_data(struct vdec_h264_hw_s *hw, + int buf_spec_num); +#ifdef ERROR_HANDLE_TEST +static void h264_clear_dpb(struct vdec_h264_hw_s *hw); +#endif + +#define H265_PUT_SAO_4K_SET 0x03 +#define H265_ABORT_SAO_4K_SET 0x04 +#define H265_ABORT_SAO_4K_SET_DONE 0x05 + +#define SYS_COMMAND HEVC_ASSIST_SCRATCH_0 +#define H265_CHECK_AXI_INFO_BASE HEVC_ASSIST_SCRATCH_8 +#define H265_SAO_4K_SET_BASE HEVC_ASSIST_SCRATCH_9 +#define H265_SAO_4K_SET_COUNT HEVC_ASSIST_SCRATCH_A +#define HEVC_SAO_MMU_STATUS 0x3639 +#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464 + +#define HEVC_CM_HEADER_START_ADDR 0x3628 +#define HEVC_CM_BODY_START_ADDR 0x3626 +#define HEVC_CM_BODY_LENGTH 0x3627 +#define HEVC_CM_HEADER_LENGTH 0x3629 +#define HEVC_CM_HEADER_OFFSET 0x362b +#define HEVC_SAO_CTRL9 0x362d +#define HEVCD_MPP_DECOMP_CTL3 0x34c4 +#define HEVCD_MPP_VDEC_MCR_CTL 0x34c8 + + +#define H265_DW_NO_SCALE +#define H265_MEM_MAP_MODE 0 /*0:linear 1:32x32 2:64x32*/ +#define H265_LOSLESS_COMPRESS_MODE +#define MAX_FRAME_4K_NUM 0x1200 +#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4) + + +/* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */ +static u32 mem_map_mode = H265_MEM_MAP_MODE; + +static int compute_losless_comp_body_size(int width, + int height, int bit_depth_10); +static int compute_losless_comp_header_size(int width, int height); + + + +static int hevc_alloc_mmu(struct vdec_h264_hw_s *hw, int pic_idx, + int pic_width, int pic_height, u16 bit_depth, + unsigned int *mmu_index_adr) { + int cur_buf_idx; + int bit_depth_10 = (bit_depth != 0x00); + int picture_size; + u32 cur_mmu_4k_number; + + WRITE_VREG(CURR_CANVAS_CTRL, pic_idx<<24); + cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff; + picture_size = compute_losless_comp_body_size(pic_width, + pic_height, bit_depth_10); + cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12); + dpb_print(DECODE_ID(hw), + PRINT_FLAG_MMU_DETAIL, + "alloc_mmu new_fb_idx %d picture_size %d cur_mmu_4k_number %d\n", + cur_buf_idx, picture_size, cur_mmu_4k_number); + return decoder_mmu_box_alloc_idx( + hw->mmu_box, + cur_buf_idx, + cur_mmu_4k_number, + mmu_index_adr); + +} + +static int compute_losless_comp_body_size(int width, + int height, int bit_depth_10) +{ + int width_x64; + int height_x32; + int bsize; + + width_x64 = width + 63; + width_x64 >>= 6; + + height_x32 = height + 31; + height_x32 >>= 5; + +#ifdef H264_MMU + bsize = (bit_depth_10 ? 4096 : 3264) * width_x64*height_x32; +#else + bsize = (bit_depth_10 ? 4096 : 3072) * width_x64*height_x32; +#endif + return bsize; +} + +static int compute_losless_comp_header_size(int width, int height) +{ + int width_x64; + int width_x128; + int height_x64; + int hsize; + + width_x64 = width + 63; + width_x64 >>= 6; + + width_x128 = width + 127; + width_x128 >>= 7; + + height_x64 = height + 63; + height_x64 >>= 6; + +#ifdef H264_MMU + hsize = 128*width_x64*height_x64; +#else + hsize = 32*width_x128*height_x64; +#endif + return hsize; +} + + + +static int get_double_write_ratio(struct vdec_h264_hw_s *hw) +{ + int ratio = 1; + int dw_mode; + + dw_mode = hw->double_write_mode; + if ((dw_mode == 2) || + (dw_mode == 3)) + ratio = 4; + else if (dw_mode == 4) + ratio = 2; + return ratio; +} + + +static int get_dw_size(struct vdec_h264_hw_s *hw, u32 *pdw_buffer_size_u_v_h) +{ + int pic_width, pic_height; + int lcu_size = 16; + int dw_buf_size; + u32 dw_buffer_size_u_v; + u32 dw_buffer_size_u_v_h; + + pic_width = hw->frame_width; + pic_height = hw->frame_height; + + if (hw->double_write_mode) { + int pic_width_dw = pic_width / + get_double_write_ratio(hw); + int pic_height_dw = pic_height / + get_double_write_ratio(hw); + + int pic_width_lcu_dw = (pic_width_dw % lcu_size) ? + pic_width_dw / lcu_size + 1 : + pic_width_dw / lcu_size; + int pic_height_lcu_dw = (pic_height_dw % lcu_size) ? + pic_height_dw / lcu_size + 1 : + pic_height_dw / lcu_size; + int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw; + + + dw_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2; + dw_buffer_size_u_v_h = (dw_buffer_size_u_v + 0xffff) >> 16; + /*64k alignment*/ + dw_buf_size = ((dw_buffer_size_u_v_h << 16) * 3); + *pdw_buffer_size_u_v_h = dw_buffer_size_u_v_h; + } else { + *pdw_buffer_size_u_v_h = 0; + dw_buf_size = 0; + } + + return dw_buf_size; +} + + +static void hevc_mcr_config_canv2axitbl(struct vdec_h264_hw_s *hw, int restore) +{ + int i, size; + u32 canvas_addr; + unsigned long maddr; + int num_buff = hw->dpb.mDPB.size; + int dw_size = 0; + u32 dw_buffer_size_u_v_h; + u32 blkmode = mem_map_mode; + + canvas_addr = ANC0_CANVAS_ADDR; + for (i = 0; i < num_buff; i++) + WRITE_VREG((canvas_addr + i), i | (i << 8) | (i << 16)); + + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x1 << 1) | (0x1 << 2)); + size = hw->losless_comp_body_size + hw->losless_comp_header_size; + + + dw_size = get_dw_size(hw, &dw_buffer_size_u_v_h); + size += dw_size; + if (size > 0) + size += 0x10000; + + dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL, + "dw_buffer_size_u_v_h = %d, dw_size = 0x%x, size = 0x%x\n", + dw_buffer_size_u_v_h, dw_size, size); + + dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL, + "body_size = %d, header_size = %d, body_size_sao = %d\n", + hw->losless_comp_body_size, + hw->losless_comp_header_size, + hw->losless_comp_body_size_sao); + + for (i = 0; i < num_buff; i++) { + if (!restore) { + if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, + HEADER_BUFFER_IDX(i), size, + DRIVER_HEADER_NAME, &maddr) < 0) { + dpb_print(DECODE_ID(hw), 0, + "%s malloc compress header failed %d\n", + DRIVER_HEADER_NAME, i); + return; + } + } else + maddr = hw->buffer_spec[i].alloc_header_addr; + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, maddr >> 5); + hw->buffer_spec[i].alloc_header_addr = maddr; + dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL, + "%s : canvas: %d axiaddr:%x size 0x%x\n", + __func__, i, (u32)maddr, size); + + if (hw->double_write_mode) { + u32 addr; + int canvas_w; + int canvas_h; + + canvas_w = hw->frame_width / + get_double_write_ratio(hw); + canvas_h = hw->frame_height / + get_double_write_ratio(hw); + + if (mem_map_mode == 0) + canvas_w = ALIGN(canvas_w, 32); + else + canvas_w = ALIGN(canvas_w, 64); + canvas_h = ALIGN(canvas_h, 32); + + hw->buffer_spec[i].dw_y_adr = + maddr + hw->losless_comp_header_size; + + hw->buffer_spec[i].dw_y_adr = + ((hw->buffer_spec[i].dw_y_adr + 0xffff) >> 16) + << 16; + hw->buffer_spec[i].dw_u_v_adr = + hw->buffer_spec[i].dw_y_adr + + (dw_buffer_size_u_v_h << 16) * 2; + + + hw->buffer_spec[i].buf_adr + = hw->buffer_spec[i].dw_y_adr; + addr = hw->buffer_spec[i].buf_adr; + + + dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL, + "dw_y_adr = 0x%x, dw_u_v_adr = 0x%x, y_addr = 0x%x, u_addr = 0x%x, v_addr = 0x%x, width = %d, height = %d\n", + hw->buffer_spec[i].dw_y_adr, + hw->buffer_spec[i].dw_u_v_adr, + hw->buffer_spec[i].y_addr, + hw->buffer_spec[i].u_addr, + hw->buffer_spec[i].v_addr, + canvas_w, + canvas_h); + + hw->buffer_spec[i].canvas_config[0].phy_addr = + hw->buffer_spec[i].dw_y_adr; + hw->buffer_spec[i].canvas_config[0].width = canvas_w; + hw->buffer_spec[i].canvas_config[0].height = canvas_h; + hw->buffer_spec[i].canvas_config[0].block_mode = + blkmode; + hw->buffer_spec[i].canvas_config[0].endian = 7; + + hw->buffer_spec[i].canvas_config[1].phy_addr = + hw->buffer_spec[i].dw_u_v_adr; + hw->buffer_spec[i].canvas_config[1].width = canvas_w; + hw->buffer_spec[i].canvas_config[1].height = canvas_h; + hw->buffer_spec[i].canvas_config[1].block_mode = + blkmode; + hw->buffer_spec[i].canvas_config[1].endian = 7; + } + } + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1); + + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (0<<1) | 1); + for (i = 0; i < 32; i++) + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0); + return; +} +static void hevc_mcr_config_mc_ref(struct vdec_h264_hw_s *hw) +{ + u32 i; + u32 ref_canv; + struct Slice *pSlice = &(hw->dpb.mSlice); + /*REFLIST[0]*/ + for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) { + struct StorablePicture *ref = pSlice->listX[0][i]; + WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24); + ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff; + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (ref->buf_spec_num & 0x3f) << 8); + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv); + } + /*REFLIST[1]*/ + for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) { + struct StorablePicture *ref = pSlice->listX[1][i]; + WRITE_VREG(CURR_CANVAS_CTRL, ref->buf_spec_num<<24); + ref_canv = READ_VREG(CURR_CANVAS_CTRL)&0xffffff; + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (ref->buf_spec_num & 0x3f) << 8); + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, ref_canv); + } + return; +} + +static void hevc_mcr_config_mcrcc(struct vdec_h264_hw_s *hw) +{ + u32 rdata32; + u32 rdata32_2; + u32 slice_type; + struct StorablePicture *ref; + struct Slice *pSlice; + slice_type = hw->dpb.mSlice.slice_type; + pSlice = &(hw->dpb.mSlice); + WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); + if (slice_type == I_SLICE) { + WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0); + return; + } + if (slice_type == B_SLICE) { + ref = pSlice->listX[0][0]; + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + ((ref->buf_spec_num & 0x3f) << 8)); + rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32 = rdata32 & 0xffff; + rdata32 = rdata32 | (rdata32 << 16); + WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32); + + ref = pSlice->listX[1][0]; + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + ((ref->buf_spec_num & 0x3f) << 8)); + rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32_2 = rdata32_2 & 0xffff; + rdata32_2 = rdata32_2 | (rdata32_2 << 16); + if (rdata32 == rdata32_2) { + ref = pSlice->listX[1][1]; + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + ((ref->buf_spec_num & 0x3f) << 8)); + rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32_2 = rdata32_2 & 0xffff; + rdata32_2 = rdata32_2 | (rdata32_2 << 16); + } + WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2); + } else { /*P-PIC*/ + ref = pSlice->listX[0][0]; + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + ((ref->buf_spec_num & 0x3f) << 8)); + rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32 = rdata32 & 0xffff; + rdata32 = rdata32 | (rdata32 << 16); + WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32); + + ref = pSlice->listX[0][1]; + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + ((ref->buf_spec_num & 0x3f) << 8)); + rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32 = rdata32 & 0xffff; + rdata32 = rdata32 | (rdata32 << 16); + WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32); + } + WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); + return; +} + +static void hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw, + u32 width, u32 height) { + u32 data32; + u32 lcu_x_num, lcu_y_num; + u32 lcu_total; + u32 mc_buffer_size_u_v; + u32 mc_buffer_size_u_v_h; + + lcu_x_num = (width + 15) >> 4; + lcu_y_num = (height + 15) >> 4; + lcu_total = lcu_x_num * lcu_y_num; + + hw->mc_buffer_size_u_v = mc_buffer_size_u_v = lcu_total*16*16/2; + hw->mc_buffer_size_u_v_h = + mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff)>>16; + + hw->losless_comp_body_size = 0; + + hw->losless_comp_body_size_sao = + compute_losless_comp_body_size(width, height, 0); + hw->losless_comp_header_size = + compute_losless_comp_header_size(width, height); + + WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1); /*sw reset ipp10b_top*/ + WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x0); /*sw reset ipp10b_top*/ + + /* setup lcu_size = 16*/ + WRITE_VREG(HEVCD_IPP_TOP_LCUCONFIG, 16); /*set lcu size = 16*/ + /*pic_width/pic_height*/ + WRITE_VREG(HEVCD_IPP_TOP_FRMCONFIG, + (height & 0xffff) << 16 | (width & 0xffff)); + /* bitdepth_luma = 8*/ + /* bitdepth_chroma = 8*/ + WRITE_VREG(HEVCD_IPP_BITDEPTH_CONFIG, 0x0);/*set bit-depth 8 */ + +#ifdef H265_LOSLESS_COMPRESS_MODE + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4)); + WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0); +#else + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31); +#endif + data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG); + data32 &= (~0x30); + data32 |= (mem_map_mode << 4); + WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32); + + WRITE_VREG(HEVCD_MPP_DECOMP_CTL3, + (0x80 << 20) | (0x80 << 10) | (0xff)); + + WRITE_VREG(HEVCD_MPP_VDEC_MCR_CTL, 0x1 | (0x1 << 4)); + + /*comfig vdec:h264:mdec to use hevc mcr/mcrcc/decomp*/ + WRITE_VREG(MDEC_PIC_DC_MUX_CTRL, + READ_VREG(MDEC_PIC_DC_MUX_CTRL) | 0x1 << 31); + /* ipp_enable*/ + WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1 << 1); + + data32 = READ_VREG(HEVC_SAO_CTRL0); + data32 &= (~0xf); + data32 |= 0x4; + WRITE_VREG(HEVC_SAO_CTRL0, data32); + WRITE_VREG(HEVC_SAO_PIC_SIZE, (height & 0xffff) << 16 | + (width & 0xffff)); + data32 = ((lcu_x_num-1) | (lcu_y_num-1) << 16); + + WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32); + data32 = (lcu_x_num | lcu_y_num << 16); + WRITE_VREG(HEVC_SAO_TILE_SIZE_LCU, data32); + data32 = (mc_buffer_size_u_v_h << 16) << 1; + WRITE_VREG(HEVC_SAO_Y_LENGTH, data32); + data32 = (mc_buffer_size_u_v_h << 16); + WRITE_VREG(HEVC_SAO_C_LENGTH, data32); + + data32 = READ_VREG(HEVC_SAO_CTRL1); + data32 &= (~0x3000); + data32 &= (~0xff0); + data32 |= endian; /* Big-Endian per 64-bit */ + + if (hw->mmu_enable && hw->double_write_mode) + data32 |= ((mem_map_mode << 12)); + else + data32 |= ((mem_map_mode << 12)|2); + + WRITE_VREG(HEVC_SAO_CTRL1, data32); + +#ifdef H265_DW_NO_SCALE + WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) & ~(0xff << 16)); + if (hw->mmu_enable && hw->double_write_mode) { + data32 = READ_VREG(HEVC_SAO_CTRL5); + data32 &= (~(0xff << 16)); + if (hw->double_write_mode == 2 || + hw->double_write_mode == 3) + data32 |= (0xff<<16); + else if (hw->double_write_mode == 4) + data32 |= (0x33<<16); + WRITE_VREG(HEVC_SAO_CTRL5, data32); + } + + +#endif + + +#ifdef H265_LOSLESS_COMPRESS_MODE + data32 = READ_VREG(HEVC_SAO_CTRL5); + data32 |= (1<<9); /*8-bit smem-mode*/ + WRITE_VREG(HEVC_SAO_CTRL5, data32); + + WRITE_VREG(HEVC_CM_BODY_LENGTH, hw->losless_comp_body_size_sao); + WRITE_VREG(HEVC_CM_HEADER_OFFSET, hw->losless_comp_body_size); + WRITE_VREG(HEVC_CM_HEADER_LENGTH, hw->losless_comp_header_size); +#endif + +#ifdef H265_LOSLESS_COMPRESS_MODE + WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | (0x1 << 1)); + WRITE_VREG(HEVC_SAO_CTRL5, READ_VREG(HEVC_SAO_CTRL5) | (0x1 << 10)); +#endif + + WRITE_VREG(HEVC_SAO_CTRL9, READ_VREG(HEVC_SAO_CTRL9) | 0x1 << 7); + + memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE); + + WRITE_VREG(MDEC_EXTIF_CFG0, hw->extif_addr); + WRITE_VREG(MDEC_EXTIF_CFG1, 0x80000000); + return; +} + +static void hevc_sao_set_slice_type(struct vdec_h264_hw_s *hw, + u32 is_new_pic, u32 is_idr) +{ + hw->is_new_pic = is_new_pic; + hw->is_idr_frame = is_idr; + return; +} + +static void hevc_sao_set_pic_buffer(struct vdec_h264_hw_s *hw, + struct StorablePicture *pic) { + u32 mc_y_adr; + u32 mc_u_v_adr; + u32 dw_y_adr; + u32 dw_u_v_adr; + u32 canvas_addr; + int ret; + if (hw->is_new_pic != 1) + return; + + if (hw->is_idr_frame) { + /* William TBD */ + memset(hw->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE); + } + + WRITE_VREG(CURR_CANVAS_CTRL, pic->buf_spec_num << 24); + canvas_addr = READ_VREG(CURR_CANVAS_CTRL)&0xffffff; + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) | + (0x0 << 2) | ((canvas_addr & 0xff) << 8)); + mc_y_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5; + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, (0x0 << 1) | + (0x0 << 2) | (((canvas_addr >> 8) & 0xff) << 8)); + mc_u_v_adr = READ_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA) << 5; + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1); + + + if (hw->double_write_mode) { + dw_y_adr = hw->buffer_spec[pic->buf_spec_num].dw_y_adr; + dw_u_v_adr = hw->buffer_spec[pic->buf_spec_num].dw_u_v_adr; + } else { + dw_y_adr = 0; + dw_u_v_adr = 0; + } +#ifdef H265_LOSLESS_COMPRESS_MODE + if (hw->double_write_mode) + WRITE_VREG(HEVC_SAO_Y_START_ADDR, dw_y_adr); + WRITE_VREG(HEVC_CM_BODY_START_ADDR, mc_y_adr); +#ifdef H264_MMU + WRITE_VREG(HEVC_CM_HEADER_START_ADDR, mc_y_adr); +#else + WRITE_VREG(HEVC_CM_HEADER_START_ADDR, + (mc_y_adr + hw->losless_comp_body_size)); +#endif +#else + WRITE_VREG(HEVC_SAO_Y_START_ADDR, mc_y_adr); +#endif + +#ifndef H265_LOSLESS_COMPRESS_MODE + WRITE_VREG(HEVC_SAO_C_START_ADDR, mc_u_v_adr); +#else + if (hw->double_write_mode) + WRITE_VREG(HEVC_SAO_C_START_ADDR, dw_u_v_adr); +#endif + +#ifndef LOSLESS_COMPRESS_MODE + if (hw->double_write_mode) { + WRITE_VREG(HEVC_SAO_Y_WPTR, mc_y_adr); + WRITE_VREG(HEVC_SAO_C_WPTR, mc_u_v_adr); + } +#else + WRITE_VREG(HEVC_SAO_Y_WPTR, dw_y_adr); + WRITE_VREG(HEVC_SAO_C_WPTR, dw_u_v_adr); +#endif + + ret = hevc_alloc_mmu(hw, pic->buf_spec_num, + hw->frame_width, hw->frame_height, 0x0, + hw->frame_mmu_map_addr); + if (ret != 0) { + dpb_print(DECODE_ID(hw), + PRINT_FLAG_MMU_DETAIL, "can't alloc need mmu1,idx %d ret =%d\n", + pic->buf_spec_num, + ret); + return; + } + + /*Reset SAO + Enable SAO slice_start*/ + WRITE_VREG(HEVC_SAO_INT_STATUS, + READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 28); + WRITE_VREG(HEVC_SAO_INT_STATUS, + READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 31); + /*pr_info("hevc_sao_set_pic_buffer:mc_y_adr: %x\n", mc_y_adr);*/ + /*Send coommand to hevc-code to supply 4k buffers to sao*/ + WRITE_VREG(H265_SAO_4K_SET_BASE, (u32)hw->frame_mmu_map_phy_addr); + WRITE_VREG(H265_SAO_4K_SET_COUNT, MAX_FRAME_4K_NUM); + WRITE_VREG(SYS_COMMAND, H265_PUT_SAO_4K_SET); + hw->frame_busy = 1; + return; +} + + +static void hevc_set_unused_4k_buff_idx(struct vdec_h264_hw_s *hw, + u32 buf_spec_num) { + WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24); + hw->hevc_cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL)&0xff; + dpb_print(DECODE_ID(hw), + PRINT_FLAG_MMU_DETAIL, " %s cur_buf_idx %d buf_spec_num %d\n", + __func__, hw->hevc_cur_buf_idx, buf_spec_num); + return; +} + + +static void hevc_set_frame_done(struct vdec_h264_hw_s *hw) +{ + ulong timeout = jiffies + HZ; + dpb_print(DECODE_ID(hw), + PRINT_FLAG_MMU_DETAIL, "hevc_frame_done...set\n"); + while ((READ_VREG(HEVC_SAO_INT_STATUS) & 0x1) == 0) { + if (time_after(jiffies, timeout)) { + dpb_print(DECODE_ID(hw), + PRINT_FLAG_MMU_DETAIL, " %s..timeout!\n", __func__); + break; + } + } + WRITE_VREG(HEVC_SAO_INT_STATUS, 0x1); + hw->frame_done = 1; + return; +} + +static void release_cur_decoding_buf(struct vdec_h264_hw_s *hw) +{ + struct h264_dpb_stru *p_H264_Dpb = &hw->dpb; + if (p_H264_Dpb->mVideo.dec_picture) { + release_picture(p_H264_Dpb, + p_H264_Dpb->mVideo.dec_picture); + p_H264_Dpb->mVideo.dec_picture->data_flag &= ~ERROR_FLAG; + p_H264_Dpb->mVideo.dec_picture = NULL; + if (hw->mmu_enable) + hevc_set_frame_done(hw); + } +} + +static void hevc_sao_wait_done(struct vdec_h264_hw_s *hw) +{ + ulong timeout = jiffies + HZ; + dpb_print(DECODE_ID(hw), + PRINT_FLAG_MMU_DETAIL, "hevc_sao_wait_done...start\n"); + while ((READ_VREG(HEVC_SAO_INT_STATUS) >> 31)) { + if (time_after(jiffies, timeout)) { + dpb_print(DECODE_ID(hw), + PRINT_FLAG_MMU_DETAIL, + "hevc_sao_wait_done...wait timeout!\n"); + break; + } + } + timeout = jiffies + HZ; + if ((hw->frame_busy == 1) && (hw->frame_done == 1)) { + WRITE_VREG(SYS_COMMAND, H265_ABORT_SAO_4K_SET); + while ((READ_VREG(SYS_COMMAND) & 0xff) != + H265_ABORT_SAO_4K_SET_DONE) { + if (time_after(jiffies, timeout)) { + dpb_print(DECODE_ID(hw), + PRINT_FLAG_MMU_DETAIL, + "wait h265_abort_sao_4k_set_done timeout!\n"); + break; + } + } + amhevc_stop(); + hw->frame_busy = 0; + hw->frame_done = 0; + dpb_print(DECODE_ID(hw), + PRINT_FLAG_MMU_DETAIL, + "sao wait done ,hevc stop!\n"); + } + return; +} +static void buf_spec_init(struct vdec_h264_hw_s *hw) +{ + int i; + unsigned long flags; + spin_lock_irqsave(&hw->bufspec_lock, flags); + for (i = 0; i < BUFSPEC_POOL_SIZE; i++) { + hw->buffer_spec[i].used = -1; + hw->buffer_spec[i].canvas_pos = -1; + } + if (dpb_is_debug(DECODE_ID(hw), + PRINT_FLAG_DUMP_BUFSPEC)) + dump_bufspec(hw, __func__); + spin_unlock_irqrestore(&hw->bufspec_lock, flags); +} + +/*is active in buf management */ +static unsigned char is_buf_spec_in_use(struct vdec_h264_hw_s *hw, + int buf_spec_num) +{ + unsigned char ret = 0; + if (hw->buffer_spec[buf_spec_num].used == 1 || + hw->buffer_spec[buf_spec_num].used == 2 || + hw->buffer_spec[buf_spec_num].used == 3 || + hw->buffer_spec[buf_spec_num].used == 5) + ret = 1; + return ret; +} + +static unsigned char is_buf_spec_in_disp_q(struct vdec_h264_hw_s *hw, + int buf_spec_num) +{ + unsigned char ret = 0; + if (hw->buffer_spec[buf_spec_num].used == 2 || + hw->buffer_spec[buf_spec_num].used == 3 || + hw->buffer_spec[buf_spec_num].used == 5) + ret = 1; + return ret; +} + +static int alloc_one_buf_spec(struct vdec_h264_hw_s *hw, int i) +{ + if (hw->mmu_enable) { + if (hw->buffer_spec[i].alloc_header_addr) + return 0; + else + return -1; + } else { + + int buf_size = (hw->mb_total << 8) + (hw->mb_total << 7); + int addr; + if (hw->buffer_spec[i].cma_alloc_addr) + return 0; + + if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, i, + PAGE_ALIGN(buf_size), DRIVER_NAME, + &hw->buffer_spec[i].cma_alloc_addr) < 0) { + hw->buffer_spec[i].cma_alloc_addr = 0; + dpb_print(DECODE_ID(hw), 0, + "%s, fail to alloc buf for bufspec%d, try later\n", + __func__, i + ); + return -1; + } + hw->buffer_spec[i].buf_adr = + hw->buffer_spec[i].cma_alloc_addr; + addr = hw->buffer_spec[i].buf_adr; + + + hw->buffer_spec[i].y_addr = addr; + addr += hw->mb_total << 8; + + hw->buffer_spec[i].u_addr = addr; + hw->buffer_spec[i].v_addr = addr; + addr += hw->mb_total << 7; + + hw->buffer_spec[i].canvas_config[0].phy_addr = + hw->buffer_spec[i].y_addr; + hw->buffer_spec[i].canvas_config[0].width = + hw->mb_width << 4; + hw->buffer_spec[i].canvas_config[0].height = + hw->mb_height << 4; + hw->buffer_spec[i].canvas_config[0].block_mode = + CANVAS_BLKMODE_32X32; + + hw->buffer_spec[i].canvas_config[1].phy_addr = + hw->buffer_spec[i].u_addr; + hw->buffer_spec[i].canvas_config[1].width = + hw->mb_width << 4; + hw->buffer_spec[i].canvas_config[1].height = + hw->mb_height << 3; + hw->buffer_spec[i].canvas_config[1].block_mode = + CANVAS_BLKMODE_32X32; + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS, + "%s, alloc buf for bufspec%d\n", + __func__, i + ); + } + return 0; +} + +static void config_decode_canvas(struct vdec_h264_hw_s *hw, int i) +{ + canvas_config(hw->buffer_spec[i]. + y_canvas_index, + hw->buffer_spec[i].y_addr, + hw->mb_width << 4, + hw->mb_height << 4, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_32X32); + + canvas_config(hw->buffer_spec[i]. + u_canvas_index, + hw->buffer_spec[i].u_addr, + hw->mb_width << 4, + hw->mb_height << 3, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_32X32); + WRITE_VREG(ANC0_CANVAS_ADDR + hw->buffer_spec[i].canvas_pos, + spec2canvas(&hw->buffer_spec[i])); +} + +static void config_decode_canvas_ex(struct vdec_h264_hw_s *hw, int i) +{ + u32 blkmode = mem_map_mode; + int canvas_w; + int canvas_h; + + canvas_w = hw->frame_width / + get_double_write_ratio(hw); + canvas_h = hw->frame_height / + get_double_write_ratio(hw); + + if (mem_map_mode == 0) + canvas_w = ALIGN(canvas_w, 32); + else + canvas_w = ALIGN(canvas_w, 64); + canvas_h = ALIGN(canvas_h, 32); + + canvas_config_ex(hw->buffer_spec[i]. + y_canvas_index, + hw->buffer_spec[i].dw_y_adr, + canvas_w, + canvas_h, + CANVAS_ADDR_NOWRAP, + blkmode, + 7); + + canvas_config_ex(hw->buffer_spec[i]. + u_canvas_index, + hw->buffer_spec[i].dw_u_v_adr, + canvas_w, + canvas_h, + CANVAS_ADDR_NOWRAP, + blkmode, + 7); +} + + +int get_free_buf_idx(struct vdec_s *vdec) +{ + int i; + unsigned long addr, flags; + int index = -1; + struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private; + int buf_total = BUFSPEC_POOL_SIZE; + spin_lock_irqsave(&hw->bufspec_lock, flags); + /*hw->start_search_pos = 0;*/ + for (i = hw->start_search_pos; i < buf_total; i++) { + if (hw->mmu_enable) + addr = hw->buffer_spec[i].alloc_header_addr; + else + addr = hw->buffer_spec[i].cma_alloc_addr; + if (hw->buffer_spec[i].used == 0 && addr) { + hw->buffer_spec[i].used = 1; + hw->start_search_pos = i+1; + index = i; + break; + } + } + if (index < 0) { + for (i = 0; i < hw->start_search_pos; i++) { + if (hw->mmu_enable) + addr = hw->buffer_spec[i].alloc_header_addr; + else + addr = hw->buffer_spec[i].cma_alloc_addr; + if (hw->buffer_spec[i].used == 0 && addr) { + hw->buffer_spec[i].used = 1; + hw->start_search_pos = i+1; + index = i; + break; + } + } + } + spin_unlock_irqrestore(&hw->bufspec_lock, flags); + if (hw->start_search_pos >= buf_total) + hw->start_search_pos = 0; + dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL, + "%s, buf_spec_num %d\n", __func__, index); + + if (index < 0) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR, + "%s fail\n", __func__); + vmh264_dump_state(vdec); + } + + if (dpb_is_debug(DECODE_ID(hw), + PRINT_FLAG_DUMP_BUFSPEC)) + dump_bufspec(hw, __func__); + return index; +} + +int release_buf_spec_num(struct vdec_s *vdec, int buf_spec_num) +{ + u32 cur_buf_idx; + unsigned long flags; + struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private; + dpb_print(DECODE_ID(hw), PRINT_FLAG_MMU_DETAIL, + "%s buf_spec_num %d used %d\n", + __func__, buf_spec_num, + hw->buffer_spec[buf_spec_num].used); + if (buf_spec_num >= 0 && + buf_spec_num < BUFSPEC_POOL_SIZE + ) { + spin_lock_irqsave(&hw->bufspec_lock, flags); + hw->buffer_spec[buf_spec_num].used = 0; + spin_unlock_irqrestore(&hw->bufspec_lock, flags); + if (hw->mmu_enable) { + WRITE_VREG(CURR_CANVAS_CTRL, buf_spec_num<<24); + cur_buf_idx = READ_VREG(CURR_CANVAS_CTRL); + cur_buf_idx = cur_buf_idx&0xff; + decoder_mmu_box_free_idx(hw->mmu_box, cur_buf_idx); + } + release_aux_data(hw, buf_spec_num); + } + if (dpb_is_debug(DECODE_ID(hw), + PRINT_FLAG_DUMP_BUFSPEC)) + dump_bufspec(hw, __func__); + return 0; +} + +static void config_buf_specs(struct vdec_s *vdec) +{ + int i, j; + unsigned long flags; + struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private; + spin_lock_irqsave(&hw->bufspec_lock, flags); + for (i = 0, j = 0; + j < hw->dpb.mDPB.size + && i < BUFSPEC_POOL_SIZE; + i++) { + int canvas; + if (hw->buffer_spec[i].used != -1) + continue; + canvas = vdec->get_canvas(j, 2); + hw->buffer_spec[i].y_canvas_index = canvas_y(canvas); + hw->buffer_spec[i].u_canvas_index = canvas_u(canvas); + hw->buffer_spec[i].v_canvas_index = canvas_v(canvas); + hw->buffer_spec[i].used = 0; + + hw->buffer_spec[i].canvas_pos = j; + + /*pr_info("config canvas (%d) %x for bufspec %d\r\n", + j, canvas, i);*/ + j++; + } + spin_unlock_irqrestore(&hw->bufspec_lock, flags); +} + +static void config_buf_specs_ex(struct vdec_s *vdec) +{ + int i, j; + unsigned long flags; + struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private; + spin_lock_irqsave(&hw->bufspec_lock, flags); + for (i = 0, j = 0; + j < hw->dpb.mDPB.size + && i < BUFSPEC_POOL_SIZE; + i++) { + int canvas; + if (hw->buffer_spec[i].used != -1) + continue; + canvas = vdec->get_canvas(j, 2); + hw->buffer_spec[i].y_canvas_index = canvas_y(canvas); + hw->buffer_spec[i].u_canvas_index = canvas_u(canvas); + hw->buffer_spec[i].v_canvas_index = canvas_v(canvas); + hw->buffer_spec[i].used = 0; + hw->buffer_spec[i].alloc_header_addr = 0; + + hw->buffer_spec[i].canvas_pos = j; + + pr_info("config canvas (%d) %x for bufspec %d\r\n", + j, canvas, i); + j++; + } + spin_unlock_irqrestore(&hw->bufspec_lock, flags); +} + + +static void dealloc_buf_specs(struct vdec_h264_hw_s *hw, + unsigned char release_all) +{ + int i; + unsigned long flags; + unsigned char dealloc_flag = 0; + for (i = 0; i < BUFSPEC_POOL_SIZE; i++) { + if (hw->buffer_spec[i].used == 4 || + release_all) { + dealloc_flag = 1; + dpb_print(DECODE_ID(hw), + PRINT_FLAG_DPB_DETAIL, + "%s buf_spec_num %d\n", + __func__, i + ); + spin_lock_irqsave + (&hw->bufspec_lock, flags); + hw->buffer_spec[i].used = -1; + spin_unlock_irqrestore + (&hw->bufspec_lock, flags); + release_aux_data(hw, i); + + if (!hw->mmu_enable) { + if (hw->buffer_spec[i].cma_alloc_addr) { + decoder_bmmu_box_free_idx( + hw->bmmu_box, + i); + spin_lock_irqsave + (&hw->bufspec_lock, flags); + hw->buffer_spec[i].cma_alloc_addr = 0; + hw->buffer_spec[i].buf_adr = 0; + spin_unlock_irqrestore + (&hw->bufspec_lock, flags); + } + } else { + if (hw->buffer_spec[i].alloc_header_addr) { + decoder_mmu_box_free_idx( + hw->mmu_box, + i); + spin_lock_irqsave + (&hw->bufspec_lock, flags); + hw->buffer_spec[i]. + alloc_header_addr = 0; + hw->buffer_spec[i].buf_adr = 0; + spin_unlock_irqrestore + (&hw->bufspec_lock, flags); + } + } + } + } + if (dealloc_flag && + dpb_is_debug(DECODE_ID(hw), + PRINT_FLAG_DUMP_BUFSPEC)) + dump_bufspec(hw, __func__); + return; +} + +unsigned char have_free_buf_spec(struct vdec_s *vdec) +{ + int i; + unsigned long addr; + struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private; + int canvas_pos_min = BUFSPEC_POOL_SIZE; + int index = -1; + int ret = 0; + int allocated_count = 0; + for (i = 0; i < BUFSPEC_POOL_SIZE; i++) { + if (hw->mmu_enable) + addr = hw->buffer_spec[i].alloc_header_addr; + else + addr = hw->buffer_spec[i].cma_alloc_addr; + if (hw->buffer_spec[i].used == 0) { + + if (addr) + return 1; + if (hw->buffer_spec[i].canvas_pos < canvas_pos_min) { + canvas_pos_min = hw->buffer_spec[i].canvas_pos; + index = i; + } + } + if (addr) + allocated_count++; + } + if (index >= 0) { + mutex_lock(&vmh264_mutex); + dealloc_buf_specs(hw, 0); + if (max_alloc_buf_count == 0 || + allocated_count < max_alloc_buf_count) { + if (alloc_one_buf_spec(hw, index) >= 0) + ret = 1; + } + mutex_unlock(&vmh264_mutex); + } + return ret; +} + +static int get_buf_spec_by_canvas_pos(struct vdec_h264_hw_s *hw, + int canvas_pos) +{ + int i; + int j = 0; + for (i = 0; i < BUFSPEC_POOL_SIZE; i++) { + if (hw->buffer_spec[i].canvas_pos >= 0) { + if (j == canvas_pos) + return i; + j++; + } + } + return -1; +} +static void update_vf_memhandle(struct vdec_h264_hw_s *hw, + struct vframe_s *vf, int index) +{ + if (index < 0) { + vf->mem_handle = NULL; + vf->mem_head_handle = NULL; + } else if (vf->type & VIDTYPE_SCATTER) { + vf->mem_handle = + decoder_mmu_box_get_mem_handle( + hw->mmu_box, index); + vf->mem_head_handle = + decoder_bmmu_box_get_mem_handle( + hw->bmmu_box, HEADER_BUFFER_IDX(index)); + } else { + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + hw->bmmu_box, VF_BUFFER_IDX(index)); + /* vf->mem_head_handle = + decoder_bmmu_box_get_mem_handle( + hw->bmmu_box, HEADER_BUFFER_IDX(index));*/ + } + return; +} +static int check_force_interlace(struct vdec_h264_hw_s *hw, + struct FrameStore *frame) +{ + int bForceInterlace = 0; + + if (frame->frame) { + if (frame->frame->coded_frame + && !frame->frame->frame_mbs_only_flag) { + if (frame->frame->structure == FRAME) + return 1; + } + } + + if ((dec_control & DEC_CONTROL_FLAG_FORCE_2997_1080P_INTERLACE) + && (hw->frame_width == 1920) + && (hw->frame_height >= 1080) + && (hw->frame_dur == 3203)) { + bForceInterlace = 1; + } else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_576P_INTERLACE) + && (hw->frame_width == 720) + && (hw->frame_height == 576) + && (hw->frame_dur == 3840)) { + bForceInterlace = 1; + } + + return bForceInterlace; +} + +int prepare_display_buf(struct vdec_s *vdec, struct FrameStore *frame) +{ + struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private; + struct vframe_s *vf = NULL; + int buffer_index = frame->buf_spec_num; + int vf_count = 1; + int i; + int bForceInterlace = 0; + + if (buffer_index < 0 || buffer_index >= BUFSPEC_POOL_SIZE) { + dpb_print(DECODE_ID(hw), 0, + "%s, buffer_index 0x%x is beyond range\n", + __func__, buffer_index); + return -1; + } + if (force_disp_bufspec_num & 0x100) { + /*recycle directly*/ + if (hw->buffer_spec[frame->buf_spec_num].used != 3 && + hw->buffer_spec[frame->buf_spec_num].used != 5) + set_frame_output_flag(&hw->dpb, frame->index); + + /*make pre_output not set*/ + return -1; + } + if (error_proc_policy & 0x1000) { + int error_skip_i_count = (error_skip_count >> 12) & 0xf; + int error_skip_frame_count = error_skip_count & 0xfff; + if (((hw->no_error_count < error_skip_frame_count) + && (error_skip_i_count == 0 || + hw->no_error_i_count < error_skip_i_count)) + && (!(frame->data_flag & I_FLAG))) + frame->data_flag |= ERROR_FLAG; + } + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, + "%s, buffer_index 0x%x frame_error %x poc %d hw error %x error_proc_policy %x\n", + __func__, buffer_index, frame->data_flag & ERROR_FLAG, + frame->poc, hw->data_flag & ERROR_FLAG, + error_proc_policy); + if ((frame->data_flag & NODISP_FLAG) || + (frame->data_flag & NULL_FLAG) || + (frame->data_flag & ERROR_FLAG) || + ((!hw->send_error_frame_flag) && + (frame->data_flag & ERROR_FLAG)) || + ((hw->i_only & 0x1) && + (!(frame->data_flag & I_FLAG))) + ) { + set_frame_output_flag(&hw->dpb, frame->index); + return 0; /*do not return -1, + otherwise flush_dpb() will not flush all dbp frames*/ + } + display_frame_count[DECODE_ID(hw)]++; + + if (dpb_is_debug(DECODE_ID(hw), + PRINT_FLAG_DPB_DETAIL)) { + dpb_print(DECODE_ID(hw), 0, + "%s, fs[%d] poc %d, buf_spec_num %d\n", + __func__, frame->index, frame->poc, + frame->buf_spec_num); + print_pic_info(DECODE_ID(hw), "predis_frm", + frame->frame, -1); + print_pic_info(DECODE_ID(hw), "predis_top", + frame->top_field, -1); + print_pic_info(DECODE_ID(hw), "predis_bot", + frame->bottom_field, -1); + } + + if (!is_interlace(frame)) + vf_count = 1; + else + vf_count = 2; + bForceInterlace = check_force_interlace(hw, frame); + if (bForceInterlace) + vf_count = 2; + hw->buffer_spec[buffer_index].vf_ref = 0; + for (i = 0; i < vf_count; i++) { + if (kfifo_get(&hw->newframe_q, &vf) == 0 || + vf == NULL) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR, + "%s fatal error, no available buffer slot.\n", + __func__); + return -1; + } + vf->duration_pulldown = 0; + vf->pts = frame->pts; + vf->pts_us64 = frame->pts64; + vf->index = VF_INDEX(frame->index, buffer_index); + if (hw->mmu_enable) { + if (hw->double_write_mode & 0x10) { + /* double write only */ + vf->compBodyAddr = 0; + vf->compHeadAddr = 0; + } else { + /*head adr*/ + vf->compHeadAddr = + hw->buffer_spec[buffer_index].alloc_header_addr; + /*body adr*/ + vf->compBodyAddr = 0; + vf->canvas0Addr = vf->canvas1Addr = 0; + } + + vf->type = VIDTYPE_SCATTER; + + if (hw->double_write_mode) { + vf->type |= VIDTYPE_PROGRESSIVE + | VIDTYPE_VIU_FIELD; + vf->type |= VIDTYPE_VIU_NV21; + if (hw->double_write_mode == 3) + vf->type |= VIDTYPE_COMPRESS; + + vf->canvas0Addr = vf->canvas1Addr = -1; + vf->plane_num = 2; + vf->canvas0_config[0] = + hw->buffer_spec[buffer_index]. + canvas_config[0]; + vf->canvas0_config[1] = + hw->buffer_spec[buffer_index]. + canvas_config[1]; + + vf->canvas1_config[0] = + hw->buffer_spec[buffer_index]. + canvas_config[0]; + vf->canvas1_config[1] = + hw->buffer_spec[buffer_index]. + canvas_config[1]; + + } else { + vf->type |= + VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD; + vf->canvas0Addr = vf->canvas1Addr = 0; + } + vf->bitdepth = + BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8; + + vf->compWidth = hw->frame_width; + vf->compHeight = hw->frame_height; + } else { + vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD | + VIDTYPE_VIU_NV21; + vf->canvas0Addr = vf->canvas1Addr = + spec2canvas(&hw->buffer_spec[buffer_index]); + } + set_frame_info(hw, vf, buffer_index); + + if (hw->mmu_enable && hw->double_write_mode) { + vf->width = hw->frame_width / + get_double_write_ratio(hw); + vf->height = hw->frame_height / + get_double_write_ratio(hw); + } + + vf->flag = 0; + if (frame->data_flag & I_FLAG) + vf->flag |= VFRAME_FLAG_SYNCFRAME; + if (frame->data_flag & ERROR_FLAG) + vf->flag |= VFRAME_FLAG_ERROR_RECOVERY; + update_vf_memhandle(hw, vf, buffer_index); + hw->buffer_spec[buffer_index].used = 2; + hw->buffer_spec[buffer_index].vf_ref++; + + if (bForceInterlace || is_interlace(frame)) { + vf->type = + VIDTYPE_INTERLACE_FIRST | + VIDTYPE_VIU_NV21; + + if (bForceInterlace) { + vf->type |= (i == 0 ? + VIDTYPE_INTERLACE_TOP : + VIDTYPE_INTERLACE_BOTTOM); + if (i == 1) { + vf->pts = 0; + vf->pts_us64 = 0; + } + } else if (frame->top_field->poc <= + frame->bottom_field->poc) /*top first*/ + vf->type |= (i == 0 ? + VIDTYPE_INTERLACE_TOP : + VIDTYPE_INTERLACE_BOTTOM); + else + vf->type |= (i == 0 ? + VIDTYPE_INTERLACE_BOTTOM : + VIDTYPE_INTERLACE_TOP); + vf->duration = vf->duration/2; + } + + kfifo_put(&hw->display_q, (const struct vframe_s *)vf); + hw->vf_pre_count++; + vf_notify_receiver(vdec->vf_provider_name, + VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL); + } + if (dpb_is_debug(DECODE_ID(hw), + PRINT_FLAG_DUMP_BUFSPEC)) + dump_bufspec(hw, __func__); + + return 0; +} + +/****************** + * Hardware config + */ +char *slice_type_name[] = { + "P_SLICE ", + "B_SLICE ", + "I_SLICE ", + "SP_SLICE", + "SI_SLICE", +}; + +char *picture_structure_name[] = { + "FRAME", + "TOP_FIELD", + "BOTTOM_FIELD" +}; + +void print_pic_info(int decindex, const char *info, + struct StorablePicture *pic, + int slice_type) +{ + if (pic) + dpb_print(decindex, PRINT_FLAG_DEC_DETAIL, + "%s: %s (original %s), %s, mb_aff_frame_flag %d poc %d, pic_num %d, buf_spec_num %d data_flag 0x%x\n", + info, + picture_structure_name[pic->structure], + pic->coded_frame ? "Frame" : "Field", + (slice_type < 0) ? "" : slice_type_name[slice_type], + pic->mb_aff_frame_flag, + pic->poc, + pic->pic_num, + pic->buf_spec_num, + pic->data_flag); +} + +static void reset_process_time(struct vdec_h264_hw_s *hw) +{ + if (hw->start_process_time) { + unsigned process_time = + 1000 * (jiffies - hw->start_process_time) / HZ; + hw->start_process_time = 0; + if (process_time > max_process_time[DECODE_ID(hw)]) + max_process_time[DECODE_ID(hw)] = process_time; + } +} + +static void start_process_time(struct vdec_h264_hw_s *hw) +{ + hw->decode_timeout_count = 2; + hw->start_process_time = jiffies; +} + +static void config_aux_buf(struct vdec_h264_hw_s *hw) +{ + WRITE_VREG(H264_AUX_ADR, hw->aux_phy_addr); + WRITE_VREG(H264_AUX_DATA_SIZE, + ((hw->prefix_aux_size >> 4) << 16) | + (hw->suffix_aux_size >> 4) + ); +} + +/* +* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta +*/ +static void set_aux_data(struct vdec_h264_hw_s *hw, + struct StorablePicture *pic, unsigned char suffix_flag, + unsigned char dv_meta_flag, struct vdec_h264_hw_s *hw_b) +{ + int i; + unsigned short *aux_adr; + unsigned size_reg_val = + READ_VREG(H264_AUX_DATA_SIZE); + unsigned aux_count = 0; + int aux_size = 0; + struct vdec_h264_hw_s *hw_buf = hw_b ? hw_b : hw; + if (pic == NULL || pic->buf_spec_num < 0 || pic->buf_spec_num >= BUFSPEC_POOL_SIZE + || (!is_buf_spec_in_use(hw, pic->buf_spec_num))) + return; + + if (suffix_flag) { + aux_adr = (unsigned short *) + (hw_buf->aux_addr + + hw_buf->prefix_aux_size); + aux_count = + ((size_reg_val & 0xffff) << 4) + >> 1; + aux_size = + hw_buf->suffix_aux_size; + } else { + aux_adr = + (unsigned short *)hw_buf->aux_addr; + aux_count = + ((size_reg_val >> 16) << 4) + >> 1; + aux_size = + hw_buf->prefix_aux_size; + } + if (dpb_is_debug(DECODE_ID(hw), + PRINT_FLAG_DPB_DETAIL)) { + dpb_print(DECODE_ID(hw), 0, + "%s:old size %d count %d,suf %d dv_flag %d\r\n", + __func__, AUX_DATA_SIZE(pic), + aux_count, suffix_flag, dv_meta_flag); + } + if (aux_size > 0 && aux_count > 0) { + int heads_size = 0; + int new_size; + char *new_buf; + for (i = 0; i < aux_count; i++) { + unsigned char tag = aux_adr[i] >> 8; + if (tag != 0 && tag != 0xff) { + if (dv_meta_flag == 0) + heads_size += 8; + else if (dv_meta_flag == 1 && tag == 0x1) + heads_size += 8; + else if (dv_meta_flag == 2 && tag != 0x1) + heads_size += 8; + } + } + new_size = AUX_DATA_SIZE(pic) + aux_count + heads_size; + new_buf = krealloc(AUX_DATA_BUF(pic), + new_size, + GFP_KERNEL); + if (new_buf) { + unsigned char valid_tag = 0; + unsigned char *h = + new_buf + + AUX_DATA_SIZE(pic); + unsigned char *p = h + 8; + int len = 0; + int padding_len = 0; + AUX_DATA_BUF(pic) = new_buf; + for (i = 0; i < aux_count; i += 4) { + int ii; + unsigned char tag = aux_adr[i + 3] >> 8; + if (tag != 0 && tag != 0xff) { + if (dv_meta_flag == 0) + valid_tag = 1; + else if (dv_meta_flag == 1 + && tag == 0x1) + valid_tag = 1; + else if (dv_meta_flag == 2 + && tag != 0x1) + valid_tag = 1; + else + valid_tag = 0; + if (valid_tag && len > 0) { + AUX_DATA_SIZE(pic) += + (len + 8); + h[0] = + (len >> 24) & 0xff; + h[1] = + (len >> 16) & 0xff; + h[2] = + (len >> 8) & 0xff; + h[3] = + (len >> 0) & 0xff; + h[6] = + (padding_len >> 8) + & 0xff; + h[7] = + (padding_len) & 0xff; + h += (len + 8); + p += 8; + len = 0; + padding_len = 0; + } + if (valid_tag) { + h[4] = tag; + h[5] = 0; + h[6] = 0; + h[7] = 0; + } + } + if (valid_tag) { + for (ii = 0; ii < 4; ii++) { + unsigned short aa = + aux_adr[i + 3 + - ii]; + *p = aa & 0xff; + p++; + len++; + /*if ((aa >> 8) == 0xff) + padding_len++;*/ + } + } + } + if (len > 0) { + AUX_DATA_SIZE(pic) += (len + 8); + h[0] = (len >> 24) & 0xff; + h[1] = (len >> 16) & 0xff; + h[2] = (len >> 8) & 0xff; + h[3] = (len >> 0) & 0xff; + h[6] = (padding_len >> 8) & 0xff; + h[7] = (padding_len) & 0xff; + } + if (dpb_is_debug(DECODE_ID(hw), + PRINT_FLAG_DPB_DETAIL)) { + dpb_print(DECODE_ID(hw), 0, + "aux: (size %d) suffix_flag %d\n", + AUX_DATA_SIZE(pic), suffix_flag); + for (i = 0; i < AUX_DATA_SIZE(pic); i++) { + dpb_print_cont(DECODE_ID(hw), 0, + "%02x ", AUX_DATA_BUF(pic)[i]); + if (((i + 1) & 0xf) == 0) + dpb_print_cont( + DECODE_ID(hw), + 0, "\n"); + } + dpb_print_cont(DECODE_ID(hw), + 0, "\n"); + } + + } + } + +} + +static void release_aux_data(struct vdec_h264_hw_s *hw, + int buf_spec_num) +{ + kfree(hw->buffer_spec[buf_spec_num].aux_data_buf); + hw->buffer_spec[buf_spec_num].aux_data_buf = NULL; + hw->buffer_spec[buf_spec_num].aux_data_size = 0; +} + +static void dump_aux_buf(struct vdec_h264_hw_s *hw) +{ + int i; + unsigned short *aux_adr = + (unsigned short *) + hw->aux_addr; + unsigned aux_size = + (READ_VREG(H264_AUX_DATA_SIZE) + >> 16) << 4; + + if (hw->prefix_aux_size > 0) { + dpb_print(DECODE_ID(hw), + 0, + "prefix aux: (size %d)\n", + aux_size); + for (i = 0; i < + (aux_size >> 1); i++) { + dpb_print_cont(DECODE_ID(hw), + 0, + "%04x ", + *(aux_adr + i)); + if (((i + 1) & 0xf) + == 0) + dpb_print_cont( + DECODE_ID(hw), + 0, "\n"); + } + } + if (hw->suffix_aux_size > 0) { + aux_adr = (unsigned short *) + (hw->aux_addr + + hw->prefix_aux_size); + aux_size = + (READ_VREG(H264_AUX_DATA_SIZE) & 0xffff) + << 4; + dpb_print(DECODE_ID(hw), + 0, + "suffix aux: (size %d)\n", + aux_size); + for (i = 0; i < + (aux_size >> 1); i++) { + dpb_print_cont(DECODE_ID(hw), + 0, + "%04x ", *(aux_adr + i)); + if (((i + 1) & 0xf) == 0) + dpb_print_cont(DECODE_ID(hw), + 0, "\n"); + } + } +} + +static void config_decode_mode(struct vdec_h264_hw_s *hw) +{ +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + struct vdec_s *vdec = hw_to_vdec(hw); +#endif + if (input_frame_based(hw_to_vdec(hw))) + WRITE_VREG(H264_DECODE_MODE, + DECODE_MODE_MULTI_FRAMEBASE); +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + else if (vdec->slave) + WRITE_VREG(H264_DECODE_MODE, + (hw->got_valid_nal << 8) | + DECODE_MODE_MULTI_DVBAL); + else if (vdec->master) + WRITE_VREG(H264_DECODE_MODE, + (hw->got_valid_nal << 8) | + DECODE_MODE_MULTI_DVENL); +#endif + else + WRITE_VREG(H264_DECODE_MODE, + DECODE_MODE_MULTI_STREAMBASE); + WRITE_VREG(H264_DECODE_SEQINFO, + hw->seq_info2); + WRITE_VREG(HEAD_PADING_REG, 0); + + if (hw->init_flag == 0) + WRITE_VREG(INIT_FLAG_REG, 0); + else + WRITE_VREG(INIT_FLAG_REG, 1); +} +int config_decode_buf(struct vdec_h264_hw_s *hw, struct StorablePicture *pic) +{ + /* static int count = 0; */ + int ret = 0; + struct h264_dpb_stru *p_H264_Dpb = &hw->dpb; + struct Slice *pSlice = &(p_H264_Dpb->mSlice); + unsigned int colocate_adr_offset; + unsigned int val; +#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF + int colocate_buf_index; +#endif +#define H264_BUFFER_INFO_INDEX PMV3_X /* 0xc24 */ +#define H264_BUFFER_INFO_DATA PMV2_X /* 0xc22 */ +#define H264_CURRENT_POC_IDX_RESET LAST_SLICE_MV_ADDR /* 0xc30 */ +#define H264_CURRENT_POC LAST_MVY /* 0xc32 shared with conceal MV */ + +#define H264_CO_MB_WR_ADDR VLD_C38 /* 0xc38 */ +/* bit 31:30 -- L1[0] picture coding structure, + * 00 - top field, 01 - bottom field, + * 10 - frame, 11 - mbaff frame + * bit 29 - L1[0] top/bot for B field pciture , 0 - top, 1 - bot + * bit 28:0 h264_co_mb_mem_rd_addr[31:3] + * -- only used for B Picture Direct mode [2:0] will set to 3'b000 + */ +#define H264_CO_MB_RD_ADDR VLD_C39 /* 0xc39 */ + +/* bit 15 -- flush co_mb_data to DDR -- W-Only + * bit 14 -- h264_co_mb_mem_wr_addr write Enable -- W-Only + * bit 13 -- h264_co_mb_info_wr_ptr write Enable -- W-Only + * bit 9 -- soft_reset -- W-Only + * bit 8 -- upgent + * bit 7:2 -- h264_co_mb_mem_wr_addr + * bit 1:0 -- h264_co_mb_info_wr_ptr + */ +#define H264_CO_MB_RW_CTL VLD_C3D /* 0xc3d */ + + unsigned long canvas_adr; + unsigned int ref_reg_val; + unsigned int one_ref_cfg = 0; + int h264_buffer_info_data_write_count; + int i, j; + unsigned int colocate_wr_adr; + unsigned int colocate_rd_adr; + unsigned char use_direct_8x8; + int canvas_pos; + canvas_pos = hw->buffer_spec[pic->buf_spec_num].canvas_pos; + WRITE_VREG(H264_CURRENT_POC_IDX_RESET, 0); + WRITE_VREG(H264_CURRENT_POC, pic->frame_poc); + WRITE_VREG(H264_CURRENT_POC, pic->top_poc); + WRITE_VREG(H264_CURRENT_POC, pic->bottom_poc); + + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "%s: pic_num is %d, poc is %d (%d, %d, %d), buf_spec_num %d canvas_pos %d\n", + __func__, pic->pic_num, pic->poc, pic->frame_poc, + pic->top_poc, pic->bottom_poc, pic->buf_spec_num, + canvas_pos); + print_pic_info(DECODE_ID(hw), "cur", pic, pSlice->slice_type); + + WRITE_VREG(CURR_CANVAS_CTRL, canvas_pos << 24); + if (!hw->mmu_enable) { + canvas_adr = READ_VREG(CURR_CANVAS_CTRL) & 0xffffff; + WRITE_VREG(REC_CANVAS_ADDR, canvas_adr); + WRITE_VREG(DBKR_CANVAS_ADDR, canvas_adr); + WRITE_VREG(DBKW_CANVAS_ADDR, canvas_adr); + } else + hevc_sao_set_pic_buffer(hw, pic); + + if (pic->mb_aff_frame_flag) + hw->buffer_spec[pic->buf_spec_num].info0 = 0xf4c0; + else if (pic->structure == TOP_FIELD) + hw->buffer_spec[pic->buf_spec_num].info0 = 0xf400; + else if (pic->structure == BOTTOM_FIELD) + hw->buffer_spec[pic->buf_spec_num].info0 = 0xf440; + else + hw->buffer_spec[pic->buf_spec_num].info0 = 0xf480; + + if (pic->bottom_poc < pic->top_poc) + hw->buffer_spec[pic->buf_spec_num].info0 |= 0x100; + + hw->buffer_spec[pic->buf_spec_num].info1 = pic->top_poc; + hw->buffer_spec[pic->buf_spec_num].info2 = pic->bottom_poc; + WRITE_VREG(H264_BUFFER_INFO_INDEX, 16); + + for (j = 0; j < hw->dpb.mDPB.size; j++) { + int long_term_flag; + i = get_buf_spec_by_canvas_pos(hw, j); + if (i < 0) + break; + long_term_flag = + get_long_term_flag_by_buf_spec_num(p_H264_Dpb, i); + if (long_term_flag > 0) { + if (long_term_flag & 0x1) + hw->buffer_spec[i].info0 |= (1 << 4); + else + hw->buffer_spec[i].info0 &= ~(1 << 4); + + if (long_term_flag & 0x2) + hw->buffer_spec[i].info0 |= (1 << 5); + else + hw->buffer_spec[i].info0 &= ~(1 << 5); + } + + if (i == pic->buf_spec_num) + WRITE_VREG(H264_BUFFER_INFO_DATA, + hw->buffer_spec[i].info0 | 0xf); + else + WRITE_VREG(H264_BUFFER_INFO_DATA, + hw->buffer_spec[i].info0); + WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info1); + WRITE_VREG(H264_BUFFER_INFO_DATA, hw->buffer_spec[i].info2); + } + + /* config reference buffer */ + if (hw->mmu_enable) { + hevc_mcr_config_mc_ref(hw); + hevc_mcr_config_mcrcc(hw); + } + + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "list0 size %d\n", pSlice->listXsize[0]); + WRITE_VREG(H264_BUFFER_INFO_INDEX, 0); + ref_reg_val = 0; + j = 0; + h264_buffer_info_data_write_count = 0; + + for (i = 0; i < (unsigned int)(pSlice->listXsize[0]); i++) { + /*ref list 0 */ + struct StorablePicture *ref = pSlice->listX[0][i]; + unsigned int cfg; + /* bit[6:5] - frame/field info, + * 01 - top, 10 - bottom, 11 - frame + */ +#ifdef ERROR_CHECK + if (ref == NULL) { + hw->data_flag |= ERROR_FLAG; + pic->data_flag |= ERROR_FLAG; + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref list0 NULL\n"); + return -1; + } + if (ref->data_flag & ERROR_FLAG) { + hw->data_flag |= ERROR_FLAG; + pic->data_flag |= ERROR_FLAG; + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark1 \n"); + } + if (ref->data_flag & NULL_FLAG) + hw->data_flag |= NULL_FLAG; +#endif + canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos; + + if (ref->structure == TOP_FIELD) + cfg = 0x1; + else if (ref->structure == BOTTOM_FIELD) + cfg = 0x2; + else /* FRAME */ + cfg = 0x3; + one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5); + ref_reg_val <<= 8; + ref_reg_val |= one_ref_cfg; + j++; + + if (j == 4) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val); + WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val); + h264_buffer_info_data_write_count++; + j = 0; + } + print_pic_info(DECODE_ID(hw), "list0", + pSlice->listX[0][i], -1); + } + if (j != 0) { + while (j != 4) { + ref_reg_val <<= 8; + ref_reg_val |= one_ref_cfg; + j++; + } + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "H264_BUFFER_INFO_DATA: %x\n", + ref_reg_val); + WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val); + h264_buffer_info_data_write_count++; + } + ref_reg_val = (one_ref_cfg << 24) | (one_ref_cfg<<16) | + (one_ref_cfg << 8) | one_ref_cfg; + for (i = h264_buffer_info_data_write_count; i < 8; i++) + WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val); + + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "list1 size %d\n", pSlice->listXsize[1]); + WRITE_VREG(H264_BUFFER_INFO_INDEX, 8); + ref_reg_val = 0; + j = 0; + + for (i = 0; i < (unsigned int)(pSlice->listXsize[1]); i++) { + /* ref list 0 */ + struct StorablePicture *ref = pSlice->listX[1][i]; + unsigned int cfg; + /* bit[6:5] - frame/field info, + * 01 - top, 10 - bottom, 11 - frame + */ +#ifdef ERROR_CHECK + if (ref == NULL) { + hw->data_flag |= ERROR_FLAG; + pic->data_flag |= ERROR_FLAG; + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error list1 NULL\n"); + return -2; + } + if (ref->data_flag & ERROR_FLAG) { + pic->data_flag |= ERROR_FLAG; + hw->data_flag |= ERROR_FLAG; + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " ref error mark2\n"); + } + if (ref->data_flag & NULL_FLAG) + hw->data_flag |= NULL_FLAG; +#endif + canvas_pos = hw->buffer_spec[ref->buf_spec_num].canvas_pos; + if (ref->structure == TOP_FIELD) + cfg = 0x1; + else if (ref->structure == BOTTOM_FIELD) + cfg = 0x2; + else /* FRAME */ + cfg = 0x3; + one_ref_cfg = (canvas_pos & 0x1f) | (cfg << 5); + ref_reg_val <<= 8; + ref_reg_val |= one_ref_cfg; + j++; + + if (j == 4) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "H264_BUFFER_INFO_DATA: %x\n", + ref_reg_val); + WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val); + j = 0; + } + print_pic_info(DECODE_ID(hw), "list1", + pSlice->listX[1][i], -1); + } + if (j != 0) { + while (j != 4) { + ref_reg_val <<= 8; + ref_reg_val |= one_ref_cfg; + j++; + } + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "H264_BUFFER_INFO_DATA: %x\n", ref_reg_val); + WRITE_VREG(H264_BUFFER_INFO_DATA, ref_reg_val); + } + + /* configure co-locate buffer */ + while ((READ_VREG(H264_CO_MB_RW_CTL) >> 11) & 0x1) + ; + if ((pSlice->mode_8x8_flags & 0x4) && + (pSlice->mode_8x8_flags & 0x2)) + use_direct_8x8 = 1; + else + use_direct_8x8 = 0; + +#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF + colocate_adr_offset = + ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0) + ? 1 : 2) * 96; + if (use_direct_8x8) + colocate_adr_offset >>= 2; + + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n", + colocate_adr_offset, pSlice->first_mb_in_slice, + colocate_adr_offset * pSlice->first_mb_in_slice); + + colocate_adr_offset *= pSlice->first_mb_in_slice; + + if ((pic->colocated_buf_index >= 0) && + (pic->colocated_buf_index < p_H264_Dpb->colocated_buf_count)) { + colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start + + ((p_H264_Dpb->colocated_buf_size * + pic->colocated_buf_index) + >> (use_direct_8x8 ? 2 : 0)); + if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) > + p_H264_Dpb->colocated_mv_addr_end) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR, + "Error, colocate buf is not enough, index is %d\n", + pic->colocated_buf_index); + ret = -3; + } + val = colocate_wr_adr + colocate_adr_offset; + WRITE_VREG(H264_CO_MB_WR_ADDR, val); + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n", + val, pSlice->first_mb_in_slice, pic->structure, + colocate_adr_offset, pSlice->mode_8x8_flags, + p_H264_Dpb->colocated_buf_size); + } else { + WRITE_VREG(H264_CO_MB_WR_ADDR, 0xffffffff); + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "WRITE_VREG(H264_CO_MB_WR_ADDR) = 0xffffffff\n"); + } +#else + colocate_buf_index = hw->buffer_spec[pic->buf_spec_num].canvas_pos; + colocate_adr_offset = + ((pic->structure == FRAME && pic->mb_aff_frame_flag == 0) ? 1 : 2) * 96; + if (use_direct_8x8) + colocate_adr_offset >>= 2; + + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "colocate buf size of each mb 0x%x first_mb_in_slice 0x%x colocate_adr_offset 0x%x\r\n", + colocate_adr_offset, pSlice->first_mb_in_slice, + colocate_adr_offset * pSlice->first_mb_in_slice); + + colocate_adr_offset *= pSlice->first_mb_in_slice; + + colocate_wr_adr = p_H264_Dpb->colocated_mv_addr_start + + ((p_H264_Dpb->colocated_buf_size * colocate_buf_index) >> + (use_direct_8x8 ? 2 : 0)); + + if ((colocate_wr_adr + p_H264_Dpb->colocated_buf_size) > + p_H264_Dpb->colocated_mv_addr_end) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR, + "Error, colocate buf is not enough, col buf index is %d\n", + colocate_buf_index); + ret = -4; + } + val = colocate_wr_adr + colocate_adr_offset; + WRITE_VREG(H264_CO_MB_WR_ADDR, val); + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "WRITE_VREG(H264_CO_MB_WR_ADDR) = %x, first_mb_in_slice %x pic_structure %x colocate_adr_offset %x mode_8x8_flags %x colocated_buf_size %x\n", + val, pSlice->first_mb_in_slice, pic->structure, + colocate_adr_offset, pSlice->mode_8x8_flags, + p_H264_Dpb->colocated_buf_size); +#endif + if (pSlice->listXsize[1] > 0) { + struct StorablePicture *colocate_pic = pSlice->listX[1][0]; + /* H264_CO_MB_RD_ADDR[bit 31:30], + * original picture structure of L1[0], + * 00 - top field, 01 - bottom field, + * 10 - frame, 11 - mbaff frame + */ + int l10_structure; + int cur_colocate_ref_type; + /* H264_CO_MB_RD_ADDR[bit 29], top/bot for B field pciture, + * 0 - top, 1 - bot + */ + unsigned int val; +#ifdef ERROR_CHECK + if (colocate_pic == NULL) { + hw->data_flag |= ERROR_FLAG; + pic->data_flag |= ERROR_FLAG; + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocate error pic NULL\n"); + return -5; + } + if (colocate_pic->data_flag & ERROR_FLAG) { + pic->data_flag |= ERROR_FLAG; + hw->data_flag |= ERROR_FLAG; + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, " colocare ref error mark\n"); + } + if (colocate_pic->data_flag & NULL_FLAG) + hw->data_flag |= NULL_FLAG; +#endif + + if (colocate_pic->mb_aff_frame_flag) + l10_structure = 3; + else { + if (colocate_pic->coded_frame) + l10_structure = 2; + else + l10_structure = (colocate_pic->structure == + BOTTOM_FIELD) ? 1 : 0; + } +#if 0 + /*case0016, p16, + *cur_colocate_ref_type should be configured base on current pic + */ + if (pic->structure == FRAME && + pic->mb_aff_frame_flag) + cur_colocate_ref_type = 0; + else if (pic->structure == BOTTOM_FIELD) + cur_colocate_ref_type = 1; + else + cur_colocate_ref_type = 0; +#else + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + " CUR TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n", + pic->mb_aff_frame_flag, + pic->structure, + pic->coded_frame); + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + " COL TMP DEBUG : mb_aff_frame_flag : %d, structure : %d coded_frame %d\n", + colocate_pic->mb_aff_frame_flag, + colocate_pic->structure, + colocate_pic->coded_frame); + if (pic->structure == FRAME || pic->mb_aff_frame_flag) { + cur_colocate_ref_type = + (abs(pic->poc - colocate_pic->top_poc) + < abs(pic->poc - + colocate_pic->bottom_poc)) ? 0 : 1; + } else + cur_colocate_ref_type = + (colocate_pic->structure + == BOTTOM_FIELD) ? 1 : 0; +#endif + +#ifndef ONE_COLOCATE_BUF_PER_DECODE_BUF + if ((colocate_pic->colocated_buf_index >= 0) && + (colocate_pic->colocated_buf_index < + p_H264_Dpb->colocated_buf_count)) { + colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start + + ((p_H264_Dpb->colocated_buf_size * + colocate_pic->colocated_buf_index) + >> (use_direct_8x8 ? 2 : 0)); + if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) > + p_H264_Dpb->colocated_mv_addr_end) { + dpb_print(DECODE_ID(hw), + PRINT_FLAG_ERROR, + "Error, colocate buf is not enough, index is %d\n", + colocate_pic->colocated_buf_index); + ret = -6; + } + /* bit 31:30 -- L1[0] picture coding structure, + * 00 - top field, 01 - bottom field, + * 10 - frame, 11 - mbaff frame + * bit 29 - L1[0] top/bot for B field pciture, + * 0 - top, 1 - bot + * bit 28:0 h264_co_mb_mem_rd_addr[31:3] + * -- only used for B Picture Direct mode + * [2:0] will set to 3'b000 + */ + /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */ + val = ((colocate_rd_adr+colocate_adr_offset) >> 3) | + (l10_structure << 30) | + (cur_colocate_ref_type << 29); + WRITE_VREG(H264_CO_MB_RD_ADDR, val); + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "co idx %d, WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, addr %x L1(0) pic_structure %d mbaff %d\n", + colocate_pic->colocated_buf_index, + val, colocate_rd_adr + colocate_adr_offset, + colocate_pic->structure, + colocate_pic->mb_aff_frame_flag); + } else { + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR, + "Error, reference pic has no colocated buf\n"); + ret = -7; + } +#else + colocate_buf_index = + hw->buffer_spec[colocate_pic->buf_spec_num].canvas_pos; + colocate_rd_adr = p_H264_Dpb->colocated_mv_addr_start + + ((p_H264_Dpb->colocated_buf_size * + colocate_buf_index) + >> (use_direct_8x8 ? 2 : 0)); + if ((colocate_rd_adr + p_H264_Dpb->colocated_buf_size) > + p_H264_Dpb->colocated_mv_addr_end) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR, + "Error, colocate buf is not enough, col buf index is %d\n", + colocate_buf_index); + ret = -8; + } + /* bit 31:30 -- L1[0] picture coding structure, + * 00 - top field, 01 - bottom field, + * 10 - frame, 11 - mbaff frame + * bit 29 - L1[0] top/bot for B field pciture, + * 0 - top, 1 - bot + * bit 28:0 h264_co_mb_mem_rd_addr[31:3] + * -- only used for B Picture Direct mode + * [2:0] will set to 3'b000 + */ + /* #define H264_CO_MB_RD_ADDR VLD_C39 0xc39 */ + val = ((colocate_rd_adr+colocate_adr_offset)>>3) | + (l10_structure << 30) | (cur_colocate_ref_type << 29); + WRITE_VREG(H264_CO_MB_RD_ADDR, val); + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "WRITE_VREG(H264_CO_MB_RD_ADDR) = %x, L1(0) pic_structure %d mbaff %d\n", + val, colocate_pic->structure, + colocate_pic->mb_aff_frame_flag); +#endif + } + return ret; +} + +static int vh264_vf_states(struct vframe_states *states, void *op_arg) +{ + unsigned long flags; + struct vdec_s *vdec = op_arg; + struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private; + + spin_lock_irqsave(&hw->lock, flags); + + states->vf_pool_size = VF_POOL_SIZE; + states->buf_free_num = kfifo_len(&hw->newframe_q); + states->buf_avail_num = kfifo_len(&hw->display_q); + + spin_unlock_irqrestore(&hw->lock, flags); + + return 0; +} + +static struct vframe_s *vh264_vf_peek(void *op_arg) +{ + struct vframe_s *vf[2] = {0, 0}; + struct vdec_s *vdec = op_arg; + struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private; + + if (!hw) + return NULL; + + if (force_disp_bufspec_num & 0x100) { + if (force_disp_bufspec_num & 0x200) + return NULL; + return &hw->vframe_dummy; + } + + if (kfifo_out_peek(&hw->display_q, (void *)&vf, 2)) { + if (vf[1]) { + vf[0]->next_vf_pts_valid = true; + vf[0]->next_vf_pts = vf[1]->pts; + } else + vf[0]->next_vf_pts_valid = false; + return vf[0]; + } + + return NULL; +} + +static struct vframe_s *vh264_vf_get(void *op_arg) +{ + struct vframe_s *vf; + struct vdec_s *vdec = op_arg; + struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private; + + if (!hw) + return NULL; + + if (force_disp_bufspec_num & 0x100) { + int buffer_index = force_disp_bufspec_num & 0xff; + if (force_disp_bufspec_num & 0x200) + return NULL; + + vf = &hw->vframe_dummy; + vf->duration_pulldown = 0; + vf->pts = 0; + vf->pts_us64 = 0; + set_frame_info(hw, vf, buffer_index); + vf->flag = 0; + if (hw->mmu_enable) { + if (hw->double_write_mode & 0x10) { + /* double write only */ + vf->compBodyAddr = 0; + vf->compHeadAddr = 0; + } else { + /*head adr*/ + vf->compHeadAddr = + hw->buffer_spec[buffer_index].alloc_header_addr; + /*body adr*/ + vf->compBodyAddr = 0; + vf->canvas0Addr = vf->canvas1Addr = 0; + } + + vf->type = VIDTYPE_SCATTER; + + if (hw->double_write_mode) { + vf->type |= VIDTYPE_PROGRESSIVE + | VIDTYPE_VIU_FIELD; + vf->type |= VIDTYPE_VIU_NV21; + if (hw->double_write_mode == 3) + vf->type |= VIDTYPE_COMPRESS; + + vf->canvas0Addr = vf->canvas1Addr = -1; + vf->plane_num = 2; + vf->canvas0_config[0] = + hw->buffer_spec[buffer_index]. + canvas_config[0]; + vf->canvas0_config[1] = + hw->buffer_spec[buffer_index]. + canvas_config[1]; + + vf->canvas1_config[0] = + hw->buffer_spec[buffer_index]. + canvas_config[0]; + vf->canvas1_config[1] = + hw->buffer_spec[buffer_index]. + canvas_config[1]; + } else { + vf->type |= + VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD; + vf->canvas0Addr = vf->canvas1Addr = 0; + } + vf->bitdepth = + BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8; + + vf->compWidth = hw->frame_width; + vf->compHeight = hw->frame_height; + + if (hw->double_write_mode) { + vf->width = hw->frame_width / + get_double_write_ratio(hw); + vf->height = hw->frame_height / + get_double_write_ratio(hw); + } + } else { + vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD | + VIDTYPE_VIU_NV21; + vf->canvas0Addr = vf->canvas1Addr = + spec2canvas(&hw->buffer_spec[buffer_index]); + } + + /*vf->mem_handle = decoder_bmmu_box_get_mem_handle( + hw->bmmu_box, buffer_index);*/ + update_vf_memhandle(hw, vf, buffer_index); + force_disp_bufspec_num |= 0x200; + return vf; + } + + if (kfifo_get(&hw->display_q, &vf)) { + int time = jiffies; + unsigned int frame_interval = + 1000*(time - hw->last_frame_time)/HZ; + struct vframe_s *next_vf; + if (dpb_is_debug(DECODE_ID(hw), + PRINT_FLAG_VDEC_DETAIL)) { + struct h264_dpb_stru *p_H264_Dpb = &hw->dpb; + int frame_index = FRAME_INDEX(vf->index); + if (frame_index < 0 || + frame_index >= DPB_SIZE_MAX) { + dpb_print(DECODE_ID(hw), 0, + "%s vf index 0x%x error\r\n", + __func__, vf->index); + } else { + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL, + "%s buf_spec_num %d vf %p poc %d dur %d pts %d interval %dms\n", + __func__, BUFSPEC_INDEX(vf->index), vf, + p_H264_Dpb->mFrameStore[frame_index].poc, + vf->duration, vf->pts, frame_interval); + } + } + if (hw->last_frame_time > 0) { + if (frame_interval > + max_get_frame_interval[DECODE_ID(hw)]) + max_get_frame_interval[DECODE_ID(hw)] + = frame_interval; + } + hw->last_frame_time = time; + hw->vf_get_count++; + if (kfifo_peek(&hw->display_q, &next_vf)) { + vf->next_vf_pts_valid = true; + vf->next_vf_pts = next_vf->pts; + } else + vf->next_vf_pts_valid = false; + return vf; + } + + return NULL; +} + +static void vh264_vf_put(struct vframe_s *vf, void *op_arg) +{ + struct vdec_s *vdec = op_arg; + struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private; + int buf_spec_num; + int frame_index; + if (vf == (&hw->vframe_dummy)) + return; + if (vf->index == -1) { + dpb_print(DECODE_ID(hw), 0, + "Warning: %s vf %p invalid index\r\n", + __func__, vf); + return; + } + frame_index = FRAME_INDEX(vf->index); + buf_spec_num = BUFSPEC_INDEX(vf->index); + if (frame_index < 0 || + frame_index >= DPB_SIZE_MAX || + buf_spec_num < 0 || + buf_spec_num >= BUFSPEC_POOL_SIZE) { + dpb_print(DECODE_ID(hw), 0, + "%s vf index 0x%x error\r\n", + __func__, vf->index); + return; + } + /*get_buf_spec_idx_by_canvas_config(hw, + &vf->canvas0_config[0]);*/ + if (hw->buffer_spec[buf_spec_num].used == 2) { + struct h264_dpb_stru *p_H264_Dpb = &hw->dpb; + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS, + "%s %p to fs[%d], poc %d buf_spec_num %d used %d vf_ref %d\n", + __func__, vf, frame_index, + p_H264_Dpb->mFrameStore[frame_index].poc, + buf_spec_num, + hw->buffer_spec[buf_spec_num].used, + hw->buffer_spec[buf_spec_num].vf_ref); + hw->buffer_spec[buf_spec_num].vf_ref--; + if (hw->buffer_spec[buf_spec_num].vf_ref <= 0) + set_frame_output_flag(&hw->dpb, frame_index); + } else { + unsigned long flags; + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS, + "%s %p isolated vf, buf_spec_num %d used %d vf_ref %d\n", + __func__, vf, buf_spec_num, + hw->buffer_spec[buf_spec_num].used, + hw->buffer_spec[buf_spec_num].vf_ref); + spin_lock_irqsave(&hw->bufspec_lock, flags); + hw->buffer_spec[buf_spec_num].vf_ref--; + if (hw->buffer_spec[buf_spec_num].vf_ref <= 0) { + if (hw->buffer_spec[buf_spec_num].used == 3) + hw->buffer_spec[buf_spec_num].used = 4; + else if (hw->buffer_spec[buf_spec_num].used == 5) + hw->buffer_spec[buf_spec_num].used = 0; + } + spin_unlock_irqrestore(&hw->bufspec_lock, flags); + if (dpb_is_debug(DECODE_ID(hw), + PRINT_FLAG_DUMP_BUFSPEC)) + dump_bufspec(hw, __func__); + + } + + hw->vf_put_count++; + kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf); + +#define ASSIST_MBOX1_IRQ_REG VDEC_ASSIST_MBOX1_IRQ_REG + if (hw->buffer_empty_flag) + WRITE_VREG(ASSIST_MBOX1_IRQ_REG, 0x1); +} + +static int vh264_event_cb(int type, void *data, void *op_arg) +{ + unsigned long flags; + struct vdec_s *vdec = op_arg; + struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private; + + if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) { + struct provider_aux_req_s *req = + (struct provider_aux_req_s *)data; + int buf_spec_num = BUFSPEC_INDEX(req->vf->index); + spin_lock_irqsave(&hw->lock, flags); + req->aux_buf = NULL; + req->aux_size = 0; + if (buf_spec_num >= 0 && + buf_spec_num < BUFSPEC_POOL_SIZE && + is_buf_spec_in_disp_q(hw, buf_spec_num) + ) { + req->aux_buf = + hw->buffer_spec[buf_spec_num].aux_data_buf; + req->aux_size = + hw->buffer_spec[buf_spec_num].aux_data_size; +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + req->dv_enhance_exist = + hw->buffer_spec[buf_spec_num].dv_enhance_exist; +#else + req->dv_enhance_exist = 0; +#endif + } + spin_unlock_irqrestore(&hw->lock, flags); + + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS, + "%s(type 0x%x vf buf_spec_num 0x%x)=>size 0x%x\n", + __func__, type, buf_spec_num, req->aux_size); + } + + return 0; +} + +static void set_frame_info(struct vdec_h264_hw_s *hw, struct vframe_s *vf, + u32 index) +{ + int force_rate = input_frame_based(hw_to_vdec(hw)) ? + force_rate_framebase : force_rate_streambase; + dpb_print(DECODE_ID(hw), PRINT_FLAG_DPB_DETAIL, + "%s (%d,%d) dur %d, vf %p, index %d\n", __func__, + hw->frame_width, hw->frame_height, hw->frame_dur, vf, index); + + vf->width = hw->frame_width; + vf->height = hw->frame_height; + if (force_rate) { + if (force_rate == -1) + vf->duration = 0; + else + vf->duration = 96000/force_rate; + } else + vf->duration = hw->frame_dur; + vf->ratio_control = + (min(hw->h264_ar, (u32) DISP_RATIO_ASPECT_RATIO_MAX)) << + DISP_RATIO_ASPECT_RATIO_BIT; + vf->orientation = hw->vh264_rotation; + if (hw->mmu_enable) + return; + vf->canvas0Addr = vf->canvas1Addr = -1; +#ifdef NV21 + vf->plane_num = 2; +#else + vf->plane_num = 3; +#endif + vf->canvas0_config[0] = hw->buffer_spec[index].canvas_config[0]; + vf->canvas0_config[1] = hw->buffer_spec[index].canvas_config[1]; +#ifndef NV21 + vf->canvas0_config[2] = hw->buffer_spec[index].canvas_config[2]; +#endif + vf->canvas1_config[0] = hw->buffer_spec[index].canvas_config[0]; + vf->canvas1_config[1] = hw->buffer_spec[index].canvas_config[1]; +#ifndef NV21 + vf->canvas1_config[2] = hw->buffer_spec[index].canvas_config[2]; +#endif +} + +static int get_max_dec_frame_buf_size(int level_idc, + int max_reference_frame_num, int mb_width, + int mb_height) +{ + int pic_size = mb_width * mb_height * 384; + + int size = 0; + + switch (level_idc) { + case 9: + size = 152064; + break; + case 10: + size = 152064; + break; + case 11: + size = 345600; + break; + case 12: + size = 912384; + break; + case 13: + size = 912384; + break; + case 20: + size = 912384; + break; + case 21: + size = 1824768; + break; + case 22: + size = 3110400; + break; + case 30: + size = 3110400; + break; + case 31: + size = 6912000; + break; + case 32: + size = 7864320; + break; + case 40: + size = 12582912; + break; + case 41: + size = 12582912; + break; + case 42: + size = 13369344; + break; + case 50: + size = 42393600; + break; + case 51: + case 52: + default: + size = 70778880; + break; + } + + size /= pic_size; + size = size + 1; /* need one more buffer */ + + if (max_reference_frame_num > size) + size = max_reference_frame_num; + + return size; +} + +static void vh264_config_canvs_for_mmu(struct vdec_h264_hw_s *hw) +{ + int i, j; + + if (hw->double_write_mode) { + mutex_lock(&vmh264_mutex); + if (hw->decode_pic_count == 0) { + for (j = 0; j < hw->dpb.mDPB.size; j++) { + i = get_buf_spec_by_canvas_pos(hw, j); + config_decode_canvas_ex(hw, i); + } + } + mutex_unlock(&vmh264_mutex); + } +} + +static int vh264_set_params(struct vdec_h264_hw_s *hw, + u32 param1, u32 param2, u32 param3, u32 param4) +{ + int i, j; + int mb_width, mb_total; + int max_reference_size, level_idc; + int mb_height; + unsigned long flags; + /*int mb_mv_byte;*/ + struct vdec_s *vdec = hw_to_vdec(hw); + u32 seq_info2; + int ret = 0; + int active_buffer_spec_num; + unsigned int buf_size; + unsigned int frame_mbs_only_flag; + unsigned int chroma_format_idc, chroma444; + unsigned int crop_infor, crop_bottom, crop_right; + unsigned int used_reorder_dpb_size_margin + = reorder_dpb_size_margin; +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + if (vdec->master || vdec->slave) + used_reorder_dpb_size_margin = + reorder_dpb_size_margin_dv; +#endif + seq_info2 = param1; + hw->seq_info = param2; + + mb_width = seq_info2 & 0xff; + mb_total = (seq_info2 >> 8) & 0xffff; + if (!mb_width && mb_total) /*for 4k2k*/ + mb_width = 256; + mb_height = mb_total/mb_width; + if (mb_width > 0x110 || + mb_height > 0xa0 || + mb_width <= 0 || + mb_height <= 0) { + dpb_print(DECODE_ID(hw), 0, + "!!!wrong seq_info2 0x%x mb_width/mb_height (0x%x/0x%x) %x\r\n", + seq_info2, + mb_width, + mb_height); + WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) | + (hw->dpb.mDPB.size<<16) | + (hw->dpb.mDPB.size<<8)); + return 0; + } + + if (seq_info2 != 0 && + hw->seq_info2 != (seq_info2 & (~0x80000000)) && + hw->seq_info2 != 0 + ) /*picture size changed*/ + h264_reconfig(hw); + + if (hw->config_bufmgr_done == 0) { + struct h264_dpb_stru *p_H264_Dpb = &hw->dpb; + u32 reg_val; + hw->cfg_param1 = param1; + hw->cfg_param2 = param2; + hw->cfg_param3 = param3; + hw->cfg_param4 = param4; + + hw->seq_info2 = seq_info2 & (~0x80000000); + dpb_print(DECODE_ID(hw), 0, + "AV_SCRATCH_1 = %x, AV_SCRATCH_2 %x\r\n", + seq_info2, hw->seq_info); + + dpb_init_global(&hw->dpb, + DECODE_ID(hw), 0, 0); + + p_H264_Dpb->fast_output_enable = fast_output_enable; + /*mb_mv_byte = (seq_info2 & 0x80000000) ? 24 : 96;*/ + +#if 1 + /*crop*/ + /* AV_SCRATCH_2 + bit 15: frame_mbs_only_flag + bit 13-14: chroma_format_idc */ + frame_mbs_only_flag = (hw->seq_info >> 15) & 0x01; + chroma_format_idc = (hw->seq_info >> 13) & 0x03; + chroma444 = (chroma_format_idc == 3) ? 1 : 0; + + /* @AV_SCRATCH_6.31-16 = (left << 8 | right ) << 1 + @AV_SCRATCH_6.15-0 = (top << 8 | bottom ) << + (2 - frame_mbs_only_flag) */ + crop_infor = param3; + crop_bottom = (crop_infor & 0xff) >> (2 - frame_mbs_only_flag); + crop_right = ((crop_infor >> 16) & 0xff) + >> (2 - frame_mbs_only_flag); + + p_H264_Dpb->mSPS.frame_mbs_only_flag = frame_mbs_only_flag; + hw->frame_width = mb_width << 4; + hw->frame_height = mb_height << 4; + if (frame_mbs_only_flag) { + hw->frame_height = + hw->frame_height - (2 >> chroma444) * + min(crop_bottom, + (unsigned int)((8 << chroma444) - 1)); + hw->frame_width = + hw->frame_width - + (2 >> chroma444) * min(crop_right, + (unsigned + int)((8 << chroma444) - 1)); + } else { + hw->frame_height = + hw->frame_height - (4 >> chroma444) * + min(crop_bottom, + (unsigned int)((8 << chroma444) + - 1)); + hw->frame_width = + hw->frame_width - + (4 >> chroma444) * min(crop_right, + (unsigned int)((8 << chroma444) - 1)); + } + dpb_print(DECODE_ID(hw), 0, + "frame_mbs_only_flag %d, crop_bottom %d, frame_height %d, ", + frame_mbs_only_flag, crop_bottom, hw->frame_height); + dpb_print(DECODE_ID(hw), 0, + "mb_height %d,crop_right %d, frame_width %d, mb_width %d\n", + mb_height, crop_right, + hw->frame_width, mb_width); + + if (hw->frame_height == 1088) + hw->frame_height = 1080; +#endif + + mb_width = (mb_width+3) & 0xfffffffc; + mb_height = (mb_height+3) & 0xfffffffc; + mb_total = mb_width * mb_height; + if (hw->mmu_enable) + hevc_mcr_sao_global_hw_init(hw, + hw->frame_width, hw->frame_height); + + reg_val = param4; + level_idc = reg_val & 0xff; + max_reference_size = (reg_val >> 8) & 0xff; + dpb_print(DECODE_ID(hw), 0, + "mb height/widht/total: %x/%x/%x level_idc %x max_ref_num %x\n", + mb_height, mb_width, mb_total, + level_idc, max_reference_size); + + p_H264_Dpb->colocated_buf_size = mb_total * 96; + hw->mb_total = mb_total; + hw->mb_width = mb_width; + hw->mb_height = mb_height; + + hw->dpb.reorder_pic_num = + get_max_dec_frame_buf_size(level_idc, + max_reference_size, mb_width, mb_height); + active_buffer_spec_num = + hw->dpb.reorder_pic_num + + used_reorder_dpb_size_margin; + hw->max_reference_size = + max_reference_size + reference_buf_margin; + + if (active_buffer_spec_num > MAX_VF_BUF_NUM) { + active_buffer_spec_num = MAX_VF_BUF_NUM; + hw->dpb.reorder_pic_num = active_buffer_spec_num + - used_reorder_dpb_size_margin; + } + hw->dpb.mDPB.size = active_buffer_spec_num; + if (hw->max_reference_size > MAX_VF_BUF_NUM) + hw->max_reference_size = MAX_VF_BUF_NUM; + hw->dpb.max_reference_size = hw->max_reference_size; + + if (hw->no_poc_reorder_flag) + hw->dpb.reorder_pic_num = 1; + dpb_print(DECODE_ID(hw), 0, + "%s active_buf_spec_num %d reorder_pic_num %d collocate_buf_num %d\r\n", + __func__, active_buffer_spec_num, + hw->dpb.reorder_pic_num, + hw->max_reference_size); + + buf_size = (hw->mb_total << 8) + (hw->mb_total << 7); + + mutex_lock(&vmh264_mutex); + if (!hw->mmu_enable) { + config_buf_specs(vdec); + i = get_buf_spec_by_canvas_pos(hw, 0); + if (alloc_one_buf_spec(hw, i) >= 0) + config_decode_canvas(hw, i); + else + ret = -1; + } else { + if (hw->double_write_mode) { + config_buf_specs_ex(vdec); + } else { + spin_lock_irqsave(&hw->bufspec_lock, flags); + for (i = 0, j = 0; + j < active_buffer_spec_num + && i < BUFSPEC_POOL_SIZE; + i++) { + if (hw->buffer_spec[i].used != -1) + continue; + hw->buffer_spec[i].used = 0; + hw->buffer_spec[i]. + alloc_header_addr = 0; + hw->buffer_spec[i].canvas_pos = j; + j++; + } + spin_unlock_irqrestore(&hw->bufspec_lock, + flags); + } + hevc_mcr_config_canv2axitbl(hw, 0); + } + mutex_unlock(&vmh264_mutex); + if (dpb_is_debug(DECODE_ID(hw), + PRINT_FLAG_DUMP_BUFSPEC)) + dump_bufspec(hw, __func__); + +#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF + buf_size = PAGE_ALIGN( + p_H264_Dpb->colocated_buf_size * + active_buffer_spec_num); +#else + buf_size = PAGE_ALIGN( + p_H264_Dpb->colocated_buf_size * + hw->max_reference_size); +#endif + + if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_REF_IDX, + buf_size, DRIVER_NAME, + &hw->collocate_cma_alloc_addr) < 0) + return -1; + + hw->dpb.colocated_mv_addr_start = + hw->collocate_cma_alloc_addr; +#ifdef ONE_COLOCATE_BUF_PER_DECODE_BUF + hw->dpb.colocated_mv_addr_end = + hw->dpb.colocated_mv_addr_start + + (p_H264_Dpb->colocated_buf_size * + active_buffer_spec_num); +#else + hw->dpb.colocated_mv_addr_end = + hw->dpb.colocated_mv_addr_start + + (p_H264_Dpb->colocated_buf_size * + hw->max_reference_size); +#endif + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "callocate cma, %lx, %x\n", + hw->collocate_cma_alloc_addr, + hw->dpb.colocated_mv_addr_start); + + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "colocated_mv_addr_start %x colocated_mv_addr_end %x\n", + hw->dpb.colocated_mv_addr_start, + hw->dpb.colocated_mv_addr_end); + if (!hw->mmu_enable) { + mutex_lock(&vmh264_mutex); + if (ret >= 0 && hw->decode_pic_count == 0) { + /* h264_reconfig: alloc later*/ + for (j = 1; j < hw->dpb.mDPB.size; j++) { + i = get_buf_spec_by_canvas_pos(hw, j); + if (alloc_one_buf_spec(hw, i) < 0) + break; + config_decode_canvas(hw, i); + } + } + mutex_unlock(&vmh264_mutex); + } else { + vh264_config_canvs_for_mmu(hw); + } + + hw->config_bufmgr_done = 1; + + /*end of config_bufmgr_done */ + } + + return ret; +} + +static void vui_config(struct vdec_h264_hw_s *hw) +{ + struct h264_dpb_stru *p_H264_Dpb = &hw->dpb; + int aspect_ratio_info_present_flag, aspect_ratio_idc; + /*time*/ + hw->num_units_in_tick = p_H264_Dpb->num_units_in_tick; + hw->time_scale = p_H264_Dpb->time_scale; + hw->timing_info_present_flag = p_H264_Dpb->vui_status & 0x2; + + hw->fixed_frame_rate_flag = 0; + if (hw->timing_info_present_flag) { + hw->fixed_frame_rate_flag = + p_H264_Dpb->fixed_frame_rate_flag; + + if (((hw->num_units_in_tick * 120) >= hw->time_scale && + ((!hw->sync_outside) || + (!hw->frame_dur))) + && hw->num_units_in_tick && hw->time_scale) { + if (hw->use_idr_framerate || + hw->fixed_frame_rate_flag || + !hw->frame_dur || + !hw->duration_from_pts_done + /*|| vh264_running*/) { + u32 frame_dur_es = + div_u64(96000ULL * 2 * hw->num_units_in_tick, + hw->time_scale); + if (hw->frame_dur != frame_dur_es) { + hw->h264_first_valid_pts_ready = false; + hw->h264pts1 = 0; + hw->h264pts2 = 0; + hw->h264_pts_count = 0; + hw->duration_from_pts_done = 0; + fixed_frame_rate_mode = + FIX_FRAME_RATE_OFF; + hw->pts_duration = 0; + hw->frame_dur = frame_dur_es; + schedule_work(&hw->notify_work); + dpb_print(DECODE_ID(hw), + PRINT_FLAG_DEC_DETAIL, + "frame_dur %d from timing_info\n", + hw->frame_dur); + } + + /*hack to avoid use ES frame duration when + *it's half of the rate from system info + * sometimes the encoder is given a wrong + * frame rate but the system side information + * is more reliable + *if ((frame_dur * 2) != frame_dur_es) { + * frame_dur = frame_dur_es; + *} + */ + } + } + } else { + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "H.264: timing_info not present\n"); + } + + /*aspect ratio*/ + aspect_ratio_info_present_flag = + p_H264_Dpb->vui_status & 0x1; + aspect_ratio_idc = p_H264_Dpb->aspect_ratio_idc; + + if (aspect_ratio_info_present_flag) { + if (aspect_ratio_idc == EXTEND_SAR) { + hw->h264_ar = + div_u64(256ULL * + p_H264_Dpb->aspect_ratio_sar_height * + hw->frame_height, + p_H264_Dpb->aspect_ratio_sar_width * + hw->frame_width); + } else { + /* pr_info("v264dec: aspect_ratio_idc = %d\n", + aspect_ratio_idc); */ + + switch (aspect_ratio_idc) { + case 1: + hw->h264_ar = 0x100 * hw->frame_height / + hw->frame_width; + break; + case 2: + hw->h264_ar = 0x100 * hw->frame_height * 11 / + (hw->frame_width * 12); + break; + case 3: + hw->h264_ar = 0x100 * hw->frame_height * 11 / + (hw->frame_width * 10); + break; + case 4: + hw->h264_ar = 0x100 * hw->frame_height * 11 / + (hw->frame_width * 16); + break; + case 5: + hw->h264_ar = 0x100 * hw->frame_height * 33 / + (hw->frame_width * 40); + break; + case 6: + hw->h264_ar = 0x100 * hw->frame_height * 11 / + (hw->frame_width * 24); + break; + case 7: + hw->h264_ar = 0x100 * hw->frame_height * 11 / + (hw->frame_width * 20); + break; + case 8: + hw->h264_ar = 0x100 * hw->frame_height * 11 / + (hw->frame_width * 32); + break; + case 9: + hw->h264_ar = 0x100 * hw->frame_height * 33 / + (hw->frame_width * 80); + break; + case 10: + hw->h264_ar = 0x100 * hw->frame_height * 11 / + (hw->frame_width * 18); + break; + case 11: + hw->h264_ar = 0x100 * hw->frame_height * 11 / + (hw->frame_width * 15); + break; + case 12: + hw->h264_ar = 0x100 * hw->frame_height * 33 / + (hw->frame_width * 64); + break; + case 13: + hw->h264_ar = 0x100 * hw->frame_height * 99 / + (hw->frame_width * 160); + break; + case 14: + hw->h264_ar = 0x100 * hw->frame_height * 3 / + (hw->frame_width * 4); + break; + case 15: + hw->h264_ar = 0x100 * hw->frame_height * 2 / + (hw->frame_width * 3); + break; + case 16: + hw->h264_ar = 0x100 * hw->frame_height * 1 / + (hw->frame_width * 2); + break; + default: + if (hw->vh264_ratio >> 16) { + hw->h264_ar = (hw->frame_height * + (hw->vh264_ratio & 0xffff) * + 0x100 + + ((hw->vh264_ratio >> 16) * + hw->frame_width / 2)) / + ((hw->vh264_ratio >> 16) * + hw->frame_width); + } else { + hw->h264_ar = hw->frame_height * 0x100 / + hw->frame_width; + } + break; + } + } + } else { + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "v264dec: aspect_ratio not available from source\n"); + if (hw->vh264_ratio >> 16) { + /* high 16 bit is width, low 16 bit is height */ + hw->h264_ar = + ((hw->vh264_ratio & 0xffff) * + hw->frame_height * 0x100 + + (hw->vh264_ratio >> 16) * + hw->frame_width / 2) / + ((hw->vh264_ratio >> 16) * + hw->frame_width); + } else + hw->h264_ar = hw->frame_height * 0x100 / + hw->frame_width; + } + + if (hw->pts_unstable && (hw->fixed_frame_rate_flag == 0)) { + if (((hw->frame_dur == RATE_2397_FPS) + && (dec_control + & DEC_CONTROL_FLAG_FORCE_RATE_2397_FPS_FIX_FRAME_RATE)) + || ((RATE_2997_FPS == + hw->frame_dur) && + (dec_control & + DEC_CONTROL_FLAG_FORCE_RATE_2997_FPS_FIX_FRAME_RATE))) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_DEC_DETAIL, + "force fix frame rate\n"); + hw->fixed_frame_rate_flag = 0x40; + } + } + + /*video_signal_from_vui: to do .. */ +} + +static void bufmgr_recover(struct vdec_h264_hw_s *hw) +{ + struct h264_dpb_stru *p_H264_Dpb = &hw->dpb; + bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2); + if (error_proc_policy & 0x20) + hw->reset_bufmgr_flag = 1; +} + +void bufmgr_force_recover(struct h264_dpb_stru *p_H264_Dpb) +{ + struct vdec_h264_hw_s *hw = + container_of(p_H264_Dpb, struct vdec_h264_hw_s, dpb); + + dpb_print(DECODE_ID(hw), 0, "call %s\n", __func__); + + bufmgr_h264_remove_unused_frame(p_H264_Dpb, 2); + hw->reset_bufmgr_flag = 1; +} + +static bool is_buffer_available(struct vdec_s *vdec) +{ + bool buffer_available = 1; + struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private); + struct h264_dpb_stru *p_H264_Dpb = &hw->dpb; + struct DecodedPictureBuffer *p_Dpb = &p_H264_Dpb->mDPB; + if ((kfifo_len(&hw->newframe_q) <= 0) || + ((hw->config_bufmgr_done) && (!have_free_buf_spec(vdec))) || + ((p_H264_Dpb->mDPB.init_done) && + (p_H264_Dpb->mDPB.used_size == p_H264_Dpb->mDPB.size) && + (is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB) == 0))) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL, + "%s, empty, newq(%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d)\n", + __func__, + kfifo_len(&hw->newframe_q), + have_free_buf_spec(vdec), + p_H264_Dpb->mDPB.init_done, + p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size, + is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB) + ); + buffer_available = 0; + if (dpb_is_debug(DECODE_ID(hw), + DEBUG_DISABLE_RUNREADY_RMBUF)) + return buffer_available; + + if ((error_proc_policy & 0x4) && + (error_proc_policy & 0x8)) { + if ((kfifo_len(&hw->display_q) <= 0) && + (p_H264_Dpb->mDPB.used_size == + p_H264_Dpb->mDPB.size) && + (p_Dpb->ref_frames_in_buffer > + (imax( + 1, p_Dpb->num_ref_frames) + - p_Dpb->ltref_frames_in_buffer + + force_sliding_margin))) + bufmgr_recover(hw); + else + bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1); + } else if ((error_proc_policy & 0x4) && + (kfifo_len(&hw->display_q) <= 0) && + ((p_H264_Dpb->mDPB.used_size == + p_H264_Dpb->mDPB.size) || + (!have_free_buf_spec(vdec)))) { + enum receviver_start_e state = RECEIVER_INACTIVE; + if ((error_proc_policy & 0x10) && + vf_get_receiver(vdec->vf_provider_name)) { + state = + vf_notify_receiver(vdec->vf_provider_name, + VFRAME_EVENT_PROVIDER_QUREY_STATE, + NULL); + if ((state == RECEIVER_STATE_NULL) + || (state == RECEIVER_STATE_NONE)) + state = RECEIVER_INACTIVE; + } + if (state == RECEIVER_INACTIVE) + bufmgr_recover(hw); + else + bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1); + } else if ((error_proc_policy & 0x8) && + (p_Dpb->ref_frames_in_buffer > + (imax( + 1, p_Dpb->num_ref_frames) + - p_Dpb->ltref_frames_in_buffer + + force_sliding_margin))) + bufmgr_recover(hw); + else + bufmgr_h264_remove_unused_frame(p_H264_Dpb, 1); + + if (hw->reset_bufmgr_flag == 1) + buffer_available = 1; + } + + return buffer_available; +} + +static void check_decoded_pic_error(struct vdec_h264_hw_s *hw) +{ + struct h264_dpb_stru *p_H264_Dpb = &hw->dpb; + struct StorablePicture *p = p_H264_Dpb->mVideo.dec_picture; + unsigned mby_mbx = READ_VREG(MBY_MBX); + unsigned mb_total = (hw->seq_info2 >> 8) & 0xffff; + unsigned decode_mb_count = + (((mby_mbx & 0xff) + 1) * + (((mby_mbx >> 8) & 0xff) + 1)); + if (mby_mbx == 0) + return; + if (get_cur_slice_picture_struct(p_H264_Dpb) != FRAME) + mb_total /= 2; + if (error_proc_policy & 0x100) { + if (decode_mb_count != mb_total) + p->data_flag |= ERROR_FLAG; + else if (p->data_flag & MAYBE_ERROR_FLAG) + p->data_flag &= ~ERROR_FLAG; + p->data_flag &= ~MAYBE_ERROR_FLAG; + } + + if ((error_proc_policy & 0x200) && + READ_VREG(ERROR_STATUS_REG) != 0) { + p->data_flag |= ERROR_FLAG; + } + + if (p->data_flag & ERROR_FLAG) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERRORFLAG_DBG, + "%s: decode error, seq_info2 0x%x, mby_mbx 0x%x, mb_total %d decoded mb_count %d ERROR_STATUS_REG 0x%x\n", + __func__, + hw->seq_info2, + mby_mbx, + mb_total, + decode_mb_count, + READ_VREG(ERROR_STATUS_REG) + ); + + } +} + +static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw, + int frame_type, + u32 vpts, + u32 vpts_valid); + +static irqreturn_t vh264_isr_thread_fn(struct vdec_s *vdec, int irq) +{ + int i; + struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private); + struct h264_dpb_stru *p_H264_Dpb = &hw->dpb; + unsigned int dec_dpb_status = p_H264_Dpb->dec_dpb_status; + u32 debug_tag; + int ret; + + if (dec_dpb_status == H264_CONFIG_REQUEST) { + WRITE_VREG(DPB_STATUS_REG, H264_ACTION_CONFIG_DONE); + reset_process_time(hw); + hw->dec_result = DEC_RESULT_CONFIG_PARAM; + vdec_schedule_work(&hw->work); + } else if (dec_dpb_status == H264_SLICE_HEAD_DONE) { + int slice_header_process_status = 0; + /*unsigned char is_idr;*/ + unsigned short *p = (unsigned short *)hw->lmem_addr; + reset_process_time(hw); + + hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL); + hw->reg_vcop_ctrl_reg = READ_VREG(VCOP_CTRL_REG); + hw->reg_rv_ai_mb_count = READ_VREG(RV_AI_MB_COUNT); + hw->vld_dec_control = READ_VREG(VLD_DECODE_CONTROL); + if (input_frame_based(vdec) && + frmbase_cont_bitlevel2 != 0 && + READ_VREG(VIFF_BIT_CNT) < + frmbase_cont_bitlevel2 && + hw->get_data_count >= 0x70000000) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS, + "%s H264_SLICE_HEAD_DONE with small bitcnt %d, goto empty_proc\n", + __func__, + READ_VREG(VIFF_BIT_CNT)); + + goto empty_proc; + } + + dma_sync_single_for_cpu( + amports_get_dma_device(), + hw->lmem_addr_remap, + PAGE_SIZE, + DMA_FROM_DEVICE); +#if 0 + if (p_H264_Dpb->mVideo.dec_picture == NULL) { + if (!is_buffer_available(vdec)) { + hw->buffer_empty_flag = 1; + dpb_print(DECODE_ID(hw), + PRINT_FLAG_UCODE_EVT, + "%s, buffer_empty, newframe_q(%d), have_free_buf_spec(%d), init_done(%d), used_size(%d/%d), is_there_unused_frame_from_dpb(%d)\n", + __func__, + kfifo_len(&hw->newframe_q), + have_free_buf_spec(vdec), + p_H264_Dpb->mDPB.init_done, + p_H264_Dpb->mDPB.used_size, + p_H264_Dpb->mDPB.size, + is_there_unused_frame_from_dpb( + &p_H264_Dpb->mDPB)); + return IRQ_HANDLED; + } + } + + hw->buffer_empty_flag = 0; +#endif +#ifdef SEND_PARAM_WITH_REG + for (i = 0; i < (RPM_END-RPM_BEGIN); i++) { + unsigned int data32; + + do { + data32 = READ_VREG(RPM_CMD_REG); + /* printk("%x\n", data32); */ + } while ((data32&0x10000) == 0); + p_H264_Dpb->dpb_param.l.data[i] = data32 & 0xffff; + WRITE_VREG(RPM_CMD_REG, 0); + /* printk("%x:%x\n", i,data32); */ + } +#else + for (i = 0; i < (RPM_END-RPM_BEGIN); i += 4) { + int ii; + + for (ii = 0; ii < 4; ii++) { + p_H264_Dpb->dpb_param.l.data[i+ii] = + p[i+3-ii]; + if (dpb_is_debug(DECODE_ID(hw), + RRINT_FLAG_RPM)) { + if (((i + ii) & 0xf) == 0) + dpb_print(DECODE_ID(hw), + 0, "%04x:", + i); + dpb_print_cont(DECODE_ID(hw), + 0, "%04x ", + p[i+3-ii]); + if (((i + ii + 1) & 0xf) == 0) + dpb_print_cont( + DECODE_ID(hw), + 0, "\r\n"); + } + } + } +#endif + if (hw->config_bufmgr_done == 0) { + hw->dec_result = DEC_RESULT_DONE; + vdec_schedule_work(&hw->work); + dpb_print(DECODE_ID(hw), + PRINT_FLAG_UCODE_EVT, + "config_bufmgr not done, discard frame\n"); + return IRQ_HANDLED; + } else if ((first_i_policy & 0x3) != 0) { + unsigned char is_i_slice = + (p_H264_Dpb->dpb_param.l.data[SLICE_TYPE] + == I_Slice) + ? 1 : 0; + unsigned char is_idr = + ((p_H264_Dpb->dpb_param.dpb.NAL_info_mmco & 0x1f) + == 5); + if ((first_i_policy & 0x3) == 0x3) + is_i_slice = is_idr; + if (!is_i_slice) { + if (hw->has_i_frame == 0) { + amvdec_stop(); + hw->dec_result = DEC_RESULT_DONE; + vdec_schedule_work(&hw->work); + dpb_print(DECODE_ID(hw), + PRINT_FLAG_UCODE_EVT, + "has_i_frame is 0, discard none I(DR) frame\n"); + return IRQ_HANDLED; + } + } else { + if (hw->skip_frame_count < 0 || is_idr) { + /* second I */ + hw->dec_flag &= (~NODISP_FLAG); + hw->skip_frame_count = 0; + } + if (hw->has_i_frame == 0 && + (!is_idr)) { + int skip_count = + (first_i_policy >> 8) & 0xff; + /* first I (not IDR) */ + if ((first_i_policy & 0x3) == 2) + hw->skip_frame_count = + -1 - skip_count; + else + hw->skip_frame_count = + skip_count; + if (hw->skip_frame_count != 0) + hw->dec_flag |= NODISP_FLAG; + } + } + } + dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT, + "current dpb index %d, poc %d, top/bot poc (%d,%d)\n", + p_H264_Dpb->dpb_param.dpb.current_dpb_index, + val(p_H264_Dpb->dpb_param.dpb.frame_pic_order_cnt), + val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt), + val(p_H264_Dpb->dpb_param.dpb.top_field_pic_order_cnt)); + + slice_header_process_status = + h264_slice_header_process(p_H264_Dpb); + if (hw->mmu_enable) + hevc_sao_set_slice_type(hw, + slice_header_process_status, + hw->dpb.mSlice.idr_flag); + vui_config(hw); + + if (p_H264_Dpb->mVideo.dec_picture) { + int cfg_ret = 0; + if (hw->sei_itu_data_len) { + hw->sei_poc = + p_H264_Dpb->mVideo.dec_picture->poc; + schedule_work(&hw->user_data_work); + } + if (slice_header_process_status == 1) { + /* for baseline , set fast_output mode */ + if ((p_H264_Dpb->mSPS.profile_idc == BASELINE) + || ((((unsigned long) + hw->vh264_amstream_dec_info.param) & 0x8) + && (!hw->i_only))) + p_H264_Dpb->fast_output_enable = 4; + else + p_H264_Dpb->fast_output_enable + = fast_output_enable; + hw->data_flag = + (p_H264_Dpb-> + dpb_param.l.data[SLICE_TYPE] + == I_Slice) + ? I_FLAG : 0; + if ((hw->i_only & 0x2) && + (!(hw->data_flag & I_FLAG)) && + (p_H264_Dpb->mSlice.structure + == FRAME)) { + hw->data_flag = NULL_FLAG; + goto pic_done_proc; + } + if ((p_H264_Dpb-> + dpb_param.dpb.NAL_info_mmco & 0x1f) + == 5) + hw->data_flag |= IDR_FLAG; + dpb_print(DECODE_ID(hw), + PRINT_FLAG_VDEC_STATUS, + "==================> frame count %d to skip %d\n", + hw->decode_pic_count+1, + hw->skip_frame_count); + } else { + struct StorablePicture *p = + p_H264_Dpb->mVideo.dec_picture; + unsigned mby_mbx = READ_VREG(MBY_MBX); + unsigned decode_mb_count = + (((mby_mbx & 0xff) + 1) * + (((mby_mbx >> 8) & 0xff) + 1)); + if ((error_proc_policy & 0x100) && + p_H264_Dpb->dpb_param.l. + data[FIRST_MB_IN_SLICE] + < decode_mb_count) { + dpb_print(DECODE_ID(hw), + PRINT_FLAG_VDEC_STATUS, + "Error detect! first_mb 0x%x mby_mbx 0x%x decode_mb 0x%x\n", + p_H264_Dpb->dpb_param.l. + data[FIRST_MB_IN_SLICE], + READ_VREG(MBY_MBX), + decode_mb_count); + if (!p_H264_Dpb->dpb_param.l. + data[FIRST_MB_IN_SLICE]) { + p->data_flag |= ERROR_FLAG; + goto pic_done_proc; + } else + p->data_flag |= MAYBE_ERROR_FLAG; + } + } + if (error_proc_policy & 0x400) { + int ret = dpb_check_ref_list_error(p_H264_Dpb); + if (ret != 0) { + dpb_print(DECODE_ID(hw), 0, + "reference list error %d frame count %d to skip %d\n", + ret, + hw->decode_pic_count+1, + hw->skip_frame_count); + hw->data_flag |= ERROR_FLAG; + p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG; + if ((error_proc_policy & 0x80) + && ((hw->dec_flag & + NODISP_FLAG) == 0)) { + hw->reset_bufmgr_flag = 1; + amvdec_stop(); + hw->dec_result + = DEC_RESULT_DONE; + vdec_schedule_work(&hw->work); + return IRQ_HANDLED; + } + } + } + if ((error_proc_policy & 0x800) + && p_H264_Dpb->dpb_error_flag != 0) { + dpb_print(DECODE_ID(hw), 0, + "dpb error %d\n", + p_H264_Dpb->dpb_error_flag); + hw->data_flag |= ERROR_FLAG; + p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG; + if ((error_proc_policy & 0x80) && + ((hw->dec_flag & NODISP_FLAG) == 0)) { + hw->reset_bufmgr_flag = 1; + amvdec_stop(); + hw->dec_result = DEC_RESULT_DONE; + vdec_schedule_work(&hw->work); + return IRQ_HANDLED; + } + } + + cfg_ret = config_decode_buf(hw, + p_H264_Dpb->mVideo.dec_picture); + if (cfg_ret < 0) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR, + "config_decode_buf fail (%d)\n", + cfg_ret); + if (error_proc_policy & 0x2) { + release_cur_decoding_buf(hw); + /*hw->data_flag |= ERROR_FLAG;*/ + hw->dec_result = DEC_RESULT_DONE; + vdec_schedule_work(&hw->work); + return IRQ_HANDLED; + } else + hw->data_flag |= ERROR_FLAG; + p_H264_Dpb->mVideo.dec_picture->data_flag |= ERROR_FLAG; + } + } + + if (slice_header_process_status == 1) + WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_NEWPIC); + else + WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_SLICE); + hw->last_mby_mbx = 0; + hw->last_vld_level = 0; + start_process_time(hw); + } else if (dec_dpb_status == H264_PIC_DATA_DONE) { +pic_done_proc: + reset_process_time(hw); + if (p_H264_Dpb->mVideo.dec_picture) { +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + DEL_EXIST(hw, + p_H264_Dpb->mVideo.dec_picture) = 0; + if (vdec->master) { + struct vdec_h264_hw_s *hw_ba = + (struct vdec_h264_hw_s *) + vdec->master->private; + if (hw_ba->last_dec_picture) + DEL_EXIST(hw_ba, + hw_ba->last_dec_picture) + = 1; + } +#endif + if (hw->chunk) { + p_H264_Dpb->mVideo.dec_picture->pts = + hw->chunk->pts; + p_H264_Dpb->mVideo.dec_picture->pts64 = + hw->chunk->pts64; +#ifdef MH264_USERDATA_ENABLE + vmh264_udc_fill_vpts(hw, + p_H264_Dpb->mSlice.slice_type, + hw->chunk->pts, 1); +#endif + +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + } else if (vdec->master) { + /*dv enhance layer, + do not checkout pts*/ + struct StorablePicture *pic = + p_H264_Dpb->mVideo.dec_picture; + pic->pts = 0; + pic->pts64 = 0; +#endif + } else { + struct StorablePicture *pic = + p_H264_Dpb->mVideo.dec_picture; + u32 offset = pic->offset_delimiter_lo | + (pic->offset_delimiter_hi << 16); + if (pts_lookup_offset_us64(PTS_TYPE_VIDEO, + offset, &pic->pts, 0, &pic->pts64)) { + pic->pts = 0; + pic->pts64 = 0; +#ifdef MH264_USERDATA_ENABLE + vmh264_udc_fill_vpts(hw, + p_H264_Dpb->mSlice.slice_type, + pic->pts, 0); +#endif + } else { +#ifdef MH264_USERDATA_ENABLE + vmh264_udc_fill_vpts(hw, + p_H264_Dpb->mSlice.slice_type, + pic->pts, 1); +#endif + } + } + check_decoded_pic_error(hw); +#ifdef ERROR_HANDLE_TEST + if ((hw->data_flag & ERROR_FLAG) + && (error_proc_policy & 0x80)) { + release_cur_decoding_buf(hw); + h264_clear_dpb(hw); + hw->dec_flag = 0; + hw->data_flag = 0; + hw->skip_frame_count = 0; + hw->has_i_frame = 0; + hw->no_error_count = 0xfff; + hw->no_error_i_count = 0xf; + } else +#endif + ret = store_picture_in_dpb(p_H264_Dpb, + p_H264_Dpb->mVideo.dec_picture, + hw->data_flag | hw->dec_flag | + p_H264_Dpb->mVideo.dec_picture->data_flag); + + + + if (ret == -1) { + release_cur_decoding_buf(hw); + bufmgr_force_recover(p_H264_Dpb); + } else { + if (hw->data_flag & ERROR_FLAG) { + hw->no_error_count = 0; + hw->no_error_i_count = 0; + } else { + hw->no_error_count++; + if (hw->data_flag & I_FLAG) + hw->no_error_i_count++; + } + if (hw->mmu_enable) + hevc_set_unused_4k_buff_idx(hw, + p_H264_Dpb->mVideo. + dec_picture->buf_spec_num); + bufmgr_post(p_H264_Dpb); + hw->last_dec_picture = + p_H264_Dpb->mVideo.dec_picture; + p_H264_Dpb->mVideo.dec_picture = NULL; + /* dump_dpb(&p_H264_Dpb->mDPB); */ + hw->has_i_frame = 1; + if (hw->mmu_enable) + hevc_set_frame_done(hw); + hw->decode_pic_count++; + p_H264_Dpb->decode_pic_count = hw->decode_pic_count; + if (hw->skip_frame_count > 0) { + /*skip n frame after first I */ + hw->skip_frame_count--; + if (hw->skip_frame_count == 0) + hw->dec_flag &= (~NODISP_FLAG); + } else if (hw->skip_frame_count < -1) { + /*skip n frame after first I until second I */ + hw->skip_frame_count++; + if (hw->skip_frame_count == -1) + hw->dec_flag &= (~NODISP_FLAG); + } + } + } + if (input_frame_based(vdec) && + frmbase_cont_bitlevel != 0 && + READ_VREG(VIFF_BIT_CNT) > + frmbase_cont_bitlevel) { + /*handle the case: multi pictures in one packet*/ + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS, + "%s H264_PIC_DATA_DONE decode slice count %d, continue (bitcnt 0x%x)\n", + __func__, + hw->decode_pic_count, + READ_VREG(VIFF_BIT_CNT)); + /*do not DEC_RESULT_GET_DATA*/ + hw->get_data_count = 0x7fffffff; + WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); + decode_frame_count[DECODE_ID(hw)]++; + start_process_time(hw); + return IRQ_HANDLED; + } + amvdec_stop(); + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS, + "%s %s decode slice count %d\n", + __func__, + (dec_dpb_status == H264_PIC_DATA_DONE) ? + "H264_PIC_DATA_DONE" : + (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) ? + "H264_FIND_NEXT_PIC_NAL" : "H264_FIND_NEXT_DVEL_NAL", + hw->decode_pic_count); + /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); */ + hw->dec_result = DEC_RESULT_DONE; +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + if (vdec->slave && + dec_dpb_status == H264_FIND_NEXT_DVEL_NAL) { + struct vdec_h264_hw_s *hw_el = + (struct vdec_h264_hw_s *)(vdec->slave->private); + hw_el->got_valid_nal = 0; + hw->switch_dvlayer_flag = 1; + } else if (vdec->master && + dec_dpb_status == H264_FIND_NEXT_PIC_NAL) { + struct vdec_h264_hw_s *hw_bl = + (struct vdec_h264_hw_s *)(vdec->master->private); + hw_bl->got_valid_nal = 0; + hw->switch_dvlayer_flag = 1; + } else { + hw->switch_dvlayer_flag = 0; + hw->got_valid_nal = 1; + } +#endif + if (!hw->wait_for_udr_send) { + hw->dec_result = DEC_RESULT_DONE; + vdec_schedule_work(&hw->work); + } +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + } else if ( + (dec_dpb_status == H264_FIND_NEXT_PIC_NAL) || + (dec_dpb_status == H264_FIND_NEXT_DVEL_NAL)) { + goto pic_done_proc; +#endif + } else if (dec_dpb_status == H264_AUX_DATA_READY) { + reset_process_time(hw); + if (READ_VREG(H264_AUX_DATA_SIZE) != 0) { + dma_sync_single_for_cpu( + amports_get_dma_device(), + hw->aux_phy_addr, + hw->prefix_aux_size + hw->suffix_aux_size, + DMA_FROM_DEVICE); + if (dpb_is_debug(DECODE_ID(hw), + PRINT_FLAG_DPB_DETAIL)) + dump_aux_buf(hw); +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + if (vdec->dolby_meta_with_el || vdec->slave) { + if (hw->last_dec_picture) + set_aux_data(hw, hw->last_dec_picture, + 0, 0, NULL); + } else { + if (vdec->master) { + struct vdec_h264_hw_s *hw_bl = + (struct vdec_h264_hw_s *) + (vdec->master->private); + if (hw_bl->last_dec_picture != NULL) { + set_aux_data(hw_bl, + hw_bl->last_dec_picture, + 0, 1, hw); + } + set_aux_data(hw, + hw->last_dec_picture, + 0, 2, NULL); + } + } +#else + if (hw->last_dec_picture) + set_aux_data(hw, + hw->last_dec_picture, 0, 0, NULL); +#endif + } +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + hw->switch_dvlayer_flag = 0; + hw->got_valid_nal = 1; +#endif + hw->dec_result = DEC_RESULT_DONE; + vdec_schedule_work(&hw->work); + } else if (/*(dec_dpb_status == H264_DATA_REQUEST) ||*/ + (dec_dpb_status == H264_SEARCH_BUFEMPTY) || + (dec_dpb_status == H264_DECODE_BUFEMPTY) || + (dec_dpb_status == H264_DECODE_TIMEOUT)) { +empty_proc: + reset_process_time(hw); + + release_cur_decoding_buf(hw); + + if (input_frame_based(vdec) || + (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0x200)) { + if (h264_debug_flag & + DISABLE_ERROR_HANDLE) { + dpb_print(DECODE_ID(hw), + PRINT_FLAG_ERROR, + "%s decoding error, level 0x%x\n", + __func__, + READ_VREG(VLD_MEM_VIFIFO_LEVEL)); + goto send_again; + } + amvdec_stop(); + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS, + "%s %s\n", __func__, + (dec_dpb_status == H264_SEARCH_BUFEMPTY) ? + "H264_SEARCH_BUFEMPTY" : + (dec_dpb_status == H264_DECODE_BUFEMPTY) ? + "H264_DECODE_BUFEMPTY" : + (dec_dpb_status == H264_DECODE_TIMEOUT) ? + "H264_DECODE_TIMEOUT" : + "OTHER"); + hw->dec_result = DEC_RESULT_DONE; + + if (dec_dpb_status == H264_SEARCH_BUFEMPTY) + hw->search_dataempty_num++; + else if (dec_dpb_status == H264_DECODE_TIMEOUT) + hw->decode_timeout_num++; + else if (dec_dpb_status == H264_DECODE_BUFEMPTY) + hw->decode_dataempty_num++; + + hw->data_flag |= ERROR_FLAG; + + vdec_schedule_work(&hw->work); + } else { + /* WRITE_VREG(DPB_STATUS_REG, H264_ACTION_INIT); */ + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS, + "%s DEC_RESULT_AGAIN\n", __func__); +send_again: + hw->dec_result = DEC_RESULT_AGAIN; + vdec_schedule_work(&hw->work); + } + } else if (dec_dpb_status == H264_DATA_REQUEST) { + reset_process_time(hw); + if (input_frame_based(vdec)) { + dpb_print(DECODE_ID(hw), + PRINT_FLAG_VDEC_STATUS, + "%s H264_DATA_REQUEST (%d)\n", + __func__, hw->get_data_count); + hw->dec_result = DEC_RESULT_GET_DATA; + hw->get_data_start_time = jiffies; + hw->get_data_count++; + if (hw->get_data_count >= frame_max_data_packet) + goto empty_proc; + vdec_schedule_work(&hw->work); + } else + goto empty_proc; + } else if (dec_dpb_status == H264_DECODE_OVER_SIZE) { + dpb_print(DECODE_ID(hw), 0, + "vmh264 decode oversize !!\n"); + release_cur_decoding_buf(hw); + hw->data_flag |= ERROR_FLAG; + hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW; + reset_process_time(hw); + hw->dec_result = DEC_RESULT_DONE; + vdec_schedule_work(&hw->work); + return IRQ_HANDLED; + } + + if (READ_VREG(AV_SCRATCH_G) == 1) { + hw->sei_itu_data_len = + (READ_VREG(H264_AUX_DATA_SIZE) >> 16) << 4; + if (hw->sei_itu_data_len > SEI_ITU_DATA_SIZE * 2) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR, + "itu data size more than 4K: %d, discarded it\n", + hw->sei_itu_data_len); + hw->sei_itu_data_len = 0; + } + + if (hw->sei_itu_data_len != 0) { + u8 *trans_data_buf; + u8 *sei_data_buf; + u32 temp; + u32 *pswap_data; + + dma_sync_single_for_cpu( + amports_get_dma_device(), + hw->aux_phy_addr, + hw->prefix_aux_size + hw->suffix_aux_size, + DMA_FROM_DEVICE); +#if 0 + dump_aux_buf(hw); +#endif + + trans_data_buf = (u8 *)hw->aux_addr; + sei_data_buf = (u8 *)hw->sei_itu_data_buf; + for (i = 0; i < hw->sei_itu_data_len/2; i++) + sei_data_buf[i] = trans_data_buf[i*2]; + hw->sei_itu_data_len = hw->sei_itu_data_len / 2; + + pswap_data = (u32 *)hw->sei_itu_data_buf; + for (i = 0; i < hw->sei_itu_data_len/4; i = i+2) { + temp = pswap_data[i]; + pswap_data[i] = pswap_data[i+1]; + pswap_data[i+1] = temp; + } + } + WRITE_VREG(AV_SCRATCH_G, 0); + return IRQ_HANDLED; + } + + + /* ucode debug */ + debug_tag = READ_VREG(DEBUG_REG1); + if (debug_tag & 0x10000) { + unsigned short *p = (unsigned short *)hw->lmem_addr; + + dma_sync_single_for_cpu( + amports_get_dma_device(), + hw->lmem_addr_remap, + PAGE_SIZE, + DMA_FROM_DEVICE); + + dpb_print(DECODE_ID(hw), 0, + "LMEM:\n", debug_tag); + for (i = 0; i < 0x400; i += 4) { + int ii; + if ((i & 0xf) == 0) + dpb_print_cont(DECODE_ID(hw), 0, + "%03x: ", i); + for (ii = 0; ii < 4; ii++) + dpb_print_cont(DECODE_ID(hw), 0, + "%04x ", p[i+3-ii]); + if (((i+ii) & 0xf) == 0) + dpb_print_cont(DECODE_ID(hw), 0, + "\n"); + } + if (((udebug_pause_pos & 0xffff) + == (debug_tag & 0xffff)) && + (udebug_pause_decode_idx == 0 || + udebug_pause_decode_idx == + hw->decode_pic_count) && + (udebug_pause_val == 0 || + udebug_pause_val == READ_VREG(DEBUG_REG2))) { + udebug_pause_pos &= 0xffff; + hw->ucode_pause_pos = udebug_pause_pos; + } + else if (debug_tag & 0x20000) + hw->ucode_pause_pos = 0xffffffff; + if (hw->ucode_pause_pos) + reset_process_time(hw); + else + WRITE_VREG(DEBUG_REG1, 0); + } else if (debug_tag != 0) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT, + "dbg%x: %x\n", debug_tag, + READ_VREG(DEBUG_REG2)); + if (((udebug_pause_pos & 0xffff) + == (debug_tag & 0xffff)) && + (udebug_pause_decode_idx == 0 || + udebug_pause_decode_idx == + hw->decode_pic_count) && + (udebug_pause_val == 0 || + udebug_pause_val == READ_VREG(DEBUG_REG2))) { + udebug_pause_pos &= 0xffff; + hw->ucode_pause_pos = udebug_pause_pos; + } + if (hw->ucode_pause_pos) + reset_process_time(hw); + else + WRITE_VREG(DEBUG_REG1, 0); + } + /**/ + return IRQ_HANDLED; +} + +static irqreturn_t vh264_isr(struct vdec_s *vdec, int irq) +{ + struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)(vdec->private); + struct h264_dpb_stru *p_H264_Dpb = &hw->dpb; + + + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + if (!hw) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR, + "decoder is not running\n"); + return IRQ_HANDLED; + } + if (hw->eos) + return IRQ_HANDLED; + + p_H264_Dpb->vdec = vdec; + p_H264_Dpb->dec_dpb_status = READ_VREG(DPB_STATUS_REG); + + dpb_print(DECODE_ID(hw), PRINT_FLAG_UCODE_EVT, + "%s DPB_STATUS_REG: 0x%x, ERROR_STATUS_REG 0x%x, sb (0x%x 0x%x 0x%x) bitcnt 0x%x mby_mbx 0x%x\n", + __func__, + p_H264_Dpb->dec_dpb_status, + READ_VREG(ERROR_STATUS_REG), + READ_VREG(VLD_MEM_VIFIFO_LEVEL), + READ_VREG(VLD_MEM_VIFIFO_WP), + READ_VREG(VLD_MEM_VIFIFO_RP), + READ_VREG(VIFF_BIT_CNT), + READ_VREG(MBY_MBX)); + + if (p_H264_Dpb->dec_dpb_status == H264_WRRSP_REQUEST) { + if (hw->mmu_enable) + hevc_sao_wait_done(hw); + WRITE_VREG(DPB_STATUS_REG, H264_WRRSP_DONE); + return IRQ_HANDLED; + } + return IRQ_WAKE_THREAD; + +} + +static void timeout_process(struct vdec_h264_hw_s *hw) +{ + hw->timeout_num++; + amvdec_stop(); + if (hw->mmu_enable) { + hevc_set_frame_done(hw); + hevc_sao_wait_done(hw); + } + dpb_print(DECODE_ID(hw), + PRINT_FLAG_ERROR, "%s decoder timeout\n", __func__); + release_cur_decoding_buf(hw); + hw->dec_result = DEC_RESULT_DONE; + hw->data_flag |= ERROR_FLAG; + reset_process_time(hw); + vdec_schedule_work(&hw->work); +} + +static void dump_bufspec(struct vdec_h264_hw_s *hw, + const char *caller) +{ + int i; + dpb_print(DECODE_ID(hw), 0, + "%s in %s:\n", __func__, caller); + for (i = 0; i < BUFSPEC_POOL_SIZE; i++) { + if (hw->buffer_spec[i].used == -1) + continue; + dpb_print(DECODE_ID(hw), 0, + "bufspec (%d): used %d adr 0x%x canvas(%d) vf_ref(%d) ", + i, hw->buffer_spec[i].used, + hw->buffer_spec[i].buf_adr, + hw->buffer_spec[i].canvas_pos, + hw->buffer_spec[i].vf_ref + ); +#ifdef CONFIG_AM_VDEC_DV + dpb_print_cont(DECODE_ID(hw), 0, + "dv_el_exist %d", + hw->buffer_spec[i].dv_enhance_exist + ); +#endif + dpb_print_cont(DECODE_ID(hw), 0, "\n"); + } + +} + +static void vmh264_dump_state(struct vdec_s *vdec) +{ + struct vdec_h264_hw_s *hw = + (struct vdec_h264_hw_s *)(vdec->private); + struct h264_dpb_stru *p_H264_Dpb = &hw->dpb; + dpb_print(DECODE_ID(hw), 0, + "====== %s\n", __func__); + dpb_print(DECODE_ID(hw), 0, + "width/height (%d/%d), reorder_pic_num %d dpb size(bufspec count) %d max_reference_size(collocate count) %d\n", + hw->frame_width, + hw->frame_height, + hw->dpb.reorder_pic_num, + hw->dpb.mDPB.size, + hw->max_reference_size + ); + + dpb_print(DECODE_ID(hw), 0, + "is_framebase(%d), eos %d, state 0x%x, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d bufmgr_reset_cnt %d\n", + input_frame_based(vdec), + hw->eos, + hw->stat, + hw->dec_result, + decode_frame_count[DECODE_ID(hw)], + display_frame_count[DECODE_ID(hw)], + run_count[DECODE_ID(hw)], + not_run_ready[DECODE_ID(hw)], + input_empty[DECODE_ID(hw)], + hw->reset_bufmgr_count + ); + + if (vf_get_receiver(vdec->vf_provider_name)) { + enum receviver_start_e state = + vf_notify_receiver(vdec->vf_provider_name, + VFRAME_EVENT_PROVIDER_QUREY_STATE, + NULL); + dpb_print(DECODE_ID(hw), 0, + "\nreceiver(%s) state %d\n", + vdec->vf_provider_name, + state); + } + + dpb_print(DECODE_ID(hw), 0, + "%s, newq(%d/%d), dispq(%d/%d) vf prepare/get/put (%d/%d/%d), free_spec(%d), initdon(%d), used_size(%d/%d), unused_fr_dpb(%d)\n", + __func__, + kfifo_len(&hw->newframe_q), + VF_POOL_SIZE, + kfifo_len(&hw->display_q), + VF_POOL_SIZE, + hw->vf_pre_count, + hw->vf_get_count, + hw->vf_put_count, + have_free_buf_spec(vdec), + p_H264_Dpb->mDPB.init_done, + p_H264_Dpb->mDPB.used_size, p_H264_Dpb->mDPB.size, + is_there_unused_frame_from_dpb(&p_H264_Dpb->mDPB) + ); + + dump_dpb(&p_H264_Dpb->mDPB, 1); + dump_pic(p_H264_Dpb); + dump_bufspec(hw, __func__); + + dpb_print(DECODE_ID(hw), 0, + "DPB_STATUS_REG=0x%x\n", + READ_VREG(DPB_STATUS_REG)); + dpb_print(DECODE_ID(hw), 0, + "MPC_E=0x%x\n", + READ_VREG(MPC_E)); + dpb_print(DECODE_ID(hw), 0, + "H264_DECODE_MODE=0x%x\n", + READ_VREG(H264_DECODE_MODE)); + dpb_print(DECODE_ID(hw), 0, + "MBY_MBX=0x%x\n", + READ_VREG(MBY_MBX)); + dpb_print(DECODE_ID(hw), 0, + "H264_DECODE_SIZE=0x%x\n", + READ_VREG(H264_DECODE_SIZE)); + dpb_print(DECODE_ID(hw), 0, + "VIFF_BIT_CNT=0x%x\n", + READ_VREG(VIFF_BIT_CNT)); + dpb_print(DECODE_ID(hw), 0, + "VLD_MEM_VIFIFO_LEVEL=0x%x\n", + READ_VREG(VLD_MEM_VIFIFO_LEVEL)); + dpb_print(DECODE_ID(hw), 0, + "VLD_MEM_VIFIFO_WP=0x%x\n", + READ_VREG(VLD_MEM_VIFIFO_WP)); + dpb_print(DECODE_ID(hw), 0, + "VLD_MEM_VIFIFO_RP=0x%x\n", + READ_VREG(VLD_MEM_VIFIFO_RP)); + dpb_print(DECODE_ID(hw), 0, + "PARSER_VIDEO_RP=0x%x\n", + READ_PARSER_REG(PARSER_VIDEO_RP)); + dpb_print(DECODE_ID(hw), 0, + "PARSER_VIDEO_WP=0x%x\n", + READ_PARSER_REG(PARSER_VIDEO_WP)); + + if (input_frame_based(vdec) && + dpb_is_debug(DECODE_ID(hw), + PRINT_FRAMEBASE_DATA) + ) { + int jj; + if (hw->chunk && hw->chunk->block && + hw->chunk->size > 0) { + u8 *data = + ((u8 *)hw->chunk->block->start_virt) + + hw->chunk->offset; + dpb_print(DECODE_ID(hw), 0, + "frame data size 0x%x\n", + hw->chunk->size); + for (jj = 0; jj < hw->chunk->size; jj++) { + if ((jj & 0xf) == 0) + dpb_print(DECODE_ID(hw), + PRINT_FRAMEBASE_DATA, + "%06x:", jj); + dpb_print_cont(DECODE_ID(hw), + PRINT_FRAMEBASE_DATA, + "%02x ", data[jj]); + if (((jj + 1) & 0xf) == 0) + dpb_print_cont(DECODE_ID(hw), + PRINT_FRAMEBASE_DATA, + "\n"); + } + } + } +} + + +static void check_timer_func(unsigned long arg) +{ + struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)arg; + struct vdec_s *vdec = hw_to_vdec(hw); + int error_skip_frame_count = error_skip_count & 0xfff; + unsigned int timeout_val = decode_timeout_val; + if (timeout_val != 0 && + hw->no_error_count < error_skip_frame_count) + timeout_val = errordata_timeout_val; + if ((h264_debug_cmd & 0x100) != 0 && + DECODE_ID(hw) == (h264_debug_cmd & 0xff)) { + hw->dec_result = DEC_RESULT_DONE; + vdec_schedule_work(&hw->work); + pr_info("vdec %d is forced to be disconnected\n", + h264_debug_cmd & 0xff); + h264_debug_cmd = 0; + return; + } + if ((h264_debug_cmd & 0x200) != 0 && + DECODE_ID(hw) == (h264_debug_cmd & 0xff)) { + pr_debug("vdec %d is forced to reset bufmgr\n", + h264_debug_cmd & 0xff); + hw->reset_bufmgr_flag = 1; + h264_debug_cmd = 0; + return; + } + + if (vdec->next_status == VDEC_STATUS_DISCONNECTED) { + hw->dec_result = DEC_RESULT_FORCE_EXIT; + vdec_schedule_work(&hw->work); + pr_debug("vdec requested to be disconnected\n"); + return; + } + + if (radr != 0) { + if (rval != 0) { + WRITE_VREG(radr, rval); + pr_info("WRITE_VREG(%x,%x)\n", radr, rval); + } else + pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr)); + rval = 0; + radr = 0; + } + + if ((input_frame_based(vdec) || + (READ_VREG(VLD_MEM_VIFIFO_LEVEL) > 0xb0)) && + ((h264_debug_flag & DISABLE_ERROR_HANDLE) == 0) && + (timeout_val > 0) && + (hw->start_process_time > 0) && + ((1000 * (jiffies - hw->start_process_time) / HZ) + > timeout_val) + ) { + u32 dpb_status = READ_VREG(DPB_STATUS_REG); + u32 mby_mbx = READ_VREG(MBY_MBX); + if ((dpb_status == H264_ACTION_DECODE_NEWPIC) || + (dpb_status == H264_ACTION_DECODE_SLICE)) { + if (hw->last_mby_mbx == mby_mbx) { + if (hw->decode_timeout_count > 0) + hw->decode_timeout_count--; + if (hw->decode_timeout_count == 0) + timeout_process(hw); + } else + start_process_time(hw); + } else if (is_in_parsing_state(dpb_status)) { + if (hw->last_vld_level == + READ_VREG(VLD_MEM_VIFIFO_LEVEL)) { + if (hw->decode_timeout_count > 0) + hw->decode_timeout_count--; + if (hw->decode_timeout_count == 0) + timeout_process(hw); + } + } + hw->last_vld_level = + READ_VREG(VLD_MEM_VIFIFO_LEVEL); + hw->last_mby_mbx = mby_mbx; + } + + if ((hw->ucode_pause_pos != 0) && + (hw->ucode_pause_pos != 0xffffffff) && + udebug_pause_pos != hw->ucode_pause_pos) { + hw->ucode_pause_pos = 0; + WRITE_VREG(DEBUG_REG1, 0); + } + + mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL); +} + +static int dec_status(struct vdec_s *vdec, struct vdec_info *vstatus) +{ + struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private; + vstatus->frame_width = hw->frame_width; + vstatus->frame_height = hw->frame_height; + if (hw->frame_dur != 0) + vstatus->frame_rate = 96000 / hw->frame_dur; + else + vstatus->frame_rate = -1; + vstatus->error_count = 0; + vstatus->status = hw->stat; + snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name), + "%s-%02d", DRIVER_NAME, hw->id); + + return 0; +} + +static int vh264_hw_ctx_restore(struct vdec_h264_hw_s *hw) +{ + int i, j; + + /* if (hw->init_flag == 0) { */ + if (h264_debug_flag & 0x40000000) { + /* if (1) */ + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS, + "%s, reset register\n", __func__); + + while (READ_VREG(DCAC_DMA_CTRL) & 0x8000) + ; + while (READ_VREG(LMEM_DMA_CTRL) & 0x8000) + ; /* reg address is 0x350 */ + +#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ + WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4)); + WRITE_VREG(DOS_SW_RESET0, 0); + + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + + WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4)); + WRITE_VREG(DOS_SW_RESET0, 0); + + WRITE_VREG(DOS_SW_RESET0, (1<<9) | (1<<8)); + WRITE_VREG(DOS_SW_RESET0, 0); + + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + +#else + WRITE_RESET_REG(RESET0_REGISTER, + RESET_IQIDCT | RESET_MC | RESET_VLD_PART); + READ_RESET_REG(RESET0_REGISTER); + WRITE_RESET_REG(RESET0_REGISTER, + RESET_IQIDCT | RESET_MC | RESET_VLD_PART); + + WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK); +#endif + WRITE_VREG(POWER_CTL_VLD, + READ_VREG(POWER_CTL_VLD) | (0 << 10) | + (1 << 9) | (1 << 6)); + } else { + /* WRITE_VREG(POWER_CTL_VLD, + * READ_VREG(POWER_CTL_VLD) | (0 << 10) | (1 << 9) ); + */ + WRITE_VREG(POWER_CTL_VLD, + READ_VREG(POWER_CTL_VLD) | + (0 << 10) | (1 << 9) | (1 << 6)); + } + /* disable PSCALE for hardware sharing */ + WRITE_VREG(PSCALE_CTRL, 0); + + /* clear mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + /* enable mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_MASK, 1); + +#ifdef NV21 + SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1<<17); +#endif + + SET_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24); + CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 0xbf << 24); + + CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31); + if (hw->mmu_enable) { + SET_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1<<31); + WRITE_VREG(MDEC_EXTIF_CFG1, 0x80000000); + } else { + CLEAR_VREG_MASK(MDEC_PIC_DC_MUX_CTRL, 1 << 31); + WRITE_VREG(MDEC_EXTIF_CFG1, 0); + } + + +#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ + /* pr_info("vh264 meson8 prot init\n"); */ + WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa); +#endif + if (hw->dpb.mDPB.size > 0) { + WRITE_VREG(AV_SCRATCH_7, (hw->max_reference_size << 24) | + (hw->dpb.mDPB.size << 16) | + (hw->dpb.mDPB.size << 8)); + + for (j = 0; j < hw->dpb.mDPB.size; j++) { + i = get_buf_spec_by_canvas_pos(hw, j); + if (i < 0) + break; + + if (!hw->mmu_enable && + hw->buffer_spec[i].cma_alloc_addr) + config_decode_canvas(hw, i); + if (hw->mmu_enable && hw->double_write_mode) + config_decode_canvas_ex(hw, i); + } + } else { + WRITE_VREG(AV_SCRATCH_0, 0); + WRITE_VREG(AV_SCRATCH_9, 0); + } + + if (hw->init_flag == 0) + WRITE_VREG(DPB_STATUS_REG, 0); + else + WRITE_VREG(DPB_STATUS_REG, H264_ACTION_DECODE_START); + + WRITE_VREG(FRAME_COUNTER_REG, hw->decode_pic_count); + WRITE_VREG(AV_SCRATCH_8, hw->buf_offset); + if (!tee_enabled()) + WRITE_VREG(AV_SCRATCH_G, hw->mc_dma_handle); + + /* hw->error_recovery_mode = (error_recovery_mode != 0) ? + * error_recovery_mode : error_recovery_mode_in; + */ + /* WRITE_VREG(AV_SCRATCH_F, + * (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) ); + */ + WRITE_VREG(AV_SCRATCH_F, (READ_VREG(AV_SCRATCH_F) & 0xffffffc3) | + ((error_recovery_mode_in & 0x1) << 4)); + /*if (hw->ucode_type == UCODE_IP_ONLY_PARAM) + SET_VREG_MASK(AV_SCRATCH_F, 1 << 6); + else*/ + CLEAR_VREG_MASK(AV_SCRATCH_F, 1 << 6); + + WRITE_VREG(LMEM_DUMP_ADR, (u32)hw->lmem_addr_remap); +#if 1 /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ + WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa); +#endif + + WRITE_VREG(DEBUG_REG1, 0); + WRITE_VREG(DEBUG_REG2, 0); + + if (hw->reg_iqidct_control) + WRITE_VREG(IQIDCT_CONTROL, hw->reg_iqidct_control); + if (hw->reg_vcop_ctrl_reg) + WRITE_VREG(VCOP_CTRL_REG, hw->reg_vcop_ctrl_reg); + if (hw->vld_dec_control) + WRITE_VREG(VLD_DECODE_CONTROL, hw->vld_dec_control); + return 0; +} + +static int vmh264_set_trickmode(struct vdec_s *vdec, unsigned long trickmode) +{ + struct vdec_h264_hw_s *hw = + (struct vdec_h264_hw_s *)vdec->private; + if (i_only_flag & 0x100) + return 0; + if (trickmode == TRICKMODE_I) + hw->i_only = 0x3; + else if (trickmode == TRICKMODE_NONE) + hw->i_only = 0x0; + return 0; +} + +static unsigned char amvdec_enable_flag; +static void vh264_local_init(struct vdec_h264_hw_s *hw) +{ + int i; + hw->init_flag = 0; + hw->eos = 0; + hw->valve_count = 0; + hw->config_bufmgr_done = 0; + hw->start_process_time = 0; + hw->has_i_frame = 0; + hw->no_error_count = 0xfff; + hw->no_error_i_count = 0xf; + + hw->dec_flag = 0; + hw->data_flag = 0; + hw->skip_frame_count = 0; + hw->reg_iqidct_control = 0; + hw->reg_vcop_ctrl_reg = 0; + hw->reg_rv_ai_mb_count = 0; + hw->vld_dec_control = 0; + hw->decode_timeout_count = 0; + + hw->vh264_ratio = hw->vh264_amstream_dec_info.ratio; + /* vh264_ratio = 0x100; */ + + hw->vh264_rotation = (((unsigned long) + hw->vh264_amstream_dec_info.param) >> 16) & 0xffff; + + hw->frame_prog = 0; + hw->frame_width = hw->vh264_amstream_dec_info.width; + hw->frame_height = hw->vh264_amstream_dec_info.height; + hw->frame_dur = hw->vh264_amstream_dec_info.rate; + hw->pts_outside = ((unsigned long) + hw->vh264_amstream_dec_info.param) & 0x01; + hw->sync_outside = ((unsigned long) + hw->vh264_amstream_dec_info.param & 0x02) >> 1; + hw->use_idr_framerate = ((unsigned long) + hw->vh264_amstream_dec_info.param & 0x04) >> 2; + hw->max_refer_buf = !(((unsigned long) + hw->vh264_amstream_dec_info.param & 0x10) >> 4); + if (hw->frame_dur < 96000/960) { + /*more than 960fps,it should not be a correct value, + *give default 30fps + */ + hw->frame_dur = 96000/30; + } + + pr_info + ("H264 sysinfo: %dx%d duration=%d, pts_outside=%d\n", + hw->frame_width, hw->frame_height, hw->frame_dur, hw->pts_outside); + pr_debug("sync_outside=%d, use_idr_framerate=%d\n", + hw->sync_outside, hw->use_idr_framerate); + if (i_only_flag & 0x100) + hw->i_only = i_only_flag & 0xff; + + if ((unsigned long) hw->vh264_amstream_dec_info.param + & 0x08) + hw->no_poc_reorder_flag = 1; + + error_recovery_mode_in = 1; /*ucode control?*/ + if (error_proc_policy & 0x80000000) + hw->send_error_frame_flag = error_proc_policy & 0x1; + else if ((unsigned long) hw->vh264_amstream_dec_info.param & 0x20) + hw->send_error_frame_flag = 1; + + INIT_KFIFO(hw->display_q); + INIT_KFIFO(hw->newframe_q); + + for (i = 0; i < VF_POOL_SIZE; i++) { + const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]); + hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */ + hw->vfpool[hw->cur_pool][i].bufWidth = 1920; + kfifo_put(&hw->newframe_q, vf); + } + + hw->duration_from_pts_done = 0; + + hw->p_last_vf = NULL; + hw->vh264_stream_switching_state = SWITCHING_STATE_OFF; + hw->hevc_cur_buf_idx = 0xffff; + + return; +} + +static s32 vh264_init(struct vdec_h264_hw_s *hw) +{ + /* int trickmode_fffb = 0; */ + + /* pr_info("\nvh264_init\n"); */ + /* init_timer(&hw->recycle_timer); */ + + /* timer init */ + init_timer(&hw->check_timer); + + hw->check_timer.data = (unsigned long)hw; + hw->check_timer.function = check_timer_func; + hw->check_timer.expires = jiffies + CHECK_INTERVAL; + + /* add_timer(&hw->check_timer); */ + hw->stat |= STAT_TIMER_ARM; + hw->stat |= STAT_ISR_REG; + + vh264_local_init(hw); + INIT_WORK(&hw->work, vh264_work); + INIT_WORK(&hw->notify_work, vh264_notify_work); + INIT_WORK(&hw->user_data_work, user_data_push_work); +#ifdef MH264_USERDATA_ENABLE + INIT_WORK(&hw->user_data_ready_work, user_data_ready_notify_work); +#endif + + if (!amvdec_enable_flag) { + amvdec_enable_flag = true; + amvdec_enable(); + if (hw->mmu_enable) + amhevc_enable(); + } + if (hw->mmu_enable) { + + hw->frame_mmu_map_addr = + dma_alloc_coherent(amports_get_dma_device(), + FRAME_MMU_MAP_SIZE, + &hw->frame_mmu_map_phy_addr, GFP_KERNEL); + if (hw->frame_mmu_map_addr == NULL) { + pr_err("%s: failed to alloc count_buffer\n", __func__); + return -ENOMEM; + } + } + if (!tee_enabled()) { + int ret = 0, size = -1; + int fw_size = 0x1000 * 16; + struct firmware_s *fw = NULL; + + /* -- ucode loading (amrisc and swap code) */ + hw->mc_cpu_addr = + dma_alloc_coherent(amports_get_dma_device(), MC_TOTAL_SIZE, + &hw->mc_dma_handle, GFP_KERNEL); + if (!hw->mc_cpu_addr) { + amvdec_enable_flag = false; + amvdec_disable(); + if (hw->mmu_enable) + amhevc_disable(); + pr_info("vh264_init: Can not allocate mc memory.\n"); + return -ENOMEM; + } + + /*pr_info("264 ucode swap area: phyaddr %p, cpu vaddr %p\n", + (void *)hw->mc_dma_handle, hw->mc_cpu_addr); + */ + + + pr_debug("start load orignal firmware ...\n"); + + fw = vmalloc(sizeof(struct firmware_s) + fw_size); + if (IS_ERR_OR_NULL(fw)) + return -ENOMEM; + + size = get_firmware_data(VIDEO_DEC_H264_MULTI, fw->data); + if (size < 0) { + pr_err("get firmware fail.\n"); + vfree(fw); + return -1; + } + + fw->len = size; + hw->fw = fw; + + /*ret = amvdec_loadmc_ex(VFORMAT_H264, NULL, buf);*/ + + /*header*/ + memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_HEADER, + fw->data + 0x4000, MC_SWAP_SIZE); + /*data*/ + memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_DATA, + fw->data + 0x2000, MC_SWAP_SIZE); + /*mmco*/ + memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MMCO, + fw->data + 0x6000, MC_SWAP_SIZE); + /*list*/ + memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_LIST, + fw->data + 0x3000, MC_SWAP_SIZE); + /*slice*/ + memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_SLICE, + fw->data + 0x5000, MC_SWAP_SIZE); + /*main*/ + memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN, + fw->data, 0x2000); + /*data*/ + memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x2000, + fw->data + 0x2000, 0x1000); + /*slice*/ + memcpy((u8 *) hw->mc_cpu_addr + MC_OFFSET_MAIN + 0x3000, + fw->data + 0x5000, 0x1000); + + if (hw->mmu_enable) { + int fw_mmu_size = 0x1000 * 16; + struct firmware_s *fw_mmu = NULL; + + pr_debug("start load mmu fw ...\n"); + + fw_mmu = vmalloc(sizeof(struct firmware_s) + fw_mmu_size); + if (IS_ERR_OR_NULL(fw_mmu)) + return -ENOMEM; + + size = get_firmware_data(VIDEO_DEC_H264_MULTI_MMU, + fw_mmu->data); + if (size < 0) { + pr_err("get mmu fw fail.\n"); + vfree(fw_mmu); + return -1; + } + + ret = amhevc_loadmc_ex(VFORMAT_HEVC, + NULL, fw_mmu->data); + + fw_mmu->len = size; + hw->fw_mmu = fw_mmu; + } + + if (ret < 0) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR, + "264 load orignal firmware error.\n"); + amvdec_disable(); + if (hw->mmu_enable) + amhevc_disable(); + if (hw->mc_cpu_addr) { + dma_free_coherent(amports_get_dma_device(), + MC_TOTAL_SIZE, hw->mc_cpu_addr, + hw->mc_dma_handle); + hw->mc_cpu_addr = NULL; + } + return -EBUSY; + } + + } +#if 1 /* #ifdef BUFFER_MGR_IN_C */ + hw->lmem_addr = __get_free_page(GFP_KERNEL); + if (!hw->lmem_addr) { + pr_info("%s: failed to alloc lmem_addr\n", __func__); + return -ENOMEM; + } else { + hw->lmem_addr_remap = dma_map_single( + amports_get_dma_device(), + (void *)hw->lmem_addr, + PAGE_SIZE, DMA_FROM_DEVICE); + if (dma_mapping_error(amports_get_dma_device(), + hw->lmem_addr_remap)) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_ERROR, + "%s: failed to map lmem_addr\n", __func__); + free_page(hw->lmem_addr); + hw->lmem_addr = 0; + hw->lmem_addr_remap = 0; + return -ENOMEM; + } + + pr_debug("%s, vaddr=%lx phy_addr=%p\n", + __func__, hw->lmem_addr, (void *)hw->lmem_addr_remap); + } + + if (prefix_aux_buf_size > 0 || + suffix_aux_buf_size > 0) { + u32 aux_buf_size; + hw->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size); + hw->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size); + aux_buf_size = hw->prefix_aux_size + hw->suffix_aux_size; + hw->aux_addr = kmalloc(aux_buf_size, GFP_KERNEL); + if (hw->aux_addr == NULL) { + pr_err("%s: failed to alloc rpm buffer\n", __func__); + return -1; + } + + hw->aux_phy_addr = dma_map_single(amports_get_dma_device(), + hw->aux_addr, aux_buf_size, DMA_FROM_DEVICE); + if (dma_mapping_error(amports_get_dma_device(), + hw->aux_phy_addr)) { + pr_err("%s: failed to map rpm buffer\n", __func__); + kfree(hw->aux_addr); + hw->aux_addr = NULL; + return -1; + } + hw->sei_itu_data_buf = kmalloc(SEI_ITU_DATA_SIZE, GFP_KERNEL); + if (hw->sei_itu_data_buf == NULL) { + pr_err("%s: failed to alloc sei itu data buffer\n", + __func__); + return -1; + } + + if (NULL == hw->sei_user_data_buffer) { + hw->sei_user_data_buffer = kmalloc(USER_DATA_SIZE, + GFP_KERNEL); + if (!hw->sei_user_data_buffer) { + pr_info("%s: Can not allocate sei_data_buffer\n", + __func__); + return -1; + } + hw->sei_user_data_wp = 0; + } + } +/* BUFFER_MGR_IN_C */ +#endif + hw->stat |= STAT_MC_LOAD; + + /* add memory barrier */ + wmb(); + + return 0; +} + +static int vh264_stop(struct vdec_h264_hw_s *hw) +{ + if (hw->stat & STAT_VDEC_RUN) { + amvdec_stop(); + hw->stat &= ~STAT_VDEC_RUN; + } + + cancel_work_sync(&hw->work); + cancel_work_sync(&hw->notify_work); + cancel_work_sync(&hw->user_data_work); +#ifdef MH264_USERDATA_ENABLE + cancel_work_sync(&hw->user_data_ready_work); +#endif + + if (hw->stat & STAT_MC_LOAD) { + if (hw->mc_cpu_addr != NULL) { + dma_free_coherent(amports_get_dma_device(), + MC_TOTAL_SIZE, hw->mc_cpu_addr, + hw->mc_dma_handle); + hw->mc_cpu_addr = NULL; + } + if (hw->frame_mmu_map_addr != NULL) { + dma_free_coherent(amports_get_dma_device(), + FRAME_MMU_MAP_SIZE, hw->frame_mmu_map_addr, + hw->frame_mmu_map_phy_addr); + hw->frame_mmu_map_addr = NULL; + } + + } + if (hw->stat & STAT_ISR_REG) { + vdec_free_irq(VDEC_IRQ_1, (void *)hw); + hw->stat &= ~STAT_ISR_REG; + } + if (hw->lmem_addr_remap) { + dma_unmap_single(amports_get_dma_device(), + hw->lmem_addr_remap, + PAGE_SIZE, DMA_FROM_DEVICE); + hw->lmem_addr_remap = 0; + } + if (hw->lmem_addr) { + free_page(hw->lmem_addr); + hw->lmem_addr = 0; + } + if (hw->aux_addr) { + dma_unmap_single(amports_get_dma_device(), + hw->aux_phy_addr, + hw->prefix_aux_size + hw->suffix_aux_size, + DMA_FROM_DEVICE); + kfree(hw->aux_addr); + hw->aux_addr = NULL; + } + if (hw->sei_itu_data_buf != NULL) { + kfree(hw->sei_itu_data_buf); + hw->sei_itu_data_buf = NULL; + } + if (hw->sei_user_data_buffer != NULL) { + kfree(hw->sei_user_data_buffer); + hw->sei_user_data_buffer = NULL; + } + /* amvdec_disable(); */ + + vfree(hw->fw); + hw->fw = NULL; + + if (hw->mmu_enable) { + vfree(hw->fw_mmu); + hw->fw_mmu = NULL; + } + + dpb_print(DECODE_ID(hw), 0, + "%s\n", + __func__); + return 0; +} + +static void vh264_notify_work(struct work_struct *work) +{ + struct vdec_h264_hw_s *hw = container_of(work, + struct vdec_h264_hw_s, notify_work); + struct vdec_s *vdec = hw_to_vdec(hw); + if (vdec->fr_hint_state == VDEC_NEED_HINT) { + vf_notify_receiver(vdec->vf_provider_name, + VFRAME_EVENT_PROVIDER_FR_HINT, + (void *)((unsigned long)hw->frame_dur)); + vdec->fr_hint_state = VDEC_HINTED; + } + + return; +} + +#ifdef MH264_USERDATA_ENABLE +static void vmh264_reset_udr_mgr(struct vdec_h264_hw_s *hw) +{ + int i; + hw->wait_for_udr_send = 0; + + INIT_LIST_HEAD(&hw->free_uds_wait_nodes); + INIT_LIST_HEAD(&hw->frame_uds); + + for (i = 0; i < MAX_FREE_USERDATA_NODES; i++) + list_add_tail(&hw->free_nodes[i].list, + &hw->free_uds_wait_nodes); +} + +static void vmh264_crate_userdata_manager( + struct vdec_h264_hw_s *hw, + u8 *userdata_buf, + int buf_len) +{ + if (hw) { + + + mutex_init(&hw->userdata_mutex); + + memset(&hw->userdata_info, 0, + sizeof(struct mh264_userdata_info_t)); + hw->userdata_info.data_buf = userdata_buf; + hw->userdata_info.buf_len = buf_len; + hw->userdata_info.data_buf_end = userdata_buf + buf_len; + + vmh264_reset_udr_mgr(hw); + + } +} + +static void vmh264_destroy_userdata_manager(struct vdec_h264_hw_s *hw) +{ + if (hw) + memset(&hw->userdata_info, + 0, + sizeof(struct mh264_userdata_info_t)); +} + +/* +#define DUMP_USERDATA_RECORD +*/ +#ifdef DUMP_USERDATA_RECORD + +#define MAX_USER_DATA_SIZE 3145728 +static void *user_data_buf; +static unsigned char *pbuf_start; +static int total_len; +static int bskip; +static int n_userdata_id; + +static void print_data(unsigned char *pdata, + int len, + unsigned int poc_number, + unsigned int flag, + unsigned int duration, + unsigned int vpts, + unsigned int vpts_valid, + int rec_id) +{ + int nLeft; + + nLeft = len; +#if 0 + pr_info("%d len:%d, flag:%d, dur:%d, vpts:0x%x, valid:%d, poc:%d\n", + rec_id, len, flag, + duration, vpts, vpts_valid, poc_number); +#endif + pr_info("%d len = %d, flag = %d, vpts = 0x%x, poc = %d\n", + rec_id, len, flag, vpts, poc); + + if (len == 96) { + int i; + nLeft = 72; + while (nLeft >= 16) { + pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + pdata[0], pdata[1], pdata[2], pdata[3], + pdata[4], pdata[5], pdata[6], pdata[7], + pdata[8], pdata[9], pdata[10], pdata[11], + pdata[12], pdata[13], pdata[14], pdata[15]); + nLeft -= 16; + pdata += 16; + } + + + while (nLeft > 0) { + pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n", + pdata[0], pdata[1], pdata[2], pdata[3], + pdata[4], pdata[5], pdata[6], pdata[7]); + nLeft -= 8; + pdata += 8; + } + + i = 0; + nLeft = 96-72; + while (i < nLeft) { + if (pdata[0] != 0) { + pr_info("some data error\n"); + break; + } + pdata++; + i++; + } + } else { + while (nLeft >= 16) { + pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + pdata[0], pdata[1], pdata[2], pdata[3], + pdata[4], pdata[5], pdata[6], pdata[7], + pdata[8], pdata[9], pdata[10], pdata[11], + pdata[12], pdata[13], pdata[14], pdata[15]); + nLeft -= 16; + pdata += 16; + } + + + while (nLeft > 0) { + pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n", + pdata[0], pdata[1], pdata[2], pdata[3], + pdata[4], pdata[5], pdata[6], pdata[7]); + nLeft -= 8; + pdata += 8; + } + + } +} + +static void push_to_buf(struct vdec_h264_hw_s *hw, + u8 *pdata, + int len, + struct userdata_meta_info_t *pmeta); + +static void dump_userdata_record(struct vdec_h264_hw_s *hw, + struct mh264_userdata_record_t *record) +{ + if (record && hw) { + u8 *pdata; + + pdata = hw->userdata_info.data_buf + record->rec_start; +/* + print_data(pdata, + record->rec_len, + record->meta_info.flags, + record->meta_info.duration, + record->meta_info.vpts, + record->meta_info.vpts_valid, + n_record_id); +*/ + push_to_buf(hw, pdata, record->rec_len, &record->meta_info); + n_userdata_id++; + } +} + + +static void push_to_buf(struct vdec_h264_hw_s *hw, + u8 *pdata, int len, + struct userdata_meta_info_t *pmeta) +{ + u32 *pLen; + int info_cnt; + u8 *pbuf_end; + + if (!user_data_buf) + return; + + if (bskip) { + pr_info("over size, skip\n"); + return; + } + info_cnt = 0; + pLen = (u32 *)pbuf_start; + + *pLen = len; + pbuf_start += sizeof(u32); + info_cnt++; + pLen++; + + *pLen = pmeta->poc_number; + pbuf_start += sizeof(u32); + info_cnt++; + pLen++; + + *pLen = pmeta->duration; + pbuf_start += sizeof(u32); + info_cnt++; + pLen++; + + *pLen = pmeta->flags; + pbuf_start += sizeof(u32); + info_cnt++; + pLen++; + + *pLen = pmeta->vpts; + pbuf_start += sizeof(u32); + info_cnt++; + pLen++; + + *pLen = pmeta->vpts_valid; + pbuf_start += sizeof(u32); + info_cnt++; + pLen++; + + + *pLen = n_userdata_id; + pbuf_start += sizeof(u32); + info_cnt++; + pLen++; + + + + pbuf_end = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE; + if (pdata + len > pbuf_end) { + int first_section_len; + + first_section_len = pbuf_end - pdata; + memcpy(pbuf_start, pdata, first_section_len); + pdata = (u8 *)hw->sei_user_data_buffer; + pbuf_start += first_section_len; + memcpy(pbuf_start, pdata, len - first_section_len); + pbuf_start += len - first_section_len; + } else { + memcpy(pbuf_start, pdata, len); + pbuf_start += len; + } + + total_len += len + info_cnt * sizeof(u32); + if (total_len >= MAX_USER_DATA_SIZE-4096) + bskip = 1; +} + +static void show_user_data_buf(void) +{ + u8 *pbuf; + int len; + unsigned int flag; + unsigned int duration; + unsigned int vpts; + unsigned int vpts_valid; + unsigned int poc_number; + int rec_id; + + pr_info("show user data buf\n"); + pbuf = user_data_buf; + + while (pbuf < pbuf_start) { + u32 *pLen; + + pLen = (u32 *)pbuf; + + len = *pLen; + pLen++; + pbuf += sizeof(u32); + + poc_number = *pLen; + pLen++; + pbuf += sizeof(u32); + + duration = *pLen; + pLen++; + pbuf += sizeof(u32); + + flag = *pLen; + pLen++; + pbuf += sizeof(u32); + + vpts = *pLen; + pLen++; + pbuf += sizeof(u32); + + vpts_valid = *pLen; + pLen++; + pbuf += sizeof(u32); + + rec_id = *pLen; + pLen++; + pbuf += sizeof(u32); + + print_data(pbuf, len, poc_number, flag, + duration, vpts, + vpts_valid, rec_id); + pbuf += len; + msleep(30); + } +} + +static int vmh264_init_userdata_dump(void) +{ + user_data_buf = kmalloc(MAX_USER_DATA_SIZE, GFP_KERNEL); + if (user_data_buf) + return 1; + else + return 0; +} + +static void vmh264_dump_userdata(void) +{ + if (user_data_buf) { + show_user_data_buf(); + kfree(user_data_buf); + user_data_buf = NULL; + } +} + +static void vmh264_reset_user_data_buf(void) +{ + total_len = 0; + pbuf_start = user_data_buf; + bskip = 0; + n_userdata_id = 0; +} +#endif + +static void vmh264_input_udc_waitqueue(struct vdec_h264_hw_s *hw, + struct userdata_meta_info_t meta_info, + int wp) +{ + struct mh264_ud_record_wait_node_t *node; + struct mh264_userdata_record_t *p_userdata_rec; + int data_length; + + node = list_entry( + hw->free_uds_wait_nodes.next, + struct mh264_ud_record_wait_node_t, + list); + + if (node) { + if (wp > hw->userdata_info.last_wp) + data_length = wp - hw->userdata_info.last_wp; + else + data_length = wp + hw->userdata_info.buf_len + - hw->userdata_info.last_wp; + + if (data_length & 0x7) + data_length = (((data_length + 8) >> 3) << 3); +#if 0 + pr_info("wakeup_push: ri:%d, wi:%d, data_len:%d, last_wp:%d, wp:%d, id = %d\n", + lg_p_mpeg12_userdata_info->read_index, + lg_p_mpeg12_userdata_info->write_index, + data_length, + lg_p_mpeg12_userdata_info->last_wp, + wp, + n_userdata_id); +#endif + p_userdata_rec = &node->ud_record; + p_userdata_rec->meta_info = meta_info; + p_userdata_rec->rec_start = hw->userdata_info.last_wp; + p_userdata_rec->rec_len = data_length; +#if 0 + dump_userdata_record(hw, p_userdata_rec); +#endif + list_move(&node->list, &hw->frame_uds); + } + hw->userdata_info.last_wp = wp; +} + +static void vmh264_udc_fill_vpts(struct vdec_h264_hw_s *hw, + int frame_type, + u32 vpts, + u32 vpts_valid) +{ + struct mh264_ud_record_wait_node_t *node; + struct mh264_ud_record_wait_node_t *tmp; + struct mh264_userdata_record_t *pud_record; + struct h264_dpb_stru *p_H264_Dpb = &hw->dpb; + + if (!list_empty(&hw->frame_uds)) { + list_for_each_entry_safe(node, tmp, &hw->frame_uds, list) { + pud_record = &node->ud_record; + pud_record->meta_info.vpts = vpts; + pud_record->meta_info.vpts_valid = vpts_valid; + pud_record->meta_info.poc_number = + p_H264_Dpb->mVideo.dec_picture->poc; + } + hw->wait_for_udr_send = 1; + schedule_work(&hw->user_data_ready_work); + } +} + + +static void user_data_ready_notify_work(struct work_struct *work) +{ + struct vdec_h264_hw_s *hw = container_of(work, + struct vdec_h264_hw_s, user_data_ready_work); + + struct mh264_ud_record_wait_node_t *node; + struct mh264_ud_record_wait_node_t *tmp; + + list_for_each_entry_safe(node, tmp, &hw->frame_uds, list) { + mutex_lock(&hw->userdata_mutex); + + hw->userdata_info.records[hw->userdata_info.write_index] + = node->ud_record; + hw->userdata_info.write_index++; + if (hw->userdata_info.write_index >= USERDATA_FIFO_NUM) + hw->userdata_info.write_index = 0; + + mutex_unlock(&hw->userdata_mutex); + + list_move(&node->list, &hw->free_uds_wait_nodes); +#ifdef DUMP_USERDATA_RECORD + dump_userdata_record(hw, &node->ud_record); +#endif + vdec_wakeup_userdata_poll(hw_to_vdec(hw)); + } + + hw->wait_for_udr_send = 0; + hw->dec_result = DEC_RESULT_DONE; + vdec_schedule_work(&hw->work); +} + +static int vmh264_user_data_read(struct vdec_s *vdec, + struct userdata_param_t *puserdata_para) +{ + struct vdec_h264_hw_s *hw = NULL; + int rec_ri, rec_wi; + int rec_len; + u8 *rec_data_start; + u8 *pdest_buf; + struct mh264_userdata_record_t *p_userdata_rec; + u32 data_size; + u32 res; + int copy_ok = 1; + + hw = (struct vdec_h264_hw_s *)vdec->private; + + pdest_buf = (void *)(puserdata_para->pbuf_addr); + mutex_lock(&hw->userdata_mutex); + +/* + pr_info("ri = %d, wi = %d\n", + lg_p_mpeg12_userdata_info->read_index, + lg_p_mpeg12_userdata_info->write_index); +*/ + rec_ri = hw->userdata_info.read_index; + rec_wi = hw->userdata_info.write_index; + + if (rec_ri == rec_wi) { + mutex_unlock(&hw->userdata_mutex); + return 0; + } + + p_userdata_rec = hw->userdata_info.records + rec_ri; + + rec_len = p_userdata_rec->rec_len; + rec_data_start = p_userdata_rec->rec_start + hw->userdata_info.data_buf; +/* + pr_info("rec_len:%d, rec_start:%d, buf_len:%d\n", + p_userdata_rec->rec_len, + p_userdata_rec->rec_start, + puserdata_para->buf_len); +*/ + if (rec_len <= puserdata_para->buf_len) { + /* dvb user data buffer is enought to + copy the whole recored. */ + data_size = rec_len; + if (rec_data_start + data_size + > hw->userdata_info.data_buf_end) { + int first_section_len; + + first_section_len = hw->userdata_info.buf_len - + p_userdata_rec->rec_start; + res = (u32)copy_to_user((void *)pdest_buf, + (void *)rec_data_start, + first_section_len); + if (res) { + pr_info("p1 read not end res=%d, request=%d\n", + res, first_section_len); + copy_ok = 0; + + p_userdata_rec->rec_len -= + first_section_len - res; + p_userdata_rec->rec_start += + first_section_len - res; + puserdata_para->data_size = + first_section_len - res; + } else { + res = (u32)copy_to_user( + (void *)(pdest_buf+first_section_len), + (void *)hw->userdata_info.data_buf, + data_size - first_section_len); + if (res) { + pr_info("p2 read not end res=%d, request=%d\n", + res, data_size); + copy_ok = 0; + } + p_userdata_rec->rec_len -= + data_size - res; + p_userdata_rec->rec_start = + data_size - first_section_len - res; + puserdata_para->data_size = + data_size - res; + } + } else { + res = (u32)copy_to_user((void *)pdest_buf, + (void *)rec_data_start, + data_size); + if (res) { + pr_info("p3 read not end res=%d, request=%d\n", + res, data_size); + copy_ok = 0; + } + p_userdata_rec->rec_len -= data_size - res; + p_userdata_rec->rec_start += data_size - res; + puserdata_para->data_size = data_size - res; + } + + if (copy_ok) { + hw->userdata_info.read_index++; + if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM) + hw->userdata_info.read_index = 0; + } + } else { + /* dvb user data buffer is not enought + to copy the whole recored. */ + data_size = puserdata_para->buf_len; + if (rec_data_start + data_size + > hw->userdata_info.data_buf_end) { + int first_section_len; + + first_section_len = hw->userdata_info.buf_len - + p_userdata_rec->rec_start; + res = (u32)copy_to_user((void *)pdest_buf, + (void *)rec_data_start, + first_section_len); + if (res) { + pr_info("p4 read not end res=%d, request=%d\n", + res, first_section_len); + copy_ok = 0; + p_userdata_rec->rec_len -= + first_section_len - res; + p_userdata_rec->rec_start += + first_section_len - res; + puserdata_para->data_size = + first_section_len - res; + } else { + /* first secton copy is ok*/ + res = (u32)copy_to_user( + (void *)(pdest_buf+first_section_len), + (void *)hw->userdata_info.data_buf, + data_size - first_section_len); + if (res) { + pr_info("p5 read not end res=%d, request=%d\n", + res, + data_size - first_section_len); + copy_ok = 0; + } + + p_userdata_rec->rec_len -= + data_size - res; + p_userdata_rec->rec_start = + data_size - first_section_len - res; + puserdata_para->data_size = + data_size - res; + } + } else { + res = (u32)copy_to_user((void *)pdest_buf, + (void *)rec_data_start, + data_size); + if (res) { + pr_info("p6 read not end res=%d, request=%d\n", + res, data_size); + copy_ok = 0; + } + + p_userdata_rec->rec_len -= data_size - res; + p_userdata_rec->rec_start += data_size - res; + puserdata_para->data_size = data_size - res; + } + + if (copy_ok) { + hw->userdata_info.read_index++; + if (hw->userdata_info.read_index >= USERDATA_FIFO_NUM) + hw->userdata_info.read_index = 0; + } + + } + res = (u32)copy_to_user((void *)&puserdata_para->meta_info, + (void *)&p_userdata_rec->meta_info, + sizeof(p_userdata_rec->meta_info)); + + if (hw->userdata_info.read_index <= hw->userdata_info.write_index) + puserdata_para->meta_info.records_in_que = + hw->userdata_info.write_index - + hw->userdata_info.read_index; + else + puserdata_para->meta_info.records_in_que = + hw->userdata_info.write_index + + USERDATA_FIFO_NUM - + hw->userdata_info.read_index; + + puserdata_para->version = (0<<24|0<<16|0<<8|1); + + mutex_unlock(&hw->userdata_mutex); + + return 1; +} + +static void vmh264_reset_userdata_fifo(struct vdec_s *vdec, int bInit) +{ + struct vdec_h264_hw_s *hw = NULL; + + hw = (struct vdec_h264_hw_s *)vdec->private; + + if (hw) { + mutex_lock(&hw->userdata_mutex); + pr_info("vmpeg12_reset_userdata_fifo: bInit: %d, ri: %d, wi: %d\n", + bInit, + hw->userdata_info.read_index, + hw->userdata_info.write_index); + hw->userdata_info.read_index = 0; + hw->userdata_info.write_index = 0; + + if (bInit) + hw->userdata_info.last_wp = 0; + mutex_unlock(&hw->userdata_mutex); + } +} +#endif + +static void user_data_push_work(struct work_struct *work) +{ + struct vdec_h264_hw_s *hw = container_of(work, + struct vdec_h264_hw_s, user_data_work); + + struct userdata_poc_info_t user_data_poc; + unsigned char *pdata; + u8 *pmax_sei_data_buffer; + u8 *sei_data_buf; + int i; +#ifdef MH264_USERDATA_ENABLE + struct userdata_meta_info_t meta_info; + memset(&meta_info, 0, sizeof(meta_info)); +#endif + + pdata = (u8 *)hw->sei_user_data_buffer + hw->sei_user_data_wp; + pmax_sei_data_buffer = (u8 *)hw->sei_user_data_buffer + USER_DATA_SIZE; + sei_data_buf = (u8 *)hw->sei_itu_data_buf; + for (i = 0; i < hw->sei_itu_data_len; i++) { + *pdata++ = sei_data_buf[i]; + if (pdata >= pmax_sei_data_buffer) + pdata = (u8 *)hw->sei_user_data_buffer; + } + + hw->sei_user_data_wp = (hw->sei_user_data_wp + + hw->sei_itu_data_len) % USER_DATA_SIZE; + user_data_poc.poc_number = hw->sei_poc; + + hw->sei_itu_data_len = 0; + +#ifdef MH264_USERDATA_ENABLE + meta_info.duration = hw->frame_dur; + meta_info.flags |= (VFORMAT_H264 << 3); + + + vmh264_input_udc_waitqueue(hw, meta_info, hw->sei_user_data_wp); + +#endif +/* + pr_info("sei_itu35_wp = %d, poc = %d\n", + hw->sei_user_data_wp, hw->sei_poc); +*/ +} + +static void vh264_work(struct work_struct *work) +{ + struct vdec_h264_hw_s *hw = container_of(work, + struct vdec_h264_hw_s, work); + struct vdec_s *vdec = hw_to_vdec(hw); + + /* finished decoding one frame or error, + * notify vdec core to switch context + */ + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL, + "%s dec_result %d %x %x %x\n", + __func__, + hw->dec_result, + READ_VREG(VLD_MEM_VIFIFO_LEVEL), + READ_VREG(VLD_MEM_VIFIFO_WP), + READ_VREG(VLD_MEM_VIFIFO_RP)); + if (!hw->mmu_enable) { + mutex_lock(&vmh264_mutex); + dealloc_buf_specs(hw, 0); + mutex_unlock(&vmh264_mutex); + } + if (hw->dec_result == DEC_RESULT_CONFIG_PARAM) { + u32 param1 = READ_VREG(AV_SCRATCH_1); + u32 param2 = READ_VREG(AV_SCRATCH_2); + u32 param3 = READ_VREG(AV_SCRATCH_6); + u32 param4 = READ_VREG(AV_SCRATCH_B); + if (vh264_set_params(hw, param1, + param2, param3, param4) < 0) + hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW; + WRITE_VREG(AV_SCRATCH_0, (hw->max_reference_size<<24) | + (hw->dpb.mDPB.size<<16) | + (hw->dpb.mDPB.size<<8)); + start_process_time(hw); + return; + } else + if (((hw->dec_result == DEC_RESULT_GET_DATA) || + (hw->dec_result == DEC_RESULT_GET_DATA_RETRY)) + && (hw_to_vdec(hw)->next_status != + VDEC_STATUS_DISCONNECTED)) { + if (!vdec_has_more_input(vdec)) { + hw->dec_result = DEC_RESULT_EOS; + vdec_schedule_work(&hw->work); + return; + } + + if (hw->dec_result == DEC_RESULT_GET_DATA) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS, + "%s DEC_RESULT_GET_DATA %x %x %x\n", + __func__, + READ_VREG(VLD_MEM_VIFIFO_LEVEL), + READ_VREG(VLD_MEM_VIFIFO_WP), + READ_VREG(VLD_MEM_VIFIFO_RP)); + vdec_vframe_dirty(vdec, hw->chunk); + vdec_clean_input(vdec); + } + if ((hw->dec_result == DEC_RESULT_GET_DATA_RETRY) && + ((1000 * (jiffies - hw->get_data_start_time) / HZ) + > get_data_timeout_val)) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS, + "%s DEC_RESULT_GET_DATA_RETRY timeout\n", + __func__); + goto result_done; + } + if (is_buffer_available(vdec)) { + int r; + int decode_size; + r = vdec_prepare_input(vdec, &hw->chunk); + if (r < 0) { + hw->dec_result = DEC_RESULT_GET_DATA_RETRY; + + dpb_print(DECODE_ID(hw), + PRINT_FLAG_VDEC_DETAIL, + "vdec_prepare_input: Insufficient data\n"); + + vdec_schedule_work(&hw->work); + return; + } + hw->dec_result = DEC_RESULT_NONE; + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS, + "%s: chunk size 0x%x\n", + __func__, hw->chunk->size); + + if (dpb_is_debug(DECODE_ID(hw), + PRINT_FRAMEBASE_DATA)) { + int jj; + u8 *data = + ((u8 *)hw->chunk->block->start_virt) + + hw->chunk->offset; + for (jj = 0; jj < r; jj++) { + if ((jj & 0xf) == 0) + dpb_print(DECODE_ID(hw), + PRINT_FRAMEBASE_DATA, + "%06x:", jj); + dpb_print_cont(DECODE_ID(hw), + PRINT_FRAMEBASE_DATA, + "%02x ", data[jj]); + if (((jj + 1) & 0xf) == 0) + dpb_print_cont(DECODE_ID(hw), + PRINT_FRAMEBASE_DATA, + "\n"); + } + } + WRITE_VREG(POWER_CTL_VLD, + READ_VREG(POWER_CTL_VLD) | + (0 << 10) | (1 << 9) | (1 << 6)); + WRITE_VREG(H264_DECODE_INFO, (1<<13)); + decode_size = hw->chunk->size + + (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1)); + WRITE_VREG(H264_DECODE_SIZE, decode_size); + WRITE_VREG(VIFF_BIT_CNT, decode_size * 8); + vdec_enable_input(vdec); + + WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); + start_process_time(hw); + } else{ + hw->dec_result = DEC_RESULT_GET_DATA_RETRY; + vdec_schedule_work(&hw->work); + } + return; + } else if (hw->dec_result == DEC_RESULT_DONE) { + /* if (!hw->ctx_valid) + hw->ctx_valid = 1; */ +result_done: + if (hw->mmu_enable + && hw->frame_busy && hw->frame_done) { + long used_4k_num; + hevc_sao_wait_done(hw); + if (hw->hevc_cur_buf_idx != 0xffff) { + used_4k_num = + (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16); + if (used_4k_num >= 0) + dpb_print(DECODE_ID(hw), + PRINT_FLAG_MMU_DETAIL, + "release unused buf , used_4k_num %ld index %d\n", + used_4k_num, hw->hevc_cur_buf_idx); + + decoder_mmu_box_free_idx_tail( + hw->mmu_box, + hw->hevc_cur_buf_idx, + used_4k_num); + hw->hevc_cur_buf_idx = 0xffff; + } + } + decode_frame_count[DECODE_ID(hw)]++; + amvdec_stop(); + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS, + "%s dec_result %d %x %x %x\n", + __func__, + hw->dec_result, + READ_VREG(VLD_MEM_VIFIFO_LEVEL), + READ_VREG(VLD_MEM_VIFIFO_WP), + READ_VREG(VLD_MEM_VIFIFO_RP)); + vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk); + } else if (hw->dec_result == DEC_RESULT_AGAIN) { + /* + stream base: stream buf empty or timeout + frame base: vdec_prepare_input fail + */ + if (!vdec_has_more_input(vdec)) { + hw->dec_result = DEC_RESULT_EOS; + vdec_schedule_work(&hw->work); + return; + } + hw->next_again_flag = 1; + } else if (hw->dec_result == DEC_RESULT_EOS) { + struct h264_dpb_stru *p_H264_Dpb = &hw->dpb; + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS, + "%s: end of stream\n", + __func__); + amvdec_stop(); + if (hw->mmu_enable) + amhevc_stop(); + hw->eos = 1; + flush_dpb(p_H264_Dpb); + vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk); + } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) { + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS, + "%s: force exit\n", + __func__); + amvdec_stop(); + if (hw->mmu_enable) + amhevc_stop(); + if (hw->stat & STAT_ISR_REG) { + WRITE_VREG(ASSIST_MBOX1_MASK, 0); + vdec_free_irq(VDEC_IRQ_1, (void *)hw); + hw->stat &= ~STAT_ISR_REG; + } + } + + del_timer_sync(&hw->check_timer); + hw->stat &= ~STAT_TIMER_ARM; + + /* mark itself has all HW resource released and input released */ + vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_CONNECTED); + +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + if (hw->switch_dvlayer_flag) { + if (vdec->slave) + vdec_set_next_sched(vdec, vdec->slave); + else if (vdec->master) + vdec_set_next_sched(vdec, vdec->master); + } else if (vdec->slave || vdec->master) + vdec_set_next_sched(vdec, vdec); +#endif + + /* mark itself has all HW resource released and input released */ + vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC); + + if (hw->vdec_cb) + hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg); +} + +static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask) +{ + bool ret = 0; + struct vdec_h264_hw_s *hw = + (struct vdec_h264_hw_s *)vdec->private; + + + if (vdec_stream_based(vdec) && (hw->init_flag == 0) + && pre_decode_buf_level != 0) { + u32 rp, wp, level; + + rp = READ_PARSER_REG(PARSER_VIDEO_RP); + wp = READ_PARSER_REG(PARSER_VIDEO_WP); + if (wp < rp) + level = vdec->input.size + wp - rp; + else + level = wp - rp; + + if (level < pre_decode_buf_level) + return 0; + } + +#ifndef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + if (vdec->master) + return 0; +#endif + if (hw->eos) + return 0; + + if (disp_vframe_valve_level && + kfifo_len(&hw->display_q) >= + disp_vframe_valve_level) { + hw->valve_count--; + if (hw->valve_count <= 0) + hw->valve_count = 2; + else + return 0; + } + if (hw->next_again_flag && + (!vdec_frame_based(vdec))) { + u32 parser_wr_ptr = + READ_PARSER_REG(PARSER_VIDEO_WP); + if (parser_wr_ptr >= hw->pre_parser_wr_ptr && + (parser_wr_ptr - hw->pre_parser_wr_ptr) < + again_threshold) + return 0; + } + + if (h264_debug_flag & 0x20000000) { + /* pr_info("%s, a\n", __func__); */ + ret = 1; + } else + ret = is_buffer_available(vdec); + + if (ret) + not_run_ready[DECODE_ID(hw)] = 0; + else + not_run_ready[DECODE_ID(hw)]++; + return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0; +} + +static unsigned char get_data_check_sum + (struct vdec_h264_hw_s *hw, int size) +{ + int jj; + int sum = 0; + u8 *data = ((u8 *)hw->chunk->block->start_virt) + + hw->chunk->offset; + for (jj = 0; jj < size; jj++) + sum += data[jj]; + return sum; +} + +static void run(struct vdec_s *vdec, unsigned long mask, + void (*callback)(struct vdec_s *, void *), void *arg) +{ + struct vdec_h264_hw_s *hw = + (struct vdec_h264_hw_s *)vdec->private; + struct h264_dpb_stru *p_H264_Dpb = &hw->dpb; + int size; + + run_count[DECODE_ID(hw)]++; + if (hw->mmu_enable) + hevc_reset_core(vdec); + hw->vdec_cb_arg = arg; + hw->vdec_cb = callback; + + if (kfifo_len(&hw->display_q) > VF_POOL_SIZE) { + hw->reset_bufmgr_flag = 1; + dpb_print(DECODE_ID(hw), 0, + "kfifo len:%d invaild, need bufmgr reset\n", + kfifo_len(&hw->display_q)); + } + + hw->pre_parser_wr_ptr = + READ_PARSER_REG(PARSER_VIDEO_WP); + hw->next_again_flag = 0; + + if (hw->reset_bufmgr_flag || + ((error_proc_policy & 0x40) && + p_H264_Dpb->buf_alloc_fail)) { + h264_reset_bufmgr(vdec); + hw->reset_bufmgr_flag = 0; + } + + if (h264_debug_cmd & 0xf000) { + if (((h264_debug_cmd >> 12) & 0xf) + == (DECODE_ID(hw) + 1)) { + h264_reconfig(hw); + h264_debug_cmd &= (~0xf000); + } + } + /* hw->chunk = vdec_prepare_input(vdec); */ +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + if (vdec->slave || vdec->master) + vdec_set_flag(vdec, VDEC_FLAG_SELF_INPUT_CONTEXT); +#endif + size = vdec_prepare_input(vdec, &hw->chunk); + if ((size < 0) || + (input_frame_based(vdec) && hw->chunk == NULL)) { + input_empty[DECODE_ID(hw)]++; + hw->dec_result = DEC_RESULT_AGAIN; + + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_DETAIL, + "vdec_prepare_input: Insufficient data\n"); + + vdec_schedule_work(&hw->work); + return; + } + input_empty[DECODE_ID(hw)] = 0; + + hw->dec_result = DEC_RESULT_NONE; + hw->get_data_count = 0; +#if 0 + pr_info("VLD_MEM_VIFIFO_LEVEL = 0x%x, rp = 0x%x, wp = 0x%x\n", + READ_VREG(VLD_MEM_VIFIFO_LEVEL), + READ_VREG(VLD_MEM_VIFIFO_RP), + READ_VREG(VLD_MEM_VIFIFO_WP)); +#endif + + if (input_frame_based(vdec)) { + u8 *data = ((u8 *)hw->chunk->block->start_virt) + + hw->chunk->offset; + if (dpb_is_debug(DECODE_ID(hw), + PRINT_FLAG_VDEC_STATUS) + ) { + dpb_print(DECODE_ID(hw), 0, + "%s: size 0x%x sum 0x%x %02x %02x %02x %02x %02x %02x .. %02x %02x %02x %02x\n", + __func__, size, get_data_check_sum(hw, size), + data[0], data[1], data[2], data[3], + data[4], data[5], data[size - 4], + data[size - 3], data[size - 2], + data[size - 1]); + } + if (dpb_is_debug(DECODE_ID(hw), + PRINT_FRAMEBASE_DATA) + ) { + int jj; + u8 *data = + ((u8 *)hw->chunk->block->start_virt) + + hw->chunk->offset; + for (jj = 0; jj < size; jj++) { + if ((jj & 0xf) == 0) + dpb_print(DECODE_ID(hw), + PRINT_FRAMEBASE_DATA, + "%06x:", jj); + dpb_print_cont(DECODE_ID(hw), + PRINT_FRAMEBASE_DATA, + "%02x ", data[jj]); + if (((jj + 1) & 0xf) == 0) + dpb_print_cont(DECODE_ID(hw), + PRINT_FRAMEBASE_DATA, + "\n"); + } + } + + } else + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS, + "%s: %x %x %x %x %x size 0x%x\n", + __func__, + READ_VREG(VLD_MEM_VIFIFO_LEVEL), + READ_VREG(VLD_MEM_VIFIFO_WP), + READ_VREG(VLD_MEM_VIFIFO_RP), + READ_PARSER_REG(PARSER_VIDEO_RP), + READ_PARSER_REG(PARSER_VIDEO_WP), + size); + + start_process_time(hw); + + if (tee_enabled()) { + if (tee_load_video_fw(VIDEO_DEC_H264_MULTI, 0) != 0) { + amvdec_enable_flag = false; + amvdec_disable(); + dpb_print(DECODE_ID(hw), 0, "%s: Error amvdec_vdec_loadmc fail\n", __func__); + return; + } + if (hw->mmu_enable) { + if (tee_load_video_fw(VIDEO_DEC_H264_MULTI_MMU, + OPTEE_VDEC_HEVC) < 0) { + amvdec_enable_flag = false; + amhevc_disable(); + dpb_print(DECODE_ID(hw), 0, "tee mmu fw load fail\n"); + return; + } + } + + } else { + if (amvdec_vdec_loadmc_ex(vdec, NULL, hw->fw->data) < 0) { + amvdec_enable_flag = false; + amvdec_disable(); + dpb_print(DECODE_ID(hw), 0, "%s: Error amvdec_vdec_loadmc fail\n", __func__); + return; + } + if (hw->mmu_enable) { + if (amhevc_loadmc_ex(VFORMAT_HEVC, + NULL, hw->fw_mmu->data) < 0) { + amvdec_enable_flag = false; + amhevc_disable(); + dpb_print(DECODE_ID(hw), 0, "mmu fw load fail\n"); + return; + } + } + } + + vmh264_reset_udr_mgr(hw); + + if (vh264_hw_ctx_restore(hw) < 0) { + vdec_schedule_work(&hw->work); + return; + } + if (input_frame_based(vdec)) { + int decode_size = hw->chunk->size + + (hw->chunk->offset & (VDEC_FIFO_ALIGN - 1)); + WRITE_VREG(H264_DECODE_INFO, (1<<13)); + WRITE_VREG(H264_DECODE_SIZE, decode_size); + WRITE_VREG(VIFF_BIT_CNT, decode_size * 8); + } else { + if (size <= 0) + size = 0x7fffffff; /*error happen*/ + WRITE_VREG(H264_DECODE_INFO, (1<<13)); + WRITE_VREG(H264_DECODE_SIZE, size); + WRITE_VREG(VIFF_BIT_CNT, size * 8); + } + config_aux_buf(hw); + config_decode_mode(hw); + vdec_enable_input(vdec); + WRITE_VREG(NAL_SEARCH_CTL, 0); + if (enable_itu_t35) + WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x1); + if (!hw->init_flag) { + if (hw->mmu_enable) + WRITE_VREG(NAL_SEARCH_CTL, + READ_VREG(NAL_SEARCH_CTL) | 0x2); + else + WRITE_VREG(NAL_SEARCH_CTL, + READ_VREG(NAL_SEARCH_CTL) & (~0x2)); + } + if (udebug_flag) + WRITE_VREG(AV_SCRATCH_K, udebug_flag); + mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL); + + amvdec_start(); + if (hw->mmu_enable /*&& !hw->frame_busy && !hw->frame_done*/) { + WRITE_VREG(HEVC_ASSIST_SCRATCH_0, 0x0); + amhevc_start(); + if (hw->config_bufmgr_done) { + hevc_mcr_sao_global_hw_init(hw, + hw->frame_width, hw->frame_height); + hevc_mcr_config_canv2axitbl(hw, 1); + } + } + + /* if (hw->init_flag) { */ + WRITE_VREG(DPB_STATUS_REG, H264_ACTION_SEARCH_HEAD); + /* } */ + + hw->init_flag = 1; +} + +static void reset(struct vdec_s *vdec) +{ + pr_info("ammvdec_h264: reset.\n"); +} + +static void h264_reconfig(struct vdec_h264_hw_s *hw) +{ + int i; + unsigned long flags; + struct h264_dpb_stru *p_H264_Dpb = &hw->dpb; + dpb_print(DECODE_ID(hw), 0, + "%s\n", __func__); + /* after calling flush_dpb() and bufmgr_h264_remove_unused_frame(), + all buffers are in display queue (used == 2), + or free (used == 0) + */ + if (dpb_is_debug(DECODE_ID(hw), + PRINT_FLAG_DUMP_BUFSPEC)) + dump_bufspec(hw, "pre h264_reconfig"); + + flush_dpb(p_H264_Dpb); + bufmgr_h264_remove_unused_frame(p_H264_Dpb, 0); + + if (hw->collocate_cma_alloc_addr) { + decoder_bmmu_box_free_idx( + hw->bmmu_box, + BMMU_REF_IDX); + hw->collocate_cma_alloc_addr = 0; + hw->dpb.colocated_mv_addr_start = 0; + hw->dpb.colocated_mv_addr_end = 0; + } + spin_lock_irqsave(&hw->bufspec_lock, flags); + for (i = 0; i < BUFSPEC_POOL_SIZE; i++) { + /*make sure buffers not put back to bufmgr when + vf_put is called*/ + if (hw->buffer_spec[i].used == 2) + hw->buffer_spec[i].used = 3; + + /* ready to release "free buffers" + */ + if (hw->buffer_spec[i].used == 0) + hw->buffer_spec[i].used = 4; + + hw->buffer_spec[i].canvas_pos = -1; + } + spin_unlock_irqrestore(&hw->bufspec_lock, flags); + hw->has_i_frame = 0; + hw->config_bufmgr_done = 0; + + if (dpb_is_debug(DECODE_ID(hw), + PRINT_FLAG_DUMP_BUFSPEC)) + dump_bufspec(hw, "after h264_reconfig"); + +} + +#ifdef ERROR_HANDLE_TEST +static void h264_clear_dpb(struct vdec_h264_hw_s *hw) +{ + int i; + struct h264_dpb_stru *p_H264_Dpb = &hw->dpb; + dpb_print(DECODE_ID(hw), PRINT_FLAG_VDEC_STATUS, + "%s\n", __func__); + remove_dpb_pictures(p_H264_Dpb); + for (i = 0; i < BUFSPEC_POOL_SIZE; i++) { + /*make sure buffers not put back to bufmgr when + vf_put is called*/ + if (hw->buffer_spec[i].used == 2) + hw->buffer_spec[i].used = 5; + } + +} +#endif + +static void h264_reset_bufmgr(struct vdec_s *vdec) +{ + int i; + struct vdec_h264_hw_s *hw = (struct vdec_h264_hw_s *)vdec->private; +#if 0 + struct h264_dpb_stru *p_H264_Dpb = &hw->dpb; + int actual_dpb_size, max_reference_size; + int reorder_pic_num; + unsigned int colocated_buf_size; + unsigned int colocated_mv_addr_start; + unsigned int colocated_mv_addr_end; + dpb_print(DECODE_ID(hw), 0, + "%s\n", __func__); + + for (i = 0; i < VF_POOL_SIZE; i++) + hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */ + + actual_dpb_size = p_H264_Dpb->mDPB.size; + max_reference_size = p_H264_Dpb->max_reference_size; + reorder_pic_num = p_H264_Dpb->reorder_pic_num; + + colocated_buf_size = p_H264_Dpb->colocated_buf_size; + colocated_mv_addr_start = p_H264_Dpb->colocated_mv_addr_start; + colocated_mv_addr_end = p_H264_Dpb->colocated_mv_addr_end; + + hw->cur_pool++; + if (hw->cur_pool >= VF_POOL_NUM) + hw->cur_pool = 0; + + INIT_KFIFO(hw->display_q); + INIT_KFIFO(hw->newframe_q); + + for (i = 0; i < VF_POOL_SIZE; i++) { + const struct vframe_s *vf = &(hw->vfpool[hw->cur_pool][i]); + hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */ + hw->vfpool[hw->cur_pool][i].bufWidth = 1920; + kfifo_put(&hw->newframe_q, vf); + } + + for (i = 0; i < BUFSPEC_POOL_SIZE; i++) + hw->buffer_spec[i].used = 0; + + dpb_init_global(&hw->dpb, + DECODE_ID(hw), 0, 0); + p_H264_Dpb->mDPB.size = actual_dpb_size; + p_H264_Dpb->max_reference_size = max_reference_size; + p_H264_Dpb->reorder_pic_num = reorder_pic_num; + + p_H264_Dpb->colocated_buf_size = colocated_buf_size; + p_H264_Dpb->colocated_mv_addr_start = colocated_mv_addr_start; + p_H264_Dpb->colocated_mv_addr_end = colocated_mv_addr_end; + + p_H264_Dpb->fast_output_enable = fast_output_enable; + hw->has_i_frame = 0; +#else + dpb_print(DECODE_ID(hw), 0, + "%s frame count %d to skip %d\n\n", + __func__, hw->decode_pic_count+1, + hw->skip_frame_count); + + for (i = 0; i < VF_POOL_SIZE; i++) + hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */ + + hw->cur_pool++; + if (hw->cur_pool >= VF_POOL_NUM) + hw->cur_pool = 0; + + for (i = 0; i < VF_POOL_SIZE; i++) + hw->vfpool[hw->cur_pool][i].index = -1; /* VF_BUF_NUM; */ + + + if (hw->collocate_cma_alloc_addr) { + decoder_bmmu_box_free_idx( + hw->bmmu_box, + BMMU_REF_IDX); + hw->collocate_cma_alloc_addr = 0; + hw->dpb.colocated_mv_addr_start = 0; + hw->dpb.colocated_mv_addr_end = 0; + } + vf_notify_receiver(vdec->vf_provider_name, VFRAME_EVENT_PROVIDER_RESET, NULL); + + dealloc_buf_specs(hw, 1); + buf_spec_init(hw); + + vh264_local_init(hw); + /*hw->decode_pic_count = 0; + hw->seq_info2 = 0;*/ + if (vh264_set_params(hw, + hw->cfg_param1, + hw->cfg_param2, + hw->cfg_param3, + hw->cfg_param4) < 0) + hw->stat |= DECODER_FATAL_ERROR_SIZE_OVERFLOW; + hw->init_flag = 1; + hw->reset_bufmgr_count++; +#endif + +} + +int ammvdec_h264_mmu_init(struct vdec_h264_hw_s *hw) +{ + int ret = -1; + int tvp_flag = vdec_secure(hw_to_vdec(hw)) ? + CODEC_MM_FLAGS_TVP : 0; + + pr_debug("ammvdec_h264_mmu_init tvp = 0x%x mmu_enable %d\n", + tvp_flag, hw->mmu_enable); + if (hw->mmu_enable && !hw->mmu_box) { + hw->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME, + hw->id, + MMU_MAX_BUFFERS, + 64 * SZ_1M, + tvp_flag); + if (!hw->mmu_box) { + pr_err("h264 4k alloc mmu box failed!!\n"); + return -1; + } + ret = 0; + } + if (!hw->bmmu_box) { + hw->bmmu_box = decoder_bmmu_box_alloc_box( + DRIVER_NAME, + hw->id, + BMMU_MAX_BUFFERS, + 4 + PAGE_SHIFT, + CODEC_MM_FLAGS_CMA_CLEAR | + CODEC_MM_FLAGS_FOR_VDECODER | + tvp_flag); + if (hw->bmmu_box) + ret = 0; + } + return ret; +} +int ammvdec_h264_mmu_release(struct vdec_h264_hw_s *hw) +{ + if (hw->mmu_box) { + decoder_mmu_box_free(hw->mmu_box); + hw->mmu_box = NULL; + } + if (hw->bmmu_box) { + decoder_bmmu_box_free(hw->bmmu_box); + hw->bmmu_box = NULL; + } + return 0; +} + +static int ammvdec_h264_probe(struct platform_device *pdev) +{ + struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; + struct vdec_h264_hw_s *hw = NULL; + char *tmpbuf; + int config_val; + + if (pdata == NULL) { + pr_info("\nammvdec_h264 memory resource undefined.\n"); + return -EFAULT; + } + + hw = (struct vdec_h264_hw_s *)h264_alloc_hw_stru(&pdev->dev, + sizeof(struct vdec_h264_hw_s), GFP_KERNEL); + if (hw == NULL) { + pr_info("\nammvdec_h264 device data allocation failed\n"); + return -ENOMEM; + } + hw->id = pdev->id; + hw->platform_dev = pdev; + platform_set_drvdata(pdev, pdata); + + hw->mmu_enable = 0; + if (force_enable_mmu && pdata->sys_info && + (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXLX) && + (get_cpu_type() != MESON_CPU_MAJOR_ID_GXLX) && + (get_cpu_type() != MESON_CPU_MAJOR_ID_G12A) && + (get_cpu_type() != MESON_CPU_MAJOR_ID_G12B) && + (pdata->sys_info->height * pdata->sys_info->width + > 1920 * 1088)) + hw->mmu_enable = 1; + if (ammvdec_h264_mmu_init(hw)) { + h264_free_hw_stru(&pdev->dev, (void *)hw); + pr_info("\nammvdec_h264 mmu alloc failed!\n"); + return -ENOMEM; + } + + if (hw->mmu_enable) { + if (pdata->config && pdata->config_len) { + /*use ptr config for doubel_write_mode, etc*/ + if (get_config_int(pdata->config, + "mh264_double_write_mode", &config_val) == 0) + hw->double_write_mode = config_val; + else + hw->double_write_mode = double_write_mode; + } else + hw->double_write_mode = double_write_mode; + } else + hw->double_write_mode = 0; + + dpb_print(DECODE_ID(hw), 0, + "%s mmu_enable %d double_write_mode %d\n", + __func__, hw->mmu_enable, hw->double_write_mode); + + pdata->private = hw; + pdata->dec_status = dec_status; + pdata->set_trickmode = vmh264_set_trickmode; + pdata->run_ready = run_ready; + pdata->run = run; + pdata->reset = reset; + pdata->irq_handler = vh264_isr; + pdata->threaded_irq_handler = vh264_isr_thread_fn; + pdata->dump_state = vmh264_dump_state; + +#ifdef MH264_USERDATA_ENABLE + pdata->user_data_read = vmh264_user_data_read; + pdata->reset_userdata_fifo = vmh264_reset_userdata_fifo; +#else + pdata->user_data_read = NULL; + pdata->reset_userdata_fifo = NULL; +#endif + if (pdata->use_vfm_path) + snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE, + VFM_DEC_PROVIDER_NAME); +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + else if (vdec_dual(pdata)) { + if (dv_toggle_prov_name) /*debug purpose*/ + snprintf(pdata->vf_provider_name, + VDEC_PROVIDER_NAME_SIZE, + (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME : + VFM_DEC_DVEL_PROVIDER_NAME); + else + snprintf(pdata->vf_provider_name, + VDEC_PROVIDER_NAME_SIZE, + (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME : + VFM_DEC_DVBL_PROVIDER_NAME); + } +#endif + else + snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE, + PROVIDER_NAME ".%02x", pdev->id & 0xff); + + vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name, + &vf_provider_ops, pdata); + + platform_set_drvdata(pdev, pdata); + + buf_spec_init(hw); + + hw->platform_dev = pdev; + +#ifdef DUMP_USERDATA_RECORD + vmh264_init_userdata_dump(); + vmh264_reset_user_data_buf(); +#endif + if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_DPB_IDX, + V_BUF_ADDR_OFFSET, DRIVER_NAME, &hw->cma_alloc_addr) < 0) { + h264_free_hw_stru(&pdev->dev, (void *)hw); + return -ENOMEM; + } + + hw->buf_offset = hw->cma_alloc_addr - DEF_BUF_START_ADDR + + DCAC_READ_MARGIN; + if (hw->mmu_enable) + if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_EXTIF_IDX, + EXTIF_BUF_SIZE, DRIVER_NAME, &hw->extif_addr) < 0) { + h264_free_hw_stru(&pdev->dev, (void *)hw); + return -ENOMEM; + } + if (!vdec_secure(pdata)) { +#if 1 + /*init internal buf*/ + tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr); + memset(tmpbuf, 0, V_BUF_ADDR_OFFSET); + dma_sync_single_for_device(amports_get_dma_device(), + hw->cma_alloc_addr, + V_BUF_ADDR_OFFSET, DMA_TO_DEVICE); +#else + /*init sps/pps internal buf 64k*/ + tmpbuf = (char *)codec_mm_phys_to_virt(hw->cma_alloc_addr + + (mem_sps_base - DEF_BUF_START_ADDR)); + memset(tmpbuf, 0, 0x10000); + dma_sync_single_for_device(amports_get_dma_device(), + hw->cma_alloc_addr + + (mem_sps_base - DEF_BUF_START_ADDR), + 0x10000, DMA_TO_DEVICE); +#endif + } + /**/ + + if (pdata->sys_info) + hw->vh264_amstream_dec_info = *pdata->sys_info; +#if 0 + if (NULL == hw->sei_data_buffer) { + hw->sei_data_buffer = + dma_alloc_coherent(amports_get_dma_device(), + USER_DATA_SIZE, + &hw->sei_data_buffer_phys, GFP_KERNEL); + if (!hw->sei_data_buffer) { + pr_info("%s: Can not allocate sei_data_buffer\n", + __func__); + ammvdec_h264_mmu_release(hw); + h264_free_hw_stru(&pdev->dev, (void *)hw); + return -ENOMEM; + } + /* pr_info("buffer 0x%x, phys 0x%x, remap 0x%x\n", + sei_data_buffer, sei_data_buffer_phys, + (u32)sei_data_buffer_remap); */ + } +#endif + pr_debug("ammvdec_h264 mem-addr=%lx,buff_offset=%x,buf_start=%lx\n", + pdata->mem_start, hw->buf_offset, hw->cma_alloc_addr); + + + vdec_source_changed(VFORMAT_H264, 3840, 2160, 60); + + if (vh264_init(hw) < 0) { + pr_info("\nammvdec_h264 init failed.\n"); + ammvdec_h264_mmu_release(hw); + h264_free_hw_stru(&pdev->dev, (void *)hw); + return -ENODEV; + } +#ifdef MH264_USERDATA_ENABLE + vmh264_crate_userdata_manager(hw, + hw->sei_user_data_buffer, + USER_DATA_SIZE); +#endif + + vdec_set_prepare_level(pdata, start_decode_buf_level); + + vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC + | CORE_MASK_COMBINE); + + atomic_set(&hw->vh264_active, 1); + + return 0; +} + +static int ammvdec_h264_remove(struct platform_device *pdev) +{ + struct vdec_h264_hw_s *hw = + (struct vdec_h264_hw_s *) + (((struct vdec_s *)(platform_get_drvdata(pdev)))->private); + int i; + + for (i = 0; i < BUFSPEC_POOL_SIZE; i++) + release_aux_data(hw, i); + + atomic_set(&hw->vh264_active, 0); + + if (hw->stat & STAT_TIMER_ARM) { + del_timer_sync(&hw->check_timer); + hw->stat &= ~STAT_TIMER_ARM; + } + + vh264_stop(hw); +#ifdef MH264_USERDATA_ENABLE +#ifdef DUMP_USERDATA_RECORD + vmh264_dump_userdata(); +#endif + vmh264_destroy_userdata_manager(hw); +#endif + /* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */ + + atomic_set(&hw->vh264_active, 0); + + vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC); + + vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED); + ammvdec_h264_mmu_release(hw); + h264_free_hw_stru(&pdev->dev, (void *)hw); + return 0; +} + +/****************************************/ + +static struct platform_driver ammvdec_h264_driver = { + .probe = ammvdec_h264_probe, + .remove = ammvdec_h264_remove, +#ifdef CONFIG_PM + .suspend = amvdec_suspend, + .resume = amvdec_resume, +#endif + .driver = { + .name = DRIVER_NAME, + } +}; + +static struct codec_profile_t ammvdec_h264_profile = { + .name = "mh264", + .profile = "" +}; + +static struct mconfig hm264_configs[] = { + MC_PU32("h264_debug_flag", &h264_debug_flag), + MC_PI32("start_decode_buf_level", &start_decode_buf_level), + MC_PU32("fixed_frame_rate_mode", &fixed_frame_rate_mode), + MC_PU32("decode_timeout_val", &decode_timeout_val), + MC_PU32("reorder_dpb_size_margin", &reorder_dpb_size_margin), + MC_PU32("reference_buf_margin", &reference_buf_margin), + MC_PU32("radr", &radr), + MC_PU32("rval", &rval), + MC_PU32("h264_debug_mask", &h264_debug_mask), + MC_PU32("h264_debug_cmd", &h264_debug_cmd), + MC_PI32("force_rate_streambase", &force_rate_streambase), + MC_PI32("dec_control", &dec_control), + MC_PI32("force_rate_framebase", &force_rate_framebase), + MC_PI32("force_disp_bufspec_num", &force_disp_bufspec_num), + MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size), + MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size), +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + MC_PU32("reorder_dpb_size_margin_dv", &reorder_dpb_size_margin_dv), + MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name), + MC_PU32("dolby_meta_with_el", &dolby_meta_with_el), +#endif + MC_PU32("i_only_flag", &i_only_flag), + MC_PU32("force_rate_streambase", &force_rate_streambase), +}; +static struct mconfig_node hm264_node; + + +static int __init ammvdec_h264_driver_init_module(void) +{ + pr_info("ammvdec_h264 module init\n"); + if (platform_driver_register(&ammvdec_h264_driver)) { + pr_info("failed to register ammvdec_h264 driver\n"); + return -ENODEV; + } + + if (vdec_is_support_4k()) { + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXLX) { + ammvdec_h264_profile.profile = + "4k, dwrite, compressed"; + } else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { + ammvdec_h264_profile.profile = "4k"; + } + } + + vcodec_profile_register(&ammvdec_h264_profile); + INIT_REG_NODE_CONFIGS("media.decoder", &hm264_node, + "mh264", hm264_configs, CONFIG_FOR_RW); + return 0; +} + +static void __exit ammvdec_h264_driver_remove_module(void) +{ + pr_info("ammvdec_h264 module remove.\n"); + + platform_driver_unregister(&ammvdec_h264_driver); +} + +/****************************************/ + +module_param(h264_debug_flag, uint, 0664); +MODULE_PARM_DESC(h264_debug_flag, "\n ammvdec_h264 h264_debug_flag\n"); + +module_param(start_decode_buf_level, int, 0664); +MODULE_PARM_DESC(start_decode_buf_level, + "\n ammvdec_h264 start_decode_buf_level\n"); + +module_param(pre_decode_buf_level, int, 0664); +MODULE_PARM_DESC(pre_decode_buf_level, "\n ammvdec_h264 pre_decode_buf_level\n"); + +module_param(fixed_frame_rate_mode, uint, 0664); +MODULE_PARM_DESC(fixed_frame_rate_mode, "\namvdec_h264 fixed_frame_rate_mode\n"); + +module_param(decode_timeout_val, uint, 0664); +MODULE_PARM_DESC(decode_timeout_val, "\n amvdec_h264 decode_timeout_val\n"); + +module_param(errordata_timeout_val, uint, 0664); +MODULE_PARM_DESC(errordata_timeout_val, "\n amvdec_h264 errordata_timeout_val\n"); + +module_param(get_data_timeout_val, uint, 0664); +MODULE_PARM_DESC(get_data_timeout_val, "\n amvdec_h264 get_data_timeout_val\n"); + +module_param(frame_max_data_packet, uint, 0664); +MODULE_PARM_DESC(frame_max_data_packet, "\n amvdec_h264 frame_max_data_packet\n"); + +module_param(reorder_dpb_size_margin, uint, 0664); +MODULE_PARM_DESC(reorder_dpb_size_margin, "\n ammvdec_h264 reorder_dpb_size_margin\n"); + +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION +module_param(reorder_dpb_size_margin_dv, uint, 0664); +MODULE_PARM_DESC(reorder_dpb_size_margin_dv, + "\n ammvdec_h264 reorder_dpb_size_margin_dv\n"); +#endif + +module_param(reference_buf_margin, uint, 0664); +MODULE_PARM_DESC(reference_buf_margin, "\n ammvdec_h264 reference_buf_margin\n"); + +module_param(radr, uint, 0664); +MODULE_PARM_DESC(radr, "\nradr\n"); + +module_param(rval, uint, 0664); +MODULE_PARM_DESC(rval, "\nrval\n"); + +module_param(h264_debug_mask, uint, 0664); +MODULE_PARM_DESC(h264_debug_mask, "\n amvdec_h264 h264_debug_mask\n"); + +module_param(h264_debug_cmd, uint, 0664); +MODULE_PARM_DESC(h264_debug_cmd, "\n amvdec_h264 h264_debug_cmd\n"); + +module_param(force_rate_streambase, int, 0664); +MODULE_PARM_DESC(force_rate_streambase, "\n amvdec_h264 force_rate_streambase\n"); + +module_param(dec_control, int, 0664); +MODULE_PARM_DESC(dec_control, "\n amvdec_h264 dec_control\n"); + +module_param(force_rate_framebase, int, 0664); +MODULE_PARM_DESC(force_rate_framebase, "\n amvdec_h264 force_rate_framebase\n"); + +module_param(force_disp_bufspec_num, int, 0664); +MODULE_PARM_DESC(force_disp_bufspec_num, "\n amvdec_h264 force_disp_bufspec_num\n"); + +module_param(V_BUF_ADDR_OFFSET, int, 0664); +MODULE_PARM_DESC(V_BUF_ADDR_OFFSET, "\n amvdec_h264 V_BUF_ADDR_OFFSET\n"); + +module_param(prefix_aux_buf_size, uint, 0664); +MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n"); + +module_param(suffix_aux_buf_size, uint, 0664); +MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n"); + +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION +module_param(dv_toggle_prov_name, uint, 0664); +MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n"); + +module_param(dolby_meta_with_el, uint, 0664); +MODULE_PARM_DESC(dolby_meta_with_el, "\n dolby_meta_with_el\n"); + +#endif + +module_param(fast_output_enable, uint, 0664); +MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h264 fast_output_enable\n"); + +module_param(error_proc_policy, uint, 0664); +MODULE_PARM_DESC(error_proc_policy, "\n amvdec_h264 error_proc_policy\n"); + +module_param(error_skip_count, uint, 0664); +MODULE_PARM_DESC(error_skip_count, "\n amvdec_h264 error_skip_count\n"); + +module_param(force_sliding_margin, uint, 0664); +MODULE_PARM_DESC(force_sliding_margin, "\n amvdec_h264 force_sliding_margin\n"); + +module_param(i_only_flag, uint, 0664); +MODULE_PARM_DESC(i_only_flag, "\n amvdec_h264 i_only_flag\n"); + +module_param(first_i_policy, uint, 0664); +MODULE_PARM_DESC(first_i_policy, "\n amvdec_h264 first_i_policy\n"); + +module_param(frmbase_cont_bitlevel, uint, 0664); +MODULE_PARM_DESC(frmbase_cont_bitlevel, + "\n amvdec_h264 frmbase_cont_bitlevel\n"); + +module_param(frmbase_cont_bitlevel2, uint, 0664); +MODULE_PARM_DESC(frmbase_cont_bitlevel2, + "\n amvdec_h264 frmbase_cont_bitlevel\n"); + +module_param(udebug_flag, uint, 0664); +MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n"); + +module_param(udebug_pause_pos, uint, 0664); +MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n"); + +module_param(udebug_pause_val, uint, 0664); +MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n"); + +module_param(udebug_pause_decode_idx, uint, 0664); +MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n"); + +module_param(max_alloc_buf_count, uint, 0664); +MODULE_PARM_DESC(max_alloc_buf_count, "\n amvdec_h264 max_alloc_buf_count\n"); + +module_param(enable_itu_t35, uint, 0664); +MODULE_PARM_DESC(enable_itu_t35, "\n amvdec_h264 enable_itu_t35\n"); + +module_param(endian, uint, 0664); +MODULE_PARM_DESC(endian, "\nrval\n"); + +module_param(mmu_enable, uint, 0664); +MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n"); + +module_param(force_enable_mmu, uint, 0664); +MODULE_PARM_DESC(force_enable_mmu, "\n force_enable_mmu\n"); + +module_param(again_threshold, uint, 0664); +MODULE_PARM_DESC(again_threshold, "\n again_threshold\n"); + + +/* +module_param(trigger_task, uint, 0664); +MODULE_PARM_DESC(trigger_task, "\n amvdec_h264 trigger_task\n"); +*/ +module_param_array(decode_frame_count, uint, &max_decode_instance_num, 0664); + +module_param_array(display_frame_count, uint, &max_decode_instance_num, 0664); + +module_param_array(max_process_time, uint, &max_decode_instance_num, 0664); + +module_param_array(run_count, uint, + &max_decode_instance_num, 0664); + +module_param_array(not_run_ready, uint, + &max_decode_instance_num, 0664); + +module_param_array(input_empty, uint, + &max_decode_instance_num, 0664); + +module_param_array(max_get_frame_interval, uint, + &max_decode_instance_num, 0664); + +module_param_array(step, uint, &max_decode_instance_num, 0664); + +module_param(disp_vframe_valve_level, uint, 0664); +MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n"); + +module_param(double_write_mode, uint, 0664); +MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n"); + +module_param(mem_map_mode, uint, 0664); +MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n"); + +module_init(ammvdec_h264_driver_init_module); +module_exit(ammvdec_h264_driver_remove_module); + +MODULE_DESCRIPTION("AMLOGIC H264 Video Decoder Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/h265/Makefile b/drivers/amlogic/media_modules/frame_provider/decoder/h265/Makefile new file mode 100644 index 000000000000..86b8b8887f15 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/h265/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_AMLOGIC_MEDIA_VDEC_H265) += amvdec_h265.o +amvdec_h265-objs += vh265.o diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/h265/vh265.c b/drivers/amlogic/media_modules/frame_provider/decoder/h265/vh265.c new file mode 100644 index 000000000000..e566b9949bde --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/h265/vh265.c @@ -0,0 +1,10905 @@ +/* + * drivers/amlogic/amports/vh265.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../../stream_input/amports/amports_priv.h" +#include +#include "../utils/decoder_mmu_box.h" +#include "../utils/decoder_bmmu_box.h" +#include "../utils/config_parser.h" +#include "../utils/firmware.h" +#define AGAIN_HAS_THRESHOLD +/*#define TEST_NO_BUF*/ +/*#define HEVC_PIC_STRUCT_SUPPORT*/ +#define MULTI_INSTANCE_SUPPORT +#define USE_UNINIT_SEMA + + /* .buf_size = 0x100000*16, + //4k2k , 0x100000 per buffer */ + /* 4096x2304 , 0x120000 per buffer */ +#define MPRED_MV_BUF_SIZE 0x120000 + +#define MMU_COMPRESS_HEADER_SIZE 0x48000 +#define MAX_FRAME_4K_NUM 0x1200 +#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4) +#define H265_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_7 + +#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009 + +#define HEVC_CM_HEADER_START_ADDR 0x3628 +#define HEVC_SAO_MMU_VH1_ADDR 0x363b +#define HEVC_SAO_MMU_VH0_ADDR 0x363a +#define HEVC_SAO_MMU_STATUS 0x3639 + +#define HEVC_DBLK_CFGB 0x350b +#define HEVCD_MPP_DECOMP_AXIURG_CTL 0x34c7 + + +#define MEM_NAME "codec_265" +/* #include */ +#include + +#include "../utils/vdec.h" +#include "../utils/amvdec.h" +#include +#include + +#define SEND_LMEM_WITH_RPM +#define SUPPORT_10BIT +/* #define ERROR_HANDLE_DEBUG */ +#if 0/*MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8B*/ +#undef SUPPORT_4K2K +#else +#define SUPPORT_4K2K +#endif + +#ifndef STAT_KTHREAD +#define STAT_KTHREAD 0x40 +#endif + +#ifdef MULTI_INSTANCE_SUPPORT +#define MAX_DECODE_INSTANCE_NUM 9 +#define MULTI_DRIVER_NAME "ammvdec_h265" +#endif +#define DRIVER_NAME "amvdec_h265" +#define MODULE_NAME "amvdec_h265" +#define DRIVER_HEADER_NAME "amvdec_h265_header" + +#define PUT_INTERVAL (HZ/100) +#define ERROR_SYSTEM_RESET_COUNT 200 + +#define PTS_NORMAL 0 +#define PTS_NONE_REF_USE_DURATION 1 + +#define PTS_MODE_SWITCHING_THRESHOLD 3 +#define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3 + +#define DUR2PTS(x) ((x)*90/96) +#define MAX_SIZE (4096 + 2304) +#define OVER_SIZE(w, h) (MAX_SIZE < (w + h)) + +static struct semaphore h265_sema; + +struct hevc_state_s; +static int hevc_print(struct hevc_state_s *hevc, + int debug_flag, const char *fmt, ...); +static int hevc_print_cont(struct hevc_state_s *hevc, + int debug_flag, const char *fmt, ...); +static int vh265_vf_states(struct vframe_states *states, void *); +static struct vframe_s *vh265_vf_peek(void *); +static struct vframe_s *vh265_vf_get(void *); +static void vh265_vf_put(struct vframe_s *, void *); +static int vh265_event_cb(int type, void *data, void *private_data); + +static int vh265_stop(struct hevc_state_s *hevc); +#ifdef MULTI_INSTANCE_SUPPORT +static int vmh265_stop(struct hevc_state_s *hevc); +static s32 vh265_init(struct vdec_s *vdec); +static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask); +static void reset_process_time(struct hevc_state_s *hevc); +static void start_process_time(struct hevc_state_s *hevc); +static void restart_process_time(struct hevc_state_s *hevc); +static void timeout_process(struct hevc_state_s *hevc); +#else +static s32 vh265_init(struct hevc_state_s *hevc); +#endif +static void vh265_prot_init(struct hevc_state_s *hevc); +static int vh265_local_init(struct hevc_state_s *hevc); +static void vh265_check_timer_func(unsigned long arg); +static void config_decode_mode(struct hevc_state_s *hevc); + +static const char vh265_dec_id[] = "vh265-dev"; + +#define PROVIDER_NAME "decoder.h265" +#define MULTI_INSTANCE_PROVIDER_NAME "vdec.h265" + +static const struct vframe_operations_s vh265_vf_provider = { + .peek = vh265_vf_peek, + .get = vh265_vf_get, + .put = vh265_vf_put, + .event_cb = vh265_event_cb, + .vf_states = vh265_vf_states, +}; + +static struct vframe_provider_s vh265_vf_prov; + +static u32 bit_depth_luma; +static u32 bit_depth_chroma; +static u32 video_signal_type; + +static int start_decode_buf_level = 0x8000; + +static unsigned int decode_timeout_val = 200; + +/*data_resend_policy: + bit 0, stream base resend data when decoding buf empty +*/ +static u32 data_resend_policy = 1; + +#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000 +/* +static const char * const video_format_names[] = { + "component", "PAL", "NTSC", "SECAM", + "MAC", "unspecified", "unspecified", "unspecified" +}; + +static const char * const color_primaries_names[] = { + "unknown", "bt709", "undef", "unknown", + "bt470m", "bt470bg", "smpte170m", "smpte240m", + "film", "bt2020" +}; + +static const char * const transfer_characteristics_names[] = { + "unknown", "bt709", "undef", "unknown", + "bt470m", "bt470bg", "smpte170m", "smpte240m", + "linear", "log100", "log316", "iec61966-2-4", + "bt1361e", "iec61966-2-1", "bt2020-10", "bt2020-12", + "smpte-st-2084", "smpte-st-428" +}; + +static const char * const matrix_coeffs_names[] = { + "GBR", "bt709", "undef", "unknown", + "fcc", "bt470bg", "smpte170m", "smpte240m", + "YCgCo", "bt2020nc", "bt2020c" +}; +*/ +#ifdef SUPPORT_10BIT +#define HEVC_CM_BODY_START_ADDR 0x3626 +#define HEVC_CM_BODY_LENGTH 0x3627 +#define HEVC_CM_HEADER_LENGTH 0x3629 +#define HEVC_CM_HEADER_OFFSET 0x362b +#define HEVC_SAO_CTRL9 0x362d +#define LOSLESS_COMPRESS_MODE +/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */ +/* hevc->double_write_mode: + * 0, no double write; + * 1, 1:1 ratio; + * 2, (1/4):(1/4) ratio; + * 3, (1/4):(1/4) ratio, with both compressed frame included + * 0x10, double write only + */ +static u32 double_write_mode; + +/*#define DECOMP_HEADR_SURGENT*/ + +static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */ +static u32 enable_mem_saving = 1; +static u32 workaround_enable; +static u32 force_w_h; +#endif +static u32 force_fps; +static u32 pts_unstable; +#define H265_DEBUG_BUFMGR 0x01 +#define H265_DEBUG_BUFMGR_MORE 0x02 +#define H265_DEBUG_REG 0x08 +#define H265_DEBUG_MAN_SEARCH_NAL 0x10 +#define H265_DEBUG_MAN_SKIP_NAL 0x20 +#define H265_DEBUG_DISPLAY_CUR_FRAME 0x40 +#define H265_DEBUG_FORCE_CLK 0x80 +#define H265_DEBUG_SEND_PARAM_WITH_REG 0x100 +#define H265_DEBUG_NO_DISPLAY 0x200 +#define H265_DEBUG_DISCARD_NAL 0x400 +#define H265_DEBUG_OUT_PTS 0x800 +#define H265_DEBUG_DUMP_PIC_LIST 0x1000 +#define H265_DEBUG_PRINT_SEI 0x2000 +#define H265_DEBUG_PIC_STRUCT 0x4000 +#define H265_DEBUG_DIS_LOC_ERROR_PROC 0x10000 +#define H265_DEBUG_DIS_SYS_ERROR_PROC 0x20000 +#define H265_NO_CHANG_DEBUG_FLAG_IN_CODE 0x40000 +#define H265_DEBUG_TRIG_SLICE_SEGMENT_PROC 0x80000 +#define H265_DEBUG_HW_RESET 0x100000 +#define H265_CFG_CANVAS_IN_DECODE 0x200000 +#define H265_DEBUG_DV 0x400000 +#define H265_DEBUG_NO_EOS_SEARCH_DONE 0x800000 +#define H265_DEBUG_NOT_USE_LAST_DISPBUF 0x1000000 +#define H265_DEBUG_IGNORE_CONFORMANCE_WINDOW 0x2000000 +#define H265_DEBUG_WAIT_DECODE_DONE_WHEN_STOP 0x4000000 +#ifdef MULTI_INSTANCE_SUPPORT +#define IGNORE_PARAM_FROM_CONFIG 0x08000000 +#define PRINT_FRAMEBASE_DATA 0x10000000 +#define PRINT_FLAG_VDEC_STATUS 0x20000000 +#define PRINT_FLAG_VDEC_DETAIL 0x40000000 +#endif +#define BUF_POOL_SIZE 32 +#define MAX_BUF_NUM 24 +#define MAX_REF_PIC_NUM 24 +#define MAX_REF_ACTIVE 16 + +#ifdef MV_USE_FIXED_BUF +#define BMMU_MAX_BUFFERS (BUF_POOL_SIZE + 1) +#define VF_BUFFER_IDX(n) (n) +#define BMMU_WORKSPACE_ID (BUF_POOL_SIZE) +#else +#define BMMU_MAX_BUFFERS (BUF_POOL_SIZE + 1 + MAX_REF_PIC_NUM) +#define VF_BUFFER_IDX(n) (n) +#define BMMU_WORKSPACE_ID (BUF_POOL_SIZE) +#define MV_BUFFER_IDX(n) (BUF_POOL_SIZE + 1 + n) +#endif + +const u32 h265_version = 201602101; +static u32 debug_mask = 0xffffffff; +static u32 log_mask; +static u32 debug; +static u32 radr; +static u32 rval; +static u32 dbg_cmd; +static u32 dump_nal; +static u32 dbg_skip_decode_index; +static u32 endian = 0xff0; +#ifdef ERROR_HANDLE_DEBUG +static u32 dbg_nal_skip_flag; + /* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */ +static u32 dbg_nal_skip_count; +#endif +/*for debug*/ +/* + udebug_flag: + bit 0, enable ucode print + bit 1, enable ucode detail print + bit [31:16] not 0, pos to dump lmem + bit 2, pop bits to lmem + bit [11:8], pre-pop bits for alignment (when bit 2 is 1) +*/ +static u32 udebug_flag; +/* + when udebug_flag[1:0] is not 0 + udebug_pause_pos not 0, + pause position +*/ +static u32 udebug_pause_pos; +/* + when udebug_flag[1:0] is not 0 + and udebug_pause_pos is not 0, + pause only when DEBUG_REG2 is equal to this val +*/ +static u32 udebug_pause_val; + +static u32 udebug_pause_decode_idx; + +static u32 decode_pic_begin; +static uint slice_parse_begin; +static u32 step; +static bool is_reset; + +static u32 dynamic_buf_num_margin = 7; +static u32 buf_alloc_width; +static u32 buf_alloc_height; + +static u32 max_buf_num = 16; +static u32 buf_alloc_size; +/*static u32 re_config_pic_flag;*/ +/* + *bit[0]: 0, + *bit[1]: 0, always release cma buffer when stop + *bit[1]: 1, never release cma buffer when stop + *bit[0]: 1, when stop, release cma buffer if blackout is 1; + *do not release cma buffer is blackout is not 1 + * + *bit[2]: 0, when start decoding, check current displayed buffer + * (only for buffer decoded by h265) if blackout is 0 + * 1, do not check current displayed buffer + * + *bit[3]: 1, if blackout is not 1, do not release current + * displayed cma buffer always. + */ +/* set to 1 for fast play; + * set to 8 for other case of "keep last frame" + */ +static u32 buffer_mode = 1; + +/* buffer_mode_dbg: debug only*/ +static u32 buffer_mode_dbg = 0xffff0000; +/**/ +/* + *bit[1:0]PB_skip_mode: 0, start decoding at begin; + *1, start decoding after first I; + *2, only decode and display none error picture; + *3, start decoding and display after IDR,etc + *bit[31:16] PB_skip_count_after_decoding (decoding but not display), + *only for mode 0 and 1. + */ +static u32 nal_skip_policy = 2; + +/* + *bit 0, 1: only display I picture; + *bit 1, 1: only decode I picture; + */ +static u32 i_only_flag; + +/* +bit 0, fast output first I picture +*/ +static u32 fast_output_enable = 1; + +/* +use_cma: 1, use both reserver memory and cma for buffers +2, only use cma for buffers +*/ +static u32 use_cma = 2; + +#define AUX_BUF_ALIGN(adr) ((adr + 0xf) & (~0xf)) +static u32 prefix_aux_buf_size = (16 * 1024); +static u32 suffix_aux_buf_size; + +static u32 max_decoding_time; +/* + *error handling + */ +/*error_handle_policy: + *bit 0: 0, auto skip error_skip_nal_count nals before error recovery; + *1, skip error_skip_nal_count nals before error recovery; + *bit 1 (valid only when bit0 == 1): + *1, wait vps/sps/pps after error recovery; + *bit 2 (valid only when bit0 == 0): + *0, auto search after error recovery (hevc_recover() called); + *1, manual search after error recovery + *(change to auto search after get IDR: WRITE_VREG(NAL_SEARCH_CTL, 0x2)) + * + *bit 4: 0, set error_mark after reset/recover + * 1, do not set error_mark after reset/recover + *bit 5: 0, check total lcu for every picture + * 1, do not check total lcu + *bit 6: 0, do not check head error + * 1, check head error + * + */ + +static u32 error_handle_policy; +static u32 error_skip_nal_count = 6; +static u32 error_handle_threshold = 30; +static u32 error_handle_nal_skip_threshold = 10; +static u32 error_handle_system_threshold = 30; +static u32 interlace_enable = 1; +static u32 fr_hint_status; + + /* + *parser_sei_enable: + * bit 0, sei; + * bit 1, sei_suffix (fill aux buf) + * bit 2, fill sei to aux buf (when bit 0 is 1) + * bit 8, debug flag + */ +static u32 parser_sei_enable; +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION +static u32 parser_dolby_vision_enable = 1; +static u32 dolby_meta_with_el; +static u32 dolby_el_flush_th = 2; +#endif +/* this is only for h265 mmu enable */ + +static u32 mmu_enable = 1; +static u32 mmu_enable_force; +static u32 work_buf_size; +static unsigned int force_disp_pic_index; +static unsigned int disp_vframe_valve_level; + +#ifdef MULTI_INSTANCE_SUPPORT +static unsigned int max_decode_instance_num + = MAX_DECODE_INSTANCE_NUM; +static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM]; +static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM]; +static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM]; +static unsigned int max_get_frame_interval[MAX_DECODE_INSTANCE_NUM]; +static unsigned int run_count[MAX_DECODE_INSTANCE_NUM]; +static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM]; +static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM]; + +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC +static unsigned char get_idx(struct hevc_state_s *hevc); +#endif + +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION +static u32 dv_toggle_prov_name; + +static u32 dv_debug; +#endif +#endif + + +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC +#define get_dbg_flag(hevc) ((debug_mask & (1 << hevc->index)) ? debug : 0) +#define get_dbg_flag2(hevc) ((debug_mask & (1 << get_idx(hevc))) ? debug : 0) +#define is_log_enable(hevc) ((log_mask & (1 << hevc->index)) ? 1 : 0) +#else +#define get_dbg_flag(hevc) debug +#define get_dbg_flag2(hevc) debug +#define is_log_enable(hevc) (log_mask ? 1 : 0) +#define get_valid_double_write_mode(hevc) double_write_mode +#define get_buf_alloc_width(hevc) buf_alloc_width +#define get_buf_alloc_height(hevc) buf_alloc_height +#define get_dynamic_buf_num_margin(hevc) dynamic_buf_num_margin +#endif +#define get_buffer_mode(hevc) buffer_mode + + +DEFINE_SPINLOCK(lock); +struct task_struct *h265_task = NULL; +#undef DEBUG_REG +#ifdef DEBUG_REG +void WRITE_VREG_DBG(unsigned adr, unsigned val) +{ + if (debug & H265_DEBUG_REG) + pr_info("%s(%x, %x)\n", __func__, adr, val); + WRITE_VREG(adr, val); +} + +#undef WRITE_VREG +#define WRITE_VREG WRITE_VREG_DBG +#endif + +static DEFINE_MUTEX(vh265_mutex); + +static DEFINE_MUTEX(vh265_log_mutex); + +static struct vdec_info *gvs; + +/************************************************** + * + *h265 buffer management include + * + *************************************************** + */ +enum NalUnitType { + NAL_UNIT_CODED_SLICE_TRAIL_N = 0, /* 0 */ + NAL_UNIT_CODED_SLICE_TRAIL_R, /* 1 */ + + NAL_UNIT_CODED_SLICE_TSA_N, /* 2 */ + /* Current name in the spec: TSA_R */ + NAL_UNIT_CODED_SLICE_TLA, /* 3 */ + + NAL_UNIT_CODED_SLICE_STSA_N, /* 4 */ + NAL_UNIT_CODED_SLICE_STSA_R, /* 5 */ + + NAL_UNIT_CODED_SLICE_RADL_N, /* 6 */ + /* Current name in the spec: RADL_R */ + NAL_UNIT_CODED_SLICE_DLP, /* 7 */ + + NAL_UNIT_CODED_SLICE_RASL_N, /* 8 */ + /* Current name in the spec: RASL_R */ + NAL_UNIT_CODED_SLICE_TFD, /* 9 */ + + NAL_UNIT_RESERVED_10, + NAL_UNIT_RESERVED_11, + NAL_UNIT_RESERVED_12, + NAL_UNIT_RESERVED_13, + NAL_UNIT_RESERVED_14, + NAL_UNIT_RESERVED_15, + + /* Current name in the spec: BLA_W_LP */ + NAL_UNIT_CODED_SLICE_BLA, /* 16 */ + /* Current name in the spec: BLA_W_DLP */ + NAL_UNIT_CODED_SLICE_BLANT, /* 17 */ + NAL_UNIT_CODED_SLICE_BLA_N_LP, /* 18 */ + /* Current name in the spec: IDR_W_DLP */ + NAL_UNIT_CODED_SLICE_IDR, /* 19 */ + NAL_UNIT_CODED_SLICE_IDR_N_LP, /* 20 */ + NAL_UNIT_CODED_SLICE_CRA, /* 21 */ + NAL_UNIT_RESERVED_22, + NAL_UNIT_RESERVED_23, + + NAL_UNIT_RESERVED_24, + NAL_UNIT_RESERVED_25, + NAL_UNIT_RESERVED_26, + NAL_UNIT_RESERVED_27, + NAL_UNIT_RESERVED_28, + NAL_UNIT_RESERVED_29, + NAL_UNIT_RESERVED_30, + NAL_UNIT_RESERVED_31, + + NAL_UNIT_VPS, /* 32 */ + NAL_UNIT_SPS, /* 33 */ + NAL_UNIT_PPS, /* 34 */ + NAL_UNIT_ACCESS_UNIT_DELIMITER, /* 35 */ + NAL_UNIT_EOS, /* 36 */ + NAL_UNIT_EOB, /* 37 */ + NAL_UNIT_FILLER_DATA, /* 38 */ + NAL_UNIT_SEI, /* 39 Prefix SEI */ + NAL_UNIT_SEI_SUFFIX, /* 40 Suffix SEI */ + NAL_UNIT_RESERVED_41, + NAL_UNIT_RESERVED_42, + NAL_UNIT_RESERVED_43, + NAL_UNIT_RESERVED_44, + NAL_UNIT_RESERVED_45, + NAL_UNIT_RESERVED_46, + NAL_UNIT_RESERVED_47, + NAL_UNIT_UNSPECIFIED_48, + NAL_UNIT_UNSPECIFIED_49, + NAL_UNIT_UNSPECIFIED_50, + NAL_UNIT_UNSPECIFIED_51, + NAL_UNIT_UNSPECIFIED_52, + NAL_UNIT_UNSPECIFIED_53, + NAL_UNIT_UNSPECIFIED_54, + NAL_UNIT_UNSPECIFIED_55, + NAL_UNIT_UNSPECIFIED_56, + NAL_UNIT_UNSPECIFIED_57, + NAL_UNIT_UNSPECIFIED_58, + NAL_UNIT_UNSPECIFIED_59, + NAL_UNIT_UNSPECIFIED_60, + NAL_UNIT_UNSPECIFIED_61, + NAL_UNIT_UNSPECIFIED_62, + NAL_UNIT_UNSPECIFIED_63, + NAL_UNIT_INVALID, +}; + +/* --------------------------------------------------- */ +/* Amrisc Software Interrupt */ +/* --------------------------------------------------- */ +#define AMRISC_STREAM_EMPTY_REQ 0x01 +#define AMRISC_PARSER_REQ 0x02 +#define AMRISC_MAIN_REQ 0x04 + +/* --------------------------------------------------- */ +/* HEVC_DEC_STATUS define */ +/* --------------------------------------------------- */ +#define HEVC_DEC_IDLE 0x0 +#define HEVC_NAL_UNIT_VPS 0x1 +#define HEVC_NAL_UNIT_SPS 0x2 +#define HEVC_NAL_UNIT_PPS 0x3 +#define HEVC_NAL_UNIT_CODED_SLICE_SEGMENT 0x4 +#define HEVC_CODED_SLICE_SEGMENT_DAT 0x5 +#define HEVC_SLICE_DECODING 0x6 +#define HEVC_NAL_UNIT_SEI 0x7 +#define HEVC_SLICE_SEGMENT_DONE 0x8 +#define HEVC_NAL_SEARCH_DONE 0x9 +#define HEVC_DECPIC_DATA_DONE 0xa +#define HEVC_DECPIC_DATA_ERROR 0xb +#define HEVC_SEI_DAT 0xc +#define HEVC_SEI_DAT_DONE 0xd +#define HEVC_NAL_DECODE_DONE 0xe + +#define HEVC_DATA_REQUEST 0x12 + +#define HEVC_DECODE_BUFEMPTY 0x20 +#define HEVC_DECODE_TIMEOUT 0x21 +#define HEVC_SEARCH_BUFEMPTY 0x22 +#define HEVC_DECODE_OVER_SIZE 0x23 +#define HEVC_DECODE_BUFEMPTY2 0x24 +#define HEVC_FIND_NEXT_PIC_NAL 0x50 +#define HEVC_FIND_NEXT_DVEL_NAL 0x51 + +#define HEVC_DUMP_LMEM 0x30 + +#define HEVC_4k2k_60HZ_NOT_SUPPORT 0x80 +#define HEVC_DISCARD_NAL 0xf0 +#define HEVC_ACTION_DEC_CONT 0xfd +#define HEVC_ACTION_ERROR 0xfe +#define HEVC_ACTION_DONE 0xff + +/* --------------------------------------------------- */ +/* Include "parser_cmd.h" */ +/* --------------------------------------------------- */ +#define PARSER_CMD_SKIP_CFG_0 0x0000090b + +#define PARSER_CMD_SKIP_CFG_1 0x1b14140f + +#define PARSER_CMD_SKIP_CFG_2 0x001b1910 + +#define PARSER_CMD_NUMBER 37 + +/************************************************** + * + *h265 buffer management + * + *************************************************** + */ +/* #define BUFFER_MGR_ONLY */ +/* #define CONFIG_HEVC_CLK_FORCED_ON */ +/* #define ENABLE_SWAP_TEST */ +#define MCRCC_ENABLE +#define INVALID_POC 0x80000000 + +#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0 +#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1 +#define HEVC_SHORT_TERM_RPS HEVC_ASSIST_SCRATCH_2 +#define HEVC_VPS_BUFFER HEVC_ASSIST_SCRATCH_3 +#define HEVC_SPS_BUFFER HEVC_ASSIST_SCRATCH_4 +#define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5 +#define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6 +/*#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7 +#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8*/ +#define HEVC_sao_mem_unit HEVC_ASSIST_SCRATCH_9 +#define HEVC_SAO_ABV HEVC_ASSIST_SCRATCH_A +#define HEVC_sao_vb_size HEVC_ASSIST_SCRATCH_B +#define HEVC_SAO_VB HEVC_ASSIST_SCRATCH_C +#define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D +#define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E +#define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F +#define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_F +#ifdef ENABLE_SWAP_TEST +#define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L +#endif + +/*#define HEVC_DECODE_PIC_BEGIN_REG HEVC_ASSIST_SCRATCH_M*/ +/*#define HEVC_DECODE_PIC_NUM_REG HEVC_ASSIST_SCRATCH_N*/ +#define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N + /*do not define ENABLE_SWAP_TEST*/ +#define HEVC_AUX_ADR HEVC_ASSIST_SCRATCH_L +#define HEVC_AUX_DATA_SIZE HEVC_ASSIST_SCRATCH_M + +#define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G +#define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H +/* + *ucode parser/search control + *bit 0: 0, header auto parse; 1, header manual parse + *bit 1: 0, auto skip for noneseamless stream; 1, no skip + *bit [3:2]: valid when bit1==0; + *0, auto skip nal before first vps/sps/pps/idr; + *1, auto skip nal before first vps/sps/pps + *2, auto skip nal before first vps/sps/pps, + * and not decode until the first I slice (with slice address of 0) + * + *3, auto skip before first I slice (nal_type >=16 && nal_type<=21) + *bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) ) + *bit [16]: for NAL_UNIT_EOS when bit0 is 0: + * 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm + *bit [17]: for NAL_SEI when bit0 is 0: + * 0, do not parse/fetch SEI in ucode; + * 1, parse/fetch SEI in ucode + *bit [18]: for NAL_SEI_SUFFIX when bit0 is 0: + * 0, do not fetch NAL_SEI_SUFFIX to aux buf; + * 1, fetch NAL_SEL_SUFFIX data to aux buf + *bit [19]: + * 0, parse NAL_SEI in ucode + * 1, fetch NAL_SEI to aux buf + *bit [20]: for DOLBY_VISION_META + * 0, do not fetch DOLBY_VISION_META to aux buf + * 1, fetch DOLBY_VISION_META to aux buf + */ +#define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I + /*read only*/ +#define CUR_NAL_UNIT_TYPE HEVC_ASSIST_SCRATCH_J + /* + [15 : 8] rps_set_id + [7 : 0] start_decoding_flag + */ +#define HEVC_DECODE_INFO HEVC_ASSIST_SCRATCH_1 + /*set before start decoder*/ +#define HEVC_DECODE_MODE HEVC_ASSIST_SCRATCH_J +#define HEVC_DECODE_MODE2 HEVC_ASSIST_SCRATCH_H +#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K + +#define DECODE_MODE_SINGLE 0x0 +#define DECODE_MODE_MULTI_FRAMEBASE 0x1 +#define DECODE_MODE_MULTI_STREAMBASE 0x2 +#define DECODE_MODE_MULTI_DVBAL 0x3 +#define DECODE_MODE_MULTI_DVENL 0x4 + +#define MAX_INT 0x7FFFFFFF + +#define RPM_BEGIN 0x100 +#define modification_list_cur 0x148 +#define RPM_END 0x180 + +#define RPS_USED_BIT 14 +/* MISC_FLAG0 */ +#define PCM_LOOP_FILTER_DISABLED_FLAG_BIT 0 +#define PCM_ENABLE_FLAG_BIT 1 +#define LOOP_FILER_ACROSS_TILES_ENABLED_FLAG_BIT 2 +#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT 3 +#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_BIT 4 +#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT 5 +#define DEBLOCKING_FILTER_OVERRIDE_FLAG_BIT 6 +#define SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT 7 +#define SLICE_SAO_LUMA_FLAG_BIT 8 +#define SLICE_SAO_CHROMA_FLAG_BIT 9 +#define SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT 10 + +union param_u { + struct { + unsigned short data[RPM_END - RPM_BEGIN]; + } l; + struct { + /* from ucode lmem, do not change this struct */ + unsigned short CUR_RPS[0x10]; + unsigned short num_ref_idx_l0_active; + unsigned short num_ref_idx_l1_active; + unsigned short slice_type; + unsigned short slice_temporal_mvp_enable_flag; + unsigned short dependent_slice_segment_flag; + unsigned short slice_segment_address; + unsigned short num_title_rows_minus1; + unsigned short pic_width_in_luma_samples; + unsigned short pic_height_in_luma_samples; + unsigned short log2_min_coding_block_size_minus3; + unsigned short log2_diff_max_min_coding_block_size; + unsigned short log2_max_pic_order_cnt_lsb_minus4; + unsigned short POClsb; + unsigned short collocated_from_l0_flag; + unsigned short collocated_ref_idx; + unsigned short log2_parallel_merge_level; + unsigned short five_minus_max_num_merge_cand; + unsigned short sps_num_reorder_pics_0; + unsigned short modification_flag; + unsigned short tiles_enabled_flag; + unsigned short num_tile_columns_minus1; + unsigned short num_tile_rows_minus1; + unsigned short tile_width[8]; + unsigned short tile_height[8]; + unsigned short misc_flag0; + unsigned short pps_beta_offset_div2; + unsigned short pps_tc_offset_div2; + unsigned short slice_beta_offset_div2; + unsigned short slice_tc_offset_div2; + unsigned short pps_cb_qp_offset; + unsigned short pps_cr_qp_offset; + unsigned short first_slice_segment_in_pic_flag; + unsigned short m_temporalId; + unsigned short m_nalUnitType; + + unsigned short vui_num_units_in_tick_hi; + unsigned short vui_num_units_in_tick_lo; + unsigned short vui_time_scale_hi; + unsigned short vui_time_scale_lo; + unsigned short bit_depth; + unsigned short profile_etc; + unsigned short sei_frame_field_info; + unsigned short video_signal_type; + unsigned short modification_list[0x20]; + unsigned short conformance_window_flag; + unsigned short conf_win_left_offset; + unsigned short conf_win_right_offset; + unsigned short conf_win_top_offset; + unsigned short conf_win_bottom_offset; + unsigned short chroma_format_idc; + unsigned short color_description; + unsigned short aspect_ratio_idc; + unsigned short sar_width; + unsigned short sar_height; + } p; +}; + +#define RPM_BUF_SIZE (0x80*2) +/* non mmu mode lmem size : 0x400, mmu mode : 0x500*/ +#define LMEM_BUF_SIZE (0x500 * 2) + +struct buff_s { + u32 buf_start; + u32 buf_size; + u32 buf_end; +}; + +struct BuffInfo_s { + u32 max_width; + u32 max_height; + unsigned int start_adr; + unsigned int end_adr; + struct buff_s ipp; + struct buff_s sao_abv; + struct buff_s sao_vb; + struct buff_s short_term_rps; + struct buff_s vps; + struct buff_s sps; + struct buff_s pps; + struct buff_s sao_up; + struct buff_s swap_buf; + struct buff_s swap_buf2; + struct buff_s scalelut; + struct buff_s dblk_para; + struct buff_s dblk_data; + struct buff_s dblk_data2; + struct buff_s mmu_vbh; + struct buff_s cm_header; + struct buff_s mpred_above; +#ifdef MV_USE_FIXED_BUF + struct buff_s mpred_mv; +#endif + struct buff_s rpm; + struct buff_s lmem; +}; +#define WORK_BUF_SPEC_NUM 2 +static struct BuffInfo_s amvh265_workbuff_spec[WORK_BUF_SPEC_NUM] = { + { + /* 8M bytes */ + .max_width = 1920, + .max_height = 1088, + .ipp = { + /* IPP work space calculation : + * 4096 * (Y+CbCr+Flags) = 12k, round to 16k + */ + .buf_size = 0x4000, + }, + .sao_abv = { + .buf_size = 0x30000, + }, + .sao_vb = { + .buf_size = 0x30000, + }, + .short_term_rps = { + /* SHORT_TERM_RPS - Max 64 set, 16 entry every set, + * total 64x16x2 = 2048 bytes (0x800) + */ + .buf_size = 0x800, + }, + .vps = { + /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, + * total 0x0800 bytes + */ + .buf_size = 0x800, + }, + .sps = { + /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, + * total 0x0800 bytes + */ + .buf_size = 0x800, + }, + .pps = { + /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, + * total 0x2000 bytes + */ + .buf_size = 0x2000, + }, + .sao_up = { + /* SAO UP STORE AREA - Max 640(10240/16) LCU, + * each has 16 bytes total 0x2800 bytes + */ + .buf_size = 0x2800, + }, + .swap_buf = { + /* 256cyclex64bit = 2K bytes 0x800 + * (only 144 cycles valid) + */ + .buf_size = 0x800, + }, + .swap_buf2 = { + .buf_size = 0x800, + }, + .scalelut = { + /* support up to 32 SCALELUT 1024x32 = + * 32Kbytes (0x8000) + */ + .buf_size = 0x8000, + }, + .dblk_para = { +#ifdef SUPPORT_10BIT + .buf_size = 0x40000, +#else + /* DBLK -> Max 256(4096/16) LCU, each para + *512bytes(total:0x20000), data 1024bytes(total:0x40000) + */ + .buf_size = 0x20000, +#endif + }, + .dblk_data = { + .buf_size = 0x40000, + }, + .dblk_data2 = { + .buf_size = 0x40000, + }, /*dblk data for adapter*/ + .mmu_vbh = { + .buf_size = 0x5000, /*2*16*2304/4, 4K*/ + }, +#if 0 + .cm_header = {/* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)*/ + .buf_size = MMU_COMPRESS_HEADER_SIZE * + (MAX_REF_PIC_NUM + 1), + }, +#endif + .mpred_above = { + .buf_size = 0x8000, + }, +#ifdef MV_USE_FIXED_BUF + .mpred_mv = {/* 1080p, 0x40000 per buffer */ + .buf_size = 0x40000 * MAX_REF_PIC_NUM, + }, +#endif + .rpm = { + .buf_size = RPM_BUF_SIZE, + }, + .lmem = { + .buf_size = 0x500 * 2, + } + }, + { + .max_width = 4096, + .max_height = 2048, + .ipp = { + /* IPP work space calculation : + * 4096 * (Y+CbCr+Flags) = 12k, round to 16k + */ + .buf_size = 0x4000, + }, + .sao_abv = { + .buf_size = 0x30000, + }, + .sao_vb = { + .buf_size = 0x30000, + }, + .short_term_rps = { + /* SHORT_TERM_RPS - Max 64 set, 16 entry every set, + * total 64x16x2 = 2048 bytes (0x800) + */ + .buf_size = 0x800, + }, + .vps = { + /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, + * total 0x0800 bytes + */ + .buf_size = 0x800, + }, + .sps = { + /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, + * total 0x0800 bytes + */ + .buf_size = 0x800, + }, + .pps = { + /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, + * total 0x2000 bytes + */ + .buf_size = 0x2000, + }, + .sao_up = { + /* SAO UP STORE AREA - Max 640(10240/16) LCU, + * each has 16 bytes total 0x2800 bytes + */ + .buf_size = 0x2800, + }, + .swap_buf = { + /* 256cyclex64bit = 2K bytes 0x800 + * (only 144 cycles valid) + */ + .buf_size = 0x800, + }, + .swap_buf2 = { + .buf_size = 0x800, + }, + .scalelut = { + /* support up to 32 SCALELUT 1024x32 = 32Kbytes + * (0x8000) + */ + .buf_size = 0x8000, + }, + .dblk_para = { + /* DBLK -> Max 256(4096/16) LCU, each para + * 512bytes(total:0x20000), + * data 1024bytes(total:0x40000) + */ + .buf_size = 0x20000, + }, + .dblk_data = { + .buf_size = 0x80000, + }, + .dblk_data2 = { + .buf_size = 0x80000, + }, /*dblk data for adapter*/ + .mmu_vbh = { + .buf_size = 0x5000, /*2*16*2304/4, 4K*/ + }, +#if 0 + .cm_header = {/*0x44000 = ((1088*2*1024*4)/32/4)*(32/8)*/ + .buf_size = MMU_COMPRESS_HEADER_SIZE * + (MAX_REF_PIC_NUM + 1), + }, +#endif + .mpred_above = { + .buf_size = 0x8000, + }, +#ifdef MV_USE_FIXED_BUF + .mpred_mv = { + /* .buf_size = 0x100000*16, + //4k2k , 0x100000 per buffer */ + /* 4096x2304 , 0x120000 per buffer */ + .buf_size = MPRED_MV_BUF_SIZE * MAX_REF_PIC_NUM, + }, +#endif + .rpm = { + .buf_size = RPM_BUF_SIZE, + }, + .lmem = { + .buf_size = 0x500 * 2, + } + } +}; + +static void init_buff_spec(struct hevc_state_s *hevc, + struct BuffInfo_s *buf_spec) +{ + buf_spec->ipp.buf_start = buf_spec->start_adr; + buf_spec->sao_abv.buf_start = + buf_spec->ipp.buf_start + buf_spec->ipp.buf_size; + + buf_spec->sao_vb.buf_start = + buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size; + buf_spec->short_term_rps.buf_start = + buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size; + buf_spec->vps.buf_start = + buf_spec->short_term_rps.buf_start + + buf_spec->short_term_rps.buf_size; + buf_spec->sps.buf_start = + buf_spec->vps.buf_start + buf_spec->vps.buf_size; + buf_spec->pps.buf_start = + buf_spec->sps.buf_start + buf_spec->sps.buf_size; + buf_spec->sao_up.buf_start = + buf_spec->pps.buf_start + buf_spec->pps.buf_size; + buf_spec->swap_buf.buf_start = + buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size; + buf_spec->swap_buf2.buf_start = + buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size; + buf_spec->scalelut.buf_start = + buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size; + buf_spec->dblk_para.buf_start = + buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size; + buf_spec->dblk_data.buf_start = + buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size; + buf_spec->dblk_data2.buf_start = + buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size; + buf_spec->mmu_vbh.buf_start = + buf_spec->dblk_data2.buf_start + buf_spec->dblk_data2.buf_size; + buf_spec->mpred_above.buf_start = + buf_spec->mmu_vbh.buf_start + buf_spec->mmu_vbh.buf_size; +#ifdef MV_USE_FIXED_BUF + buf_spec->mpred_mv.buf_start = + buf_spec->mpred_above.buf_start + + buf_spec->mpred_above.buf_size; + + buf_spec->rpm.buf_start = + buf_spec->mpred_mv.buf_start + + buf_spec->mpred_mv.buf_size; +#else + buf_spec->rpm.buf_start = + buf_spec->mpred_above.buf_start + + buf_spec->mpred_above.buf_size; +#endif + buf_spec->lmem.buf_start = + buf_spec->rpm.buf_start + + buf_spec->rpm.buf_size; + buf_spec->end_adr = + buf_spec->lmem.buf_start + + buf_spec->lmem.buf_size; + + if (hevc && get_dbg_flag2(hevc)) { + hevc_print(hevc, 0, + "%s workspace (%x %x) size = %x\n", __func__, + buf_spec->start_adr, buf_spec->end_adr, + buf_spec->end_adr - buf_spec->start_adr); + + hevc_print(hevc, 0, + "ipp.buf_start :%x\n", + buf_spec->ipp.buf_start); + hevc_print(hevc, 0, + "sao_abv.buf_start :%x\n", + buf_spec->sao_abv.buf_start); + hevc_print(hevc, 0, + "sao_vb.buf_start :%x\n", + buf_spec->sao_vb.buf_start); + hevc_print(hevc, 0, + "short_term_rps.buf_start :%x\n", + buf_spec->short_term_rps.buf_start); + hevc_print(hevc, 0, + "vps.buf_start :%x\n", + buf_spec->vps.buf_start); + hevc_print(hevc, 0, + "sps.buf_start :%x\n", + buf_spec->sps.buf_start); + hevc_print(hevc, 0, + "pps.buf_start :%x\n", + buf_spec->pps.buf_start); + hevc_print(hevc, 0, + "sao_up.buf_start :%x\n", + buf_spec->sao_up.buf_start); + hevc_print(hevc, 0, + "swap_buf.buf_start :%x\n", + buf_spec->swap_buf.buf_start); + hevc_print(hevc, 0, + "swap_buf2.buf_start :%x\n", + buf_spec->swap_buf2.buf_start); + hevc_print(hevc, 0, + "scalelut.buf_start :%x\n", + buf_spec->scalelut.buf_start); + hevc_print(hevc, 0, + "dblk_para.buf_start :%x\n", + buf_spec->dblk_para.buf_start); + hevc_print(hevc, 0, + "dblk_data.buf_start :%x\n", + buf_spec->dblk_data.buf_start); + hevc_print(hevc, 0, + "dblk_data2.buf_start :%x\n", + buf_spec->dblk_data2.buf_start); + hevc_print(hevc, 0, + "mpred_above.buf_start :%x\n", + buf_spec->mpred_above.buf_start); +#ifdef MV_USE_FIXED_BUF + hevc_print(hevc, 0, + "mpred_mv.buf_start :%x\n", + buf_spec->mpred_mv.buf_start); +#endif + if ((get_dbg_flag2(hevc) + & + H265_DEBUG_SEND_PARAM_WITH_REG) + == 0) { + hevc_print(hevc, 0, + "rpm.buf_start :%x\n", + buf_spec->rpm.buf_start); + } + } + +} + +enum SliceType { + B_SLICE, + P_SLICE, + I_SLICE +}; + +/*USE_BUF_BLOCK*/ +struct BUF_s { + unsigned long start_adr; + unsigned int size; + int used_flag; +} /*BUF_t */; + +/* level 6, 6.1 maximum slice number is 800; other is 200 */ +#define MAX_SLICE_NUM 800 +struct PIC_s { + int index; + int scatter_alloc; + int BUF_index; + int mv_buf_index; + int POC; + int decode_idx; + int slice_type; + int RefNum_L0; + int RefNum_L1; + int num_reorder_pic; + int stream_offset; + unsigned char referenced; + unsigned char output_mark; + unsigned char recon_mark; + unsigned char output_ready; + unsigned char error_mark; + /**/ int slice_idx; + int m_aiRefPOCList0[MAX_SLICE_NUM][16]; + int m_aiRefPOCList1[MAX_SLICE_NUM][16]; + /*buffer */ + unsigned int header_adr; +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + unsigned char dv_enhance_exist; +#endif + char *aux_data_buf; + int aux_data_size; + unsigned long cma_alloc_addr; + struct page *alloc_pages; + unsigned int mpred_mv_wr_start_addr; + unsigned int mc_y_adr; + unsigned int mc_u_v_adr; +#ifdef SUPPORT_10BIT + /*unsigned int comp_body_size;*/ + unsigned int dw_y_adr; + unsigned int dw_u_v_adr; +#endif + int mc_canvas_y; + int mc_canvas_u_v; + int width; + int height; + + int y_canvas_index; + int uv_canvas_index; +#ifdef MULTI_INSTANCE_SUPPORT + struct canvas_config_s canvas_config[2]; +#endif +#ifdef SUPPORT_10BIT + int mem_saving_mode; + u32 bit_depth_luma; + u32 bit_depth_chroma; +#endif +#ifdef LOSLESS_COMPRESS_MODE + unsigned int losless_comp_body_size; +#endif + unsigned char pic_struct; + int vf_ref; + + u32 pts; + u64 pts64; + + u32 aspect_ratio_idc; + u32 sar_width; + u32 sar_height; + u32 double_write_mode; +} /*PIC_t */; + +#define MAX_TILE_COL_NUM 10 +#define MAX_TILE_ROW_NUM 20 +struct tile_s { + int width; + int height; + int start_cu_x; + int start_cu_y; + + unsigned int sao_vb_start_addr; + unsigned int sao_abv_start_addr; +}; + +#define SEI_MASTER_DISPLAY_COLOR_MASK 0x00000001 +#define SEI_CONTENT_LIGHT_LEVEL_MASK 0x00000002 + +#define VF_POOL_SIZE 32 + +#ifdef MULTI_INSTANCE_SUPPORT +#define DEC_RESULT_NONE 0 +#define DEC_RESULT_DONE 1 +#define DEC_RESULT_AGAIN 2 +#define DEC_RESULT_CONFIG_PARAM 3 +#define DEC_RESULT_ERROR 4 +#define DEC_INIT_PICLIST 5 +#define DEC_UNINIT_PICLIST 6 +#define DEC_RESULT_GET_DATA 7 +#define DEC_RESULT_GET_DATA_RETRY 8 +#define DEC_RESULT_EOS 9 +#define DEC_RESULT_FORCE_EXIT 10 + +static void vh265_work(struct work_struct *work); +static void vh265_notify_work(struct work_struct *work); + +#endif + +struct debug_log_s { + struct list_head list; + uint8_t data; /*will alloc more size*/ +}; + +struct hevc_state_s { +#ifdef MULTI_INSTANCE_SUPPORT + struct platform_device *platform_dev; + void (*vdec_cb)(struct vdec_s *, void *); + void *vdec_cb_arg; + struct vframe_chunk_s *chunk; + int dec_result; + struct work_struct work; + struct work_struct notify_work; + struct work_struct set_clk_work; + /* timeout handle */ + unsigned long int start_process_time; + unsigned int last_lcu_idx; + unsigned int decode_timeout_count; + unsigned int timeout_num; +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + unsigned char switch_dvlayer_flag; + unsigned char no_switch_dvlayer_count; +#endif + unsigned char start_parser_type; + /*start_decoding_flag: + vps/pps/sps/idr info from ucode*/ + unsigned char start_decoding_flag; + unsigned char rps_set_id; + unsigned char eos; + int pic_decoded_lcu_idx; + u8 over_decode; +#endif + struct vframe_s vframe_dummy; + char *provider_name; + int index; + struct device *cma_dev; + unsigned char m_ins_flag; + unsigned char dolby_enhance_flag; + unsigned long buf_start; + u32 buf_size; + u32 mv_buf_size; + + struct BuffInfo_s work_space_buf_store; + struct BuffInfo_s *work_space_buf; + + u32 prefix_aux_size; + u32 suffix_aux_size; + void *aux_addr; + void *rpm_addr; + void *lmem_addr; + dma_addr_t aux_phy_addr; + dma_addr_t rpm_phy_addr; + dma_addr_t lmem_phy_addr; + + unsigned int pic_list_init_flag; + unsigned int use_cma_flag; + + unsigned short *rpm_ptr; + unsigned short *lmem_ptr; + unsigned short *debug_ptr; + int debug_ptr_size; + int pic_w; + int pic_h; + int lcu_x_num; + int lcu_y_num; + int lcu_total; + int lcu_size; + int lcu_size_log2; + int lcu_x_num_pre; + int lcu_y_num_pre; + int first_pic_after_recover; + + int num_tile_col; + int num_tile_row; + int tile_enabled; + int tile_x; + int tile_y; + int tile_y_x; + int tile_start_lcu_x; + int tile_start_lcu_y; + int tile_width_lcu; + int tile_height_lcu; + + int slice_type; + unsigned int slice_addr; + unsigned int slice_segment_addr; + + unsigned char interlace_flag; + unsigned char curr_pic_struct; + + unsigned short sps_num_reorder_pics_0; + unsigned short misc_flag0; + int m_temporalId; + int m_nalUnitType; + int TMVPFlag; + int isNextSliceSegment; + int LDCFlag; + int m_pocRandomAccess; + int plevel; + int MaxNumMergeCand; + + int new_pic; + int new_tile; + int curr_POC; + int iPrevPOC; +#ifdef MULTI_INSTANCE_SUPPORT + int decoded_poc; + struct PIC_s *decoding_pic; +#endif + int iPrevTid0POC; + int list_no; + int RefNum_L0; + int RefNum_L1; + int ColFromL0Flag; + int LongTerm_Curr; + int LongTerm_Col; + int Col_POC; + int LongTerm_Ref; +#ifdef MULTI_INSTANCE_SUPPORT + int m_pocRandomAccess_bak; + int curr_POC_bak; + int iPrevPOC_bak; + int iPrevTid0POC_bak; + unsigned char start_parser_type_bak; + unsigned char start_decoding_flag_bak; + unsigned char rps_set_id_bak; + int pic_decoded_lcu_idx_bak; + int decode_idx_bak; +#endif + struct PIC_s *cur_pic; + struct PIC_s *col_pic; + int skip_flag; + int decode_idx; + int slice_idx; + unsigned char have_vps; + unsigned char have_sps; + unsigned char have_pps; + unsigned char have_valid_start_slice; + unsigned char wait_buf; + unsigned char error_flag; + unsigned int error_skip_nal_count; + long used_4k_num; + + unsigned char + ignore_bufmgr_error; /* bit 0, for decoding; + bit 1, for displaying + bit 1 must be set if bit 0 is 1*/ + int PB_skip_mode; + int PB_skip_count_after_decoding; +#ifdef SUPPORT_10BIT + int mem_saving_mode; +#endif +#ifdef LOSLESS_COMPRESS_MODE + unsigned int losless_comp_body_size; +#endif + int pts_mode; + int last_lookup_pts; + int last_pts; + u64 last_lookup_pts_us64; + u64 last_pts_us64; + u32 shift_byte_count_lo; + u32 shift_byte_count_hi; + int pts_mode_switching_count; + int pts_mode_recovery_count; + + int pic_num; + + /**/ + union param_u param; + + struct tile_s m_tile[MAX_TILE_ROW_NUM][MAX_TILE_COL_NUM]; + + struct timer_list timer; + struct BUF_s m_BUF[BUF_POOL_SIZE]; + struct BUF_s m_mv_BUF[MAX_REF_PIC_NUM]; + struct PIC_s *m_PIC[MAX_REF_PIC_NUM]; + + DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE); + DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE); + DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE); + struct vframe_s vfpool[VF_POOL_SIZE]; + + u32 stat; + u32 frame_width; + u32 frame_height; + u32 frame_dur; + u32 frame_ar; + u32 bit_depth_luma; + u32 bit_depth_chroma; + u32 video_signal_type; + u32 saved_resolution; + bool get_frame_dur; + u32 error_watchdog_count; + u32 error_skip_nal_wt_cnt; + u32 error_system_watchdog_count; + +#ifdef DEBUG_PTS + unsigned long pts_missed; + unsigned long pts_hit; +#endif + struct dec_sysinfo vh265_amstream_dec_info; + unsigned char init_flag; + unsigned char uninit_list; + u32 start_decoding_time; + + int show_frame_num; +#ifdef USE_UNINIT_SEMA + struct semaphore h265_uninit_done_sema; +#endif + int fatal_error; + + + u32 sei_present_flag; + void *frame_mmu_map_addr; + dma_addr_t frame_mmu_map_phy_addr; + unsigned int mmu_mc_buf_start; + unsigned int mmu_mc_buf_end; + unsigned int mmu_mc_start_4k_adr; + void *mmu_box; + void *bmmu_box; + int mmu_enable; + + unsigned int dec_status; + + /* data for SEI_MASTER_DISPLAY_COLOR */ + unsigned int primaries[3][2]; + unsigned int white_point[2]; + unsigned int luminance[2]; + /* data for SEI_CONTENT_LIGHT_LEVEL */ + unsigned int content_light_level[2]; + + struct PIC_s *pre_top_pic; + struct PIC_s *pre_bot_pic; + +#ifdef MULTI_INSTANCE_SUPPORT + int double_write_mode; + int dynamic_buf_num_margin; + int start_action; +#endif + u32 i_only; + struct list_head log_list; + u32 ucode_pause_pos; + u32 start_shift_bytes; + + u32 vf_pre_count; + u32 vf_get_count; + u32 vf_put_count; + u8 head_error_flag; + int valve_count; + struct firmware_s *fw; + int max_pic_w; + int max_pic_h; +#ifdef AGAIN_HAS_THRESHOLD + u8 next_again_flag; + u32 pre_parser_wr_ptr; +#endif +} /*hevc_stru_t */; + +#ifdef AGAIN_HAS_THRESHOLD +u32 again_threshold = 0x40; +#endif +#ifdef SEND_LMEM_WITH_RPM +#define get_lmem_params(hevc, ladr) \ + hevc->lmem_ptr[ladr - (ladr & 0x3) + 3 - (ladr & 0x3)] + +void check_head_error(struct hevc_state_s *hevc) +{ +#define pcm_enabled_flag 0x040 +#define pcm_sample_bit_depth_luma 0x041 +#define pcm_sample_bit_depth_chroma 0x042 + hevc->head_error_flag = 0; + if ((error_handle_policy & 0x40) == 0) + return; + if (get_lmem_params(hevc, pcm_enabled_flag)) { + uint16_t pcm_depth_luma = get_lmem_params( + hevc, pcm_sample_bit_depth_luma); + uint16_t pcm_sample_chroma = get_lmem_params( + hevc, pcm_sample_bit_depth_chroma); + if (pcm_depth_luma > + hevc->bit_depth_luma || + pcm_sample_chroma > + hevc->bit_depth_chroma) { + hevc_print(hevc, 0, + "error, pcm bit depth %d, %d is greater than normal bit depth %d, %d\n", + pcm_depth_luma, + pcm_sample_chroma, + hevc->bit_depth_luma, + hevc->bit_depth_chroma); + hevc->head_error_flag = 1; + } + } +} +#endif + +#ifdef SUPPORT_10BIT +/* Losless compression body buffer size 4K per 64x32 (jt) */ +static int compute_losless_comp_body_size(struct hevc_state_s *hevc, + int width, int height, int mem_saving_mode) +{ + int width_x64; + int height_x32; + int bsize; + + width_x64 = width + 63; + width_x64 >>= 6; + + height_x32 = height + 31; + height_x32 >>= 5; + if (mem_saving_mode == 1 && hevc->mmu_enable) + bsize = 3200 * width_x64 * height_x32; + else if (mem_saving_mode == 1) + bsize = 3072 * width_x64 * height_x32; + else + bsize = 4096 * width_x64 * height_x32; + + return bsize; +} + +/* Losless compression header buffer size 32bytes per 128x64 (jt) */ +static int compute_losless_comp_header_size(int width, int height) +{ + int width_x128; + int height_x64; + int hsize; + + width_x128 = width + 127; + width_x128 >>= 7; + + height_x64 = height + 63; + height_x64 >>= 6; + + hsize = 32*width_x128*height_x64; + + return hsize; +} +#endif + +static int add_log(struct hevc_state_s *hevc, + const char *fmt, ...) +{ +#define HEVC_LOG_BUF 196 + struct debug_log_s *log_item; + unsigned char buf[HEVC_LOG_BUF]; + int len = 0; + va_list args; + mutex_lock(&vh265_log_mutex); + va_start(args, fmt); + len = sprintf(buf, "<%ld> <%05d> ", + jiffies, hevc->decode_idx); + len += vsnprintf(buf + len, + HEVC_LOG_BUF - len, fmt, args); + va_end(args); + log_item = kmalloc( + sizeof(struct debug_log_s) + len, + GFP_KERNEL); + if (log_item) { + INIT_LIST_HEAD(&log_item->list); + strcpy(&log_item->data, buf); + list_add_tail(&log_item->list, + &hevc->log_list); + } + mutex_unlock(&vh265_log_mutex); + return 0; +} + +static void dump_log(struct hevc_state_s *hevc) +{ + int i = 0; + struct debug_log_s *log_item, *tmp; + mutex_lock(&vh265_log_mutex); + list_for_each_entry_safe(log_item, tmp, &hevc->log_list, list) { + hevc_print(hevc, 0, + "[LOG%04d]%s\n", + i++, + &log_item->data); + list_del(&log_item->list); + kfree(log_item); + } + mutex_unlock(&vh265_log_mutex); +} + +static unsigned char is_skip_decoding(struct hevc_state_s *hevc, + struct PIC_s *pic) +{ + if (pic->error_mark + && ((hevc->ignore_bufmgr_error & 0x1) == 0)) + return 1; + return 0; +} + +static int get_pic_poc(struct hevc_state_s *hevc, + unsigned int idx) +{ + if (idx != 0xff && idx >= 0 + && idx < MAX_REF_PIC_NUM + && hevc->m_PIC[idx]) + return hevc->m_PIC[idx]->POC; + return INVALID_POC; +} + +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC +static int get_valid_double_write_mode(struct hevc_state_s *hevc) +{ + return (hevc->m_ins_flag && + ((double_write_mode & 0x80000000) == 0)) ? + hevc->double_write_mode : + (double_write_mode & 0x7fffffff); +} + +static int get_dynamic_buf_num_margin(struct hevc_state_s *hevc) +{ + return (hevc->m_ins_flag && + ((dynamic_buf_num_margin & 0x80000000) == 0)) ? + hevc->dynamic_buf_num_margin : + (dynamic_buf_num_margin & 0x7fffffff); +} +#endif + +static int get_double_write_mode(struct hevc_state_s *hevc) +{ + u32 valid_dw_mode = get_valid_double_write_mode(hevc); + u32 dw; + if (valid_dw_mode == 0x100) { + int w = hevc->pic_w; + int h = hevc->pic_h; + if (w > 1920 && h > 1088) + dw = 0x4; /*1:2*/ + else + dw = 0x1; /*1:1*/ + + } else + dw = valid_dw_mode; + return dw; +} + +static int get_double_write_ratio(struct hevc_state_s *hevc, + int dw_mode) +{ + int ratio = 1; + if ((dw_mode == 2) || + (dw_mode == 3)) + ratio = 4; + else if (dw_mode == 4) + ratio = 2; + return ratio; +} +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC +static unsigned char get_idx(struct hevc_state_s *hevc) +{ + return hevc->index; +} +#endif + +#undef pr_info +#define pr_info printk +static int hevc_print(struct hevc_state_s *hevc, + int flag, const char *fmt, ...) +{ +#define HEVC_PRINT_BUF 256 + unsigned char buf[HEVC_PRINT_BUF]; + int len = 0; +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + if (hevc == NULL || + (flag == 0) || + ((debug_mask & + (1 << hevc->index)) + && (debug & flag))) { +#endif + va_list args; + + va_start(args, fmt); + if (hevc) + len = sprintf(buf, "[%d]", hevc->index); + vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args); + pr_debug("%s", buf); + va_end(args); +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + } +#endif + return 0; +} + +static int hevc_print_cont(struct hevc_state_s *hevc, + int flag, const char *fmt, ...) +{ + unsigned char buf[HEVC_PRINT_BUF]; + int len = 0; +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + if (hevc == NULL || + (flag == 0) || + ((debug_mask & + (1 << hevc->index)) + && (debug & flag))) { +#endif + va_list args; + + va_start(args, fmt); + vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args); + pr_info("%s", buf); + va_end(args); +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + } +#endif + return 0; +} + +static void put_mv_buf(struct hevc_state_s *hevc, + struct PIC_s *pic); + +static void update_vf_memhandle(struct hevc_state_s *hevc, + struct vframe_s *vf, struct PIC_s *pic); + +static void set_canvas(struct hevc_state_s *hevc, struct PIC_s *pic); + +static void release_aux_data(struct hevc_state_s *hevc, + struct PIC_s *pic); +static void release_pic_mmu_buf(struct hevc_state_s *hevc, struct PIC_s *pic); + +#ifdef MULTI_INSTANCE_SUPPORT +static void backup_decode_state(struct hevc_state_s *hevc) +{ + hevc->m_pocRandomAccess_bak = hevc->m_pocRandomAccess; + hevc->curr_POC_bak = hevc->curr_POC; + hevc->iPrevPOC_bak = hevc->iPrevPOC; + hevc->iPrevTid0POC_bak = hevc->iPrevTid0POC; + hevc->start_parser_type_bak = hevc->start_parser_type; + hevc->start_decoding_flag_bak = hevc->start_decoding_flag; + hevc->rps_set_id_bak = hevc->rps_set_id; + hevc->pic_decoded_lcu_idx_bak = hevc->pic_decoded_lcu_idx; + hevc->decode_idx_bak = hevc->decode_idx; + +} + +static void restore_decode_state(struct hevc_state_s *hevc) +{ + struct vdec_s *vdec = hw_to_vdec(hevc); + if (!vdec_has_more_input(vdec)) { + hevc->pic_decoded_lcu_idx = + READ_VREG(HEVC_PARSER_LCU_START) + & 0xffffff; + return; + } + hevc_print(hevc, PRINT_FLAG_VDEC_STATUS, + "%s: discard pic index 0x%x\n", + __func__, hevc->decoding_pic ? + hevc->decoding_pic->index : 0xff); + if (hevc->decoding_pic) { + hevc->decoding_pic->error_mark = 0; + hevc->decoding_pic->output_ready = 0; + hevc->decoding_pic->output_mark = 0; + hevc->decoding_pic->referenced = 0; + hevc->decoding_pic->POC = INVALID_POC; + put_mv_buf(hevc, hevc->decoding_pic); + release_pic_mmu_buf(hevc, hevc->decoding_pic); + release_aux_data(hevc, hevc->decoding_pic); + hevc->decoding_pic = NULL; + } + hevc->decode_idx = hevc->decode_idx_bak; + hevc->m_pocRandomAccess = hevc->m_pocRandomAccess_bak; + hevc->curr_POC = hevc->curr_POC_bak; + hevc->iPrevPOC = hevc->iPrevPOC_bak; + hevc->iPrevTid0POC = hevc->iPrevTid0POC_bak; + hevc->start_parser_type = hevc->start_parser_type_bak; + hevc->start_decoding_flag = hevc->start_decoding_flag_bak; + hevc->rps_set_id = hevc->rps_set_id_bak; + hevc->pic_decoded_lcu_idx = hevc->pic_decoded_lcu_idx_bak; + + if (hevc->pic_list_init_flag == 1) + hevc->pic_list_init_flag = 0; + /*if (hevc->decode_idx == 0) + hevc->start_decoding_flag = 0;*/ + + hevc->slice_idx = 0; + hevc->used_4k_num = -1; +} +#endif + +static void hevc_init_stru(struct hevc_state_s *hevc, + struct BuffInfo_s *buf_spec_i) +{ + int i; + INIT_LIST_HEAD(&hevc->log_list); + hevc->work_space_buf = buf_spec_i; + hevc->prefix_aux_size = 0; + hevc->suffix_aux_size = 0; + hevc->aux_addr = NULL; + hevc->rpm_addr = NULL; + hevc->lmem_addr = NULL; + + hevc->curr_POC = INVALID_POC; + + hevc->pic_list_init_flag = 0; + hevc->use_cma_flag = 0; + hevc->decode_idx = 0; + hevc->slice_idx = 0; + hevc->new_pic = 0; + hevc->new_tile = 0; + hevc->iPrevPOC = 0; + hevc->list_no = 0; + /* int m_uiMaxCUWidth = 1<<7; */ + /* int m_uiMaxCUHeight = 1<<7; */ + hevc->m_pocRandomAccess = MAX_INT; + hevc->tile_enabled = 0; + hevc->tile_x = 0; + hevc->tile_y = 0; + hevc->iPrevTid0POC = 0; + hevc->slice_addr = 0; + hevc->slice_segment_addr = 0; + hevc->skip_flag = 0; + hevc->misc_flag0 = 0; + + hevc->cur_pic = NULL; + hevc->col_pic = NULL; + hevc->wait_buf = 0; + hevc->error_flag = 0; + hevc->head_error_flag = 0; + hevc->error_skip_nal_count = 0; + hevc->have_vps = 0; + hevc->have_sps = 0; + hevc->have_pps = 0; + hevc->have_valid_start_slice = 0; + + hevc->pts_mode = PTS_NORMAL; + hevc->last_pts = 0; + hevc->last_lookup_pts = 0; + hevc->last_pts_us64 = 0; + hevc->last_lookup_pts_us64 = 0; + hevc->pts_mode_switching_count = 0; + hevc->pts_mode_recovery_count = 0; + + hevc->PB_skip_mode = nal_skip_policy & 0x3; + hevc->PB_skip_count_after_decoding = (nal_skip_policy >> 16) & 0xffff; + if (hevc->PB_skip_mode == 0) + hevc->ignore_bufmgr_error = 0x1; + else + hevc->ignore_bufmgr_error = 0x0; + + for (i = 0; i < MAX_REF_PIC_NUM; i++) + hevc->m_PIC[i] = NULL; + hevc->pic_num = 0; + hevc->lcu_x_num_pre = 0; + hevc->lcu_y_num_pre = 0; + hevc->first_pic_after_recover = 0; + + hevc->pre_top_pic = NULL; + hevc->pre_bot_pic = NULL; + + hevc->sei_present_flag = 0; + hevc->valve_count = 0; +#ifdef MULTI_INSTANCE_SUPPORT + hevc->decoded_poc = INVALID_POC; + hevc->start_process_time = 0; + hevc->last_lcu_idx = 0; + hevc->decode_timeout_count = 0; + hevc->timeout_num = 0; + hevc->eos = 0; + hevc->pic_decoded_lcu_idx = -1; + hevc->over_decode = 0; + hevc->used_4k_num = -1; + hevc->start_decoding_flag = 0; + hevc->rps_set_id = 0; + backup_decode_state(hevc); +#endif +} + +static int prepare_display_buf(struct hevc_state_s *hevc, struct PIC_s *pic); +static int H265_alloc_mmu(struct hevc_state_s *hevc, + struct PIC_s *new_pic, unsigned short bit_depth, + unsigned int *mmu_index_adr); + +static void get_rpm_param(union param_u *params) +{ + int i; + unsigned int data32; + + for (i = 0; i < 128; i++) { + do { + data32 = READ_VREG(RPM_CMD_REG); + /* hevc_print(hevc, 0, "%x\n", data32); */ + } while ((data32 & 0x10000) == 0); + params->l.data[i] = data32 & 0xffff; + /* hevc_print(hevc, 0, "%x\n", data32); */ + WRITE_VREG(RPM_CMD_REG, 0); + } +} + +static struct PIC_s *get_pic_by_POC(struct hevc_state_s *hevc, int POC) +{ + int i; + struct PIC_s *pic; + struct PIC_s *ret_pic = NULL; + if (POC == INVALID_POC) + return NULL; + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + pic = hevc->m_PIC[i]; + if (pic == NULL || pic->index == -1 || + pic->BUF_index == -1) + continue; + if (pic->POC == POC) { + if (ret_pic == NULL) + ret_pic = pic; + else { + if (pic->decode_idx > ret_pic->decode_idx) + ret_pic = pic; + } + } + } + return ret_pic; +} + +static struct PIC_s *get_ref_pic_by_POC(struct hevc_state_s *hevc, int POC) +{ + int i; + struct PIC_s *pic; + struct PIC_s *ret_pic = NULL; + + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + pic = hevc->m_PIC[i]; + if (pic == NULL || pic->index == -1 || + pic->BUF_index == -1) + continue; + if ((pic->POC == POC) && (pic->referenced)) { + if (ret_pic == NULL) + ret_pic = pic; + else { + if (pic->decode_idx > ret_pic->decode_idx) + ret_pic = pic; + } + } + } + + if (ret_pic == NULL) { + if (get_dbg_flag(hevc)) { + hevc_print(hevc, 0, + "Wrong, POC of %d is not in referenced list\n", + POC); + } + ret_pic = get_pic_by_POC(hevc, POC); + } + return ret_pic; +} + +static unsigned int log2i(unsigned int val) +{ + unsigned int ret = -1; + + while (val != 0) { + val >>= 1; + ret++; + } + return ret; +} + +static int init_buf_spec(struct hevc_state_s *hevc); + +static void uninit_mmu_buffers(struct hevc_state_s *hevc) +{ + + if (hevc->mmu_box) + decoder_mmu_box_free(hevc->mmu_box); + hevc->mmu_box = NULL; + + if (hevc->bmmu_box) + decoder_bmmu_box_free(hevc->bmmu_box); + hevc->bmmu_box = NULL; +} +static int init_mmu_buffers(struct hevc_state_s *hevc) +{ + int tvp_flag = vdec_secure(hw_to_vdec(hevc)) ? + CODEC_MM_FLAGS_TVP : 0; + int buf_size = 64; + if ((hevc->max_pic_w * hevc->max_pic_h) > 0 && + (hevc->max_pic_w * hevc->max_pic_h) <= 1920*1088) { + buf_size = 24; + } + if (get_dbg_flag(hevc)) { + hevc_print(hevc, 0, "%s max_w %d max_h %d\n", + __func__, hevc->max_pic_w, hevc->max_pic_h); + } + + if (hevc->mmu_enable) { + hevc->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME, + hevc->index, + MAX_REF_PIC_NUM, + buf_size * SZ_1M, + tvp_flag + ); + if (!hevc->mmu_box) { + pr_err("h265 alloc mmu box failed!!\n"); + return -1; + } + } + hevc->bmmu_box = decoder_bmmu_box_alloc_box(DRIVER_NAME, + hevc->index, + BMMU_MAX_BUFFERS, + 4 + PAGE_SHIFT, + CODEC_MM_FLAGS_CMA_CLEAR | + CODEC_MM_FLAGS_FOR_VDECODER | + tvp_flag); + if (!hevc->bmmu_box) { + if (hevc->mmu_box) + decoder_mmu_box_free(hevc->mmu_box); + hevc->mmu_box = NULL; + pr_err("h265 alloc mmu box failed!!\n"); + return -1; + } + return 0; +} + +struct buf_stru_s +{ + int lcu_total; + int mc_buffer_size_h; + int mc_buffer_size_u_v_h; +}; + +#ifndef MV_USE_FIXED_BUF +static void dealloc_mv_bufs(struct hevc_state_s *hevc) +{ + int i; + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + if (hevc->m_mv_BUF[i].start_adr) { + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + hevc_print(hevc, 0, + "dealloc mv buf(%d) adr 0x%p size 0x%x used_flag %d\n", + i, hevc->m_mv_BUF[i].start_adr, + hevc->m_mv_BUF[i].size, + hevc->m_mv_BUF[i].used_flag); + decoder_bmmu_box_free_idx( + hevc->bmmu_box, + MV_BUFFER_IDX(i)); + hevc->m_mv_BUF[i].start_adr = 0; + hevc->m_mv_BUF[i].size = 0; + hevc->m_mv_BUF[i].used_flag = 0; + } + } + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + if (hevc->m_PIC[i] != NULL) + hevc->m_PIC[i]->mv_buf_index = -1; + } + +} + +static int alloc_mv_buf(struct hevc_state_s *hevc, int i) +{ + int ret = 0; + /*get_cma_alloc_ref();*/ /*DEBUG_TMP*/ + if (decoder_bmmu_box_alloc_buf_phy + (hevc->bmmu_box, + MV_BUFFER_IDX(i), hevc->mv_buf_size, + DRIVER_NAME, + &hevc->m_mv_BUF[i].start_adr) < 0) { + hevc->m_mv_BUF[i].start_adr = 0; + ret = -1; + } else { + hevc->m_mv_BUF[i].size = hevc->mv_buf_size; + hevc->m_mv_BUF[i].used_flag = 0; + ret = 0; + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "MV Buffer %d: start_adr %p size %x\n", + i, + (void *)hevc->m_mv_BUF[i].start_adr, + hevc->m_mv_BUF[i].size); + } + } + /*put_cma_alloc_ref();*/ /*DEBUG_TMP*/ + return ret; +} +#endif + +static int get_mv_buf(struct hevc_state_s *hevc, struct PIC_s *pic) +{ +#ifdef MV_USE_FIXED_BUF + if (pic && pic->index >= 0) + pic->mpred_mv_wr_start_addr = + hevc->work_space_buf->mpred_mv.buf_start + + (pic->index * MPRED_MV_BUF_SIZE); + return 0; +#else + int i; + int ret = -1; + int new_size; + if (pic->width > 1920 || pic->height > 1088) + new_size = MPRED_MV_BUF_SIZE + 0x10000; /*0x120000*/ + else + new_size = 0x40000 + 0x10000; + if (new_size != hevc->mv_buf_size) { + dealloc_mv_bufs(hevc); + hevc->mv_buf_size = new_size; + } + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + if (hevc->m_mv_BUF[i].start_adr && + hevc->m_mv_BUF[i].used_flag == 0) { + hevc->m_mv_BUF[i].used_flag = 1; + ret = i; + break; + } + } + if (ret < 0) { + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + if (hevc->m_mv_BUF[i].start_adr == 0) { + if (alloc_mv_buf(hevc, i) >= 0) { + hevc->m_mv_BUF[i].used_flag = 1; + ret = i; + } + break; + } + } + } + + if (ret >= 0) { + pic->mv_buf_index = ret; + pic->mpred_mv_wr_start_addr = + (hevc->m_mv_BUF[ret].start_adr + 0xffff) & + (~0xffff); + hevc_print(hevc, H265_DEBUG_BUFMGR_MORE, + "%s => %d (0x%x) size 0x%x\n", + __func__, ret, + pic->mpred_mv_wr_start_addr, + hevc->m_mv_BUF[ret].size); + + } else { + hevc_print(hevc, 0, + "%s: Error, mv buf is not enough\n", + __func__); + } + return ret; + +#endif +} + +static void put_mv_buf(struct hevc_state_s *hevc, + struct PIC_s *pic) +{ +#ifndef MV_USE_FIXED_BUF + int i = pic->mv_buf_index; + if (i < 0 || i >= MAX_REF_PIC_NUM) { + hevc_print(hevc, H265_DEBUG_BUFMGR_MORE, + "%s: index %d beyond range\n", + __func__, i); + return; + } + hevc_print(hevc, H265_DEBUG_BUFMGR_MORE, + "%s(%d): used_flag(%d)\n", + __func__, i, + hevc->m_mv_BUF[i].used_flag); + + if (hevc->m_mv_BUF[i].start_adr && + hevc->m_mv_BUF[i].used_flag) + hevc->m_mv_BUF[i].used_flag = 0; + pic->mv_buf_index = -1; +#endif +} + +static int cal_current_buf_size(struct hevc_state_s *hevc, + struct buf_stru_s *buf_stru) +{ + + int buf_size; + int pic_width = hevc->pic_w; + int pic_height = hevc->pic_h; + int lcu_size = hevc->lcu_size; + int pic_width_lcu = (pic_width % lcu_size) ? pic_width / lcu_size + + 1 : pic_width / lcu_size; + int pic_height_lcu = (pic_height % lcu_size) ? pic_height / lcu_size + + 1 : pic_height / lcu_size; + /*SUPPORT_10BIT*/ + int losless_comp_header_size = compute_losless_comp_header_size + (pic_width, pic_height); + /*always alloc buf for 10bit*/ + int losless_comp_body_size = compute_losless_comp_body_size + (hevc, pic_width, pic_height, 0); + int mc_buffer_size = losless_comp_header_size + + losless_comp_body_size; + int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16; + int mc_buffer_size_u_v_h = 0; + + int dw_mode = get_double_write_mode(hevc); + + if (hevc->mmu_enable) + buf_size = + ((MMU_COMPRESS_HEADER_SIZE + 0xffff) >> 16) + << 16; + else + buf_size = 0; + + if (dw_mode) { + int pic_width_dw = pic_width / + get_double_write_ratio(hevc, dw_mode); + int pic_height_dw = pic_height / + get_double_write_ratio(hevc, dw_mode); + + int pic_width_lcu_dw = (pic_width_dw % lcu_size) ? + pic_width_dw / lcu_size + 1 : + pic_width_dw / lcu_size; + int pic_height_lcu_dw = (pic_height_dw % lcu_size) ? + pic_height_dw / lcu_size + 1 : + pic_height_dw / lcu_size; + int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw; + + int mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2; + mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16; + /*64k alignment*/ + buf_size += ((mc_buffer_size_u_v_h << 16) * 3); + } + + if ((!hevc->mmu_enable) && + ((dw_mode & 0x10) == 0)) { + /* use compress mode without mmu, + need buf for compress decoding*/ + buf_size += (mc_buffer_size_h << 16); + } + + /*in case start adr is not 64k alignment*/ + if (buf_size > 0) + buf_size += 0x10000; + + if (buf_stru) { + buf_stru->lcu_total = pic_width_lcu * pic_height_lcu; + buf_stru->mc_buffer_size_h = mc_buffer_size_h; + buf_stru->mc_buffer_size_u_v_h = mc_buffer_size_u_v_h; + } + return buf_size; +} + +static int alloc_buf(struct hevc_state_s *hevc) +{ + int i; + int ret = -1; + int buf_size = cal_current_buf_size(hevc, NULL); + + for (i = 0; i < BUF_POOL_SIZE; i++) { + if (hevc->m_BUF[i].start_adr == 0) + break; + } + if (i < BUF_POOL_SIZE) { + if (buf_size > 0) { + /*get_cma_alloc_ref();*/ /*DEBUG_TMP*/ + /*alloc compress header first*/ + + if (decoder_bmmu_box_alloc_buf_phy + (hevc->bmmu_box, + VF_BUFFER_IDX(i), buf_size, + DRIVER_NAME, + &hevc->m_BUF[i].start_adr) < 0) + hevc->m_BUF[i].start_adr = 0; + else { + hevc->m_BUF[i].size = buf_size; + hevc->m_BUF[i].used_flag = 0; + ret = 0; + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "Buffer %d: start_adr %p size %x\n", + i, + (void *)hevc->m_BUF[i].start_adr, + hevc->m_BUF[i].size); + } + } + /*put_cma_alloc_ref();*/ /*DEBUG_TMP*/ + } else + ret = 0; + } + if (ret >= 0) { + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "alloc buf(%d) for %d/%d size 0x%x) => %p\n", + i, hevc->pic_w, hevc->pic_h, + buf_size, + hevc->m_BUF[i].start_adr); + } + } else { + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "alloc buf(%d) for %d/%d size 0x%x) => Fail!!!\n", + i, hevc->pic_w, hevc->pic_h, + buf_size); + } + } + return ret; +} + +static void set_buf_unused(struct hevc_state_s *hevc, int i) +{ + if (i >= 0 && i < BUF_POOL_SIZE) + hevc->m_BUF[i].used_flag = 0; +} + +static void dealloc_unused_buf(struct hevc_state_s *hevc) +{ + int i; + for (i = 0; i < BUF_POOL_SIZE; i++) { + if (hevc->m_BUF[i].start_adr && + hevc->m_BUF[i].used_flag == 0) { + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "dealloc buf(%d) adr 0x%p size 0x%x\n", + i, hevc->m_BUF[i].start_adr, + hevc->m_BUF[i].size); + } + decoder_bmmu_box_free_idx( + hevc->bmmu_box, + VF_BUFFER_IDX(i)); + hevc->m_BUF[i].start_adr = 0; + hevc->m_BUF[i].size = 0; + } + } + +} + +static void dealloc_pic_buf(struct hevc_state_s *hevc, + struct PIC_s *pic) +{ + int i = pic->BUF_index; + pic->BUF_index = -1; + if (i >= 0 && + i < BUF_POOL_SIZE && + hevc->m_BUF[i].start_adr) { + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "dealloc buf(%d) adr 0x%p size 0x%x\n", + i, hevc->m_BUF[i].start_adr, + hevc->m_BUF[i].size); + } + decoder_bmmu_box_free_idx( + hevc->bmmu_box, + VF_BUFFER_IDX(i)); + hevc->m_BUF[i].used_flag = 0; + hevc->m_BUF[i].start_adr = 0; + hevc->m_BUF[i].size = 0; + } +} + +static int get_work_pic_num(struct hevc_state_s *hevc) +{ + int used_buf_num = 0; + if (get_dynamic_buf_num_margin(hevc) > 0) { + used_buf_num = hevc->sps_num_reorder_pics_0 + + get_dynamic_buf_num_margin(hevc); +#ifdef MULTI_INSTANCE_SUPPORT + /* + need one more for multi instance, as + apply_ref_pic_set() has no chanch to run to + to clear referenced flag in some case + */ + if (hevc->m_ins_flag) + used_buf_num++; +#endif + } else + used_buf_num = max_buf_num; + + if (used_buf_num > MAX_BUF_NUM) + used_buf_num = MAX_BUF_NUM; + return used_buf_num; +} + +static int get_alloc_pic_count(struct hevc_state_s *hevc) +{ + int alloc_pic_count = 0; + int i; + struct PIC_s *pic; + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + pic = hevc->m_PIC[i]; + if (pic && pic->index >= 0) + alloc_pic_count++; + } + return alloc_pic_count; +} + +static int config_pic(struct hevc_state_s *hevc, struct PIC_s *pic) +{ + int ret = -1; + int i; + /*int lcu_size_log2 = hevc->lcu_size_log2; + int MV_MEM_UNIT=lcu_size_log2== + 6 ? 0x100 : lcu_size_log2==5 ? 0x40 : 0x10;*/ + /*int MV_MEM_UNIT = lcu_size_log2 == 6 ? 0x200 : lcu_size_log2 == + 5 ? 0x80 : 0x20; + int mpred_mv_end = hevc->work_space_buf->mpred_mv.buf_start + + hevc->work_space_buf->mpred_mv.buf_size;*/ + unsigned int y_adr = 0; + struct buf_stru_s buf_stru; + int buf_size = cal_current_buf_size(hevc, &buf_stru); + int dw_mode = get_double_write_mode(hevc); + + for (i = 0; i < BUF_POOL_SIZE; i++) { + if (hevc->m_BUF[i].start_adr != 0 && + hevc->m_BUF[i].used_flag == 0 && + buf_size <= hevc->m_BUF[i].size) { + hevc->m_BUF[i].used_flag = 1; + break; + } + } + if (i >= BUF_POOL_SIZE) + return -1; + + if (hevc->mmu_enable) { + pic->header_adr = hevc->m_BUF[i].start_adr; + y_adr = hevc->m_BUF[i].start_adr + MMU_COMPRESS_HEADER_SIZE; + } else + y_adr = hevc->m_BUF[i].start_adr; + + y_adr = ((y_adr + 0xffff) >> 16) << 16; /*64k alignment*/ + pic->POC = INVALID_POC; + /*ensure get_pic_by_POC() + not get the buffer not decoded*/ + pic->BUF_index = i; + + if ((!hevc->mmu_enable) && + ((dw_mode & 0x10) == 0) + ) { + pic->mc_y_adr = y_adr; + y_adr += (buf_stru.mc_buffer_size_h << 16); + } + pic->mc_canvas_y = pic->index; + pic->mc_canvas_u_v = pic->index; + if (dw_mode & 0x10) { + pic->mc_y_adr = y_adr; + pic->mc_u_v_adr = y_adr + + ((buf_stru.mc_buffer_size_u_v_h << 16) << 1); + + pic->mc_canvas_y = (pic->index << 1); + pic->mc_canvas_u_v = (pic->index << 1) + 1; + + pic->dw_y_adr = pic->mc_y_adr; + pic->dw_u_v_adr = pic->mc_u_v_adr; + } else if (dw_mode) { + pic->dw_y_adr = y_adr; + pic->dw_u_v_adr = pic->dw_y_adr + + ((buf_stru.mc_buffer_size_u_v_h << 16) << 1); + } + + + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "%s index %d BUF_index %d mc_y_adr %x\n", + __func__, pic->index, + pic->BUF_index, pic->mc_y_adr); + if (hevc->mmu_enable && + dw_mode) + hevc_print(hevc, 0, + "mmu double write adr %ld\n", + pic->cma_alloc_addr); + + + } + ret = 0; + + return ret; +} + +static void init_pic_list(struct hevc_state_s *hevc) +{ + int i; + int init_buf_num = get_work_pic_num(hevc); + int dw_mode = get_double_write_mode(hevc); + + /*alloc decoder buf*/ + for (i = 0; i < init_buf_num; i++) { + if (alloc_buf(hevc) < 0) { + if (i <= 8) { + /*if alloced (i+1)>=9 + don't send errors.*/ + hevc->fatal_error |= + DECODER_FATAL_ERROR_NO_MEM; + } + break; + } + } + + for (i = 0; i < init_buf_num; i++) { + struct PIC_s *pic = + vmalloc(sizeof(struct PIC_s)); + if (pic == NULL) { + hevc_print(hevc, 0, + "%s: alloc pic %d fail!!!\n", + __func__, i); + break; + } + memset(pic, 0, sizeof(struct PIC_s)); + hevc->m_PIC[i] = pic; + pic->index = i; + pic->BUF_index = -1; + pic->mv_buf_index = -1; + if (config_pic(hevc, pic) < 0) { + if (get_dbg_flag(hevc)) + hevc_print(hevc, 0, + "Config_pic %d fail\n", pic->index); + pic->index = -1; + i++; + break; + } + pic->width = hevc->pic_w; + pic->height = hevc->pic_h; + pic->double_write_mode = dw_mode; + if (pic->double_write_mode) + set_canvas(hevc, pic); + } + + for (; i < MAX_REF_PIC_NUM; i++) { + struct PIC_s *pic = + vmalloc(sizeof(struct PIC_s)); + if (pic == NULL) { + hevc_print(hevc, 0, + "%s: alloc pic %d fail!!!\n", + __func__, i); + break; + } + memset(pic, 0, sizeof(struct PIC_s)); + hevc->m_PIC[i] = pic; + pic->index = -1; + pic->BUF_index = -1; + } + +} + +static void uninit_pic_list(struct hevc_state_s *hevc) +{ + int i; +#ifndef MV_USE_FIXED_BUF + dealloc_mv_bufs(hevc); +#endif + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + struct PIC_s *pic = hevc->m_PIC[i]; + + if (pic) { + release_aux_data(hevc, pic); + vfree(pic); + hevc->m_PIC[i] = NULL; + } + } +} + +#ifdef LOSLESS_COMPRESS_MODE +static void init_decode_head_hw(struct hevc_state_s *hevc) +{ + + struct BuffInfo_s *buf_spec = hevc->work_space_buf; + unsigned int data32; + + int losless_comp_header_size = + compute_losless_comp_header_size(hevc->pic_w, + hevc->pic_h); + int losless_comp_body_size = compute_losless_comp_body_size(hevc, + hevc->pic_w, hevc->pic_h, hevc->mem_saving_mode); + + hevc->losless_comp_body_size = losless_comp_body_size; + + + if (hevc->mmu_enable) { + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4)); + WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0); + } else { + if (hevc->mem_saving_mode == 1) + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, + (1 << 3) | ((workaround_enable & 2) ? 1 : 0)); + else + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, + ((workaround_enable & 2) ? 1 : 0)); + WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5)); + /* + *WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff); + * //8-bit mode + */ + } + WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size); + WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size); + WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size); + + if (hevc->mmu_enable) { + WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start); + WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, + buf_spec->mmu_vbh.buf_start + + buf_spec->mmu_vbh.buf_size/2); + data32 = READ_VREG(HEVC_SAO_CTRL9); + data32 |= 0x1; + WRITE_VREG(HEVC_SAO_CTRL9, data32); + + /* use HEVC_CM_HEADER_START_ADDR */ + data32 = READ_VREG(HEVC_SAO_CTRL5); + data32 |= (1<<10); + WRITE_VREG(HEVC_SAO_CTRL5, data32); + } + + if (!hevc->m_ins_flag) + hevc_print(hevc, 0, + "%s: (%d, %d) body_size 0x%x header_size 0x%x\n", + __func__, hevc->pic_w, hevc->pic_h, + losless_comp_body_size, losless_comp_header_size); + +} +#endif +#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464 + +static void init_pic_list_hw(struct hevc_state_s *hevc) +{ + int i; + int cur_pic_num = MAX_REF_PIC_NUM; + int dw_mode = get_double_write_mode(hevc); + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, + (0x1 << 1) | (0x1 << 2)); + else + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0); + + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + if (hevc->m_PIC[i] == NULL || + hevc->m_PIC[i]->index == -1) { + cur_pic_num = i; + break; + } + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) { + if (hevc->mmu_enable) + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, + hevc->m_PIC[i]->header_adr>>5); + else + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, + hevc->m_PIC[i]->mc_y_adr >> 5); + } else + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, + hevc->m_PIC[i]->mc_y_adr | + (hevc->m_PIC[i]->mc_canvas_y << 8) | 0x1); + if (dw_mode & 0x10) { + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) { + if (hevc->mmu_enable) + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, + hevc->m_PIC[i]->header_adr>>5); + else + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, + hevc->m_PIC[i]->mc_u_v_adr >> 5); + } + else + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, + hevc->m_PIC[i]->mc_u_v_adr | + (hevc->m_PIC[i]->mc_canvas_u_v << 8) + | 0x1); + } + } + if (cur_pic_num == 0) + return; + for (; i < MAX_REF_PIC_NUM; i++) { + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) { + if (hevc->mmu_enable) + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, + hevc->m_PIC[cur_pic_num-1]->header_adr>>5); + else + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, + hevc->m_PIC[cur_pic_num-1]->mc_y_adr >> 5); +#ifndef LOSLESS_COMPRESS_MODE + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, + hevc->m_PIC[cur_pic_num-1]->mc_u_v_adr >> 5); +#endif + } else { + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, + hevc->m_PIC[cur_pic_num-1]->mc_y_adr| + (hevc->m_PIC[cur_pic_num-1]->mc_canvas_y<<8) + | 0x1); +#ifndef LOSLESS_COMPRESS_MODE + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, + hevc->m_PIC[cur_pic_num-1]->mc_u_v_adr| + (hevc->m_PIC[cur_pic_num-1]->mc_canvas_u_v<<8) + | 0x1); +#endif + } + } + + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1); + + /* Zero out canvas registers in IPP -- avoid simulation X */ + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (0 << 8) | (0 << 1) | 1); + for (i = 0; i < 32; i++) + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0); + +#ifdef LOSLESS_COMPRESS_MODE + if ((dw_mode & 0x10) == 0) + init_decode_head_hw(hevc); +#endif + +} + + +static void dump_pic_list(struct hevc_state_s *hevc) +{ + int i; + struct PIC_s *pic; + + hevc_print(hevc, 0, + "pic_list_init_flag is %d\r\n", hevc->pic_list_init_flag); + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + pic = hevc->m_PIC[i]; + if (pic == NULL || pic->index == -1) + continue; + hevc_print_cont(hevc, 0, + "index %d buf_idx %d mv_idx %d decode_idx:%d, POC:%d, referenced:%d, ", + pic->index, pic->BUF_index, +#ifndef MV_USE_FIXED_BUF + pic->mv_buf_index, +#else + -1, +#endif + pic->decode_idx, pic->POC, pic->referenced); + hevc_print_cont(hevc, 0, + "num_reorder_pic:%d, output_mark:%d, w/h %d,%d", + pic->num_reorder_pic, pic->output_mark, + pic->width, pic->height); + hevc_print_cont(hevc, 0, + "output_ready:%d, mv_wr_start %x vf_ref %d\n", + pic->output_ready, pic->mpred_mv_wr_start_addr, + pic->vf_ref); + } +} + +static void clear_referenced_flag(struct hevc_state_s *hevc) +{ + int i; + struct PIC_s *pic; + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + pic = hevc->m_PIC[i]; + if (pic == NULL || pic->index == -1) + continue; + if (pic->referenced) { + pic->referenced = 0; + put_mv_buf(hevc, pic); + } + } +} + +static struct PIC_s *output_pic(struct hevc_state_s *hevc, + unsigned char flush_flag) +{ + int num_pic_not_yet_display = 0; + int i; + struct PIC_s *pic; + struct PIC_s *pic_display = NULL; + + if (hevc->i_only & 0x4) { + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + pic = hevc->m_PIC[i]; + if (pic == NULL || + (pic->index == -1) || + (pic->BUF_index == -1) || + (pic->POC == INVALID_POC)) + continue; + if (pic->output_mark) { + if (pic_display) { + if (pic->decode_idx < + pic_display->decode_idx) + pic_display = pic; + + } else + pic_display = pic; + + } + } + if (pic_display) { + pic_display->output_mark = 0; + pic_display->recon_mark = 0; + pic_display->output_ready = 1; + pic_display->referenced = 0; + put_mv_buf(hevc, pic_display); + } + } else { + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + pic = hevc->m_PIC[i]; + if (pic == NULL || + (pic->index == -1) || + (pic->BUF_index == -1) || + (pic->POC == INVALID_POC)) + continue; + if (pic->output_mark) + num_pic_not_yet_display++; + if (pic->slice_type == 2 && + hevc->vf_pre_count == 0 && + fast_output_enable & 0x1) { + /*fast output for first I picture*/ + pic->num_reorder_pic = 0; + hevc_print(hevc, 0, "VH265: output first frame\n"); + } + } + + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + pic = hevc->m_PIC[i]; + if (pic == NULL || + (pic->index == -1) || + (pic->BUF_index == -1) || + (pic->POC == INVALID_POC)) + continue; + if (pic->output_mark) { + if (pic_display) { + if (pic->POC < pic_display->POC) + pic_display = pic; + else if ((pic->POC == pic_display->POC) + && (pic->decode_idx < + pic_display-> + decode_idx)) + pic_display + = pic; + } else + pic_display = pic; + } + } + if (pic_display) { + if ((num_pic_not_yet_display > + pic_display->num_reorder_pic) + || flush_flag) { + pic_display->output_mark = 0; + pic_display->recon_mark = 0; + pic_display->output_ready = 1; + } else if (num_pic_not_yet_display >= + (MAX_REF_PIC_NUM - 1)) { + pic_display->output_mark = 0; + pic_display->recon_mark = 0; + pic_display->output_ready = 1; + hevc_print(hevc, 0, + "Warning, num_reorder_pic %d is byeond buf num\n", + pic_display->num_reorder_pic); + } else + pic_display = NULL; + } + } + return pic_display; +} + +static int config_mc_buffer(struct hevc_state_s *hevc, struct PIC_s *cur_pic) +{ + int i; + struct PIC_s *pic; + + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + hevc_print(hevc, 0, + "config_mc_buffer entered .....\n"); + if (cur_pic->slice_type != 2) { /* P and B pic */ + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (0 << 8) | (0 << 1) | 1); + for (i = 0; i < cur_pic->RefNum_L0; i++) { + pic = + get_ref_pic_by_POC(hevc, + cur_pic-> + m_aiRefPOCList0[cur_pic-> + slice_idx][i]); + if (pic) { + if ((pic->width != hevc->pic_w) || + (pic->height != hevc->pic_h)) { + hevc_print(hevc, 0, + "%s: Wrong reference pic (poc %d) width/height %d/%d\n", + __func__, pic->POC, + pic->width, pic->height); + cur_pic->error_mark = 1; + } + if (pic->error_mark) + cur_pic->error_mark = 1; + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, + (pic->mc_canvas_u_v << 16) + | (pic->mc_canvas_u_v + << 8) | + pic->mc_canvas_y); + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print_cont(hevc, 0, + "refid %x mc_canvas_u_v %x", + i, pic->mc_canvas_u_v); + hevc_print_cont(hevc, 0, + " mc_canvas_y %x\n", + pic->mc_canvas_y); + } + } else + cur_pic->error_mark = 1; + + if (pic == NULL || pic->error_mark) { + hevc_print(hevc, 0, + "Error %s, %dth poc (%d) %s", + __func__, i, + cur_pic->m_aiRefPOCList0[cur_pic-> + slice_idx][i], + pic ? "has error" : + "not in list0"); + } + } + } + if (cur_pic->slice_type == 0) { /* B pic */ + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + hevc_print(hevc, 0, + "config_mc_buffer RefNum_L1\n"); + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (16 << 8) | (0 << 1) | 1); + for (i = 0; i < cur_pic->RefNum_L1; i++) { + pic = + get_ref_pic_by_POC(hevc, + cur_pic-> + m_aiRefPOCList1[cur_pic-> + slice_idx][i]); + if (pic) { + if ((pic->width != hevc->pic_w) || + (pic->height != hevc->pic_h)) { + hevc_print(hevc, 0, + "%s: Wrong reference pic (poc %d) width/height %d/%d\n", + __func__, pic->POC, + pic->width, pic->height); + cur_pic->error_mark = 1; + } + + if (pic->error_mark) + cur_pic->error_mark = 1; + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, + (pic->mc_canvas_u_v << 16) + | (pic->mc_canvas_u_v + << 8) | + pic->mc_canvas_y); + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print_cont(hevc, 0, + "refid %x mc_canvas_u_v %x", + i, pic->mc_canvas_u_v); + hevc_print_cont(hevc, 0, + " mc_canvas_y %x\n", + pic->mc_canvas_y); + } + } else + cur_pic->error_mark = 1; + + if (pic == NULL || pic->error_mark) { + hevc_print(hevc, 0, + "Error %s, %dth poc (%d) %s", + __func__, i, + cur_pic->m_aiRefPOCList1[cur_pic-> + slice_idx][i], + pic ? "has error" : + "not in list1"); + } + } + } + return 0; +} + +static void apply_ref_pic_set(struct hevc_state_s *hevc, int cur_poc, + union param_u *params) +{ + int ii, i; + int poc_tmp; + struct PIC_s *pic; + unsigned char is_referenced; + /* hevc_print(hevc, 0, + "%s cur_poc %d\n", __func__, cur_poc); */ + for (ii = 0; ii < MAX_REF_PIC_NUM; ii++) { + pic = hevc->m_PIC[ii]; + if (pic == NULL || + pic->index == -1 || + pic->BUF_index == -1 + ) + continue; + + if ((pic->referenced == 0 || pic->POC == cur_poc)) + continue; + is_referenced = 0; + for (i = 0; i < 16; i++) { + int delt; + + if (params->p.CUR_RPS[i] & 0x8000) + break; + delt = + params->p.CUR_RPS[i] & + ((1 << (RPS_USED_BIT - 1)) - 1); + if (params->p.CUR_RPS[i] & (1 << (RPS_USED_BIT - 1))) { + poc_tmp = + cur_poc - ((1 << (RPS_USED_BIT - 1)) - + delt); + } else + poc_tmp = cur_poc + delt; + if (poc_tmp == pic->POC) { + is_referenced = 1; + /* hevc_print(hevc, 0, "i is %d\n", i); */ + break; + } + } + if (is_referenced == 0) { + pic->referenced = 0; + put_mv_buf(hevc, pic); + /* hevc_print(hevc, 0, + "set poc %d reference to 0\n", pic->POC); */ + } + } + +} + +static void set_ref_pic_list(struct hevc_state_s *hevc, union param_u *params) +{ + struct PIC_s *pic = hevc->cur_pic; + int i, rIdx; + int num_neg = 0; + int num_pos = 0; + int total_num; + int num_ref_idx_l0_active = + (params->p.num_ref_idx_l0_active > + MAX_REF_ACTIVE) ? MAX_REF_ACTIVE : + params->p.num_ref_idx_l0_active; + int num_ref_idx_l1_active = + (params->p.num_ref_idx_l1_active > + MAX_REF_ACTIVE) ? MAX_REF_ACTIVE : + params->p.num_ref_idx_l1_active; + + int RefPicSetStCurr0[16]; + int RefPicSetStCurr1[16]; + + for (i = 0; i < 16; i++) { + RefPicSetStCurr0[i] = 0; + RefPicSetStCurr1[i] = 0; + pic->m_aiRefPOCList0[pic->slice_idx][i] = 0; + pic->m_aiRefPOCList1[pic->slice_idx][i] = 0; + } + for (i = 0; i < 16; i++) { + if (params->p.CUR_RPS[i] & 0x8000) + break; + if ((params->p.CUR_RPS[i] >> RPS_USED_BIT) & 1) { + int delt = + params->p.CUR_RPS[i] & + ((1 << (RPS_USED_BIT - 1)) - 1); + + if ((params->p.CUR_RPS[i] >> (RPS_USED_BIT - 1)) & 1) { + RefPicSetStCurr0[num_neg] = + pic->POC - ((1 << (RPS_USED_BIT - 1)) - + delt); + /* hevc_print(hevc, 0, + * "RefPicSetStCurr0 %x %x %x\n", + * RefPicSetStCurr0[num_neg], pic->POC, + * (0x800-(params[i]&0x7ff))); + */ + num_neg++; + } else { + RefPicSetStCurr1[num_pos] = pic->POC + delt; + /* hevc_print(hevc, 0, + * "RefPicSetStCurr1 %d\n", + * RefPicSetStCurr1[num_pos]); + */ + num_pos++; + } + } + } + total_num = num_neg + num_pos; + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "%s: curpoc %d slice_type %d, total %d ", + __func__, pic->POC, params->p.slice_type, total_num); + hevc_print_cont(hevc, 0, + "num_neg %d num_list0 %d num_list1 %d\n", + num_neg, num_ref_idx_l0_active, num_ref_idx_l1_active); + } + + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "HEVC Stream buf start "); + hevc_print_cont(hevc, 0, + "%x end %x wr %x rd %x lev %x ctl %x intctl %x\n", + READ_VREG(HEVC_STREAM_START_ADDR), + READ_VREG(HEVC_STREAM_END_ADDR), + READ_VREG(HEVC_STREAM_WR_PTR), + READ_VREG(HEVC_STREAM_RD_PTR), + READ_VREG(HEVC_STREAM_LEVEL), + READ_VREG(HEVC_STREAM_FIFO_CTL), + READ_VREG(HEVC_PARSER_INT_CONTROL)); + } + + if (total_num > 0) { + if (params->p.modification_flag & 0x1) { + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + hevc_print(hevc, 0, "ref0 POC (modification):"); + for (rIdx = 0; rIdx < num_ref_idx_l0_active; rIdx++) { + int cIdx = params->p.modification_list[rIdx]; + + pic->m_aiRefPOCList0[pic->slice_idx][rIdx] = + cIdx >= + num_neg ? RefPicSetStCurr1[cIdx - + num_neg] : + RefPicSetStCurr0[cIdx]; + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print_cont(hevc, 0, "%d ", + pic->m_aiRefPOCList0[pic-> + slice_idx] + [rIdx]); + } + } + } else { + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + hevc_print(hevc, 0, "ref0 POC:"); + for (rIdx = 0; rIdx < num_ref_idx_l0_active; rIdx++) { + int cIdx = rIdx % total_num; + + pic->m_aiRefPOCList0[pic->slice_idx][rIdx] = + cIdx >= + num_neg ? RefPicSetStCurr1[cIdx - + num_neg] : + RefPicSetStCurr0[cIdx]; + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print_cont(hevc, 0, "%d ", + pic->m_aiRefPOCList0[pic-> + slice_idx] + [rIdx]); + } + } + } + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + hevc_print_cont(hevc, 0, "\n"); + if (params->p.slice_type == B_SLICE) { + if (params->p.modification_flag & 0x2) { + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + hevc_print(hevc, 0, + "ref1 POC (modification):"); + for (rIdx = 0; rIdx < num_ref_idx_l1_active; + rIdx++) { + int cIdx; + + if (params->p.modification_flag & 0x1) { + cIdx = + params->p. + modification_list + [num_ref_idx_l0_active + + rIdx]; + } else { + cIdx = + params->p. + modification_list[rIdx]; + } + pic->m_aiRefPOCList1[pic-> + slice_idx][rIdx] = + cIdx >= + num_pos ? + RefPicSetStCurr0[cIdx - num_pos] + : RefPicSetStCurr1[cIdx]; + if (get_dbg_flag(hevc) & + H265_DEBUG_BUFMGR) { + hevc_print_cont(hevc, 0, "%d ", + pic-> + m_aiRefPOCList1[pic-> + slice_idx] + [rIdx]); + } + } + } else { + if (get_dbg_flag(hevc) & + H265_DEBUG_BUFMGR) + hevc_print(hevc, 0, "ref1 POC:"); + for (rIdx = 0; rIdx < num_ref_idx_l1_active; + rIdx++) { + int cIdx = rIdx % total_num; + + pic->m_aiRefPOCList1[pic-> + slice_idx][rIdx] = + cIdx >= + num_pos ? + RefPicSetStCurr0[cIdx - + num_pos] + : RefPicSetStCurr1[cIdx]; + if (get_dbg_flag(hevc) & + H265_DEBUG_BUFMGR) { + hevc_print_cont(hevc, 0, "%d ", + pic-> + m_aiRefPOCList1[pic-> + slice_idx] + [rIdx]); + } + } + } + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + hevc_print_cont(hevc, 0, "\n"); + } + } + /*set m_PIC */ + pic->slice_type = (params->p.slice_type == I_SLICE) ? 2 : + (params->p.slice_type == P_SLICE) ? 1 : + (params->p.slice_type == B_SLICE) ? 0 : 3; + pic->RefNum_L0 = num_ref_idx_l0_active; + pic->RefNum_L1 = num_ref_idx_l1_active; +} + +static void update_tile_info(struct hevc_state_s *hevc, int pic_width_cu, + int pic_height_cu, int sao_mem_unit, + union param_u *params) +{ + int i, j; + int start_cu_x, start_cu_y; + int sao_vb_size = (sao_mem_unit + (2 << 4)) * pic_height_cu; + int sao_abv_size = sao_mem_unit * pic_width_cu; + + hevc->tile_enabled = params->p.tiles_enabled_flag & 1; + if (params->p.tiles_enabled_flag & 1) { + hevc->num_tile_col = params->p.num_tile_columns_minus1 + 1; + hevc->num_tile_row = params->p.num_tile_rows_minus1 + 1; + + if (hevc->num_tile_row > MAX_TILE_ROW_NUM + || hevc->num_tile_row <= 0) { + hevc->num_tile_row = 1; + hevc_print(hevc, 0, + "%s: num_tile_rows_minus1 (%d) error!!\n", + __func__, params->p.num_tile_rows_minus1); + } + if (hevc->num_tile_col > MAX_TILE_COL_NUM + || hevc->num_tile_col <= 0) { + hevc->num_tile_col = 1; + hevc_print(hevc, 0, + "%s: num_tile_columns_minus1 (%d) error!!\n", + __func__, params->p.num_tile_columns_minus1); + } + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "%s pic_w_cu %d pic_h_cu %d tile_enabled ", + __func__, pic_width_cu, pic_height_cu); + hevc_print_cont(hevc, 0, + "num_tile_col %d num_tile_row %d:\n", + hevc->num_tile_col, hevc->num_tile_row); + } + + if (params->p.tiles_enabled_flag & 2) { /* uniform flag */ + int w = pic_width_cu / hevc->num_tile_col; + int h = pic_height_cu / hevc->num_tile_row; + + start_cu_y = 0; + for (i = 0; i < hevc->num_tile_row; i++) { + start_cu_x = 0; + for (j = 0; j < hevc->num_tile_col; j++) { + if (j == (hevc->num_tile_col - 1)) { + hevc->m_tile[i][j].width = + pic_width_cu - + start_cu_x; + } else + hevc->m_tile[i][j].width = w; + if (i == (hevc->num_tile_row - 1)) { + hevc->m_tile[i][j].height = + pic_height_cu - + start_cu_y; + } else + hevc->m_tile[i][j].height = h; + hevc->m_tile[i][j].start_cu_x + = start_cu_x; + hevc->m_tile[i][j].start_cu_y + = start_cu_y; + hevc->m_tile[i][j].sao_vb_start_addr = + hevc->work_space_buf->sao_vb. + buf_start + j * sao_vb_size; + hevc->m_tile[i][j].sao_abv_start_addr = + hevc->work_space_buf->sao_abv. + buf_start + i * sao_abv_size; + if (get_dbg_flag(hevc) & + H265_DEBUG_BUFMGR) { + hevc_print_cont(hevc, 0, + "{y=%d, x=%d w %d h %d ", + i, j, hevc->m_tile[i][j].width, + hevc->m_tile[i][j].height); + hevc_print_cont(hevc, 0, + "start_x %d start_y %d ", + hevc->m_tile[i][j].start_cu_x, + hevc->m_tile[i][j].start_cu_y); + hevc_print_cont(hevc, 0, + "sao_vb_start 0x%x ", + hevc->m_tile[i][j]. + sao_vb_start_addr); + hevc_print_cont(hevc, 0, + "sao_abv_start 0x%x}\n", + hevc->m_tile[i][j]. + sao_abv_start_addr); + } + start_cu_x += hevc->m_tile[i][j].width; + + } + start_cu_y += hevc->m_tile[i][0].height; + } + } else { + start_cu_y = 0; + for (i = 0; i < hevc->num_tile_row; i++) { + start_cu_x = 0; + for (j = 0; j < hevc->num_tile_col; j++) { + if (j == (hevc->num_tile_col - 1)) { + hevc->m_tile[i][j].width = + pic_width_cu - + start_cu_x; + } else { + hevc->m_tile[i][j].width = + params->p.tile_width[j]; + } + if (i == (hevc->num_tile_row - 1)) { + hevc->m_tile[i][j].height = + pic_height_cu - + start_cu_y; + } else { + hevc->m_tile[i][j].height = + params-> + p.tile_height[i]; + } + hevc->m_tile[i][j].start_cu_x + = start_cu_x; + hevc->m_tile[i][j].start_cu_y + = start_cu_y; + hevc->m_tile[i][j].sao_vb_start_addr = + hevc->work_space_buf->sao_vb. + buf_start + j * sao_vb_size; + hevc->m_tile[i][j].sao_abv_start_addr = + hevc->work_space_buf->sao_abv. + buf_start + i * sao_abv_size; + if (get_dbg_flag(hevc) & + H265_DEBUG_BUFMGR) { + hevc_print_cont(hevc, 0, + "{y=%d, x=%d w %d h %d ", + i, j, hevc->m_tile[i][j].width, + hevc->m_tile[i][j].height); + hevc_print_cont(hevc, 0, + "start_x %d start_y %d ", + hevc->m_tile[i][j].start_cu_x, + hevc->m_tile[i][j].start_cu_y); + hevc_print_cont(hevc, 0, + "sao_vb_start 0x%x ", + hevc->m_tile[i][j]. + sao_vb_start_addr); + hevc_print_cont(hevc, 0, + "sao_abv_start 0x%x}\n", + hevc->m_tile[i][j]. + sao_abv_start_addr); + + } + start_cu_x += hevc->m_tile[i][j].width; + } + start_cu_y += hevc->m_tile[i][0].height; + } + } + } else { + hevc->num_tile_col = 1; + hevc->num_tile_row = 1; + hevc->m_tile[0][0].width = pic_width_cu; + hevc->m_tile[0][0].height = pic_height_cu; + hevc->m_tile[0][0].start_cu_x = 0; + hevc->m_tile[0][0].start_cu_y = 0; + hevc->m_tile[0][0].sao_vb_start_addr = + hevc->work_space_buf->sao_vb.buf_start; + hevc->m_tile[0][0].sao_abv_start_addr = + hevc->work_space_buf->sao_abv.buf_start; + } +} + +static int get_tile_index(struct hevc_state_s *hevc, int cu_adr, + int pic_width_lcu) +{ + int cu_x; + int cu_y; + int tile_x = 0; + int tile_y = 0; + int i; + + if (pic_width_lcu == 0) { + if (get_dbg_flag(hevc)) { + hevc_print(hevc, 0, + "%s Error, pic_width_lcu is 0, pic_w %d, pic_h %d\n", + __func__, hevc->pic_w, hevc->pic_h); + } + return -1; + } + cu_x = cu_adr % pic_width_lcu; + cu_y = cu_adr / pic_width_lcu; + if (hevc->tile_enabled) { + for (i = 0; i < hevc->num_tile_col; i++) { + if (cu_x >= hevc->m_tile[0][i].start_cu_x) + tile_x = i; + else + break; + } + for (i = 0; i < hevc->num_tile_row; i++) { + if (cu_y >= hevc->m_tile[i][0].start_cu_y) + tile_y = i; + else + break; + } + } + return (tile_x) | (tile_y << 8); +} + +static void print_scratch_error(int error_num) +{ +#if 0 + if (get_dbg_flag(hevc)) { + hevc_print(hevc, 0, + " ERROR : HEVC_ASSIST_SCRATCH_TEST Error : %d\n", + error_num); + } +#endif +} + +static void hevc_config_work_space_hw(struct hevc_state_s *hevc) +{ + struct BuffInfo_s *buf_spec = hevc->work_space_buf; + + if (get_dbg_flag(hevc)) + hevc_print(hevc, 0, + "%s %x %x %x %x %x %x %x %x %x %x %x %x %x\n", + __func__, + buf_spec->ipp.buf_start, + buf_spec->start_adr, + buf_spec->short_term_rps.buf_start, + buf_spec->vps.buf_start, + buf_spec->sps.buf_start, + buf_spec->pps.buf_start, + buf_spec->sao_up.buf_start, + buf_spec->swap_buf.buf_start, + buf_spec->swap_buf2.buf_start, + buf_spec->scalelut.buf_start, + buf_spec->dblk_para.buf_start, + buf_spec->dblk_data.buf_start, + buf_spec->dblk_data2.buf_start); + WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE, buf_spec->ipp.buf_start); + if ((get_dbg_flag(hevc) & H265_DEBUG_SEND_PARAM_WITH_REG) == 0) + WRITE_VREG(HEVC_RPM_BUFFER, (u32)hevc->rpm_phy_addr); + WRITE_VREG(HEVC_SHORT_TERM_RPS, buf_spec->short_term_rps.buf_start); + WRITE_VREG(HEVC_VPS_BUFFER, buf_spec->vps.buf_start); + WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start); + WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start); + WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start); + if (hevc->mmu_enable) { + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) { + WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, hevc->frame_mmu_map_phy_addr); + hevc_print(hevc, H265_DEBUG_BUFMGR_MORE, + "write HEVC_ASSIST_MMU_MAP_ADDR\n"); + } else + WRITE_VREG(H265_MMU_MAP_BUFFER, hevc->frame_mmu_map_phy_addr); + } /*else + WRITE_VREG(HEVC_STREAM_SWAP_BUFFER, + buf_spec->swap_buf.buf_start); + WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2, buf_spec->swap_buf2.buf_start);*/ + WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start); + /* cfg_p_addr */ + WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start); + /* cfg_d_addr */ + WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start); + + WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_data2.buf_start); + + WRITE_VREG(LMEM_DUMP_ADR, (u32)hevc->lmem_phy_addr); +} + +static void parser_cmd_write(void) +{ + u32 i; + const unsigned short parser_cmd[PARSER_CMD_NUMBER] = { + 0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423, + 0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE, + 0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A, + 0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408, + 0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D, + 0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00, + 0x7C00 + }; + for (i = 0; i < PARSER_CMD_NUMBER; i++) + WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]); +} + +static void hevc_init_decoder_hw(struct hevc_state_s *hevc, + int decode_pic_begin, int decode_pic_num) +{ + unsigned int data32; + int i; +#if 0 + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) { + /* Set MCR fetch priorities*/ + data32 = 0x1 | (0x1 << 2) | (0x1 <<3) | + (24 << 4) | (32 << 11) | (24 << 18) | (32 << 25); + WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32); + } +#endif +#if 1 + /* m8baby test1902 */ + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + hevc_print(hevc, 0, + "%s\n", __func__); + data32 = READ_VREG(HEVC_PARSER_VERSION); + if (data32 != 0x00010001) { + print_scratch_error(25); + return; + } + WRITE_VREG(HEVC_PARSER_VERSION, 0x5a5a55aa); + data32 = READ_VREG(HEVC_PARSER_VERSION); + if (data32 != 0x5a5a55aa) { + print_scratch_error(26); + return; + } +#if 0 + /* test Parser Reset */ + /* reset iqit to start mem init again */ + WRITE_VREG(DOS_SW_RESET3, (1 << 14) | + (1 << 3) /* reset_whole parser */ + ); + WRITE_VREG(DOS_SW_RESET3, 0); /* clear reset_whole parser */ + data32 = READ_VREG(HEVC_PARSER_VERSION); + if (data32 != 0x00010001) + hevc_print(hevc, 0, + "Test Parser Fatal Error\n"); +#endif + /* reset iqit to start mem init again */ + WRITE_VREG(DOS_SW_RESET3, (1 << 14) + ); + CLEAR_VREG_MASK(HEVC_CABAC_CONTROL, 1); + CLEAR_VREG_MASK(HEVC_PARSER_CORE_CONTROL, 1); + +#endif + if (!hevc->m_ins_flag) { + data32 = READ_VREG(HEVC_STREAM_CONTROL); + data32 = data32 | (1 << 0); /* stream_fetch_enable */ + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) + data32 |= (0xf << 25); /*arwlen_axi_max*/ + WRITE_VREG(HEVC_STREAM_CONTROL, data32); + } + data32 = READ_VREG(HEVC_SHIFT_STARTCODE); + if (data32 != 0x00000100) { + print_scratch_error(29); + return; + } + data32 = READ_VREG(HEVC_SHIFT_EMULATECODE); + if (data32 != 0x00000300) { + print_scratch_error(30); + return; + } + WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678); + WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0); + data32 = READ_VREG(HEVC_SHIFT_STARTCODE); + if (data32 != 0x12345678) { + print_scratch_error(31); + return; + } + data32 = READ_VREG(HEVC_SHIFT_EMULATECODE); + if (data32 != 0x9abcdef0) { + print_scratch_error(32); + return; + } + WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x00000100); + WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300); + + data32 = READ_VREG(HEVC_PARSER_INT_CONTROL); + data32 &= 0x03ffffff; + data32 = data32 | (3 << 29) | (2 << 26) | (1 << 24) + | /* stream_buffer_empty_int_amrisc_enable */ + (1 << 22) | /* stream_fifo_empty_int_amrisc_enable*/ + (1 << 7) | /* dec_done_int_cpu_enable */ + (1 << 4) | /* startcode_found_int_cpu_enable */ + (0 << 3) | /* startcode_found_int_amrisc_enable */ + (1 << 0) /* parser_int_enable */ + ; + WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32); + + data32 = READ_VREG(HEVC_SHIFT_STATUS); + data32 = data32 | (1 << 1) | /* emulation_check_on */ + (1 << 0) /* startcode_check_on */ + ; + WRITE_VREG(HEVC_SHIFT_STATUS, data32); + + WRITE_VREG(HEVC_SHIFT_CONTROL, (3 << 6) |/* sft_valid_wr_position */ + (2 << 4) | /* emulate_code_length_sub_1 */ + (2 << 1) | /* start_code_length_sub_1 */ + (1 << 0) /* stream_shift_enable */ + ); + + WRITE_VREG(HEVC_CABAC_CONTROL, (1 << 0) /* cabac_enable */ + ); + /* hevc_parser_core_clk_en */ + WRITE_VREG(HEVC_PARSER_CORE_CONTROL, (1 << 0) + ); + + WRITE_VREG(HEVC_DEC_STATUS_REG, 0); + + /* Initial IQIT_SCALELUT memory -- just to avoid X in simulation */ + WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0); /* cfg_p_addr */ + for (i = 0; i < 1024; i++) + WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0); + +#ifdef ENABLE_SWAP_TEST + WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100); +#endif + + /*WRITE_VREG(HEVC_DECODE_PIC_BEGIN_REG, 0);*/ + /*WRITE_VREG(HEVC_DECODE_PIC_NUM_REG, 0xffffffff);*/ + WRITE_VREG(HEVC_DECODE_SIZE, 0); + /*WRITE_VREG(HEVC_DECODE_COUNT, 0);*/ + /* Send parser_cmd */ + WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0)); + + parser_cmd_write(); + + WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0); + WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1); + WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2); + + WRITE_VREG(HEVC_PARSER_IF_CONTROL, + /* (1 << 8) | // sao_sw_pred_enable */ + (1 << 5) | /* parser_sao_if_en */ + (1 << 2) | /* parser_mpred_if_en */ + (1 << 0) /* parser_scaler_if_en */ + ); + + /* Changed to Start MPRED in microcode */ + /* + * hevc_print(hevc, 0, "[test.c] Start MPRED\n"); + * WRITE_VREG(HEVC_MPRED_INT_STATUS, + * (1<<31) + * ); + */ + + WRITE_VREG(HEVCD_IPP_TOP_CNTL, (0 << 1) | /* enable ipp */ + (1 << 0) /* software reset ipp and mpp */ + ); + WRITE_VREG(HEVCD_IPP_TOP_CNTL, (1 << 1) | /* enable ipp */ + (0 << 0) /* software reset ipp and mpp */ + ); + + if (get_double_write_mode(hevc) & 0x10) + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, + 0x1 << 31 /*/Enable NV21 reference read mode for MC*/ + ); + +} + +static void decoder_hw_reset(void) +{ + int i; + unsigned int data32; + /* reset iqit to start mem init again */ + WRITE_VREG(DOS_SW_RESET3, (1 << 14) + ); + CLEAR_VREG_MASK(HEVC_CABAC_CONTROL, 1); + CLEAR_VREG_MASK(HEVC_PARSER_CORE_CONTROL, 1); + + data32 = READ_VREG(HEVC_STREAM_CONTROL); + data32 = data32 | (1 << 0) /* stream_fetch_enable */ + ; + WRITE_VREG(HEVC_STREAM_CONTROL, data32); + + data32 = READ_VREG(HEVC_SHIFT_STARTCODE); + if (data32 != 0x00000100) { + print_scratch_error(29); + return; + } + data32 = READ_VREG(HEVC_SHIFT_EMULATECODE); + if (data32 != 0x00000300) { + print_scratch_error(30); + return; + } + WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678); + WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0); + data32 = READ_VREG(HEVC_SHIFT_STARTCODE); + if (data32 != 0x12345678) { + print_scratch_error(31); + return; + } + data32 = READ_VREG(HEVC_SHIFT_EMULATECODE); + if (data32 != 0x9abcdef0) { + print_scratch_error(32); + return; + } + WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x00000100); + WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300); + + data32 = READ_VREG(HEVC_PARSER_INT_CONTROL); + data32 &= 0x03ffffff; + data32 = data32 | (3 << 29) | (2 << 26) | (1 << 24) + | /* stream_buffer_empty_int_amrisc_enable */ + (1 << 22) | /*stream_fifo_empty_int_amrisc_enable */ + (1 << 7) | /* dec_done_int_cpu_enable */ + (1 << 4) | /* startcode_found_int_cpu_enable */ + (0 << 3) | /* startcode_found_int_amrisc_enable */ + (1 << 0) /* parser_int_enable */ + ; + WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32); + + data32 = READ_VREG(HEVC_SHIFT_STATUS); + data32 = data32 | (1 << 1) | /* emulation_check_on */ + (1 << 0) /* startcode_check_on */ + ; + WRITE_VREG(HEVC_SHIFT_STATUS, data32); + + WRITE_VREG(HEVC_SHIFT_CONTROL, (3 << 6) |/* sft_valid_wr_position */ + (2 << 4) | /* emulate_code_length_sub_1 */ + (2 << 1) | /* start_code_length_sub_1 */ + (1 << 0) /* stream_shift_enable */ + ); + + WRITE_VREG(HEVC_CABAC_CONTROL, (1 << 0) /* cabac_enable */ + ); + /* hevc_parser_core_clk_en */ + WRITE_VREG(HEVC_PARSER_CORE_CONTROL, (1 << 0) + ); + + /* Initial IQIT_SCALELUT memory -- just to avoid X in simulation */ + WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0); /* cfg_p_addr */ + for (i = 0; i < 1024; i++) + WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0); + + /* Send parser_cmd */ + WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0)); + + parser_cmd_write(); + + WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0); + WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1); + WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2); + + WRITE_VREG(HEVC_PARSER_IF_CONTROL, + /* (1 << 8) | // sao_sw_pred_enable */ + (1 << 5) | /* parser_sao_if_en */ + (1 << 2) | /* parser_mpred_if_en */ + (1 << 0) /* parser_scaler_if_en */ + ); + + WRITE_VREG(HEVCD_IPP_TOP_CNTL, (0 << 1) | /* enable ipp */ + (1 << 0) /* software reset ipp and mpp */ + ); + WRITE_VREG(HEVCD_IPP_TOP_CNTL, (1 << 1) | /* enable ipp */ + (0 << 0) /* software reset ipp and mpp */ + ); +} + +#ifdef CONFIG_HEVC_CLK_FORCED_ON +static void config_hevc_clk_forced_on(void) +{ + unsigned int rdata32; + /* IQIT */ + rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL); + WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2)); + + /* DBLK */ + rdata32 = READ_VREG(HEVC_DBLK_CFG0); + WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2)); + + /* SAO */ + rdata32 = READ_VREG(HEVC_SAO_CTRL1); + WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2)); + + /* MPRED */ + rdata32 = READ_VREG(HEVC_MPRED_CTRL1); + WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24)); + + /* PARSER */ + rdata32 = READ_VREG(HEVC_STREAM_CONTROL); + WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15)); + rdata32 = READ_VREG(HEVC_SHIFT_CONTROL); + WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15)); + rdata32 = READ_VREG(HEVC_CABAC_CONTROL); + WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13)); + rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL); + WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15)); + rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL); + WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15)); + rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL); + WRITE_VREG(HEVC_PARSER_IF_CONTROL, + rdata32 | (0x3 << 5) | (0x3 << 2) | (0x3 << 0)); + + /* IPP */ + rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG); + WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff); + + /* MCRCC */ + rdata32 = READ_VREG(HEVCD_MCRCC_CTL1); + WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3)); +} +#endif + +#ifdef MCRCC_ENABLE +static void config_mcrcc_axi_hw(struct hevc_state_s *hevc, int slice_type) +{ + unsigned int rdata32; + unsigned int rdata32_2; + int l0_cnt = 0; + int l1_cnt = 0x7fff; + + if (get_double_write_mode(hevc) & 0x10) { + l0_cnt = hevc->cur_pic->RefNum_L0; + l1_cnt = hevc->cur_pic->RefNum_L1; + } + + WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc */ + + if (slice_type == 2) { /* I-PIC */ + /* remove reset -- disables clock */ + WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0); + return; + } + + if (slice_type == 0) { /* B-PIC */ + /* Programme canvas0 */ + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (0 << 8) | (0 << 1) | 0); + rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32 = rdata32 & 0xffff; + rdata32 = rdata32 | (rdata32 << 16); + WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32); + + /* Programme canvas1 */ + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (16 << 8) | (1 << 1) | 0); + rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32_2 = rdata32_2 & 0xffff; + rdata32_2 = rdata32_2 | (rdata32_2 << 16); + if (rdata32 == rdata32_2 && l1_cnt > 1) { + rdata32_2 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32_2 = rdata32_2 & 0xffff; + rdata32_2 = rdata32_2 | (rdata32_2 << 16); + } + WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32_2); + } else { /* P-PIC */ + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (0 << 8) | (1 << 1) | 0); + rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32 = rdata32 & 0xffff; + rdata32 = rdata32 | (rdata32 << 16); + WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32); + + if (l0_cnt == 1) { + WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32); + } else { + /* Programme canvas1 */ + rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32 = rdata32 & 0xffff; + rdata32 = rdata32 | (rdata32 << 16); + WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32); + } + } + /* enable mcrcc progressive-mode */ + WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); +} +#endif + +static void config_title_hw(struct hevc_state_s *hevc, int sao_vb_size, + int sao_mem_unit) +{ + WRITE_VREG(HEVC_sao_mem_unit, sao_mem_unit); + WRITE_VREG(HEVC_SAO_ABV, hevc->work_space_buf->sao_abv.buf_start); + WRITE_VREG(HEVC_sao_vb_size, sao_vb_size); + WRITE_VREG(HEVC_SAO_VB, hevc->work_space_buf->sao_vb.buf_start); +} + +static void config_aux_buf(struct hevc_state_s *hevc) +{ + WRITE_VREG(HEVC_AUX_ADR, hevc->aux_phy_addr); + WRITE_VREG(HEVC_AUX_DATA_SIZE, + ((hevc->prefix_aux_size >> 4) << 16) | + (hevc->suffix_aux_size >> 4) + ); +} + +static void config_mpred_hw(struct hevc_state_s *hevc) +{ + int i; + unsigned int data32; + struct PIC_s *cur_pic = hevc->cur_pic; + struct PIC_s *col_pic = hevc->col_pic; + int AMVP_MAX_NUM_CANDS_MEM = 3; + int AMVP_MAX_NUM_CANDS = 2; + int NUM_CHROMA_MODE = 5; + int DM_CHROMA_IDX = 36; + int above_ptr_ctrl = 0; + int buffer_linear = 1; + int cu_size_log2 = 3; + + int mpred_mv_rd_start_addr; + int mpred_curr_lcu_x; + int mpred_curr_lcu_y; + int mpred_above_buf_start; + int mpred_mv_rd_ptr; + int mpred_mv_rd_ptr_p1; + int mpred_mv_rd_end_addr; + int MV_MEM_UNIT; + int mpred_mv_wr_ptr; + int *ref_poc_L0, *ref_poc_L1; + + int above_en; + int mv_wr_en; + int mv_rd_en; + int col_isIntra; + + if (hevc->slice_type != 2) { + above_en = 1; + mv_wr_en = 1; + mv_rd_en = 1; + col_isIntra = 0; + } else { + above_en = 1; + mv_wr_en = 1; + mv_rd_en = 0; + col_isIntra = 0; + } + + mpred_mv_rd_start_addr = col_pic->mpred_mv_wr_start_addr; + data32 = READ_VREG(HEVC_MPRED_CURR_LCU); + mpred_curr_lcu_x = data32 & 0xffff; + mpred_curr_lcu_y = (data32 >> 16) & 0xffff; + + MV_MEM_UNIT = + hevc->lcu_size_log2 == 6 ? 0x200 : hevc->lcu_size_log2 == + 5 ? 0x80 : 0x20; + mpred_mv_rd_ptr = + mpred_mv_rd_start_addr + (hevc->slice_addr * MV_MEM_UNIT); + + mpred_mv_rd_ptr_p1 = mpred_mv_rd_ptr + MV_MEM_UNIT; + mpred_mv_rd_end_addr = + mpred_mv_rd_start_addr + + ((hevc->lcu_x_num * hevc->lcu_y_num) * MV_MEM_UNIT); + + mpred_above_buf_start = hevc->work_space_buf->mpred_above.buf_start; + + mpred_mv_wr_ptr = + cur_pic->mpred_mv_wr_start_addr + + (hevc->slice_addr * MV_MEM_UNIT); + + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "cur pic index %d col pic index %d\n", cur_pic->index, + col_pic->index); + } + + WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR, + cur_pic->mpred_mv_wr_start_addr); + WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR, mpred_mv_rd_start_addr); + + data32 = ((hevc->lcu_x_num - hevc->tile_width_lcu) * MV_MEM_UNIT); + WRITE_VREG(HEVC_MPRED_MV_WR_ROW_JUMP, data32); + WRITE_VREG(HEVC_MPRED_MV_RD_ROW_JUMP, data32); + + data32 = READ_VREG(HEVC_MPRED_CTRL0); + data32 = (hevc->slice_type | + hevc->new_pic << 2 | + hevc->new_tile << 3 | + hevc->isNextSliceSegment << 4 | + hevc->TMVPFlag << 5 | + hevc->LDCFlag << 6 | + hevc->ColFromL0Flag << 7 | + above_ptr_ctrl << 8 | + above_en << 9 | + mv_wr_en << 10 | + mv_rd_en << 11 | + col_isIntra << 12 | + buffer_linear << 13 | + hevc->LongTerm_Curr << 14 | + hevc->LongTerm_Col << 15 | + hevc->lcu_size_log2 << 16 | + cu_size_log2 << 20 | hevc->plevel << 24); + WRITE_VREG(HEVC_MPRED_CTRL0, data32); + + data32 = READ_VREG(HEVC_MPRED_CTRL1); + data32 = ( +#if 0 + /* no set in m8baby test1902 */ + /* Don't override clk_forced_on , */ + (data32 & (0x1 << 24)) | +#endif + hevc->MaxNumMergeCand | + AMVP_MAX_NUM_CANDS << 4 | + AMVP_MAX_NUM_CANDS_MEM << 8 | + NUM_CHROMA_MODE << 12 | DM_CHROMA_IDX << 16); + WRITE_VREG(HEVC_MPRED_CTRL1, data32); + + data32 = (hevc->pic_w | hevc->pic_h << 16); + WRITE_VREG(HEVC_MPRED_PIC_SIZE, data32); + + data32 = ((hevc->lcu_x_num - 1) | (hevc->lcu_y_num - 1) << 16); + WRITE_VREG(HEVC_MPRED_PIC_SIZE_LCU, data32); + + data32 = (hevc->tile_start_lcu_x | hevc->tile_start_lcu_y << 16); + WRITE_VREG(HEVC_MPRED_TILE_START, data32); + + data32 = (hevc->tile_width_lcu | hevc->tile_height_lcu << 16); + WRITE_VREG(HEVC_MPRED_TILE_SIZE_LCU, data32); + + data32 = (hevc->RefNum_L0 | hevc->RefNum_L1 << 8 | 0 + /* col_RefNum_L0<<16| */ + /* col_RefNum_L1<<24 */ + ); + WRITE_VREG(HEVC_MPRED_REF_NUM, data32); + + data32 = (hevc->LongTerm_Ref); + WRITE_VREG(HEVC_MPRED_LT_REF, data32); + + data32 = 0; + for (i = 0; i < hevc->RefNum_L0; i++) + data32 = data32 | (1 << i); + WRITE_VREG(HEVC_MPRED_REF_EN_L0, data32); + + data32 = 0; + for (i = 0; i < hevc->RefNum_L1; i++) + data32 = data32 | (1 << i); + WRITE_VREG(HEVC_MPRED_REF_EN_L1, data32); + + WRITE_VREG(HEVC_MPRED_CUR_POC, hevc->curr_POC); + WRITE_VREG(HEVC_MPRED_COL_POC, hevc->Col_POC); + + /* below MPRED Ref_POC_xx_Lx registers must follow Ref_POC_xx_L0 -> + * Ref_POC_xx_L1 in pair write order!!! + */ + ref_poc_L0 = &(cur_pic->m_aiRefPOCList0[cur_pic->slice_idx][0]); + ref_poc_L1 = &(cur_pic->m_aiRefPOCList1[cur_pic->slice_idx][0]); + + WRITE_VREG(HEVC_MPRED_L0_REF00_POC, ref_poc_L0[0]); + WRITE_VREG(HEVC_MPRED_L1_REF00_POC, ref_poc_L1[0]); + + WRITE_VREG(HEVC_MPRED_L0_REF01_POC, ref_poc_L0[1]); + WRITE_VREG(HEVC_MPRED_L1_REF01_POC, ref_poc_L1[1]); + + WRITE_VREG(HEVC_MPRED_L0_REF02_POC, ref_poc_L0[2]); + WRITE_VREG(HEVC_MPRED_L1_REF02_POC, ref_poc_L1[2]); + + WRITE_VREG(HEVC_MPRED_L0_REF03_POC, ref_poc_L0[3]); + WRITE_VREG(HEVC_MPRED_L1_REF03_POC, ref_poc_L1[3]); + + WRITE_VREG(HEVC_MPRED_L0_REF04_POC, ref_poc_L0[4]); + WRITE_VREG(HEVC_MPRED_L1_REF04_POC, ref_poc_L1[4]); + + WRITE_VREG(HEVC_MPRED_L0_REF05_POC, ref_poc_L0[5]); + WRITE_VREG(HEVC_MPRED_L1_REF05_POC, ref_poc_L1[5]); + + WRITE_VREG(HEVC_MPRED_L0_REF06_POC, ref_poc_L0[6]); + WRITE_VREG(HEVC_MPRED_L1_REF06_POC, ref_poc_L1[6]); + + WRITE_VREG(HEVC_MPRED_L0_REF07_POC, ref_poc_L0[7]); + WRITE_VREG(HEVC_MPRED_L1_REF07_POC, ref_poc_L1[7]); + + WRITE_VREG(HEVC_MPRED_L0_REF08_POC, ref_poc_L0[8]); + WRITE_VREG(HEVC_MPRED_L1_REF08_POC, ref_poc_L1[8]); + + WRITE_VREG(HEVC_MPRED_L0_REF09_POC, ref_poc_L0[9]); + WRITE_VREG(HEVC_MPRED_L1_REF09_POC, ref_poc_L1[9]); + + WRITE_VREG(HEVC_MPRED_L0_REF10_POC, ref_poc_L0[10]); + WRITE_VREG(HEVC_MPRED_L1_REF10_POC, ref_poc_L1[10]); + + WRITE_VREG(HEVC_MPRED_L0_REF11_POC, ref_poc_L0[11]); + WRITE_VREG(HEVC_MPRED_L1_REF11_POC, ref_poc_L1[11]); + + WRITE_VREG(HEVC_MPRED_L0_REF12_POC, ref_poc_L0[12]); + WRITE_VREG(HEVC_MPRED_L1_REF12_POC, ref_poc_L1[12]); + + WRITE_VREG(HEVC_MPRED_L0_REF13_POC, ref_poc_L0[13]); + WRITE_VREG(HEVC_MPRED_L1_REF13_POC, ref_poc_L1[13]); + + WRITE_VREG(HEVC_MPRED_L0_REF14_POC, ref_poc_L0[14]); + WRITE_VREG(HEVC_MPRED_L1_REF14_POC, ref_poc_L1[14]); + + WRITE_VREG(HEVC_MPRED_L0_REF15_POC, ref_poc_L0[15]); + WRITE_VREG(HEVC_MPRED_L1_REF15_POC, ref_poc_L1[15]); + + if (hevc->new_pic) { + WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, mpred_above_buf_start); + WRITE_VREG(HEVC_MPRED_MV_WPTR, mpred_mv_wr_ptr); + /* WRITE_VREG(HEVC_MPRED_MV_RPTR,mpred_mv_rd_ptr); */ + WRITE_VREG(HEVC_MPRED_MV_RPTR, mpred_mv_rd_start_addr); + } else if (!hevc->isNextSliceSegment) { + /* WRITE_VREG(HEVC_MPRED_MV_RPTR,mpred_mv_rd_ptr_p1); */ + WRITE_VREG(HEVC_MPRED_MV_RPTR, mpred_mv_rd_ptr); + } + + WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, mpred_mv_rd_end_addr); +} + +static void config_sao_hw(struct hevc_state_s *hevc, union param_u *params) +{ + unsigned int data32, data32_2; + int misc_flag0 = hevc->misc_flag0; + int slice_deblocking_filter_disabled_flag = 0; + + int mc_buffer_size_u_v = + hevc->lcu_total * hevc->lcu_size * hevc->lcu_size / 2; + int mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16; + struct PIC_s *cur_pic = hevc->cur_pic; + + data32 = READ_VREG(HEVC_SAO_CTRL0); + data32 &= (~0xf); + data32 |= hevc->lcu_size_log2; + WRITE_VREG(HEVC_SAO_CTRL0, data32); + + data32 = (hevc->pic_w | hevc->pic_h << 16); + WRITE_VREG(HEVC_SAO_PIC_SIZE, data32); + + data32 = ((hevc->lcu_x_num - 1) | (hevc->lcu_y_num - 1) << 16); + WRITE_VREG(HEVC_SAO_PIC_SIZE_LCU, data32); + + if (hevc->new_pic) + WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff); +#ifdef LOSLESS_COMPRESS_MODE +/*SUPPORT_10BIT*/ + if ((get_double_write_mode(hevc) & 0x10) == 0) { + data32 = READ_VREG(HEVC_SAO_CTRL5); + data32 &= (~(0xff << 16)); + + if (get_double_write_mode(hevc) == 2 || + get_double_write_mode(hevc) == 3) + data32 |= (0xff<<16); + else if (get_double_write_mode(hevc) == 4) + data32 |= (0x33<<16); + + if (hevc->mem_saving_mode == 1) + data32 |= (1 << 9); + else + data32 &= ~(1 << 9); + if (workaround_enable & 1) + data32 |= (1 << 7); + WRITE_VREG(HEVC_SAO_CTRL5, data32); + } + data32 = cur_pic->mc_y_adr; + if (get_double_write_mode(hevc)) + WRITE_VREG(HEVC_SAO_Y_START_ADDR, cur_pic->dw_y_adr); + + if ((get_double_write_mode(hevc) & 0x10) == 0) + WRITE_VREG(HEVC_CM_BODY_START_ADDR, data32); + + if (hevc->mmu_enable) + WRITE_VREG(HEVC_CM_HEADER_START_ADDR, cur_pic->header_adr); +#else + data32 = cur_pic->mc_y_adr; + WRITE_VREG(HEVC_SAO_Y_START_ADDR, data32); +#endif + data32 = (mc_buffer_size_u_v_h << 16) << 1; + WRITE_VREG(HEVC_SAO_Y_LENGTH, data32); + +#ifdef LOSLESS_COMPRESS_MODE +/*SUPPORT_10BIT*/ + if (get_double_write_mode(hevc)) + WRITE_VREG(HEVC_SAO_C_START_ADDR, cur_pic->dw_u_v_adr); +#else + data32 = cur_pic->mc_u_v_adr; + WRITE_VREG(HEVC_SAO_C_START_ADDR, data32); +#endif + data32 = (mc_buffer_size_u_v_h << 16); + WRITE_VREG(HEVC_SAO_C_LENGTH, data32); + +#ifdef LOSLESS_COMPRESS_MODE +/*SUPPORT_10BIT*/ + if (get_double_write_mode(hevc)) { + WRITE_VREG(HEVC_SAO_Y_WPTR, cur_pic->dw_y_adr); + WRITE_VREG(HEVC_SAO_C_WPTR, cur_pic->dw_u_v_adr); + } +#else + /* multi tile to do... */ + data32 = cur_pic->mc_y_adr; + WRITE_VREG(HEVC_SAO_Y_WPTR, data32); + + data32 = cur_pic->mc_u_v_adr; + WRITE_VREG(HEVC_SAO_C_WPTR, data32); +#endif + /* DBLK CONFIG HERE */ + if (hevc->new_pic) { + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) { + data32 = (0x57 << 8) | /* 1st/2nd write both enable*/ + (0x0 << 0); /* h265 video format*/ + if (hevc->pic_w >= 1280) + data32 |= (0x1 << 4); /*dblk pipeline mode=1 for performance*/ + data32 &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/ + if (get_double_write_mode(hevc) == 0) + data32 |= (0x1 << 8); /*enable first write*/ + else if (get_double_write_mode(hevc) == 0x10) + data32 |= (0x1 << 9); /*double write only*/ + else + data32 |= ((0x1 << 8) |(0x1 << 9)); + + WRITE_VREG(HEVC_DBLK_CFGB, data32); + hevc_print(hevc, H265_DEBUG_BUFMGR_MORE, + "[DBLK DEBUG] HEVC1 CFGB : 0x%x\n", data32); + } + + data32 = (hevc->pic_w | hevc->pic_h << 16); + WRITE_VREG(HEVC_DBLK_CFG2, data32); + + if ((misc_flag0 >> PCM_ENABLE_FLAG_BIT) & 0x1) { + data32 = + ((misc_flag0 >> + PCM_LOOP_FILTER_DISABLED_FLAG_BIT) & + 0x1) << 3; + } else + data32 = 0; + data32 |= + (((params->p.pps_cb_qp_offset & 0x1f) << 4) | + ((params->p.pps_cr_qp_offset + & 0x1f) << + 9)); + data32 |= + (hevc->lcu_size == + 64) ? 0 : ((hevc->lcu_size == 32) ? 1 : 2); + + WRITE_VREG(HEVC_DBLK_CFG1, data32); + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) { + /*if (debug & 0x80) {*/ + data32 = 1 << 28; /* Debug only: sts1 chooses dblk_main*/ + WRITE_VREG(HEVC_DBLK_STS1 + 4, data32); /* 0x3510 */ + hevc_print(hevc, H265_DEBUG_BUFMGR_MORE, + "[DBLK DEBUG] HEVC1 STS1 : 0x%x\n", + data32); + /*}*/ + } + } +#if 0 + data32 = READ_VREG(HEVC_SAO_CTRL1); + data32 &= (~0x3000); + data32 |= (mem_map_mode << + 12); + +/* [13:12] axi_aformat, + * 0-Linear, 1-32x32, 2-64x32 + */ + WRITE_VREG(HEVC_SAO_CTRL1, data32); + + data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG); + data32 &= (~0x30); + data32 |= (mem_map_mode << + 4); + +/* [5:4] -- address_format + * 00:linear 01:32x32 10:64x32 + */ + WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32); +#else + /* m8baby test1902 */ + data32 = READ_VREG(HEVC_SAO_CTRL1); + data32 &= (~0x3000); + data32 |= (mem_map_mode << + 12); + +/* [13:12] axi_aformat, 0-Linear, + * 1-32x32, 2-64x32 + */ + data32 &= (~0xff0); + /* data32 |= 0x670; // Big-Endian per 64-bit */ + data32 |= endian; /* Big-Endian per 64-bit */ + if (get_cpu_type() < MESON_CPU_MAJOR_ID_G12A) { + data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/ + if (get_double_write_mode(hevc) == 0) + data32 |= 0x2; /*disable double write*/ + else if (!hevc->mmu_enable && (get_double_write_mode(hevc) & 0x10)) + data32 |= 0x1; /*disable cm*/ + } + WRITE_VREG(HEVC_SAO_CTRL1, data32); + + if (get_double_write_mode(hevc) & 0x10) { + /* [23:22] dw_v1_ctrl + *[21:20] dw_v0_ctrl + *[19:18] dw_h1_ctrl + *[17:16] dw_h0_ctrl + */ + data32 = READ_VREG(HEVC_SAO_CTRL5); + /*set them all 0 for H265_NV21 (no down-scale)*/ + data32 &= ~(0xff << 16); + WRITE_VREG(HEVC_SAO_CTRL5, data32); + } + + data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG); + data32 &= (~0x30); + /* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */ + data32 |= (mem_map_mode << + 4); + data32 &= (~0xF); + data32 |= 0xf; /* valid only when double write only */ + /*data32 |= 0x8;*/ /* Big-Endian per 64-bit */ + WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32); +#endif + data32 = 0; + data32_2 = READ_VREG(HEVC_SAO_CTRL0); + data32_2 &= (~0x300); + /* slice_deblocking_filter_disabled_flag = 0; + * ucode has handle it , so read it from ucode directly + */ + if (hevc->tile_enabled) { + data32 |= + ((misc_flag0 >> + LOOP_FILER_ACROSS_TILES_ENABLED_FLAG_BIT) & + 0x1) << 0; + data32_2 |= + ((misc_flag0 >> + LOOP_FILER_ACROSS_TILES_ENABLED_FLAG_BIT) & + 0x1) << 8; + } + slice_deblocking_filter_disabled_flag = (misc_flag0 >> + SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) & + 0x1; /* ucode has handle it,so read it from ucode directly */ + if ((misc_flag0 & (1 << DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_BIT)) + && (misc_flag0 & (1 << DEBLOCKING_FILTER_OVERRIDE_FLAG_BIT))) { + /* slice_deblocking_filter_disabled_flag = + * (misc_flag0>>SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT)&0x1; + * //ucode has handle it , so read it from ucode directly + */ + data32 |= slice_deblocking_filter_disabled_flag << 2; + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + hevc_print_cont(hevc, 0, + "(1,%x)", data32); + if (!slice_deblocking_filter_disabled_flag) { + data32 |= (params->p.slice_beta_offset_div2 & 0xf) << 3; + data32 |= (params->p.slice_tc_offset_div2 & 0xf) << 7; + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + hevc_print_cont(hevc, 0, + "(2,%x)", data32); + } + } else { + data32 |= + ((misc_flag0 >> + PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) & + 0x1) << 2; + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + hevc_print_cont(hevc, 0, + "(3,%x)", data32); + if (((misc_flag0 >> PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) & + 0x1) == 0) { + data32 |= (params->p.pps_beta_offset_div2 & 0xf) << 3; + data32 |= (params->p.pps_tc_offset_div2 & 0xf) << 7; + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + hevc_print_cont(hevc, 0, + "(4,%x)", data32); + } + } + if ((misc_flag0 & (1 << PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)) + && ((misc_flag0 & (1 << SLICE_SAO_LUMA_FLAG_BIT)) + || (misc_flag0 & (1 << SLICE_SAO_CHROMA_FLAG_BIT)) + || (!slice_deblocking_filter_disabled_flag))) { + data32 |= + ((misc_flag0 >> + SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT) + & 0x1) << 1; + data32_2 |= + ((misc_flag0 >> + SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT) + & 0x1) << 9; + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + hevc_print_cont(hevc, 0, + "(5,%x)\n", data32); + } else { + data32 |= + ((misc_flag0 >> + PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT) + & 0x1) << 1; + data32_2 |= + ((misc_flag0 >> + PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT) + & 0x1) << 9; + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + hevc_print_cont(hevc, 0, + "(6,%x)\n", data32); + } + WRITE_VREG(HEVC_DBLK_CFG9, data32); + WRITE_VREG(HEVC_SAO_CTRL0, data32_2); +} + +#ifdef TEST_NO_BUF +static unsigned char test_flag = 1; +#endif + +static void pic_list_process(struct hevc_state_s *hevc) +{ + int work_pic_num = get_work_pic_num(hevc); + int alloc_pic_count = 0; + int i; + struct PIC_s *pic; + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + pic = hevc->m_PIC[i]; + if (pic == NULL || pic->index == -1) + continue; + alloc_pic_count++; + if (pic->output_mark == 0 && pic->referenced == 0 + && pic->output_ready == 0 + && (pic->width != hevc->pic_w || + pic->height != hevc->pic_h) + ) { + set_buf_unused(hevc, pic->BUF_index); + pic->BUF_index = -1; + if (alloc_pic_count > work_pic_num) { + pic->width = 0; + pic->height = 0; + pic->index = -1; + } else { + pic->width = hevc->pic_w; + pic->height = hevc->pic_h; + } + } + } + if (alloc_pic_count < work_pic_num) { + int new_count = alloc_pic_count; + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + pic = hevc->m_PIC[i]; + if (pic && pic->index == -1) { + pic->index = i; + pic->BUF_index = -1; + pic->width = hevc->pic_w; + pic->height = hevc->pic_h; + new_count++; + if (new_count >= + work_pic_num) + break; + } + } + + } + dealloc_unused_buf(hevc); + if (get_alloc_pic_count(hevc) + != alloc_pic_count) { + hevc_print_cont(hevc, 0, + "%s: work_pic_num is %d, Change alloc_pic_count from %d to %d\n", + __func__, + work_pic_num, + alloc_pic_count, + get_alloc_pic_count(hevc)); + } +} + +static void recycle_mmu_bufs(struct hevc_state_s *hevc) +{ + int i; + struct PIC_s *pic; + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + pic = hevc->m_PIC[i]; + if (pic == NULL || pic->index == -1) + continue; + + if (pic->output_mark == 0 && pic->referenced == 0 + && pic->output_ready == 0 + && pic->scatter_alloc + ) + release_pic_mmu_buf(hevc, pic); + } + +} + +static struct PIC_s *get_new_pic(struct hevc_state_s *hevc, + union param_u *rpm_param) +{ + struct PIC_s *new_pic = NULL; + struct PIC_s *pic; + int i; + int ret; + + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + pic = hevc->m_PIC[i]; + if (pic == NULL || pic->index == -1) + continue; + + if (pic->output_mark == 0 && pic->referenced == 0 + && pic->output_ready == 0 + && pic->width == hevc->pic_w + && pic->height == hevc->pic_h + ) { + if (new_pic) { + if (new_pic->POC != INVALID_POC) { + if (pic->POC == INVALID_POC || + pic->POC < new_pic->POC) + new_pic = pic; + } + } else + new_pic = pic; + } + } + + if (new_pic == NULL) + return NULL; + + if (new_pic->BUF_index < 0) { + if (alloc_buf(hevc) < 0) + return NULL; + else { + if (config_pic(hevc, new_pic) < 0) { + dealloc_pic_buf(hevc, new_pic); + return NULL; + } + } + new_pic->width = hevc->pic_w; + new_pic->height = hevc->pic_h; + set_canvas(hevc, new_pic); + + init_pic_list_hw(hevc); + } + + if (new_pic) { + new_pic->double_write_mode = + get_double_write_mode(hevc); + if (new_pic->double_write_mode) + set_canvas(hevc, new_pic); + +#ifdef TEST_NO_BUF + if (test_flag) { + test_flag = 0; + return NULL; + } else + test_flag = 1; +#endif + if (get_mv_buf(hevc, new_pic) < 0) + return NULL; + + if (hevc->mmu_enable) { + ret = H265_alloc_mmu(hevc, new_pic, + rpm_param->p.bit_depth, + hevc->frame_mmu_map_addr); + if (ret != 0) { + hevc_print(hevc, 0, + "can't alloc need mmu1,idx %d ret =%d\n", + new_pic->decode_idx, + ret); + return NULL; + } + } + new_pic->referenced = 1; + new_pic->decode_idx = hevc->decode_idx; + new_pic->slice_idx = 0; + new_pic->referenced = 1; + new_pic->output_mark = 0; + new_pic->recon_mark = 0; + new_pic->error_mark = 0; + /* new_pic->output_ready = 0; */ + new_pic->num_reorder_pic = rpm_param->p.sps_num_reorder_pics_0; + new_pic->losless_comp_body_size = hevc->losless_comp_body_size; + new_pic->POC = hevc->curr_POC; + new_pic->pic_struct = hevc->curr_pic_struct; + if (new_pic->aux_data_buf) + release_aux_data(hevc, new_pic); + new_pic->mem_saving_mode = + hevc->mem_saving_mode; + new_pic->bit_depth_luma = + hevc->bit_depth_luma; + new_pic->bit_depth_chroma = + hevc->bit_depth_chroma; + + hevc_print(hevc, H265_DEBUG_BUFMGR_MORE, + "%s: index %d, buf_idx %d, decode_idx %d, POC %d\n", + __func__, new_pic->index, + new_pic->BUF_index, new_pic->decode_idx, + new_pic->POC); + + } + + return new_pic; +} + +static int get_display_pic_num(struct hevc_state_s *hevc) +{ + int i; + struct PIC_s *pic; + int num = 0; + + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + pic = hevc->m_PIC[i]; + if (pic == NULL || + pic->index == -1) + continue; + + if (pic->output_ready == 1) + num++; + } + return num; +} + +static void flush_output(struct hevc_state_s *hevc, struct PIC_s *pic) +{ + struct PIC_s *pic_display; + + if (pic) { + /*PB skip control */ + if (pic->error_mark == 0 && hevc->PB_skip_mode == 1) { + /* start decoding after first I */ + hevc->ignore_bufmgr_error |= 0x1; + } + if (hevc->ignore_bufmgr_error & 1) { + if (hevc->PB_skip_count_after_decoding > 0) + hevc->PB_skip_count_after_decoding--; + else { + /* start displaying */ + hevc->ignore_bufmgr_error |= 0x2; + } + } + /**/ + if (pic->POC != INVALID_POC) { + pic->output_mark = 1; + pic->recon_mark = 1; + } + pic->recon_mark = 1; + } + do { + pic_display = output_pic(hevc, 1); + + if (pic_display) { + pic_display->referenced = 0; + put_mv_buf(hevc, pic_display); + if ((pic_display->error_mark + && ((hevc->ignore_bufmgr_error & 0x2) == 0)) + || (get_dbg_flag(hevc) & + H265_DEBUG_DISPLAY_CUR_FRAME) + || (get_dbg_flag(hevc) & + H265_DEBUG_NO_DISPLAY)) { + pic_display->output_ready = 0; + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "[BM] Display: POC %d, ", + pic_display->POC); + hevc_print_cont(hevc, 0, + "decoding index %d ==> ", + pic_display->decode_idx); + hevc_print_cont(hevc, 0, + "Debug mode or error, recycle it\n"); + } + } else { + if (hevc->i_only & 0x1 + && pic_display->slice_type != 2) { + pic_display->output_ready = 0; + } else { + prepare_display_buf(hevc, pic_display); + if (get_dbg_flag(hevc) + & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "[BM] flush Display: POC %d, ", + pic_display->POC); + hevc_print_cont(hevc, 0, + "decoding index %d\n", + pic_display->decode_idx); + } + } + } + } + } while (pic_display); + clear_referenced_flag(hevc); +} + +/* +* dv_meta_flag: 1, dolby meta only; 2, not include dolby meta +*/ +static void set_aux_data(struct hevc_state_s *hevc, + struct PIC_s *pic, unsigned char suffix_flag, + unsigned char dv_meta_flag) +{ + int i; + unsigned short *aux_adr; + unsigned int size_reg_val = + READ_VREG(HEVC_AUX_DATA_SIZE); + unsigned int aux_count = 0; + int aux_size = 0; + if (pic == NULL) + return; + if (suffix_flag) { + aux_adr = (unsigned short *) + (hevc->aux_addr + + hevc->prefix_aux_size); + aux_count = + ((size_reg_val & 0xffff) << 4) + >> 1; + aux_size = + hevc->suffix_aux_size; + } else { + aux_adr = + (unsigned short *)hevc->aux_addr; + aux_count = + ((size_reg_val >> 16) << 4) + >> 1; + aux_size = + hevc->prefix_aux_size; + } + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR_MORE) { + hevc_print(hevc, 0, + "%s:old size %d count %d,suf %d dv_flag %d\r\n", + __func__, pic->aux_data_size, + aux_count, suffix_flag, dv_meta_flag); + } + if (aux_size > 0 && aux_count > 0) { + int heads_size = 0; + int new_size; + char *new_buf; + + for (i = 0; i < aux_count; i++) { + unsigned char tag = aux_adr[i] >> 8; + if (tag != 0 && tag != 0xff) { + if (dv_meta_flag == 0) + heads_size += 8; + else if (dv_meta_flag == 1 && tag == 0x1) + heads_size += 8; + else if (dv_meta_flag == 2 && tag != 0x1) + heads_size += 8; + } + } + new_size = pic->aux_data_size + aux_count + heads_size; + new_buf = vmalloc(new_size); + if (new_buf) { + unsigned char valid_tag = 0; + unsigned char *h = + new_buf + + pic->aux_data_size; + unsigned char *p = h + 8; + int len = 0; + int padding_len = 0; + memcpy(new_buf, pic->aux_data_buf, pic->aux_data_size); + if (pic->aux_data_buf) + vfree(pic->aux_data_buf); + pic->aux_data_buf = new_buf; + for (i = 0; i < aux_count; i += 4) { + int ii; + unsigned char tag = aux_adr[i + 3] >> 8; + if (tag != 0 && tag != 0xff) { + if (dv_meta_flag == 0) + valid_tag = 1; + else if (dv_meta_flag == 1 + && tag == 0x1) + valid_tag = 1; + else if (dv_meta_flag == 2 + && tag != 0x1) + valid_tag = 1; + else + valid_tag = 0; + if (valid_tag && len > 0) { + pic->aux_data_size += + (len + 8); + h[0] = (len >> 24) + & 0xff; + h[1] = (len >> 16) + & 0xff; + h[2] = (len >> 8) + & 0xff; + h[3] = (len >> 0) + & 0xff; + h[6] = + (padding_len >> 8) + & 0xff; + h[7] = (padding_len) + & 0xff; + h += (len + 8); + p += 8; + len = 0; + padding_len = 0; + } + if (valid_tag) { + h[4] = tag; + h[5] = 0; + h[6] = 0; + h[7] = 0; + } + } + if (valid_tag) { + for (ii = 0; ii < 4; ii++) { + unsigned short aa = + aux_adr[i + 3 + - ii]; + *p = aa & 0xff; + p++; + len++; + /*if ((aa >> 8) == 0xff) + padding_len++;*/ + } + } + } + if (len > 0) { + pic->aux_data_size += (len + 8); + h[0] = (len >> 24) & 0xff; + h[1] = (len >> 16) & 0xff; + h[2] = (len >> 8) & 0xff; + h[3] = (len >> 0) & 0xff; + h[6] = (padding_len >> 8) & 0xff; + h[7] = (padding_len) & 0xff; + } + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR_MORE) { + hevc_print(hevc, 0, + "aux: (size %d) suffix_flag %d\n", + pic->aux_data_size, suffix_flag); + for (i = 0; i < pic->aux_data_size; i++) { + hevc_print_cont(hevc, 0, + "%02x ", pic->aux_data_buf[i]); + if (((i + 1) & 0xf) == 0) + hevc_print_cont(hevc, 0, "\n"); + } + hevc_print_cont(hevc, 0, "\n"); + } + + } else { + hevc_print(hevc, 0, "new buf alloc failed\n"); + if (pic->aux_data_buf) + vfree(pic->aux_data_buf); + pic->aux_data_buf = NULL; + pic->aux_data_size = 0; + } + } + +} + +static void release_aux_data(struct hevc_state_s *hevc, + struct PIC_s *pic) +{ + if (pic->aux_data_buf) + vfree(pic->aux_data_buf); + pic->aux_data_buf = NULL; + pic->aux_data_size = 0; +} + +static inline void hevc_pre_pic(struct hevc_state_s *hevc, + struct PIC_s *pic) +{ + + /* prev pic */ + /*if (hevc->curr_POC != 0) {*/ + int decoded_poc = hevc->iPrevPOC; +#ifdef MULTI_INSTANCE_SUPPORT + if (hevc->m_ins_flag) { + decoded_poc = hevc->decoded_poc; + hevc->decoded_poc = INVALID_POC; + } +#endif + if (hevc->m_nalUnitType != NAL_UNIT_CODED_SLICE_IDR + && hevc->m_nalUnitType != + NAL_UNIT_CODED_SLICE_IDR_N_LP) { + struct PIC_s *pic_display; + + pic = get_pic_by_POC(hevc, decoded_poc); + if (pic && (pic->POC != INVALID_POC)) { + /*PB skip control */ + if (pic->error_mark == 0 + && hevc->PB_skip_mode == 1) { + /* start decoding after + * first I + */ + hevc->ignore_bufmgr_error |= 0x1; + } + if (hevc->ignore_bufmgr_error & 1) { + if (hevc->PB_skip_count_after_decoding > 0) { + hevc->PB_skip_count_after_decoding--; + } else { + /* start displaying */ + hevc->ignore_bufmgr_error |= 0x2; + } + } + if (hevc->mmu_enable) { + if (!hevc->m_ins_flag) { + hevc->used_4k_num = + READ_VREG(HEVC_SAO_MMU_STATUS) >> 16; + + if ((!is_skip_decoding(hevc, pic)) && + (hevc->used_4k_num >= 0) && + (hevc->cur_pic->scatter_alloc + == 1)) { + hevc_print(hevc, + H265_DEBUG_BUFMGR_MORE, + "%s pic index %d scatter_alloc %d page_start %d\n", + "decoder_mmu_box_free_idx_tail", + hevc->cur_pic->index, + hevc->cur_pic->scatter_alloc, + hevc->used_4k_num); + decoder_mmu_box_free_idx_tail( + hevc->mmu_box, + hevc->cur_pic->index, + hevc->used_4k_num); + hevc->cur_pic->scatter_alloc + = 2; + } + hevc->used_4k_num = -1; + } + } + + pic->output_mark = 1; + pic->recon_mark = 1; + } + do { + pic_display = output_pic(hevc, 0); + + if (pic_display) { + if ((pic_display->error_mark && + ((hevc->ignore_bufmgr_error & + 0x2) == 0)) + || (get_dbg_flag(hevc) & + H265_DEBUG_DISPLAY_CUR_FRAME) + || (get_dbg_flag(hevc) & + H265_DEBUG_NO_DISPLAY)) { + pic_display->output_ready = 0; + if (get_dbg_flag(hevc) & + H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "[BM] Display: POC %d, ", + pic_display->POC); + hevc_print_cont(hevc, 0, + "decoding index %d ==> ", + pic_display-> + decode_idx); + hevc_print_cont(hevc, 0, + "Debug or err,recycle it\n"); + } + } else { + if (hevc->i_only & 0x1 + && pic_display-> + slice_type != 2) { + pic_display->output_ready = 0; + } else { + prepare_display_buf + (hevc, + pic_display); + if (get_dbg_flag(hevc) & + H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "[BM] Display: POC %d, ", + pic_display->POC); + hevc_print_cont(hevc, 0, + "decoding index %d\n", + pic_display-> + decode_idx); + } + } + } + } + } while (pic_display); + } else { + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "[BM] current pic is IDR, "); + hevc_print(hevc, 0, + "clear referenced flag of all buffers\n"); + } + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + dump_pic_list(hevc); + pic = get_pic_by_POC(hevc, decoded_poc); + flush_output(hevc, pic); + } + +} + +static void check_pic_decoded_error_pre(struct hevc_state_s *hevc, + int decoded_lcu) +{ + int current_lcu_idx = decoded_lcu; + if (decoded_lcu < 0) + return; + + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "cur lcu idx = %d, (total %d)\n", + current_lcu_idx, hevc->lcu_total); + } + if ((error_handle_policy & 0x20) == 0 && hevc->cur_pic != NULL) { + if (hevc->first_pic_after_recover) { + if (current_lcu_idx != + ((hevc->lcu_x_num_pre*hevc->lcu_y_num_pre) - 1)) + hevc->cur_pic->error_mark = 1; + } else { + if (hevc->lcu_x_num_pre != 0 + && hevc->lcu_y_num_pre != 0 + && current_lcu_idx != 0 + && current_lcu_idx < + ((hevc->lcu_x_num_pre*hevc->lcu_y_num_pre) - 1)) + hevc->cur_pic->error_mark = 1; + } + if (hevc->cur_pic->error_mark) { + hevc_print(hevc, 0, + "cur lcu idx = %d, (total %d), set error_mark\n", + current_lcu_idx, + hevc->lcu_x_num_pre*hevc->lcu_y_num_pre); + if (is_log_enable(hevc)) + add_log(hevc, + "cur lcu idx = %d, (total %d), set error_mark", + current_lcu_idx, + hevc->lcu_x_num_pre * + hevc->lcu_y_num_pre); + + } + + } + if (hevc->cur_pic && hevc->head_error_flag) { + hevc->cur_pic->error_mark = 1; + hevc_print(hevc, 0, + "head has error, set error_mark\n"); + } + hevc->lcu_x_num_pre = hevc->lcu_x_num; + hevc->lcu_y_num_pre = hevc->lcu_y_num; +} + +static void check_pic_decoded_error(struct hevc_state_s *hevc, + int decoded_lcu) +{ + int current_lcu_idx = decoded_lcu; + if (decoded_lcu < 0) + return; + + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "cur lcu idx = %d, (total %d)\n", + current_lcu_idx, hevc->lcu_total); + } + if ((error_handle_policy & 0x20) == 0 && hevc->cur_pic != NULL) { + if (hevc->lcu_x_num != 0 + && hevc->lcu_y_num != 0 + && current_lcu_idx != 0 + && current_lcu_idx < + ((hevc->lcu_x_num*hevc->lcu_y_num) - 1)) + hevc->cur_pic->error_mark = 1; + if (hevc->cur_pic->error_mark) { + hevc_print(hevc, 0, + "cur lcu idx = %d, (total %d), set error_mark\n", + current_lcu_idx, + hevc->lcu_x_num*hevc->lcu_y_num); + if (is_log_enable(hevc)) + add_log(hevc, + "cur lcu idx = %d, (total %d), set error_mark", + current_lcu_idx, + hevc->lcu_x_num * + hevc->lcu_y_num); + + } + + } + if (hevc->cur_pic && hevc->head_error_flag) { + hevc->cur_pic->error_mark = 1; + hevc_print(hevc, 0, + "head has error, set error_mark\n"); + } + + if ((error_handle_policy & 0x80) == 0) { + if (hevc->over_decode && hevc->cur_pic) { + hevc_print(hevc, 0, + "over decode, set error_mark\n"); + hevc->cur_pic->error_mark = 1; + } + } +} + +static int hevc_slice_segment_header_process(struct hevc_state_s *hevc, + union param_u *rpm_param, + int decode_pic_begin) +{ +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + struct vdec_s *vdec = hw_to_vdec(hevc); +#endif + int i; + int lcu_x_num_div; + int lcu_y_num_div; + int Col_ref; + int dbg_skip_flag = 0; + + if (hevc->wait_buf == 0) { + hevc->sps_num_reorder_pics_0 = + rpm_param->p.sps_num_reorder_pics_0; + hevc->m_temporalId = rpm_param->p.m_temporalId; + hevc->m_nalUnitType = rpm_param->p.m_nalUnitType; + hevc->interlace_flag = + (rpm_param->p.profile_etc >> 2) & 0x1; + hevc->curr_pic_struct = + (rpm_param->p.sei_frame_field_info >> 3) & 0xf; + + if (interlace_enable == 0 || hevc->m_ins_flag) + hevc->interlace_flag = 0; + if (interlace_enable & 0x100) + hevc->interlace_flag = interlace_enable & 0x1; + if (hevc->interlace_flag == 0) + hevc->curr_pic_struct = 0; + /* if(hevc->m_nalUnitType == NAL_UNIT_EOS){ */ + /* + *hevc->m_pocRandomAccess = MAX_INT; + * //add to fix RAP_B_Bossen_1 + */ + /* } */ + hevc->misc_flag0 = rpm_param->p.misc_flag0; + if (rpm_param->p.first_slice_segment_in_pic_flag == 0) { + hevc->slice_segment_addr = + rpm_param->p.slice_segment_address; + if (!rpm_param->p.dependent_slice_segment_flag) + hevc->slice_addr = hevc->slice_segment_addr; + } else { + hevc->slice_segment_addr = 0; + hevc->slice_addr = 0; + } + + hevc->iPrevPOC = hevc->curr_POC; + hevc->slice_type = (rpm_param->p.slice_type == I_SLICE) ? 2 : + (rpm_param->p.slice_type == P_SLICE) ? 1 : + (rpm_param->p.slice_type == B_SLICE) ? 0 : 3; + /* hevc->curr_predFlag_L0=(hevc->slice_type==2) ? 0:1; */ + /* hevc->curr_predFlag_L1=(hevc->slice_type==0) ? 1:0; */ + hevc->TMVPFlag = rpm_param->p.slice_temporal_mvp_enable_flag; + hevc->isNextSliceSegment = + rpm_param->p.dependent_slice_segment_flag ? 1 : 0; + if (hevc->pic_w != rpm_param->p.pic_width_in_luma_samples + || hevc->pic_h != + rpm_param->p.pic_height_in_luma_samples) { + hevc_print(hevc, 0, + "Pic Width/Height Change (%d,%d)=>(%d,%d), interlace %d\n", + hevc->pic_w, hevc->pic_h, + rpm_param->p.pic_width_in_luma_samples, + rpm_param->p.pic_height_in_luma_samples, + hevc->interlace_flag); + + hevc->pic_w = rpm_param->p.pic_width_in_luma_samples; + hevc->pic_h = rpm_param->p.pic_height_in_luma_samples; + hevc->frame_width = hevc->pic_w; + hevc->frame_height = hevc->pic_h; +#ifdef LOSLESS_COMPRESS_MODE + if (/*re_config_pic_flag == 0 &&*/ + (get_double_write_mode(hevc) & 0x10) == 0) + init_decode_head_hw(hevc); +#endif + } + + if (OVER_SIZE(hevc->pic_w, hevc->pic_h)) { + hevc_print(hevc, 0, "over size : %u x %u.\n", + hevc->pic_w, hevc->pic_h); + if ((!hevc->m_ins_flag) && + ((debug & + H265_NO_CHANG_DEBUG_FLAG_IN_CODE) == 0)) + debug |= (H265_DEBUG_DIS_LOC_ERROR_PROC | + H265_DEBUG_DIS_SYS_ERROR_PROC); + hevc->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW; + return 3; + } + if (hevc->bit_depth_chroma > 10 || + hevc->bit_depth_luma > 10) { + hevc_print(hevc, 0, "unsupport bitdepth : %u,%u\n", + hevc->bit_depth_chroma, + hevc->bit_depth_luma); + if (!hevc->m_ins_flag) + debug |= (H265_DEBUG_DIS_LOC_ERROR_PROC | + H265_DEBUG_DIS_SYS_ERROR_PROC); + hevc->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW; + return 4; + } + + /* it will cause divide 0 error */ + if (hevc->pic_w == 0 || hevc->pic_h == 0) { + if (get_dbg_flag(hevc)) { + hevc_print(hevc, 0, + "Fatal Error, pic_w = %d, pic_h = %d\n", + hevc->pic_w, hevc->pic_h); + } + return 3; + } + pic_list_process(hevc); + + hevc->lcu_size = + 1 << (rpm_param->p.log2_min_coding_block_size_minus3 + + 3 + rpm_param-> + p.log2_diff_max_min_coding_block_size); + if (hevc->lcu_size == 0) { + hevc_print(hevc, 0, + "Error, lcu_size = 0 (%d,%d)\n", + rpm_param->p. + log2_min_coding_block_size_minus3, + rpm_param->p. + log2_diff_max_min_coding_block_size); + return 3; + } + hevc->lcu_size_log2 = log2i(hevc->lcu_size); + lcu_x_num_div = (hevc->pic_w / hevc->lcu_size); + lcu_y_num_div = (hevc->pic_h / hevc->lcu_size); + hevc->lcu_x_num = + ((hevc->pic_w % hevc->lcu_size) == + 0) ? lcu_x_num_div : lcu_x_num_div + 1; + hevc->lcu_y_num = + ((hevc->pic_h % hevc->lcu_size) == + 0) ? lcu_y_num_div : lcu_y_num_div + 1; + hevc->lcu_total = hevc->lcu_x_num * hevc->lcu_y_num; + + if (hevc->m_nalUnitType == NAL_UNIT_CODED_SLICE_IDR + || hevc->m_nalUnitType == + NAL_UNIT_CODED_SLICE_IDR_N_LP) { + hevc->curr_POC = 0; + if ((hevc->m_temporalId - 1) == 0) + hevc->iPrevTid0POC = hevc->curr_POC; + } else { + int iMaxPOClsb = + 1 << (rpm_param->p. + log2_max_pic_order_cnt_lsb_minus4 + 4); + int iPrevPOClsb; + int iPrevPOCmsb; + int iPOCmsb; + int iPOClsb = rpm_param->p.POClsb; + + if (iMaxPOClsb == 0) { + hevc_print(hevc, 0, + "error iMaxPOClsb is 0\n"); + return 3; + } + + iPrevPOClsb = hevc->iPrevTid0POC % iMaxPOClsb; + iPrevPOCmsb = hevc->iPrevTid0POC - iPrevPOClsb; + + if ((iPOClsb < iPrevPOClsb) + && ((iPrevPOClsb - iPOClsb) >= + (iMaxPOClsb / 2))) + iPOCmsb = iPrevPOCmsb + iMaxPOClsb; + else if ((iPOClsb > iPrevPOClsb) + && ((iPOClsb - iPrevPOClsb) > + (iMaxPOClsb / 2))) + iPOCmsb = iPrevPOCmsb - iMaxPOClsb; + else + iPOCmsb = iPrevPOCmsb; + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "iPrePOC%d iMaxPOClsb%d iPOCmsb%d iPOClsb%d\n", + hevc->iPrevTid0POC, iMaxPOClsb, iPOCmsb, + iPOClsb); + } + if (hevc->m_nalUnitType == NAL_UNIT_CODED_SLICE_BLA + || hevc->m_nalUnitType == + NAL_UNIT_CODED_SLICE_BLANT + || hevc->m_nalUnitType == + NAL_UNIT_CODED_SLICE_BLA_N_LP) { + /* For BLA picture types, POCmsb is set to 0. */ + iPOCmsb = 0; + } + hevc->curr_POC = (iPOCmsb + iPOClsb); + if ((hevc->m_temporalId - 1) == 0) + hevc->iPrevTid0POC = hevc->curr_POC; + else { + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "m_temporalID is %d\n", + hevc->m_temporalId); + } + } + } + hevc->RefNum_L0 = + (rpm_param->p.num_ref_idx_l0_active > + MAX_REF_ACTIVE) ? MAX_REF_ACTIVE : rpm_param->p. + num_ref_idx_l0_active; + hevc->RefNum_L1 = + (rpm_param->p.num_ref_idx_l1_active > + MAX_REF_ACTIVE) ? MAX_REF_ACTIVE : rpm_param->p. + num_ref_idx_l1_active; + + /* if(curr_POC==0x10) dump_lmem(); */ + + /* skip RASL pictures after CRA/BLA pictures */ + if (hevc->m_pocRandomAccess == MAX_INT) {/* first picture */ + if (hevc->m_nalUnitType == NAL_UNIT_CODED_SLICE_CRA || + hevc->m_nalUnitType == NAL_UNIT_CODED_SLICE_BLA + || hevc->m_nalUnitType == + NAL_UNIT_CODED_SLICE_BLANT + || hevc->m_nalUnitType == + NAL_UNIT_CODED_SLICE_BLA_N_LP) + hevc->m_pocRandomAccess = hevc->curr_POC; + else + hevc->m_pocRandomAccess = -MAX_INT; + } else if (hevc->m_nalUnitType == NAL_UNIT_CODED_SLICE_BLA + || hevc->m_nalUnitType == + NAL_UNIT_CODED_SLICE_BLANT + || hevc->m_nalUnitType == + NAL_UNIT_CODED_SLICE_BLA_N_LP) + hevc->m_pocRandomAccess = hevc->curr_POC; + else if ((hevc->curr_POC < hevc->m_pocRandomAccess) && + (nal_skip_policy >= 3) && + (hevc->m_nalUnitType == + NAL_UNIT_CODED_SLICE_RASL_N || + hevc->m_nalUnitType == + NAL_UNIT_CODED_SLICE_TFD)) { /* skip */ + if (get_dbg_flag(hevc)) { + hevc_print(hevc, 0, + "RASL picture with POC %d < %d ", + hevc->curr_POC, hevc->m_pocRandomAccess); + hevc_print(hevc, 0, + "RandomAccess point POC), skip it\n"); + } + return 1; + } + + WRITE_VREG(HEVC_WAIT_FLAG, READ_VREG(HEVC_WAIT_FLAG) | 0x2); + hevc->skip_flag = 0; + /**/ + /* if((iPrevPOC != curr_POC)){ */ + if (rpm_param->p.slice_segment_address == 0) { + struct PIC_s *pic; + + hevc->new_pic = 1; +#ifdef MULTI_INSTANCE_SUPPORT + if (!hevc->m_ins_flag) +#endif + check_pic_decoded_error_pre(hevc, + READ_VREG(HEVC_PARSER_LCU_START) + & 0xffffff); + /**/ if (use_cma == 0) { + if (hevc->pic_list_init_flag == 0) { + init_pic_list(hevc); + init_pic_list_hw(hevc); + init_buf_spec(hevc); + hevc->pic_list_init_flag = 3; + } + } + hevc->first_pic_after_recover = 0; + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR_MORE) + dump_pic_list(hevc); + /* prev pic */ + hevc_pre_pic(hevc, pic); + /* + *update referenced of old pictures + *(cur_pic->referenced is 1 and not updated) + */ + apply_ref_pic_set(hevc, hevc->curr_POC, + rpm_param); + + if (hevc->mmu_enable) + recycle_mmu_bufs(hevc); + +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + if (vdec->master) { + struct hevc_state_s *hevc_ba = + (struct hevc_state_s *) + vdec->master->private; + if (hevc_ba->cur_pic != NULL) { + hevc_ba->cur_pic->dv_enhance_exist = 1; + hevc_print(hevc, H265_DEBUG_DV, + "To decode el (poc %d) => set bl (poc %d) dv_enhance_exist flag\n", + hevc->curr_POC, hevc_ba->cur_pic->POC); + } + } + if (vdec->master == NULL && + vdec->slave == NULL) + set_aux_data(hevc, hevc->cur_pic, 1, 0); +#else + set_aux_data(hevc, hevc->cur_pic, 1, 0); +#endif + /* new pic */ + hevc->cur_pic = get_new_pic(hevc, rpm_param); + if (hevc->cur_pic == NULL) { + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + dump_pic_list(hevc); + hevc->wait_buf = 1; + return -1; + } +#ifdef MULTI_INSTANCE_SUPPORT + hevc->decoding_pic = hevc->cur_pic; +#endif +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + hevc->cur_pic->dv_enhance_exist = 0; + if (vdec->slave) + hevc_print(hevc, H265_DEBUG_DV, + "Clear bl (poc %d) dv_enhance_exist flag\n", + hevc->curr_POC); + if (vdec->master == NULL && + vdec->slave == NULL) + set_aux_data(hevc, hevc->cur_pic, 0, 0); +#else + set_aux_data(hevc, hevc->cur_pic, 0, 0); +#endif + if (get_dbg_flag(hevc) & H265_DEBUG_DISPLAY_CUR_FRAME) { + hevc->cur_pic->output_ready = 1; + hevc->cur_pic->stream_offset = + READ_VREG(HEVC_SHIFT_BYTE_COUNT); + prepare_display_buf(hevc, hevc->cur_pic); + hevc->wait_buf = 2; + return -1; + } + } else { +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + if (vdec->master == NULL && + vdec->slave == NULL) { + set_aux_data(hevc, hevc->cur_pic, 1, 0); + set_aux_data(hevc, hevc->cur_pic, 0, 0); + } +#else + set_aux_data(hevc, hevc->cur_pic, 1, 0); + set_aux_data(hevc, hevc->cur_pic, 0, 0); +#endif + if (hevc->pic_list_init_flag != 3 + || hevc->cur_pic == NULL) { + /* make it dec from the first slice segment */ + return 3; + } + hevc->cur_pic->slice_idx++; + hevc->new_pic = 0; + } + } else { + if (hevc->wait_buf == 1) { + pic_list_process(hevc); + hevc->cur_pic = get_new_pic(hevc, rpm_param); + if (hevc->cur_pic == NULL) + return -1; + +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + hevc->cur_pic->dv_enhance_exist = 0; + if (vdec->master == NULL && + vdec->slave == NULL) + set_aux_data(hevc, hevc->cur_pic, 0, 0); +#else + set_aux_data(hevc, hevc->cur_pic, 0, 0); +#endif + hevc->wait_buf = 0; + } else if (hevc->wait_buf == + 2) { + if (get_display_pic_num(hevc) > + 1) + return -1; + hevc->wait_buf = 0; + } + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR_MORE) + dump_pic_list(hevc); + } + + if (hevc->new_pic) { +#if 1 + /*SUPPORT_10BIT*/ + int sao_mem_unit = + (hevc->lcu_size == 16 ? 9 : + hevc->lcu_size == + 32 ? 14 : 24) << 4; +#else + int sao_mem_unit = ((hevc->lcu_size / 8) * 2 + 4) << 4; +#endif + int pic_height_cu = + (hevc->pic_h + hevc->lcu_size - 1) / hevc->lcu_size; + int pic_width_cu = + (hevc->pic_w + hevc->lcu_size - 1) / hevc->lcu_size; + int sao_vb_size = (sao_mem_unit + (2 << 4)) * pic_height_cu; + + /* int sao_abv_size = sao_mem_unit*pic_width_cu; */ + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "==>%s dec idx %d, struct %d interlace %d pic idx %d\n", + __func__, + hevc->decode_idx, + hevc->curr_pic_struct, + hevc->interlace_flag, + hevc->cur_pic->index); + } + if (dbg_skip_decode_index != 0 && + hevc->decode_idx == dbg_skip_decode_index) + dbg_skip_flag = 1; + + hevc->decode_idx++; + update_tile_info(hevc, pic_width_cu, pic_height_cu, + sao_mem_unit, rpm_param); + + config_title_hw(hevc, sao_vb_size, sao_mem_unit); + } + + if (hevc->iPrevPOC != hevc->curr_POC) { + hevc->new_tile = 1; + hevc->tile_x = 0; + hevc->tile_y = 0; + hevc->tile_y_x = 0; + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "new_tile (new_pic) tile_x=%d, tile_y=%d\n", + hevc->tile_x, hevc->tile_y); + } + } else if (hevc->tile_enabled) { + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "slice_segment_address is %d\n", + rpm_param->p.slice_segment_address); + } + hevc->tile_y_x = + get_tile_index(hevc, rpm_param->p.slice_segment_address, + (hevc->pic_w + + hevc->lcu_size - + 1) / hevc->lcu_size); + if ((hevc->tile_y_x != (hevc->tile_x | (hevc->tile_y << 8))) + && (hevc->tile_y_x != -1)) { + hevc->new_tile = 1; + hevc->tile_x = hevc->tile_y_x & 0xff; + hevc->tile_y = (hevc->tile_y_x >> 8) & 0xff; + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "new_tile seg adr %d tile_x=%d, tile_y=%d\n", + rpm_param->p.slice_segment_address, + hevc->tile_x, hevc->tile_y); + } + } else + hevc->new_tile = 0; + } else + hevc->new_tile = 0; + + if ((hevc->tile_x > (MAX_TILE_COL_NUM - 1)) + || (hevc->tile_y > (MAX_TILE_ROW_NUM - 1))) + hevc->new_tile = 0; + + if (hevc->new_tile) { + hevc->tile_start_lcu_x = + hevc->m_tile[hevc->tile_y][hevc->tile_x].start_cu_x; + hevc->tile_start_lcu_y = + hevc->m_tile[hevc->tile_y][hevc->tile_x].start_cu_y; + hevc->tile_width_lcu = + hevc->m_tile[hevc->tile_y][hevc->tile_x].width; + hevc->tile_height_lcu = + hevc->m_tile[hevc->tile_y][hevc->tile_x].height; + } + + set_ref_pic_list(hevc, rpm_param); + + Col_ref = rpm_param->p.collocated_ref_idx; + + hevc->LDCFlag = 0; + if (rpm_param->p.slice_type != I_SLICE) { + hevc->LDCFlag = 1; + for (i = 0; (i < hevc->RefNum_L0) && hevc->LDCFlag; i++) { + if (hevc->cur_pic-> + m_aiRefPOCList0[hevc->cur_pic->slice_idx][i] > + hevc->curr_POC) + hevc->LDCFlag = 0; + } + if (rpm_param->p.slice_type == B_SLICE) { + for (i = 0; (i < hevc->RefNum_L1) + && hevc->LDCFlag; i++) { + if (hevc->cur_pic-> + m_aiRefPOCList1[hevc->cur_pic-> + slice_idx][i] > + hevc->curr_POC) + hevc->LDCFlag = 0; + } + } + } + + hevc->ColFromL0Flag = rpm_param->p.collocated_from_l0_flag; + + hevc->plevel = + rpm_param->p.log2_parallel_merge_level; + hevc->MaxNumMergeCand = 5 - rpm_param->p.five_minus_max_num_merge_cand; + + hevc->LongTerm_Curr = 0; /* to do ... */ + hevc->LongTerm_Col = 0; /* to do ... */ + + hevc->list_no = 0; + if (rpm_param->p.slice_type == B_SLICE) + hevc->list_no = 1 - hevc->ColFromL0Flag; + if (hevc->list_no == 0) { + if (Col_ref < hevc->RefNum_L0) { + hevc->Col_POC = + hevc->cur_pic->m_aiRefPOCList0[hevc->cur_pic-> + slice_idx][Col_ref]; + } else + hevc->Col_POC = INVALID_POC; + } else { + if (Col_ref < hevc->RefNum_L1) { + hevc->Col_POC = + hevc->cur_pic->m_aiRefPOCList1[hevc->cur_pic-> + slice_idx][Col_ref]; + } else + hevc->Col_POC = INVALID_POC; + } + + hevc->LongTerm_Ref = 0; /* to do ... */ + + if (hevc->slice_type != 2) { + /* if(hevc->i_only==1){ */ + /* return 0xf; */ + /* } */ + + if (hevc->Col_POC != INVALID_POC) { + hevc->col_pic = get_ref_pic_by_POC(hevc, hevc->Col_POC); + if (hevc->col_pic == NULL) { + hevc->cur_pic->error_mark = 1; + if (get_dbg_flag(hevc)) { + hevc_print(hevc, 0, + "WRONG,fail to get the pic Col_POC\n"); + } + if (is_log_enable(hevc)) + add_log(hevc, + "WRONG,fail to get the pic Col_POC"); + } else if (hevc->col_pic->error_mark) { + hevc->cur_pic->error_mark = 1; + if (get_dbg_flag(hevc)) { + hevc_print(hevc, 0, + "WRONG, Col_POC error_mark is 1\n"); + } + if (is_log_enable(hevc)) + add_log(hevc, + "WRONG, Col_POC error_mark is 1"); + } else { + if ((hevc->col_pic->width + != hevc->pic_w) || + (hevc->col_pic->height + != hevc->pic_h)) { + hevc_print(hevc, 0, + "Wrong reference pic (poc %d) width/height %d/%d\n", + hevc->col_pic->POC, + hevc->col_pic->width, + hevc->col_pic->height); + hevc->cur_pic->error_mark = 1; + } + + } + + if (hevc->cur_pic->error_mark + && ((hevc->ignore_bufmgr_error & 0x1) == 0)) { +#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + /*count info*/ + vdec_count_info(gvs, hevc->cur_pic->error_mark, + hevc->cur_pic->stream_offset); +#endif + } + + if (is_skip_decoding(hevc, + hevc->cur_pic)) { + return 2; + } + } else + hevc->col_pic = hevc->cur_pic; + } /* */ + if (hevc->col_pic == NULL) + hevc->col_pic = hevc->cur_pic; +#ifdef BUFFER_MGR_ONLY + return 0xf; +#else + if ((decode_pic_begin > 0 && hevc->decode_idx <= decode_pic_begin) + || (dbg_skip_flag)) + return 0xf; +#endif + + config_mc_buffer(hevc, hevc->cur_pic); + + if (is_skip_decoding(hevc, + hevc->cur_pic)) { + if (get_dbg_flag(hevc)) + hevc_print(hevc, 0, + "Discard this picture index %d\n", + hevc->cur_pic->index); +#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + /*count info*/ + vdec_count_info(gvs, hevc->cur_pic->error_mark, + hevc->cur_pic->stream_offset); +#endif + return 2; + } +#ifdef MCRCC_ENABLE + config_mcrcc_axi_hw(hevc, hevc->cur_pic->slice_type); +#endif + config_mpred_hw(hevc); + + config_sao_hw(hevc, rpm_param); + + if ((hevc->slice_type != 2) && (hevc->i_only & 0x2)) + return 0xf; + + return 0; +} + + + +static int H265_alloc_mmu(struct hevc_state_s *hevc, struct PIC_s *new_pic, + unsigned short bit_depth, unsigned int *mmu_index_adr) { + int cur_buf_idx = new_pic->index; + int bit_depth_10 = (bit_depth != 0x00); + int picture_size; + int cur_mmu_4k_number; + int ret; + picture_size = compute_losless_comp_body_size(hevc, new_pic->width, + new_pic->height, !bit_depth_10); + cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12); + + /*hevc_print(hevc, 0, + "alloc_mmu cur_idx : %d picture_size : %d mmu_4k_number : %d\r\n", + cur_buf_idx, picture_size, cur_mmu_4k_number);*/ + if (new_pic->scatter_alloc) { + decoder_mmu_box_free_idx(hevc->mmu_box, new_pic->index); + new_pic->scatter_alloc = 0; + } + if (cur_mmu_4k_number > MAX_FRAME_4K_NUM) { + hevc_print(hevc, 0, "over max !! 0x%x width %d height %d\n", + cur_mmu_4k_number, + new_pic->width, + new_pic->height); + return -1; + } + ret = decoder_mmu_box_alloc_idx( + hevc->mmu_box, + cur_buf_idx, + cur_mmu_4k_number, + mmu_index_adr); + if (ret == 0) + new_pic->scatter_alloc = 1; + hevc_print(hevc, H265_DEBUG_BUFMGR_MORE, + "%s pic index %d page count(%d) ret =%d\n", + __func__, cur_buf_idx, + cur_mmu_4k_number, + ret); + return ret; +} + + +static void release_pic_mmu_buf(struct hevc_state_s *hevc, + struct PIC_s *pic) +{ + hevc_print(hevc, H265_DEBUG_BUFMGR_MORE, + "%s pic index %d scatter_alloc %d\n", + __func__, pic->index, + pic->scatter_alloc); + + if (hevc->mmu_enable && pic->scatter_alloc) + decoder_mmu_box_free_idx(hevc->mmu_box, pic->index); + pic->scatter_alloc = 0; +} + +/* + ************************************************* + * + *h265 buffer management end + * + ************************************************** + */ +static struct hevc_state_s *gHevc; + +static void hevc_local_uninit(struct hevc_state_s *hevc) +{ + hevc->rpm_ptr = NULL; + hevc->lmem_ptr = NULL; + + if (hevc->aux_addr) { + dma_unmap_single(amports_get_dma_device(), + hevc->aux_phy_addr, + hevc->prefix_aux_size + hevc->suffix_aux_size, + DMA_FROM_DEVICE); + kfree(hevc->aux_addr); + hevc->aux_addr = NULL; + } + if (hevc->rpm_addr) { + dma_unmap_single(amports_get_dma_device(), + hevc->rpm_phy_addr, RPM_BUF_SIZE, DMA_FROM_DEVICE); + kfree(hevc->rpm_addr); + hevc->rpm_addr = NULL; + } + if (hevc->lmem_addr) { + dma_unmap_single(amports_get_dma_device(), + hevc->lmem_phy_addr, LMEM_BUF_SIZE, DMA_FROM_DEVICE); + kfree(hevc->lmem_addr); + hevc->lmem_addr = NULL; + } + + if (hevc->mmu_enable && hevc->frame_mmu_map_addr) { + if (hevc->frame_mmu_map_phy_addr) + dma_free_coherent(amports_get_dma_device(), + FRAME_MMU_MAP_SIZE, hevc->frame_mmu_map_addr, + hevc->frame_mmu_map_phy_addr); + + hevc->frame_mmu_map_addr = NULL; + } + + kfree(gvs); + gvs = NULL; +} + +static int hevc_local_init(struct hevc_state_s *hevc) +{ + int ret = -1; + struct BuffInfo_s *cur_buf_info = NULL; + + memset(&hevc->param, 0, sizeof(union param_u)); + + cur_buf_info = &hevc->work_space_buf_store; +#ifdef SUPPORT_4K2K + if (vdec_is_support_4k()) + memcpy(cur_buf_info, &amvh265_workbuff_spec[1], /* 4k */ + sizeof(struct BuffInfo_s)); + else + memcpy(cur_buf_info, &amvh265_workbuff_spec[0], /* 1080p */ + sizeof(struct BuffInfo_s)); +#else + memcpy(cur_buf_info, &amvh265_workbuff_spec[0], /* 1080p work space */ + sizeof(struct BuffInfo_s)); +#endif + cur_buf_info->start_adr = hevc->buf_start; + init_buff_spec(hevc, cur_buf_info); + + hevc_init_stru(hevc, cur_buf_info); + + hevc->bit_depth_luma = 8; + hevc->bit_depth_chroma = 8; + hevc->video_signal_type = 0; + bit_depth_luma = hevc->bit_depth_luma; + bit_depth_chroma = hevc->bit_depth_chroma; + video_signal_type = hevc->video_signal_type; + + if ((get_dbg_flag(hevc) & H265_DEBUG_SEND_PARAM_WITH_REG) == 0) { + hevc->rpm_addr = kmalloc(RPM_BUF_SIZE, GFP_KERNEL); + if (hevc->rpm_addr == NULL) { + pr_err("%s: failed to alloc rpm buffer\n", __func__); + return -1; + } + + hevc->rpm_phy_addr = dma_map_single(amports_get_dma_device(), + hevc->rpm_addr, RPM_BUF_SIZE, DMA_FROM_DEVICE); + if (dma_mapping_error(amports_get_dma_device(), + hevc->rpm_phy_addr)) { + pr_err("%s: failed to map rpm buffer\n", __func__); + kfree(hevc->rpm_addr); + hevc->rpm_addr = NULL; + return -1; + } + + hevc->rpm_ptr = hevc->rpm_addr; + } + + if (prefix_aux_buf_size > 0 || + suffix_aux_buf_size > 0) { + u32 aux_buf_size; + + hevc->prefix_aux_size = AUX_BUF_ALIGN(prefix_aux_buf_size); + hevc->suffix_aux_size = AUX_BUF_ALIGN(suffix_aux_buf_size); + aux_buf_size = hevc->prefix_aux_size + hevc->suffix_aux_size; + hevc->aux_addr = kmalloc(aux_buf_size, GFP_KERNEL); + if (hevc->aux_addr == NULL) { + pr_err("%s: failed to alloc rpm buffer\n", __func__); + return -1; + } + + hevc->aux_phy_addr = dma_map_single(amports_get_dma_device(), + hevc->aux_addr, aux_buf_size, DMA_FROM_DEVICE); + if (dma_mapping_error(amports_get_dma_device(), + hevc->aux_phy_addr)) { + pr_err("%s: failed to map rpm buffer\n", __func__); + kfree(hevc->aux_addr); + hevc->aux_addr = NULL; + return -1; + } + } + + hevc->lmem_addr = kmalloc(LMEM_BUF_SIZE, GFP_KERNEL); + if (hevc->lmem_addr == NULL) { + pr_err("%s: failed to alloc lmem buffer\n", __func__); + return -1; + } + hevc->lmem_phy_addr = dma_map_single(amports_get_dma_device(), + hevc->lmem_addr, LMEM_BUF_SIZE, DMA_FROM_DEVICE); + if (dma_mapping_error(amports_get_dma_device(), + hevc->lmem_phy_addr)) { + pr_err("%s: failed to map lmem buffer\n", __func__); + kfree(hevc->lmem_addr); + hevc->lmem_addr = NULL; + return -1; + } + hevc->lmem_ptr = hevc->lmem_addr; + + if (hevc->mmu_enable) { + hevc->frame_mmu_map_addr = + dma_alloc_coherent(amports_get_dma_device(), + FRAME_MMU_MAP_SIZE, + &hevc->frame_mmu_map_phy_addr, GFP_KERNEL); + if (hevc->frame_mmu_map_addr == NULL) { + pr_err("%s: failed to alloc count_buffer\n", __func__); + return -1; + } + memset(hevc->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE); + } + ret = 0; + return ret; +} + +/* + ******************************************* + * Mailbox command + ******************************************* + */ +#define CMD_FINISHED 0 +#define CMD_ALLOC_VIEW 1 +#define CMD_FRAME_DISPLAY 3 +#define CMD_DEBUG 10 + + +#define DECODE_BUFFER_NUM_MAX 32 +#define DISPLAY_BUFFER_NUM 6 + +#define video_domain_addr(adr) (adr&0x7fffffff) +#define DECODER_WORK_SPACE_SIZE 0x800000 + +#define spec2canvas(x) \ + (((x)->uv_canvas_index << 16) | \ + ((x)->uv_canvas_index << 8) | \ + ((x)->y_canvas_index << 0)) + + +static void set_canvas(struct hevc_state_s *hevc, struct PIC_s *pic) +{ + int canvas_w = ALIGN(pic->width, 64)/4; + int canvas_h = ALIGN(pic->height, 32)/4; + int blkmode = mem_map_mode; + + /*CANVAS_BLKMODE_64X32*/ +#ifdef SUPPORT_10BIT + if (pic->double_write_mode) { + canvas_w = pic->width / + get_double_write_ratio(hevc, pic->double_write_mode); + canvas_h = pic->height / + get_double_write_ratio(hevc, pic->double_write_mode); + + if (mem_map_mode == 0) + canvas_w = ALIGN(canvas_w, 32); + else + canvas_w = ALIGN(canvas_w, 64); + canvas_h = ALIGN(canvas_h, 32); + + pic->y_canvas_index = 128 + pic->index * 2; + pic->uv_canvas_index = 128 + pic->index * 2 + 1; + + canvas_config_ex(pic->y_canvas_index, + pic->dw_y_adr, canvas_w, canvas_h, + CANVAS_ADDR_NOWRAP, blkmode, 0x7); + canvas_config_ex(pic->uv_canvas_index, pic->dw_u_v_adr, + canvas_w, canvas_h, + CANVAS_ADDR_NOWRAP, blkmode, 0x7); +#ifdef MULTI_INSTANCE_SUPPORT + pic->canvas_config[0].phy_addr = + pic->dw_y_adr; + pic->canvas_config[0].width = + canvas_w; + pic->canvas_config[0].height = + canvas_h; + pic->canvas_config[0].block_mode = + blkmode; + pic->canvas_config[0].endian = 7; + + pic->canvas_config[1].phy_addr = + pic->dw_u_v_adr; + pic->canvas_config[1].width = + canvas_w; + pic->canvas_config[1].height = + canvas_h; + pic->canvas_config[1].block_mode = + blkmode; + pic->canvas_config[1].endian = 7; +#endif + } else { + if (!hevc->mmu_enable) { + /* to change after 10bit VPU is ready ... */ + pic->y_canvas_index = 128 + pic->index; + pic->uv_canvas_index = 128 + pic->index; + + canvas_config_ex(pic->y_canvas_index, + pic->mc_y_adr, canvas_w, canvas_h, + CANVAS_ADDR_NOWRAP, blkmode, 0x7); + canvas_config_ex(pic->uv_canvas_index, pic->mc_u_v_adr, + canvas_w, canvas_h, + CANVAS_ADDR_NOWRAP, blkmode, 0x7); + } + } +#else + pic->y_canvas_index = 128 + pic->index * 2; + pic->uv_canvas_index = 128 + pic->index * 2 + 1; + + canvas_config_ex(pic->y_canvas_index, pic->mc_y_adr, canvas_w, canvas_h, + CANVAS_ADDR_NOWRAP, blkmode, 0x7); + canvas_config_ex(pic->uv_canvas_index, pic->mc_u_v_adr, + canvas_w, canvas_h, + CANVAS_ADDR_NOWRAP, blkmode, 0x7); +#endif +} + +static int init_buf_spec(struct hevc_state_s *hevc) +{ + int pic_width = hevc->pic_w; + int pic_height = hevc->pic_h; + + /* hevc_print(hevc, 0, + *"%s1: %d %d\n", __func__, hevc->pic_w, hevc->pic_h); + */ + hevc_print(hevc, 0, + "%s2 %d %d\n", __func__, pic_width, pic_height); + /* pic_width = hevc->pic_w; */ + /* pic_height = hevc->pic_h; */ + + if (hevc->frame_width == 0 || hevc->frame_height == 0) { + hevc->frame_width = pic_width; + hevc->frame_height = pic_height; + + } + + return 0; +} + +static int parse_sei(struct hevc_state_s *hevc, + struct PIC_s *pic, char *sei_buf, uint32_t size) +{ + char *p = sei_buf; + char *p_sei; + uint16_t header; + uint8_t nal_unit_type; + uint8_t payload_type, payload_size; + int i, j; + + if (size < 2) + return 0; + header = *p++; + header <<= 8; + header += *p++; + nal_unit_type = header >> 9; + if ((nal_unit_type != NAL_UNIT_SEI) + && (nal_unit_type != NAL_UNIT_SEI_SUFFIX)) + return 0; + while (p+2 <= sei_buf+size) { + payload_type = *p++; + payload_size = *p++; + if (p+payload_size <= sei_buf+size) { + switch (payload_type) { + case SEI_PicTiming: + p_sei = p; + hevc->curr_pic_struct = (*p_sei >> 4)&0x0f; + pic->pic_struct = hevc->curr_pic_struct; + if (get_dbg_flag(hevc) & + H265_DEBUG_PIC_STRUCT) { + hevc_print(hevc, 0, + "parse result pic_struct = %d\n", + hevc->curr_pic_struct); + } + break; + case SEI_MasteringDisplayColorVolume: + /*hevc_print(hevc, 0, + "sei type: primary display color volume %d, size %d\n", + payload_type, + payload_size);*/ + /* master_display_colour */ + p_sei = p; + for (i = 0; i < 3; i++) { + for (j = 0; j < 2; j++) { + hevc->primaries[i][j] + = (*p_sei<<8) + | *(p_sei+1); + p_sei += 2; + } + } + for (i = 0; i < 2; i++) { + hevc->white_point[i] + = (*p_sei<<8) + | *(p_sei+1); + p_sei += 2; + } + for (i = 0; i < 2; i++) { + hevc->luminance[i] + = (*p_sei<<24) + | (*(p_sei+1)<<16) + | (*(p_sei+2)<<8) + | *(p_sei+3); + p_sei += 4; + } + hevc->sei_present_flag |= + SEI_MASTER_DISPLAY_COLOR_MASK; + /*for (i = 0; i < 3; i++) + for (j = 0; j < 2; j++) + hevc_print(hevc, 0, + "\tprimaries[%1d][%1d] = %04x\n", + i, j, + hevc->primaries[i][j]); + hevc_print(hevc, 0, + "\twhite_point = (%04x, %04x)\n", + hevc->white_point[0], + hevc->white_point[1]); + hevc_print(hevc, 0, + "\tmax,min luminance = %08x, %08x\n", + hevc->luminance[0], + hevc->luminance[1]);*/ + break; + case SEI_ContentLightLevel: + hevc_print(hevc, 0, + "sei type: max content light level %d, size %d\n", + payload_type, payload_size); + /* content_light_level */ + p_sei = p; + hevc->content_light_level[0] + = (*p_sei<<8) | *(p_sei+1); + p_sei += 2; + hevc->content_light_level[1] + = (*p_sei<<8) | *(p_sei+1); + p_sei += 2; + hevc->sei_present_flag |= + SEI_CONTENT_LIGHT_LEVEL_MASK; + hevc_print(hevc, 0, + "\tmax cll = %04x, max_pa_cll = %04x\n", + hevc->content_light_level[0], + hevc->content_light_level[1]); + break; + default: + break; + } + } + p += payload_size; + } + return 0; +} + +static unsigned calc_ar(unsigned idc, unsigned sar_w, unsigned sar_h, + unsigned w, unsigned h) +{ + unsigned ar; + + if (idc == 255) { + ar = div_u64(256ULL * sar_h * h, + sar_w * w); + } else { + switch (idc) { + case 1: + ar = 0x100 * h / w; + break; + case 2: + ar = 0x100 * h * 11 / (w * 12); + break; + case 3: + ar = 0x100 * h * 11 / (w * 10); + break; + case 4: + ar = 0x100 * h * 11 / (w * 16); + break; + case 5: + ar = 0x100 * h * 33 / (w * 40); + break; + case 6: + ar = 0x100 * h * 11 / (w * 24); + break; + case 7: + ar = 0x100 * h * 11 / (w * 20); + break; + case 8: + ar = 0x100 * h * 11 / (w * 32); + break; + case 9: + ar = 0x100 * h * 33 / (w * 80); + break; + case 10: + ar = 0x100 * h * 11 / (w * 18); + break; + case 11: + ar = 0x100 * h * 11 / (w * 15); + break; + case 12: + ar = 0x100 * h * 33 / (w * 64); + break; + case 13: + ar = 0x100 * h * 99 / (w * 160); + break; + case 14: + ar = 0x100 * h * 3 / (w * 4); + break; + case 15: + ar = 0x100 * h * 2 / (w * 3); + break; + case 16: + ar = 0x100 * h * 1 / (w * 2); + break; + default: + ar = h * 0x100 / w; + break; + } + } + + return ar; +} + +static void set_frame_info(struct hevc_state_s *hevc, struct vframe_s *vf, + struct PIC_s *pic) +{ + unsigned int ar; + int i, j; + char *p; + unsigned size = 0; + unsigned type = 0; + struct vframe_master_display_colour_s *vf_dp + = &vf->prop.master_display_colour; + + vf->width = pic->width / + get_double_write_ratio(hevc, pic->double_write_mode); + vf->height = pic->height / + get_double_write_ratio(hevc, pic->double_write_mode); + + vf->duration = hevc->frame_dur; + vf->duration_pulldown = 0; + vf->flag = 0; + + ar = min_t(u32, hevc->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX); + vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT); + + /* signal_type */ + if (hevc->video_signal_type & VIDEO_SIGNAL_TYPE_AVAILABLE_MASK) + vf->signal_type = hevc->video_signal_type; + else + vf->signal_type = 0; + + if (((pic->aspect_ratio_idc == 255) && + pic->sar_width && + pic->sar_height) || + ((pic->aspect_ratio_idc != 255) && + (pic->width))) { + ar = min_t(u32, + calc_ar(pic->aspect_ratio_idc, + pic->sar_width, + pic->sar_height, + pic->width, + pic->height), + DISP_RATIO_ASPECT_RATIO_MAX); + vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT); + } + if (pic->aux_data_buf + && pic->aux_data_size) { + /* parser sei */ + p = pic->aux_data_buf; + while (p < pic->aux_data_buf + + pic->aux_data_size - 8) { + size = *p++; + size = (size << 8) | *p++; + size = (size << 8) | *p++; + size = (size << 8) | *p++; + type = *p++; + type = (type << 8) | *p++; + type = (type << 8) | *p++; + type = (type << 8) | *p++; + if (type == 0x02000000) { + /* hevc_print(hevc, 0, + "sei(%d)\n", size); */ + parse_sei(hevc, pic, p, size); + } + p += size; + } + } + + /* master_display_colour */ + if (hevc->sei_present_flag & SEI_MASTER_DISPLAY_COLOR_MASK) { + for (i = 0; i < 3; i++) + for (j = 0; j < 2; j++) + vf_dp->primaries[i][j] = hevc->primaries[i][j]; + for (i = 0; i < 2; i++) { + vf_dp->white_point[i] = hevc->white_point[i]; + vf_dp->luminance[i] + = hevc->luminance[i]; + } + vf_dp->present_flag = 1; + } else + vf_dp->present_flag = 0; + + /* content_light_level */ + if (hevc->sei_present_flag & SEI_CONTENT_LIGHT_LEVEL_MASK) { + vf_dp->content_light_level.max_content + = hevc->content_light_level[0]; + vf_dp->content_light_level.max_pic_average + = hevc->content_light_level[1]; + vf_dp->content_light_level.present_flag = 1; + } else + vf_dp->content_light_level.present_flag = 0; +} + +static int vh265_vf_states(struct vframe_states *states, void *op_arg) +{ + unsigned long flags; +#ifdef MULTI_INSTANCE_SUPPORT + struct vdec_s *vdec = op_arg; + struct hevc_state_s *hevc = (struct hevc_state_s *)vdec->private; +#else + struct hevc_state_s *hevc = (struct hevc_state_s *)op_arg; +#endif + + spin_lock_irqsave(&lock, flags); + + states->vf_pool_size = VF_POOL_SIZE; + states->buf_free_num = kfifo_len(&hevc->newframe_q); + states->buf_avail_num = kfifo_len(&hevc->display_q); + + if (step == 2) + states->buf_avail_num = 0; + spin_unlock_irqrestore(&lock, flags); + return 0; +} + +static struct vframe_s *vh265_vf_peek(void *op_arg) +{ + struct vframe_s *vf[2] = {0, 0}; +#ifdef MULTI_INSTANCE_SUPPORT + struct vdec_s *vdec = op_arg; + struct hevc_state_s *hevc = (struct hevc_state_s *)vdec->private; +#else + struct hevc_state_s *hevc = (struct hevc_state_s *)op_arg; +#endif + + if (step == 2) + return NULL; + + if (force_disp_pic_index & 0x100) { + if (force_disp_pic_index & 0x200) + return NULL; + return &hevc->vframe_dummy; + } + + + if (kfifo_out_peek(&hevc->display_q, (void *)&vf, 2)) { + if (vf[1]) { + vf[0]->next_vf_pts_valid = true; + vf[0]->next_vf_pts = vf[1]->pts; + } else + vf[0]->next_vf_pts_valid = false; + return vf[0]; + } + + return NULL; +} + +static struct vframe_s *vh265_vf_get(void *op_arg) +{ + struct vframe_s *vf; +#ifdef MULTI_INSTANCE_SUPPORT + struct vdec_s *vdec = op_arg; + struct hevc_state_s *hevc = (struct hevc_state_s *)vdec->private; +#else + struct hevc_state_s *hevc = (struct hevc_state_s *)op_arg; +#endif + + if (step == 2) + return NULL; + else if (step == 1) + step = 2; + +#if 0 + if (force_disp_pic_index & 0x100) { + int buffer_index = force_disp_pic_index & 0xff; + struct PIC_s *pic = NULL; + if (buffer_index >= 0 + && buffer_index < MAX_REF_PIC_NUM) + pic = hevc->m_PIC[buffer_index]; + if (pic == NULL) + return NULL; + if (force_disp_pic_index & 0x200) + return NULL; + + vf = &hevc->vframe_dummy; + if (get_double_write_mode(hevc)) { + vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD | + VIDTYPE_VIU_NV21; + if (hevc->m_ins_flag) { + vf->canvas0Addr = vf->canvas1Addr = -1; + vf->plane_num = 2; + vf->canvas0_config[0] = + pic->canvas_config[0]; + vf->canvas0_config[1] = + pic->canvas_config[1]; + + vf->canvas1_config[0] = + pic->canvas_config[0]; + vf->canvas1_config[1] = + pic->canvas_config[1]; + } else { + vf->canvas0Addr = vf->canvas1Addr + = spec2canvas(pic); + } + } else { + vf->canvas0Addr = vf->canvas1Addr = 0; + vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD; + if (hevc->mmu_enable) + vf->type |= VIDTYPE_SCATTER; + } + vf->compWidth = pic->width; + vf->compHeight = pic->height; + update_vf_memhandle(hevc, vf, pic); + switch (hevc->bit_depth_luma) { + case 9: + vf->bitdepth = BITDEPTH_Y9 | BITDEPTH_U9 | BITDEPTH_V9; + break; + case 10: + vf->bitdepth = BITDEPTH_Y10 | BITDEPTH_U10 + | BITDEPTH_V10; + break; + default: + vf->bitdepth = BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8; + break; + } + if ((vf->type & VIDTYPE_COMPRESS) == 0) + vf->bitdepth = + BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8; + if (hevc->mem_saving_mode == 1) + vf->bitdepth |= BITDEPTH_SAVING_MODE; + vf->duration_pulldown = 0; + vf->pts = 0; + vf->pts_us64 = 0; + set_frame_info(hevc, vf); + + vf->width = pic->width / + get_double_write_ratio(hevc, pic->double_write_mode); + vf->height = pic->height / + get_double_write_ratio(hevc, pic->double_write_mode); + + force_disp_pic_index |= 0x200; + return vf; + } +#endif + + if (kfifo_get(&hevc->display_q, &vf)) { + struct vframe_s *next_vf; + if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT) + hevc_print(hevc, 0, + "%s(type %d index 0x%x poc %d/%d) pts(%d,%d) dur %d\n", + __func__, vf->type, vf->index, + get_pic_poc(hevc, vf->index & 0xff), + get_pic_poc(hevc, (vf->index >> 8) & 0xff), + vf->pts, vf->pts_us64, + vf->duration); + + hevc->show_frame_num++; + hevc->vf_get_count++; + + if (kfifo_peek(&hevc->display_q, &next_vf)) { + vf->next_vf_pts_valid = true; + vf->next_vf_pts = next_vf->pts; + } else + vf->next_vf_pts_valid = false; + + return vf; + } + + return NULL; +} + +static void vh265_vf_put(struct vframe_s *vf, void *op_arg) +{ + unsigned long flags; +#ifdef MULTI_INSTANCE_SUPPORT + struct vdec_s *vdec = op_arg; + struct hevc_state_s *hevc = (struct hevc_state_s *)vdec->private; +#else + struct hevc_state_s *hevc = (struct hevc_state_s *)op_arg; +#endif + unsigned char index_top = vf->index & 0xff; + unsigned char index_bot = (vf->index >> 8) & 0xff; + if (vf == (&hevc->vframe_dummy)) + return; + if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT) + hevc_print(hevc, 0, + "%s(type %d index 0x%x)\n", + __func__, vf->type, vf->index); + hevc->vf_put_count++; + kfifo_put(&hevc->newframe_q, (const struct vframe_s *)vf); + spin_lock_irqsave(&lock, flags); + + if (index_top != 0xff && index_top >= 0 + && index_top < MAX_REF_PIC_NUM + && hevc->m_PIC[index_top]) { + if (hevc->m_PIC[index_top]->vf_ref > 0) { + hevc->m_PIC[index_top]->vf_ref--; + + if (hevc->m_PIC[index_top]->vf_ref == 0) { + hevc->m_PIC[index_top]->output_ready = 0; + + if (hevc->wait_buf != 0) + WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, + 0x1); + } + } + } + + if (index_bot != 0xff && index_bot >= 0 + && index_bot < MAX_REF_PIC_NUM + && hevc->m_PIC[index_bot]) { + if (hevc->m_PIC[index_bot]->vf_ref > 0) { + hevc->m_PIC[index_bot]->vf_ref--; + + if (hevc->m_PIC[index_bot]->vf_ref == 0) { + hevc->m_PIC[index_bot]->output_ready = 0; + if (hevc->wait_buf != 0) + WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, + 0x1); + } + } + } + spin_unlock_irqrestore(&lock, flags); +} + +static int vh265_event_cb(int type, void *data, void *op_arg) +{ + unsigned long flags; +#ifdef MULTI_INSTANCE_SUPPORT + struct vdec_s *vdec = op_arg; + struct hevc_state_s *hevc = (struct hevc_state_s *)vdec->private; +#else + struct hevc_state_s *hevc = (struct hevc_state_s *)op_arg; +#endif + if (type & VFRAME_EVENT_RECEIVER_RESET) { +#if 0 + amhevc_stop(); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_light_unreg_provider(&vh265_vf_prov); +#endif + spin_lock_irqsave(&hevc->lock, flags); + vh265_local_init(); + vh265_prot_init(); + spin_unlock_irqrestore(&hevc->lock, flags); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_reg_provider(&vh265_vf_prov); +#endif + amhevc_start(); +#endif + } else if (type & VFRAME_EVENT_RECEIVER_GET_AUX_DATA) { + struct provider_aux_req_s *req = + (struct provider_aux_req_s *)data; + unsigned char index; + + spin_lock_irqsave(&lock, flags); + index = req->vf->index & 0xff; + req->aux_buf = NULL; + req->aux_size = 0; + if (req->bot_flag) + index = (req->vf->index >> 8) & 0xff; + if (index != 0xff && index >= 0 + && index < MAX_REF_PIC_NUM + && hevc->m_PIC[index]) { + req->aux_buf = hevc->m_PIC[index]->aux_data_buf; + req->aux_size = hevc->m_PIC[index]->aux_data_size; +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + req->dv_enhance_exist = + hevc->m_PIC[index]->dv_enhance_exist; + hevc_print(hevc, H265_DEBUG_DV, + "query dv_enhance_exist for pic (poc %d) flag => %d\n", + hevc->m_PIC[index]->POC, req->dv_enhance_exist); +#else + req->dv_enhance_exist = 0; +#endif + } + spin_unlock_irqrestore(&lock, flags); + + if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT) + hevc_print(hevc, 0, + "%s(type 0x%x vf index 0x%x)=>size 0x%x\n", + __func__, type, index, req->aux_size); + } + + return 0; +} + +#ifdef HEVC_PIC_STRUCT_SUPPORT +static int process_pending_vframe(struct hevc_state_s *hevc, + struct PIC_s *pair_pic, unsigned char pair_frame_top_flag) +{ + struct vframe_s *vf; + + if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT) + hevc_print(hevc, 0, + "%s: pair_pic index 0x%x %s\n", + __func__, pair_pic->index, + pair_frame_top_flag ? + "top" : "bot"); + + if (kfifo_len(&hevc->pending_q) > 1) { + /* do not pending more than 1 frame */ + if (kfifo_get(&hevc->pending_q, &vf) == 0) { + hevc_print(hevc, 0, + "fatal error, no available buffer slot."); + return -1; + } + if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT) + hevc_print(hevc, 0, + "%s warning(1), vf=>display_q: (index 0x%x)\n", + __func__, vf->index); + hevc->vf_pre_count++; + kfifo_put(&hevc->display_q, (const struct vframe_s *)vf); + } + + if (kfifo_peek(&hevc->pending_q, &vf)) { + if (pair_pic == NULL || pair_pic->vf_ref <= 0) { + /* + *if pair_pic is recycled (pair_pic->vf_ref <= 0), + *do not use it + */ + if (kfifo_get(&hevc->pending_q, &vf) == 0) { + hevc_print(hevc, 0, + "fatal error, no available buffer slot."); + return -1; + } + if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT) + hevc_print(hevc, 0, + "%s warning(2), vf=>display_q: (index 0x%x)\n", + __func__, vf->index); + if (vf) { + hevc->vf_pre_count++; + kfifo_put(&hevc->display_q, + (const struct vframe_s *)vf); + } + } else if ((!pair_frame_top_flag) && + (((vf->index >> 8) & 0xff) == 0xff)) { + if (kfifo_get(&hevc->pending_q, &vf) == 0) { + hevc_print(hevc, 0, + "fatal error, no available buffer slot."); + return -1; + } + if (vf) { + vf->type = VIDTYPE_PROGRESSIVE + | VIDTYPE_VIU_NV21; + vf->index &= 0xff; + vf->index |= (pair_pic->index << 8); + vf->canvas1Addr = spec2canvas(pair_pic); + pair_pic->vf_ref++; + kfifo_put(&hevc->display_q, + (const struct vframe_s *)vf); + hevc->vf_pre_count++; + if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT) + hevc_print(hevc, 0, + "%s vf => display_q: (index 0x%x)\n", + __func__, vf->index); + } + } else if (pair_frame_top_flag && + ((vf->index & 0xff) == 0xff)) { + if (kfifo_get(&hevc->pending_q, &vf) == 0) { + hevc_print(hevc, 0, + "fatal error, no available buffer slot."); + return -1; + } + if (vf) { + vf->type = VIDTYPE_PROGRESSIVE + | VIDTYPE_VIU_NV21; + vf->index &= 0xff00; + vf->index |= pair_pic->index; + vf->canvas0Addr = spec2canvas(pair_pic); + pair_pic->vf_ref++; + kfifo_put(&hevc->display_q, + (const struct vframe_s *)vf); + hevc->vf_pre_count++; + if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT) + hevc_print(hevc, 0, + "%s vf => display_q: (index 0x%x)\n", + __func__, vf->index); + } + } + } + return 0; +} +#endif +static void update_vf_memhandle(struct hevc_state_s *hevc, + struct vframe_s *vf, struct PIC_s *pic) +{ + if (pic->index < 0) { + vf->mem_handle = NULL; + vf->mem_head_handle = NULL; + } else if (vf->type & VIDTYPE_SCATTER) { + vf->mem_handle = + decoder_mmu_box_get_mem_handle( + hevc->mmu_box, pic->index); + vf->mem_head_handle = + decoder_bmmu_box_get_mem_handle( + hevc->bmmu_box, VF_BUFFER_IDX(pic->BUF_index)); + } else { + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + hevc->bmmu_box, VF_BUFFER_IDX(pic->BUF_index)); + vf->mem_head_handle = NULL; + /*vf->mem_head_handle = + decoder_bmmu_box_get_mem_handle( + hevc->bmmu_box, VF_BUFFER_IDX(BUF_index));*/ + } + return; +} +static int prepare_display_buf(struct hevc_state_s *hevc, struct PIC_s *pic) +{ +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + struct vdec_s *vdec = hw_to_vdec(hevc); +#endif + struct vframe_s *vf = NULL; + int stream_offset = pic->stream_offset; + unsigned short slice_type = pic->slice_type; + if (force_disp_pic_index & 0x100) { + /*recycle directly*/ + pic->output_ready = 0; + return -1; + } + if (kfifo_get(&hevc->newframe_q, &vf) == 0) { + hevc_print(hevc, 0, + "fatal error, no available buffer slot."); + return -1; + } + display_frame_count[hevc->index]++; + if (vf) { + /*hevc_print(hevc, PRINT_FLAG_VDEC_STATUS, + "%s: pic index 0x%x\n", + __func__, pic->index);*/ + +#ifdef MULTI_INSTANCE_SUPPORT + if (vdec_frame_based(hw_to_vdec(hevc))) { + vf->pts = pic->pts; + vf->pts_us64 = pic->pts64; + } + /* if (pts_lookup_offset(PTS_TYPE_VIDEO, + stream_offset, &vf->pts, 0) != 0) { */ +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + else if (vdec->master == NULL) { +#else + else { +#endif +#endif + hevc_print(hevc, H265_DEBUG_OUT_PTS, + "call pts_lookup_offset_us64(0x%x)\n", + stream_offset); + if (pts_lookup_offset_us64 + (PTS_TYPE_VIDEO, stream_offset, &vf->pts, 0, + &vf->pts_us64) != 0) { +#ifdef DEBUG_PTS + hevc->pts_missed++; +#endif + vf->pts = 0; + vf->pts_us64 = 0; + } +#ifdef DEBUG_PTS + else + hevc->pts_hit++; +#endif +#ifdef MULTI_INSTANCE_SUPPORT +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + } else { + vf->pts = 0; + vf->pts_us64 = 0; + } +#else + } +#endif +#endif + if (pts_unstable && (hevc->frame_dur > 0)) + hevc->pts_mode = PTS_NONE_REF_USE_DURATION; + + if ((hevc->pts_mode == PTS_NORMAL) && (vf->pts != 0) + && hevc->get_frame_dur) { + int pts_diff = (int)vf->pts - hevc->last_lookup_pts; + + if (pts_diff < 0) { + hevc->pts_mode_switching_count++; + hevc->pts_mode_recovery_count = 0; + + if (hevc->pts_mode_switching_count >= + PTS_MODE_SWITCHING_THRESHOLD) { + hevc->pts_mode = + PTS_NONE_REF_USE_DURATION; + hevc_print(hevc, 0, + "HEVC: switch to n_d mode.\n"); + } + + } else { + int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD; + + hevc->pts_mode_recovery_count++; + if (hevc->pts_mode_recovery_count > p) { + hevc->pts_mode_switching_count = 0; + hevc->pts_mode_recovery_count = 0; + } + } + } + + if (vf->pts != 0) + hevc->last_lookup_pts = vf->pts; + + if ((hevc->pts_mode == PTS_NONE_REF_USE_DURATION) + && (slice_type != 2)) + vf->pts = hevc->last_pts + DUR2PTS(hevc->frame_dur); + hevc->last_pts = vf->pts; + + if (vf->pts_us64 != 0) + hevc->last_lookup_pts_us64 = vf->pts_us64; + + if ((hevc->pts_mode == PTS_NONE_REF_USE_DURATION) + && (slice_type != 2)) { + vf->pts_us64 = + hevc->last_pts_us64 + + (DUR2PTS(hevc->frame_dur) * 100 / 9); + } + hevc->last_pts_us64 = vf->pts_us64; + if ((get_dbg_flag(hevc) & H265_DEBUG_OUT_PTS) != 0) { + hevc_print(hevc, 0, + "H265 dec out pts: vf->pts=%d, vf->pts_us64 = %lld\n", + vf->pts, vf->pts_us64); + } + + /* + *vf->index: + *(1) vf->type is VIDTYPE_PROGRESSIVE + * and vf->canvas0Addr != vf->canvas1Addr, + * vf->index[7:0] is the index of top pic + * vf->index[15:8] is the index of bot pic + *(2) other cases, + * only vf->index[7:0] is used + * vf->index[15:8] == 0xff + */ + vf->index = 0xff00 | pic->index; +#if 1 +/*SUPPORT_10BIT*/ + if (pic->double_write_mode & 0x10) { + /* double write only */ + vf->compBodyAddr = 0; + vf->compHeadAddr = 0; + } else { + + if (hevc->mmu_enable) { + vf->compBodyAddr = 0; + vf->compHeadAddr = pic->header_adr; + } else { + vf->compBodyAddr = pic->mc_y_adr; /*body adr*/ + vf->compHeadAddr = pic->mc_y_adr + + pic->losless_comp_body_size; + vf->mem_head_handle = NULL; + } + + /*head adr*/ + vf->canvas0Addr = vf->canvas1Addr = 0; + } + if (pic->double_write_mode) { + vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD; + vf->type |= VIDTYPE_VIU_NV21; + if (pic->double_write_mode == 3) { + vf->type |= VIDTYPE_COMPRESS; + if (hevc->mmu_enable) + vf->type |= VIDTYPE_SCATTER; + } +#ifdef MULTI_INSTANCE_SUPPORT + if (hevc->m_ins_flag && + (get_dbg_flag(hevc) + & H265_CFG_CANVAS_IN_DECODE) == 0) { + vf->canvas0Addr = vf->canvas1Addr = -1; + vf->plane_num = 2; + vf->canvas0_config[0] = + pic->canvas_config[0]; + vf->canvas0_config[1] = + pic->canvas_config[1]; + + vf->canvas1_config[0] = + pic->canvas_config[0]; + vf->canvas1_config[1] = + pic->canvas_config[1]; + + } else +#endif + vf->canvas0Addr = vf->canvas1Addr + = spec2canvas(pic); + } else { + vf->canvas0Addr = vf->canvas1Addr = 0; + vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD; + if (hevc->mmu_enable) + vf->type |= VIDTYPE_SCATTER; + } + vf->compWidth = pic->width; + vf->compHeight = pic->height; + update_vf_memhandle(hevc, vf, pic); + switch (pic->bit_depth_luma) { + case 9: + vf->bitdepth = BITDEPTH_Y9; + break; + case 10: + vf->bitdepth = BITDEPTH_Y10; + break; + default: + vf->bitdepth = BITDEPTH_Y8; + break; + } + switch (pic->bit_depth_chroma) { + case 9: + vf->bitdepth |= (BITDEPTH_U9 | BITDEPTH_V9); + break; + case 10: + vf->bitdepth |= (BITDEPTH_U10 | BITDEPTH_V10); + break; + default: + vf->bitdepth |= (BITDEPTH_U8 | BITDEPTH_V8); + break; + } + if ((vf->type & VIDTYPE_COMPRESS) == 0) + vf->bitdepth = + BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8; + if (pic->mem_saving_mode == 1) + vf->bitdepth |= BITDEPTH_SAVING_MODE; +#else + vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD; + vf->type |= VIDTYPE_VIU_NV21; + vf->canvas0Addr = vf->canvas1Addr = spec2canvas(pic); +#endif + set_frame_info(hevc, vf, pic); + /* if((vf->width!=pic->width)||(vf->height!=pic->height)) */ + /* hevc_print(hevc, 0, + "aaa: %d/%d, %d/%d\n", + vf->width,vf->height, pic->width, pic->height); */ + vf->width = pic->width; + vf->height = pic->height; + + if (force_w_h != 0) { + vf->width = (force_w_h >> 16) & 0xffff; + vf->height = force_w_h & 0xffff; + } + if (force_fps & 0x100) { + u32 rate = force_fps & 0xff; + + if (rate) + vf->duration = 96000/rate; + else + vf->duration = 0; + } + if (force_fps & 0x200) { + vf->pts = 0; + vf->pts_us64 = 0; + } + /* + * !!! to do ... + * need move below code to get_new_pic(), + * hevc->xxx can only be used by current decoded pic + */ + if (hevc->param.p.conformance_window_flag && + (get_dbg_flag(hevc) & + H265_DEBUG_IGNORE_CONFORMANCE_WINDOW) == 0) { + unsigned int SubWidthC, SubHeightC; + + switch (hevc->param.p.chroma_format_idc) { + case 1: + SubWidthC = 2; + SubHeightC = 2; + break; + case 2: + SubWidthC = 2; + SubHeightC = 1; + break; + default: + SubWidthC = 1; + SubHeightC = 1; + break; + } + vf->width -= SubWidthC * + (hevc->param.p.conf_win_left_offset + + hevc->param.p.conf_win_right_offset); + vf->height -= SubHeightC * + (hevc->param.p.conf_win_top_offset + + hevc->param.p.conf_win_bottom_offset); + + vf->compWidth -= SubWidthC * + (hevc->param.p.conf_win_left_offset + + hevc->param.p.conf_win_right_offset); + vf->compHeight -= SubHeightC * + (hevc->param.p.conf_win_top_offset + + hevc->param.p.conf_win_bottom_offset); + + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + hevc_print(hevc, 0, + "conformance_window %d, %d, %d, %d, %d => cropped width %d, height %d com_w %d com_h %d\n", + hevc->param.p.chroma_format_idc, + hevc->param.p.conf_win_left_offset, + hevc->param.p.conf_win_right_offset, + hevc->param.p.conf_win_top_offset, + hevc->param.p.conf_win_bottom_offset, + vf->width, vf->height, vf->compWidth, vf->compHeight); + } + + vf->width = vf->width / + get_double_write_ratio(hevc, pic->double_write_mode); + vf->height = vf->height / + get_double_write_ratio(hevc, pic->double_write_mode); +#ifdef HEVC_PIC_STRUCT_SUPPORT + if (pic->pic_struct == 3 || pic->pic_struct == 4) { + struct vframe_s *vf2; + + if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT) + hevc_print(hevc, 0, + "pic_struct = %d index 0x%x\n", + pic->pic_struct, + pic->index); + + if (kfifo_get(&hevc->newframe_q, &vf2) == 0) { + hevc_print(hevc, 0, + "fatal error, no available buffer slot."); + return -1; + } + pic->vf_ref = 2; + vf->duration = vf->duration>>1; + memcpy(vf2, vf, sizeof(struct vframe_s)); + + if (pic->pic_struct == 3) { + vf->type = VIDTYPE_INTERLACE_TOP + | VIDTYPE_VIU_NV21; + vf2->type = VIDTYPE_INTERLACE_BOTTOM + | VIDTYPE_VIU_NV21; + } else { + vf->type = VIDTYPE_INTERLACE_BOTTOM + | VIDTYPE_VIU_NV21; + vf2->type = VIDTYPE_INTERLACE_TOP + | VIDTYPE_VIU_NV21; + } + hevc->vf_pre_count++; + kfifo_put(&hevc->display_q, + (const struct vframe_s *)vf); + hevc->vf_pre_count++; + kfifo_put(&hevc->display_q, + (const struct vframe_s *)vf2); + } else if (pic->pic_struct == 5 + || pic->pic_struct == 6) { + struct vframe_s *vf2, *vf3; + + if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT) + hevc_print(hevc, 0, + "pic_struct = %d index 0x%x\n", + pic->pic_struct, + pic->index); + + if (kfifo_get(&hevc->newframe_q, &vf2) == 0) { + hevc_print(hevc, 0, + "fatal error, no available buffer slot."); + return -1; + } + if (kfifo_get(&hevc->newframe_q, &vf3) == 0) { + hevc_print(hevc, 0, + "fatal error, no available buffer slot."); + return -1; + } + pic->vf_ref = 3; + vf->duration = vf->duration/3; + memcpy(vf2, vf, sizeof(struct vframe_s)); + memcpy(vf3, vf, sizeof(struct vframe_s)); + + if (pic->pic_struct == 5) { + vf->type = VIDTYPE_INTERLACE_TOP + | VIDTYPE_VIU_NV21; + vf2->type = VIDTYPE_INTERLACE_BOTTOM + | VIDTYPE_VIU_NV21; + vf3->type = VIDTYPE_INTERLACE_TOP + | VIDTYPE_VIU_NV21; + } else { + vf->type = VIDTYPE_INTERLACE_BOTTOM + | VIDTYPE_VIU_NV21; + vf2->type = VIDTYPE_INTERLACE_TOP + | VIDTYPE_VIU_NV21; + vf3->type = VIDTYPE_INTERLACE_BOTTOM + | VIDTYPE_VIU_NV21; + } + hevc->vf_pre_count++; + kfifo_put(&hevc->display_q, + (const struct vframe_s *)vf); + hevc->vf_pre_count++; + kfifo_put(&hevc->display_q, + (const struct vframe_s *)vf2); + hevc->vf_pre_count++; + kfifo_put(&hevc->display_q, + (const struct vframe_s *)vf3); + + } else if (pic->pic_struct == 9 + || pic->pic_struct == 10) { + if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT) + hevc_print(hevc, 0, + "pic_struct = %d index 0x%x\n", + pic->pic_struct, + pic->index); + + pic->vf_ref = 1; + /* process previous pending vf*/ + process_pending_vframe(hevc, + pic, (pic->pic_struct == 9)); + + /* process current vf */ + kfifo_put(&hevc->pending_q, + (const struct vframe_s *)vf); + vf->height <<= 1; + if (pic->pic_struct == 9) { + vf->type = VIDTYPE_INTERLACE_TOP + | VIDTYPE_VIU_NV21 | VIDTYPE_VIU_FIELD; + process_pending_vframe(hevc, + hevc->pre_bot_pic, 0); + } else { + vf->type = VIDTYPE_INTERLACE_BOTTOM | + VIDTYPE_VIU_NV21 | VIDTYPE_VIU_FIELD; + vf->index = (pic->index << 8) | 0xff; + process_pending_vframe(hevc, + hevc->pre_top_pic, 1); + } + + /**/ + if (pic->pic_struct == 9) + hevc->pre_top_pic = pic; + else + hevc->pre_bot_pic = pic; + + } else if (pic->pic_struct == 11 + || pic->pic_struct == 12) { + if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT) + hevc_print(hevc, 0, + "pic_struct = %d index 0x%x\n", + pic->pic_struct, + pic->index); + pic->vf_ref = 1; + /* process previous pending vf*/ + process_pending_vframe(hevc, pic, + (pic->pic_struct == 11)); + + /* put current into pending q */ + vf->height <<= 1; + if (pic->pic_struct == 11) + vf->type = VIDTYPE_INTERLACE_TOP | + VIDTYPE_VIU_NV21 | VIDTYPE_VIU_FIELD; + else { + vf->type = VIDTYPE_INTERLACE_BOTTOM | + VIDTYPE_VIU_NV21 | VIDTYPE_VIU_FIELD; + vf->index = (pic->index << 8) | 0xff; + } + kfifo_put(&hevc->pending_q, + (const struct vframe_s *)vf); + + /**/ + if (pic->pic_struct == 11) + hevc->pre_top_pic = pic; + else + hevc->pre_bot_pic = pic; + + } else { + pic->vf_ref = 1; + + if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT) + hevc_print(hevc, 0, + "pic_struct = %d index 0x%x\n", + pic->pic_struct, + pic->index); + + switch (pic->pic_struct) { + case 7: + vf->duration <<= 1; + break; + case 8: + vf->duration = vf->duration * 3; + break; + case 1: + vf->height <<= 1; + vf->type = VIDTYPE_INTERLACE_TOP | + VIDTYPE_VIU_NV21 | VIDTYPE_VIU_FIELD; + process_pending_vframe(hevc, pic, 1); + hevc->pre_top_pic = pic; + break; + case 2: + vf->height <<= 1; + vf->type = VIDTYPE_INTERLACE_BOTTOM + | VIDTYPE_VIU_NV21 + | VIDTYPE_VIU_FIELD; + process_pending_vframe(hevc, pic, 0); + hevc->pre_bot_pic = pic; + break; + } + hevc->vf_pre_count++; + kfifo_put(&hevc->display_q, + (const struct vframe_s *)vf); + } +#else + vf->type_original = vf->type; + pic->vf_ref = 1; + hevc->vf_pre_count++; + kfifo_put(&hevc->display_q, (const struct vframe_s *)vf); + + if (get_dbg_flag(hevc) & H265_DEBUG_PIC_STRUCT) + hevc_print(hevc, 0, + "%s(type %d index 0x%x poc %d/%d) pts(%d,%d) dur %d\n", + __func__, vf->type, vf->index, + get_pic_poc(hevc, vf->index & 0xff), + get_pic_poc(hevc, (vf->index >> 8) & 0xff), + vf->pts, vf->pts_us64, + vf->duration); +#endif +#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + /*count info*/ + vdec_count_info(gvs, 0, stream_offset); +#endif + vf_notify_receiver(hevc->provider_name, + VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL); + } + + return 0; +} + +static void process_nal_sei(struct hevc_state_s *hevc, + int payload_type, int payload_size) +{ + unsigned short data; + + if (get_dbg_flag(hevc) & H265_DEBUG_PRINT_SEI) + hevc_print(hevc, 0, + "\tsei message: payload_type = 0x%02x, payload_size = 0x%02x\n", + payload_type, payload_size); + + if (payload_type == 137) { + int i, j; + /* MASTERING_DISPLAY_COLOUR_VOLUME */ + if (payload_size >= 24) { + if (get_dbg_flag(hevc) & H265_DEBUG_PRINT_SEI) + hevc_print(hevc, 0, + "\tsei MASTERING_DISPLAY_COLOUR_VOLUME available\n"); + for (i = 0; i < 3; i++) { + for (j = 0; j < 2; j++) { + data = + (READ_HREG(HEVC_SHIFTED_DATA) >> 16); + hevc->primaries[i][j] = data; + WRITE_HREG(HEVC_SHIFT_COMMAND, + (1<<7)|16); + if (get_dbg_flag(hevc) & + H265_DEBUG_PRINT_SEI) + hevc_print(hevc, 0, + "\t\tprimaries[%1d][%1d] = %04x\n", + i, j, hevc->primaries[i][j]); + } + } + for (i = 0; i < 2; i++) { + data = (READ_HREG(HEVC_SHIFTED_DATA) >> 16); + hevc->white_point[i] = data; + WRITE_HREG(HEVC_SHIFT_COMMAND, (1<<7)|16); + if (get_dbg_flag(hevc) & H265_DEBUG_PRINT_SEI) + hevc_print(hevc, 0, + "\t\twhite_point[%1d] = %04x\n", + i, hevc->white_point[i]); + } + for (i = 0; i < 2; i++) { + data = (READ_HREG(HEVC_SHIFTED_DATA) >> 16); + hevc->luminance[i] = data << 16; + WRITE_HREG(HEVC_SHIFT_COMMAND, + (1<<7)|16); + data = + (READ_HREG(HEVC_SHIFTED_DATA) >> 16); + hevc->luminance[i] |= data; + WRITE_HREG(HEVC_SHIFT_COMMAND, + (1<<7)|16); + if (get_dbg_flag(hevc) & + H265_DEBUG_PRINT_SEI) + hevc_print(hevc, 0, + "\t\tluminance[%1d] = %08x\n", + i, hevc->luminance[i]); + } + hevc->sei_present_flag |= SEI_MASTER_DISPLAY_COLOR_MASK; + } + payload_size -= 24; + while (payload_size > 0) { + data = (READ_HREG(HEVC_SHIFTED_DATA) >> 24); + payload_size--; + WRITE_HREG(HEVC_SHIFT_COMMAND, (1<<7)|8); + hevc_print(hevc, 0, "\t\tskip byte %02x\n", data); + } + } +} + +static int hevc_recover(struct hevc_state_s *hevc) +{ + int ret = -1; + u32 rem; + u64 shift_byte_count64; + unsigned int hevc_shift_byte_count; + unsigned int hevc_stream_start_addr; + unsigned int hevc_stream_end_addr; + unsigned int hevc_stream_rd_ptr; + unsigned int hevc_stream_wr_ptr; + unsigned int hevc_stream_control; + unsigned int hevc_stream_fifo_ctl; + unsigned int hevc_stream_buf_size; + + mutex_lock(&vh265_mutex); +#if 0 + for (i = 0; i < (hevc->debug_ptr_size / 2); i += 4) { + int ii; + + for (ii = 0; ii < 4; ii++) + hevc_print(hevc, 0, + "%04x ", hevc->debug_ptr[i + 3 - ii]); + if (((i + ii) & 0xf) == 0) + hevc_print(hevc, 0, "\n"); + } +#endif +#define ES_VID_MAN_RD_PTR (1<<0) + if (!hevc->init_flag) { + hevc_print(hevc, 0, "h265 has stopped, recover return!\n"); + mutex_unlock(&vh265_mutex); + return ret; + } + amhevc_stop(); + msleep(20); + ret = 0; + /* reset */ + WRITE_PARSER_REG(PARSER_VIDEO_RP, READ_VREG(HEVC_STREAM_RD_PTR)); + SET_PARSER_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR); + + hevc_stream_start_addr = READ_VREG(HEVC_STREAM_START_ADDR); + hevc_stream_end_addr = READ_VREG(HEVC_STREAM_END_ADDR); + hevc_stream_rd_ptr = READ_VREG(HEVC_STREAM_RD_PTR); + hevc_stream_wr_ptr = READ_VREG(HEVC_STREAM_WR_PTR); + hevc_stream_control = READ_VREG(HEVC_STREAM_CONTROL); + hevc_stream_fifo_ctl = READ_VREG(HEVC_STREAM_FIFO_CTL); + hevc_stream_buf_size = hevc_stream_end_addr - hevc_stream_start_addr; + + /* HEVC streaming buffer will reset and restart + * from current hevc_stream_rd_ptr position + */ + /* calculate HEVC_SHIFT_BYTE_COUNT value with the new position. */ + hevc_shift_byte_count = READ_VREG(HEVC_SHIFT_BYTE_COUNT); + if ((hevc->shift_byte_count_lo & (1 << 31)) + && ((hevc_shift_byte_count & (1 << 31)) == 0)) + hevc->shift_byte_count_hi++; + + hevc->shift_byte_count_lo = hevc_shift_byte_count; + shift_byte_count64 = ((u64)(hevc->shift_byte_count_hi) << 32) | + hevc->shift_byte_count_lo; + div_u64_rem(shift_byte_count64, hevc_stream_buf_size, &rem); + shift_byte_count64 -= rem; + shift_byte_count64 += hevc_stream_rd_ptr - hevc_stream_start_addr; + + if (rem > (hevc_stream_rd_ptr - hevc_stream_start_addr)) + shift_byte_count64 += hevc_stream_buf_size; + + hevc->shift_byte_count_lo = (u32)shift_byte_count64; + hevc->shift_byte_count_hi = (u32)(shift_byte_count64 >> 32); + + WRITE_VREG(DOS_SW_RESET3, + /* (1<<2)| */ + (1 << 3) | (1 << 4) | (1 << 8) | + (1 << 11) | (1 << 12) | (1 << 14) + | (1 << 15) | (1 << 17) | (1 << 18) | (1 << 19)); + WRITE_VREG(DOS_SW_RESET3, 0); + + WRITE_VREG(HEVC_STREAM_START_ADDR, hevc_stream_start_addr); + WRITE_VREG(HEVC_STREAM_END_ADDR, hevc_stream_end_addr); + WRITE_VREG(HEVC_STREAM_RD_PTR, hevc_stream_rd_ptr); + WRITE_VREG(HEVC_STREAM_WR_PTR, hevc_stream_wr_ptr); + WRITE_VREG(HEVC_STREAM_CONTROL, hevc_stream_control); + WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, hevc->shift_byte_count_lo); + WRITE_VREG(HEVC_STREAM_FIFO_CTL, hevc_stream_fifo_ctl); + + hevc_config_work_space_hw(hevc); + decoder_hw_reset(); + + hevc->have_vps = 0; + hevc->have_sps = 0; + hevc->have_pps = 0; + + hevc->have_valid_start_slice = 0; + + if (get_double_write_mode(hevc) & 0x10) + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, + 0x1 << 31 /*/Enable NV21 reference read mode for MC*/ + ); + + WRITE_VREG(HEVC_WAIT_FLAG, 1); + /* clear mailbox interrupt */ + WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1); + /* enable mailbox interrupt */ + WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1); + /* disable PSCALE for hardware sharing */ + WRITE_VREG(HEVC_PSCALE_CTRL, 0); + + CLEAR_PARSER_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR); + + WRITE_VREG(DEBUG_REG1, 0x0); + + if ((error_handle_policy & 1) == 0) { + if ((error_handle_policy & 4) == 0) { + /* ucode auto mode, and do not check vps/sps/pps/idr */ + WRITE_VREG(NAL_SEARCH_CTL, + 0xc); + } else { + WRITE_VREG(NAL_SEARCH_CTL, 0x1);/* manual parser NAL */ + } + } else { + WRITE_VREG(NAL_SEARCH_CTL, 0x1);/* manual parser NAL */ + } + + if (get_dbg_flag(hevc) & H265_DEBUG_NO_EOS_SEARCH_DONE) + WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x10000); + WRITE_VREG(NAL_SEARCH_CTL, + READ_VREG(NAL_SEARCH_CTL) + | ((parser_sei_enable & 0x7) << 17)); +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + WRITE_VREG(NAL_SEARCH_CTL, + READ_VREG(NAL_SEARCH_CTL) | + ((parser_dolby_vision_enable & 0x1) << 20)); +#endif + config_decode_mode(hevc); + WRITE_VREG(DECODE_STOP_POS, udebug_flag); + + /* if (amhevc_loadmc(vh265_mc) < 0) { */ + /* amhevc_disable(); */ + /* return -EBUSY; */ + /* } */ +#if 0 + for (i = 0; i < (hevc->debug_ptr_size / 2); i += 4) { + int ii; + + for (ii = 0; ii < 4; ii++) { + /* hevc->debug_ptr[i+3-ii]=ttt++; */ + hevc_print(hevc, 0, + "%04x ", hevc->debug_ptr[i + 3 - ii]); + } + if (((i + ii) & 0xf) == 0) + hevc_print(hevc, 0, "\n"); + } +#endif + init_pic_list_hw(hevc); + + hevc_print(hevc, 0, "%s HEVC_SHIFT_BYTE_COUNT=0x%x\n", __func__, + READ_VREG(HEVC_SHIFT_BYTE_COUNT)); + + amhevc_start(); + + /* skip, search next start code */ + WRITE_VREG(HEVC_WAIT_FLAG, READ_VREG(HEVC_WAIT_FLAG) & (~0x2)); + hevc->skip_flag = 1; +#ifdef ERROR_HANDLE_DEBUG + if (dbg_nal_skip_count & 0x20000) { + dbg_nal_skip_count &= ~0x20000; + mutex_unlock(&vh265_mutex); + return ret; + } +#endif + WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE); + /* Interrupt Amrisc to excute */ + WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ); +#ifdef MULTI_INSTANCE_SUPPORT + if (!hevc->m_ins_flag) +#endif + hevc->first_pic_after_recover = 1; + mutex_unlock(&vh265_mutex); + return ret; +} + +static void dump_aux_buf(struct hevc_state_s *hevc) +{ + int i; + unsigned short *aux_adr = + (unsigned short *) + hevc->aux_addr; + unsigned int aux_size = + (READ_VREG(HEVC_AUX_DATA_SIZE) + >> 16) << 4; + + if (hevc->prefix_aux_size > 0) { + hevc_print(hevc, 0, + "prefix aux: (size %d)\n", + aux_size); + for (i = 0; i < + (aux_size >> 1); i++) { + hevc_print_cont(hevc, 0, + "%04x ", + *(aux_adr + i)); + if (((i + 1) & 0xf) + == 0) + hevc_print_cont(hevc, + 0, "\n"); + } + } + if (hevc->suffix_aux_size > 0) { + aux_adr = (unsigned short *) + (hevc->aux_addr + + hevc->prefix_aux_size); + aux_size = + (READ_VREG(HEVC_AUX_DATA_SIZE) & 0xffff) + << 4; + hevc_print(hevc, 0, + "suffix aux: (size %d)\n", + aux_size); + for (i = 0; i < + (aux_size >> 1); i++) { + hevc_print_cont(hevc, 0, + "%04x ", *(aux_adr + i)); + if (((i + 1) & 0xf) == 0) + hevc_print_cont(hevc, 0, "\n"); + } + } +} + +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION +static void dolby_get_meta(struct hevc_state_s *hevc) +{ + struct vdec_s *vdec = hw_to_vdec(hevc); + dma_sync_single_for_cpu( + amports_get_dma_device(), + hevc->aux_phy_addr, + hevc->prefix_aux_size + hevc->suffix_aux_size, + DMA_FROM_DEVICE); + if (get_dbg_flag(hevc) & + H265_DEBUG_BUFMGR_MORE) + dump_aux_buf(hevc); + if (vdec->dolby_meta_with_el || vdec->slave) { + set_aux_data(hevc, + hevc->cur_pic, 0, 0); + } else if (vdec->master) { + struct hevc_state_s *hevc_ba = + (struct hevc_state_s *) + vdec->master->private; + /*do not use hevc_ba*/ + set_aux_data(hevc, + hevc_ba->cur_pic, + 0, 1); + set_aux_data(hevc, + hevc->cur_pic, 0, 2); + } +} +#endif + +static void read_decode_info(struct hevc_state_s *hevc) +{ + uint32_t decode_info = + READ_HREG(HEVC_DECODE_INFO); + hevc->start_decoding_flag |= + (decode_info & 0xff); + hevc->rps_set_id = (decode_info >> 8) & 0xff; +} + +static irqreturn_t vh265_isr_thread_fn(int irq, void *data) +{ + struct hevc_state_s *hevc = (struct hevc_state_s *) data; + unsigned int dec_status = hevc->dec_status; + int i, ret; +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + struct vdec_s *vdec = hw_to_vdec(hevc); +#endif + if (hevc->eos) + return IRQ_HANDLED; + if ( +#ifdef MULTI_INSTANCE_SUPPORT + (!hevc->m_ins_flag) && +#endif + hevc->error_flag == 1) { + if ((error_handle_policy & 0x10) == 0) { + if (hevc->cur_pic) { + int current_lcu_idx = + READ_VREG(HEVC_PARSER_LCU_START) + & 0xffffff; + if (current_lcu_idx < + ((hevc->lcu_x_num*hevc->lcu_y_num)-1)) + hevc->cur_pic->error_mark = 1; + + } + } + if ((error_handle_policy & 1) == 0) { + hevc->error_skip_nal_count = 1; + /* manual search nal, skip error_skip_nal_count + * of nal and trigger the HEVC_NAL_SEARCH_DONE irq + */ + WRITE_VREG(NAL_SEARCH_CTL, + (error_skip_nal_count << 4) | 0x1); + } else { + hevc->error_skip_nal_count = error_skip_nal_count; + WRITE_VREG(NAL_SEARCH_CTL, 0x1);/* manual parser NAL */ + } + if ((get_dbg_flag(hevc) & H265_DEBUG_NO_EOS_SEARCH_DONE) +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + || vdec->master + || vdec->slave +#endif + ) { + WRITE_VREG(NAL_SEARCH_CTL, + READ_VREG(NAL_SEARCH_CTL) | 0x10000); + } + WRITE_VREG(NAL_SEARCH_CTL, + READ_VREG(NAL_SEARCH_CTL) + | ((parser_sei_enable & 0x7) << 17)); +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + WRITE_VREG(NAL_SEARCH_CTL, + READ_VREG(NAL_SEARCH_CTL) | + ((parser_dolby_vision_enable & 0x1) << 20)); +#endif + config_decode_mode(hevc); + /* search new nal */ + WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE); + /* Interrupt Amrisc to excute */ + WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ); + + /* hevc_print(hevc, 0, + *"%s: error handle\n", __func__); + */ + hevc->error_flag = 2; + return IRQ_HANDLED; + } else if ( +#ifdef MULTI_INSTANCE_SUPPORT + (!hevc->m_ins_flag) && +#endif + hevc->error_flag == 3) { + hevc_print(hevc, 0, "error_flag=3, hevc_recover\n"); + hevc_recover(hevc); + hevc->error_flag = 0; + + if ((error_handle_policy & 0x10) == 0) { + if (hevc->cur_pic) { + int current_lcu_idx = + READ_VREG(HEVC_PARSER_LCU_START) + & 0xffffff; + if (current_lcu_idx < + ((hevc->lcu_x_num*hevc->lcu_y_num)-1)) + hevc->cur_pic->error_mark = 1; + + } + } + if ((error_handle_policy & 1) == 0) { + /* need skip some data when + * error_flag of 3 is triggered, + */ + /* to avoid hevc_recover() being called + * for many times at the same bitstream position + */ + hevc->error_skip_nal_count = 1; + /* manual search nal, skip error_skip_nal_count + * of nal and trigger the HEVC_NAL_SEARCH_DONE irq + */ + WRITE_VREG(NAL_SEARCH_CTL, + (error_skip_nal_count << 4) | 0x1); + } + + if ((error_handle_policy & 0x2) == 0) { + hevc->have_vps = 1; + hevc->have_sps = 1; + hevc->have_pps = 1; + } + return IRQ_HANDLED; + } + if (!hevc->m_ins_flag) { + i = READ_VREG(HEVC_SHIFT_BYTE_COUNT); + if ((hevc->shift_byte_count_lo & (1 << 31)) + && ((i & (1 << 31)) == 0)) + hevc->shift_byte_count_hi++; + hevc->shift_byte_count_lo = i; + } +#ifdef MULTI_INSTANCE_SUPPORT + if ((dec_status == HEVC_DECPIC_DATA_DONE || + dec_status == HEVC_FIND_NEXT_PIC_NAL || + dec_status == HEVC_FIND_NEXT_DVEL_NAL) + && (hevc->chunk)) { + hevc->cur_pic->pts = hevc->chunk->pts; + hevc->cur_pic->pts64 = hevc->chunk->pts64; + } + + if (dec_status == HEVC_DECODE_BUFEMPTY || + dec_status == HEVC_DECODE_BUFEMPTY2) { + if (hevc->m_ins_flag) { + read_decode_info(hevc); + if (vdec_frame_based(hw_to_vdec(hevc))) { + goto pic_done; + } else { + if ( +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + vdec->master || + vdec->slave || +#endif + (data_resend_policy & 0x1)) { + hevc->dec_result = DEC_RESULT_AGAIN; + amhevc_stop(); + restore_decode_state(hevc); + } else + hevc->dec_result = DEC_RESULT_GET_DATA; + } + reset_process_time(hevc); + vdec_schedule_work(&hevc->work); + } + return IRQ_HANDLED; + } else if ((dec_status == HEVC_SEARCH_BUFEMPTY) || + (dec_status == HEVC_NAL_DECODE_DONE) + ) { + if (hevc->m_ins_flag) { + read_decode_info(hevc); + if (vdec_frame_based(hw_to_vdec(hevc))) { + /*hevc->dec_result = DEC_RESULT_GET_DATA;*/ + goto pic_done; + } else { + hevc->dec_result = DEC_RESULT_AGAIN; + amhevc_stop(); + restore_decode_state(hevc); + } + + reset_process_time(hevc); + vdec_schedule_work(&hevc->work); + } + + return IRQ_HANDLED; + } else if (dec_status == HEVC_DECPIC_DATA_DONE) { + if (hevc->m_ins_flag) { +pic_done: + read_decode_info(hevc); + + hevc->decoded_poc = hevc->curr_POC; + hevc->decoding_pic = NULL; + hevc->dec_result = DEC_RESULT_DONE; + amhevc_stop(); + + reset_process_time(hevc); + vdec_schedule_work(&hevc->work); + } + + return IRQ_HANDLED; +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + } else if (dec_status == HEVC_FIND_NEXT_PIC_NAL || + dec_status == HEVC_FIND_NEXT_DVEL_NAL) { + if (hevc->m_ins_flag) { + unsigned char next_parser_type = + READ_HREG(CUR_NAL_UNIT_TYPE) & 0xff; + read_decode_info(hevc); + + if (vdec->slave && + dec_status == HEVC_FIND_NEXT_DVEL_NAL) { + /*cur is base, found enhance*/ + struct hevc_state_s *hevc_el = + (struct hevc_state_s *) + vdec->slave->private; + hevc->switch_dvlayer_flag = 1; + hevc->no_switch_dvlayer_count = 0; + hevc_el->start_parser_type = + next_parser_type; + hevc_print(hevc, H265_DEBUG_DV, + "switch (poc %d) to el\n", + hevc->cur_pic ? + hevc->cur_pic->POC : + INVALID_POC); + } else if (vdec->master && + dec_status == HEVC_FIND_NEXT_PIC_NAL) { + /*cur is enhance, found base*/ + struct hevc_state_s *hevc_ba = + (struct hevc_state_s *) + vdec->master->private; + hevc->switch_dvlayer_flag = 1; + hevc->no_switch_dvlayer_count = 0; + hevc_ba->start_parser_type = + next_parser_type; + hevc_print(hevc, H265_DEBUG_DV, + "switch (poc %d) to bl\n", + hevc->cur_pic ? + hevc->cur_pic->POC : + INVALID_POC); + } else { + hevc->switch_dvlayer_flag = 0; + hevc->start_parser_type = + next_parser_type; + hevc->no_switch_dvlayer_count++; + hevc_print(hevc, H265_DEBUG_DV, + "%s: no_switch_dvlayer_count = %d\n", + vdec->master ? "el" : "bl", + hevc->no_switch_dvlayer_count); + if (vdec->slave && + dolby_el_flush_th != 0 && + hevc->no_switch_dvlayer_count > + dolby_el_flush_th) { + struct hevc_state_s *hevc_el = + (struct hevc_state_s *) + vdec->slave->private; + struct PIC_s *el_pic; + check_pic_decoded_error(hevc_el, + hevc_el->pic_decoded_lcu_idx); + el_pic = get_pic_by_POC(hevc_el, + hevc_el->curr_POC); + hevc_el->curr_POC = INVALID_POC; + hevc_el->m_pocRandomAccess = MAX_INT; + flush_output(hevc_el, el_pic); + hevc_el->decoded_poc = INVALID_POC; /* + already call flush_output*/ + hevc_el->decoding_pic = NULL; + hevc->no_switch_dvlayer_count = 0; + if (get_dbg_flag(hevc) & H265_DEBUG_DV) + hevc_print(hevc, 0, + "no el anymore, flush_output el\n"); + } + } + hevc->decoded_poc = hevc->curr_POC; + hevc->decoding_pic = NULL; + hevc->dec_result = DEC_RESULT_DONE; + amhevc_stop(); + reset_process_time(hevc); + if (READ_VREG(HEVC_AUX_DATA_SIZE) != 0) + dolby_get_meta(hevc); + + vdec_schedule_work(&hevc->work); + } + + return IRQ_HANDLED; +#endif + } + +#endif + + if (dec_status == HEVC_SEI_DAT) { + if (!hevc->m_ins_flag) { + int payload_type = + READ_HREG(CUR_NAL_UNIT_TYPE) & 0xffff; + int payload_size = + (READ_HREG(CUR_NAL_UNIT_TYPE) >> 16) & 0xffff; + process_nal_sei(hevc, + payload_type, payload_size); + } + WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_SEI_DAT_DONE); + } else if (dec_status == HEVC_NAL_SEARCH_DONE) { + int naltype = READ_HREG(CUR_NAL_UNIT_TYPE); + int parse_type = HEVC_DISCARD_NAL; + + hevc->error_watchdog_count = 0; + hevc->error_skip_nal_wt_cnt = 0; +#ifdef MULTI_INSTANCE_SUPPORT + if (hevc->m_ins_flag) + reset_process_time(hevc); +#endif + if (slice_parse_begin > 0 && + get_dbg_flag(hevc) & H265_DEBUG_DISCARD_NAL) { + hevc_print(hevc, 0, + "nal type %d, discard %d\n", naltype, + slice_parse_begin); + if (naltype <= NAL_UNIT_CODED_SLICE_CRA) + slice_parse_begin--; + } + if (naltype == NAL_UNIT_EOS) { + struct PIC_s *pic; + + hevc_print(hevc, 0, "get NAL_UNIT_EOS, flush output\n"); +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + if ((vdec->master || vdec->slave) && + READ_VREG(HEVC_AUX_DATA_SIZE) != 0) { + if (hevc->decoding_pic) + dolby_get_meta(hevc); + } +#endif + check_pic_decoded_error(hevc, + hevc->pic_decoded_lcu_idx); + pic = get_pic_by_POC(hevc, hevc->curr_POC); + hevc->curr_POC = INVALID_POC; + /* add to fix RAP_B_Bossen_1 */ + hevc->m_pocRandomAccess = MAX_INT; + flush_output(hevc, pic); + WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_DISCARD_NAL); + /* Interrupt Amrisc to excute */ + WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ); +#ifdef MULTI_INSTANCE_SUPPORT + if (hevc->m_ins_flag) { + hevc->decoded_poc = INVALID_POC; /* + already call flush_output*/ + hevc->decoding_pic = NULL; + hevc->dec_result = DEC_RESULT_DONE; + amhevc_stop(); + + vdec_schedule_work(&hevc->work); + } +#endif + return IRQ_HANDLED; + } + + if ( +#ifdef MULTI_INSTANCE_SUPPORT + (!hevc->m_ins_flag) && +#endif + hevc->error_skip_nal_count > 0) { + hevc_print(hevc, 0, + "nal type %d, discard %d\n", naltype, + hevc->error_skip_nal_count); + hevc->error_skip_nal_count--; + if (hevc->error_skip_nal_count == 0) { + hevc_recover(hevc); + hevc->error_flag = 0; + if ((error_handle_policy & 0x2) == 0) { + hevc->have_vps = 1; + hevc->have_sps = 1; + hevc->have_pps = 1; + } + return IRQ_HANDLED; + } + } else if (naltype == NAL_UNIT_VPS) { + parse_type = HEVC_NAL_UNIT_VPS; + hevc->have_vps = 1; +#ifdef ERROR_HANDLE_DEBUG + if (dbg_nal_skip_flag & 1) + parse_type = HEVC_DISCARD_NAL; +#endif + } else if (hevc->have_vps) { + if (naltype == NAL_UNIT_SPS) { + parse_type = HEVC_NAL_UNIT_SPS; + hevc->have_sps = 1; +#ifdef ERROR_HANDLE_DEBUG + if (dbg_nal_skip_flag & 2) + parse_type = HEVC_DISCARD_NAL; +#endif + } else if (naltype == NAL_UNIT_PPS) { + parse_type = HEVC_NAL_UNIT_PPS; + hevc->have_pps = 1; +#ifdef ERROR_HANDLE_DEBUG + if (dbg_nal_skip_flag & 4) + parse_type = HEVC_DISCARD_NAL; +#endif + } else if (hevc->have_sps && hevc->have_pps) { + int seg = HEVC_NAL_UNIT_CODED_SLICE_SEGMENT; + + if ((naltype == NAL_UNIT_CODED_SLICE_IDR) || + (naltype == + NAL_UNIT_CODED_SLICE_IDR_N_LP) + || (naltype == + NAL_UNIT_CODED_SLICE_CRA) + || (naltype == + NAL_UNIT_CODED_SLICE_BLA) + || (naltype == + NAL_UNIT_CODED_SLICE_BLANT) + || (naltype == + NAL_UNIT_CODED_SLICE_BLA_N_LP) + ) { + if (slice_parse_begin > 0) { + hevc_print(hevc, 0, + "discard %d, for debugging\n", + slice_parse_begin); + slice_parse_begin--; + } else { + parse_type = seg; + } + hevc->have_valid_start_slice = 1; + } else if (naltype <= + NAL_UNIT_CODED_SLICE_CRA + && (hevc->have_valid_start_slice + || (hevc->PB_skip_mode != 3))) { + if (slice_parse_begin > 0) { + hevc_print(hevc, 0, + "discard %d, dd\n", + slice_parse_begin); + slice_parse_begin--; + } else + parse_type = seg; + + } + } + } + if (hevc->have_vps && hevc->have_sps && hevc->have_pps + && hevc->have_valid_start_slice && + hevc->error_flag == 0) { + if ((get_dbg_flag(hevc) & + H265_DEBUG_MAN_SEARCH_NAL) == 0 + /* && (!hevc->m_ins_flag)*/) { + /* auot parser NAL; do not check + *vps/sps/pps/idr + */ + WRITE_VREG(NAL_SEARCH_CTL, 0x2); + } + + if ((get_dbg_flag(hevc) & + H265_DEBUG_NO_EOS_SEARCH_DONE) +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + || vdec->master + || vdec->slave +#endif + ) { + WRITE_VREG(NAL_SEARCH_CTL, + READ_VREG(NAL_SEARCH_CTL) | + 0x10000); + } + WRITE_VREG(NAL_SEARCH_CTL, + READ_VREG(NAL_SEARCH_CTL) + | ((parser_sei_enable & 0x7) << 17)); +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + WRITE_VREG(NAL_SEARCH_CTL, + READ_VREG(NAL_SEARCH_CTL) | + ((parser_dolby_vision_enable & 0x1) << 20)); +#endif + config_decode_mode(hevc); + } + + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) { + hevc_print(hevc, 0, + "naltype = %d parse_type %d\n %d %d %d %d\n", + naltype, parse_type, hevc->have_vps, + hevc->have_sps, hevc->have_pps, + hevc->have_valid_start_slice); + } + + WRITE_VREG(HEVC_DEC_STATUS_REG, parse_type); + /* Interrupt Amrisc to excute */ + WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ); +#ifdef MULTI_INSTANCE_SUPPORT + if (hevc->m_ins_flag) + start_process_time(hevc); +#endif + } else if (dec_status == HEVC_SLICE_SEGMENT_DONE) { +#ifdef MULTI_INSTANCE_SUPPORT + if (hevc->m_ins_flag) { + reset_process_time(hevc); + read_decode_info(hevc); + + } +#endif + if (hevc->start_decoding_time > 0) { + u32 process_time = 1000* + (jiffies - hevc->start_decoding_time)/HZ; + if (process_time > max_decoding_time) + max_decoding_time = process_time; + } + + hevc->error_watchdog_count = 0; + if (hevc->pic_list_init_flag == 2) { + hevc->pic_list_init_flag = 3; + hevc_print(hevc, 0, "set pic_list_init_flag to 3\n"); + } else if (hevc->wait_buf == 0) { + u32 vui_time_scale; + u32 vui_num_units_in_tick; + unsigned char reconfig_flag = 0; + + if (get_dbg_flag(hevc) & H265_DEBUG_SEND_PARAM_WITH_REG) + get_rpm_param(&hevc->param); + else { + dma_sync_single_for_cpu( + amports_get_dma_device(), + hevc->rpm_phy_addr, + RPM_BUF_SIZE, + DMA_FROM_DEVICE); + + for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) { + int ii; + + for (ii = 0; ii < 4; ii++) { + hevc->param.l.data[i + ii] = + hevc->rpm_ptr[i + 3 + - ii]; + } + } +#ifdef SEND_LMEM_WITH_RPM + dma_sync_single_for_cpu( + amports_get_dma_device(), + hevc->lmem_phy_addr, + LMEM_BUF_SIZE, + DMA_FROM_DEVICE); + check_head_error(hevc); +#endif + } + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR_MORE) { + hevc_print(hevc, 0, + "rpm_param: (%d)\n", hevc->slice_idx); + hevc->slice_idx++; + for (i = 0; i < (RPM_END - RPM_BEGIN); i++) { + hevc_print_cont(hevc, 0, + "%04x ", hevc->param.l.data[i]); + if (((i + 1) & 0xf) == 0) + hevc_print_cont(hevc, 0, "\n"); + } + + hevc_print(hevc, 0, + "vui_timing_info: %x, %x, %x, %x\n", + hevc->param.p.vui_num_units_in_tick_hi, + hevc->param.p.vui_num_units_in_tick_lo, + hevc->param.p.vui_time_scale_hi, + hevc->param.p.vui_time_scale_lo); + } + if ( +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + vdec->master == NULL && + vdec->slave == NULL && +#endif + READ_VREG(HEVC_AUX_DATA_SIZE) != 0 + ) { + dma_sync_single_for_cpu( + amports_get_dma_device(), + hevc->aux_phy_addr, + hevc->prefix_aux_size + hevc->suffix_aux_size, + DMA_FROM_DEVICE); + if (get_dbg_flag(hevc) & + H265_DEBUG_BUFMGR_MORE) + dump_aux_buf(hevc); + } + + vui_time_scale = + (u32)(hevc->param.p.vui_time_scale_hi << 16) | + hevc->param.p.vui_time_scale_lo; + vui_num_units_in_tick = + (u32)(hevc->param. + p.vui_num_units_in_tick_hi << 16) | + hevc->param. + p.vui_num_units_in_tick_lo; + if (hevc->bit_depth_luma != + ((hevc->param.p.bit_depth & 0xf) + 8)) { + reconfig_flag = 1; + hevc_print(hevc, 0, "Bit depth luma = %d\n", + (hevc->param.p.bit_depth & 0xf) + 8); + } + if (hevc->bit_depth_chroma != + (((hevc->param.p.bit_depth >> 4) & 0xf) + 8)) { + reconfig_flag = 1; + hevc_print(hevc, 0, "Bit depth chroma = %d\n", + ((hevc->param.p.bit_depth >> 4) & + 0xf) + 8); + } + hevc->bit_depth_luma = + (hevc->param.p.bit_depth & 0xf) + 8; + hevc->bit_depth_chroma = + ((hevc->param.p.bit_depth >> 4) & 0xf) + 8; + bit_depth_luma = hevc->bit_depth_luma; + bit_depth_chroma = hevc->bit_depth_chroma; +#ifdef SUPPORT_10BIT + if (hevc->bit_depth_luma == 8 && + hevc->bit_depth_chroma == 8 && + enable_mem_saving) + hevc->mem_saving_mode = 1; + else + hevc->mem_saving_mode = 0; +#endif + if (reconfig_flag && + (get_double_write_mode(hevc) & 0x10) == 0) + init_decode_head_hw(hevc); + + if ((vui_time_scale != 0) + && (vui_num_units_in_tick != 0)) { + hevc->frame_dur = + div_u64(96000ULL * + vui_num_units_in_tick, + vui_time_scale); + if (hevc->get_frame_dur != true) + schedule_work( + &hevc->notify_work); + + hevc->get_frame_dur = true; +#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + gvs->frame_dur = hevc->frame_dur; +#endif + } + + if (hevc->video_signal_type != + ((hevc->param.p.video_signal_type << 16) + | hevc->param.p.color_description)) { + u32 v = hevc->param.p.video_signal_type; + u32 c = hevc->param.p.color_description; +#if 0 + if (v & 0x2000) { + hevc_print(hevc, 0, + "video_signal_type present:\n"); + hevc_print(hevc, 0, " %s %s\n", + video_format_names[(v >> 10) & 7], + ((v >> 9) & 1) ? + "full_range" : "limited"); + if (v & 0x100) { + hevc_print(hevc, 0, + " color_description present:\n"); + hevc_print(hevc, 0, + " color_primarie = %s\n", + color_primaries_names + [v & 0xff]); + hevc_print(hevc, 0, + " transfer_characteristic = %s\n", + transfer_characteristics_names + [(c >> 8) & 0xff]); + hevc_print(hevc, 0, + " matrix_coefficient = %s\n", + matrix_coeffs_names[c & 0xff]); + } + } +#endif + hevc->video_signal_type = (v << 16) | c; + video_signal_type = hevc->video_signal_type; + } + + if (use_cma && + (hevc->param.p.slice_segment_address == 0) + && (hevc->pic_list_init_flag == 0)) { + int log = hevc->param.p.log2_min_coding_block_size_minus3; + int log_s = hevc->param.p.log2_diff_max_min_coding_block_size; + + hevc->pic_w = hevc->param.p.pic_width_in_luma_samples; + hevc->pic_h = hevc->param.p.pic_height_in_luma_samples; + hevc->lcu_size = 1 << (log + 3 + log_s); + hevc->lcu_size_log2 = log2i(hevc->lcu_size); + if (hevc->pic_w == 0 || hevc->pic_h == 0 + || hevc->lcu_size == 0) { + /* skip search next start code */ + WRITE_VREG(HEVC_WAIT_FLAG, READ_VREG(HEVC_WAIT_FLAG) + & (~0x2)); + hevc->skip_flag = 1; + WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE); + /* Interrupt Amrisc to excute */ + WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ); +#ifdef MULTI_INSTANCE_SUPPORT + if (hevc->m_ins_flag) + start_process_time(hevc); +#endif + } else { + hevc->sps_num_reorder_pics_0 = + hevc->param.p.sps_num_reorder_pics_0; + hevc->pic_list_init_flag = 1; +#ifdef MULTI_INSTANCE_SUPPORT + if (hevc->m_ins_flag) { + vdec_schedule_work(&hevc->work); + } else +#endif + up(&h265_sema); + hevc_print(hevc, 0, "set pic_list_init_flag 1\n"); + } + return IRQ_HANDLED; + } + +} + ret = + hevc_slice_segment_header_process(hevc, + &hevc->param, decode_pic_begin); + if (ret < 0) { +#ifdef MULTI_INSTANCE_SUPPORT + if (hevc->m_ins_flag) { + hevc->wait_buf = 0; + hevc->dec_result = DEC_RESULT_AGAIN; + amhevc_stop(); + restore_decode_state(hevc); + reset_process_time(hevc); + vdec_schedule_work(&hevc->work); + return IRQ_HANDLED; + } +#else + ; +#endif + } else if (ret == 0) { + if ((hevc->new_pic) && (hevc->cur_pic)) { + hevc->cur_pic->stream_offset = + READ_VREG(HEVC_SHIFT_BYTE_COUNT); + hevc_print(hevc, H265_DEBUG_OUT_PTS, + "read stream_offset = 0x%x\n", + hevc->cur_pic->stream_offset); + hevc->cur_pic->aspect_ratio_idc = + hevc->param.p.aspect_ratio_idc; + hevc->cur_pic->sar_width = + hevc->param.p.sar_width; + hevc->cur_pic->sar_height = + hevc->param.p.sar_height; + } + + WRITE_VREG(HEVC_DEC_STATUS_REG, + HEVC_CODED_SLICE_SEGMENT_DAT); + /* Interrupt Amrisc to excute */ + WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ); + + hevc->start_decoding_time = jiffies; +#ifdef MULTI_INSTANCE_SUPPORT + if (hevc->m_ins_flag) + start_process_time(hevc); +#endif +#if 1 + /*to do..., copy aux data to hevc->cur_pic*/ +#endif +#ifdef MULTI_INSTANCE_SUPPORT + } else if (hevc->m_ins_flag) { + hevc_print(hevc, PRINT_FLAG_VDEC_STATUS, + "%s, bufmgr ret %d skip, DEC_RESULT_DONE\n", + __func__, ret); + hevc->decoded_poc = INVALID_POC; + hevc->decoding_pic = NULL; + hevc->dec_result = DEC_RESULT_DONE; + amhevc_stop(); + reset_process_time(hevc); + vdec_schedule_work(&hevc->work); +#endif + } else { + /* skip, search next start code */ +#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + gvs->drop_frame_count++; +#endif + WRITE_VREG(HEVC_WAIT_FLAG, READ_VREG(HEVC_WAIT_FLAG) & (~0x2)); + hevc->skip_flag = 1; + WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE); + /* Interrupt Amrisc to excute */ + WRITE_VREG(HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ); + } + + } else if (dec_status == HEVC_DECODE_OVER_SIZE) { + hevc_print(hevc, 0 , "hevc decode oversize !!\n"); +#ifdef MULTI_INSTANCE_SUPPORT + if (!hevc->m_ins_flag) + debug |= (H265_DEBUG_DIS_LOC_ERROR_PROC | + H265_DEBUG_DIS_SYS_ERROR_PROC); +#endif + hevc->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW; + } + return IRQ_HANDLED; +} + +static void wait_hevc_search_done(struct hevc_state_s *hevc) +{ + int count = 0; + WRITE_VREG(HEVC_SHIFT_STATUS, 0); + while (READ_VREG(HEVC_STREAM_CONTROL) & 0x2) { + msleep(20); + count++; + if (count > 100) { + hevc_print(hevc, 0, "%s timeout\n", __func__); + break; + } + } +} +static irqreturn_t vh265_isr(int irq, void *data) +{ + int i, temp; + unsigned int dec_status; + struct hevc_state_s *hevc = (struct hevc_state_s *)data; + u32 debug_tag; + dec_status = READ_VREG(HEVC_DEC_STATUS_REG); + if (hevc->init_flag == 0) + return IRQ_HANDLED; + hevc->dec_status = dec_status; + if (is_log_enable(hevc)) + add_log(hevc, + "isr: status = 0x%x dec info 0x%x lcu 0x%x shiftbyte 0x%x shiftstatus 0x%x", + dec_status, READ_HREG(HEVC_DECODE_INFO), + READ_VREG(HEVC_MPRED_CURR_LCU), + READ_VREG(HEVC_SHIFT_BYTE_COUNT), + READ_VREG(HEVC_SHIFT_STATUS)); + + if (get_dbg_flag(hevc) & H265_DEBUG_BUFMGR) + hevc_print(hevc, 0, + "265 isr dec status = 0x%x dec info 0x%x shiftbyte 0x%x shiftstatus 0x%x\n", + dec_status, READ_HREG(HEVC_DECODE_INFO), + READ_VREG(HEVC_SHIFT_BYTE_COUNT), + READ_VREG(HEVC_SHIFT_STATUS)); + + debug_tag = READ_HREG(DEBUG_REG1); + if (debug_tag & 0x10000) { + dma_sync_single_for_cpu( + amports_get_dma_device(), + hevc->lmem_phy_addr, + LMEM_BUF_SIZE, + DMA_FROM_DEVICE); + + hevc_print(hevc, 0, + "LMEM:\n", READ_HREG(DEBUG_REG1)); + + if (hevc->mmu_enable) + temp = 0x500; + else + temp = 0x400; + for (i = 0; i < temp; i += 4) { + int ii; + if ((i & 0xf) == 0) + hevc_print_cont(hevc, 0, "%03x: ", i); + for (ii = 0; ii < 4; ii++) { + hevc_print_cont(hevc, 0, "%04x ", + hevc->lmem_ptr[i + 3 - ii]); + } + if (((i + ii) & 0xf) == 0) + hevc_print_cont(hevc, 0, "\n"); + } + + if (((udebug_pause_pos & 0xffff) + == (debug_tag & 0xffff)) && + (udebug_pause_decode_idx == 0 || + udebug_pause_decode_idx == hevc->decode_idx) && + (udebug_pause_val == 0 || + udebug_pause_val == READ_HREG(DEBUG_REG2))) { + udebug_pause_pos &= 0xffff; + hevc->ucode_pause_pos = udebug_pause_pos; + } + else if (debug_tag & 0x20000) + hevc->ucode_pause_pos = 0xffffffff; + if (hevc->ucode_pause_pos) + reset_process_time(hevc); + else + WRITE_HREG(DEBUG_REG1, 0); + } else if (debug_tag != 0) { + hevc_print(hevc, 0, + "dbg%x: %x l/w/r %x %x %x\n", READ_HREG(DEBUG_REG1), + READ_HREG(DEBUG_REG2), + READ_VREG(HEVC_STREAM_LEVEL), + READ_VREG(HEVC_STREAM_WR_PTR), + READ_VREG(HEVC_STREAM_RD_PTR)); + if (((udebug_pause_pos & 0xffff) + == (debug_tag & 0xffff)) && + (udebug_pause_decode_idx == 0 || + udebug_pause_decode_idx == hevc->decode_idx) && + (udebug_pause_val == 0 || + udebug_pause_val == READ_HREG(DEBUG_REG2))) { + udebug_pause_pos &= 0xffff; + hevc->ucode_pause_pos = udebug_pause_pos; + } + if (hevc->ucode_pause_pos) + reset_process_time(hevc); + else + WRITE_HREG(DEBUG_REG1, 0); + return IRQ_HANDLED; + } + + + if (hevc->pic_list_init_flag == 1) + return IRQ_HANDLED; + + return IRQ_WAKE_THREAD; + +} + +static void vh265_set_clk(struct work_struct *work) +{ + struct hevc_state_s *hevc = container_of(work, + struct hevc_state_s, work); + + if (hevc->m_ins_flag == 0 && + hevc->get_frame_dur && hevc->show_frame_num > 60 && + hevc->frame_dur > 0 && hevc->saved_resolution != + hevc->frame_width * hevc->frame_height * + (96000 / hevc->frame_dur)) { + int fps = 96000 / hevc->frame_dur; + + if (hevc_source_changed(VFORMAT_HEVC, + hevc->frame_width, hevc->frame_height, fps) > 0) + hevc->saved_resolution = hevc->frame_width * + hevc->frame_height * fps; + } +} + +static void vh265_check_timer_func(unsigned long arg) +{ + struct hevc_state_s *hevc = (struct hevc_state_s *)arg; + struct timer_list *timer = &hevc->timer; + unsigned char empty_flag; + unsigned int buf_level; + + enum receviver_start_e state = RECEIVER_INACTIVE; + + if (hevc->init_flag == 0) { + if (hevc->stat & STAT_TIMER_ARM) { + mod_timer(&hevc->timer, jiffies + PUT_INTERVAL); + } + return; + } +#ifdef MULTI_INSTANCE_SUPPORT + if (hevc->m_ins_flag && + (get_dbg_flag(hevc) & + H265_DEBUG_WAIT_DECODE_DONE_WHEN_STOP) == 0 && + hw_to_vdec(hevc)->next_status == + VDEC_STATUS_DISCONNECTED) { + hevc->dec_result = DEC_RESULT_FORCE_EXIT; + vdec_schedule_work(&hevc->work); + hevc_print(hevc, + 0, "vdec requested to be disconnected\n"); + return; + } + + if (hevc->m_ins_flag) { + if ((input_frame_based(hw_to_vdec(hevc)) || + (READ_VREG(HEVC_STREAM_LEVEL) > 0xb0)) && + ((get_dbg_flag(hevc) & + H265_DEBUG_DIS_LOC_ERROR_PROC) == 0) && + (decode_timeout_val > 0) && + (hevc->start_process_time > 0) && + ((1000 * (jiffies - hevc->start_process_time) / HZ) + > decode_timeout_val) + ) { + u32 dec_status = READ_VREG(HEVC_DEC_STATUS_REG); + int current_lcu_idx = + READ_VREG(HEVC_PARSER_LCU_START)&0xffffff; + if (dec_status == HEVC_CODED_SLICE_SEGMENT_DAT) { + if (hevc->last_lcu_idx == current_lcu_idx) { + if (hevc->decode_timeout_count > 0) + hevc->decode_timeout_count--; + if (hevc->decode_timeout_count == 0) + timeout_process(hevc); + } else + restart_process_time(hevc); + hevc->last_lcu_idx = current_lcu_idx; + } else { + hevc->pic_decoded_lcu_idx = current_lcu_idx; + timeout_process(hevc); + } + } + } else { +#endif + if (hevc->m_ins_flag == 0 && + vf_get_receiver(hevc->provider_name)) { + state = + vf_notify_receiver(hevc->provider_name, + VFRAME_EVENT_PROVIDER_QUREY_STATE, + NULL); + if ((state == RECEIVER_STATE_NULL) + || (state == RECEIVER_STATE_NONE)) + state = RECEIVER_INACTIVE; + } else + state = RECEIVER_INACTIVE; + + empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1; + /* error watchdog */ + if (hevc->m_ins_flag == 0 && + (empty_flag == 0) + && (hevc->pic_list_init_flag == 0 + || hevc->pic_list_init_flag + == 3)) { + /* decoder has input */ + if ((get_dbg_flag(hevc) & + H265_DEBUG_DIS_LOC_ERROR_PROC) == 0) { + + buf_level = READ_VREG(HEVC_STREAM_LEVEL); + /* receiver has no buffer to recycle */ + if ((state == RECEIVER_INACTIVE) && + (kfifo_is_empty(&hevc->display_q) && + buf_level > 0x200) + ) { + if (hevc->error_flag == 0) { + hevc->error_watchdog_count++; + if (hevc->error_watchdog_count == + error_handle_threshold) { + hevc_print(hevc, 0, + "H265 dec err local reset.\n"); + hevc->error_flag = 1; + hevc->error_watchdog_count = 0; + hevc->error_skip_nal_wt_cnt = 0; + hevc-> + error_system_watchdog_count++; + WRITE_VREG + (HEVC_ASSIST_MBOX0_IRQ_REG, + 0x1); + } + } else if (hevc->error_flag == 2) { + int th = + error_handle_nal_skip_threshold; + hevc->error_skip_nal_wt_cnt++; + if (hevc->error_skip_nal_wt_cnt + == th) { + hevc->error_flag = 3; + hevc->error_watchdog_count = 0; + hevc-> + error_skip_nal_wt_cnt = 0; + WRITE_VREG + (HEVC_ASSIST_MBOX0_IRQ_REG, + 0x1); + } + } + } + } + + if ((get_dbg_flag(hevc) + & H265_DEBUG_DIS_SYS_ERROR_PROC) == 0) + /* receiver has no buffer to recycle */ + if ((state == RECEIVER_INACTIVE) && + (kfifo_is_empty(&hevc->display_q)) + ) { /* no buffer to recycle */ + if ((get_dbg_flag(hevc) & + H265_DEBUG_DIS_LOC_ERROR_PROC) != + 0) + hevc->error_system_watchdog_count++; + if (hevc->error_system_watchdog_count == + error_handle_system_threshold) { + /* and it lasts for a while */ + hevc_print(hevc, 0, + "H265 dec fatal error watchdog.\n"); + hevc-> + error_system_watchdog_count = 0; + hevc->fatal_error |= DECODER_FATAL_ERROR_UNKNOWN; + } + } + } else { + hevc->error_watchdog_count = 0; + hevc->error_system_watchdog_count = 0; + } +#ifdef MULTI_INSTANCE_SUPPORT + } +#endif + if ((hevc->ucode_pause_pos != 0) && + (hevc->ucode_pause_pos != 0xffffffff) && + udebug_pause_pos != hevc->ucode_pause_pos) { + hevc->ucode_pause_pos = 0; + WRITE_HREG(DEBUG_REG1, 0); + } + + if (get_dbg_flag(hevc) & H265_DEBUG_DUMP_PIC_LIST) { + dump_pic_list(hevc); + debug &= ~H265_DEBUG_DUMP_PIC_LIST; + } + if (get_dbg_flag(hevc) & H265_DEBUG_TRIG_SLICE_SEGMENT_PROC) { + WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1); + debug &= ~H265_DEBUG_TRIG_SLICE_SEGMENT_PROC; + } +#ifdef TEST_NO_BUF + if (hevc->wait_buf) + WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1); +#endif + if (get_dbg_flag(hevc) & H265_DEBUG_HW_RESET) { + hevc->error_skip_nal_count = error_skip_nal_count; + WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE); + + debug &= ~H265_DEBUG_HW_RESET; + } + +#ifdef ERROR_HANDLE_DEBUG + if ((dbg_nal_skip_count > 0) && ((dbg_nal_skip_count & 0x10000) != 0)) { + hevc->error_skip_nal_count = dbg_nal_skip_count & 0xffff; + dbg_nal_skip_count &= ~0x10000; + WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE); + } +#endif + + if (radr != 0) { + if (rval != 0) { + WRITE_VREG(radr, rval); + hevc_print(hevc, 0, + "WRITE_VREG(%x,%x)\n", radr, rval); + } else + hevc_print(hevc, 0, + "READ_VREG(%x)=%x\n", radr, READ_VREG(radr)); + rval = 0; + radr = 0; + } + if (dbg_cmd != 0) { + if (dbg_cmd == 1) { + u32 disp_laddr; + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB && + get_double_write_mode(hevc) == 0) { + disp_laddr = + READ_VCBUS_REG(AFBC_BODY_BADDR) << 4; + } else { + struct canvas_s cur_canvas; + + canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0) + & 0xff), &cur_canvas); + disp_laddr = cur_canvas.addr; + } + hevc_print(hevc, 0, + "current displayed buffer address %x\r\n", + disp_laddr); + } + dbg_cmd = 0; + } + /*don't changed at start.*/ + if (hevc->m_ins_flag == 0) + schedule_work(&hevc->set_clk_work); + + mod_timer(timer, jiffies + PUT_INTERVAL); +} + +static int h265_task_handle(void *data) +{ + int ret = 0; + struct hevc_state_s *hevc = (struct hevc_state_s *)data; + + set_user_nice(current, -10); + while (1) { + if (use_cma == 0) { + hevc_print(hevc, 0, + "ERROR: use_cma can not be changed dynamically\n"); + } + ret = down_interruptible(&h265_sema); + if ((hevc->init_flag != 0) && (hevc->pic_list_init_flag == 1)) { + init_pic_list(hevc); + init_pic_list_hw(hevc); + init_buf_spec(hevc); + hevc->pic_list_init_flag = 2; + hevc_print(hevc, 0, "set pic_list_init_flag to 2\n"); + + WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1); + + } + + if (hevc->uninit_list) { + /*USE_BUF_BLOCK*/ + uninit_pic_list(hevc); + hevc_print(hevc, 0, "uninit list\n"); + hevc->uninit_list = 0; +#ifdef USE_UNINIT_SEMA + if (use_cma && hevc->init_flag) { + up(&hevc->h265_uninit_done_sema); + break; + } +#endif + } + } + + while (!kthread_should_stop()) { + msleep(1); + } + + return 0; + +} + +void vh265_free_cmabuf(void) +{ + struct hevc_state_s *hevc = gHevc; + + mutex_lock(&vh265_mutex); + + if (hevc->init_flag) { + mutex_unlock(&vh265_mutex); + return; + } + + mutex_unlock(&vh265_mutex); +} + +#ifdef MULTI_INSTANCE_SUPPORT +int vh265_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus) +#else +int vh265_dec_status(struct vdec_info *vstatus) +#endif +{ +#ifdef MULTI_INSTANCE_SUPPORT + struct hevc_state_s *hevc = + (struct hevc_state_s *)vdec->private; +#else + struct hevc_state_s *hevc = gHevc; +#endif + vstatus->frame_width = hevc->frame_width; + vstatus->frame_height = hevc->frame_height; + if (hevc->frame_dur != 0) + vstatus->frame_rate = 96000 / hevc->frame_dur; + else + vstatus->frame_rate = -1; + vstatus->error_count = 0; + vstatus->status = hevc->stat | hevc->fatal_error; +#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + vstatus->bit_rate = gvs->bit_rate; + vstatus->frame_dur = hevc->frame_dur; + if (gvs) { + vstatus->bit_rate = gvs->bit_rate; + vstatus->frame_data = gvs->frame_data; + vstatus->total_data = gvs->total_data; + vstatus->frame_count = gvs->frame_count; + vstatus->error_frame_count = gvs->error_frame_count; + vstatus->drop_frame_count = gvs->drop_frame_count; + vstatus->total_data = gvs->total_data; + vstatus->samp_cnt = gvs->samp_cnt; + vstatus->offset = gvs->offset; + } + snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name), + "%s", DRIVER_NAME); +#endif + return 0; +} + +int vh265_set_isreset(struct vdec_s *vdec, int isreset) +{ + is_reset = isreset; + return 0; +} + +static int vh265_vdec_info_init(void) +{ + gvs = kzalloc(sizeof(struct vdec_info), GFP_KERNEL); + if (NULL == gvs) { + pr_info("the struct of vdec status malloc failed.\n"); + return -ENOMEM; + } + return 0; +} + +#if 0 +static void H265_DECODE_INIT(void) +{ + /* enable hevc clocks */ + WRITE_VREG(DOS_GCLK_EN3, 0xffffffff); + /* *************************************************************** */ + /* Power ON HEVC */ + /* *************************************************************** */ + /* Powerup HEVC */ + WRITE_VREG(P_AO_RTI_GEN_PWR_SLEEP0, + READ_VREG(P_AO_RTI_GEN_PWR_SLEEP0) & (~(0x3 << 6))); + WRITE_VREG(DOS_MEM_PD_HEVC, 0x0); + WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) | (0x3ffff << 2)); + WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) & (~(0x3ffff << 2))); + /* remove isolations */ + WRITE_VREG(AO_RTI_GEN_PWR_ISO0, + READ_VREG(AO_RTI_GEN_PWR_ISO0) & (~(0x3 << 10))); + +} +#endif + +static void config_decode_mode(struct hevc_state_s *hevc) +{ +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + struct vdec_s *vdec = hw_to_vdec(hevc); +#endif + unsigned decode_mode; + if (!hevc->m_ins_flag) + decode_mode = DECODE_MODE_SINGLE; + else if (vdec_frame_based(hw_to_vdec(hevc))) + decode_mode = + DECODE_MODE_MULTI_FRAMEBASE; +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + else if (vdec->slave) + decode_mode = + (hevc->start_parser_type << 8) + | DECODE_MODE_MULTI_DVBAL; + else if (vdec->master) + decode_mode = + (hevc->start_parser_type << 8) + | DECODE_MODE_MULTI_DVENL; +#endif + else + decode_mode = + DECODE_MODE_MULTI_STREAMBASE; + + if (hevc->m_ins_flag) + decode_mode |= + (hevc->start_decoding_flag << 16); + /* set MBX0 interrupt flag */ + decode_mode |= (0x80 << 24); + WRITE_VREG(HEVC_DECODE_MODE, decode_mode); + WRITE_VREG(HEVC_DECODE_MODE2, + hevc->rps_set_id); +} + +static void vh265_prot_init(struct hevc_state_s *hevc) +{ +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + struct vdec_s *vdec = hw_to_vdec(hevc); +#endif + /* H265_DECODE_INIT(); */ + + hevc_config_work_space_hw(hevc); + + hevc_init_decoder_hw(hevc, 0, 0xffffffff); + + WRITE_VREG(HEVC_WAIT_FLAG, 1); + + /* WRITE_VREG(P_HEVC_MPSR, 1); */ + + /* clear mailbox interrupt */ + WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1); + + /* enable mailbox interrupt */ + WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1); + + /* disable PSCALE for hardware sharing */ + WRITE_VREG(HEVC_PSCALE_CTRL, 0); + + WRITE_VREG(DEBUG_REG1, 0x0 | (dump_nal << 8)); + + if ((get_dbg_flag(hevc) & + (H265_DEBUG_MAN_SKIP_NAL | + H265_DEBUG_MAN_SEARCH_NAL)) + /*||hevc->m_ins_flag*/ + ) { + WRITE_VREG(NAL_SEARCH_CTL, 0x1); /* manual parser NAL */ + } else { + /* check vps/sps/pps/i-slice in ucode */ + unsigned ctl_val = 0x8; + if (hevc->PB_skip_mode == 0) + ctl_val = 0x4; /* check vps/sps/pps only in ucode */ + else if (hevc->PB_skip_mode == 3) + ctl_val = 0x0; /* check vps/sps/pps/idr in ucode */ + WRITE_VREG(NAL_SEARCH_CTL, ctl_val); + } + if ((get_dbg_flag(hevc) & H265_DEBUG_NO_EOS_SEARCH_DONE) +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + || vdec->master + || vdec->slave +#endif + ) + WRITE_VREG(NAL_SEARCH_CTL, READ_VREG(NAL_SEARCH_CTL) | 0x10000); + + WRITE_VREG(NAL_SEARCH_CTL, + READ_VREG(NAL_SEARCH_CTL) + | ((parser_sei_enable & 0x7) << 17)); +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + WRITE_VREG(NAL_SEARCH_CTL, + READ_VREG(NAL_SEARCH_CTL) | + ((parser_dolby_vision_enable & 0x1) << 20)); +#endif + WRITE_VREG(DECODE_STOP_POS, udebug_flag); + + config_decode_mode(hevc); + config_aux_buf(hevc); +} + +static int vh265_local_init(struct hevc_state_s *hevc) +{ + int i; + int ret = -1; + +#ifdef DEBUG_PTS + hevc->pts_missed = 0; + hevc->pts_hit = 0; +#endif + + hevc->saved_resolution = 0; + hevc->get_frame_dur = false; + hevc->frame_width = hevc->vh265_amstream_dec_info.width; + hevc->frame_height = hevc->vh265_amstream_dec_info.height; + if (OVER_SIZE(hevc->frame_width, hevc->frame_height)) { + pr_info("over size : %u x %u.\n", + hevc->frame_width, hevc->frame_height); + hevc->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW; + return ret; + } + hevc->frame_dur = + (hevc->vh265_amstream_dec_info.rate == + 0) ? 3600 : hevc->vh265_amstream_dec_info.rate; +#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + gvs->frame_dur = hevc->frame_dur; +#endif + if (hevc->frame_width && hevc->frame_height) + hevc->frame_ar = hevc->frame_height * 0x100 / hevc->frame_width; + + if (i_only_flag) + hevc->i_only = i_only_flag & 0xff; + else if ((unsigned long) hevc->vh265_amstream_dec_info.param + & 0x08) + hevc->i_only = 0x7; + else + hevc->i_only = 0x0; + hevc->error_watchdog_count = 0; + hevc->sei_present_flag = 0; + pts_unstable = ((unsigned long)hevc->vh265_amstream_dec_info.param + & 0x40) >> 6; + hevc_print(hevc, 0, + "h265:pts_unstable=%d\n", pts_unstable); +/* + *TODO:FOR VERSION + */ + hevc_print(hevc, 0, + "h265: ver (%d,%d) decinfo: %dx%d rate=%d\n", h265_version, + 0, hevc->frame_width, hevc->frame_height, hevc->frame_dur); + + if (hevc->frame_dur == 0) + hevc->frame_dur = 96000 / 24; + + INIT_KFIFO(hevc->display_q); + INIT_KFIFO(hevc->newframe_q); + + + for (i = 0; i < VF_POOL_SIZE; i++) { + const struct vframe_s *vf = &hevc->vfpool[i]; + + hevc->vfpool[i].index = -1; + kfifo_put(&hevc->newframe_q, vf); + } + + + ret = hevc_local_init(hevc); + + return ret; +} +#ifdef MULTI_INSTANCE_SUPPORT +static s32 vh265_init(struct vdec_s *vdec) +{ + struct hevc_state_s *hevc = (struct hevc_state_s *)vdec->private; +#else +static s32 vh265_init(struct hevc_state_s *hevc) +{ + +#endif + int ret, size = -1; + int fw_size = 0x1000 * 16; + struct firmware_s *fw = NULL; + + init_timer(&hevc->timer); + + hevc->stat |= STAT_TIMER_INIT; + if (vh265_local_init(hevc) < 0) + return -EBUSY; + + INIT_WORK(&hevc->notify_work, vh265_notify_work); + INIT_WORK(&hevc->set_clk_work, vh265_set_clk); + fw = vmalloc(sizeof(struct firmware_s) + fw_size); + if (IS_ERR_OR_NULL(fw)) + return -ENOMEM; +#ifdef MULTI_INSTANCE_SUPPORT + if (tee_enabled()) + size = 1; + else +#endif + + if (hevc->mmu_enable) { + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) { + size = get_firmware_data(VIDEO_DEC_HEVC, fw->data); + hevc_print(hevc, 0, "vh265 ucode loaded!\n"); + } else { + size = get_firmware_data(VIDEO_DEC_HEVC_MMU, fw->data); + hevc_print(hevc, 0, "vh265 mmu ucode loaded!\n"); + } + } else { + size = get_firmware_data(VIDEO_DEC_HEVC, fw->data); + hevc_print(hevc, 0, "vh265 ucode loaded!\n"); + } + + if (size < 0) { + pr_err("get firmware fail.\n"); + vfree(fw); + return -1; + } + + fw->len = size; + +#ifdef MULTI_INSTANCE_SUPPORT + if (hevc->m_ins_flag) { + hevc->timer.data = (ulong) hevc; + hevc->timer.function = vh265_check_timer_func; + hevc->timer.expires = jiffies + PUT_INTERVAL; + +#ifdef USE_UNINIT_SEMA + sema_init(&hevc->h265_uninit_done_sema, 0); +#endif + + /*add_timer(&hevc->timer); + *hevc->stat |= STAT_TIMER_ARM; + */ + + INIT_WORK(&hevc->work, vh265_work); + + hevc->fw = fw; + + return 0; + } +#endif + amhevc_enable(); + + if (size == 1) { + pr_info ("tee load ok"); + + if (hevc->mmu_enable) { + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) + ret = tee_load_video_fw((u32)VIDEO_DEC_HEVC, 0); + else + ret = tee_load_video_fw((u32)VIDEO_DEC_HEVC_MMU, 0); + } else + ret = tee_load_video_fw((u32)VIDEO_DEC_HEVC, 0); + } else + ret = amhevc_loadmc_ex(VFORMAT_HEVC, NULL, fw->data); + + if (ret < 0) { + amhevc_disable(); + vfree(fw); + return -EBUSY; + } + + vfree(fw); + + hevc->stat |= STAT_MC_LOAD; + + /* enable AMRISC side protocol */ + vh265_prot_init(hevc); + + if (vdec_request_threaded_irq(VDEC_IRQ_0, vh265_isr, + vh265_isr_thread_fn, + IRQF_ONESHOT,/*run thread on this irq disabled*/ + "vh265-irq", (void *)hevc)) { + hevc_print(hevc, 0, "vh265 irq register error.\n"); + amhevc_disable(); + return -ENOENT; + } + + hevc->stat |= STAT_ISR_REG; + hevc->provider_name = PROVIDER_NAME; + +#ifdef MULTI_INSTANCE_SUPPORT + vf_provider_init(&vh265_vf_prov, hevc->provider_name, + &vh265_vf_provider, vdec); + vf_reg_provider(&vh265_vf_prov); + vf_notify_receiver(hevc->provider_name, VFRAME_EVENT_PROVIDER_START, + NULL); + if (hevc->frame_dur != 0) { + if (!is_reset) + vf_notify_receiver(hevc->provider_name, + VFRAME_EVENT_PROVIDER_FR_HINT, + (void *) + ((unsigned long)hevc->frame_dur)); + fr_hint_status = VDEC_HINTED; + } else + fr_hint_status = VDEC_NEED_HINT; +#else + vf_provider_init(&vh265_vf_prov, PROVIDER_NAME, &vh265_vf_provider, + hevc); + vf_reg_provider(&vh265_vf_prov); + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL); + if (hevc->frame_dur != 0) { + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_FR_HINT, + (void *) + ((unsigned long)hevc->frame_dur)); + fr_hint_status = VDEC_HINTED; + } else + fr_hint_status = VDEC_NEED_HINT; +#endif + hevc->stat |= STAT_VF_HOOK; + + hevc->timer.data = (ulong) hevc; + hevc->timer.function = vh265_check_timer_func; + hevc->timer.expires = jiffies + PUT_INTERVAL; + + add_timer(&hevc->timer); + + hevc->stat |= STAT_TIMER_ARM; + + if (use_cma) { +#ifdef USE_UNINIT_SEMA + sema_init(&hevc->h265_uninit_done_sema, 0); +#endif + if (h265_task == NULL) { + sema_init(&h265_sema, 1); + h265_task = + kthread_run(h265_task_handle, hevc, + "kthread_h265"); + } + } + /* hevc->stat |= STAT_KTHREAD; */ +#if 0 + if (get_dbg_flag(hevc) & H265_DEBUG_FORCE_CLK) { + hevc_print(hevc, 0, "%s force clk\n", __func__); + WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, + READ_VREG(HEVC_IQIT_CLK_RST_CTRL) | + ((1 << 2) | (1 << 1))); + WRITE_VREG(HEVC_DBLK_CFG0, + READ_VREG(HEVC_DBLK_CFG0) | ((1 << 2) | + (1 << 1) | 0x3fff0000));/* 2,29:16 */ + WRITE_VREG(HEVC_SAO_CTRL1, READ_VREG(HEVC_SAO_CTRL1) | + (1 << 2)); /* 2 */ + WRITE_VREG(HEVC_MPRED_CTRL1, READ_VREG(HEVC_MPRED_CTRL1) | + (1 << 24)); /* 24 */ + WRITE_VREG(HEVC_STREAM_CONTROL, + READ_VREG(HEVC_STREAM_CONTROL) | + (1 << 15)); /* 15 */ + WRITE_VREG(HEVC_CABAC_CONTROL, READ_VREG(HEVC_CABAC_CONTROL) | + (1 << 13)); /* 13 */ + WRITE_VREG(HEVC_PARSER_CORE_CONTROL, + READ_VREG(HEVC_PARSER_CORE_CONTROL) | + (1 << 15)); /* 15 */ + WRITE_VREG(HEVC_PARSER_INT_CONTROL, + READ_VREG(HEVC_PARSER_INT_CONTROL) | + (1 << 15)); /* 15 */ + WRITE_VREG(HEVC_PARSER_IF_CONTROL, + READ_VREG(HEVC_PARSER_IF_CONTROL) | ((1 << 6) | + (1 << 3) | (1 << 1))); /* 6, 3, 1 */ + WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, 0xffffffff); /* 31:0 */ + WRITE_VREG(HEVCD_MCRCC_CTL1, READ_VREG(HEVCD_MCRCC_CTL1) | + (1 << 3)); /* 3 */ + } +#endif + amhevc_start(); + + hevc->stat |= STAT_VDEC_RUN; +#ifndef MULTI_INSTANCE_SUPPORT + set_vdec_func(&vh265_dec_status); +#endif + hevc->init_flag = 1; + if (hevc->mmu_enable) + error_handle_threshold = 300; + else + error_handle_threshold = 30; + /* pr_info("%d, vh265_init, RP=0x%x\n", + * __LINE__, READ_VREG(HEVC_STREAM_RD_PTR)); + */ + + return 0; +} + +static int vh265_stop(struct hevc_state_s *hevc) +{ + if (get_dbg_flag(hevc) & + H265_DEBUG_WAIT_DECODE_DONE_WHEN_STOP) { + int wait_timeout_count = 0; + + while (READ_VREG(HEVC_DEC_STATUS_REG) == + HEVC_CODED_SLICE_SEGMENT_DAT && + wait_timeout_count < 10){ + wait_timeout_count++; + msleep(20); + } + } + if (hevc->stat & STAT_VDEC_RUN) { + amhevc_stop(); + hevc->stat &= ~STAT_VDEC_RUN; + } + + if (hevc->stat & STAT_ISR_REG) { +#ifdef MULTI_INSTANCE_SUPPORT + if (!hevc->m_ins_flag) +#endif + WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0); + vdec_free_irq(VDEC_IRQ_0, (void *)hevc); + hevc->stat &= ~STAT_ISR_REG; + } + + hevc->stat &= ~STAT_TIMER_INIT; + if (hevc->stat & STAT_TIMER_ARM) { + del_timer_sync(&hevc->timer); + hevc->stat &= ~STAT_TIMER_ARM; + } + + if (hevc->stat & STAT_VF_HOOK) { + if (fr_hint_status == VDEC_HINTED && !is_reset) { + vf_notify_receiver(hevc->provider_name, + VFRAME_EVENT_PROVIDER_FR_END_HINT, + NULL); + } + fr_hint_status = VDEC_NO_NEED_HINT; + vf_unreg_provider(&vh265_vf_prov); + hevc->stat &= ~STAT_VF_HOOK; + } + + hevc_local_uninit(hevc); + + if (use_cma) { + hevc->uninit_list = 1; + up(&h265_sema); +#ifdef USE_UNINIT_SEMA + if (hevc->init_flag) { + down(&hevc->h265_uninit_done_sema); + if (!IS_ERR(h265_task)) { + kthread_stop(h265_task); + h265_task = NULL; + } + } +#else + while (hevc->uninit_list) /* wait uninit complete */ + msleep(20); +#endif + + } + hevc->init_flag = 0; + cancel_work_sync(&hevc->notify_work); + cancel_work_sync(&hevc->set_clk_work); + uninit_mmu_buffers(hevc); + amhevc_disable(); + + kfree(gvs); + gvs = NULL; + + return 0; +} + +#ifdef MULTI_INSTANCE_SUPPORT +static void reset_process_time(struct hevc_state_s *hevc) +{ + if (hevc->start_process_time) { + unsigned int process_time = + 1000 * (jiffies - hevc->start_process_time) / HZ; + hevc->start_process_time = 0; + if (process_time > max_process_time[hevc->index]) + max_process_time[hevc->index] = process_time; + } +} + +static void start_process_time(struct hevc_state_s *hevc) +{ + hevc->start_process_time = jiffies; + hevc->decode_timeout_count = 2; + hevc->last_lcu_idx = 0; +} + +static void restart_process_time(struct hevc_state_s *hevc) +{ + hevc->start_process_time = jiffies; + hevc->decode_timeout_count = 2; +} + +static void timeout_process(struct hevc_state_s *hevc) +{ + hevc->timeout_num++; + amhevc_stop(); + read_decode_info(hevc); + + hevc_print(hevc, + 0, "%s decoder timeout\n", __func__); + check_pic_decoded_error(hevc, + hevc->pic_decoded_lcu_idx); + hevc->decoded_poc = hevc->curr_POC; + hevc->decoding_pic = NULL; + hevc->dec_result = DEC_RESULT_DONE; + reset_process_time(hevc); + vdec_schedule_work(&hevc->work); +} + +static unsigned char is_new_pic_available(struct hevc_state_s *hevc) +{ + struct PIC_s *new_pic = NULL; + struct PIC_s *pic; + /* recycle un-used pic */ + int i; + /*return 1 if pic_list is not initialized yet*/ + if (hevc->pic_list_init_flag != 3) + return 1; + + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + pic = hevc->m_PIC[i]; + if (pic == NULL || pic->index == -1) + continue; + if (pic->output_mark == 0 && pic->referenced == 0 + && pic->output_ready == 0 + ) { + if (new_pic) { + if (pic->POC < new_pic->POC) + new_pic = pic; + } else + new_pic = pic; + } + } + return (new_pic != NULL) ? 1 : 0; +} + +static int vmh265_stop(struct hevc_state_s *hevc) +{ + if (hevc->stat & STAT_TIMER_ARM) { + del_timer_sync(&hevc->timer); + hevc->stat &= ~STAT_TIMER_ARM; + } + if (hevc->stat & STAT_VDEC_RUN) { + amhevc_stop(); + hevc->stat &= ~STAT_VDEC_RUN; + } + if (hevc->stat & STAT_ISR_REG) { + vdec_free_irq(VDEC_IRQ_0, (void *)hevc); + hevc->stat &= ~STAT_ISR_REG; + } + + if (hevc->stat & STAT_VF_HOOK) { + if (fr_hint_status == VDEC_HINTED) + vf_notify_receiver(hevc->provider_name, + VFRAME_EVENT_PROVIDER_FR_END_HINT, + NULL); + fr_hint_status = VDEC_NO_NEED_HINT; + vf_unreg_provider(&vh265_vf_prov); + hevc->stat &= ~STAT_VF_HOOK; + } + + hevc_local_uninit(hevc); + + if (use_cma) { + hevc->uninit_list = 1; + reset_process_time(hevc); + vdec_schedule_work(&hevc->work); +#ifdef USE_UNINIT_SEMA + if (hevc->init_flag) { + down(&hevc->h265_uninit_done_sema); + } +#else + while (hevc->uninit_list) /* wait uninit complete */ + msleep(20); +#endif + } + hevc->init_flag = 0; + cancel_work_sync(&hevc->work); + cancel_work_sync(&hevc->notify_work); + cancel_work_sync(&hevc->set_clk_work); + uninit_mmu_buffers(hevc); + + vfree(hevc->fw); + hevc->fw = NULL; + + dump_log(hevc); + return 0; +} + +static unsigned char get_data_check_sum + (struct hevc_state_s *hevc, int size) +{ + int jj; + int sum = 0; + u8 *data = ((u8 *)hevc->chunk->block->start_virt) + + hevc->chunk->offset; + for (jj = 0; jj < size; jj++) + sum += data[jj]; + return sum; +} + +static void vh265_notify_work(struct work_struct *work) +{ + struct hevc_state_s *hevc = + container_of(work, + struct hevc_state_s, + notify_work); + struct vdec_s *vdec = hw_to_vdec(hevc); +#ifdef MULTI_INSTANCE_SUPPORT + if (vdec->fr_hint_state == VDEC_NEED_HINT) { + vf_notify_receiver(hevc->provider_name, + VFRAME_EVENT_PROVIDER_FR_HINT, + (void *) + ((unsigned long)hevc->frame_dur)); + vdec->fr_hint_state = VDEC_HINTED; + } else if (fr_hint_status == VDEC_NEED_HINT) { + vf_notify_receiver(hevc->provider_name, + VFRAME_EVENT_PROVIDER_FR_HINT, + (void *) + ((unsigned long)hevc->frame_dur)); + fr_hint_status = VDEC_HINTED; + } +#else + if (fr_hint_status == VDEC_NEED_HINT) + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_FR_HINT, + (void *) + ((unsigned long)hevc->frame_dur)); + fr_hint_status = VDEC_HINTED; + } +#endif + + return; +} + +static void vh265_work(struct work_struct *work) +{ + struct hevc_state_s *hevc = container_of(work, + struct hevc_state_s, work); + struct vdec_s *vdec = hw_to_vdec(hevc); + + if (hevc->uninit_list) { + /*USE_BUF_BLOCK*/ + uninit_pic_list(hevc); + hevc_print(hevc, 0, "uninit list\n"); + hevc->uninit_list = 0; +#ifdef USE_UNINIT_SEMA + up(&hevc->h265_uninit_done_sema); +#endif + return; + } + + /* finished decoding one frame or error, + * notify vdec core to switch context + */ + if (hevc->pic_list_init_flag == 1 + && (hevc->dec_result != DEC_RESULT_FORCE_EXIT)) { + hevc->pic_list_init_flag = 2; + init_pic_list(hevc); + init_pic_list_hw(hevc); + init_buf_spec(hevc); + hevc_print(hevc, 0, + "set pic_list_init_flag to 2\n"); + + WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1); + return; + } + + hevc_print(hevc, PRINT_FLAG_VDEC_DETAIL, + "%s dec_result %d %x %x %x\n", + __func__, + hevc->dec_result, + READ_VREG(HEVC_STREAM_LEVEL), + READ_VREG(HEVC_STREAM_WR_PTR), + READ_VREG(HEVC_STREAM_RD_PTR)); + + if (((hevc->dec_result == DEC_RESULT_GET_DATA) || + (hevc->dec_result == DEC_RESULT_GET_DATA_RETRY)) + && (hw_to_vdec(hevc)->next_status != + VDEC_STATUS_DISCONNECTED)) { + if (!vdec_has_more_input(vdec)) { + hevc->dec_result = DEC_RESULT_EOS; + vdec_schedule_work(&hevc->work); + return; + } + if (!input_frame_based(vdec)) { + int r = vdec_sync_input(vdec); + if (r >= 0x200) { + WRITE_VREG(HEVC_DECODE_SIZE, + READ_VREG(HEVC_DECODE_SIZE) + r); + + hevc_print(hevc, PRINT_FLAG_VDEC_STATUS, + "%s DEC_RESULT_GET_DATA %x %x %x mpc %x size 0x%x\n", + __func__, + READ_VREG(HEVC_STREAM_LEVEL), + READ_VREG(HEVC_STREAM_WR_PTR), + READ_VREG(HEVC_STREAM_RD_PTR), + READ_VREG(HEVC_MPC_E), r); + + start_process_time(hevc); + if (READ_VREG(HEVC_DEC_STATUS_REG) + == HEVC_DECODE_BUFEMPTY2) + WRITE_VREG(HEVC_DEC_STATUS_REG, + HEVC_ACTION_DONE); + else + WRITE_VREG(HEVC_DEC_STATUS_REG, + HEVC_ACTION_DEC_CONT); + } else { + hevc->dec_result = DEC_RESULT_GET_DATA_RETRY; + vdec_schedule_work(&hevc->work); + } + return; + } + + /*below for frame_base*/ + if (hevc->dec_result == DEC_RESULT_GET_DATA) { + hevc_print(hevc, PRINT_FLAG_VDEC_STATUS, + "%s DEC_RESULT_GET_DATA %x %x %x mpc %x\n", + __func__, + READ_VREG(HEVC_STREAM_LEVEL), + READ_VREG(HEVC_STREAM_WR_PTR), + READ_VREG(HEVC_STREAM_RD_PTR), + READ_VREG(HEVC_MPC_E)); + vdec_vframe_dirty(vdec, hevc->chunk); + vdec_clean_input(vdec); + } + + /*if (is_new_pic_available(hevc)) {*/ + if (run_ready(vdec, VDEC_HEVC)) { + int r; + int decode_size; + r = vdec_prepare_input(vdec, &hevc->chunk); + if (r < 0) { + hevc->dec_result = DEC_RESULT_GET_DATA_RETRY; + + hevc_print(hevc, + PRINT_FLAG_VDEC_DETAIL, + "amvdec_vh265: Insufficient data\n"); + + vdec_schedule_work(&hevc->work); + return; + } + hevc->dec_result = DEC_RESULT_NONE; + hevc_print(hevc, PRINT_FLAG_VDEC_STATUS, + "%s: chunk size 0x%x sum 0x%x mpc %x\n", + __func__, r, + (get_dbg_flag(hevc) & PRINT_FLAG_VDEC_STATUS) ? + get_data_check_sum(hevc, r) : 0, + READ_VREG(HEVC_MPC_E)); + + if (get_dbg_flag(hevc) & PRINT_FRAMEBASE_DATA) { + int jj; + u8 *data = + ((u8 *)hevc->chunk->block->start_virt) + + hevc->chunk->offset; + for (jj = 0; jj < r; jj++) { + if ((jj & 0xf) == 0) + hevc_print(hevc, + PRINT_FRAMEBASE_DATA, + "%06x:", jj); + hevc_print_cont(hevc, + PRINT_FRAMEBASE_DATA, + "%02x ", data[jj]); + if (((jj + 1) & 0xf) == 0) + hevc_print_cont(hevc, + PRINT_FRAMEBASE_DATA, + "\n"); + } + } + + decode_size = hevc->chunk->size + + (hevc->chunk->offset & (VDEC_FIFO_ALIGN - 1)); + WRITE_VREG(HEVC_DECODE_SIZE, + READ_VREG(HEVC_DECODE_SIZE) + decode_size); + + vdec_enable_input(vdec); + + hevc_print(hevc, PRINT_FLAG_VDEC_STATUS, + "%s: mpc %x\n", + __func__, READ_VREG(HEVC_MPC_E)); + + start_process_time(hevc); + WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE); + } else{ + hevc->dec_result = DEC_RESULT_GET_DATA_RETRY; + + /*hevc_print(hevc, PRINT_FLAG_VDEC_DETAIL, + * "amvdec_vh265: Insufficient data\n"); + */ + + vdec_schedule_work(&hevc->work); + } + return; + } else if (hevc->dec_result == DEC_RESULT_DONE) { + /* if (!hevc->ctx_valid) + hevc->ctx_valid = 1; */ + decode_frame_count[hevc->index]++; + if (hevc->mmu_enable) { + hevc->used_4k_num = + READ_VREG(HEVC_SAO_MMU_STATUS) >> 16; + if (hevc->used_4k_num >= 0 && + hevc->cur_pic && + hevc->cur_pic->scatter_alloc + == 1) { + hevc_print(hevc, H265_DEBUG_BUFMGR_MORE, + "%s pic index %d scatter_alloc %d page_start %d\n", + "decoder_mmu_box_free_idx_tail", + hevc->cur_pic->index, + hevc->cur_pic->scatter_alloc, + hevc->used_4k_num); + decoder_mmu_box_free_idx_tail( + hevc->mmu_box, + hevc->cur_pic->index, + hevc->used_4k_num); + hevc->cur_pic->scatter_alloc = 2; + } + } + hevc->pic_decoded_lcu_idx = + READ_VREG(HEVC_PARSER_LCU_START) + & 0xffffff; + hevc->over_decode = + (READ_VREG(HEVC_SHIFT_STATUS) >> 15) & 0x1; + if (hevc->over_decode) + hevc_print(hevc, 0, + "!!!Over decode\n"); + + if (is_log_enable(hevc)) + add_log(hevc, + "%s dec_result %d lcu %d used_mmu %d shiftbyte 0x%x decbytes 0x%x", + __func__, + hevc->dec_result, + hevc->pic_decoded_lcu_idx, + hevc->used_4k_num, + READ_VREG(HEVC_SHIFT_BYTE_COUNT), + READ_VREG(HEVC_SHIFT_BYTE_COUNT) - + hevc->start_shift_bytes + ); + + hevc_print(hevc, PRINT_FLAG_VDEC_STATUS, + "%s dec_result %d (%x %x %x) lcu %d used_mmu %d shiftbyte 0x%x decbytes 0x%x\n", + __func__, + hevc->dec_result, + READ_VREG(HEVC_STREAM_LEVEL), + READ_VREG(HEVC_STREAM_WR_PTR), + READ_VREG(HEVC_STREAM_RD_PTR), + hevc->pic_decoded_lcu_idx, + hevc->used_4k_num, + READ_VREG(HEVC_SHIFT_BYTE_COUNT), + READ_VREG(HEVC_SHIFT_BYTE_COUNT) - + hevc->start_shift_bytes + ); + + hevc->used_4k_num = -1; + + check_pic_decoded_error(hevc, + hevc->pic_decoded_lcu_idx); +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION +#if 1 + if (vdec->slave) { + if (dv_debug & 0x1) + vdec_set_flag(vdec->slave, + VDEC_FLAG_SELF_INPUT_CONTEXT); + else + vdec_set_flag(vdec->slave, + VDEC_FLAG_OTHER_INPUT_CONTEXT); + } +#else + if (vdec->slave) { + if (no_interleaved_el_slice) + vdec_set_flag(vdec->slave, + VDEC_FLAG_INPUT_KEEP_CONTEXT); + /* this will move real HW pointer for input */ + else + vdec_set_flag(vdec->slave, 0); + /* this will not move real HW pointer + *and SL layer decoding + *will start from same stream position + *as current BL decoder + */ + } +#endif +#endif +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + hevc->shift_byte_count_lo + = READ_VREG(HEVC_SHIFT_BYTE_COUNT); + if (vdec->slave) { + /*cur is base, found enhance*/ + struct hevc_state_s *hevc_el = + (struct hevc_state_s *) + vdec->slave->private; + if (hevc_el) + hevc_el->shift_byte_count_lo = + hevc->shift_byte_count_lo; + } else if (vdec->master) { + /*cur is enhance, found base*/ + struct hevc_state_s *hevc_ba = + (struct hevc_state_s *) + vdec->master->private; + if (hevc_ba) + hevc_ba->shift_byte_count_lo = + hevc->shift_byte_count_lo; + } +#endif + vdec_vframe_dirty(hw_to_vdec(hevc), hevc->chunk); + } else if (hevc->dec_result == DEC_RESULT_AGAIN) { + /* + stream base: stream buf empty or timeout + frame base: vdec_prepare_input fail + */ + if (!vdec_has_more_input(vdec)) { + hevc->dec_result = DEC_RESULT_EOS; + vdec_schedule_work(&hevc->work); + return; + } +#ifdef AGAIN_HAS_THRESHOLD + hevc->next_again_flag = 1; +#endif + } else if (hevc->dec_result == DEC_RESULT_EOS) { + struct PIC_s *pic; + hevc->eos = 1; +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + if ((vdec->master || vdec->slave) && + READ_VREG(HEVC_AUX_DATA_SIZE) != 0) + dolby_get_meta(hevc); +#endif + check_pic_decoded_error(hevc, + hevc->pic_decoded_lcu_idx); + pic = get_pic_by_POC(hevc, hevc->curr_POC); + hevc_print(hevc, PRINT_FLAG_VDEC_STATUS, + "%s: end of stream, last dec poc %d => 0x%pf\n", + __func__, hevc->curr_POC, pic); + flush_output(hevc, pic); +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + hevc->shift_byte_count_lo + = READ_VREG(HEVC_SHIFT_BYTE_COUNT); + if (vdec->slave) { + /*cur is base, found enhance*/ + struct hevc_state_s *hevc_el = + (struct hevc_state_s *) + vdec->slave->private; + if (hevc_el) + hevc_el->shift_byte_count_lo = + hevc->shift_byte_count_lo; + } else if (vdec->master) { + /*cur is enhance, found base*/ + struct hevc_state_s *hevc_ba = + (struct hevc_state_s *) + vdec->master->private; + if (hevc_ba) + hevc_ba->shift_byte_count_lo = + hevc->shift_byte_count_lo; + } +#endif + vdec_vframe_dirty(hw_to_vdec(hevc), hevc->chunk); + } else if (hevc->dec_result == DEC_RESULT_FORCE_EXIT) { + hevc_print(hevc, PRINT_FLAG_VDEC_STATUS, + "%s: force exit\n", + __func__); + if (hevc->stat & STAT_VDEC_RUN) { + amhevc_stop(); + hevc->stat &= ~STAT_VDEC_RUN; + } + if (hevc->stat & STAT_ISR_REG) { + WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0); + vdec_free_irq(VDEC_IRQ_0, (void *)hevc); + hevc->stat &= ~STAT_ISR_REG; + } + hevc_print(hevc, 0, "%s: force exit end\n", + __func__); + } + + if (hevc->stat & STAT_VDEC_RUN) { + amhevc_stop(); + hevc->stat &= ~STAT_VDEC_RUN; + } + + if (hevc->stat & STAT_TIMER_ARM) { + del_timer_sync(&hevc->timer); + hevc->stat &= ~STAT_TIMER_ARM; + } + + wait_hevc_search_done(hevc); +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + if (hevc->switch_dvlayer_flag) { + if (vdec->slave) + vdec_set_next_sched(vdec, vdec->slave); + else if (vdec->master) + vdec_set_next_sched(vdec, vdec->master); + } else if (vdec->slave || vdec->master) + vdec_set_next_sched(vdec, vdec); +#endif + + /* mark itself has all HW resource released and input released */ + vdec_core_finish_run(vdec, CORE_MASK_VDEC_1 | CORE_MASK_HEVC); + + + if (hevc->vdec_cb) + hevc->vdec_cb(hw_to_vdec(hevc), hevc->vdec_cb_arg); +} + +static int vh265_hw_ctx_restore(struct hevc_state_s *hevc) +{ + /* new to do ... */ + vh265_prot_init(hevc); + return 0; +} + +static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask) +{ + struct hevc_state_s *hevc = + (struct hevc_state_s *)vdec->private; + bool ret = 0; + if (step == 0x12) + return 0; + else if (step == 0x11) + step = 0x12; + + if (hevc->eos) + return 0; +#ifdef AGAIN_HAS_THRESHOLD + if (hevc->next_again_flag && + (!vdec_frame_based(vdec))) { + u32 parser_wr_ptr = + READ_PARSER_REG(PARSER_VIDEO_WP); + if (parser_wr_ptr >= hevc->pre_parser_wr_ptr && + (parser_wr_ptr - hevc->pre_parser_wr_ptr) < + again_threshold) + return 0; + } +#endif + + if (disp_vframe_valve_level && + kfifo_len(&hevc->display_q) >= + disp_vframe_valve_level) { + hevc->valve_count--; + if (hevc->valve_count <= 0) + hevc->valve_count = 2; + else + return 0; + } + + ret = is_new_pic_available(hevc); + if (!ret) { + hevc_print(hevc, + PRINT_FLAG_VDEC_DETAIL, "%s=>%d\r\n", + __func__, ret); + } + if (ret) + not_run_ready[hevc->index] = 0; + else + not_run_ready[hevc->index]++; + return ret ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0; +} + +static void run(struct vdec_s *vdec, unsigned long mask, + void (*callback)(struct vdec_s *, void *), void *arg) +{ + struct hevc_state_s *hevc = + (struct hevc_state_s *)vdec->private; + int r, loadr = 0; + unsigned char check_sum = 0; + + run_count[hevc->index]++; + hevc->vdec_cb_arg = arg; + hevc->vdec_cb = callback; + + hevc_reset_core(vdec); + +#ifdef AGAIN_HAS_THRESHOLD + hevc->pre_parser_wr_ptr = + READ_PARSER_REG(PARSER_VIDEO_WP); + hevc->next_again_flag = 0; +#endif + r = vdec_prepare_input(vdec, &hevc->chunk); + if (r < 0) { + input_empty[hevc->index]++; + hevc->dec_result = DEC_RESULT_AGAIN; + + hevc_print(hevc, PRINT_FLAG_VDEC_DETAIL, + "ammvdec_vh265: Insufficient data\n"); + + vdec_schedule_work(&hevc->work); + return; + } + input_empty[hevc->index] = 0; + hevc->dec_result = DEC_RESULT_NONE; + + if (vdec_frame_based(vdec) && + ((get_dbg_flag(hevc) & PRINT_FLAG_VDEC_STATUS) + || is_log_enable(hevc))) + check_sum = get_data_check_sum(hevc, r); + + if (is_log_enable(hevc)) + add_log(hevc, + "%s: size 0x%x sum 0x%x shiftbyte 0x%x", + __func__, r, + check_sum, + READ_VREG(HEVC_SHIFT_BYTE_COUNT) + ); + hevc->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT); + hevc_print(hevc, PRINT_FLAG_VDEC_STATUS, + "%s: size 0x%x sum 0x%x (%x %x %x %x %x) byte count %x\n", + __func__, r, + check_sum, + READ_VREG(HEVC_STREAM_LEVEL), + READ_VREG(HEVC_STREAM_WR_PTR), + READ_VREG(HEVC_STREAM_RD_PTR), + READ_PARSER_REG(PARSER_VIDEO_RP), + READ_PARSER_REG(PARSER_VIDEO_WP), + hevc->start_shift_bytes + ); + if ((get_dbg_flag(hevc) & PRINT_FRAMEBASE_DATA) && + input_frame_based(vdec)) { + int jj; + u8 *data = ((u8 *)hevc->chunk->block->start_virt) + + hevc->chunk->offset; + for (jj = 0; jj < r; jj++) { + if ((jj & 0xf) == 0) + hevc_print(hevc, PRINT_FRAMEBASE_DATA, + "%06x:", jj); + hevc_print_cont(hevc, PRINT_FRAMEBASE_DATA, + "%02x ", data[jj]); + if (((jj + 1) & 0xf) == 0) + hevc_print_cont(hevc, PRINT_FRAMEBASE_DATA, + "\n"); + } + } + + if (hevc->mmu_enable) { + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) + loadr = amhevc_vdec_loadmc_ex(vdec, + "vh265_mc", hevc->fw->data); + else + loadr = amhevc_vdec_loadmc_ex(vdec, + "vh265_mc_mmu", hevc->fw->data); + } else + loadr = amhevc_vdec_loadmc_ex(vdec, + "vh265_mc", hevc->fw->data); + + if (loadr < 0) { + amhevc_disable(); + hevc_print(hevc, 0, + "%s: Error amvdec_loadmc fail\n", + __func__); + return; + } + + if (vh265_hw_ctx_restore(hevc) < 0) { + vdec_schedule_work(&hevc->work); + return; + } + + vdec_enable_input(vdec); + + WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE); + + if (vdec_frame_based(vdec)) { + WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0); + r = hevc->chunk->size + + (hevc->chunk->offset & (VDEC_FIFO_ALIGN - 1)); + } +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + else { + if (vdec->master || vdec->slave) + WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, + hevc->shift_byte_count_lo); + } +#endif + WRITE_VREG(HEVC_DECODE_SIZE, r); + /*WRITE_VREG(HEVC_DECODE_COUNT, hevc->decode_idx);*/ + hevc->init_flag = 1; + + if (hevc->pic_list_init_flag == 3) + init_pic_list_hw(hevc); + + backup_decode_state(hevc); + + start_process_time(hevc); + mod_timer(&hevc->timer, jiffies); + hevc->stat |= STAT_TIMER_ARM; + hevc->stat |= STAT_ISR_REG; + amhevc_start(); + hevc->stat |= STAT_VDEC_RUN; +} + +static void reset(struct vdec_s *vdec) +{ + + struct hevc_state_s *hevc = + (struct hevc_state_s *)vdec->private; + + hevc_print(hevc, + PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__); + +} + +static irqreturn_t vh265_irq_cb(struct vdec_s *vdec, int irq) +{ + struct hevc_state_s *hevc = + (struct hevc_state_s *)vdec->private; + + return vh265_isr(0, hevc); +} + +static irqreturn_t vh265_threaded_irq_cb(struct vdec_s *vdec, int irq) +{ + struct hevc_state_s *hevc = + (struct hevc_state_s *)vdec->private; + + return vh265_isr_thread_fn(0, hevc); +} +#endif + +static int amvdec_h265_probe(struct platform_device *pdev) +{ +#ifdef MULTI_INSTANCE_SUPPORT + struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; +#else + struct vdec_dev_reg_s *pdata = + (struct vdec_dev_reg_s *)pdev->dev.platform_data; +#endif + int ret; + struct hevc_state_s *hevc; + + hevc = vmalloc(sizeof(struct hevc_state_s)); + if (hevc == NULL) { + hevc_print(hevc, 0, "%s vmalloc hevc failed\r\n", __func__); + return -ENOMEM; + } + gHevc = hevc; + if ((debug & H265_NO_CHANG_DEBUG_FLAG_IN_CODE) == 0) + debug &= (~(H265_DEBUG_DIS_LOC_ERROR_PROC | + H265_DEBUG_DIS_SYS_ERROR_PROC)); + memset(hevc, 0, sizeof(struct hevc_state_s)); + if (get_dbg_flag(hevc)) + hevc_print(hevc, 0, "%s\r\n", __func__); + mutex_lock(&vh265_mutex); + + if ((get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) && + (parser_sei_enable & 0x100) == 0) + parser_sei_enable = 7; /*old 1*/ + hevc->m_ins_flag = 0; + hevc->init_flag = 0; + hevc->uninit_list = 0; + hevc->fatal_error = 0; + hevc->show_frame_num = 0; +#ifdef MULTI_INSTANCE_SUPPORT + hevc->platform_dev = pdev; + platform_set_drvdata(pdev, pdata); +#endif + + if (pdata == NULL) { + hevc_print(hevc, 0, + "\namvdec_h265 memory resource undefined.\n"); + vfree(hevc); + mutex_unlock(&vh265_mutex); + return -EFAULT; + } + if (mmu_enable_force == 0) { + if (get_cpu_type() < MESON_CPU_MAJOR_ID_GXL + || double_write_mode == 0x10) + hevc->mmu_enable = 0; + else + hevc->mmu_enable = 1; + } + if (init_mmu_buffers(hevc)) { + hevc_print(hevc, 0, + "\n 265 mmu init failed!\n"); + vfree(hevc); + mutex_unlock(&vh265_mutex); + return -EFAULT; + } + + ret = decoder_bmmu_box_alloc_buf_phy(hevc->bmmu_box, BMMU_WORKSPACE_ID, + work_buf_size, DRIVER_NAME, &hevc->buf_start); + if (ret < 0) { + uninit_mmu_buffers(hevc); + devm_kfree(&pdev->dev, (void *)hevc); + vfree(hevc); + mutex_unlock(&vh265_mutex); + return ret; + } + hevc->buf_size = work_buf_size; + + if (get_dbg_flag(hevc)) { + hevc_print(hevc, 0, + "===H.265 decoder mem resource 0x%lx size 0x%x\n", + hevc->buf_start, hevc->buf_size); + } + + if (pdata->sys_info) + hevc->vh265_amstream_dec_info = *pdata->sys_info; + else { + hevc->vh265_amstream_dec_info.width = 0; + hevc->vh265_amstream_dec_info.height = 0; + hevc->vh265_amstream_dec_info.rate = 30; + } +#ifndef MULTI_INSTANCE_SUPPORT + if (pdata->flag & DEC_FLAG_HEVC_WORKAROUND) { + workaround_enable |= 3; + hevc_print(hevc, 0, + "amvdec_h265 HEVC_WORKAROUND flag set.\n"); + } else + workaround_enable &= ~3; +#endif + hevc->cma_dev = pdata->cma_dev; + vh265_vdec_info_init(); + +#ifdef MULTI_INSTANCE_SUPPORT + pdata->private = hevc; + pdata->dec_status = vh265_dec_status; + pdata->set_isreset = vh265_set_isreset; + is_reset = 0; + if (vh265_init(pdata) < 0) { +#else + if (vh265_init(hevc) < 0) { +#endif + hevc_print(hevc, 0, + "\namvdec_h265 init failed.\n"); + hevc_local_uninit(hevc); + uninit_mmu_buffers(hevc); + vfree(hevc); + mutex_unlock(&vh265_mutex); + return -ENODEV; + } + /*set the max clk for smooth playing...*/ + hevc_source_changed(VFORMAT_HEVC, + 3840, 2160, 60); + mutex_unlock(&vh265_mutex); + + return 0; +} + +static int amvdec_h265_remove(struct platform_device *pdev) +{ + struct hevc_state_s *hevc = gHevc; + + if (get_dbg_flag(hevc)) + hevc_print(hevc, 0, "%s\r\n", __func__); + + mutex_lock(&vh265_mutex); + + vh265_stop(hevc); + + hevc_source_changed(VFORMAT_HEVC, 0, 0, 0); + + +#ifdef DEBUG_PTS + hevc_print(hevc, 0, + "pts missed %ld, pts hit %ld, duration %d\n", + hevc->pts_missed, hevc->pts_hit, hevc->frame_dur); +#endif + + vfree(hevc); + hevc = NULL; + gHevc = NULL; + + mutex_unlock(&vh265_mutex); + + return 0; +} +/****************************************/ + +static struct platform_driver amvdec_h265_driver = { + .probe = amvdec_h265_probe, + .remove = amvdec_h265_remove, +#ifdef CONFIG_PM + .suspend = amhevc_suspend, + .resume = amhevc_resume, +#endif + .driver = { + .name = DRIVER_NAME, + } +}; + +#ifdef MULTI_INSTANCE_SUPPORT +static void vh265_dump_state(struct vdec_s *vdec) +{ + int i; + struct hevc_state_s *hevc = + (struct hevc_state_s *)vdec->private; + hevc_print(hevc, 0, + "====== %s\n", __func__); + + hevc_print(hevc, 0, + "width/height (%d/%d), reorder_pic_num %d buf count(bufspec size) %d\n", + hevc->frame_width, + hevc->frame_height, + hevc->sps_num_reorder_pics_0, + get_work_pic_num(hevc) + ); + + hevc_print(hevc, 0, + "is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d\n", + input_frame_based(vdec), + hevc->eos, + hevc->dec_result, + decode_frame_count[hevc->index], + display_frame_count[hevc->index], + run_count[hevc->index], + not_run_ready[hevc->index], + input_empty[hevc->index] + ); + + if (vf_get_receiver(vdec->vf_provider_name)) { + enum receviver_start_e state = + vf_notify_receiver(vdec->vf_provider_name, + VFRAME_EVENT_PROVIDER_QUREY_STATE, + NULL); + hevc_print(hevc, 0, + "\nreceiver(%s) state %d\n", + vdec->vf_provider_name, + state); + } + + hevc_print(hevc, 0, + "%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), pic_list_init_flag(%d), is_new_pic_available(%d)\n", + __func__, + kfifo_len(&hevc->newframe_q), + VF_POOL_SIZE, + kfifo_len(&hevc->display_q), + VF_POOL_SIZE, + hevc->vf_pre_count, + hevc->vf_get_count, + hevc->vf_put_count, + hevc->pic_list_init_flag, + is_new_pic_available(hevc) + ); + + dump_pic_list(hevc); + + for (i = 0; i < BUF_POOL_SIZE; i++) { + hevc_print(hevc, 0, + "Buf(%d) start_adr 0x%x size 0x%x used %d\n", + i, + hevc->m_BUF[i].start_adr, + hevc->m_BUF[i].size, + hevc->m_BUF[i].used_flag); + } + + for (i = 0; i < MAX_REF_PIC_NUM; i++) { + hevc_print(hevc, 0, + "mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n", + i, + hevc->m_mv_BUF[i].start_adr, + hevc->m_mv_BUF[i].size, + hevc->m_mv_BUF[i].used_flag); + } + + hevc_print(hevc, 0, + "HEVC_DEC_STATUS_REG=0x%x\n", + READ_VREG(HEVC_DEC_STATUS_REG)); + hevc_print(hevc, 0, + "HEVC_MPC_E=0x%x\n", + READ_VREG(HEVC_MPC_E)); + hevc_print(hevc, 0, + "HEVC_DECODE_MODE=0x%x\n", + READ_VREG(HEVC_DECODE_MODE)); + hevc_print(hevc, 0, + "HEVC_DECODE_MODE2=0x%x\n", + READ_VREG(HEVC_DECODE_MODE2)); + hevc_print(hevc, 0, + "NAL_SEARCH_CTL=0x%x\n", + READ_VREG(NAL_SEARCH_CTL)); + hevc_print(hevc, 0, + "HEVC_PARSER_LCU_START=0x%x\n", + READ_VREG(HEVC_PARSER_LCU_START)); + hevc_print(hevc, 0, + "HEVC_DECODE_SIZE=0x%x\n", + READ_VREG(HEVC_DECODE_SIZE)); + hevc_print(hevc, 0, + "HEVC_SHIFT_BYTE_COUNT=0x%x\n", + READ_VREG(HEVC_SHIFT_BYTE_COUNT)); + hevc_print(hevc, 0, + "HEVC_STREAM_START_ADDR=0x%x\n", + READ_VREG(HEVC_STREAM_START_ADDR)); + hevc_print(hevc, 0, + "HEVC_STREAM_END_ADDR=0x%x\n", + READ_VREG(HEVC_STREAM_END_ADDR)); + hevc_print(hevc, 0, + "HEVC_STREAM_LEVEL=0x%x\n", + READ_VREG(HEVC_STREAM_LEVEL)); + hevc_print(hevc, 0, + "HEVC_STREAM_WR_PTR=0x%x\n", + READ_VREG(HEVC_STREAM_WR_PTR)); + hevc_print(hevc, 0, + "HEVC_STREAM_RD_PTR=0x%x\n", + READ_VREG(HEVC_STREAM_RD_PTR)); + hevc_print(hevc, 0, + "PARSER_VIDEO_RP=0x%x\n", + READ_PARSER_REG(PARSER_VIDEO_RP)); + hevc_print(hevc, 0, + "PARSER_VIDEO_WP=0x%x\n", + READ_PARSER_REG(PARSER_VIDEO_WP)); + + if (input_frame_based(vdec) && + (get_dbg_flag(hevc) & PRINT_FRAMEBASE_DATA) + ) { + int jj; + if (hevc->chunk && hevc->chunk->block && + hevc->chunk->size > 0) { + u8 *data = + ((u8 *)hevc->chunk->block->start_virt) + + hevc->chunk->offset; + hevc_print(hevc, 0, + "frame data size 0x%x\n", + hevc->chunk->size); + for (jj = 0; jj < hevc->chunk->size; jj++) { + if ((jj & 0xf) == 0) + hevc_print(hevc, + PRINT_FRAMEBASE_DATA, + "%06x:", jj); + hevc_print_cont(hevc, + PRINT_FRAMEBASE_DATA, + "%02x ", data[jj]); + if (((jj + 1) & 0xf) == 0) + hevc_print_cont(hevc, + PRINT_FRAMEBASE_DATA, + "\n"); + } + } + } + +} + +static int ammvdec_h265_probe(struct platform_device *pdev) +{ + + struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; + struct hevc_state_s *hevc = NULL; + int ret; +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + int config_val; +#endif + if (pdata == NULL) { + pr_info("\nammvdec_h265 memory resource undefined.\n"); + return -EFAULT; + } + + /* hevc = (struct hevc_state_s *)devm_kzalloc(&pdev->dev, + sizeof(struct hevc_state_s), GFP_KERNEL); */ + hevc = vmalloc(sizeof(struct hevc_state_s)); + memset(hevc, 0, sizeof(struct hevc_state_s)); + if (hevc == NULL) { + pr_info("\nammvdec_h265 device data allocation failed\n"); + return -ENOMEM; + } + pdata->private = hevc; + pdata->dec_status = vh265_dec_status; + /* pdata->set_trickmode = set_trickmode; */ + pdata->run_ready = run_ready; + pdata->run = run; + pdata->reset = reset; + pdata->irq_handler = vh265_irq_cb; + pdata->threaded_irq_handler = vh265_threaded_irq_cb; + pdata->dump_state = vh265_dump_state; + + hevc->index = pdev->id; + + if (pdata->use_vfm_path) + snprintf(pdata->vf_provider_name, + VDEC_PROVIDER_NAME_SIZE, + VFM_DEC_PROVIDER_NAME); +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + else if (vdec_dual(pdata)) { + struct hevc_state_s *hevc_pair = NULL; + + if (dv_toggle_prov_name) /*debug purpose*/ + snprintf(pdata->vf_provider_name, + VDEC_PROVIDER_NAME_SIZE, + (pdata->master) ? VFM_DEC_DVBL_PROVIDER_NAME : + VFM_DEC_DVEL_PROVIDER_NAME); + else + snprintf(pdata->vf_provider_name, + VDEC_PROVIDER_NAME_SIZE, + (pdata->master) ? VFM_DEC_DVEL_PROVIDER_NAME : + VFM_DEC_DVBL_PROVIDER_NAME); + hevc->dolby_enhance_flag = pdata->master ? 1 : 0; + if (pdata->master) + hevc_pair = (struct hevc_state_s *) + pdata->master->private; + else if (pdata->slave) + hevc_pair = (struct hevc_state_s *) + pdata->slave->private; + if (hevc_pair) + hevc->shift_byte_count_lo = + hevc_pair->shift_byte_count_lo; + } +#endif + else + snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE, + MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff); + + vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name, + &vh265_vf_provider, pdata); + + hevc->provider_name = pdata->vf_provider_name; + platform_set_drvdata(pdev, pdata); + + hevc->platform_dev = pdev; + + if (((get_dbg_flag(hevc) & IGNORE_PARAM_FROM_CONFIG) == 0) && + pdata->config && pdata->config_len) { +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + /*use ptr config for doubel_write_mode, etc*/ + hevc_print(hevc, 0, "pdata->config=%s\n", pdata->config); + + if (get_config_int(pdata->config, "hevc_double_write_mode", + &config_val) == 0) + hevc->double_write_mode = config_val; + else + hevc->double_write_mode = double_write_mode; + + /*use ptr config for max_pic_w, etc*/ + if (get_config_int(pdata->config, "hevc_buf_width", + &config_val) == 0) { + hevc->max_pic_w = config_val; + } + if (get_config_int(pdata->config, "hevc_buf_height", + &config_val) == 0) { + hevc->max_pic_h = config_val; + } + +#endif + } else { + hevc->vh265_amstream_dec_info.width = 0; + hevc->vh265_amstream_dec_info.height = 0; + hevc->vh265_amstream_dec_info.rate = 30; + hevc->dynamic_buf_num_margin = dynamic_buf_num_margin; + hevc->double_write_mode = double_write_mode; + } + + if (mmu_enable_force == 0) { + if (get_cpu_type() < MESON_CPU_MAJOR_ID_GXL + || hevc->double_write_mode == 0x10) + hevc->mmu_enable = 0; + else + hevc->mmu_enable = 1; + } + + if (init_mmu_buffers(hevc) < 0) { + hevc_print(hevc, 0, + "\n 265 mmu init failed!\n"); + mutex_unlock(&vh265_mutex); + /* devm_kfree(&pdev->dev, (void *)hevc);*/ + if (hevc) + vfree((void *)hevc); + return -EFAULT; + } +#if 0 + hevc->buf_start = pdata->mem_start; + hevc->buf_size = pdata->mem_end - pdata->mem_start + 1; +#else + + ret = decoder_bmmu_box_alloc_buf_phy(hevc->bmmu_box, + BMMU_WORKSPACE_ID, work_buf_size, + DRIVER_NAME, &hevc->buf_start); + if (ret < 0) { + uninit_mmu_buffers(hevc); + /* devm_kfree(&pdev->dev, (void *)hevc); */ + if (hevc) + vfree((void *)hevc); + mutex_unlock(&vh265_mutex); + return ret; + } + hevc->buf_size = work_buf_size; +#endif + if ((get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) && + (parser_sei_enable & 0x100) == 0) + parser_sei_enable = 7; + hevc->m_ins_flag = 1; + hevc->init_flag = 0; + hevc->uninit_list = 0; + hevc->fatal_error = 0; + hevc->show_frame_num = 0; + if (pdata == NULL) { + hevc_print(hevc, 0, + "\namvdec_h265 memory resource undefined.\n"); + uninit_mmu_buffers(hevc); + /* devm_kfree(&pdev->dev, (void *)hevc); */ + if (hevc) + vfree((void *)hevc); + return -EFAULT; + } + /* + *hevc->mc_buf_spec.buf_end = pdata->mem_end + 1; + *for (i = 0; i < WORK_BUF_SPEC_NUM; i++) + * amvh265_workbuff_spec[i].start_adr = pdata->mem_start; + */ + if (get_dbg_flag(hevc)) { + hevc_print(hevc, 0, + "===H.265 decoder mem resource 0x%lx size 0x%x\n", + hevc->buf_start, hevc->buf_size); + } + + hevc_print(hevc, 0, + "dynamic_buf_num_margin=%d\n", + hevc->dynamic_buf_num_margin); + hevc_print(hevc, 0, + "double_write_mode=%d\n", + hevc->double_write_mode); + + hevc->cma_dev = pdata->cma_dev; + + if (vh265_init(pdata) < 0) { + hevc_print(hevc, 0, + "\namvdec_h265 init failed.\n"); + hevc_local_uninit(hevc); + uninit_mmu_buffers(hevc); + /* devm_kfree(&pdev->dev, (void *)hevc); */ + if (hevc) + vfree((void *)hevc); + return -ENODEV; + } + + vdec_set_prepare_level(pdata, start_decode_buf_level); + + /*set the max clk for smooth playing...*/ + hevc_source_changed(VFORMAT_HEVC, + 3840, 2160, 60); + + vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC + | CORE_MASK_COMBINE); + + return 0; +} + +static int ammvdec_h265_remove(struct platform_device *pdev) +{ + struct hevc_state_s *hevc = + (struct hevc_state_s *) + (((struct vdec_s *)(platform_get_drvdata(pdev)))->private); + + if (get_dbg_flag(hevc)) + hevc_print(hevc, 0, "%s\r\n", __func__); + + vmh265_stop(hevc); + + /* vdec_source_changed(VFORMAT_H264, 0, 0, 0); */ + + vdec_core_release(hw_to_vdec(hevc), CORE_MASK_HEVC); + + vdec_set_status(hw_to_vdec(hevc), VDEC_STATUS_DISCONNECTED); + if (hevc) + vfree((void *)hevc); + return 0; +} + +static struct platform_driver ammvdec_h265_driver = { + .probe = ammvdec_h265_probe, + .remove = ammvdec_h265_remove, +#ifdef CONFIG_PM + .suspend = amhevc_suspend, + .resume = amhevc_resume, +#endif + .driver = { + .name = MULTI_DRIVER_NAME, + } +}; +#endif + +static struct codec_profile_t amvdec_h265_profile = { + .name = "hevc", + .profile = "" +}; +static struct mconfig h265_configs[] = { + MC_PU32("use_cma", &use_cma), + MC_PU32("bit_depth_luma", &bit_depth_luma), + MC_PU32("bit_depth_chroma", &bit_depth_chroma), + MC_PU32("video_signal_type", &video_signal_type), +#ifdef ERROR_HANDLE_DEBUG + MC_PU32("dbg_nal_skip_flag", &dbg_nal_skip_flag), + MC_PU32("dbg_nal_skip_count", &dbg_nal_skip_count), +#endif + MC_PU32("radr", &radr), + MC_PU32("rval", &rval), + MC_PU32("dbg_cmd", &dbg_cmd), + MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index), + MC_PU32("endian", &endian), + MC_PU32("step", &step), + MC_PU32("udebug_flag", &udebug_flag), + MC_PU32("decode_pic_begin", &decode_pic_begin), + MC_PU32("slice_parse_begin", &slice_parse_begin), + MC_PU32("nal_skip_policy", &nal_skip_policy), + MC_PU32("i_only_flag", &i_only_flag), + MC_PU32("error_handle_policy", &error_handle_policy), + MC_PU32("error_handle_threshold", &error_handle_threshold), + MC_PU32("error_handle_nal_skip_threshold", + &error_handle_nal_skip_threshold), + MC_PU32("error_handle_system_threshold", + &error_handle_system_threshold), + MC_PU32("error_skip_nal_count", &error_skip_nal_count), + MC_PU32("debug", &debug), + MC_PU32("debug_mask", &debug_mask), + MC_PU32("buffer_mode", &buffer_mode), + MC_PU32("double_write_mode", &double_write_mode), + MC_PU32("buf_alloc_width", &buf_alloc_width), + MC_PU32("buf_alloc_height", &buf_alloc_height), + MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin), + MC_PU32("max_buf_num", &max_buf_num), + MC_PU32("buf_alloc_size", &buf_alloc_size), + MC_PU32("buffer_mode_dbg", &buffer_mode_dbg), + MC_PU32("mem_map_mode", &mem_map_mode), + MC_PU32("enable_mem_saving", &enable_mem_saving), + MC_PU32("force_w_h", &force_w_h), + MC_PU32("force_fps", &force_fps), + MC_PU32("max_decoding_time", &max_decoding_time), + MC_PU32("prefix_aux_buf_size", &prefix_aux_buf_size), + MC_PU32("suffix_aux_buf_size", &suffix_aux_buf_size), + MC_PU32("interlace_enable", &interlace_enable), + MC_PU32("pts_unstable", &pts_unstable), + MC_PU32("parser_sei_enable", &parser_sei_enable), + MC_PU32("start_decode_buf_level", &start_decode_buf_level), + MC_PU32("decode_timeout_val", &decode_timeout_val), +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + MC_PU32("parser_dolby_vision_enable", &parser_dolby_vision_enable), + MC_PU32("dv_toggle_prov_name", &dv_toggle_prov_name), + MC_PU32("dv_debug", &dv_debug), +#endif +}; +static struct mconfig_node decoder_265_node; + +static int __init amvdec_h265_driver_init_module(void) +{ + struct BuffInfo_s *p_buf_info; +#ifdef SUPPORT_4K2K + if (vdec_is_support_4k()) + p_buf_info = &amvh265_workbuff_spec[1]; + else + p_buf_info = &amvh265_workbuff_spec[0]; +#else + p_buf_info = &amvh265_workbuff_spec[0]; +#endif + init_buff_spec(NULL, p_buf_info); + work_buf_size = + (p_buf_info->end_adr - p_buf_info->start_adr + + 0xffff) & (~0xffff); + + pr_debug("amvdec_h265 module init\n"); + error_handle_policy = 0; + +#ifdef ERROR_HANDLE_DEBUG + dbg_nal_skip_flag = 0; + dbg_nal_skip_count = 0; +#endif + udebug_flag = 0; + decode_pic_begin = 0; + slice_parse_begin = 0; + step = 0; + buf_alloc_size = 0; + +#ifdef MULTI_INSTANCE_SUPPORT + if (platform_driver_register(&ammvdec_h265_driver)) + pr_err("failed to register ammvdec_h265 driver\n"); + +#endif + if (platform_driver_register(&amvdec_h265_driver)) { + pr_err("failed to register amvdec_h265 driver\n"); + return -ENODEV; + } +#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8*/ + if (!has_hevc_vdec()) { + /* not support hevc */ + amvdec_h265_profile.name = "hevc_unsupport"; + } + if (vdec_is_support_4k()) { + if (is_meson_m8m2_cpu()) { + /* m8m2 support 4k */ + amvdec_h265_profile.profile = "4k"; + } else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) { + amvdec_h265_profile.profile = + "4k, 9bit, 10bit, dwrite, compressed"; + } else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_MG9TV) + amvdec_h265_profile.profile = "4k"; + } +#endif + if (codec_mm_get_total_size() < 80 * SZ_1M) { + pr_info("amvdec_h265 default mmu enabled.\n"); + mmu_enable = 1; + } + + vcodec_profile_register(&amvdec_h265_profile); + INIT_REG_NODE_CONFIGS("media.decoder", &decoder_265_node, + "h265", h265_configs, CONFIG_FOR_RW); + return 0; +} + +static void __exit amvdec_h265_driver_remove_module(void) +{ + pr_debug("amvdec_h265 module remove.\n"); + +#ifdef MULTI_INSTANCE_SUPPORT + platform_driver_unregister(&ammvdec_h265_driver); +#endif + platform_driver_unregister(&amvdec_h265_driver); +} + +/****************************************/ +/* + *module_param(stat, uint, 0664); + *MODULE_PARM_DESC(stat, "\n amvdec_h265 stat\n"); + */ +module_param(use_cma, uint, 0664); +MODULE_PARM_DESC(use_cma, "\n amvdec_h265 use_cma\n"); + +module_param(bit_depth_luma, uint, 0664); +MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_h265 bit_depth_luma\n"); + +module_param(bit_depth_chroma, uint, 0664); +MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_h265 bit_depth_chroma\n"); + +module_param(video_signal_type, uint, 0664); +MODULE_PARM_DESC(video_signal_type, "\n amvdec_h265 video_signal_type\n"); + +#ifdef ERROR_HANDLE_DEBUG +module_param(dbg_nal_skip_flag, uint, 0664); +MODULE_PARM_DESC(dbg_nal_skip_flag, "\n amvdec_h265 dbg_nal_skip_flag\n"); + +module_param(dbg_nal_skip_count, uint, 0664); +MODULE_PARM_DESC(dbg_nal_skip_count, "\n amvdec_h265 dbg_nal_skip_count\n"); +#endif + +module_param(radr, uint, 0664); +MODULE_PARM_DESC(radr, "\n radr\n"); + +module_param(rval, uint, 0664); +MODULE_PARM_DESC(rval, "\n rval\n"); + +module_param(dbg_cmd, uint, 0664); +MODULE_PARM_DESC(dbg_cmd, "\n dbg_cmd\n"); + +module_param(dump_nal, uint, 0664); +MODULE_PARM_DESC(dump_nal, "\n dump_nal\n"); + +module_param(dbg_skip_decode_index, uint, 0664); +MODULE_PARM_DESC(dbg_skip_decode_index, "\n dbg_skip_decode_index\n"); + +module_param(endian, uint, 0664); +MODULE_PARM_DESC(endian, "\n rval\n"); + +module_param(step, uint, 0664); +MODULE_PARM_DESC(step, "\n amvdec_h265 step\n"); + +module_param(decode_pic_begin, uint, 0664); +MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_h265 decode_pic_begin\n"); + +module_param(slice_parse_begin, uint, 0664); +MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_h265 slice_parse_begin\n"); + +module_param(nal_skip_policy, uint, 0664); +MODULE_PARM_DESC(nal_skip_policy, "\n amvdec_h265 nal_skip_policy\n"); + +module_param(i_only_flag, uint, 0664); +MODULE_PARM_DESC(i_only_flag, "\n amvdec_h265 i_only_flag\n"); + +module_param(fast_output_enable, uint, 0664); +MODULE_PARM_DESC(fast_output_enable, "\n amvdec_h265 fast_output_enable\n"); + +module_param(error_handle_policy, uint, 0664); +MODULE_PARM_DESC(error_handle_policy, "\n amvdec_h265 error_handle_policy\n"); + +module_param(error_handle_threshold, uint, 0664); +MODULE_PARM_DESC(error_handle_threshold, + "\n amvdec_h265 error_handle_threshold\n"); + +module_param(error_handle_nal_skip_threshold, uint, 0664); +MODULE_PARM_DESC(error_handle_nal_skip_threshold, + "\n amvdec_h265 error_handle_nal_skip_threshold\n"); + +module_param(error_handle_system_threshold, uint, 0664); +MODULE_PARM_DESC(error_handle_system_threshold, + "\n amvdec_h265 error_handle_system_threshold\n"); + +module_param(error_skip_nal_count, uint, 0664); +MODULE_PARM_DESC(error_skip_nal_count, + "\n amvdec_h265 error_skip_nal_count\n"); + +module_param(debug, uint, 0664); +MODULE_PARM_DESC(debug, "\n amvdec_h265 debug\n"); + +module_param(debug_mask, uint, 0664); +MODULE_PARM_DESC(debug_mask, "\n amvdec_h265 debug mask\n"); + +module_param(log_mask, uint, 0664); +MODULE_PARM_DESC(log_mask, "\n amvdec_h265 log_mask\n"); + +module_param(buffer_mode, uint, 0664); +MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n"); + +module_param(double_write_mode, uint, 0664); +MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n"); + +module_param(buf_alloc_width, uint, 0664); +MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n"); + +module_param(buf_alloc_height, uint, 0664); +MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n"); + +module_param(dynamic_buf_num_margin, uint, 0664); +MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n"); + +module_param(max_buf_num, uint, 0664); +MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n"); + +module_param(buf_alloc_size, uint, 0664); +MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n"); + +#if 0 +module_param(re_config_pic_flag, uint, 0664); +MODULE_PARM_DESC(re_config_pic_flag, "\n re_config_pic_flag\n"); +#endif + +module_param(buffer_mode_dbg, uint, 0664); +MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n"); + +module_param(mem_map_mode, uint, 0664); +MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n"); + +module_param(enable_mem_saving, uint, 0664); +MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n"); + +module_param(force_w_h, uint, 0664); +MODULE_PARM_DESC(force_w_h, "\n force_w_h\n"); + +module_param(force_fps, uint, 0664); +MODULE_PARM_DESC(force_fps, "\n force_fps\n"); + +module_param(max_decoding_time, uint, 0664); +MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n"); + +module_param(prefix_aux_buf_size, uint, 0664); +MODULE_PARM_DESC(prefix_aux_buf_size, "\n prefix_aux_buf_size\n"); + +module_param(suffix_aux_buf_size, uint, 0664); +MODULE_PARM_DESC(suffix_aux_buf_size, "\n suffix_aux_buf_size\n"); + +module_param(interlace_enable, uint, 0664); +MODULE_PARM_DESC(interlace_enable, "\n interlace_enable\n"); +module_param(pts_unstable, uint, 0664); +MODULE_PARM_DESC(pts_unstable, "\n amvdec_h265 pts_unstable\n"); +module_param(parser_sei_enable, uint, 0664); +MODULE_PARM_DESC(parser_sei_enable, "\n parser_sei_enable\n"); + +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION +module_param(parser_dolby_vision_enable, uint, 0664); +MODULE_PARM_DESC(parser_dolby_vision_enable, + "\n parser_dolby_vision_enable\n"); + +module_param(dolby_meta_with_el, uint, 0664); +MODULE_PARM_DESC(dolby_meta_with_el, + "\n dolby_meta_with_el\n"); + +module_param(dolby_el_flush_th, uint, 0664); +MODULE_PARM_DESC(dolby_el_flush_th, + "\n dolby_el_flush_th\n"); +#endif +module_param(mmu_enable, uint, 0664); +MODULE_PARM_DESC(mmu_enable, "\n mmu_enable\n"); + +module_param(mmu_enable_force, uint, 0664); +MODULE_PARM_DESC(mmu_enable_force, "\n mmu_enable_force\n"); + +#ifdef MULTI_INSTANCE_SUPPORT +module_param(start_decode_buf_level, int, 0664); +MODULE_PARM_DESC(start_decode_buf_level, + "\n h265 start_decode_buf_level\n"); + +module_param(decode_timeout_val, uint, 0664); +MODULE_PARM_DESC(decode_timeout_val, + "\n h265 decode_timeout_val\n"); + +module_param(data_resend_policy, uint, 0664); +MODULE_PARM_DESC(data_resend_policy, + "\n h265 data_resend_policy\n"); + +module_param_array(decode_frame_count, uint, + &max_decode_instance_num, 0664); + +module_param_array(display_frame_count, uint, + &max_decode_instance_num, 0664); + +module_param_array(max_process_time, uint, + &max_decode_instance_num, 0664); + +module_param_array(max_get_frame_interval, + uint, &max_decode_instance_num, 0664); + +module_param_array(run_count, uint, + &max_decode_instance_num, 0664); + +module_param_array(input_empty, uint, + &max_decode_instance_num, 0664); + +module_param_array(not_run_ready, uint, + &max_decode_instance_num, 0664); +#endif +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION +module_param(dv_toggle_prov_name, uint, 0664); +MODULE_PARM_DESC(dv_toggle_prov_name, "\n dv_toggle_prov_name\n"); + +module_param(dv_debug, uint, 0664); +MODULE_PARM_DESC(dv_debug, "\n dv_debug\n"); +#endif + +#ifdef AGAIN_HAS_THRESHOLD +module_param(again_threshold, uint, 0664); +MODULE_PARM_DESC(again_threshold, "\n again_threshold\n"); +#endif + +module_param(force_disp_pic_index, int, 0664); +MODULE_PARM_DESC(force_disp_pic_index, + "\n amvdec_h265 force_disp_pic_index\n"); + +module_param(udebug_flag, uint, 0664); +MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n"); + +module_param(udebug_pause_pos, uint, 0664); +MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n"); + +module_param(udebug_pause_val, uint, 0664); +MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n"); + +module_param(udebug_pause_decode_idx, uint, 0664); +MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n"); + +module_param(disp_vframe_valve_level, uint, 0664); +MODULE_PARM_DESC(disp_vframe_valve_level, "\n disp_vframe_valve_level\n"); + +module_init(amvdec_h265_driver_init_module); +module_exit(amvdec_h265_driver_remove_module); + +MODULE_DESCRIPTION("AMLOGIC h265 Video Decoder Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Tim Yao "); diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/h265/vh265.h b/drivers/amlogic/media_modules/frame_provider/decoder/h265/vh265.h new file mode 100644 index 000000000000..11de11a22bcd --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/h265/vh265.h @@ -0,0 +1,27 @@ +/* + * drivers/amlogic/amports/vh265.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef VH265_H +#define VH265_H + +extern u32 get_blackout_policy(void); + +extern s32 vh265_init(void); + +extern s32 vh265_release(void); + +#endif /* VMPEG4_H */ diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/mjpeg/Makefile b/drivers/amlogic/media_modules/frame_provider/decoder/mjpeg/Makefile new file mode 100644 index 000000000000..ab91854d49d4 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/mjpeg/Makefile @@ -0,0 +1,5 @@ +obj-$(CONFIG_AMLOGIC_MEDIA_VDEC_MJPEG) += amvdec_mjpeg.o +amvdec_mjpeg-objs += vmjpeg.o + +obj-$(CONFIG_AMLOGIC_MEDIA_VDEC_MJPEG_MULTI) += amvdec_mmjpeg.o +amvdec_mmjpeg-objs += vmjpeg_multi.o diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/mjpeg/vmjpeg.c b/drivers/amlogic/media_modules/frame_provider/decoder/mjpeg/vmjpeg.c new file mode 100644 index 000000000000..b5af67a2ffe4 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/mjpeg/vmjpeg.c @@ -0,0 +1,956 @@ +/* + * drivers/amlogic/amports/vmjpeg.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "../../../stream_input/amports/amports_priv.h" +#include +#include "../utils/decoder_mmu_box.h" +#include "../utils/decoder_bmmu_box.h" +#include +#include + +#ifdef CONFIG_AM_VDEC_MJPEG_LOG +#define AMLOG +#define LOG_LEVEL_VAR amlog_level_vmjpeg +#define LOG_MASK_VAR amlog_mask_vmjpeg +#define LOG_LEVEL_ERROR 0 +#define LOG_LEVEL_INFO 1 +#define LOG_LEVEL_DESC "0:ERROR, 1:INFO" +#endif +#include +MODULE_AMLOG(LOG_LEVEL_ERROR, 0, LOG_LEVEL_DESC, LOG_DEFAULT_MASK_DESC); + +#include "../utils/amvdec.h" +#include "../utils/firmware.h" + +#define DRIVER_NAME "amvdec_mjpeg" +#define MODULE_NAME "amvdec_mjpeg" + +/* protocol register usage + * AV_SCRATCH_0 - AV_SCRATCH_1 : initial display buffer fifo + * AV_SCRATCH_2 - AV_SCRATCH_3 : decoder settings + * AV_SCRATCH_4 - AV_SCRATCH_7 : display buffer spec + * AV_SCRATCH_8 - AV_SCRATCH_9 : amrisc/host display buffer management + * AV_SCRATCH_a : time stamp + */ + +#define MREG_DECODE_PARAM AV_SCRATCH_2 /* bit 0-3: pico_addr_mode */ +/* bit 15-4: reference height */ +#define MREG_TO_AMRISC AV_SCRATCH_8 +#define MREG_FROM_AMRISC AV_SCRATCH_9 +#define MREG_FRAME_OFFSET AV_SCRATCH_A + +#define PICINFO_BUF_IDX_MASK 0x0007 +#define PICINFO_AVI1 0x0080 +#define PICINFO_INTERLACE 0x0020 +#define PICINFO_INTERLACE_AVI1_BOT 0x0010 +#define PICINFO_INTERLACE_FIRST 0x0010 + +#define VF_POOL_SIZE 16 +#define DECODE_BUFFER_NUM_MAX 4 +#define MAX_BMMU_BUFFER_NUM DECODE_BUFFER_NUM_MAX +#define PUT_INTERVAL (HZ/100) + +#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6*/ +/* #define NV21 */ +#endif +static DEFINE_MUTEX(vmjpeg_mutex); + +static struct dec_sysinfo vmjpeg_amstream_dec_info; + +static struct vframe_s *vmjpeg_vf_peek(void *); +static struct vframe_s *vmjpeg_vf_get(void *); +static void vmjpeg_vf_put(struct vframe_s *, void *); +static int vmjpeg_vf_states(struct vframe_states *states, void *); +static int vmjpeg_event_cb(int type, void *data, void *private_data); + +static int vmjpeg_prot_init(void); +static void vmjpeg_local_init(void); + +static const char vmjpeg_dec_id[] = "vmjpeg-dev"; +static struct vdec_info *gvs; +static struct work_struct set_clk_work; + +#define PROVIDER_NAME "decoder.mjpeg" +static const struct vframe_operations_s vmjpeg_vf_provider = { + .peek = vmjpeg_vf_peek, + .get = vmjpeg_vf_get, + .put = vmjpeg_vf_put, + .event_cb = vmjpeg_event_cb, + .vf_states = vmjpeg_vf_states, +}; +static void *mm_blk_handle; +static struct vframe_provider_s vmjpeg_vf_prov; + +static DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE); +static DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE); +static DECLARE_KFIFO(recycle_q, struct vframe_s *, VF_POOL_SIZE); + +static struct vframe_s vfpool[VF_POOL_SIZE]; +static s32 vfbuf_use[DECODE_BUFFER_NUM_MAX]; + +static u32 frame_width, frame_height, frame_dur; +static u32 saved_resolution; +static struct timer_list recycle_timer; +static u32 stat; +static u32 buf_size = 32 * 1024 * 1024; +static DEFINE_SPINLOCK(lock); +static bool is_reset; + +static inline u32 index2canvas0(u32 index) +{ + const u32 canvas_tab[4] = { +#ifdef NV21 + 0x010100, 0x030302, 0x050504, 0x070706 +#else + 0x020100, 0x050403, 0x080706, 0x0b0a09 +#endif + }; + + return canvas_tab[index]; +} + +static inline u32 index2canvas1(u32 index) +{ + const u32 canvas_tab[4] = { +#ifdef NV21 + 0x0d0d0c, 0x0f0f0e, 0x171716, 0x191918 +#else + 0x0e0d0c, 0x181716, 0x222120, 0x252423 +#endif + }; + + return canvas_tab[index]; +} + +static void set_frame_info(struct vframe_s *vf) +{ + vf->width = frame_width; + vf->height = frame_height; + vf->duration = frame_dur; + vf->ratio_control = 0; + vf->duration_pulldown = 0; + vf->flag = 0; +} + +static irqreturn_t vmjpeg_isr(int irq, void *dev_id) +{ + u32 reg, offset, pts, pts_valid = 0; + struct vframe_s *vf = NULL; + u64 pts_us64; + + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + reg = READ_VREG(MREG_FROM_AMRISC); + + if (reg & PICINFO_BUF_IDX_MASK) { + offset = READ_VREG(MREG_FRAME_OFFSET); + + if (pts_lookup_offset_us64 + (PTS_TYPE_VIDEO, offset, &pts, 0, &pts_us64) == 0) + pts_valid = 1; + + if ((reg & PICINFO_INTERLACE) == 0) { + u32 index = ((reg & PICINFO_BUF_IDX_MASK) - 1) & 3; + + if (index >= DECODE_BUFFER_NUM_MAX) { + pr_err("fatal error, invalid buffer index."); + return IRQ_HANDLED; + } + + if (kfifo_get(&newframe_q, &vf) == 0) { + pr_info( + "fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + + set_frame_info(vf); + vf->signal_type = 0; + vf->index = index; +#ifdef NV21 + vf->type = + VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD | + VIDTYPE_VIU_NV21; +#else + vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD; +#endif + vf->canvas0Addr = vf->canvas1Addr = + index2canvas0(index); + vf->pts = (pts_valid) ? pts : 0; + vf->pts_us64 = (pts_valid) ? pts_us64 : 0; + vf->orientation = 0; + vf->type_original = vf->type; + vfbuf_use[index]++; + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + index); + + gvs->frame_dur = frame_dur; + vdec_count_info(gvs, 0, offset); + + kfifo_put(&display_q, (const struct vframe_s *)vf); + + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + + } else { + u32 index = ((reg & PICINFO_BUF_IDX_MASK) - 1) & 3; + + if (index >= DECODE_BUFFER_NUM_MAX) { + pr_info("fatal error, invalid buffer index."); + return IRQ_HANDLED; + } + + if (kfifo_get(&newframe_q, &vf) == 0) { + pr_info + ("fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + + set_frame_info(vf); + vf->signal_type = 0; + vf->index = index; +#if 0 + if (reg & PICINFO_AVI1) { + /* AVI1 format */ + if (reg & PICINFO_INTERLACE_AVI1_BOT) { + vf->type = + VIDTYPE_INTERLACE_BOTTOM | + VIDTYPE_INTERLACE_FIRST; + } else + vf->type = VIDTYPE_INTERLACE_TOP; + } else { + if (reg & PICINFO_INTERLACE_FIRST) { + vf->type = + VIDTYPE_INTERLACE_TOP | + VIDTYPE_INTERLACE_FIRST; + } else + vf->type = VIDTYPE_INTERLACE_BOTTOM; + } + + vf->type |= VIDTYPE_VIU_FIELD; +#ifdef NV21 + vf->type |= VIDTYPE_VIU_NV21; +#endif + vf->duration >>= 1; + vf->canvas0Addr = vf->canvas1Addr = + index2canvas0(index); + vf->orientation = 0; + if ((vf->type & VIDTYPE_INTERLACE_FIRST) && + (pts_valid)) + vf->pts = pts; + else + vf->pts = 0; + + vfbuf_use[index]++; + + kfifo_put(&display_q, (const struct vframe_s *)vf); +#else + /* send whole frame by weaving top & bottom field */ +#ifdef NV21 + vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_NV21; +#else + vf->type = VIDTYPE_PROGRESSIVE; +#endif + vf->canvas0Addr = index2canvas0(index); + vf->canvas1Addr = index2canvas1(index); + vf->orientation = 0; + if (pts_valid) { + vf->pts = pts; + vf->pts_us64 = pts_us64; + } else { + vf->pts = 0; + vf->pts_us64 = 0; + } + vf->type_original = vf->type; + vfbuf_use[index]++; + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + index); + + gvs->frame_dur = frame_dur; + vdec_count_info(gvs, 0, offset); + + kfifo_put(&display_q, (const struct vframe_s *)vf); + + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); +#endif + } + + WRITE_VREG(MREG_FROM_AMRISC, 0); + } + + return IRQ_HANDLED; +} + +static struct vframe_s *vmjpeg_vf_peek(void *op_arg) +{ + struct vframe_s *vf; + + if (kfifo_peek(&display_q, &vf)) + return vf; + + return NULL; +} + +static struct vframe_s *vmjpeg_vf_get(void *op_arg) +{ + struct vframe_s *vf; + + if (kfifo_get(&display_q, &vf)) + return vf; + + return NULL; +} + +static void vmjpeg_vf_put(struct vframe_s *vf, void *op_arg) +{ + kfifo_put(&recycle_q, (const struct vframe_s *)vf); +} + +static int vmjpeg_event_cb(int type, void *data, void *private_data) +{ + if (type & VFRAME_EVENT_RECEIVER_RESET) { + unsigned long flags; + + amvdec_stop(); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_light_unreg_provider(&vmjpeg_vf_prov); +#endif + spin_lock_irqsave(&lock, flags); + vmjpeg_local_init(); + vmjpeg_prot_init(); + spin_unlock_irqrestore(&lock, flags); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_reg_provider(&vmjpeg_vf_prov); +#endif + amvdec_start(); + } + return 0; +} + +static int vmjpeg_vf_states(struct vframe_states *states, void *op_arg) +{ + unsigned long flags; + + spin_lock_irqsave(&lock, flags); + + states->vf_pool_size = VF_POOL_SIZE; + states->buf_free_num = kfifo_len(&newframe_q); + states->buf_avail_num = kfifo_len(&display_q); + states->buf_recycle_num = kfifo_len(&recycle_q); + + spin_unlock_irqrestore(&lock, flags); + + return 0; +} +static void mjpeg_set_clk(struct work_struct *work) +{ + if (frame_dur > 0 && saved_resolution != + frame_width * frame_height * (96000 / frame_dur)) { + int fps = 96000 / frame_dur; + + saved_resolution = frame_width * frame_height * fps; + vdec_source_changed(VFORMAT_MJPEG, + frame_width, frame_height, fps); + } +} + +static void vmjpeg_put_timer_func(unsigned long arg) +{ + struct timer_list *timer = (struct timer_list *)arg; + + while (!kfifo_is_empty(&recycle_q) && + (READ_VREG(MREG_TO_AMRISC) == 0)) { + struct vframe_s *vf; + + if (kfifo_get(&recycle_q, &vf)) { + if ((vf->index >= 0) + && (vf->index < DECODE_BUFFER_NUM_MAX) + && (--vfbuf_use[vf->index] == 0)) { + WRITE_VREG(MREG_TO_AMRISC, vf->index + 1); + vf->index = DECODE_BUFFER_NUM_MAX; + } + + kfifo_put(&newframe_q, (const struct vframe_s *)vf); + } + } + + schedule_work(&set_clk_work); + + timer->expires = jiffies + PUT_INTERVAL; + + add_timer(timer); +} + +int vmjpeg_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus) +{ + vstatus->frame_width = frame_width; + vstatus->frame_height = frame_height; + if (0 != frame_dur) + vstatus->frame_rate = 96000 / frame_dur; + else + vstatus->frame_rate = 96000; + vstatus->error_count = 0; + vstatus->status = stat; + vstatus->bit_rate = gvs->bit_rate; + vstatus->frame_dur = frame_dur; + vstatus->frame_data = gvs->frame_data; + vstatus->total_data = gvs->total_data; + vstatus->frame_count = gvs->frame_count; + vstatus->error_frame_count = gvs->error_frame_count; + vstatus->drop_frame_count = gvs->drop_frame_count; + vstatus->total_data = gvs->total_data; + vstatus->samp_cnt = gvs->samp_cnt; + vstatus->offset = gvs->offset; + snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name), + "%s", DRIVER_NAME); + + return 0; +} + +int vmjpeg_set_isreset(struct vdec_s *vdec, int isreset) +{ + is_reset = isreset; + return 0; +} + +/****************************************/ +static int vmjpeg_canvas_init(void) +{ + int i, ret; + u32 canvas_width, canvas_height; + u32 decbuf_size, decbuf_y_size, decbuf_uv_size; + unsigned long buf_start; + + if (buf_size <= 0x00400000) { + /* SD only */ + canvas_width = 768; + canvas_height = 576; + decbuf_y_size = 0x80000; + decbuf_uv_size = 0x20000; + decbuf_size = 0x100000; + } else { + /* HD & SD */ + canvas_width = 1920; + canvas_height = 1088; + decbuf_y_size = 0x200000; + decbuf_uv_size = 0x80000; + decbuf_size = 0x300000; + } + + for (i = 0; i < MAX_BMMU_BUFFER_NUM; i++) { + + ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, i, + decbuf_size, DRIVER_NAME, &buf_start); + if (ret < 0) + return ret; +#ifdef NV21 + canvas_config(index2canvas0(i) & 0xff, + buf_start, + canvas_width, canvas_height, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + canvas_config((index2canvas0(i) >> 8) & 0xff, + buf_start + + decbuf_y_size, canvas_width, + canvas_height / 2, CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + canvas_config(index2canvas1(i) & 0xff, + buf_start + + decbuf_size / 2, canvas_width, + canvas_height, CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + canvas_config((index2canvas1(i) >> 8) & 0xff, + buf_start + + decbuf_y_size + decbuf_uv_size / 2, + canvas_width, canvas_height / 2, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); +#else + canvas_config(index2canvas0(i) & 0xff, + buf_start, + canvas_width, canvas_height, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + canvas_config((index2canvas0(i) >> 8) & 0xff, + buf_start + + decbuf_y_size, canvas_width / 2, + canvas_height / 2, CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + canvas_config((index2canvas0(i) >> 16) & 0xff, + buf_start + + decbuf_y_size + decbuf_uv_size, + canvas_width / 2, canvas_height / 2, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + canvas_config(index2canvas1(i) & 0xff, + buf_start + + decbuf_size / 2, canvas_width, + canvas_height, CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + canvas_config((index2canvas1(i) >> 8) & 0xff, + buf_start + + decbuf_y_size + decbuf_uv_size / 2, + canvas_width / 2, canvas_height / 2, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + canvas_config((index2canvas1(i) >> 16) & 0xff, + buf_start + + decbuf_y_size + decbuf_uv_size + + decbuf_uv_size / 2, canvas_width / 2, + canvas_height / 2, CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); +#endif + + } + return 0; +} + +static void init_scaler(void) +{ + /* 4 point triangle */ + const unsigned int filt_coef[] = { + 0x20402000, 0x20402000, 0x1f3f2101, 0x1f3f2101, + 0x1e3e2202, 0x1e3e2202, 0x1d3d2303, 0x1d3d2303, + 0x1c3c2404, 0x1c3c2404, 0x1b3b2505, 0x1b3b2505, + 0x1a3a2606, 0x1a3a2606, 0x19392707, 0x19392707, + 0x18382808, 0x18382808, 0x17372909, 0x17372909, + 0x16362a0a, 0x16362a0a, 0x15352b0b, 0x15352b0b, + 0x14342c0c, 0x14342c0c, 0x13332d0d, 0x13332d0d, + 0x12322e0e, 0x12322e0e, 0x11312f0f, 0x11312f0f, + 0x10303010 + }; + int i; + + /* pscale enable, PSCALE cbus bmem enable */ + WRITE_VREG(PSCALE_CTRL, 0xc000); + + /* write filter coefs */ + WRITE_VREG(PSCALE_BMEM_ADDR, 0); + for (i = 0; i < 33; i++) { + WRITE_VREG(PSCALE_BMEM_DAT, 0); + WRITE_VREG(PSCALE_BMEM_DAT, filt_coef[i]); + } + + /* Y horizontal initial info */ + WRITE_VREG(PSCALE_BMEM_ADDR, 37 * 2); + /* [35]: buf repeat pix0, + * [34:29] => buf receive num, + * [28:16] => buf blk x, + * [15:0] => buf phase + */ + WRITE_VREG(PSCALE_BMEM_DAT, 0x0008); + WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000); + + /* C horizontal initial info */ + WRITE_VREG(PSCALE_BMEM_ADDR, 41 * 2); + WRITE_VREG(PSCALE_BMEM_DAT, 0x0008); + WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000); + + /* Y vertical initial info */ + WRITE_VREG(PSCALE_BMEM_ADDR, 39 * 2); + WRITE_VREG(PSCALE_BMEM_DAT, 0x0008); + WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000); + + /* C vertical initial info */ + WRITE_VREG(PSCALE_BMEM_ADDR, 43 * 2); + WRITE_VREG(PSCALE_BMEM_DAT, 0x0008); + WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000); + + /* Y horizontal phase step */ + WRITE_VREG(PSCALE_BMEM_ADDR, 36 * 2 + 1); + /* [19:0] => Y horizontal phase step */ + WRITE_VREG(PSCALE_BMEM_DAT, 0x10000); + /* C horizontal phase step */ + WRITE_VREG(PSCALE_BMEM_ADDR, 40 * 2 + 1); + /* [19:0] => C horizontal phase step */ + WRITE_VREG(PSCALE_BMEM_DAT, 0x10000); + + /* Y vertical phase step */ + WRITE_VREG(PSCALE_BMEM_ADDR, 38 * 2 + 1); + /* [19:0] => Y vertical phase step */ + WRITE_VREG(PSCALE_BMEM_DAT, 0x10000); + /* C vertical phase step */ + WRITE_VREG(PSCALE_BMEM_ADDR, 42 * 2 + 1); + /* [19:0] => C horizontal phase step */ + WRITE_VREG(PSCALE_BMEM_DAT, 0x10000); + + /* reset pscaler */ +#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6*/ + WRITE_VREG(DOS_SW_RESET0, (1 << 10)); + WRITE_VREG(DOS_SW_RESET0, 0); +#else + WRITE_RESET_REG(RESET2_REGISTER, RESET_PSCALE); +#endif + READ_RESET_REG(RESET2_REGISTER); + READ_RESET_REG(RESET2_REGISTER); + READ_RESET_REG(RESET2_REGISTER); + + WRITE_VREG(PSCALE_RST, 0x7); + WRITE_VREG(PSCALE_RST, 0x0); +} + +static int vmjpeg_prot_init(void) +{ + int r; +#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6*/ + WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6)); + WRITE_VREG(DOS_SW_RESET0, 0); +#else + WRITE_RESET_REG(RESET0_REGISTER, RESET_IQIDCT | RESET_MC); +#endif + + r = vmjpeg_canvas_init(); + + WRITE_VREG(AV_SCRATCH_0, 12); + WRITE_VREG(AV_SCRATCH_1, 0x031a); +#ifdef NV21 + WRITE_VREG(AV_SCRATCH_4, 0x010100); + WRITE_VREG(AV_SCRATCH_5, 0x030302); + WRITE_VREG(AV_SCRATCH_6, 0x050504); + WRITE_VREG(AV_SCRATCH_7, 0x070706); +#else + WRITE_VREG(AV_SCRATCH_4, 0x020100); + WRITE_VREG(AV_SCRATCH_5, 0x050403); + WRITE_VREG(AV_SCRATCH_6, 0x080706); + WRITE_VREG(AV_SCRATCH_7, 0x0b0a09); +#endif + init_scaler(); + + /* clear buffer IN/OUT registers */ + WRITE_VREG(MREG_TO_AMRISC, 0); + WRITE_VREG(MREG_FROM_AMRISC, 0); + + WRITE_VREG(MCPU_INTR_MSK, 0xffff); + WRITE_VREG(MREG_DECODE_PARAM, (frame_height << 4) | 0x8000); + + /* clear mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + /* enable mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_MASK, 1); + /* set interrupt mapping for vld */ + WRITE_VREG(ASSIST_AMR1_INT8, 8); +#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6*/ +#ifdef NV21 + SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17); +#else + CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17); +#endif +#endif + return r; +} + +static int vmjpeg_vdec_info_init(void) +{ + gvs = kzalloc(sizeof(struct vdec_info), GFP_KERNEL); + if (NULL == gvs) { + pr_info("the struct of vdec status malloc failed.\n"); + return -ENOMEM; + } + return 0; +} + +static void vmjpeg_local_init(void) +{ + int i; + + frame_width = vmjpeg_amstream_dec_info.width; + frame_height = vmjpeg_amstream_dec_info.height; + frame_dur = vmjpeg_amstream_dec_info.rate; + saved_resolution = 0; + amlog_level(LOG_LEVEL_INFO, "mjpegdec: w(%d), h(%d), dur(%d)\n", + frame_width, frame_height, frame_dur); + + for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) + vfbuf_use[i] = 0; + + INIT_KFIFO(display_q); + INIT_KFIFO(recycle_q); + INIT_KFIFO(newframe_q); + + for (i = 0; i < VF_POOL_SIZE; i++) { + const struct vframe_s *vf = &vfpool[i]; + + vfpool[i].index = DECODE_BUFFER_NUM_MAX; + kfifo_put(&newframe_q, vf); + } + if (mm_blk_handle) { + decoder_bmmu_box_free(mm_blk_handle); + mm_blk_handle = NULL; + } + + mm_blk_handle = decoder_bmmu_box_alloc_box( + DRIVER_NAME, + 0, + MAX_BMMU_BUFFER_NUM, + 4 + PAGE_SHIFT, + CODEC_MM_FLAGS_CMA_CLEAR | + CODEC_MM_FLAGS_FOR_VDECODER); +} + +static s32 vmjpeg_init(void) +{ + int ret = -1, size = -1; + char *buf = vmalloc(0x1000 * 16); + + if (IS_ERR_OR_NULL(buf)) + return -ENOMEM; + + init_timer(&recycle_timer); + + stat |= STAT_TIMER_INIT; + + amvdec_enable(); + + vmjpeg_local_init(); + + size = get_firmware_data(VIDEO_DEC_MJPEG, buf); + if (size < 0) { + amvdec_disable(); + pr_err("get firmware fail."); + vfree(buf); + return -1; + } + + if (size == 1) + pr_info ("tee load ok"); + else if (amvdec_loadmc_ex(VFORMAT_MJPEG, NULL, buf) < 0) { + amvdec_disable(); + vfree(buf); + return -EBUSY; + } + + vfree(buf); + + stat |= STAT_MC_LOAD; + + /* enable AMRISC side protocol */ + ret = vmjpeg_prot_init(); + if (ret < 0) + return ret; + + ret = vdec_request_irq(VDEC_IRQ_1, vmjpeg_isr, + "vmjpeg-irq", (void *)vmjpeg_dec_id); + + if (ret) { + amvdec_disable(); + + amlog_level(LOG_LEVEL_ERROR, "vmjpeg irq register error.\n"); + return -ENOENT; + } + + stat |= STAT_ISR_REG; + +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_provider_init(&vmjpeg_vf_prov, PROVIDER_NAME, &vmjpeg_vf_provider, + NULL); + vf_reg_provider(&vmjpeg_vf_prov); + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL); +#else + vf_provider_init(&vmjpeg_vf_prov, PROVIDER_NAME, &vmjpeg_vf_provider, + NULL); + vf_reg_provider(&vmjpeg_vf_prov); +#endif + + if (!is_reset) + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_FR_HINT, + (void *) + ((unsigned long)vmjpeg_amstream_dec_info.rate)); + + stat |= STAT_VF_HOOK; + + recycle_timer.data = (ulong)&recycle_timer; + recycle_timer.function = vmjpeg_put_timer_func; + recycle_timer.expires = jiffies + PUT_INTERVAL; + + add_timer(&recycle_timer); + + stat |= STAT_TIMER_ARM; + + amvdec_start(); + + stat |= STAT_VDEC_RUN; + + return 0; +} + +static int amvdec_mjpeg_probe(struct platform_device *pdev) +{ + struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; + + mutex_lock(&vmjpeg_mutex); + + amlog_level(LOG_LEVEL_INFO, "amvdec_mjpeg probe start.\n"); + + INIT_WORK(&set_clk_work, mjpeg_set_clk); + + if (pdata == NULL) { + amlog_level(LOG_LEVEL_ERROR, + "amvdec_mjpeg memory resource undefined.\n"); + mutex_unlock(&vmjpeg_mutex); + + return -EFAULT; + } + + if (pdata->sys_info) + vmjpeg_amstream_dec_info = *pdata->sys_info; + + pdata->dec_status = vmjpeg_dec_status; + pdata->set_isreset = vmjpeg_set_isreset; + is_reset = 0; + vmjpeg_vdec_info_init(); + + if (vmjpeg_init() < 0) { + amlog_level(LOG_LEVEL_ERROR, "amvdec_mjpeg init failed.\n"); + mutex_unlock(&vmjpeg_mutex); + kfree(gvs); + gvs = NULL; + return -ENODEV; + } + + mutex_unlock(&vmjpeg_mutex); + + amlog_level(LOG_LEVEL_INFO, "amvdec_mjpeg probe end.\n"); + + return 0; +} + +static int amvdec_mjpeg_remove(struct platform_device *pdev) +{ + mutex_lock(&vmjpeg_mutex); + + cancel_work_sync(&set_clk_work); + + if (stat & STAT_VDEC_RUN) { + amvdec_stop(); + stat &= ~STAT_VDEC_RUN; + } + + if (stat & STAT_ISR_REG) { + vdec_free_irq(VDEC_IRQ_1, (void *)vmjpeg_dec_id); + stat &= ~STAT_ISR_REG; + } + + if (stat & STAT_TIMER_ARM) { + del_timer_sync(&recycle_timer); + stat &= ~STAT_TIMER_ARM; + } + + if (stat & STAT_VF_HOOK) { + if (!is_reset) + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_FR_END_HINT, + NULL); + + vf_unreg_provider(&vmjpeg_vf_prov); + stat &= ~STAT_VF_HOOK; + } + + amvdec_disable(); + + mutex_unlock(&vmjpeg_mutex); + + kfree(gvs); + gvs = NULL; + + if (mm_blk_handle) { + decoder_bmmu_box_free(mm_blk_handle); + mm_blk_handle = NULL; + } + + amlog_level(LOG_LEVEL_INFO, "amvdec_mjpeg remove.\n"); + + return 0; +} + +/****************************************/ + +static struct platform_driver amvdec_mjpeg_driver = { + .probe = amvdec_mjpeg_probe, + .remove = amvdec_mjpeg_remove, +#ifdef CONFIG_PM + .suspend = amvdec_suspend, + .resume = amvdec_resume, +#endif + .driver = { + .name = DRIVER_NAME, + } +}; + +static struct codec_profile_t amvdec_mjpeg_profile = { + .name = "mjpeg", + .profile = "" +}; +static struct mconfig mjpeg_configs[] = { + MC_PU32("stat", &stat), +}; +static struct mconfig_node mjpeg_node; + +static int __init amvdec_mjpeg_driver_init_module(void) +{ + amlog_level(LOG_LEVEL_INFO, "amvdec_mjpeg module init\n"); + + if (platform_driver_register(&amvdec_mjpeg_driver)) { + amlog_level(LOG_LEVEL_ERROR, + "failed to register amvdec_mjpeg driver\n"); + return -ENODEV; + } + vcodec_profile_register(&amvdec_mjpeg_profile); + INIT_REG_NODE_CONFIGS("media.decoder", &mjpeg_node, + "mjpeg", mjpeg_configs, CONFIG_FOR_RW); + return 0; +} + +static void __exit amvdec_mjpeg_driver_remove_module(void) +{ + amlog_level(LOG_LEVEL_INFO, "amvdec_mjpeg module remove.\n"); + + platform_driver_unregister(&amvdec_mjpeg_driver); +} + +/****************************************/ + +module_param(stat, uint, 0664); +MODULE_PARM_DESC(stat, "\n amvdec_mjpeg stat\n"); + +module_init(amvdec_mjpeg_driver_init_module); +module_exit(amvdec_mjpeg_driver_remove_module); + +MODULE_DESCRIPTION("AMLOGIC MJMPEG Video Decoder Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Tim Yao "); diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/mjpeg/vmjpeg_multi.c b/drivers/amlogic/media_modules/frame_provider/decoder/mjpeg/vmjpeg_multi.c new file mode 100644 index 000000000000..a0b449324efe --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/mjpeg/vmjpeg_multi.c @@ -0,0 +1,932 @@ +/* + * drivers/amlogic/amports/vmjpeg.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "../../../stream_input/amports/amports_priv.h" + +#include "../utils/vdec_input.h" +#include "../utils/vdec.h" +#include "../utils/amvdec.h" +#include "../utils/decoder_mmu_box.h" +#include "../utils/decoder_bmmu_box.h" +#include +#include +#include "../utils/firmware.h" + +#define MEM_NAME "codec_mmjpeg" + +#define DRIVER_NAME "ammvdec_mjpeg" +#define MODULE_NAME "ammvdec_mjpeg" +#define CHECK_INTERVAL (HZ/100) + +/* protocol register usage + * AV_SCRATCH_4 : decode buffer spec + * AV_SCRATCH_5 : decode buffer index + */ + +#define MREG_DECODE_PARAM AV_SCRATCH_2 /* bit 0-3: pico_addr_mode */ +/* bit 15-4: reference height */ +#define MREG_TO_AMRISC AV_SCRATCH_8 +#define MREG_FROM_AMRISC AV_SCRATCH_9 +#define MREG_FRAME_OFFSET AV_SCRATCH_A +#define DEC_STATUS_REG AV_SCRATCH_J + +#define PICINFO_BUF_IDX_MASK 0x0007 +#define PICINFO_AVI1 0x0080 +#define PICINFO_INTERLACE 0x0020 +#define PICINFO_INTERLACE_AVI1_BOT 0x0010 +#define PICINFO_INTERLACE_FIRST 0x0010 + +#define VF_POOL_SIZE 16 +#define DECODE_BUFFER_NUM_MAX 4 +#define MAX_BMMU_BUFFER_NUM DECODE_BUFFER_NUM_MAX + +#define DEFAULT_MEM_SIZE (32*SZ_1M) +static int debug_enable; +#define DECODE_ID(hw) (hw_to_vdec(hw)->id) + +static struct vframe_s *vmjpeg_vf_peek(void *); +static struct vframe_s *vmjpeg_vf_get(void *); +static void vmjpeg_vf_put(struct vframe_s *, void *); +static int vmjpeg_vf_states(struct vframe_states *states, void *); +static int vmjpeg_event_cb(int type, void *data, void *private_data); +static void vmjpeg_work(struct work_struct *work); +static int pre_decode_buf_level = 0x800; + +static const char vmjpeg_dec_id[] = "vmmjpeg-dev"; + +#define PROVIDER_NAME "vdec.mjpeg" +static const struct vframe_operations_s vf_provider_ops = { + .peek = vmjpeg_vf_peek, + .get = vmjpeg_vf_get, + .put = vmjpeg_vf_put, + .event_cb = vmjpeg_event_cb, + .vf_states = vmjpeg_vf_states, +}; + +#define DEC_RESULT_NONE 0 +#define DEC_RESULT_DONE 1 +#define DEC_RESULT_AGAIN 2 +#define DEC_RESULT_FORCE_EXIT 3 +#define DEC_RESULT_EOS 4 +#define DEC_DECODE_TIMEOUT 0x21 + + +struct buffer_spec_s { + unsigned int y_addr; + unsigned int u_addr; + unsigned int v_addr; + + int y_canvas_index; + int u_canvas_index; + int v_canvas_index; + + struct canvas_config_s canvas_config[3]; + unsigned long cma_alloc_addr; + int cma_alloc_count; + unsigned int buf_adr; +}; + +#define spec2canvas(x) \ + (((x)->v_canvas_index << 16) | \ + ((x)->u_canvas_index << 8) | \ + ((x)->y_canvas_index << 0)) + +struct vdec_mjpeg_hw_s { + spinlock_t lock; + struct mutex vmjpeg_mutex; + + struct platform_device *platform_dev; + DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE); + DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE); + + struct vframe_s vfpool[VF_POOL_SIZE]; + struct buffer_spec_s buffer_spec[DECODE_BUFFER_NUM_MAX]; + s32 vfbuf_use[DECODE_BUFFER_NUM_MAX]; + + u32 frame_width; + u32 frame_height; + u32 frame_dur; + u32 saved_resolution; + u8 init_flag; + u32 stat; + u32 dec_result; + unsigned long buf_start; + u32 buf_size; + void *mm_blk_handle; + struct dec_sysinfo vmjpeg_amstream_dec_info; + + struct vframe_chunk_s *chunk; + struct work_struct work; + void (*vdec_cb)(struct vdec_s *, void *); + void *vdec_cb_arg; + struct firmware_s *fw; + struct timer_list check_timer; + unsigned decode_timeout_count; + u8 eos; + u32 frame_num, put_num; +}; + +static void set_frame_info(struct vdec_mjpeg_hw_s *hw, struct vframe_s *vf) +{ + vf->width = hw->frame_width; + vf->height = hw->frame_height; + vf->duration = hw->frame_dur; + vf->ratio_control = 0; + vf->duration_pulldown = 0; + vf->flag = 0; + + vf->canvas0Addr = vf->canvas1Addr = -1; + vf->plane_num = 3; + + vf->canvas0_config[0] = hw->buffer_spec[vf->index].canvas_config[0]; + vf->canvas0_config[1] = hw->buffer_spec[vf->index].canvas_config[1]; + vf->canvas0_config[2] = hw->buffer_spec[vf->index].canvas_config[2]; + + vf->canvas1_config[0] = hw->buffer_spec[vf->index].canvas_config[0]; + vf->canvas1_config[1] = hw->buffer_spec[vf->index].canvas_config[1]; + vf->canvas1_config[2] = hw->buffer_spec[vf->index].canvas_config[2]; +} + +static irqreturn_t vmjpeg_isr(struct vdec_s *vdec, int irq) +{ + struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)(vdec->private); + u32 reg; + struct vframe_s *vf = NULL; + u32 index, offset = 0, pts; + u64 pts_us64; + + if (debug_enable & 0x1) + pr_info("%s: %d\n", __func__, __LINE__); + + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + if (!hw) + return IRQ_HANDLED; + if (hw->eos) + return IRQ_HANDLED; + reg = READ_VREG(MREG_FROM_AMRISC); + index = READ_VREG(AV_SCRATCH_5); + + if (index >= DECODE_BUFFER_NUM_MAX) { + pr_err("fatal error, invalid buffer index."); + return IRQ_HANDLED; + } + + if (kfifo_get(&hw->newframe_q, &vf) == 0) { + pr_info( + "fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + + vf->index = index; + set_frame_info(hw, vf); + + vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD; + /* vf->pts = (pts_valid) ? pts : 0; */ + /* vf->pts_us64 = (pts_valid) ? pts_us64 : 0; */ + + if (hw->chunk) { + vf->pts = hw->chunk->pts; + vf->pts_us64 = hw->chunk->pts64; + } else { + offset = READ_VREG(MREG_FRAME_OFFSET); + if (pts_lookup_offset_us64 + (PTS_TYPE_VIDEO, offset, &pts, 3000, + &pts_us64) == 0) { + vf->pts = pts; + vf->pts_us64 = pts_us64; + } else { + vf->pts = 0; + vf->pts_us64 = 0; + } + } + vf->orientation = 0; + hw->vfbuf_use[index]++; + + kfifo_put(&hw->display_q, (const struct vframe_s *)vf); + + hw->frame_num++; + vf_notify_receiver(vdec->vf_provider_name, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + + hw->dec_result = DEC_RESULT_DONE; + + schedule_work(&hw->work); + + return IRQ_HANDLED; +} + +static struct vframe_s *vmjpeg_vf_peek(void *op_arg) +{ + struct vframe_s *vf; + struct vdec_s *vdec = op_arg; + struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private; + + if (!hw) + return NULL; + + if (kfifo_peek(&hw->display_q, &vf)) + return vf; + + return NULL; +} + +static struct vframe_s *vmjpeg_vf_get(void *op_arg) +{ + struct vframe_s *vf; + struct vdec_s *vdec = op_arg; + struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private; + + if (!hw) + return NULL; + + if (kfifo_get(&hw->display_q, &vf)) + return vf; + + return NULL; +} + +static void vmjpeg_vf_put(struct vframe_s *vf, void *op_arg) +{ + struct vdec_s *vdec = op_arg; + struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private; + + hw->vfbuf_use[vf->index]--; + kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf); + hw->put_num++; +} + +static int vmjpeg_event_cb(int type, void *data, void *private_data) +{ + return 0; +} + +static int vmjpeg_vf_states(struct vframe_states *states, void *op_arg) +{ + unsigned long flags; + struct vdec_s *vdec = op_arg; + struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private; + + spin_lock_irqsave(&hw->lock, flags); + + states->vf_pool_size = VF_POOL_SIZE; + states->buf_free_num = kfifo_len(&hw->newframe_q); + states->buf_avail_num = kfifo_len(&hw->display_q); + states->buf_recycle_num = 0; + + spin_unlock_irqrestore(&hw->lock, flags); + + return 0; +} + +static int vmjpeg_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus) +{ + struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)vdec->private; + vstatus->frame_width = hw->frame_width; + vstatus->frame_height = hw->frame_height; + if (0 != hw->frame_dur) + vstatus->frame_rate = 96000 / hw->frame_dur; + else + vstatus->frame_rate = 96000; + vstatus->error_count = 0; + vstatus->status = hw->stat; + + return 0; +} + +/****************************************/ +static void vmjpeg_canvas_init(struct vdec_s *vdec) +{ + int i, ret; + u32 canvas_width, canvas_height; + u32 decbuf_size, decbuf_y_size, decbuf_uv_size; + unsigned long buf_start, addr; + struct vdec_mjpeg_hw_s *hw = + (struct vdec_mjpeg_hw_s *)vdec->private; + + canvas_width = 1920; + canvas_height = 1088; + decbuf_y_size = 0x200000; + decbuf_uv_size = 0x80000; + decbuf_size = 0x300000; + + for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) { + int canvas; + + canvas = vdec->get_canvas(i, 3); + + ret = decoder_bmmu_box_alloc_buf_phy(hw->mm_blk_handle, i, + decbuf_size, DRIVER_NAME, &buf_start); + if (ret < 0) { + pr_err("CMA alloc failed! size 0x%d idx %d\n", + decbuf_size, i); + return; + } + + hw->buffer_spec[i].buf_adr = buf_start; + addr = hw->buffer_spec[i].buf_adr; + + hw->buffer_spec[i].y_addr = addr; + addr += decbuf_y_size; + hw->buffer_spec[i].u_addr = addr; + addr += decbuf_uv_size; + hw->buffer_spec[i].v_addr = addr; + + hw->buffer_spec[i].y_canvas_index = canvas_y(canvas); + hw->buffer_spec[i].u_canvas_index = canvas_u(canvas); + hw->buffer_spec[i].v_canvas_index = canvas_v(canvas); + + canvas_config(hw->buffer_spec[i].y_canvas_index, + hw->buffer_spec[i].y_addr, + canvas_width, + canvas_height, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + hw->buffer_spec[i].canvas_config[0].phy_addr = + hw->buffer_spec[i].y_addr; + hw->buffer_spec[i].canvas_config[0].width = + canvas_width; + hw->buffer_spec[i].canvas_config[0].height = + canvas_height; + hw->buffer_spec[i].canvas_config[0].block_mode = + CANVAS_BLKMODE_LINEAR; + + canvas_config(hw->buffer_spec[i].u_canvas_index, + hw->buffer_spec[i].u_addr, + canvas_width / 2, + canvas_height / 2, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + hw->buffer_spec[i].canvas_config[1].phy_addr = + hw->buffer_spec[i].u_addr; + hw->buffer_spec[i].canvas_config[1].width = + canvas_width / 2; + hw->buffer_spec[i].canvas_config[1].height = + canvas_height / 2; + hw->buffer_spec[i].canvas_config[1].block_mode = + CANVAS_BLKMODE_LINEAR; + + canvas_config(hw->buffer_spec[i].v_canvas_index, + hw->buffer_spec[i].v_addr, + canvas_width / 2, + canvas_height / 2, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + hw->buffer_spec[i].canvas_config[2].phy_addr = + hw->buffer_spec[i].v_addr; + hw->buffer_spec[i].canvas_config[2].width = + canvas_width / 2; + hw->buffer_spec[i].canvas_config[2].height = + canvas_height / 2; + hw->buffer_spec[i].canvas_config[2].block_mode = + CANVAS_BLKMODE_LINEAR; + } +} + +static void init_scaler(void) +{ + /* 4 point triangle */ + const unsigned int filt_coef[] = { + 0x20402000, 0x20402000, 0x1f3f2101, 0x1f3f2101, + 0x1e3e2202, 0x1e3e2202, 0x1d3d2303, 0x1d3d2303, + 0x1c3c2404, 0x1c3c2404, 0x1b3b2505, 0x1b3b2505, + 0x1a3a2606, 0x1a3a2606, 0x19392707, 0x19392707, + 0x18382808, 0x18382808, 0x17372909, 0x17372909, + 0x16362a0a, 0x16362a0a, 0x15352b0b, 0x15352b0b, + 0x14342c0c, 0x14342c0c, 0x13332d0d, 0x13332d0d, + 0x12322e0e, 0x12322e0e, 0x11312f0f, 0x11312f0f, + 0x10303010 + }; + int i; + + /* pscale enable, PSCALE cbus bmem enable */ + WRITE_VREG(PSCALE_CTRL, 0xc000); + + /* write filter coefs */ + WRITE_VREG(PSCALE_BMEM_ADDR, 0); + for (i = 0; i < 33; i++) { + WRITE_VREG(PSCALE_BMEM_DAT, 0); + WRITE_VREG(PSCALE_BMEM_DAT, filt_coef[i]); + } + + /* Y horizontal initial info */ + WRITE_VREG(PSCALE_BMEM_ADDR, 37 * 2); + /* [35]: buf repeat pix0, + * [34:29] => buf receive num, + * [28:16] => buf blk x, + * [15:0] => buf phase + */ + WRITE_VREG(PSCALE_BMEM_DAT, 0x0008); + WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000); + + /* C horizontal initial info */ + WRITE_VREG(PSCALE_BMEM_ADDR, 41 * 2); + WRITE_VREG(PSCALE_BMEM_DAT, 0x0008); + WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000); + + /* Y vertical initial info */ + WRITE_VREG(PSCALE_BMEM_ADDR, 39 * 2); + WRITE_VREG(PSCALE_BMEM_DAT, 0x0008); + WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000); + + /* C vertical initial info */ + WRITE_VREG(PSCALE_BMEM_ADDR, 43 * 2); + WRITE_VREG(PSCALE_BMEM_DAT, 0x0008); + WRITE_VREG(PSCALE_BMEM_DAT, 0x60000000); + + /* Y horizontal phase step */ + WRITE_VREG(PSCALE_BMEM_ADDR, 36 * 2 + 1); + /* [19:0] => Y horizontal phase step */ + WRITE_VREG(PSCALE_BMEM_DAT, 0x10000); + /* C horizontal phase step */ + WRITE_VREG(PSCALE_BMEM_ADDR, 40 * 2 + 1); + /* [19:0] => C horizontal phase step */ + WRITE_VREG(PSCALE_BMEM_DAT, 0x10000); + + /* Y vertical phase step */ + WRITE_VREG(PSCALE_BMEM_ADDR, 38 * 2 + 1); + /* [19:0] => Y vertical phase step */ + WRITE_VREG(PSCALE_BMEM_DAT, 0x10000); + /* C vertical phase step */ + WRITE_VREG(PSCALE_BMEM_ADDR, 42 * 2 + 1); + /* [19:0] => C horizontal phase step */ + WRITE_VREG(PSCALE_BMEM_DAT, 0x10000); + + /* reset pscaler */ +#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6*/ + WRITE_VREG(DOS_SW_RESET0, (1 << 10)); + WRITE_VREG(DOS_SW_RESET0, 0); +#else + WRITE_RESET_REG(RESET2_REGISTER, RESET_PSCALE); +#endif + READ_RESET_REG(RESET2_REGISTER); + READ_RESET_REG(RESET2_REGISTER); + READ_RESET_REG(RESET2_REGISTER); + + WRITE_VREG(PSCALE_RST, 0x7); + WRITE_VREG(PSCALE_RST, 0x0); +} + +static void timeout_process(struct vdec_mjpeg_hw_s *hw) +{ + amvdec_stop(); + pr_info("%s decoder timeout\n", __func__); + hw->dec_result = DEC_RESULT_DONE; + + vdec_schedule_work(&hw->work); +} + +static void check_timer_func(unsigned long arg) +{ + struct vdec_mjpeg_hw_s *hw = (struct vdec_mjpeg_hw_s *)arg; + struct vdec_s *vdec = hw_to_vdec(hw); + if ((debug_enable & 0x2) != 0) { + pr_info("%s: status:nstatus=%d:%d\n", + __func__, vdec->status, vdec->next_status); + pr_info("%s: %d,buftl=%x:%x:%x:%x\n", + __func__, __LINE__, + READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL), + READ_PARSER_REG(PARSER_VIDEO_WP), + READ_VREG(VLD_MEM_VIFIFO_LEVEL), + READ_VREG(VLD_MEM_VIFIFO_WP)); + } + if ((debug_enable & 0x100) != 0) { + hw->dec_result = DEC_RESULT_DONE; + vdec_schedule_work(&hw->work); + pr_info("vdec %d is forced to be disconnected\n", + debug_enable & 0xff); + debug_enable = 0; + return; + } + + if (input_stream_based(vdec) + && READ_VREG(VLD_MEM_VIFIFO_LEVEL) <= 0x80) { + if (hw->decode_timeout_count > 0) + hw->decode_timeout_count--; + if (hw->decode_timeout_count == 0) + timeout_process(hw); + } + + if (READ_VREG(DEC_STATUS_REG) == DEC_DECODE_TIMEOUT) { + pr_info("ucode DEC_DECODE_TIMEOUT\n"); + if (hw->decode_timeout_count > 0) + hw->decode_timeout_count--; + if (hw->decode_timeout_count == 0) + timeout_process(hw); + WRITE_VREG(DEC_STATUS_REG, 0); + } + + if (vdec->next_status == VDEC_STATUS_DISCONNECTED) { + hw->dec_result = DEC_RESULT_FORCE_EXIT; + vdec_schedule_work(&hw->work); + pr_info("vdec requested to be disconnected\n"); + return; + } + mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL); +} +static void vmjpeg_hw_ctx_restore(struct vdec_s *vdec, int index) +{ + struct vdec_mjpeg_hw_s *hw = + (struct vdec_mjpeg_hw_s *)vdec->private; + + WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6)); + WRITE_VREG(DOS_SW_RESET0, 0); + + vmjpeg_canvas_init(vdec); + + /* find next decode buffer index */ + WRITE_VREG(AV_SCRATCH_4, spec2canvas(&hw->buffer_spec[index])); + WRITE_VREG(AV_SCRATCH_5, index); + + init_scaler(); + + /* clear buffer IN/OUT registers */ + WRITE_VREG(MREG_TO_AMRISC, 0); + WRITE_VREG(MREG_FROM_AMRISC, 0); + + WRITE_VREG(MCPU_INTR_MSK, 0xffff); + WRITE_VREG(MREG_DECODE_PARAM, (hw->frame_height << 4) | 0x8000); + + /* clear mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + /* enable mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_MASK, 1); + /* set interrupt mapping for vld */ + WRITE_VREG(ASSIST_AMR1_INT8, 8); +#if 1/*MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6*/ + CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17); +#endif +} + +static s32 vmjpeg_init(struct vdec_s *vdec) +{ + int i; + int size = -1, fw_size = 0x1000 * 16; + struct firmware_s *fw = NULL; + struct vdec_mjpeg_hw_s *hw = + (struct vdec_mjpeg_hw_s *)vdec->private; + + fw = vmalloc(sizeof(struct firmware_s) + fw_size); + if (IS_ERR_OR_NULL(fw)) + return -ENOMEM; + if (tee_enabled()) { + size = 1; + pr_debug (" tee load\n"); + } else + size = get_firmware_data(VIDEO_DEC_MJPEG_MULTI, fw->data); + if (size < 0) { + pr_err("get firmware fail."); + vfree(fw); + return -1; + } + + fw->len = size; + hw->fw = fw; + + hw->frame_width = hw->vmjpeg_amstream_dec_info.width; + hw->frame_height = hw->vmjpeg_amstream_dec_info.height; + hw->frame_dur = hw->vmjpeg_amstream_dec_info.rate; + hw->saved_resolution = 0; + hw->eos = 0; + hw->init_flag = 0; + hw->frame_num = 0; + hw->put_num = 0; + for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) + hw->vfbuf_use[i] = 0; + + INIT_KFIFO(hw->display_q); + INIT_KFIFO(hw->newframe_q); + + for (i = 0; i < VF_POOL_SIZE; i++) { + const struct vframe_s *vf = &hw->vfpool[i]; + + hw->vfpool[i].index = -1; + kfifo_put(&hw->newframe_q, vf); + } + + if (hw->mm_blk_handle) { + decoder_bmmu_box_free(hw->mm_blk_handle); + hw->mm_blk_handle = NULL; + } + + hw->mm_blk_handle = decoder_bmmu_box_alloc_box( + DRIVER_NAME, + 0, + MAX_BMMU_BUFFER_NUM, + 4 + PAGE_SHIFT, + CODEC_MM_FLAGS_CMA_CLEAR | + CODEC_MM_FLAGS_FOR_VDECODER); + + init_timer(&hw->check_timer); + + hw->check_timer.data = (unsigned long)hw; + hw->check_timer.function = check_timer_func; + hw->check_timer.expires = jiffies + CHECK_INTERVAL; + /*add_timer(&hw->check_timer);*/ + hw->stat |= STAT_TIMER_ARM; + + INIT_WORK(&hw->work, vmjpeg_work); + + return 0; +} + +static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask) +{ + struct vdec_mjpeg_hw_s *hw = + (struct vdec_mjpeg_hw_s *)vdec->private; + if (hw->eos) + return 0; + if (vdec_stream_based(vdec) && (hw->init_flag == 0) + && pre_decode_buf_level != 0) { + u32 rp, wp, level; + + rp = READ_PARSER_REG(PARSER_VIDEO_RP); + wp = READ_PARSER_REG(PARSER_VIDEO_WP); + if (wp < rp) + level = vdec->input.size + wp - rp; + else + level = wp - rp; + + if (level < pre_decode_buf_level) + return 0; + } + return CORE_MASK_VDEC_1 | CORE_MASK_HEVC; +} + +static void run(struct vdec_s *vdec, unsigned long mask, + void (*callback)(struct vdec_s *, void *), void *arg) +{ + struct vdec_mjpeg_hw_s *hw = + (struct vdec_mjpeg_hw_s *)vdec->private; + int i,ret = -1; + + hw->vdec_cb_arg = arg; + hw->vdec_cb = callback; + + for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) { + if (hw->vfbuf_use[i] == 0) + break; + } + + if (i == DECODE_BUFFER_NUM_MAX) { + hw->dec_result = DEC_RESULT_AGAIN; + schedule_work(&hw->work); + return; + } + + ret = vdec_prepare_input(vdec, &hw->chunk); + if (ret < 0) { + if (debug_enable & 0x1) { + pr_info("%s: %d,r=%d,buftl=%x:%x:%x\n", + __func__, __LINE__, ret, + READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL), + READ_PARSER_REG(PARSER_VIDEO_WP), + READ_VREG(VLD_MEM_VIFIFO_WP)); + } + hw->dec_result = DEC_RESULT_AGAIN; + schedule_work(&hw->work); + return; + } + + hw->dec_result = DEC_RESULT_NONE; + + if (amvdec_vdec_loadmc_ex(vdec, "vmmjpeg_mc",hw->fw->data) < 0) { + pr_err("%s: Error amvdec_loadmc fail\n", __func__); + return; + } +/* if (amvdec_vdec_loadmc_buf_ex(vdec, hw->fw->data, hw->fw->len) < 0) { + pr_err("%s: Error amvdec_loadmc fail\n", __func__); + return; + }*/ + + vmjpeg_hw_ctx_restore(vdec, i); +#if 0 + vdec_enable_input(vdec); + mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL); +#endif + amvdec_start(); + vdec_enable_input(vdec); + mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL); + hw->decode_timeout_count = 2; + hw->init_flag = 1; + if (debug_enable&0x1) { + + pr_info("%s (0x%x 0x%x 0x%x) vldcrl 0x%x bitcnt 0x%x powerctl 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + __func__, + READ_VREG(VLD_MEM_VIFIFO_LEVEL), + READ_VREG(VLD_MEM_VIFIFO_WP), + READ_VREG(VLD_MEM_VIFIFO_RP), + READ_VREG(VLD_DECODE_CONTROL), + READ_VREG(VIFF_BIT_CNT), + READ_VREG(POWER_CTL_VLD), + READ_VREG(VLD_MEM_VIFIFO_START_PTR), + READ_VREG(VLD_MEM_VIFIFO_CURR_PTR), + READ_VREG(VLD_MEM_VIFIFO_CONTROL), + READ_VREG(VLD_MEM_VIFIFO_BUF_CNTL), + READ_VREG(VLD_MEM_VIFIFO_END_PTR)); + + } +} + +static void vmjpeg_work(struct work_struct *work) +{ + struct vdec_mjpeg_hw_s *hw = container_of(work, + struct vdec_mjpeg_hw_s, work); + if (debug_enable & 0x2) + pr_info("%s: result=%d,len=%d:%d\n", + __func__, hw->dec_result, + kfifo_len(&hw->newframe_q), + kfifo_len(&hw->display_q)); + if (hw->dec_result == DEC_RESULT_DONE) + vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk); + else if (hw->dec_result == DEC_RESULT_AGAIN) { + /* + stream base: stream buf empty or timeout + frame base: vdec_prepare_input fail + */ + if (!vdec_has_more_input(hw_to_vdec(hw))) { + hw->dec_result = DEC_RESULT_EOS; + vdec_schedule_work(&hw->work); + /*pr_info("%s: return\n", + __func__);*/ + return; + } + } else if (hw->dec_result == DEC_RESULT_FORCE_EXIT) { + pr_info("%s: force exit\n", + __func__); + } else if (hw->dec_result == DEC_RESULT_EOS) { + /*pr_info("%s: end of stream\n", + __func__);*/ + if (READ_VREG(VLD_MEM_VIFIFO_LEVEL) < 0x100) + hw->eos = 1; + vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk); + } + amvdec_stop(); + /* mark itself has all HW resource released and input released */ + vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_CONNECTED); + vdec_core_finish_run(hw_to_vdec(hw), CORE_MASK_VDEC_1 + | CORE_MASK_HEVC); + del_timer_sync(&hw->check_timer); + hw->stat &= ~STAT_TIMER_ARM; + + if (hw->vdec_cb) + hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg); +} + +static int amvdec_mjpeg_probe(struct platform_device *pdev) +{ + struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; + struct vdec_mjpeg_hw_s *hw = NULL; + + if (pdata == NULL) { + pr_info("amvdec_mjpeg memory resource undefined.\n"); + return -EFAULT; + } + + hw = (struct vdec_mjpeg_hw_s *)devm_kzalloc(&pdev->dev, + sizeof(struct vdec_mjpeg_hw_s), GFP_KERNEL); + if (hw == NULL) { + pr_info("\nammvdec_mjpeg device data allocation failed\n"); + return -ENOMEM; + } + + pdata->private = hw; + pdata->dec_status = vmjpeg_dec_status; + + pdata->run = run; + pdata->run_ready = run_ready; + pdata->irq_handler = vmjpeg_isr; + + + if (pdata->use_vfm_path) + snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE, + VFM_DEC_PROVIDER_NAME); + else + snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE, + PROVIDER_NAME ".%02x", pdev->id & 0xff); + + vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name, + &vf_provider_ops, pdata); + + platform_set_drvdata(pdev, pdata); + + hw->platform_dev = pdev; + + if (pdata->sys_info) + hw->vmjpeg_amstream_dec_info = *pdata->sys_info; + + if (vmjpeg_init(pdata) < 0) { + pr_info("amvdec_mjpeg init failed.\n"); + return -ENODEV; + } + + vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC + | CORE_MASK_COMBINE); + + return 0; +} + +static int amvdec_mjpeg_remove(struct platform_device *pdev) +{ + struct vdec_mjpeg_hw_s *hw = + (struct vdec_mjpeg_hw_s *) + (((struct vdec_s *)(platform_get_drvdata(pdev)))->private); + + + if (hw->stat & STAT_TIMER_ARM) { + del_timer_sync(&hw->check_timer); + hw->stat &= ~STAT_TIMER_ARM; + } + cancel_work_sync(&hw->work); + if (hw->mm_blk_handle) { + decoder_bmmu_box_free(hw->mm_blk_handle); + hw->mm_blk_handle = NULL; + } + + vfree(hw->fw); + hw->fw = NULL; + + vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC); + vdec_set_status(hw_to_vdec(hw), VDEC_STATUS_DISCONNECTED); + + return 0; +} + +/****************************************/ + +static struct platform_driver amvdec_mjpeg_driver = { + .probe = amvdec_mjpeg_probe, + .remove = amvdec_mjpeg_remove, +#ifdef CONFIG_PM + .suspend = amvdec_suspend, + .resume = amvdec_resume, +#endif + .driver = { + .name = DRIVER_NAME, + } +}; + +static struct codec_profile_t amvdec_mjpeg_profile = { + .name = "mmjpeg", + .profile = "" +}; + +static int __init amvdec_mjpeg_driver_init_module(void) +{ + if (platform_driver_register(&amvdec_mjpeg_driver)) { + pr_err("failed to register amvdec_mjpeg driver\n"); + return -ENODEV; + } + vcodec_profile_register(&amvdec_mjpeg_profile); + return 0; +} + +static void __exit amvdec_mjpeg_driver_remove_module(void) +{ + platform_driver_unregister(&amvdec_mjpeg_driver); +} + +/****************************************/ +module_param(debug_enable, uint, 0664); +MODULE_PARM_DESC(debug_enable, "\n debug enable\n"); +module_param(pre_decode_buf_level, int, 0664); +MODULE_PARM_DESC(pre_decode_buf_level, + "\n ammvdec_h264 pre_decode_buf_level\n"); +module_init(amvdec_mjpeg_driver_init_module); +module_exit(amvdec_mjpeg_driver_remove_module); + +MODULE_DESCRIPTION("AMLOGIC MJMPEG Video Decoder Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Tim Yao "); diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/mpeg12/Makefile b/drivers/amlogic/media_modules/frame_provider/decoder/mpeg12/Makefile new file mode 100644 index 000000000000..9a07229b0cb0 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/mpeg12/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_AMLOGIC_MEDIA_VDEC_MPEG12) += amvdec_mpeg12.o +amvdec_mpeg12-objs += vmpeg12.o diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/mpeg12/vmpeg12.c b/drivers/amlogic/media_modules/frame_provider/decoder/mpeg12/vmpeg12.c new file mode 100644 index 000000000000..2e3a90edea7c --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/mpeg12/vmpeg12.c @@ -0,0 +1,2179 @@ +/* + * drivers/amlogic/amports/vmpeg12.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vmpeg12.h" +#include +#include "../../../stream_input/amports/amports_priv.h" +#include "../utils/decoder_mmu_box.h" +#include "../utils/decoder_bmmu_box.h" +#include +#include + +#ifdef CONFIG_AM_VDEC_MPEG12_LOG +#define AMLOG +#define LOG_LEVEL_VAR amlog_level_vmpeg +#define LOG_MASK_VAR amlog_mask_vmpeg +#define LOG_LEVEL_ERROR 0 +#define LOG_LEVEL_INFO 1 +#define LOG_LEVEL_DESC "0:ERROR, 1:INFO" +#endif +#include +MODULE_AMLOG(LOG_LEVEL_ERROR, 0, LOG_LEVEL_DESC, LOG_DEFAULT_MASK_DESC); + +#include "../utils/amvdec.h" +#include "../utils/vdec.h" +#include "../utils/firmware.h" + +#define DRIVER_NAME "amvdec_mpeg12" +#define MODULE_NAME "amvdec_mpeg12" + +/* protocol registers */ +#define MREG_SEQ_INFO AV_SCRATCH_4 +#define MREG_PIC_INFO AV_SCRATCH_5 +#define MREG_PIC_WIDTH AV_SCRATCH_6 +#define MREG_PIC_HEIGHT AV_SCRATCH_7 +#define MREG_BUFFERIN AV_SCRATCH_8 +#define MREG_BUFFEROUT AV_SCRATCH_9 + +#define MREG_CMD AV_SCRATCH_A +#define MREG_CO_MV_START AV_SCRATCH_B +#define MREG_ERROR_COUNT AV_SCRATCH_C +#define MREG_FRAME_OFFSET AV_SCRATCH_D +#define MREG_WAIT_BUFFER AV_SCRATCH_E +#define MREG_FATAL_ERROR AV_SCRATCH_F +#define MREG_FORCE_I_RDY AV_SCRATCH_G + +#define PICINFO_ERROR 0x80000000 +#define PICINFO_TYPE_MASK 0x00030000 +#define PICINFO_TYPE_I 0x00000000 +#define PICINFO_TYPE_P 0x00010000 +#define PICINFO_TYPE_B 0x00020000 + +#define PICINFO_PROG 0x8000 +#define PICINFO_RPT_FIRST 0x4000 +#define PICINFO_TOP_FIRST 0x2000 +#define PICINFO_FRAME 0x1000 + +#define SEQINFO_EXT_AVAILABLE 0x80000000 +#define SEQINFO_PROG 0x00010000 +#define CCBUF_SIZE (5*1024) + +#define VF_POOL_SIZE 32 +#define DECODE_BUFFER_NUM_MAX 8 +#define PUT_INTERVAL (HZ/100) +#define WORKSPACE_SIZE (2*SZ_64K) +#define MAX_BMMU_BUFFER_NUM (DECODE_BUFFER_NUM_MAX + 1) + + +#define INCPTR(p) ptr_atomic_wrap_inc(&p) + +#define DEC_CONTROL_FLAG_FORCE_2500_720_576_INTERLACE 0x0002 +#define DEC_CONTROL_FLAG_FORCE_3000_704_480_INTERLACE 0x0004 +#define DEC_CONTROL_FLAG_FORCE_2500_704_576_INTERLACE 0x0008 +#define DEC_CONTROL_FLAG_FORCE_2500_544_576_INTERLACE 0x0010 +#define DEC_CONTROL_FLAG_FORCE_2500_480_576_INTERLACE 0x0020 +#define DEC_CONTROL_INTERNAL_MASK 0x0fff +#define DEC_CONTROL_FLAG_FORCE_SEQ_INTERLACE 0x1000 + +#define INTERLACE_SEQ_ALWAYS + +#if 1/* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ +#define NV21 +#endif + + +enum { + FRAME_REPEAT_TOP, + FRAME_REPEAT_BOT, + FRAME_REPEAT_NONE +}; + +static struct vframe_s *vmpeg_vf_peek(void *); +static struct vframe_s *vmpeg_vf_get(void *); +static void vmpeg_vf_put(struct vframe_s *, void *); +static int vmpeg_vf_states(struct vframe_states *states, void *); +static int vmpeg_event_cb(int type, void *data, void *private_data); + +static int vmpeg12_prot_init(void); +static void vmpeg12_local_init(void); + +static const char vmpeg12_dec_id[] = "vmpeg12-dev"; +#define PROVIDER_NAME "decoder.mpeg12" +static const struct vframe_operations_s vmpeg_vf_provider = { + .peek = vmpeg_vf_peek, + .get = vmpeg_vf_get, + .put = vmpeg_vf_put, + .event_cb = vmpeg_event_cb, + .vf_states = vmpeg_vf_states, +}; +static void *mm_blk_handle; +static struct vframe_provider_s vmpeg_vf_prov; + +static DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE); +static DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE); +static DECLARE_KFIFO(recycle_q, struct vframe_s *, VF_POOL_SIZE); + +static const u32 frame_rate_tab[16] = { + 96000 / 30, 96000000 / 23976, 96000 / 24, 96000 / 25, + 9600000 / 2997, 96000 / 30, 96000 / 50, 9600000 / 5994, + 96000 / 60, + /* > 8 reserved, use 24 */ + 96000 / 24, 96000 / 24, 96000 / 24, 96000 / 24, + 96000 / 24, 96000 / 24, 96000 / 24 +}; + +static struct vframe_s vfpool[VF_POOL_SIZE]; +static struct vframe_s vfpool2[VF_POOL_SIZE]; +static int cur_pool_idx; +static s32 vfbuf_use[DECODE_BUFFER_NUM_MAX]; +static u32 dec_control; +static u32 frame_width, frame_height, frame_dur, frame_prog; +static u32 saved_resolution; +static struct timer_list recycle_timer; +static u32 stat; +static u32 buf_size = 32 * 1024 * 1024; +static u32 ccbuf_phyAddress; +static void *ccbuf_phyAddress_virt; +static int ccbuf_phyAddress_is_remaped_nocache; +static u32 lastpts; +static u32 fr_hint_status; +static u32 last_offset; + + +static DEFINE_SPINLOCK(lock); + +static u32 frame_rpt_state; + +static struct dec_sysinfo vmpeg12_amstream_dec_info; +static struct vdec_info *gvs; +static struct vdec_s *vdec; + +/* for error handling */ +static s32 frame_force_skip_flag; +static s32 error_frame_skip_level; +static s32 wait_buffer_counter; +static u32 first_i_frame_ready; +static u32 force_first_i_ready; + +static struct work_struct userdata_push_work; +static struct work_struct notify_work; +static struct work_struct reset_work; +static struct work_struct set_clk_work; +static bool is_reset; + +struct mpeg12_userdata_recored_t { + struct userdata_meta_info_t meta_info; + u32 rec_start; + u32 rec_len; +}; + +#define USERDATA_FIFO_NUM 256 + +struct mpeg12_userdata_info_t { + struct mpeg12_userdata_recored_t records[USERDATA_FIFO_NUM]; + u8 *data_buf; + u8 *data_buf_end; + u32 buf_len; + u32 read_index; + u32 write_index; + u32 last_wp; +}; + +static struct mpeg12_userdata_info_t *p_userdata_mgr; + + +static inline int pool_index(struct vframe_s *vf) +{ + if ((vf >= &vfpool[0]) && (vf <= &vfpool[VF_POOL_SIZE - 1])) + return 0; + else if ((vf >= &vfpool2[0]) && (vf <= &vfpool2[VF_POOL_SIZE - 1])) + return 1; + else + return -1; +} + +static inline u32 index2canvas(u32 index) +{ + const u32 canvas_tab[8] = { +#ifdef NV21 + 0x010100, 0x030302, 0x050504, 0x070706, + 0x090908, 0x0b0b0a, 0x0d0d0c, 0x0f0f0e +#else + 0x020100, 0x050403, 0x080706, 0x0b0a09, + 0x0e0d0c, 0x11100f, 0x141312, 0x171615 +#endif + }; + + return canvas_tab[index]; +} + +static void set_frame_info(struct vframe_s *vf) +{ + unsigned int ar_bits; + u32 temp; + +#ifdef CONFIG_AM_VDEC_MPEG12_LOG + bool first = (frame_width == 0) && (frame_height == 0); +#endif + temp = READ_VREG(MREG_PIC_WIDTH); + if (temp > 1920) + vf->width = frame_width = 1920; + else + vf->width = frame_width = temp; + + temp = READ_VREG(MREG_PIC_HEIGHT); + if (temp > 1088) + vf->height = frame_height = 1088; + else + vf->height = frame_height = temp; + + vf->flag = 0; + + if (frame_dur > 0) + vf->duration = frame_dur; + else { + int index = (READ_VREG(MREG_SEQ_INFO) >> 4) & 0xf; + vf->duration = frame_dur = frame_rate_tab[index]; + schedule_work(¬ify_work); + } + + gvs->frame_dur = vf->duration; + + ar_bits = READ_VREG(MREG_SEQ_INFO) & 0xf; + + if (ar_bits == 0x2) + vf->ratio_control = 0xc0 << DISP_RATIO_ASPECT_RATIO_BIT; + + else if (ar_bits == 0x3) + vf->ratio_control = 0x90 << DISP_RATIO_ASPECT_RATIO_BIT; + + else if (ar_bits == 0x4) + vf->ratio_control = 0x74 << DISP_RATIO_ASPECT_RATIO_BIT; + + else + vf->ratio_control = 0; + + amlog_level_if(first, LOG_LEVEL_INFO, + "mpeg2dec: w(%d), h(%d), dur(%d), dur-ES(%d)\n", + frame_width, frame_height, frame_dur, + frame_rate_tab[(READ_VREG(MREG_SEQ_INFO) >> 4) & 0xf]); +} + +static bool error_skip(u32 info, struct vframe_s *vf) +{ + if (error_frame_skip_level) { + /* skip error frame */ + if ((info & PICINFO_ERROR) || (frame_force_skip_flag)) { + if ((info & PICINFO_ERROR) == 0) { + if ((info & PICINFO_TYPE_MASK) == + PICINFO_TYPE_I) + frame_force_skip_flag = 0; + } else { + if (error_frame_skip_level >= 2) + frame_force_skip_flag = 1; + } + if ((info & PICINFO_ERROR) || (frame_force_skip_flag)) + return true; + } + } + + return false; +} + + +static void aml_swap_data(uint8_t *user_data, int ud_size) +{ + int swap_blocks, i, j, k, m; + unsigned char c_temp; + + /* swap byte order */ + swap_blocks = ud_size / 8; + for (i = 0; i < swap_blocks; i++) { + j = i * 8; + k = j + 7; + for (m = 0; m < 4; m++) { + c_temp = user_data[j]; + user_data[j++] = user_data[k]; + user_data[k--] = c_temp; + } + } +} + +/* +#define DUMP_USER_DATA +*/ +#ifdef DUMP_USER_DATA +static int last_wp; +#define DUMP_USER_DATA_HEX + + +#ifdef DUMP_USER_DATA_HEX +static void print_data(unsigned char *pdata, + int len, + unsigned int flag, + unsigned int duration, + unsigned int vpts, + unsigned int vpts_valid, + int rec_id, + u32 reference) +{ + int nLeft; + + nLeft = len; + + pr_info("%d len:%d, flag:0x%x, dur:%d, vpts:0x%x, valid:%d, refer:%d\n", + rec_id, len, flag, + duration, vpts, vpts_valid, + reference); + while (nLeft >= 16) { + pr_info("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + pdata[0], pdata[1], pdata[2], pdata[3], + pdata[4], pdata[5], pdata[6], pdata[7], + pdata[8], pdata[9], pdata[10], pdata[11], + pdata[12], pdata[13], pdata[14], pdata[15]); + nLeft -= 16; + pdata += 16; + } + + + while (nLeft > 0) { + pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n", + pdata[0], pdata[1], pdata[2], pdata[3], + pdata[4], pdata[5], pdata[6], pdata[7]); + nLeft -= 8; + pdata += 8; + } +} +#endif + + +#define DEBUG_CC_DUMP_ASCII + +#ifdef DEBUG_CC_DUMP_ASCII +static int vbi_to_ascii(int c) +{ + if (c < 0) + return '?'; + + c &= 0x7F; + + if (c < 0x20 || c >= 0x7F) + return '.'; + + return c; +} + +static void dump_cc_ascii(const uint8_t *buf, int poc) +{ + int cc_flag; + int cc_count; + int i; + int szAscii[32]; + int index = 0; + + cc_flag = buf[1] & 0x40; + if (!cc_flag) { + pr_info("### cc_flag is invalid\n"); + return; + } + cc_count = buf[1] & 0x1f; + + for (i = 0; i < cc_count; ++i) { + unsigned int b0; + unsigned int cc_valid; + unsigned int cc_type; + unsigned char cc_data1; + unsigned char cc_data2; + + b0 = buf[3 + i * 3]; + cc_valid = b0 & 4; + cc_type = b0 & 3; + cc_data1 = buf[4 + i * 3]; + cc_data2 = buf[5 + i * 3]; + + + if (cc_type == 0) { + /* NTSC pair, Line 21 */ + szAscii[index++] = vbi_to_ascii(cc_data1); + szAscii[index++] = vbi_to_ascii(cc_data2); + if ((!cc_valid) || (i >= 3)) + break; + } + } + switch (index) { + case 8: + pr_info("push poc:%d : %c %c %c %c %c %c %c %c\n", + poc, + szAscii[0], szAscii[1], szAscii[2], szAscii[3], + szAscii[4], szAscii[5], szAscii[6], szAscii[7]); + break; + case 7: + pr_info("push poc:%d : %c %c %c %c %c %c %c\n", + poc, + szAscii[0], szAscii[1], szAscii[2], szAscii[3], + szAscii[4], szAscii[5], szAscii[6]); + break; + case 6: + pr_info("push poc:%d : %c %c %c %c %c %c\n", poc, + szAscii[0], szAscii[1], szAscii[2], szAscii[3], + szAscii[4], szAscii[5]); + break; + case 5: + pr_info("push poc:%d : %c %c %c %c %c\n", poc, + szAscii[0], szAscii[1], szAscii[2], szAscii[3], + szAscii[4]); + break; + case 4: + pr_info("push poc:%d : %c %c %c %c\n", poc, + szAscii[0], szAscii[1], szAscii[2], szAscii[3]); + break; + case 3: + pr_info("push poc:%d : %c %c %c\n", poc, + szAscii[0], szAscii[1], szAscii[2]); + break; + case 2: + pr_info("push poc:%d : %c %c\n", poc, + szAscii[0], szAscii[1]); + break; + case 1: + pr_info("push poc:%d : %c\n", poc, szAscii[0]); + break; + default: + pr_info("push poc:%d and no CC data: index = %d\n", + poc, index); + break; + } +} +#endif + + +static int is_atsc(u8 *pdata) +{ + if ((pdata[0] == 0x47) && + (pdata[1] == 0x41) && + (pdata[2] == 0x39) && + (pdata[3] == 0x34)) + return 1; + else + return 0; +} +/* +#define DUMP_HEAD_INFO_DATA +*/ +static void dump_data(u8 *pdata, + unsigned int user_data_length, + unsigned int flag, + unsigned int duration, + unsigned int vpts, + unsigned int vpts_valid, + int rec_id, + u32 reference) +{ + unsigned char szBuf[256]; + + + memset(szBuf, 0, 256); + memcpy(szBuf, pdata, user_data_length); + + aml_swap_data(szBuf, user_data_length); +#ifdef DUMP_USER_DATA_HEX + print_data(szBuf, + user_data_length, + flag, + duration, + vpts, + vpts_valid, + rec_id, + reference); +#endif + +#ifdef DEBUG_CC_DUMP_ASCII +#ifdef DUMP_HEAD_INFO_DATA + if (is_atsc(szBuf+8)) + dump_cc_ascii(szBuf+8+4, reference); +#else + if (is_atsc(szBuf)) + dump_cc_ascii(szBuf+4, reference); +#endif +#endif +} + + + + +#define MAX_USER_DATA_SIZE 1572864 +static void *user_data_buf; +static unsigned char *pbuf_start; +static int total_len; +static int bskip; +static int n_userdata_id; + +static void reset_user_data_buf(void) +{ + total_len = 0; + pbuf_start = user_data_buf; + bskip = 0; + n_userdata_id = 0; +} + +static void push_to_buf(u8 *pdata, int len, struct userdata_meta_info_t *pmeta, + u32 reference) +{ + u32 *pLen; + int info_cnt; + u8 *pbuf_end; + + if (!user_data_buf) + return; + + if (bskip) { + pr_info("over size, skip\n"); + return; + } + info_cnt = 0; + pLen = (u32 *)pbuf_start; + + *pLen = len; + pbuf_start += sizeof(u32); + info_cnt++; + pLen++; + + *pLen = pmeta->duration; + pbuf_start += sizeof(u32); + info_cnt++; + pLen++; + + *pLen = pmeta->flags; + pbuf_start += sizeof(u32); + info_cnt++; + pLen++; + + *pLen = pmeta->vpts; + pbuf_start += sizeof(u32); + info_cnt++; + pLen++; + + *pLen = pmeta->vpts_valid; + pbuf_start += sizeof(u32); + info_cnt++; + pLen++; + + + *pLen = n_userdata_id; + pbuf_start += sizeof(u32); + info_cnt++; + pLen++; + + *pLen = reference; + pbuf_start += sizeof(u32); + info_cnt++; + pLen++; + + + + pbuf_end = (u8 *)ccbuf_phyAddress_virt + CCBUF_SIZE; + if (pdata + len > pbuf_end) { + int first_section_len; + + first_section_len = pbuf_end - pdata; + memcpy(pbuf_start, pdata, first_section_len); + pdata = (u8 *)ccbuf_phyAddress_virt; + pbuf_start += first_section_len; + memcpy(pbuf_start, pdata, len - first_section_len); + pbuf_start += len - first_section_len; + } else { + memcpy(pbuf_start, pdata, len); + pbuf_start += len; + } + + total_len += len + info_cnt * sizeof(u32); + if (total_len >= MAX_USER_DATA_SIZE-4096) + bskip = 1; +} + +static void dump_userdata_info(void *puser_data, + int len, + struct userdata_meta_info_t *pmeta, + u32 reference) +{ + u8 *pstart; + + pstart = (u8 *)puser_data; + +#ifdef DUMP_HEAD_INFO_DATA + push_to_buf(pstart, len, pmeta, reference); +#else + push_to_buf(pstart+8, len - 8, pmeta, reference); +#endif +} + +static void show_user_data_buf(void) +{ + u8 *pbuf; + int len; + unsigned int flag; + unsigned int duration; + unsigned int vpts; + unsigned int vpts_valid; + int rec_id; + u32 reference; + + pr_info("show user data buf\n"); + pbuf = user_data_buf; + + while (pbuf < pbuf_start) { + u32 *pLen; + + pLen = (u32 *)pbuf; + + len = *pLen; + pLen++; + pbuf += sizeof(u32); + + duration = *pLen; + pLen++; + pbuf += sizeof(u32); + + flag = *pLen; + pLen++; + pbuf += sizeof(u32); + + vpts = *pLen; + pLen++; + pbuf += sizeof(u32); + + vpts_valid = *pLen; + pLen++; + pbuf += sizeof(u32); + + rec_id = *pLen; + pLen++; + pbuf += sizeof(u32); + + reference = *pLen; + pLen++; + pbuf += sizeof(u32); + + + dump_data(pbuf, len, flag, duration, + vpts, vpts_valid, rec_id, reference); + pbuf += len; + msleep(30); + } +} +#endif + +static void vmpeg12_add_userdata(struct userdata_meta_info_t meta_info, + int wp, + u32 reference); +/* +#define PRINT_HEAD_INFO +*/ +static void userdata_push_do_work(struct work_struct *work) +{ + u32 reg; + u32 offset, pts; + u64 pts_us64 = 0; + u8 *pdata; + u8 head_info[8]; + struct userdata_meta_info_t meta_info; + u32 wp; + u32 index; + u32 picture_struct; + u32 reference; + u32 picture_type; + u32 temp; +#ifdef PRINT_HEAD_INFO + u8 *ptype_str; +#endif + memset(&meta_info, 0, sizeof(meta_info)); + + meta_info.duration = frame_dur; + + reg = READ_VREG(AV_SCRATCH_M); + meta_info.flags = ((reg >> 30) << 1); + meta_info.flags |= (VFORMAT_MPEG12 << 3); + /* check top_field_first flag */ + if ((reg >> 28) & 0x1) { + meta_info.flags |= (1 << 10); + meta_info.flags |= (((reg >> 29) & 0x1) << 11); + } + + offset = READ_VREG(AV_SCRATCH_N); + if (offset != last_offset) { + meta_info.flags |= 1; + last_offset = offset; + } + + if (pts_pickout_offset_us64 + (PTS_TYPE_VIDEO, offset, &pts, 0, &pts_us64) != 0) { + pr_info("pick out pts failed by offset = 0x%x\n", offset); + pts = -1; + meta_info.vpts_valid = 0; + } else + meta_info.vpts_valid = 1; + meta_info.vpts = pts; + + if (!ccbuf_phyAddress_is_remaped_nocache && + ccbuf_phyAddress && + ccbuf_phyAddress_virt) { + codec_mm_dma_flush( + ccbuf_phyAddress_virt, + CCBUF_SIZE, + DMA_FROM_DEVICE); + } + + + if (p_userdata_mgr) { + int new_wp; + + new_wp = reg & 0xffff; + if (new_wp < p_userdata_mgr->last_wp) + pdata = (u8 *)ccbuf_phyAddress_virt; + else + pdata = (u8 *)ccbuf_phyAddress_virt + + p_userdata_mgr->last_wp; + memcpy(head_info, pdata, 8); + } else + memset(head_info, 0, 8); + aml_swap_data(head_info, 8); + + wp = (head_info[0] << 8 | head_info[1]); + index = (head_info[2] << 8 | head_info[3]); + + picture_struct = (head_info[6] << 8 | head_info[7]); + temp = (head_info[4] << 8 | head_info[5]); + reference = temp & 0x3FF; + picture_type = (temp >> 10) & 0x7; + +#if 0 + pr_info("index = %d, wp = %d, ref = %d, type = %d, struct = 0x%x, vpts:0x%x\n", + index, wp, reference, + picture_type, picture_struct, meta_info.vpts); +#endif + switch (picture_type) { + case 1: + /* pr_info("I type, pos:%d\n", + (meta_info.flags>>1)&0x3); */ + meta_info.flags |= (1<<7); +#ifdef PRINT_HEAD_INFO + ptype_str = " I"; +#endif + break; + case 2: + /* pr_info("P type, pos:%d\n", + (meta_info.flags>>1)&0x3); */ + meta_info.flags |= (2<<7); +#ifdef PRINT_HEAD_INFO + ptype_str = " P"; +#endif + break; + case 3: + /* pr_info("B type, pos:%d\n", + (meta_info.flags>>1)&0x3); */ + meta_info.flags |= (3<<7); +#ifdef PRINT_HEAD_INFO + ptype_str = " B"; +#endif + break; + case 4: + /* pr_info("D type, pos:%d\n", + (meta_info.flags>>1)&0x3); */ + meta_info.flags |= (4<<7); +#ifdef PRINT_HEAD_INFO + ptype_str = " D"; +#endif + break; + default: + /* pr_info("Unknown type:0x%x, pos:%d\n", + pheader->picture_coding_type, + (meta_info.flags>>1)&0x3); */ +#ifdef PRINT_HEAD_INFO + ptype_str = " U"; +#endif + break; + } +#ifdef PRINT_HEAD_INFO + pr_info("ref:%d, type:%s, ext:%d, offset:0x%x, first:%d, id:%d\n", + reference, ptype_str, + (reg >> 30), offset, + (reg >> 28)&0x3, + n_userdata_id); +#endif + vmpeg12_add_userdata(meta_info, reg & 0xffff, reference); + + WRITE_VREG(AV_SCRATCH_M, 0); +} + +static void vmpeg12_notify_work(struct work_struct *work) +{ + pr_info("frame duration changed %d\n", frame_dur); + if (fr_hint_status == VDEC_NEED_HINT) { + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_FR_HINT, + (void *)((unsigned long)frame_dur)); + fr_hint_status = VDEC_HINTED; + } + return; +} +static irqreturn_t vmpeg12_isr(int irq, void *dev_id) +{ + u32 reg, info, seqinfo, offset, pts, pts_valid = 0; + struct vframe_s *vf; + u64 pts_us64 = 0; + + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + reg = READ_VREG(MREG_BUFFEROUT); + + if (reg) { + info = READ_VREG(MREG_PIC_INFO); + offset = READ_VREG(MREG_FRAME_OFFSET); + seqinfo = READ_VREG(MREG_SEQ_INFO); + + if ((first_i_frame_ready == 0) && + ((info & PICINFO_TYPE_MASK) == PICINFO_TYPE_I) && + ((info & PICINFO_ERROR) == 0)) + first_i_frame_ready = 1; + + if ((pts_lookup_offset_us64 + (PTS_TYPE_VIDEO, offset, &pts, 0, &pts_us64) == 0) + && (((info & PICINFO_TYPE_MASK) == PICINFO_TYPE_I) + || ((info & PICINFO_TYPE_MASK) == + PICINFO_TYPE_P))) + pts_valid = 1; + + if (pts_valid && lastpts == pts) + pts_valid = 0; + if (pts_valid) + lastpts = pts; + /*if (frame_prog == 0) */ + { + frame_prog = info & PICINFO_PROG; + if ((seqinfo & SEQINFO_EXT_AVAILABLE) + && (!(seqinfo & SEQINFO_PROG))) + frame_prog = 0; + } + + if ((dec_control & + DEC_CONTROL_FLAG_FORCE_2500_720_576_INTERLACE) + && (frame_width == 720 || frame_width == 480) + && (frame_height == 576) + && (frame_dur == 3840)) + frame_prog = 0; + else if ((dec_control & + DEC_CONTROL_FLAG_FORCE_3000_704_480_INTERLACE) + && (frame_width == 704) && (frame_height == 480) + && (frame_dur == 3200)) + frame_prog = 0; + else if ((dec_control & + DEC_CONTROL_FLAG_FORCE_2500_704_576_INTERLACE) + && (frame_width == 704) && (frame_height == 576) + && (frame_dur == 3840)) + frame_prog = 0; + else if ((dec_control & + DEC_CONTROL_FLAG_FORCE_2500_544_576_INTERLACE) + && (frame_width == 544) && (frame_height == 576) + && (frame_dur == 3840)) + frame_prog = 0; + else if ((dec_control & + DEC_CONTROL_FLAG_FORCE_2500_480_576_INTERLACE) + && (frame_width == 480) && (frame_height == 576) + && (frame_dur == 3840)) + frame_prog = 0; + else if (dec_control & DEC_CONTROL_FLAG_FORCE_SEQ_INTERLACE) + frame_prog = 0; + if (frame_prog & PICINFO_PROG) { + u32 index = ((reg & 0xf) - 1) & 7; + + seqinfo = READ_VREG(MREG_SEQ_INFO); + + if (kfifo_get(&newframe_q, &vf) == 0) { + pr_info + ("fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + + set_frame_info(vf); + vf->signal_type = 0; + vf->index = index; +#ifdef NV21 + vf->type = + VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD | + VIDTYPE_VIU_NV21; +#else + vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD; +#endif + if ((seqinfo & SEQINFO_EXT_AVAILABLE) + && (seqinfo & SEQINFO_PROG)) { + if (info & PICINFO_RPT_FIRST) { + if (info & PICINFO_TOP_FIRST) { + vf->duration = + vf->duration * 3; + /* repeat three times */ + } else { + vf->duration = + vf->duration * 2; + /* repeat two times */ + } + } + vf->duration_pulldown = 0; + /* no pull down */ + + } else { + vf->duration_pulldown = + (info & PICINFO_RPT_FIRST) ? + vf->duration >> 1 : 0; + } + + /*count info*/ + vdec_count_info(gvs, info & PICINFO_ERROR, offset); + + vf->duration += vf->duration_pulldown; + vf->canvas0Addr = vf->canvas1Addr = + index2canvas(index); + vf->orientation = 0; + vf->pts = (pts_valid) ? pts : 0; + vf->pts_us64 = (pts_valid) ? pts_us64 : 0; + vf->type_original = vf->type; + + vfbuf_use[index] = 1; + + if ((error_skip(info, vf)) || + ((first_i_frame_ready == 0) + && ((PICINFO_TYPE_MASK & info) != + PICINFO_TYPE_I))) { + gvs->drop_frame_count++; + kfifo_put(&recycle_q, + (const struct vframe_s *)vf); + } else { + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + index); + kfifo_put(&display_q, + (const struct vframe_s *)vf); + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + } + + } else { + u32 index = ((reg & 0xf) - 1) & 7; + int first_field_type = (info & PICINFO_TOP_FIRST) ? + VIDTYPE_INTERLACE_TOP : + VIDTYPE_INTERLACE_BOTTOM; + +#ifdef INTERLACE_SEQ_ALWAYS + /* once an interlaced sequence exist, + *always force interlaced type + */ + /* to make DI easy. */ + dec_control |= DEC_CONTROL_FLAG_FORCE_SEQ_INTERLACE; +#endif +#if 0 + if (info & PICINFO_FRAME) { + frame_rpt_state = + (info & PICINFO_TOP_FIRST) ? + FRAME_REPEAT_TOP : FRAME_REPEAT_BOT; + } else { + if (frame_rpt_state == FRAME_REPEAT_TOP) { + first_field_type = + VIDTYPE_INTERLACE_TOP; + } else if (frame_rpt_state == + FRAME_REPEAT_BOT) { + first_field_type = + VIDTYPE_INTERLACE_BOTTOM; + } + frame_rpt_state = FRAME_REPEAT_NONE; + } +#else + frame_rpt_state = FRAME_REPEAT_NONE; +#endif + if (kfifo_get(&newframe_q, &vf) == 0) { + pr_info + ("fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + if (info & PICINFO_RPT_FIRST) + vfbuf_use[index] = 3; + else + vfbuf_use[index] = 2; + + set_frame_info(vf); + vf->signal_type = 0; + vf->index = index; + vf->type = + (first_field_type == VIDTYPE_INTERLACE_TOP) ? + VIDTYPE_INTERLACE_TOP : + VIDTYPE_INTERLACE_BOTTOM; +#ifdef NV21 + vf->type |= VIDTYPE_VIU_NV21; +#endif + if (info & PICINFO_RPT_FIRST) + vf->duration /= 3; + else + vf->duration >>= 1; + vf->duration_pulldown = (info & PICINFO_RPT_FIRST) ? + vf->duration >> 1 : 0; + vf->duration += vf->duration_pulldown; + vf->orientation = 0; + vf->canvas0Addr = vf->canvas1Addr = + index2canvas(index); + vf->pts = (pts_valid) ? pts : 0; + vf->pts_us64 = (pts_valid) ? pts_us64 : 0; + vf->type_original = vf->type; + + if ((error_skip(info, vf)) || + ((first_i_frame_ready == 0) + && ((PICINFO_TYPE_MASK & info) != + PICINFO_TYPE_I))) { + gvs->drop_frame_count++; + kfifo_put(&recycle_q, + (const struct vframe_s *)vf); + } else { + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + index); + kfifo_put(&display_q, + (const struct vframe_s *)vf); + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + } + + if (kfifo_get(&newframe_q, &vf) == 0) { + pr_info + ("fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + + set_frame_info(vf); + vf->signal_type = 0; + vf->index = index; + vf->type = (first_field_type == + VIDTYPE_INTERLACE_TOP) ? + VIDTYPE_INTERLACE_BOTTOM : + VIDTYPE_INTERLACE_TOP; +#ifdef NV21 + vf->type |= VIDTYPE_VIU_NV21; +#endif + if (info & PICINFO_RPT_FIRST) + vf->duration /= 3; + else + vf->duration >>= 1; + vf->duration_pulldown = (info & PICINFO_RPT_FIRST) ? + vf->duration >> 1 : 0; + vf->duration += vf->duration_pulldown; + vf->orientation = 0; + vf->canvas0Addr = vf->canvas1Addr = + index2canvas(index); + vf->pts = 0; + vf->pts_us64 = 0; + vf->type_original = vf->type; + + /*count info*/ + vdec_count_info(gvs, info & PICINFO_ERROR, offset); + + if ((error_skip(info, vf)) || + ((first_i_frame_ready == 0) + && ((PICINFO_TYPE_MASK & info) != + PICINFO_TYPE_I))) { + gvs->drop_frame_count++; + kfifo_put(&recycle_q, + (const struct vframe_s *)vf); + } else { + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + index); + kfifo_put(&display_q, + (const struct vframe_s *)vf); + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + } + + if (info & PICINFO_RPT_FIRST) { + if (kfifo_get(&newframe_q, &vf) == 0) { + pr_info("error, no available buffer slot."); + return IRQ_HANDLED; + } + + set_frame_info(vf); + + vf->index = index; + vf->type = (first_field_type == + VIDTYPE_INTERLACE_TOP) ? + VIDTYPE_INTERLACE_TOP : + VIDTYPE_INTERLACE_BOTTOM; +#ifdef NV21 + vf->type |= VIDTYPE_VIU_NV21; +#endif + vf->duration /= 3; + vf->duration_pulldown = + (info & PICINFO_RPT_FIRST) ? + vf->duration >> 1 : 0; + vf->duration += vf->duration_pulldown; + vf->orientation = 0; + vf->canvas0Addr = vf->canvas1Addr = + index2canvas(index); + vf->pts = 0; + vf->pts_us64 = 0; + if ((error_skip(info, vf)) || + ((first_i_frame_ready == 0) + && ((PICINFO_TYPE_MASK & info) + != PICINFO_TYPE_I))) { + kfifo_put(&recycle_q, + (const struct vframe_s *)vf); + } else { + kfifo_put(&display_q, + (const struct vframe_s *)vf); + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + } + } + } + WRITE_VREG(MREG_BUFFEROUT, 0); + } + + reg = READ_VREG(AV_SCRATCH_M); + if (reg & (1<<16)) + schedule_work(&userdata_push_work); + + return IRQ_HANDLED; +} + +static struct vframe_s *vmpeg_vf_peek(void *op_arg) +{ + struct vframe_s *vf; + + if (kfifo_peek(&display_q, &vf)) + return vf; + + return NULL; +} + +static struct vframe_s *vmpeg_vf_get(void *op_arg) +{ + struct vframe_s *vf; + + if (kfifo_get(&display_q, &vf)) + return vf; + + return NULL; +} + +static void vmpeg_vf_put(struct vframe_s *vf, void *op_arg) +{ + if (pool_index(vf) == cur_pool_idx) + kfifo_put(&recycle_q, (const struct vframe_s *)vf); +} + +static int vmpeg_event_cb(int type, void *data, void *private_data) +{ + if (type & VFRAME_EVENT_RECEIVER_RESET) { + unsigned long flags; + + amvdec_stop(); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_light_unreg_provider(&vmpeg_vf_prov); +#endif + spin_lock_irqsave(&lock, flags); + vmpeg12_local_init(); + vmpeg12_prot_init(); + spin_unlock_irqrestore(&lock, flags); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_reg_provider(&vmpeg_vf_prov); +#endif + amvdec_start(); + } + return 0; +} + +static int vmpeg_vf_states(struct vframe_states *states, void *op_arg) +{ + unsigned long flags; + + spin_lock_irqsave(&lock, flags); + + states->vf_pool_size = VF_POOL_SIZE; + states->buf_free_num = kfifo_len(&newframe_q); + states->buf_avail_num = kfifo_len(&display_q); + states->buf_recycle_num = kfifo_len(&recycle_q); + + spin_unlock_irqrestore(&lock, flags); + + return 0; +} + +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER +static void vmpeg12_ppmgr_reset(void) +{ + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_RESET, NULL); + + vmpeg12_local_init(); + + pr_info("vmpeg12dec: vf_ppmgr_reset\n"); +} +#endif + +static void vmpeg12_reset_userdata_fifo(struct vdec_s *vdec, int bInit); + +static void reset_do_work(struct work_struct *work) +{ + amvdec_stop(); + +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vmpeg12_ppmgr_reset(); +#else + vf_light_unreg_provider(&vmpeg_vf_prov); + vmpeg12_local_init(); + vf_reg_provider(&vmpeg_vf_prov); +#endif + vmpeg12_prot_init(); + vmpeg12_reset_userdata_fifo(vdec, 1); +#ifdef DUMP_USER_DATA + last_wp = 0; +#endif + + amvdec_start(); +} + +static void vmpeg12_set_clk(struct work_struct *work) +{ + if (frame_dur > 0 && saved_resolution != + frame_width * frame_height * (96000 / frame_dur)) { + int fps = 96000 / frame_dur; + + saved_resolution = frame_width * frame_height * fps; + vdec_source_changed(VFORMAT_MPEG12, + frame_width, frame_height, fps); + } +} + + +static void vmpeg_put_timer_func(unsigned long arg) +{ + struct timer_list *timer = (struct timer_list *)arg; + int fatal_reset = 0; + + enum receviver_start_e state = RECEIVER_INACTIVE; + + if (vf_get_receiver(PROVIDER_NAME)) { + state = vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_QUREY_STATE, NULL); + if ((state == RECEIVER_STATE_NULL) + || (state == RECEIVER_STATE_NONE)) { + /* receiver has no event_cb or + *receiver's event_cb does not process this event + */ + state = RECEIVER_INACTIVE; + } + } else + state = RECEIVER_INACTIVE; + + if (READ_VREG(MREG_FATAL_ERROR) == 1) + fatal_reset = 1; + + if ((READ_VREG(MREG_WAIT_BUFFER) != 0) && + (kfifo_is_empty(&recycle_q)) && + (kfifo_is_empty(&display_q)) && (state == RECEIVER_INACTIVE)) { + if (++wait_buffer_counter > 4) + fatal_reset = 1; + + } else + wait_buffer_counter = 0; + + if (fatal_reset && (kfifo_is_empty(&display_q))) { + pr_info("$$$$decoder is waiting for buffer or fatal reset.\n"); + schedule_work(&reset_work); + } + + while (!kfifo_is_empty(&recycle_q) && (READ_VREG(MREG_BUFFERIN) == 0)) { + struct vframe_s *vf; + + if (kfifo_get(&recycle_q, &vf)) { + if ((vf->index < DECODE_BUFFER_NUM_MAX) && + (--vfbuf_use[vf->index] == 0)) { + WRITE_VREG(MREG_BUFFERIN, vf->index + 1); + vf->index = DECODE_BUFFER_NUM_MAX; + } + + if (pool_index(vf) == cur_pool_idx) { + kfifo_put(&newframe_q, + (const struct vframe_s *)vf); + } + } + } + + schedule_work(&set_clk_work); + + timer->expires = jiffies + PUT_INTERVAL; + + add_timer(timer); +} + +int vmpeg12_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus) +{ + vstatus->frame_width = frame_width; + vstatus->frame_height = frame_height; + if (frame_dur != 0) + vstatus->frame_rate = 96000 / frame_dur; + else + vstatus->frame_rate = -1; + vstatus->error_count = READ_VREG(AV_SCRATCH_C); + vstatus->status = stat; + vstatus->bit_rate = gvs->bit_rate; + vstatus->frame_dur = frame_dur; + vstatus->frame_data = gvs->frame_data; + vstatus->total_data = gvs->total_data; + vstatus->frame_count = gvs->frame_count; + vstatus->error_frame_count = gvs->error_frame_count; + vstatus->drop_frame_count = gvs->drop_frame_count; + vstatus->total_data = gvs->total_data; + vstatus->samp_cnt = gvs->samp_cnt; + vstatus->offset = gvs->offset; + snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name), + "%s", DRIVER_NAME); + + return 0; +} + +int vmpeg12_set_isreset(struct vdec_s *vdec, int isreset) +{ + is_reset = isreset; + return 0; +} + +static DEFINE_MUTEX(userdata_mutex); + + +void vmpeg12_crate_userdata_manager(u8 *userdata_buf, int buf_len) +{ + mutex_lock(&userdata_mutex); + + p_userdata_mgr = (struct mpeg12_userdata_info_t *) + vmalloc(sizeof(struct mpeg12_userdata_info_t)); + if (p_userdata_mgr) { + memset(p_userdata_mgr, 0, + sizeof(struct mpeg12_userdata_info_t)); + p_userdata_mgr->data_buf = userdata_buf; + p_userdata_mgr->buf_len = buf_len; + p_userdata_mgr->data_buf_end = userdata_buf + buf_len; + } + mutex_unlock(&userdata_mutex); +} + +void vmpeg12_destroy_userdata_manager(void) +{ + mutex_lock(&userdata_mutex); + + if (p_userdata_mgr) { + vfree(p_userdata_mgr); + p_userdata_mgr = NULL; + } + mutex_unlock(&userdata_mutex); +} + +static void vmpeg12_add_userdata(struct userdata_meta_info_t meta_info, + int wp, + u32 reference) +{ + struct mpeg12_userdata_recored_t *p_userdata_rec; + int data_length; + + mutex_lock(&userdata_mutex); + + if (p_userdata_mgr) { + if (wp > p_userdata_mgr->last_wp) + data_length = wp - p_userdata_mgr->last_wp; + else { + p_userdata_mgr->last_wp = 0; + data_length = wp - p_userdata_mgr->last_wp; + } + + if (data_length & 0x7) + data_length = (((data_length + 8) >> 3) << 3); +/* +pr_info("wakeup_push: ri:%d, wi:%d, data_len:%d, last_wp:%d, wp:%d, id = %d\n", + p_userdata_mgr->read_index, + p_userdata_mgr->write_index, + data_length, + p_userdata_mgr->last_wp, + wp, + n_userdata_id); +*/ + p_userdata_rec = p_userdata_mgr->records + + p_userdata_mgr->write_index; + p_userdata_rec->meta_info = meta_info; + p_userdata_rec->rec_start = p_userdata_mgr->last_wp; + p_userdata_rec->rec_len = data_length; + p_userdata_mgr->last_wp = wp; + +#ifdef DUMP_USER_DATA + dump_userdata_info(p_userdata_mgr->data_buf + + p_userdata_rec->rec_start, + data_length, + &meta_info, + reference); + n_userdata_id++; +#endif + + p_userdata_mgr->write_index++; + if (p_userdata_mgr->write_index >= USERDATA_FIFO_NUM) + p_userdata_mgr->write_index = 0; + } + mutex_unlock(&userdata_mutex); + + vdec_wakeup_userdata_poll(vdec); +} + + +static int vmpeg12_user_data_read(struct vdec_s *vdec, + struct userdata_param_t *puserdata_para) +{ + int rec_ri, rec_wi; + int rec_len; + u8 *rec_data_start; + u8 *pdest_buf; + struct mpeg12_userdata_recored_t *p_userdata_rec; + + + u32 data_size; + u32 res; + int copy_ok = 1; + + pdest_buf = (void *)(puserdata_para->pbuf_addr); + mutex_lock(&userdata_mutex); + + if (!p_userdata_mgr) { + mutex_unlock(&userdata_mutex); + return 0; + } +/* + pr_info("ri = %d, wi = %d\n", + p_userdata_mgr->read_index, + p_userdata_mgr->write_index); +*/ + rec_ri = p_userdata_mgr->read_index; + rec_wi = p_userdata_mgr->write_index; + + if (rec_ri == rec_wi) { + mutex_unlock(&userdata_mutex); + return 0; + } + + p_userdata_rec = p_userdata_mgr->records + rec_ri; + + rec_len = p_userdata_rec->rec_len; + rec_data_start = p_userdata_rec->rec_start + p_userdata_mgr->data_buf; +/* + pr_info("rec_len:%d, rec_start:%d, buf_len:%d\n", + p_userdata_rec->rec_len, + p_userdata_rec->rec_start, + puserdata_para->buf_len); +*/ + if (rec_len <= puserdata_para->buf_len) { + /* dvb user data buffer is enought to copy the whole recored. */ + data_size = rec_len; + if (rec_data_start + data_size + > p_userdata_mgr->data_buf_end) { + int first_section_len; + + first_section_len = p_userdata_mgr->buf_len + - p_userdata_rec->rec_start; + res = (u32)copy_to_user((void *)pdest_buf, + (void *)rec_data_start, + first_section_len); + if (res) { + pr_info("p1 read not end res=%d, request=%d\n", + res, first_section_len); + copy_ok = 0; + + p_userdata_rec->rec_len -= + first_section_len - res; + p_userdata_rec->rec_start += + first_section_len - res; + puserdata_para->data_size = + first_section_len - res; + } else { + res = (u32)copy_to_user( + (void *)(pdest_buf+first_section_len), + (void *)p_userdata_mgr->data_buf, + data_size - first_section_len); + if (res) { + pr_info("p2 read not end res=%d, request=%d\n", + res, data_size); + copy_ok = 0; + } + p_userdata_rec->rec_len -= data_size - res; + p_userdata_rec->rec_start = + data_size - first_section_len - res; + puserdata_para->data_size = data_size - res; + } + } else { + res = (u32)copy_to_user((void *)pdest_buf, + (void *)rec_data_start, + data_size); + if (res) { + pr_info("p3 read not end res=%d, request=%d\n", + res, data_size); + copy_ok = 0; + } + p_userdata_rec->rec_len -= data_size - res; + p_userdata_rec->rec_start += data_size - res; + puserdata_para->data_size = data_size - res; + } + + if (copy_ok) { + p_userdata_mgr->read_index++; + if (p_userdata_mgr->read_index >= USERDATA_FIFO_NUM) + p_userdata_mgr->read_index = 0; + } + } else { + /* dvb user data buffer is not enought + to copy the whole recored. */ + data_size = puserdata_para->buf_len; + if (rec_data_start + data_size + > p_userdata_mgr->data_buf_end) { + int first_section_len; + + first_section_len = p_userdata_mgr->buf_len + - p_userdata_rec->rec_start; + res = (u32)copy_to_user((void *)pdest_buf, + (void *)rec_data_start, + first_section_len); + if (res) { + pr_info("p4 read not end res=%d, request=%d\n", + res, first_section_len); + copy_ok = 0; + p_userdata_rec->rec_len -= + first_section_len - res; + p_userdata_rec->rec_start += + first_section_len - res; + puserdata_para->data_size = + first_section_len - res; + } else { + /* first secton copy is ok*/ + res = (u32)copy_to_user( + (void *)(pdest_buf+first_section_len), + (void *)p_userdata_mgr->data_buf, + data_size - first_section_len); + if (res) { + pr_info("p5 read not end res=%d, request=%d\n", + res, + data_size - first_section_len); + copy_ok = 0; + } + + p_userdata_rec->rec_len -= data_size - res; + p_userdata_rec->rec_start = + data_size - first_section_len - res; + puserdata_para->data_size = data_size - res; + } + } else { + res = (u32)copy_to_user((void *)pdest_buf, + (void *)rec_data_start, + data_size); + if (res) { + pr_info("p6 read not end res=%d, request=%d\n", + res, data_size); + copy_ok = 0; + } + + p_userdata_rec->rec_len -= data_size - res; + p_userdata_rec->rec_start += data_size - res; + puserdata_para->data_size = data_size - res; + } + + if (copy_ok) { + p_userdata_mgr->read_index++; + if (p_userdata_mgr->read_index + >= USERDATA_FIFO_NUM) + p_userdata_mgr->read_index = 0; + } + + } + res = (u32)copy_to_user((void *)&puserdata_para->meta_info, + (void *)&p_userdata_rec->meta_info, + sizeof(p_userdata_rec->meta_info)); + + if (p_userdata_mgr->read_index <= p_userdata_mgr->write_index) + puserdata_para->meta_info.records_in_que = + p_userdata_mgr->write_index - + p_userdata_mgr->read_index; + else + puserdata_para->meta_info.records_in_que = + p_userdata_mgr->write_index + + USERDATA_FIFO_NUM - + p_userdata_mgr->read_index; + puserdata_para->version = (0<<24|0<<16|0<<8|1); + + mutex_unlock(&userdata_mutex); + + return 1; +} + +static void vmpeg12_reset_userdata_fifo(struct vdec_s *vdec, int bInit) +{ + mutex_lock(&userdata_mutex); + + if (p_userdata_mgr) { + pr_info("vmpeg12_reset_userdata_fifo: bInit: %d, ri: %d, wi: %d\n", + bInit, p_userdata_mgr->read_index, + p_userdata_mgr->write_index); + p_userdata_mgr->read_index = 0; + p_userdata_mgr->write_index = 0; + + if (bInit) + p_userdata_mgr->last_wp = 0; + } + + mutex_unlock(&userdata_mutex); +} + +static int vmpeg12_vdec_info_init(void) +{ + gvs = kzalloc(sizeof(struct vdec_info), GFP_KERNEL); + if (NULL == gvs) { + pr_info("the struct of vdec status malloc failed.\n"); + return -ENOMEM; + } + return 0; +} + +/****************************************/ +static int vmpeg12_canvas_init(void) +{ + int i, ret; + u32 canvas_width, canvas_height; + u32 decbuf_size, decbuf_y_size, decbuf_uv_size; + static unsigned long buf_start; + + if (buf_size <= 0x00400000) { + /* SD only */ + canvas_width = 768; + canvas_height = 576; + decbuf_y_size = 0x80000; + decbuf_uv_size = 0x20000; + decbuf_size = 0x100000; + } else { + /* HD & SD */ + canvas_width = 1920; + canvas_height = 1088; + decbuf_y_size = 0x200000; + decbuf_uv_size = 0x80000; + decbuf_size = 0x300000; + } + + + for (i = 0; i < MAX_BMMU_BUFFER_NUM; i++) { + + if (i == (MAX_BMMU_BUFFER_NUM - 1)) /* workspace mem */ + decbuf_size = WORKSPACE_SIZE; + + ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, i, + decbuf_size, DRIVER_NAME, &buf_start); + if (ret < 0) + return ret; + + if (i == (MAX_BMMU_BUFFER_NUM - 1)) { + + WRITE_VREG(MREG_CO_MV_START, (buf_start + CCBUF_SIZE)); + if (!ccbuf_phyAddress) { + ccbuf_phyAddress + = (u32)buf_start; + + ccbuf_phyAddress_virt + = codec_mm_phys_to_virt(ccbuf_phyAddress); + if (!ccbuf_phyAddress_virt) { + ccbuf_phyAddress_virt + = ioremap_nocache( + ccbuf_phyAddress, + CCBUF_SIZE); + ccbuf_phyAddress_is_remaped_nocache = 1; + } + } + + } else { +#ifdef NV21 + canvas_config(2 * i + 0, + buf_start, + canvas_width, canvas_height, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); + canvas_config(2 * i + 1, + buf_start + + decbuf_y_size, canvas_width, + canvas_height / 2, CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_32X32); +#else + canvas_config(3 * i + 0, + buf_start, + canvas_width, canvas_height, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); + canvas_config(3 * i + 1, + buf_start + + decbuf_y_size, canvas_width / 2, + canvas_height / 2, CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_32X32); + canvas_config(3 * i + 2, + buf_start + + decbuf_y_size + decbuf_uv_size, + canvas_width / 2, canvas_height / 2, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); +#endif + } + } + + return 0; +} + +static int vmpeg12_prot_init(void) +{ + int ret; + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M6) { + int save_reg = READ_VREG(POWER_CTL_VLD); + + WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4)); + WRITE_VREG(DOS_SW_RESET0, 0); + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) { + + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + + WRITE_VREG(DOS_SW_RESET0, (1<<7) | (1<<6) | (1<<4)); + WRITE_VREG(DOS_SW_RESET0, 0); + + WRITE_VREG(DOS_SW_RESET0, (1<<9) | (1<<8)); + WRITE_VREG(DOS_SW_RESET0, 0); + + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + + WRITE_VREG(MDEC_SW_RESET, (1 << 7)); + WRITE_VREG(MDEC_SW_RESET, 0); + } + + WRITE_VREG(POWER_CTL_VLD, save_reg); + + } else + WRITE_RESET_REG(RESET0_REGISTER, RESET_IQIDCT | RESET_MC); + + ret = vmpeg12_canvas_init(); + +#ifdef NV21 + WRITE_VREG(AV_SCRATCH_0, 0x010100); + WRITE_VREG(AV_SCRATCH_1, 0x030302); + WRITE_VREG(AV_SCRATCH_2, 0x050504); + WRITE_VREG(AV_SCRATCH_3, 0x070706); + WRITE_VREG(AV_SCRATCH_4, 0x090908); + WRITE_VREG(AV_SCRATCH_5, 0x0b0b0a); + WRITE_VREG(AV_SCRATCH_6, 0x0d0d0c); + WRITE_VREG(AV_SCRATCH_7, 0x0f0f0e); +#else + WRITE_VREG(AV_SCRATCH_0, 0x020100); + WRITE_VREG(AV_SCRATCH_1, 0x050403); + WRITE_VREG(AV_SCRATCH_2, 0x080706); + WRITE_VREG(AV_SCRATCH_3, 0x0b0a09); + WRITE_VREG(AV_SCRATCH_4, 0x0e0d0c); + WRITE_VREG(AV_SCRATCH_5, 0x11100f); + WRITE_VREG(AV_SCRATCH_6, 0x141312); + WRITE_VREG(AV_SCRATCH_7, 0x171615); +#endif + + /* set to mpeg1 default */ + WRITE_VREG(MPEG1_2_REG, 0); + /* disable PSCALE for hardware sharing */ + WRITE_VREG(PSCALE_CTRL, 0); + /* for Mpeg1 default value */ + WRITE_VREG(PIC_HEAD_INFO, 0x380); + /* disable mpeg4 */ + WRITE_VREG(M4_CONTROL_REG, 0); + /* clear mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + /* clear buffer IN/OUT registers */ + WRITE_VREG(MREG_BUFFERIN, 0); + WRITE_VREG(MREG_BUFFEROUT, 0); + /* set reference width and height */ + if ((frame_width != 0) && (frame_height != 0)) + WRITE_VREG(MREG_CMD, (frame_width << 16) | frame_height); + else + WRITE_VREG(MREG_CMD, 0); + WRITE_VREG(MREG_FORCE_I_RDY, (force_first_i_ready & 0x01)); + /* clear error count */ + WRITE_VREG(MREG_ERROR_COUNT, 0); + WRITE_VREG(MREG_FATAL_ERROR, 0); + /* clear wait buffer status */ + WRITE_VREG(MREG_WAIT_BUFFER, 0); +#ifdef NV21 + SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17); +#endif + return ret; +} + +static void vmpeg12_local_init(void) +{ + int i; + + INIT_KFIFO(display_q); + INIT_KFIFO(recycle_q); + INIT_KFIFO(newframe_q); + + cur_pool_idx ^= 1; + + for (i = 0; i < VF_POOL_SIZE; i++) { + const struct vframe_s *vf; + + if (cur_pool_idx == 0) { + vf = &vfpool[i]; + vfpool[i].index = DECODE_BUFFER_NUM_MAX; + } else { + vf = &vfpool2[i]; + vfpool2[i].index = DECODE_BUFFER_NUM_MAX; + } + kfifo_put(&newframe_q, (const struct vframe_s *)vf); + } + + for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) + vfbuf_use[i] = 0; + + if (mm_blk_handle) { + decoder_bmmu_box_free(mm_blk_handle); + mm_blk_handle = NULL; + } + + mm_blk_handle = decoder_bmmu_box_alloc_box( + DRIVER_NAME, + 0, + MAX_BMMU_BUFFER_NUM, + 4 + PAGE_SHIFT, + CODEC_MM_FLAGS_CMA_CLEAR | + CODEC_MM_FLAGS_FOR_VDECODER); + + + frame_width = frame_height = frame_dur = frame_prog = 0; + frame_force_skip_flag = 0; + wait_buffer_counter = 0; + first_i_frame_ready = force_first_i_ready; + saved_resolution = 0; + dec_control &= DEC_CONTROL_INTERNAL_MASK; +} + +static s32 vmpeg12_init(void) +{ + int ret = -1, size = -1; + char *buf = vmalloc(0x1000 * 16); + + if (IS_ERR_OR_NULL(buf)) + return -ENOMEM; + + init_timer(&recycle_timer); + + stat |= STAT_TIMER_INIT; + + vmpeg12_local_init(); + + amvdec_enable(); + + size = get_firmware_data(VIDEO_DEC_MPEG12, buf); + if (size < 0) { + pr_err("get firmware fail."); + vfree(buf); + return -1; + } + + if (size == 1) + pr_info ("tee load ok"); + else if (amvdec_loadmc_ex(VFORMAT_MPEG12, NULL, buf) < 0) { + amvdec_disable(); + vfree(buf); + return -EBUSY; + } + + vfree(buf); + + stat |= STAT_MC_LOAD; + + /* enable AMRISC side protocol */ + vmpeg12_prot_init(); + + ret = vdec_request_irq(VDEC_IRQ_1, vmpeg12_isr, + "vmpeg12-irq", (void *)vmpeg12_dec_id); + + if (ret) { + amvdec_disable(); + amlog_level(LOG_LEVEL_ERROR, "vmpeg12 irq register error.\n"); + return -ENOENT; + } + + stat |= STAT_ISR_REG; +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_provider_init(&vmpeg_vf_prov, PROVIDER_NAME, &vmpeg_vf_provider, + NULL); + vf_reg_provider(&vmpeg_vf_prov); + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL); +#else + vf_provider_init(&vmpeg_vf_prov, PROVIDER_NAME, &vmpeg_vf_provider, + NULL); + vf_reg_provider(&vmpeg_vf_prov); +#endif + if (vmpeg12_amstream_dec_info.rate != 0) { + if (!is_reset) + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_FR_HINT, + (void *) + ((unsigned long) + vmpeg12_amstream_dec_info.rate)); + fr_hint_status = VDEC_HINTED; + } else + fr_hint_status = VDEC_NEED_HINT; + + stat |= STAT_VF_HOOK; + + recycle_timer.data = (ulong)&recycle_timer; + recycle_timer.function = vmpeg_put_timer_func; + recycle_timer.expires = jiffies + PUT_INTERVAL; + + add_timer(&recycle_timer); + + stat |= STAT_TIMER_ARM; + + amvdec_start(); + + stat |= STAT_VDEC_RUN; + + return 0; +} + +#ifdef DUMP_USER_DATA +static int amvdec_mpeg12_init_userdata_dump(void) +{ + user_data_buf = kmalloc(MAX_USER_DATA_SIZE, GFP_KERNEL); + if (user_data_buf) + return 1; + else + return 0; +} +#endif + +static int amvdec_mpeg12_probe(struct platform_device *pdev) +{ + struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; + + amlog_level(LOG_LEVEL_INFO, "amvdec_mpeg12 probe start.\n"); + + if (pdata == NULL) { + amlog_level(LOG_LEVEL_ERROR, + "amvdec_mpeg12 platform data undefined.\n"); + return -EFAULT; + } + + if (pdata->sys_info) + vmpeg12_amstream_dec_info = *pdata->sys_info; + + pdata->dec_status = vmpeg12_dec_status; + pdata->set_isreset = vmpeg12_set_isreset; + + pdata->user_data_read = vmpeg12_user_data_read; + pdata->reset_userdata_fifo = vmpeg12_reset_userdata_fifo; + + is_reset = 0; + + vmpeg12_vdec_info_init(); + + INIT_WORK(&set_clk_work, vmpeg12_set_clk); + if (vmpeg12_init() < 0) { + amlog_level(LOG_LEVEL_ERROR, "amvdec_mpeg12 init failed.\n"); + kfree(gvs); + gvs = NULL; + + return -ENODEV; + } + vdec = pdata; +#ifdef DUMP_USER_DATA + amvdec_mpeg12_init_userdata_dump(); +#endif + vmpeg12_crate_userdata_manager(ccbuf_phyAddress_virt, CCBUF_SIZE); + + INIT_WORK(&userdata_push_work, userdata_push_do_work); + INIT_WORK(¬ify_work, vmpeg12_notify_work); + INIT_WORK(&reset_work, reset_do_work); + + + last_offset = 0xFFFFFFFF; +#ifdef DUMP_USER_DATA + last_wp = 0; + reset_user_data_buf(); +#endif + + amlog_level(LOG_LEVEL_INFO, "amvdec_mpeg12 probe end.\n"); + + return 0; +} + +static int amvdec_mpeg12_remove(struct platform_device *pdev) +{ + cancel_work_sync(&userdata_push_work); + cancel_work_sync(¬ify_work); + cancel_work_sync(&reset_work); + cancel_work_sync(&set_clk_work); + + if (stat & STAT_VDEC_RUN) { + amvdec_stop(); + stat &= ~STAT_VDEC_RUN; + } + + if (stat & STAT_ISR_REG) { + vdec_free_irq(VDEC_IRQ_1, (void *)vmpeg12_dec_id); + stat &= ~STAT_ISR_REG; + } + + if (stat & STAT_TIMER_ARM) { + del_timer_sync(&recycle_timer); + stat &= ~STAT_TIMER_ARM; + } + + if (stat & STAT_VF_HOOK) { + if (fr_hint_status == VDEC_HINTED && !is_reset) + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_FR_END_HINT, NULL); + fr_hint_status = VDEC_NO_NEED_HINT; + + vf_unreg_provider(&vmpeg_vf_prov); + stat &= ~STAT_VF_HOOK; + } + + amvdec_disable(); + if (ccbuf_phyAddress_is_remaped_nocache) + iounmap(ccbuf_phyAddress_virt); + + ccbuf_phyAddress_virt = NULL; + ccbuf_phyAddress = 0; + ccbuf_phyAddress_is_remaped_nocache = 0; + vmpeg12_destroy_userdata_manager(); + + if (mm_blk_handle) { + decoder_bmmu_box_free(mm_blk_handle); + mm_blk_handle = NULL; + } + amlog_level(LOG_LEVEL_INFO, "amvdec_mpeg12 remove.\n"); + + kfree(gvs); + gvs = NULL; + vdec = NULL; + +#ifdef DUMP_USER_DATA + if (user_data_buf) { + show_user_data_buf(); + kfree(user_data_buf); + user_data_buf = NULL; + } +#endif + + return 0; +} + +/****************************************/ + +static struct platform_driver amvdec_mpeg12_driver = { + .probe = amvdec_mpeg12_probe, + .remove = amvdec_mpeg12_remove, +#ifdef CONFIG_PM + .suspend = amvdec_suspend, + .resume = amvdec_resume, +#endif + .driver = { + .name = DRIVER_NAME, + } +}; + +static struct codec_profile_t amvdec_mpeg12_profile = { + .name = "mpeg12", + .profile = "" +}; + + +static struct mconfig mpeg12_configs[] = { + MC_PU32("stat", &stat), + MC_PU32("dec_control", &dec_control), + MC_PU32("error_frame_skip_level", &error_frame_skip_level), +}; +static struct mconfig_node mpeg12_node; + + +static int __init amvdec_mpeg12_driver_init_module(void) +{ + amlog_level(LOG_LEVEL_INFO, "amvdec_mpeg12 module init\n"); + + if (platform_driver_register(&amvdec_mpeg12_driver)) { + amlog_level(LOG_LEVEL_ERROR, + "failed to register amvdec_mpeg12 driver\n"); + return -ENODEV; + } + vcodec_profile_register(&amvdec_mpeg12_profile); + INIT_REG_NODE_CONFIGS("media.decoder", &mpeg12_node, + "mpeg12", mpeg12_configs, CONFIG_FOR_RW); + return 0; +} + +static void __exit amvdec_mpeg12_driver_remove_module(void) +{ + amlog_level(LOG_LEVEL_INFO, "amvdec_mpeg12 module remove.\n"); + + platform_driver_unregister(&amvdec_mpeg12_driver); +} + +/****************************************/ +module_param(dec_control, uint, 0664); +MODULE_PARM_DESC(dec_control, "\n amvmpeg12 decoder control\n"); +module_param(error_frame_skip_level, uint, 0664); +MODULE_PARM_DESC(error_frame_skip_level, + "\n amvdec_mpeg12 error_frame_skip_level\n"); +module_param(force_first_i_ready, uint, 0664); +MODULE_PARM_DESC(force_first_i_ready, "\n amvmpeg12 force_first_i_ready\n"); + +module_init(amvdec_mpeg12_driver_init_module); +module_exit(amvdec_mpeg12_driver_remove_module); + +MODULE_DESCRIPTION("AMLOGIC MPEG1/2 Video Decoder Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Tim Yao "); diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/mpeg12/vmpeg12.h b/drivers/amlogic/media_modules/frame_provider/decoder/mpeg12/vmpeg12.h new file mode 100644 index 000000000000..e26a41437e0f --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/mpeg12/vmpeg12.h @@ -0,0 +1,26 @@ +/* + * drivers/amlogic/amports/vmpeg12.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef VMPEG12_H +#define VMPEG12_H + +/* /#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ +/* TODO: move to register headers */ +#define VPP_VD1_POSTBLEND (1 << 10) +/* /#endif */ + +#endif /* VMPEG12_H */ diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/mpeg4/Makefile b/drivers/amlogic/media_modules/frame_provider/decoder/mpeg4/Makefile new file mode 100644 index 000000000000..917cc85e6c7a --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/mpeg4/Makefile @@ -0,0 +1,5 @@ +obj-$(CONFIG_AMLOGIC_MEDIA_VDEC_MPEG4) += amvdec_mpeg4.o +amvdec_mpeg4-objs += vmpeg4.o + +obj-$(CONFIG_AMLOGIC_MEDIA_VDEC_MPEG4_MULTI) += amvdec_mmpeg4.o +amvdec_mmpeg4-objs += vmpeg4_multi.o diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/mpeg4/vmpeg4.c b/drivers/amlogic/media_modules/frame_provider/decoder/mpeg4/vmpeg4.c new file mode 100644 index 000000000000..f6a5910316b4 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/mpeg4/vmpeg4.c @@ -0,0 +1,1257 @@ +/* + * drivers/amlogic/amports/vmpeg4.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include "vmpeg4.h" +#include +#include "../../../stream_input/amports/amports_priv.h" +#include "../utils/decoder_mmu_box.h" +#include "../utils/decoder_bmmu_box.h" +#include +#include + +/* #define CONFIG_AM_VDEC_MPEG4_LOG */ +#ifdef CONFIG_AM_VDEC_MPEG4_LOG +#define AMLOG +#define LOG_LEVEL_VAR amlog_level_vmpeg4 +#define LOG_MASK_VAR amlog_mask_vmpeg4 +#define LOG_LEVEL_ERROR 0 +#define LOG_LEVEL_INFO 1 +#define LOG_LEVEL_DESC "0:ERROR, 1:INFO" +#define LOG_MASK_PTS 0x01 +#define LOG_MASK_DESC "0x01:DEBUG_PTS" +#endif + +#include + +MODULE_AMLOG(LOG_LEVEL_ERROR, 0, LOG_LEVEL_DESC, LOG_DEFAULT_MASK_DESC); + +#include "../utils/amvdec.h" +#include "../utils/vdec.h" +#include "../utils/firmware.h" + +#define DRIVER_NAME "amvdec_mpeg4" +#define MODULE_NAME "amvdec_mpeg4" + +#define DEBUG_PTS + +/* /#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ +#define NV21 +/* /#endif */ + +#define I_PICTURE 0 +#define P_PICTURE 1 +#define B_PICTURE 2 + +#define ORI_BUFFER_START_ADDR 0x01000000 + +#define INTERLACE_FLAG 0x80 +#define TOP_FIELD_FIRST_FLAG 0x40 + +/* protocol registers */ +#define MP4_PIC_RATIO AV_SCRATCH_5 +#define MP4_RATE AV_SCRATCH_3 +#define MP4_ERR_COUNT AV_SCRATCH_6 +#define MP4_PIC_WH AV_SCRATCH_7 +#define MREG_BUFFERIN AV_SCRATCH_8 +#define MREG_BUFFEROUT AV_SCRATCH_9 +#define MP4_NOT_CODED_CNT AV_SCRATCH_A +#define MP4_VOP_TIME_INC AV_SCRATCH_B +#define MP4_OFFSET_REG AV_SCRATCH_C +#define MP4_SYS_RATE AV_SCRATCH_E +#define MEM_OFFSET_REG AV_SCRATCH_F + +#define PARC_FORBIDDEN 0 +#define PARC_SQUARE 1 +#define PARC_CIF 2 +#define PARC_10_11 3 +#define PARC_16_11 4 +#define PARC_40_33 5 +#define PARC_RESERVED 6 +/* values between 6 and 14 are reserved */ +#define PARC_EXTENDED 15 + +#define VF_POOL_SIZE 32 +#define DECODE_BUFFER_NUM_MAX 8 +#define PUT_INTERVAL (HZ/100) +#define WORKSPACE_SIZE (1 * SZ_1M) +#define MAX_BMMU_BUFFER_NUM (DECODE_BUFFER_NUM_MAX + 1) +#define DCAC_BUFF_START_IP 0x02b00000 + + +#define RATE_DETECT_COUNT 5 +#define DURATION_UNIT 96000 +#define PTS_UNIT 90000 + +#define DUR2PTS(x) ((x) - ((x) >> 4)) + +static struct vframe_s *vmpeg_vf_peek(void *); +static struct vframe_s *vmpeg_vf_get(void *); +static void vmpeg_vf_put(struct vframe_s *, void *); +static int vmpeg_vf_states(struct vframe_states *states, void *); +static int vmpeg_event_cb(int type, void *data, void *private_data); + +static int vmpeg4_prot_init(void); +static void vmpeg4_local_init(void); + +static const char vmpeg4_dec_id[] = "vmpeg4-dev"; + +#define PROVIDER_NAME "decoder.mpeg4" + +/* + *int query_video_status(int type, int *value); + */ +static const struct vframe_operations_s vmpeg_vf_provider = { + .peek = vmpeg_vf_peek, + .get = vmpeg_vf_get, + .put = vmpeg_vf_put, + .event_cb = vmpeg_event_cb, + .vf_states = vmpeg_vf_states, +}; +static void *mm_blk_handle; +static struct vframe_provider_s vmpeg_vf_prov; + +static DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE); +static DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE); +static DECLARE_KFIFO(recycle_q, struct vframe_s *, VF_POOL_SIZE); + +static struct vframe_s vfpool[VF_POOL_SIZE]; +static s32 vfbuf_use[DECODE_BUFFER_NUM_MAX]; +static u32 frame_width, frame_height, frame_dur, frame_prog; +static u32 saved_resolution; +static struct timer_list recycle_timer; +static u32 stat; +static u32 buf_size = 32 * 1024 * 1024; +static u32 buf_offset; +static u32 vmpeg4_ratio; +static u64 vmpeg4_ratio64; +static u32 rate_detect; +static u32 vmpeg4_rotation; +static u32 fr_hint_status; + +static u32 total_frame; +static u32 last_vop_time_inc, last_duration; +static u32 last_anch_pts, vop_time_inc_since_last_anch, + frame_num_since_last_anch; +static u64 last_anch_pts_us64; +static struct vdec_info *gvs; + +#ifdef CONFIG_AM_VDEC_MPEG4_LOG +u32 pts_hit, pts_missed, pts_i_hit, pts_i_missed; +#endif + +static struct work_struct reset_work; +static struct work_struct notify_work; +static struct work_struct set_clk_work; +static bool is_reset; + +static DEFINE_SPINLOCK(lock); + +static struct dec_sysinfo vmpeg4_amstream_dec_info; + +static unsigned char aspect_ratio_table[16] = { + PARC_FORBIDDEN, + PARC_SQUARE, + PARC_CIF, + PARC_10_11, + PARC_16_11, + PARC_40_33, + PARC_RESERVED, PARC_RESERVED, PARC_RESERVED, PARC_RESERVED, + PARC_RESERVED, PARC_RESERVED, PARC_RESERVED, PARC_RESERVED, + PARC_RESERVED, PARC_EXTENDED +}; + +static inline u32 index2canvas(u32 index) +{ + const u32 canvas_tab[8] = { +#ifdef NV21 + 0x010100, 0x030302, 0x050504, 0x070706, + 0x090908, 0x0b0b0a, 0x0d0d0c, 0x0f0f0e +#else + 0x020100, 0x050403, 0x080706, 0x0b0a09, + 0x0e0d0c, 0x11100f, 0x141312, 0x171615 +#endif + }; + + return canvas_tab[index]; +} + +static void set_aspect_ratio(struct vframe_s *vf, unsigned int pixel_ratio) +{ + int ar = 0; + unsigned int num = 0; + unsigned int den = 0; + + if (vmpeg4_ratio64 != 0) { + num = vmpeg4_ratio64 >> 32; + den = vmpeg4_ratio64 & 0xffffffff; + } else { + num = vmpeg4_ratio >> 16; + den = vmpeg4_ratio & 0xffff; + + } + if ((num == 0) || (den == 0)) { + num = 1; + den = 1; + } + + if (vmpeg4_ratio == 0) { + vf->ratio_control |= (0x90 << DISP_RATIO_ASPECT_RATIO_BIT); + /* always stretch to 16:9 */ + } else if (pixel_ratio > 0x0f) { + num = (pixel_ratio >> 8) * + vmpeg4_amstream_dec_info.width * num; + ar = div_u64((pixel_ratio & 0xff) * + vmpeg4_amstream_dec_info.height * den * 0x100ULL + + (num >> 1), num); + } else { + switch (aspect_ratio_table[pixel_ratio]) { + case 0: + num = vmpeg4_amstream_dec_info.width * num; + ar = (vmpeg4_amstream_dec_info.height * den * 0x100 + + (num >> 1)) / num; + break; + case 1: + num = vf->width * num; + ar = (vf->height * den * 0x100 + (num >> 1)) / num; + break; + case 2: + num = (vf->width * 12) * num; + ar = (vf->height * den * 0x100 * 11 + + ((num) >> 1)) / num; + break; + case 3: + num = (vf->width * 10) * num; + ar = (vf->height * den * 0x100 * 11 + (num >> 1)) / + num; + break; + case 4: + num = (vf->width * 16) * num; + ar = (vf->height * den * 0x100 * 11 + (num >> 1)) / + num; + break; + case 5: + num = (vf->width * 40) * num; + ar = (vf->height * den * 0x100 * 33 + (num >> 1)) / + num; + break; + default: + num = vf->width * num; + ar = (vf->height * den * 0x100 + (num >> 1)) / num; + break; + } + } + + ar = min(ar, DISP_RATIO_ASPECT_RATIO_MAX); + + vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT); +} + +static irqreturn_t vmpeg4_isr(int irq, void *dev_id) +{ + u32 reg; + struct vframe_s *vf = NULL; + u32 picture_type; + u32 buffer_index; + u32 pts, pts_valid = 0, offset = 0; + u64 pts_us64 = 0; + u32 rate, vop_time_inc, repeat_cnt, duration = 3200; + + reg = READ_VREG(MREG_BUFFEROUT); + + if (reg) { + buffer_index = reg & 0x7; + picture_type = (reg >> 3) & 7; + rate = READ_VREG(MP4_RATE); + repeat_cnt = READ_VREG(MP4_NOT_CODED_CNT); + vop_time_inc = READ_VREG(MP4_VOP_TIME_INC); + + if (buffer_index >= DECODE_BUFFER_NUM_MAX) { + pr_err("fatal error, invalid buffer index."); + return IRQ_HANDLED; + } + + if (vmpeg4_amstream_dec_info.width == 0) { + vmpeg4_amstream_dec_info.width = + READ_VREG(MP4_PIC_WH) >> 16; + } +#if 0 + else { + pr_info("info width = %d, ucode width = %d\n", + vmpeg4_amstream_dec_info.width, + READ_VREG(MP4_PIC_WH) >> 16); + } +#endif + + if (vmpeg4_amstream_dec_info.height == 0) { + vmpeg4_amstream_dec_info.height = + READ_VREG(MP4_PIC_WH) & 0xffff; + } +#if 0 + else { + pr_info("info height = %d, ucode height = %d\n", + vmpeg4_amstream_dec_info.height, + READ_VREG(MP4_PIC_WH) & 0xffff); + } +#endif + if (vmpeg4_amstream_dec_info.rate == 0 + || vmpeg4_amstream_dec_info.rate > 96000) { + /* if ((rate >> 16) != 0) { */ + if ((rate & 0xffff) != 0 && (rate >> 16) != 0) { + vmpeg4_amstream_dec_info.rate = + (rate >> 16) * DURATION_UNIT / + (rate & 0xffff); + duration = vmpeg4_amstream_dec_info.rate; + if (fr_hint_status == VDEC_NEED_HINT) { + schedule_work(¬ify_work); + fr_hint_status = VDEC_HINTED; + } + } else if (rate_detect < RATE_DETECT_COUNT) { + if (vop_time_inc < last_vop_time_inc) { + duration = + vop_time_inc + rate - + last_vop_time_inc; + } else { + duration = + vop_time_inc - last_vop_time_inc; + } + + if (duration == last_duration) { + rate_detect++; + if (rate_detect >= RATE_DETECT_COUNT) { + vmpeg4_amstream_dec_info.rate = + duration * DURATION_UNIT / + rate; + duration = + vmpeg4_amstream_dec_info.rate; + } + } else + rate_detect = 0; + + last_duration = duration; + } + } else { + duration = vmpeg4_amstream_dec_info.rate; +#if 0 + pr_info("info rate = %d, ucode rate = 0x%x:0x%x\n", + vmpeg4_amstream_dec_info.rate, + READ_VREG(MP4_RATE), vop_time_inc); +#endif + } + + if ((picture_type == I_PICTURE) || + (picture_type == P_PICTURE)) { + offset = READ_VREG(MP4_OFFSET_REG); + /*2500-->3000,because some mpeg4 + *video may checkout failed; + *may have av sync problem.can changed small later. + *263 may need small? + */ + if (pts_lookup_offset_us64 + (PTS_TYPE_VIDEO, offset, &pts, 3000, + &pts_us64) == 0) { + pts_valid = 1; + last_anch_pts = pts; + last_anch_pts_us64 = pts_us64; +#ifdef CONFIG_AM_VDEC_MPEG4_LOG + pts_hit++; +#endif + } else { +#ifdef CONFIG_AM_VDEC_MPEG4_LOG + pts_missed++; +#endif + } +#ifdef CONFIG_AM_VDEC_MPEG4_LOG + amlog_mask(LOG_MASK_PTS, + "I offset 0x%x, pts_valid %d pts=0x%x\n", + offset, pts_valid, pts); +#endif + } + + if (pts_valid) { + last_anch_pts = pts; + last_anch_pts_us64 = pts_us64; + frame_num_since_last_anch = 0; + vop_time_inc_since_last_anch = 0; + } else { + pts = last_anch_pts; + pts_us64 = last_anch_pts_us64; + + if ((rate != 0) && ((rate >> 16) == 0) + && vmpeg4_amstream_dec_info.rate == 0) { + /* variable PTS rate */ + /*bug on variable pts calc, + *do as dixed vop first if we + *have rate setting before. + */ + if (vop_time_inc > last_vop_time_inc) { + vop_time_inc_since_last_anch += + vop_time_inc - last_vop_time_inc; + } else { + vop_time_inc_since_last_anch += + vop_time_inc + rate - + last_vop_time_inc; + } + + pts += vop_time_inc_since_last_anch * + PTS_UNIT / rate; + pts_us64 += (vop_time_inc_since_last_anch * + PTS_UNIT / rate) * 100 / 9; + + if (vop_time_inc_since_last_anch > (1 << 14)) { + /* avoid overflow */ + last_anch_pts = pts; + last_anch_pts_us64 = pts_us64; + vop_time_inc_since_last_anch = 0; + } + } else { + /* fixed VOP rate */ + frame_num_since_last_anch++; + pts += DUR2PTS(frame_num_since_last_anch * + vmpeg4_amstream_dec_info.rate); + pts_us64 += DUR2PTS(frame_num_since_last_anch * + vmpeg4_amstream_dec_info.rate) * + 100 / 9; + + if (frame_num_since_last_anch > (1 << 15)) { + /* avoid overflow */ + last_anch_pts = pts; + last_anch_pts_us64 = pts_us64; + frame_num_since_last_anch = 0; + } + } + } + + if (reg & INTERLACE_FLAG) { /* interlace */ + if (kfifo_get(&newframe_q, &vf) == 0) { + printk + ("fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + vf->signal_type = 0; + vf->index = buffer_index; + vf->width = vmpeg4_amstream_dec_info.width; + vf->height = vmpeg4_amstream_dec_info.height; + vf->bufWidth = 1920; + vf->flag = 0; + vf->orientation = vmpeg4_rotation; + vf->pts = pts; + vf->pts_us64 = pts_us64; + vf->duration = duration >> 1; + vf->duration_pulldown = 0; + vf->type = (reg & TOP_FIELD_FIRST_FLAG) ? + VIDTYPE_INTERLACE_TOP : + VIDTYPE_INTERLACE_BOTTOM; +#ifdef NV21 + vf->type |= VIDTYPE_VIU_NV21; +#endif + vf->canvas0Addr = vf->canvas1Addr = + index2canvas(buffer_index); + vf->type_original = vf->type; + + set_aspect_ratio(vf, READ_VREG(MP4_PIC_RATIO)); + + vfbuf_use[buffer_index]++; + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + buffer_index); + + kfifo_put(&display_q, (const struct vframe_s *)vf); + + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + + if (kfifo_get(&newframe_q, &vf) == 0) { + printk( + "fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + vf->signal_type = 0; + vf->index = buffer_index; + vf->width = vmpeg4_amstream_dec_info.width; + vf->height = vmpeg4_amstream_dec_info.height; + vf->bufWidth = 1920; + vf->flag = 0; + vf->orientation = vmpeg4_rotation; + + vf->pts = 0; + vf->pts_us64 = 0; + vf->duration = duration >> 1; + + vf->duration_pulldown = 0; + vf->type = (reg & TOP_FIELD_FIRST_FLAG) ? + VIDTYPE_INTERLACE_BOTTOM : VIDTYPE_INTERLACE_TOP; +#ifdef NV21 + vf->type |= VIDTYPE_VIU_NV21; +#endif + vf->canvas0Addr = vf->canvas1Addr = + index2canvas(buffer_index); + vf->type_original = vf->type; + + set_aspect_ratio(vf, READ_VREG(MP4_PIC_RATIO)); + + vfbuf_use[buffer_index]++; + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + buffer_index); + + amlog_mask(LOG_MASK_PTS, + "[%s:%d] [inte] dur=0x%x rate=%d picture_type=%d\n", + __func__, __LINE__, vf->duration, + vmpeg4_amstream_dec_info.rate, picture_type); + + kfifo_put(&display_q, (const struct vframe_s *)vf); + + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + + } else { /* progressive */ + if (kfifo_get(&newframe_q, &vf) == 0) { + printk + ("fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + vf->signal_type = 0; + vf->index = buffer_index; + vf->width = vmpeg4_amstream_dec_info.width; + vf->height = vmpeg4_amstream_dec_info.height; + vf->bufWidth = 1920; + vf->flag = 0; + vf->orientation = vmpeg4_rotation; + vf->pts = pts; + vf->pts_us64 = pts_us64; + vf->duration = duration; + vf->duration_pulldown = repeat_cnt * duration; +#ifdef NV21 + vf->type = + VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD | + VIDTYPE_VIU_NV21; +#else + vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD; +#endif + vf->canvas0Addr = vf->canvas1Addr = + index2canvas(buffer_index); + vf->type_original = vf->type; + + set_aspect_ratio(vf, READ_VREG(MP4_PIC_RATIO)); + + amlog_mask(LOG_MASK_PTS, + "[%s:%d] [prog] dur=0x%x rate=%d picture_type=%d\n", + __func__, __LINE__, vf->duration, + vmpeg4_amstream_dec_info.rate, picture_type); + + vfbuf_use[buffer_index]++; + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + buffer_index); + + kfifo_put(&display_q, (const struct vframe_s *)vf); + + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + } + + total_frame += repeat_cnt + 1; + + WRITE_VREG(MREG_BUFFEROUT, 0); + + last_vop_time_inc = vop_time_inc; + + /*count info*/ + gvs->frame_dur = duration; + vdec_count_info(gvs, 0, offset); + } + + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + return IRQ_HANDLED; +} + +static struct vframe_s *vmpeg_vf_peek(void *op_arg) +{ + struct vframe_s *vf; + + if (kfifo_peek(&display_q, &vf)) + return vf; + + return NULL; +} + +static struct vframe_s *vmpeg_vf_get(void *op_arg) +{ + struct vframe_s *vf; + + if (kfifo_get(&display_q, &vf)) + return vf; + + return NULL; +} + +static void vmpeg_vf_put(struct vframe_s *vf, void *op_arg) +{ + kfifo_put(&recycle_q, (const struct vframe_s *)vf); +} + +static int vmpeg_event_cb(int type, void *data, void *private_data) +{ + if (type & VFRAME_EVENT_RECEIVER_RESET) { + unsigned long flags; + + amvdec_stop(); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_light_unreg_provider(&vmpeg_vf_prov); +#endif + spin_lock_irqsave(&lock, flags); + vmpeg4_local_init(); + vmpeg4_prot_init(); + spin_unlock_irqrestore(&lock, flags); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_reg_provider(&vmpeg_vf_prov); +#endif + amvdec_start(); + } + return 0; +} + +static int vmpeg_vf_states(struct vframe_states *states, void *op_arg) +{ + unsigned long flags; + + spin_lock_irqsave(&lock, flags); + + states->vf_pool_size = VF_POOL_SIZE; + states->buf_free_num = kfifo_len(&newframe_q); + states->buf_avail_num = kfifo_len(&display_q); + states->buf_recycle_num = kfifo_len(&recycle_q); + + spin_unlock_irqrestore(&lock, flags); + + return 0; +} + +static void vmpeg4_notify_work(struct work_struct *work) +{ + pr_info("frame duration changed %d\n", vmpeg4_amstream_dec_info.rate); + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_FR_HINT, + (void *) + ((unsigned long) + vmpeg4_amstream_dec_info.rate)); + return; +} + +static void reset_do_work(struct work_struct *work) +{ + unsigned long flags; + + amvdec_stop(); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_light_unreg_provider(&vmpeg_vf_prov); +#endif + spin_lock_irqsave(&lock, flags); + vmpeg4_local_init(); + vmpeg4_prot_init(); + spin_unlock_irqrestore(&lock, flags); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_reg_provider(&vmpeg_vf_prov); +#endif + amvdec_start(); +} + +static void vmpeg4_set_clk(struct work_struct *work) +{ + if (frame_dur > 0 && saved_resolution != + frame_width * frame_height * (96000 / frame_dur)) { + int fps = 96000 / frame_dur; + + saved_resolution = frame_width * frame_height * fps; + vdec_source_changed(VFORMAT_MPEG4, + frame_width, frame_height, fps); + } +} + +static void vmpeg_put_timer_func(unsigned long arg) +{ + struct timer_list *timer = (struct timer_list *)arg; + + while (!kfifo_is_empty(&recycle_q) && (READ_VREG(MREG_BUFFERIN) == 0)) { + struct vframe_s *vf; + + if (kfifo_get(&recycle_q, &vf)) { + if ((vf->index >= 0) + && (vf->index < DECODE_BUFFER_NUM_MAX) + && (--vfbuf_use[vf->index] == 0)) { + WRITE_VREG(MREG_BUFFERIN, ~(1 << vf->index)); + vf->index = DECODE_BUFFER_NUM_MAX; + } + kfifo_put(&newframe_q, (const struct vframe_s *)vf); + } + } + + schedule_work(&set_clk_work); + + if (READ_VREG(AV_SCRATCH_L)) { + pr_info("mpeg4 fatal error happened,need reset !!\n"); + schedule_work(&reset_work); + } + + + timer->expires = jiffies + PUT_INTERVAL; + + add_timer(timer); +} + +int vmpeg4_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus) +{ + vstatus->frame_width = vmpeg4_amstream_dec_info.width; + vstatus->frame_height = vmpeg4_amstream_dec_info.height; + if (0 != vmpeg4_amstream_dec_info.rate) + vstatus->frame_rate = + DURATION_UNIT / vmpeg4_amstream_dec_info.rate; + else + vstatus->frame_rate = -1; + vstatus->error_count = READ_VREG(MP4_ERR_COUNT); + vstatus->status = stat; + vstatus->bit_rate = gvs->bit_rate; + vstatus->frame_dur = frame_dur; + vstatus->frame_data = gvs->frame_data; + vstatus->total_data = gvs->total_data; + vstatus->frame_count = gvs->frame_count; + vstatus->error_frame_count = gvs->error_frame_count; + vstatus->drop_frame_count = gvs->drop_frame_count; + vstatus->total_data = gvs->total_data; + vstatus->samp_cnt = gvs->samp_cnt; + vstatus->offset = gvs->offset; + snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name), + "%s", DRIVER_NAME); + + return 0; +} + +int vmpeg4_set_isreset(struct vdec_s *vdec, int isreset) +{ + is_reset = isreset; + return 0; +} + +static int vmpeg4_vdec_info_init(void) +{ + gvs = kzalloc(sizeof(struct vdec_info), GFP_KERNEL); + if (NULL == gvs) { + pr_info("the struct of vdec status malloc failed.\n"); + return -ENOMEM; + } + return 0; +} + +/****************************************/ +static int vmpeg4_canvas_init(void) +{ + int i, ret; + u32 canvas_width, canvas_height; + unsigned long buf_start; + u32 alloc_size, decbuf_size, decbuf_y_size, decbuf_uv_size; + + if (buf_size <= 0x00400000) { + /* SD only */ + canvas_width = 768; + canvas_height = 576; + decbuf_y_size = 0x80000; + decbuf_uv_size = 0x20000; + decbuf_size = 0x100000; + } else { + int w = vmpeg4_amstream_dec_info.width; + int h = vmpeg4_amstream_dec_info.height; + int align_w, align_h; + int max, min; + + align_w = ALIGN(w, 64); + align_h = ALIGN(h, 64); + if (align_w > align_h) { + max = align_w; + min = align_h; + } else { + max = align_h; + min = align_w; + } + /* HD & SD */ + if ((max > 1920 || min > 1088) && + ALIGN(align_w * align_h * 3/2, SZ_64K) * 9 <= + buf_size) { + canvas_width = align_w; + canvas_height = align_h; + decbuf_y_size = ALIGN(align_w * align_h, SZ_64K); + decbuf_uv_size = ALIGN(align_w * align_h/4, SZ_64K); + decbuf_size = ALIGN(align_w * align_h * 3/2, SZ_64K); + } else { /*1080p*/ + if (h > w) { + canvas_width = 1088; + canvas_height = 1920; + } else { + canvas_width = 1920; + canvas_height = 1088; + } + decbuf_y_size = 0x200000; + decbuf_uv_size = 0x80000; + decbuf_size = 0x300000; + } + } + + for (i = 0; i < MAX_BMMU_BUFFER_NUM; i++) { + /* workspace mem */ + if (i == (MAX_BMMU_BUFFER_NUM - 1)) + alloc_size = WORKSPACE_SIZE; + else + alloc_size = decbuf_size; + + ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, i, + alloc_size, DRIVER_NAME, &buf_start); + if (ret < 0) + return ret; + if (i == (MAX_BMMU_BUFFER_NUM - 1)) { + buf_offset = buf_start - DCAC_BUFF_START_IP; + continue; + } + + +#ifdef NV21 + canvas_config(2 * i + 0, + buf_start, + canvas_width, canvas_height, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); + canvas_config(2 * i + 1, + buf_start + + decbuf_y_size, canvas_width, + canvas_height / 2, CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_32X32); +#else + canvas_config(3 * i + 0, + buf_start, + canvas_width, canvas_height, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); + canvas_config(3 * i + 1, + buf_start + + decbuf_y_size, canvas_width / 2, + canvas_height / 2, CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_32X32); + canvas_config(3 * i + 2, + buf_start + + decbuf_y_size + decbuf_uv_size, + canvas_width / 2, canvas_height / 2, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); +#endif + + } + return 0; +} + +static int vmpeg4_prot_init(void) +{ + int r; +#if 1 /* /MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ + WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6)); + WRITE_VREG(DOS_SW_RESET0, 0); +#else + WRITE_RESET_REG(RESET0_REGISTER, RESET_IQIDCT | RESET_MC); +#endif + + r = vmpeg4_canvas_init(); + + /* index v << 16 | u << 8 | y */ +#ifdef NV21 + WRITE_VREG(AV_SCRATCH_0, 0x010100); + WRITE_VREG(AV_SCRATCH_1, 0x030302); + WRITE_VREG(AV_SCRATCH_2, 0x050504); + WRITE_VREG(AV_SCRATCH_3, 0x070706); + WRITE_VREG(AV_SCRATCH_G, 0x090908); + WRITE_VREG(AV_SCRATCH_H, 0x0b0b0a); + WRITE_VREG(AV_SCRATCH_I, 0x0d0d0c); + WRITE_VREG(AV_SCRATCH_J, 0x0f0f0e); +#else + WRITE_VREG(AV_SCRATCH_0, 0x020100); + WRITE_VREG(AV_SCRATCH_1, 0x050403); + WRITE_VREG(AV_SCRATCH_2, 0x080706); + WRITE_VREG(AV_SCRATCH_3, 0x0b0a09); + WRITE_VREG(AV_SCRATCH_G, 0x0e0d0c); + WRITE_VREG(AV_SCRATCH_H, 0x11100f); + WRITE_VREG(AV_SCRATCH_I, 0x141312); + WRITE_VREG(AV_SCRATCH_J, 0x171615); +#endif + WRITE_VREG(AV_SCRATCH_L, 0);/*clearfatal error flag*/ + + /* notify ucode the buffer offset */ + WRITE_VREG(AV_SCRATCH_F, buf_offset); + + /* disable PSCALE for hardware sharing */ + WRITE_VREG(PSCALE_CTRL, 0); + + /* clear repeat count */ + WRITE_VREG(MP4_NOT_CODED_CNT, 0); + + WRITE_VREG(MREG_BUFFERIN, 0); + WRITE_VREG(MREG_BUFFEROUT, 0); + + /* clear mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + /* enable mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_MASK, 1); + + + +#ifdef NV21 + SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17); +#endif + +#if 1/* /MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ + pr_debug("mpeg4 meson8 prot init\n"); + WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa); +#endif + + WRITE_VREG(MP4_PIC_WH, (vmpeg4_amstream_dec_info. + width << 16) | vmpeg4_amstream_dec_info.height); + WRITE_VREG(MP4_SYS_RATE, vmpeg4_amstream_dec_info.rate); + return r; +} + +static void vmpeg4_local_init(void) +{ + int i; + + vmpeg4_ratio = vmpeg4_amstream_dec_info.ratio; + + vmpeg4_ratio64 = vmpeg4_amstream_dec_info.ratio64; + + vmpeg4_rotation = + (((unsigned long) vmpeg4_amstream_dec_info.param) + >> 16) & 0xffff; + + frame_width = frame_height = frame_dur = frame_prog = 0; + + total_frame = 0; + saved_resolution = 0; + last_anch_pts = 0; + + last_anch_pts_us64 = 0; + + last_vop_time_inc = last_duration = 0; + + vop_time_inc_since_last_anch = 0; + + frame_num_since_last_anch = 0; + +#ifdef CONFIG_AM_VDEC_MPEG4_LOG + pts_hit = pts_missed = pts_i_hit = pts_i_missed = 0; +#endif + + for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) + vfbuf_use[i] = 0; + + INIT_KFIFO(display_q); + INIT_KFIFO(recycle_q); + INIT_KFIFO(newframe_q); + + for (i = 0; i < VF_POOL_SIZE; i++) { + const struct vframe_s *vf = &vfpool[i]; + + vfpool[i].index = DECODE_BUFFER_NUM_MAX; + kfifo_put(&newframe_q, (const struct vframe_s *)vf); + } + if (mm_blk_handle) { + decoder_bmmu_box_free(mm_blk_handle); + mm_blk_handle = NULL; + } + + mm_blk_handle = decoder_bmmu_box_alloc_box( + DRIVER_NAME, + 0, + MAX_BMMU_BUFFER_NUM, + 4 + PAGE_SHIFT, + CODEC_MM_FLAGS_CMA_CLEAR | + CODEC_MM_FLAGS_FOR_VDECODER); +} + +static s32 vmpeg4_init(void) +{ + int r; + int trickmode_fffb = 0; + int size = -1; + char *buf = vmalloc(0x1000 * 16); + + if (IS_ERR_OR_NULL(buf)) + return -ENOMEM; + + query_video_status(0, &trickmode_fffb); + + amlog_level(LOG_LEVEL_INFO, "vmpeg4_init\n"); + init_timer(&recycle_timer); + + stat |= STAT_TIMER_INIT; + + amvdec_enable(); + + vmpeg4_local_init(); + + if (vmpeg4_amstream_dec_info.format == VIDEO_DEC_FORMAT_MPEG4_3) { + size = get_firmware_data(VIDEO_DEC_MPEG4_3, buf); + + amlog_level(LOG_LEVEL_INFO, "load VIDEO_DEC_FORMAT_MPEG4_3\n"); + } else if (vmpeg4_amstream_dec_info.format == + VIDEO_DEC_FORMAT_MPEG4_4) { + size = get_firmware_data(VIDEO_DEC_MPEG4_4, buf); + + amlog_level(LOG_LEVEL_INFO, "load VIDEO_DEC_FORMAT_MPEG4_4\n"); + } else if (vmpeg4_amstream_dec_info.format == + VIDEO_DEC_FORMAT_MPEG4_5) { + size = get_firmware_data(VIDEO_DEC_MPEG4_5, buf); + + amlog_level(LOG_LEVEL_INFO, "load VIDEO_DEC_FORMAT_MPEG4_5\n"); + } else if (vmpeg4_amstream_dec_info.format == VIDEO_DEC_FORMAT_H263) { + size = get_firmware_data(VIDEO_DEC_H263, buf); + + amlog_level(LOG_LEVEL_INFO, "load VIDEO_DEC_FORMAT_H263\n"); + } else + amlog_level(LOG_LEVEL_ERROR, "not supported MPEG4 format\n"); + + if (size < 0) { + pr_err("get firmware fail."); + vfree(buf); + return -1; + } + + if (size == 1) + pr_info ("tee load ok"); + else if (amvdec_loadmc_ex(VFORMAT_MPEG4, NULL, buf) < 0) { + amvdec_disable(); + vfree(buf); + return -EBUSY; + } + + vfree(buf); + + stat |= STAT_MC_LOAD; + + /* enable AMRISC side protocol */ + r = vmpeg4_prot_init(); + if (r < 0) + return r; + + if (vdec_request_irq(VDEC_IRQ_1, vmpeg4_isr, + "vmpeg4-irq", (void *)vmpeg4_dec_id)) { + amvdec_disable(); + + amlog_level(LOG_LEVEL_ERROR, "vmpeg4 irq register error.\n"); + return -ENOENT; + } + + stat |= STAT_ISR_REG; + fr_hint_status = VDEC_NO_NEED_HINT; +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_provider_init(&vmpeg_vf_prov, PROVIDER_NAME, &vmpeg_vf_provider, + NULL); + vf_reg_provider(&vmpeg_vf_prov); + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL); +#else + vf_provider_init(&vmpeg_vf_prov, PROVIDER_NAME, &vmpeg_vf_provider, + NULL); + vf_reg_provider(&vmpeg_vf_prov); +#endif + if (vmpeg4_amstream_dec_info.rate != 0) { + if (!is_reset) + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_FR_HINT, + (void *) + ((unsigned long) + vmpeg4_amstream_dec_info.rate)); + fr_hint_status = VDEC_HINTED; + } else + fr_hint_status = VDEC_NEED_HINT; + + stat |= STAT_VF_HOOK; + + recycle_timer.data = (ulong)&recycle_timer; + recycle_timer.function = vmpeg_put_timer_func; + recycle_timer.expires = jiffies + PUT_INTERVAL; + + add_timer(&recycle_timer); + + stat |= STAT_TIMER_ARM; + + amvdec_start(); + + stat |= STAT_VDEC_RUN; + + return 0; +} + +static int amvdec_mpeg4_probe(struct platform_device *pdev) +{ + struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; + + if (pdata == NULL) { + amlog_level(LOG_LEVEL_ERROR, + "amvdec_mpeg4 memory resource undefined.\n"); + return -EFAULT; + } + + if (pdata->sys_info) + vmpeg4_amstream_dec_info = *pdata->sys_info; + + pdata->dec_status = vmpeg4_dec_status; + pdata->set_isreset = vmpeg4_set_isreset; + is_reset = 0; + + INIT_WORK(&reset_work, reset_do_work); + INIT_WORK(¬ify_work, vmpeg4_notify_work); + INIT_WORK(&set_clk_work, vmpeg4_set_clk); + + vmpeg4_vdec_info_init(); + + if (vmpeg4_init() < 0) { + amlog_level(LOG_LEVEL_ERROR, "amvdec_mpeg4 init failed.\n"); + kfree(gvs); + gvs = NULL; + return -ENODEV; + } + + return 0; +} + +static int amvdec_mpeg4_remove(struct platform_device *pdev) +{ + if (stat & STAT_VDEC_RUN) { + amvdec_stop(); + stat &= ~STAT_VDEC_RUN; + } + + if (stat & STAT_ISR_REG) { + vdec_free_irq(VDEC_IRQ_1, (void *)vmpeg4_dec_id); + stat &= ~STAT_ISR_REG; + } + + if (stat & STAT_TIMER_ARM) { + del_timer_sync(&recycle_timer); + stat &= ~STAT_TIMER_ARM; + } + + if (stat & STAT_VF_HOOK) { + if (fr_hint_status == VDEC_HINTED && !is_reset) + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_FR_END_HINT, NULL); + fr_hint_status = VDEC_NO_NEED_HINT; + + vf_unreg_provider(&vmpeg_vf_prov); + stat &= ~STAT_VF_HOOK; + } + + cancel_work_sync(&reset_work); + cancel_work_sync(¬ify_work); + cancel_work_sync(&set_clk_work); + + amvdec_disable(); + + if (mm_blk_handle) { + decoder_bmmu_box_free(mm_blk_handle); + mm_blk_handle = NULL; + } + + amlog_mask(LOG_MASK_PTS, + "pts hit %d, pts missed %d, i hit %d, missed %d\n", pts_hit, + pts_missed, pts_i_hit, pts_i_missed); + amlog_mask(LOG_MASK_PTS, "total frame %d, rate %d\n", total_frame, + vmpeg4_amstream_dec_info.rate); + kfree(gvs); + gvs = NULL; + + return 0; +} + +/****************************************/ + +static struct platform_driver amvdec_mpeg4_driver = { + .probe = amvdec_mpeg4_probe, + .remove = amvdec_mpeg4_remove, +#ifdef CONFIG_PM + .suspend = amvdec_suspend, + .resume = amvdec_resume, +#endif + .driver = { + .name = DRIVER_NAME, + } +}; + +static struct codec_profile_t amvdec_mpeg4_profile = { + .name = "mpeg4", + .profile = "" +}; +static struct mconfig mpeg4_configs[] = { + MC_PU32("stat", &stat), +}; +static struct mconfig_node mpeg4_node; + +static int __init amvdec_mpeg4_driver_init_module(void) +{ + amlog_level(LOG_LEVEL_INFO, "amvdec_mpeg4 module init\n"); + + if (platform_driver_register(&amvdec_mpeg4_driver)) { + amlog_level(LOG_LEVEL_ERROR, + "failed to register amvdec_mpeg4 driver\n"); + return -ENODEV; + } + vcodec_profile_register(&amvdec_mpeg4_profile); + INIT_REG_NODE_CONFIGS("media.decoder", &mpeg4_node, + "mpeg4", mpeg4_configs, CONFIG_FOR_R); + return 0; +} + +static void __exit amvdec_mpeg4_driver_remove_module(void) +{ + amlog_level(LOG_LEVEL_INFO, "amvdec_mpeg4 module remove.\n"); + + platform_driver_unregister(&amvdec_mpeg4_driver); +} + +/****************************************/ +module_init(amvdec_mpeg4_driver_init_module); +module_exit(amvdec_mpeg4_driver_remove_module); + +MODULE_DESCRIPTION("AMLOGIC MPEG4 Video Decoder Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Tim Yao "); diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/mpeg4/vmpeg4.h b/drivers/amlogic/media_modules/frame_provider/decoder/mpeg4/vmpeg4.h new file mode 100644 index 000000000000..7914e6a6ada4 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/mpeg4/vmpeg4.h @@ -0,0 +1,26 @@ +/* + * drivers/amlogic/amports/vmpeg4.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef VMPEG4_H +#define VMPEG4_H + +/* /#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ +/* TODO: move to register headers */ +#define VPP_VD1_POSTBLEND (1 << 10) +/* /#endif */ + +#endif /* VMPEG4_H */ diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/mpeg4/vmpeg4_multi.c b/drivers/amlogic/media_modules/frame_provider/decoder/mpeg4/vmpeg4_multi.c new file mode 100644 index 000000000000..f21d830360b9 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/mpeg4/vmpeg4_multi.c @@ -0,0 +1,1317 @@ +/* + * drivers/amlogic/amports/vmpeg4.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include "vmpeg4.h" +#include +#include "../../../stream_input/amports/amports_priv.h" + +#include "../utils/amvdec.h" +#include "../utils/vdec_input.h" +#include "../utils/vdec.h" +#include "../utils/firmware.h" + +#define DRIVER_NAME "ammvdec_mpeg4" +#define MODULE_NAME "ammvdec_mpeg4" + +#define MEM_NAME "codec_mpeg4" + +#define DEBUG_PTS + +#define NV21 +#define I_PICTURE 0 +#define P_PICTURE 1 +#define B_PICTURE 2 + +#define ORI_BUFFER_START_ADDR 0x01000000 +#define DEFAULT_MEM_SIZE (32*SZ_1M) + +#define INTERLACE_FLAG 0x80 +#define TOP_FIELD_FIRST_FLAG 0x40 + +/* protocol registers */ +#define MREG_REF0 AV_SCRATCH_1 +#define MREG_REF1 AV_SCRATCH_2 +#define MP4_PIC_RATIO AV_SCRATCH_5 +#define MP4_RATE AV_SCRATCH_3 +#define MP4_ERR_COUNT AV_SCRATCH_6 +#define MP4_PIC_WH AV_SCRATCH_7 +#define MREG_INPUT AV_SCRATCH_8 +#define MREG_BUFFEROUT AV_SCRATCH_9 +#define MP4_NOT_CODED_CNT AV_SCRATCH_A +#define MP4_VOP_TIME_INC AV_SCRATCH_B +#define MP4_OFFSET_REG AV_SCRATCH_C +#define MP4_SYS_RATE AV_SCRATCH_E +#define MEM_OFFSET_REG AV_SCRATCH_F + +#define PARC_FORBIDDEN 0 +#define PARC_SQUARE 1 +#define PARC_CIF 2 +#define PARC_10_11 3 +#define PARC_16_11 4 +#define PARC_40_33 5 +#define PARC_RESERVED 6 +/* values between 6 and 14 are reserved */ +#define PARC_EXTENDED 15 + +#define VF_POOL_SIZE 16 +#define DECODE_BUFFER_NUM_MAX 4 +#define PUT_INTERVAL (HZ/100) + +#define CTX_LMEM_SWAP_OFFSET 0 +#define CTX_QUANT_MATRIX_OFFSET 0x800 +/* dcac buffer must align at 4k boundary */ +#define CTX_DCAC_BUF_OFFSET 0x1000 +#define CTX_DECBUF_OFFSET (0x0c0000 + 0x1000) + +#define RATE_DETECT_COUNT 5 +#define DURATION_UNIT 96000 +#define PTS_UNIT 90000 + +#define DUR2PTS(x) ((x) - ((x) >> 4)) + +#define DEC_RESULT_NONE 0 +#define DEC_RESULT_DONE 1 +#define DEC_RESULT_AGAIN 2 +#define DEC_RESULT_ERROR 3 + +static struct vframe_s *vmpeg_vf_peek(void *); +static struct vframe_s *vmpeg_vf_get(void *); +static void vmpeg_vf_put(struct vframe_s *, void *); +static int vmpeg_vf_states(struct vframe_states *states, void *); +static int vmpeg_event_cb(int type, void *data, void *private_data); + +struct vdec_mpeg4_hw_s { + spinlock_t lock; + struct platform_device *platform_dev; + struct device *cma_dev; + + DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE); + DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE); + struct vframe_s vfpool[VF_POOL_SIZE]; + + s32 vfbuf_use[DECODE_BUFFER_NUM_MAX]; + u32 frame_width; + u32 frame_height; + u32 frame_dur; + u32 frame_prog; + + u32 ctx_valid; + u32 reg_vcop_ctrl_reg; + u32 reg_pic_head_info; + u32 reg_mpeg1_2_reg; + u32 reg_slice_qp; + u32 reg_mp4_pic_wh; + u32 reg_mp4_rate; + u32 reg_mb_info; + u32 reg_dc_ac_ctrl; + u32 reg_iqidct_control; + u32 reg_resync_marker_length; + u32 reg_rv_ai_mb_count; + + struct vframe_chunk_s *chunk; + u32 stat; + u32 buf_start; + u32 buf_size; + unsigned long cma_alloc_addr; + int cma_alloc_count; + u32 vmpeg4_ratio; + u64 vmpeg4_ratio64; + u32 rate_detect; + u32 vmpeg4_rotation; + u32 total_frame; + u32 last_vop_time_inc; + u32 last_duration; + u32 last_anch_pts; + u32 vop_time_inc_since_last_anch; + u32 frame_num_since_last_anch; + u64 last_anch_pts_us64; + + u32 pts_hit; + u32 pts_missed; + u32 pts_i_hit; + u32 pts_i_missed; + + u32 buffer_info[DECODE_BUFFER_NUM_MAX]; + u32 pts[DECODE_BUFFER_NUM_MAX]; + u64 pts64[DECODE_BUFFER_NUM_MAX]; + bool pts_valid[DECODE_BUFFER_NUM_MAX]; + u32 canvas_spec[DECODE_BUFFER_NUM_MAX]; +#ifdef NV21 + struct canvas_config_s canvas_config[DECODE_BUFFER_NUM_MAX][2]; +#else + struct canvas_config_s canvas_config[DECODE_BUFFER_NUM_MAX][3]; +#endif + struct dec_sysinfo vmpeg4_amstream_dec_info; + + s32 refs[2]; + int dec_result; + struct work_struct work; + + void (*vdec_cb)(struct vdec_s *, void *); + void *vdec_cb_arg; + struct firmware_s *fw; +}; +static void vmpeg4_local_init(struct vdec_mpeg4_hw_s *hw); +static int vmpeg4_hw_ctx_restore(struct vdec_mpeg4_hw_s *hw); + +#define PROVIDER_NAME "vdec.mpeg4" + +/* + *int query_video_status(int type, int *value); + */ +static const struct vframe_operations_s vf_provider_ops = { + .peek = vmpeg_vf_peek, + .get = vmpeg_vf_get, + .put = vmpeg_vf_put, + .event_cb = vmpeg_event_cb, + .vf_states = vmpeg_vf_states, +}; + +static unsigned char aspect_ratio_table[16] = { + PARC_FORBIDDEN, + PARC_SQUARE, + PARC_CIF, + PARC_10_11, + PARC_16_11, + PARC_40_33, + PARC_RESERVED, PARC_RESERVED, PARC_RESERVED, PARC_RESERVED, + PARC_RESERVED, PARC_RESERVED, PARC_RESERVED, PARC_RESERVED, + PARC_RESERVED, PARC_EXTENDED +}; + +static int find_buffer(struct vdec_mpeg4_hw_s *hw) +{ + int i; + + for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) { + if (hw->vfbuf_use[i] == 0) + return i; + } + + return -1; +} + +static int spec_to_index(struct vdec_mpeg4_hw_s *hw, u32 spec) +{ + int i; + + for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) { + if (hw->canvas_spec[i] == spec) + return i; + } + + return -1; +} + +static void set_frame_info(struct vdec_mpeg4_hw_s *hw, struct vframe_s *vf, + int buffer_index) +{ + int ar = 0; + unsigned int num = 0; + unsigned int den = 0; + unsigned int pixel_ratio = READ_VREG(MP4_PIC_RATIO); + + if (hw->vmpeg4_ratio64 != 0) { + num = hw->vmpeg4_ratio64>>32; + den = hw->vmpeg4_ratio64 & 0xffffffff; + } else { + num = hw->vmpeg4_ratio>>16; + den = hw->vmpeg4_ratio & 0xffff; + + } + if ((num == 0) || (den == 0)) { + num = 1; + den = 1; + } + + if (hw->vmpeg4_ratio == 0) { + vf->ratio_control |= (0x90 << DISP_RATIO_ASPECT_RATIO_BIT); + /* always stretch to 16:9 */ + } else if (pixel_ratio > 0x0f) { + num = (pixel_ratio >> 8) * + hw->vmpeg4_amstream_dec_info.width * num; + ar = div_u64((pixel_ratio & 0xff) * + hw->vmpeg4_amstream_dec_info.height * den * 0x100ULL + + (num >> 1), num); + } else { + switch (aspect_ratio_table[pixel_ratio]) { + case 0: + num = hw->vmpeg4_amstream_dec_info.width * num; + ar = (hw->vmpeg4_amstream_dec_info.height * den * + 0x100 + (num >> 1)) / num; + break; + case 1: + num = vf->width * num; + ar = (vf->height * den * 0x100 + (num >> 1)) / num; + break; + case 2: + num = (vf->width * 12) * num; + ar = (vf->height * den * 0x100 * 11 + + ((num) >> 1)) / num; + break; + case 3: + num = (vf->width * 10) * num; + ar = (vf->height * den * 0x100 * 11 + (num >> 1)) / + num; + break; + case 4: + num = (vf->width * 16) * num; + ar = (vf->height * den * 0x100 * 11 + (num >> 1)) / + num; + break; + case 5: + num = (vf->width * 40) * num; + ar = (vf->height * den * 0x100 * 33 + (num >> 1)) / + num; + break; + default: + num = vf->width * num; + ar = (vf->height * den * 0x100 + (num >> 1)) / num; + break; + } + } + + ar = min(ar, DISP_RATIO_ASPECT_RATIO_MAX); + + vf->signal_type = 0; + vf->type_original = vf->type; + vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT); + vf->canvas0Addr = vf->canvas1Addr = -1; +#ifdef NV21 + vf->plane_num = 2; +#else + vf->plane_num = 3; +#endif + vf->canvas0_config[0] = hw->canvas_config[buffer_index][0]; + vf->canvas0_config[1] = hw->canvas_config[buffer_index][1]; +#ifndef NV21 + vf->canvas0_config[2] = hw->canvas_config[buffer_index][2]; +#endif + vf->canvas1_config[0] = hw->canvas_config[buffer_index][0]; + vf->canvas1_config[1] = hw->canvas_config[buffer_index][1]; +#ifndef NV21 + vf->canvas1_config[2] = hw->canvas_config[buffer_index][2]; +#endif +} + +static inline void vmpeg4_save_hw_context(struct vdec_mpeg4_hw_s *hw) +{ + hw->reg_mpeg1_2_reg = READ_VREG(MPEG1_2_REG); + hw->reg_vcop_ctrl_reg = READ_VREG(VCOP_CTRL_REG); + hw->reg_pic_head_info = READ_VREG(PIC_HEAD_INFO); + hw->reg_slice_qp = READ_VREG(SLICE_QP); + hw->reg_mp4_pic_wh = READ_VREG(MP4_PIC_WH); + hw->reg_mp4_rate = READ_VREG(MP4_RATE); + hw->reg_mb_info = READ_VREG(MB_INFO); + hw->reg_dc_ac_ctrl = READ_VREG(DC_AC_CTRL); + hw->reg_iqidct_control = READ_VREG(IQIDCT_CONTROL); + hw->reg_resync_marker_length = READ_VREG(RESYNC_MARKER_LENGTH); + hw->reg_rv_ai_mb_count = READ_VREG(RV_AI_MB_COUNT); +} + +static irqreturn_t vmpeg4_isr(struct vdec_s *vdec, int irq) +{ + u32 reg; + struct vframe_s *vf = NULL; + u32 picture_type; + int index; + u32 pts, offset = 0; + bool pts_valid = false; + u64 pts_us64 = 0; + u32 time_increment_resolution, fixed_vop_rate, vop_time_inc; + u32 repeat_cnt, duration = 3200; + struct vdec_mpeg4_hw_s *hw = (struct vdec_mpeg4_hw_s *)(vdec->private); + + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + reg = READ_VREG(MREG_BUFFEROUT); + + time_increment_resolution = READ_VREG(MP4_RATE); + fixed_vop_rate = time_increment_resolution >> 16; + time_increment_resolution &= 0xffff; + + if (hw->vmpeg4_amstream_dec_info.rate == 0) { + if ((fixed_vop_rate != 0) && (time_increment_resolution != 0)) { + /* fixed VOP rate */ + hw->vmpeg4_amstream_dec_info.rate = fixed_vop_rate * + DURATION_UNIT / + time_increment_resolution; + } + } + + if (reg == 2) { + /* timeout when decoding next frame */ + + /* for frame based case, insufficient result may happen + * at the beginning when only VOL head is available save + * HW context also, such as for the QTable from VCOP register + */ + if (input_frame_based(vdec)) + vmpeg4_save_hw_context(hw); + + hw->dec_result = DEC_RESULT_AGAIN; + + schedule_work(&hw->work); + + return IRQ_HANDLED; + } else { + picture_type = (reg >> 3) & 7; + repeat_cnt = READ_VREG(MP4_NOT_CODED_CNT); + vop_time_inc = READ_VREG(MP4_VOP_TIME_INC); + + index = spec_to_index(hw, READ_VREG(REC_CANVAS_ADDR)); + + if (index < 0) { + pr_err("invalid buffer index."); + hw->dec_result = DEC_RESULT_ERROR; + + schedule_work(&hw->work); + + return IRQ_HANDLED; + } + + hw->dec_result = DEC_RESULT_DONE; + + pr_debug("amvdec_mpeg4: offset = 0x%x\n", + READ_VREG(MP4_OFFSET_REG)); + + if (hw->vmpeg4_amstream_dec_info.width == 0) { + hw->vmpeg4_amstream_dec_info.width = + READ_VREG(MP4_PIC_WH) >> 16; + } +#if 0 + else { + pr_info("info width = %d, ucode width = %d\n", + hw->vmpeg4_amstream_dec_info.width, + READ_VREG(MP4_PIC_WH) >> 16); + } +#endif + + if (hw->vmpeg4_amstream_dec_info.height == 0) { + hw->vmpeg4_amstream_dec_info.height = + READ_VREG(MP4_PIC_WH) & 0xffff; + } +#if 0 + else { + pr_info("info height = %d, ucode height = %d\n", + hw->vmpeg4_amstream_dec_info.height, + READ_VREG(MP4_PIC_WH) & 0xffff); + } +#endif + if (hw->vmpeg4_amstream_dec_info.rate == 0) { + if (vop_time_inc < hw->last_vop_time_inc) { + duration = vop_time_inc + + time_increment_resolution - + hw->last_vop_time_inc; + } else { + duration = vop_time_inc - + hw->last_vop_time_inc; + } + + if (duration == hw->last_duration) { + hw->rate_detect++; + if (hw->rate_detect >= RATE_DETECT_COUNT) { + hw->vmpeg4_amstream_dec_info.rate = + duration * DURATION_UNIT / + time_increment_resolution; + duration = + hw->vmpeg4_amstream_dec_info.rate; + } + } else { + hw->rate_detect = 0; + hw->last_duration = duration; + } + } else { + duration = hw->vmpeg4_amstream_dec_info.rate; +#if 0 + pr_info("info rate = %d, ucode rate = 0x%x:0x%x\n", + hw->vmpeg4_amstream_dec_info.rate, + READ_VREG(MP4_RATE), vop_time_inc); +#endif + } + + if ((picture_type == I_PICTURE) || + (picture_type == P_PICTURE)) { + offset = READ_VREG(MP4_OFFSET_REG); + if (hw->chunk) { + hw->pts_valid[index] = hw->chunk->pts_valid; + hw->pts[index] = hw->chunk->pts; + hw->pts64[index] = hw->chunk->pts64; + } else { + if (pts_lookup_offset_us64 + (PTS_TYPE_VIDEO, offset, &pts, 3000, + &pts_us64) == 0) { + hw->pts_valid[index] = true; + hw->pts[index] = pts; + hw->pts64[index] = pts_us64; + hw->pts_hit++; + } else { + hw->pts_valid[index] = false; + hw->pts_missed++; + } + } + pr_debug("I/P offset 0x%x, pts_valid %d pts=0x%x\n", + offset, hw->pts_valid[index], + hw->pts[index]); + } else { + hw->pts_valid[index] = false; + hw->pts[index] = 0; + hw->pts64[index] = 0; + } + + hw->buffer_info[index] = reg; + hw->vfbuf_use[index] = 0; + + pr_debug("amvdec_mpeg4: decoded buffer %d, frame_type %s\n", + index, + (picture_type == I_PICTURE) ? "I" : + (picture_type == P_PICTURE) ? "P" : "B"); + + /* Buffer management + * todo: add sequence-end flush + */ + if ((picture_type == I_PICTURE) || + (picture_type == P_PICTURE)) { + hw->vfbuf_use[index]++; + + if (hw->refs[1] == -1) { + hw->refs[1] = index; + index = -1; + } else if (hw->refs[0] == -1) { + hw->refs[0] = hw->refs[1]; + hw->refs[1] = index; + index = hw->refs[0]; + } else { + hw->vfbuf_use[hw->refs[0]]--; + hw->refs[0] = hw->refs[1]; + hw->refs[1] = index; + index = hw->refs[0]; + } + } else { + /* if this is a B frame, then drop (depending on if + * there are two reference frames) or display + * immediately + */ + if (hw->refs[1] == -1) + index = -1; + } + + vmpeg4_save_hw_context(hw); + + if (index < 0) { + schedule_work(&hw->work); + return IRQ_HANDLED; + } + + reg = hw->buffer_info[index]; + pts_valid = hw->pts_valid[index]; + pts = hw->pts[index]; + pts_us64 = hw->pts64[index]; + + pr_debug("queued buffer %d, pts = 0x%x, pts_valid=%d\n", + index, pts, pts_valid); + + if (pts_valid) { + hw->last_anch_pts = pts; + hw->last_anch_pts_us64 = pts_us64; + hw->frame_num_since_last_anch = 0; + hw->vop_time_inc_since_last_anch = 0; + } else { + pts = hw->last_anch_pts; + pts_us64 = hw->last_anch_pts_us64; + + if ((time_increment_resolution != 0) && + (fixed_vop_rate == 0) && + (hw->vmpeg4_amstream_dec_info.rate == 0)) { + /* variable PTS rate */ + /*bug on variable pts calc, + *do as dixed vop first if we + *have rate setting before. + */ + if (vop_time_inc > hw->last_vop_time_inc) { + duration = vop_time_inc - + hw->last_vop_time_inc; + } else { + duration = vop_time_inc + + time_increment_resolution - + hw->last_vop_time_inc; + } + + hw->vop_time_inc_since_last_anch += duration; + + pts += hw->vop_time_inc_since_last_anch * + PTS_UNIT / time_increment_resolution; + pts_us64 += (hw->vop_time_inc_since_last_anch * + PTS_UNIT / time_increment_resolution) * + 100 / 9; + + if (hw->vop_time_inc_since_last_anch > + (1 << 14)) { + /* avoid overflow */ + hw->last_anch_pts = pts; + hw->last_anch_pts_us64 = pts_us64; + hw->vop_time_inc_since_last_anch = 0; + } + } else { + /* fixed VOP rate */ + hw->frame_num_since_last_anch++; + pts += DUR2PTS(hw->frame_num_since_last_anch * + hw->vmpeg4_amstream_dec_info.rate); + pts_us64 += DUR2PTS( + hw->frame_num_since_last_anch * + hw->vmpeg4_amstream_dec_info.rate) * + 100 / 9; + + if (hw->frame_num_since_last_anch > (1 << 15)) { + /* avoid overflow */ + hw->last_anch_pts = pts; + hw->last_anch_pts_us64 = pts_us64; + hw->frame_num_since_last_anch = 0; + } + } + } + + if (reg & INTERLACE_FLAG) { /* interlace */ + if (kfifo_get(&hw->newframe_q, &vf) == 0) { + pr_err + ("fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + + vf->index = index; + vf->width = hw->vmpeg4_amstream_dec_info.width; + vf->height = hw->vmpeg4_amstream_dec_info.height; + vf->bufWidth = 1920; + vf->flag = 0; + vf->orientation = hw->vmpeg4_rotation; + vf->pts = pts; + vf->pts_us64 = pts_us64; + vf->duration = duration >> 1; + vf->duration_pulldown = 0; + vf->type = (reg & TOP_FIELD_FIRST_FLAG) ? + VIDTYPE_INTERLACE_TOP : + VIDTYPE_INTERLACE_BOTTOM; +#ifdef NV21 + vf->type |= VIDTYPE_VIU_NV21; +#endif + set_frame_info(hw, vf, index); + + hw->vfbuf_use[index]++; + + kfifo_put(&hw->display_q, (const struct vframe_s *)vf); + + vf_notify_receiver(vdec->vf_provider_name, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + + if (kfifo_get(&hw->newframe_q, &vf) == 0) { + pr_err("fatal error, no available buffer slot."); + hw->dec_result = DEC_RESULT_ERROR; + schedule_work(&hw->work); + return IRQ_HANDLED; + } + + vf->index = index; + vf->width = hw->vmpeg4_amstream_dec_info.width; + vf->height = hw->vmpeg4_amstream_dec_info.height; + vf->bufWidth = 1920; + vf->flag = 0; + vf->orientation = hw->vmpeg4_rotation; + + vf->pts = 0; + vf->pts_us64 = 0; + vf->duration = duration >> 1; + + vf->duration_pulldown = 0; + vf->type = (reg & TOP_FIELD_FIRST_FLAG) ? + VIDTYPE_INTERLACE_BOTTOM : VIDTYPE_INTERLACE_TOP; +#ifdef NV21 + vf->type |= VIDTYPE_VIU_NV21; +#endif + set_frame_info(hw, vf, index); + + hw->vfbuf_use[index]++; + + kfifo_put(&hw->display_q, (const struct vframe_s *)vf); + + vf_notify_receiver(vdec->vf_provider_name, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + + } else { /* progressive */ + if (kfifo_get(&hw->newframe_q, &vf) == 0) { + pr_err("fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + + vf->index = index; + vf->width = hw->vmpeg4_amstream_dec_info.width; + vf->height = hw->vmpeg4_amstream_dec_info.height; + vf->bufWidth = 1920; + vf->flag = 0; + vf->orientation = hw->vmpeg4_rotation; + vf->pts = pts; + vf->pts_us64 = pts_us64; + vf->duration = duration; + vf->duration_pulldown = repeat_cnt * duration; +#ifdef NV21 + vf->type = + VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD | + VIDTYPE_VIU_NV21; +#else + vf->type = + VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD; +#endif + set_frame_info(hw, vf, index); + + + hw->vfbuf_use[index]++; + + kfifo_put(&hw->display_q, (const struct vframe_s *)vf); + + vf_notify_receiver(vdec->vf_provider_name, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + } + + hw->total_frame += repeat_cnt + 1; + hw->last_vop_time_inc = vop_time_inc; + + schedule_work(&hw->work); + } + + return IRQ_HANDLED; +} + +static void vmpeg4_work(struct work_struct *work) +{ + struct vdec_mpeg4_hw_s *hw = + container_of(work, struct vdec_mpeg4_hw_s, work); + + /* finished decoding one frame or error, + * notify vdec core to switch context + */ + amvdec_stop(); + + if ((hw->dec_result == DEC_RESULT_DONE) || + ((hw->chunk) && + (input_frame_based(&(hw_to_vdec(hw))->input)))) { + if (!hw->ctx_valid) + hw->ctx_valid = 1; + + vdec_vframe_dirty(hw_to_vdec(hw), hw->chunk); + } + + /* mark itself has all HW resource released and input released */ + vdec_core_finish_run(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC); + + if (hw->vdec_cb) + hw->vdec_cb(hw_to_vdec(hw), hw->vdec_cb_arg); +} + +static struct vframe_s *vmpeg_vf_peek(void *op_arg) +{ + struct vframe_s *vf; + struct vdec_s *vdec = op_arg; + struct vdec_mpeg4_hw_s *hw = (struct vdec_mpeg4_hw_s *)vdec->private; + + if (!hw) + return NULL; + + if (kfifo_peek(&hw->display_q, &vf)) + return vf; + + return NULL; +} + +static struct vframe_s *vmpeg_vf_get(void *op_arg) +{ + struct vframe_s *vf; + struct vdec_s *vdec = op_arg; + struct vdec_mpeg4_hw_s *hw = (struct vdec_mpeg4_hw_s *)vdec->private; + + if (kfifo_get(&hw->display_q, &vf)) + return vf; + + return NULL; +} + +static void vmpeg_vf_put(struct vframe_s *vf, void *op_arg) +{ + struct vdec_s *vdec = op_arg; + struct vdec_mpeg4_hw_s *hw = (struct vdec_mpeg4_hw_s *)vdec->private; + + hw->vfbuf_use[vf->index]--; + + kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf); +} + +static int vmpeg_event_cb(int type, void *data, void *private_data) +{ + return 0; +} + +static int vmpeg_vf_states(struct vframe_states *states, void *op_arg) +{ + unsigned long flags; + struct vdec_s *vdec = op_arg; + struct vdec_mpeg4_hw_s *hw = (struct vdec_mpeg4_hw_s *)vdec->private; + + spin_lock_irqsave(&hw->lock, flags); + + states->vf_pool_size = VF_POOL_SIZE; + states->buf_free_num = kfifo_len(&hw->newframe_q); + states->buf_avail_num = kfifo_len(&hw->display_q); + states->buf_recycle_num = 0; + + spin_unlock_irqrestore(&hw->lock, flags); + + return 0; +} + + +static int dec_status(struct vdec_s *vdec, struct vdec_info *vstatus) +{ + struct vdec_mpeg4_hw_s *hw = (struct vdec_mpeg4_hw_s *)vdec->private; + + vstatus->frame_width = hw->vmpeg4_amstream_dec_info.width; + vstatus->frame_height = hw->vmpeg4_amstream_dec_info.height; + if (0 != hw->vmpeg4_amstream_dec_info.rate) + vstatus->frame_rate = DURATION_UNIT / + hw->vmpeg4_amstream_dec_info.rate; + else + vstatus->frame_rate = DURATION_UNIT; + vstatus->error_count = READ_VREG(MP4_ERR_COUNT); + vstatus->status = hw->stat; + + return 0; +} + +/****************************************/ +static int vmpeg4_canvas_init(struct vdec_mpeg4_hw_s *hw) +{ + int i; + u32 decbuf_size, decbuf_y_size; + struct vdec_s *vdec = hw_to_vdec(hw); + u32 decbuf_start; + + int w = hw->vmpeg4_amstream_dec_info.width; + int h = hw->vmpeg4_amstream_dec_info.height; + + if (w == 0) + w = 1920; + if (h == 0) + h = 1088; + + w = ALIGN(w, 64); + h = ALIGN(h, 64); + decbuf_y_size = ALIGN(w * h, SZ_64K); + decbuf_size = ALIGN(w * h * 3/2, SZ_64K); + + decbuf_start = hw->buf_start + CTX_DECBUF_OFFSET; + + for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) { +#ifdef NV21 + unsigned int canvas = vdec->get_canvas(i, 2); +#else + unsigned int canvas = vdec->get_canvas(i, 3); +#endif + + hw->canvas_spec[i] = canvas; + +#ifdef NV21 + hw->canvas_config[i][0].phy_addr = decbuf_start + + i * decbuf_size; + hw->canvas_config[i][0].width = w; + hw->canvas_config[i][0].height = h; + hw->canvas_config[i][0].block_mode = CANVAS_BLKMODE_32X32; + + canvas_config_config(canvas_y(canvas), + &hw->canvas_config[i][0]); + + hw->canvas_config[i][1].phy_addr = decbuf_start + + i * decbuf_size + decbuf_y_size; + hw->canvas_config[i][1].width = w; + hw->canvas_config[i][1].height = h / 2; + hw->canvas_config[i][1].block_mode = CANVAS_BLKMODE_32X32; + + canvas_config_config(canvas_u(canvas), + &hw->canvas_config[i][1]); +#else + hw->canvas_config[i][0].phy_addr = decbuf_start + + i * decbuf_size; + hw->canvas_config[i][0].width = w; + hw->canvas_config[i][0].height = h; + hw->canvas_config[i][0].block_mode = CANVAS_BLKMODE_32X32; + + canvas_config_config(canvas_y(canvas), + &hw->canvas_config[i][0]); + + hw->canvas_config[i][1].phy_addr = decbuf_start + + i * decbuf_size + decbuf_y_size; + hw->canvas_config[i][1].width = w / 2; + hw->canvas_config[i][1].height = h / 2; + hw->canvas_config[i][1].block_mode = CANVAS_BLKMODE_32X32; + + canvas_config_config(canvas_u(canvas), + &hw->canvas_config[i][1]); + + hw->canvas_config[i][2].phy_addr = decbuf_start + + i * decbuf_size + decbuf_y_size + + decbuf_uv_size; + hw->canvas_config[i][2].width = w / 2; + hw->canvas_config[i][2].height = h / 2; + hw->canvas_config[i][2].block_mode = CANVAS_BLKMODE_32X32; + + canvas_config_config(canvas_v(canvas), + &hw->canvas_config[i][2]); +#endif + } + + return 0; +} + +static int vmpeg4_hw_ctx_restore(struct vdec_mpeg4_hw_s *hw) +{ + int index; + + + index = find_buffer(hw); + if (index < 0) + return -1; + + + if (vmpeg4_canvas_init(hw) < 0) + return -1; + + /* prepare REF0 & REF1 + * points to the past two IP buffers + * prepare REC_CANVAS_ADDR and ANC2_CANVAS_ADDR + * points to the output buffer + */ + if (hw->refs[0] == -1) { + WRITE_VREG(MREG_REF0, (hw->refs[1] == -1) ? 0xffffffff : + hw->canvas_spec[hw->refs[1]]); + } else { + WRITE_VREG(MREG_REF0, (hw->refs[0] == -1) ? 0xffffffff : + hw->canvas_spec[hw->refs[0]]); + } + WRITE_VREG(MREG_REF1, (hw->refs[1] == -1) ? 0xffffffff : + hw->canvas_spec[hw->refs[1]]); + + WRITE_VREG(MREG_REF0, (hw->refs[0] == -1) ? 0xffffffff : + hw->canvas_spec[hw->refs[0]]); + WRITE_VREG(MREG_REF1, (hw->refs[1] == -1) ? 0xffffffff : + hw->canvas_spec[hw->refs[1]]); + WRITE_VREG(REC_CANVAS_ADDR, hw->canvas_spec[index]); + WRITE_VREG(ANC2_CANVAS_ADDR, hw->canvas_spec[index]); + + pr_debug("vmpeg4_hw_ctx_restore ref0=0x%x, ref1=0x%x, rec=0x%x, ctx_valid=%d\n", + READ_VREG(MREG_REF0), + READ_VREG(MREG_REF1), + READ_VREG(REC_CANVAS_ADDR), + hw->ctx_valid); + + /* notify ucode the buffer start address */ + WRITE_VREG(MEM_OFFSET_REG, hw->buf_start); + + /* disable PSCALE for hardware sharing */ + WRITE_VREG(PSCALE_CTRL, 0); + + WRITE_VREG(MREG_BUFFEROUT, 0); + + /* clear mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + /* enable mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_MASK, 1); + + /* clear repeat count */ + WRITE_VREG(MP4_NOT_CODED_CNT, 0); + +#ifdef NV21 + SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17); +#endif + +#if 1/* /MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ + WRITE_VREG(MDEC_PIC_DC_THRESH, 0x404038aa); +#endif + + WRITE_VREG(MP4_PIC_WH, (hw->ctx_valid) ? + hw->reg_mp4_pic_wh : + ((hw->vmpeg4_amstream_dec_info.width << 16) | + hw->vmpeg4_amstream_dec_info.height)); + WRITE_VREG(MP4_SYS_RATE, hw->vmpeg4_amstream_dec_info.rate); + + if (hw->ctx_valid) { + WRITE_VREG(DC_AC_CTRL, hw->reg_dc_ac_ctrl); + WRITE_VREG(IQIDCT_CONTROL, hw->reg_iqidct_control); + WRITE_VREG(RESYNC_MARKER_LENGTH, hw->reg_resync_marker_length); + WRITE_VREG(RV_AI_MB_COUNT, hw->reg_rv_ai_mb_count); + } + WRITE_VREG(MPEG1_2_REG, (hw->ctx_valid) ? hw->reg_mpeg1_2_reg : 1); + WRITE_VREG(VCOP_CTRL_REG, hw->reg_vcop_ctrl_reg); + WRITE_VREG(PIC_HEAD_INFO, hw->reg_pic_head_info); + WRITE_VREG(SLICE_QP, hw->reg_slice_qp); + WRITE_VREG(MB_INFO, hw->reg_mb_info); + + if (hw->chunk) { + /* frame based input */ + WRITE_VREG(MREG_INPUT, (hw->chunk->offset & 7) | (1<<7) | + (hw->ctx_valid<<6)); + } else { + /* stream based input */ + WRITE_VREG(MREG_INPUT, (hw->ctx_valid<<6)); + } + + return 0; +} + +static void vmpeg4_local_init(struct vdec_mpeg4_hw_s *hw) +{ + int i; + + hw->vmpeg4_ratio = hw->vmpeg4_amstream_dec_info.ratio; + + hw->vmpeg4_ratio64 = hw->vmpeg4_amstream_dec_info.ratio64; + + hw->vmpeg4_rotation = + (((unsigned long) hw->vmpeg4_amstream_dec_info.param) + >> 16) & 0xffff; + + hw->frame_width = hw->frame_height = hw->frame_dur = hw->frame_prog = 0; + + hw->total_frame = 0; + + hw->last_anch_pts = 0; + + hw->last_anch_pts_us64 = 0; + + hw->last_vop_time_inc = hw->last_duration = 0; + + hw->vop_time_inc_since_last_anch = 0; + + hw->frame_num_since_last_anch = 0; + + hw->pts_hit = hw->pts_missed = hw->pts_i_hit = hw->pts_i_missed = 0; + + for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) + hw->vfbuf_use[i] = 0; + + INIT_KFIFO(hw->display_q); + INIT_KFIFO(hw->newframe_q); + + for (i = 0; i < VF_POOL_SIZE; i++) { + const struct vframe_s *vf = &hw->vfpool[i]; + + hw->vfpool[i].index = DECODE_BUFFER_NUM_MAX; + kfifo_put(&hw->newframe_q, (const struct vframe_s *)vf); + } + + INIT_WORK(&hw->work, vmpeg4_work); +} + +static s32 vmpeg4_init(struct vdec_mpeg4_hw_s *hw) +{ + int trickmode_fffb = 0; + int size = -1, fw_size = 0x1000 * 16; + struct firmware_s *fw = NULL; + + fw = vmalloc(sizeof(struct firmware_s) + fw_size); + if (IS_ERR_OR_NULL(fw)) + return -ENOMEM; + + if (hw->vmpeg4_amstream_dec_info.format == + VIDEO_DEC_FORMAT_MPEG4_3) { + size = get_firmware_data(VIDEO_DEC_MPEG4_3, fw->data); + + pr_info("load VIDEO_DEC_FORMAT_MPEG4_3\n"); + } else if (hw->vmpeg4_amstream_dec_info.format == + VIDEO_DEC_FORMAT_MPEG4_4) { + size = get_firmware_data(VIDEO_DEC_MPEG4_4, fw->data); + + pr_info("load VIDEO_DEC_FORMAT_MPEG4_4\n"); + } else if (hw->vmpeg4_amstream_dec_info.format == + VIDEO_DEC_FORMAT_MPEG4_5) { + size = get_firmware_data(VIDEO_DEC_MPEG4_5, fw->data); + + pr_info("load VIDEO_DEC_FORMAT_MPEG4_5\n"); + } else if (hw->vmpeg4_amstream_dec_info.format == + VIDEO_DEC_FORMAT_H263) { + size = get_firmware_data(VIDEO_DEC_H263, fw->data); + + pr_info("load VIDEO_DEC_FORMAT_H263\n"); + } + + if (size < 0) { + pr_err("get firmware fail."); + vfree(fw); + return -1; + } + + fw->len = size; + hw->fw = fw; + + query_video_status(0, &trickmode_fffb); + + pr_info("vmpeg4_init\n"); + + amvdec_enable(); + + vmpeg4_local_init(hw); + + return 0; +} + +static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask) +{ + int index; + struct vdec_mpeg4_hw_s *hw = (struct vdec_mpeg4_hw_s *)vdec->private; + + index = find_buffer(hw); + + return (index >= 0) ? (CORE_MASK_VDEC_1 | CORE_MASK_HEVC) : 0; +} + +static void run(struct vdec_s *vdec, unsigned long mask, + void (*callback)(struct vdec_s *, void *), void *arg) +{ + struct vdec_mpeg4_hw_s *hw = (struct vdec_mpeg4_hw_s *)vdec->private; + int save_reg = READ_VREG(POWER_CTL_VLD); + int ret = -1; + + /* reset everything except DOS_TOP[1] and APB_CBUS[0] */ + WRITE_VREG(DOS_SW_RESET0, 0xfffffff0); + WRITE_VREG(DOS_SW_RESET0, 0); + WRITE_VREG(POWER_CTL_VLD, save_reg); + + hw->vdec_cb_arg = arg; + hw->vdec_cb = callback; + + ret = vdec_prepare_input(vdec, &hw->chunk); + if (ret < 0) { + pr_debug("amvdec_mpeg4: Input not ready\n"); + hw->dec_result = DEC_RESULT_AGAIN; + schedule_work(&hw->work); + return; + } + + vdec_enable_input(vdec); + + if (hw->chunk) + pr_debug("input chunk offset %d, size %d\n", + hw->chunk->offset, hw->chunk->size); + + hw->dec_result = DEC_RESULT_NONE; + + if (amvdec_vdec_loadmc_buf_ex(vdec, hw->fw->data, hw->fw->len) < 0) { + pr_err("VIDEO_DEC_FORMAT_MPEG4 ucode loading failed\n"); + hw->dec_result = DEC_RESULT_ERROR; + schedule_work(&hw->work); + return; + } + + if (vmpeg4_hw_ctx_restore(hw) < 0) { + hw->dec_result = DEC_RESULT_ERROR; + pr_err("amvdec_mpeg4: error HW context restore\n"); + schedule_work(&hw->work); + return; + } + + /* wmb before ISR is handled */ + wmb(); + + amvdec_start(); +} + +static void reset(struct vdec_s *vdec) +{ + struct vdec_mpeg4_hw_s *hw = (struct vdec_mpeg4_hw_s *)vdec->private; + + pr_info("amvdec_mpeg4: reset.\n"); + + vmpeg4_local_init(hw); + + hw->ctx_valid = false; +} + +static int amvdec_mpeg4_probe(struct platform_device *pdev) +{ + struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; + struct vdec_mpeg4_hw_s *hw = NULL; + + pr_info("amvdec_mpeg4[%d] probe start.\n", pdev->id); + + if (pdata == NULL) { + pr_err("ammvdec_mpeg4 memory resource undefined.\n"); + return -EFAULT; + } + + hw = (struct vdec_mpeg4_hw_s *)devm_kzalloc(&pdev->dev, + sizeof(struct vdec_mpeg4_hw_s), GFP_KERNEL); + if (hw == NULL) { + pr_info("\namvdec_mpeg4 decoder driver alloc failed\n"); + return -ENOMEM; + } + + pdata->private = hw; + pdata->dec_status = dec_status; + /* pdata->set_trickmode = set_trickmode; */ + pdata->run_ready = run_ready; + pdata->run = run; + pdata->reset = reset; + pdata->irq_handler = vmpeg4_isr; + + + if (pdata->use_vfm_path) + snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE, + VFM_DEC_PROVIDER_NAME); + else + snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE, + PROVIDER_NAME ".%02x", pdev->id & 0xff); + + vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name, + &vf_provider_ops, pdata); + + platform_set_drvdata(pdev, pdata); + + hw->platform_dev = pdev; + hw->cma_dev = pdata->cma_dev; + + hw->cma_alloc_count = PAGE_ALIGN(DEFAULT_MEM_SIZE) / PAGE_SIZE; + hw->cma_alloc_addr = codec_mm_alloc_for_dma(MEM_NAME, + hw->cma_alloc_count, + 4, CODEC_MM_FLAGS_FOR_VDECODER); + + if (!hw->cma_alloc_addr) { + pr_err("codec_mm alloc failed, request buf size 0x%lx\n", + hw->cma_alloc_count * PAGE_SIZE); + hw->cma_alloc_count = 0; + return -ENOMEM; + } + hw->buf_start = hw->cma_alloc_addr; + hw->buf_size = DEFAULT_MEM_SIZE; + + if (pdata->sys_info) + hw->vmpeg4_amstream_dec_info = *pdata->sys_info; + + if (vmpeg4_init(hw) < 0) { + pr_err("amvdec_mpeg4 init failed.\n"); + + return -ENODEV; + } + + vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC + | CORE_MASK_COMBINE); + + return 0; +} + +static int amvdec_mpeg4_remove(struct platform_device *pdev) +{ + struct vdec_mpeg4_hw_s *hw = + (struct vdec_mpeg4_hw_s *) + (((struct vdec_s *)(platform_get_drvdata(pdev)))->private); + + + vdec_core_release(hw_to_vdec(hw), CORE_MASK_VDEC_1 | CORE_MASK_HEVC); + + amvdec_disable(); + + if (hw->cma_alloc_addr) { + pr_info("codec_mm release buffer 0x%lx\n", hw->cma_alloc_addr); + codec_mm_free_for_dma(MEM_NAME, hw->cma_alloc_addr); + hw->cma_alloc_count = 0; + } + + vfree(hw->fw); + hw->fw = NULL; + + pr_info("pts hit %d, pts missed %d, i hit %d, missed %d\n", hw->pts_hit, + hw->pts_missed, hw->pts_i_hit, hw->pts_i_missed); + pr_info("total frame %d, rate %d\n", hw->total_frame, + hw->vmpeg4_amstream_dec_info.rate); + + return 0; +} + +/****************************************/ + +static struct platform_driver amvdec_mpeg4_driver = { + .probe = amvdec_mpeg4_probe, + .remove = amvdec_mpeg4_remove, +#ifdef CONFIG_PM + .suspend = amvdec_suspend, + .resume = amvdec_resume, +#endif + .driver = { + .name = DRIVER_NAME, + } +}; + +static struct codec_profile_t amvdec_mpeg4_profile = { + .name = "mmpeg4", + .profile = "" +}; + +static int __init amvdec_mmpeg4_driver_init_module(void) +{ + pr_info("amvdec_mmpeg4 module init\n"); + + if (platform_driver_register(&amvdec_mpeg4_driver)) { + pr_err("failed to register amvdec_mpeg4 driver\n"); + return -ENODEV; + } + vcodec_profile_register(&amvdec_mpeg4_profile); + return 0; +} + +static void __exit amvdec_mmpeg4_driver_remove_module(void) +{ + pr_info("amvdec_mmpeg4 module remove.\n"); + + platform_driver_unregister(&amvdec_mpeg4_driver); +} + +/****************************************/ + +module_init(amvdec_mmpeg4_driver_init_module); +module_exit(amvdec_mmpeg4_driver_remove_module); + +MODULE_DESCRIPTION("AMLOGIC MPEG4 Video Decoder Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Tim Yao "); + diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/real/Makefile b/drivers/amlogic/media_modules/frame_provider/decoder/real/Makefile new file mode 100644 index 000000000000..ab03ef29f11b --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/real/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_AMLOGIC_MEDIA_VDEC_REAL) += amvdec_real.o +amvdec_real-objs += vreal.o diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/real/vreal.c b/drivers/amlogic/media_modules/frame_provider/decoder/real/vreal.c new file mode 100644 index 000000000000..ef0f340d2b78 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/real/vreal.c @@ -0,0 +1,1040 @@ +/* + * drivers/amlogic/amports/vreal.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../../stream_input/amports/amports_priv.h" +#include "../utils/vdec.h" +#include +#include "../utils/amvdec.h" + +#include "../../../stream_input/parser/streambuf.h" +#include "../../../stream_input/parser/streambuf_reg.h" +#include "../../../stream_input/parser/rmparser.h" + +#include "vreal.h" +#include +#include "../utils/decoder_mmu_box.h" +#include "../utils/decoder_bmmu_box.h" +#include +#include +#include "../utils/firmware.h" + +#define DRIVER_NAME "amvdec_real" +#define MODULE_NAME "amvdec_real" + +#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ +#define NV21 +#endif + +#define RM_DEF_BUFFER_ADDR 0x01000000 +/* protocol registers */ +#define STATUS_AMRISC AV_SCRATCH_4 + +#define RV_PIC_INFO AV_SCRATCH_5 +#define VPTS_TR AV_SCRATCH_6 +#define VDTS AV_SCRATCH_7 +#define FROM_AMRISC AV_SCRATCH_8 +#define TO_AMRISC AV_SCRATCH_9 +#define SKIP_B_AMRISC AV_SCRATCH_A +#define INT_REASON AV_SCRATCH_B +#define WAIT_BUFFER AV_SCRATCH_E + +#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ +#define MDEC_WIDTH AV_SCRATCH_I +#define MDEC_HEIGHT AV_SCRATCH_J +#else +#define MDEC_WIDTH HARM_ASB_MB2 +#define MDEC_HEIGHT HASB_ARM_MB0 +#endif + +#define PARC_FORBIDDEN 0 +#define PARC_SQUARE 1 +#define PARC_CIF 2 +#define PARC_10_11 3 +#define PARC_16_11 4 +#define PARC_40_33 5 +#define PARC_RESERVED 6 +/* values between 6 and 14 are reserved */ +#define PARC_EXTENDED 15 + +#define VF_POOL_SIZE 16 +#define VF_BUF_NUM 4 +#define PUT_INTERVAL (HZ/100) +#define WORKSPACE_SIZE (1 * SZ_1M) +#define MAX_BMMU_BUFFER_NUM (VF_BUF_NUM + 1) +#define RV_AI_BUFF_START_IP 0x01f00000 + +static struct vframe_s *vreal_vf_peek(void *); +static struct vframe_s *vreal_vf_get(void *); +static void vreal_vf_put(struct vframe_s *, void *); +static int vreal_vf_states(struct vframe_states *states, void *); +static int vreal_event_cb(int type, void *data, void *private_data); + +static int vreal_prot_init(void); +static void vreal_local_init(void); + +static const char vreal_dec_id[] = "vreal-dev"; + +#define PROVIDER_NAME "decoder.real" + +/* + *int query_video_status(int type, int *value); + */ +static const struct vframe_operations_s vreal_vf_provider = { + .peek = vreal_vf_peek, + .get = vreal_vf_get, + .put = vreal_vf_put, + .event_cb = vreal_event_cb, + .vf_states = vreal_vf_states, +}; + +static struct vframe_provider_s vreal_vf_prov; +static void *mm_blk_handle; + +static DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE); +static DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE); +static DECLARE_KFIFO(recycle_q, struct vframe_s *, VF_POOL_SIZE); + +static struct vframe_s vfpool[VF_POOL_SIZE]; +static s32 vfbuf_use[VF_BUF_NUM]; + +static u32 frame_width, frame_height, frame_dur, frame_prog; +static u32 saved_resolution; +static struct timer_list recycle_timer; +static u32 stat; +static u32 buf_size = 32 * 1024 * 1024; +static u32 buf_offset; +static u32 vreal_ratio; +u32 vreal_format; +static u32 wait_key_frame; +static u32 last_tr; +static u32 frame_count; +static u32 current_vdts; +static u32 hold; +static u32 decoder_state; +static u32 real_err_count; + +static u32 fatal_flag; +static s32 wait_buffer_counter; +static struct work_struct set_clk_work; +static bool is_reset; + +static DEFINE_SPINLOCK(lock); + +static unsigned short pic_sz_tbl[12] ____cacheline_aligned; +static dma_addr_t pic_sz_tbl_map; +static const unsigned char RPR_size[9] = { 0, 1, 1, 2, 2, 3, 3, 3, 3 }; + +static struct dec_sysinfo vreal_amstream_dec_info; + +static unsigned char aspect_ratio_table[16] = { + PARC_FORBIDDEN, + PARC_SQUARE, + PARC_CIF, + PARC_10_11, + PARC_16_11, + PARC_40_33, + PARC_RESERVED, PARC_RESERVED, PARC_RESERVED, PARC_RESERVED, + PARC_RESERVED, PARC_RESERVED, PARC_RESERVED, PARC_RESERVED, + PARC_RESERVED, PARC_EXTENDED +}; + +static inline u32 index2canvas(u32 index) +{ + const u32 canvas_tab[4] = { +#ifdef NV21 + 0x010100, 0x030302, 0x050504, 0x070706 +#else + 0x020100, 0x050403, 0x080706, 0x0b0a09 +#endif + }; + + return canvas_tab[index]; +} + +static void set_aspect_ratio(struct vframe_s *vf, unsigned int pixel_ratio) +{ + int ar = 0; + + if (vreal_ratio == 0) { + vf->ratio_control |= (0x90 << + DISP_RATIO_ASPECT_RATIO_BIT); + /* always stretch to 16:9 */ + } else { + switch (aspect_ratio_table[pixel_ratio]) { + case 0: + ar = vreal_amstream_dec_info.height * vreal_ratio / + vreal_amstream_dec_info.width; + break; + case 1: + case 0xff: + ar = vreal_ratio * vf->height / vf->width; + break; + case 2: + ar = (vreal_ratio * vf->height * 12) / (vf->width * 11); + break; + case 3: + ar = (vreal_ratio * vf->height * 11) / (vf->width * 10); + break; + case 4: + ar = (vreal_ratio * vf->height * 11) / (vf->width * 16); + break; + case 5: + ar = (vreal_ratio * vf->height * 33) / (vf->width * 40); + break; + default: + ar = vreal_ratio * vf->height / vf->width; + break; + } + } + + ar = min(ar, DISP_RATIO_ASPECT_RATIO_MAX); + + vf->ratio_control |= (ar << DISP_RATIO_ASPECT_RATIO_BIT); +} + +static irqreturn_t vreal_isr(int irq, void *dev_id) +{ + u32 from; + struct vframe_s *vf = NULL; + u32 buffer_index; + unsigned int status; + unsigned int vdts; + unsigned int info; + unsigned int tr; + unsigned int pictype; + u32 r = READ_VREG(INT_REASON); + + if (decoder_state == 0) + return IRQ_HANDLED; + + status = READ_VREG(STATUS_AMRISC); + if (status & (PARSER_ERROR_WRONG_PACKAGE_SIZE | + PARSER_ERROR_WRONG_HEAD_VER | + DECODER_ERROR_VLC_DECODE_TBL)) { + /* decoder or parser error */ + real_err_count++; + /* pr_info("real decoder or parser + *error, status 0x%x\n", status); + */ + } + + if (r == 2) { + pr_info("first vpts = 0x%x\n", READ_VREG(VDTS)); + pts_checkin_offset(PTS_TYPE_AUDIO, 0, READ_VREG(VDTS) * 90); + WRITE_VREG(AV_SCRATCH_B, 0); + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + return IRQ_HANDLED; + } else if (r == 3) { + pr_info("first apts = 0x%x\n", READ_VREG(VDTS)); + pts_checkin_offset(PTS_TYPE_VIDEO, 0, READ_VREG(VDTS) * 90); + WRITE_VREG(AV_SCRATCH_B, 0); + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + return IRQ_HANDLED; + } + + from = READ_VREG(FROM_AMRISC); + if ((hold == 0) && from) { + tr = READ_VREG(VPTS_TR); + pictype = (tr >> 13) & 3; + tr = (tr & 0x1fff) * 96; + + if (kfifo_get(&newframe_q, &vf) == 0) { + pr_info("fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + + vdts = READ_VREG(VDTS); + if (last_tr == -1) /* ignore tr for first time */ + vf->duration = frame_dur; + else { + if (tr > last_tr) + vf->duration = tr - last_tr; + else + vf->duration = (96 << 13) + tr - last_tr; + + if (vf->duration > 10 * frame_dur) { + /* not a reasonable duration, + *should not happen + */ + vf->duration = frame_dur; + } +#if 0 + else { + if (check_frame_duration == 0) { + frame_dur = vf->duration; + check_frame_duration = 1; + } + } +#endif + } + + last_tr = tr; + buffer_index = from & 0x03; + + if (pictype == 0) { /* I */ + current_vdts = vdts * 90 + 1; + vf->pts = current_vdts; + if (wait_key_frame) + wait_key_frame = 0; + } else { + if (wait_key_frame) { + while (READ_VREG(TO_AMRISC)) + ; + WRITE_VREG(TO_AMRISC, ~(1 << buffer_index)); + WRITE_VREG(FROM_AMRISC, 0); + return IRQ_HANDLED; + } else { + current_vdts += + vf->duration - (vf->duration >> 4); + vf->pts = current_vdts; + } + } + + /* pr_info("pts %d, picture type %d\n", vf->pts, pictype); */ + + info = READ_VREG(RV_PIC_INFO); + vf->signal_type = 0; + vf->index = buffer_index; + vf->width = info >> 16; + vf->height = (info >> 4) & 0xfff; + vf->bufWidth = 1920; + vf->flag = 0; + vf->ratio_control = 0; + set_aspect_ratio(vf, info & 0x0f); + vf->duration_pulldown = 0; +#ifdef NV21 + vf->type = VIDTYPE_PROGRESSIVE | + VIDTYPE_VIU_FIELD | VIDTYPE_VIU_NV21; +#else + vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD; +#endif + vf->canvas0Addr = vf->canvas1Addr = index2canvas(buffer_index); + vf->orientation = 0; + vf->type_original = vf->type; + + vfbuf_use[buffer_index] = 1; + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + buffer_index); + + kfifo_put(&display_q, (const struct vframe_s *)vf); + + frame_count++; + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL); + WRITE_VREG(FROM_AMRISC, 0); + } + + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + return IRQ_HANDLED; +} + +static struct vframe_s *vreal_vf_peek(void *op_arg) +{ + struct vframe_s *vf; + + if (kfifo_peek(&display_q, &vf)) + return vf; + + return NULL; +} + +static struct vframe_s *vreal_vf_get(void *op_arg) +{ + struct vframe_s *vf; + + if (kfifo_get(&display_q, &vf)) + return vf; + + return NULL; +} + +static void vreal_vf_put(struct vframe_s *vf, void *op_arg) +{ + kfifo_put(&recycle_q, (const struct vframe_s *)vf); +} + +static int vreal_event_cb(int type, void *data, void *private_data) +{ + if (type & VFRAME_EVENT_RECEIVER_RESET) { + unsigned long flags; + + amvdec_stop(); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_light_unreg_provider(&vreal_vf_prov); +#endif + spin_lock_irqsave(&lock, flags); + vreal_local_init(); + vreal_prot_init(); + spin_unlock_irqrestore(&lock, flags); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_reg_provider(&vreal_vf_prov); +#endif + amvdec_start(); + } + return 0; +} + +static int vreal_vf_states(struct vframe_states *states, void *op_arg) +{ + unsigned long flags; + + spin_lock_irqsave(&lock, flags); + + states->vf_pool_size = VF_POOL_SIZE; + states->buf_free_num = kfifo_len(&newframe_q); + states->buf_avail_num = kfifo_len(&display_q); + states->buf_recycle_num = kfifo_len(&recycle_q); + + spin_unlock_irqrestore(&lock, flags); + + return 0; +} +#if 0 +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER +static void vreal_ppmgr_reset(void) +{ + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_RESET, NULL); + + vreal_local_init(); + + pr_info("vrealdec: vf_ppmgr_reset\n"); +} +#endif +#endif + +static void vreal_set_clk(struct work_struct *work) +{ + if (frame_dur > 0 && + saved_resolution != + frame_width * frame_height * (96000 / frame_dur)) { + int fps = 96000 / frame_dur; + + saved_resolution = frame_width * frame_height * fps; + vdec_source_changed(VFORMAT_REAL, + frame_width, frame_height, fps); + } +} + +static void vreal_put_timer_func(unsigned long arg) +{ + struct timer_list *timer = (struct timer_list *)arg; + /* unsigned int status; */ + +#if 0 + enum receviver_start_e state = RECEIVER_INACTIVE; + + if (vf_get_receiver(PROVIDER_NAME)) { + state = + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_QUREY_STATE, NULL); + if ((state == RECEIVER_STATE_NULL) + || (state == RECEIVER_STATE_NONE)) { + /* receiver has no event_cb + *or receiver's event_cb does not process this event + */ + state = RECEIVER_INACTIVE; + } + } else + state = RECEIVER_INACTIVE; + + if ((READ_VREG(WAIT_BUFFER) != 0) && + kfifo_is_empty(&display_q) && + kfifo_is_empty(&recycle_q) && (state == RECEIVER_INACTIVE)) { + pr_info("$$$$$$decoder is waiting for buffer\n"); + if (++wait_buffer_counter > 2) { + amvdec_stop(); + +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vreal_ppmgr_reset(); +#else + vf_light_unreg_provider(&vreal_vf_prov); + vreal_local_init(); + vf_reg_provider(&vreal_vf_prov); +#endif + vreal_prot_init(); + amvdec_start(); + } + } +#endif + + while (!kfifo_is_empty(&recycle_q) && (READ_VREG(TO_AMRISC) == 0)) { + struct vframe_s *vf; + + if (kfifo_get(&recycle_q, &vf)) { + if ((vf->index >= 0) && (vf->index < VF_BUF_NUM) + && (--vfbuf_use[vf->index] == 0)) { + WRITE_VREG(TO_AMRISC, ~(1 << vf->index)); + vf->index = VF_BUF_NUM; + } + + kfifo_put(&newframe_q, (const struct vframe_s *)vf); + } + } + + schedule_work(&set_clk_work); + + timer->expires = jiffies + PUT_INTERVAL; + + add_timer(timer); +} + +int vreal_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus) +{ + vstatus->frame_width = vreal_amstream_dec_info.width; + vstatus->frame_height = vreal_amstream_dec_info.height; + if (0 != vreal_amstream_dec_info.rate) + vstatus->frame_rate = 96000 / vreal_amstream_dec_info.rate; + else + vstatus->frame_rate = 96000; + vstatus->error_count = real_err_count; + vstatus->status = + ((READ_VREG(STATUS_AMRISC) << 16) | fatal_flag) | stat; + /* pr_info("vreal_dec_status 0x%x\n", vstatus->status); */ + return 0; +} + +int vreal_set_isreset(struct vdec_s *vdec, int isreset) +{ + is_reset = isreset; + return 0; +} + +/****************************************/ +static int vreal_canvas_init(void) +{ + int i, ret; + unsigned long buf_start; + u32 canvas_width, canvas_height; + u32 alloc_size, decbuf_size, decbuf_y_size, decbuf_uv_size; + + if (buf_size <= 0x00400000) { + /* SD only */ + canvas_width = 768; + canvas_height = 576; + decbuf_y_size = 0x80000; + decbuf_uv_size = 0x20000; + decbuf_size = 0x100000; + } else { + /* HD & SD */ + #if 1 + int w = vreal_amstream_dec_info.width; + int h = vreal_amstream_dec_info.height; + int align_w, align_h; + int max, min; + + align_w = ALIGN(w, 64); + align_h = ALIGN(h, 64); + if (align_w > align_h) { + max = align_w; + min = align_h; + } else { + canvas_width = 1920; + canvas_height = 1088; + max = align_h; + min = align_w; + } + /* HD & SD */ + if ((max > 1920 || min > 1088) && + ALIGN(align_w * align_h * 3/2, SZ_64K) * 9 <= + buf_size) { + canvas_width = align_w; + canvas_height = align_h; + decbuf_y_size = ALIGN(align_w * align_h, SZ_64K); + decbuf_uv_size = ALIGN(align_w * align_h/4, SZ_64K); + decbuf_size = ALIGN(align_w * align_h * 3/2, SZ_64K); + } else { /*1080p*/ + if (h > w) { + canvas_width = 1088; + canvas_height = 1920; + } else { + canvas_width = 1920; + canvas_height = 1088; + } + decbuf_y_size = 0x200000; + decbuf_uv_size = 0x80000; + decbuf_size = 0x300000; + } + #endif + } + + for (i = 0; i < MAX_BMMU_BUFFER_NUM; i++) { + /* workspace mem */ + if (i == (MAX_BMMU_BUFFER_NUM - 1)) + alloc_size = WORKSPACE_SIZE; + else + alloc_size = decbuf_size; + + ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, i, + alloc_size, DRIVER_NAME, &buf_start); + if (ret < 0) + return ret; + + if (i == (MAX_BMMU_BUFFER_NUM - 1)) { + buf_offset = buf_start - RV_AI_BUFF_START_IP; + continue; + } + +#ifdef NV21 + canvas_config(2 * i + 0, + buf_start, + canvas_width, canvas_height, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); + canvas_config(2 * i + 1, + buf_start + + decbuf_y_size, canvas_width, + canvas_height / 2, CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_32X32); +#else + canvas_config(3 * i + 0, + buf_start, + canvas_width, canvas_height, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); + canvas_config(3 * i + 1, + buf_start + + decbuf_y_size, canvas_width / 2, + canvas_height / 2, CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_32X32); + canvas_config(3 * i + 2, + buf_start + + decbuf_y_size + decbuf_uv_size, + canvas_width / 2, canvas_height / 2, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); +#endif + } + + return 0; +} + +static int vreal_prot_init(void) +{ + int r; +#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ + WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6)); + WRITE_VREG(DOS_SW_RESET0, 0); +#else + WRITE_RESET_REG(RESET0_REGISTER, RESET_IQIDCT | RESET_MC); +#endif + + + + r = vreal_canvas_init(); + + /* index v << 16 | u << 8 | y */ +#ifdef NV21 + WRITE_VREG(AV_SCRATCH_0, 0x010100); + WRITE_VREG(AV_SCRATCH_1, 0x030302); + WRITE_VREG(AV_SCRATCH_2, 0x050504); + WRITE_VREG(AV_SCRATCH_3, 0x070706); +#else + WRITE_VREG(AV_SCRATCH_0, 0x020100); + WRITE_VREG(AV_SCRATCH_1, 0x050403); + WRITE_VREG(AV_SCRATCH_2, 0x080706); + WRITE_VREG(AV_SCRATCH_3, 0x0b0a09); +#endif + + /* notify ucode the buffer offset */ + WRITE_VREG(AV_SCRATCH_F, buf_offset); + +#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ + WRITE_VREG(DOS_SW_RESET0, (1 << 9) | (1 << 8)); + WRITE_VREG(DOS_SW_RESET0, 0); +#else + WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK); +#endif + + /* disable PSCALE for hardware sharing */ + WRITE_VREG(PSCALE_CTRL, 0); + + WRITE_VREG(FROM_AMRISC, 0); + WRITE_VREG(TO_AMRISC, 0); + WRITE_VREG(STATUS_AMRISC, 0); + + WRITE_VREG(RV_PIC_INFO, 0); + WRITE_VREG(VPTS_TR, 0); + WRITE_VREG(VDTS, 0); + WRITE_VREG(SKIP_B_AMRISC, 0); + + WRITE_VREG(MDEC_WIDTH, (frame_width + 15) & 0xfff0); + WRITE_VREG(MDEC_HEIGHT, (frame_height + 15) & 0xfff0); + + /* clear mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + /* enable mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_MASK, 1); + + /* clear wait buffer status */ + WRITE_VREG(WAIT_BUFFER, 0); + +#ifdef NV21 + SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17); +#endif + return r; +} + +static void vreal_local_init(void) +{ + int i; + + /* vreal_ratio = vreal_amstream_dec_info.ratio; */ + vreal_ratio = 0x100; + + frame_prog = 0; + + frame_width = vreal_amstream_dec_info.width; + frame_height = vreal_amstream_dec_info.height; + frame_dur = vreal_amstream_dec_info.rate; + + for (i = 0; i < VF_BUF_NUM; i++) + vfbuf_use[i] = 0; + + INIT_KFIFO(display_q); + INIT_KFIFO(recycle_q); + INIT_KFIFO(newframe_q); + + for (i = 0; i < VF_POOL_SIZE; i++) { + const struct vframe_s *vf = &vfpool[i]; + vfpool[i].index = VF_BUF_NUM; + kfifo_put(&newframe_q, vf); + } + + if (mm_blk_handle) { + decoder_bmmu_box_free(mm_blk_handle); + mm_blk_handle = NULL; + } + + mm_blk_handle = decoder_bmmu_box_alloc_box( + DRIVER_NAME, + 0, + MAX_BMMU_BUFFER_NUM, + 4 + PAGE_SHIFT, + CODEC_MM_FLAGS_CMA_CLEAR | + CODEC_MM_FLAGS_FOR_VDECODER); + + decoder_state = 1; + hold = 0; + last_tr = -1; + wait_key_frame = 1; + frame_count = 0; + current_vdts = 0; + real_err_count = 0; + + pic_sz_tbl_map = 0; + saved_resolution = 0; + fatal_flag = 0; + wait_buffer_counter = 0; +} + +static void load_block_data(void *dest, unsigned int count) +{ + unsigned short *pdest = (unsigned short *)dest; + unsigned short src_tbl[12]; + unsigned int i; + + src_tbl[0] = RPR_size[vreal_amstream_dec_info.extra + 1]; + memcpy((void *)&src_tbl[1], vreal_amstream_dec_info.param, + 2 << src_tbl[0]); + +#if 0 + for (i = 0; i < 12; i++) + pr_info("src_tbl[%d]: 0x%x\n", i, src_tbl[i]); +#endif + + for (i = 0; i < count / 4; i++) { + pdest[i * 4] = src_tbl[i * 4 + 3]; + pdest[i * 4 + 1] = src_tbl[i * 4 + 2]; + pdest[i * 4 + 2] = src_tbl[i * 4 + 1]; + pdest[i * 4 + 3] = src_tbl[i * 4]; + } + + pic_sz_tbl_map = dma_map_single(amports_get_dma_device(), &pic_sz_tbl, + sizeof(pic_sz_tbl), DMA_TO_DEVICE); + +} + +s32 vreal_init(struct vdec_s *vdec) +{ + int ret = -1, size = -1; + char *buf = vmalloc(0x1000 * 16); + + if (IS_ERR_OR_NULL(buf)) + return -ENOMEM; + + pr_info("vreal_init\n"); + + init_timer(&recycle_timer); + + stat |= STAT_TIMER_INIT; + + amvdec_enable(); + + vreal_local_init(); + + ret = rmparser_init(vdec); + if (ret) { + amvdec_disable(); + vfree(buf); + pr_info("rm parser init failed\n"); + return ret; + } + + if (vreal_amstream_dec_info.format == VIDEO_DEC_FORMAT_REAL_8) { + if (vreal_amstream_dec_info.param == NULL) { + rmparser_release(); + amvdec_disable(); + vfree(buf); + return -1; + } + load_block_data((void *)pic_sz_tbl, 12); + + /* TODO: need to load the table into lmem */ + WRITE_VREG(LMEM_DMA_ADR, (unsigned int)pic_sz_tbl_map); + WRITE_VREG(LMEM_DMA_COUNT, 10); + WRITE_VREG(LMEM_DMA_CTRL, 0xc178 | (3 << 11)); + while (READ_VREG(LMEM_DMA_CTRL) & 0x8000) + ; + size = get_firmware_data(VIDEO_DEC_REAL_V8, buf); + + pr_info("load VIDEO_DEC_FORMAT_REAL_8\n"); + } else if (vreal_amstream_dec_info.format == VIDEO_DEC_FORMAT_REAL_9) { + size = get_firmware_data(VIDEO_DEC_REAL_V9, buf); + + pr_info("load VIDEO_DEC_FORMAT_REAL_9\n"); + } else + pr_info("unsurpported real format\n"); + + if (size < 0) { + rmparser_release(); + amvdec_disable(); + pr_err("get firmware fail."); + vfree(buf); + return -1; + } + if (size == 1) + pr_info ("tee load ok"); + else if (amvdec_loadmc_ex(VFORMAT_REAL, NULL, buf) < 0) { + rmparser_release(); + amvdec_disable(); + vfree(buf); + return -EBUSY; + } + + vfree(buf); + + stat |= STAT_MC_LOAD; + + /* enable AMRISC side protocol */ + ret = vreal_prot_init(); + if (ret < 0) { + rmparser_release(); + amvdec_disable(); + return ret; + } + if (vdec_request_irq(VDEC_IRQ_1, vreal_isr, + "vreal-irq", (void *)vreal_dec_id)) { + rmparser_release(); + amvdec_disable(); + + pr_info("vreal irq register error.\n"); + return -ENOENT; + } + + stat |= STAT_ISR_REG; +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_provider_init(&vreal_vf_prov, PROVIDER_NAME, &vreal_vf_provider, + NULL); + vf_reg_provider(&vreal_vf_prov); + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL); +#else + vf_provider_init(&vreal_vf_prov, PROVIDER_NAME, &vreal_vf_provider, + NULL); + vf_reg_provider(&vreal_vf_prov); +#endif + + if (!is_reset) + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_FR_HINT, + (void *)((unsigned long)vreal_amstream_dec_info.rate)); + + stat |= STAT_VF_HOOK; + + recycle_timer.data = (ulong)&recycle_timer; + recycle_timer.function = vreal_put_timer_func; + recycle_timer.expires = jiffies + PUT_INTERVAL; + + add_timer(&recycle_timer); + + stat |= STAT_TIMER_ARM; + + amvdec_start(); + + stat |= STAT_VDEC_RUN; + + pr_info("vreal init finished\n"); + + return 0; +} + +void vreal_set_fatal_flag(int flag) +{ + if (flag) + fatal_flag = PARSER_FATAL_ERROR; +} + +static int amvdec_real_probe(struct platform_device *pdev) +{ + struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; + + if (pdata == NULL) { + pr_info("amvdec_real memory resource undefined.\n"); + return -EFAULT; + } + if (pdata->sys_info) + vreal_amstream_dec_info = *pdata->sys_info; + + pdata->dec_status = vreal_dec_status; + pdata->set_isreset = vreal_set_isreset; + is_reset = 0; + + if (vreal_init(pdata) < 0) { + pr_info("amvdec_real init failed.\n"); + return -ENODEV; + } + INIT_WORK(&set_clk_work, vreal_set_clk); + return 0; +} + +static int amvdec_real_remove(struct platform_device *pdev) +{ + cancel_work_sync(&set_clk_work); + if (stat & STAT_VDEC_RUN) { + amvdec_stop(); + stat &= ~STAT_VDEC_RUN; + } + + if (stat & STAT_ISR_REG) { + vdec_free_irq(VDEC_IRQ_1, (void *)vreal_dec_id); + stat &= ~STAT_ISR_REG; + } + + if (stat & STAT_TIMER_ARM) { + del_timer_sync(&recycle_timer); + stat &= ~STAT_TIMER_ARM; + } + + if (stat & STAT_VF_HOOK) { + if (!is_reset) + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_FR_END_HINT, NULL); + + vf_unreg_provider(&vreal_vf_prov); + stat &= ~STAT_VF_HOOK; + } + + if (pic_sz_tbl_map != 0) { + dma_unmap_single(NULL, pic_sz_tbl_map, sizeof(pic_sz_tbl), + DMA_TO_DEVICE); + } + + rmparser_release(); + + vdec_source_changed(VFORMAT_REAL, 0, 0, 0); + + amvdec_disable(); + + if (mm_blk_handle) { + decoder_bmmu_box_free(mm_blk_handle); + mm_blk_handle = NULL; + } + pr_info("frame duration %d, frames %d\n", frame_dur, frame_count); + return 0; +} + +/****************************************/ + +static struct platform_driver amvdec_real_driver = { + .probe = amvdec_real_probe, + .remove = amvdec_real_remove, +#ifdef CONFIG_PM + .suspend = amvdec_suspend, + .resume = amvdec_resume, +#endif + .driver = { + .name = DRIVER_NAME, + } +}; + +static struct codec_profile_t amvdec_real_profile = { + .name = "real", + .profile = "rmvb,1080p+" +}; +static struct mconfig real_configs[] = { + MC_PU32("stat", &stat), +}; +static struct mconfig_node real_node; + +static int __init amvdec_real_driver_init_module(void) +{ + pr_debug("amvdec_real module init\n"); + + if (platform_driver_register(&amvdec_real_driver)) { + pr_err("failed to register amvdec_real driver\n"); + return -ENODEV; + } + vcodec_profile_register(&amvdec_real_profile); + INIT_REG_NODE_CONFIGS("media.decoder", &real_node, + "real", real_configs, CONFIG_FOR_R); + return 0; +} + +static void __exit amvdec_real_driver_remove_module(void) +{ + pr_debug("amvdec_real module remove.\n"); + + platform_driver_unregister(&amvdec_real_driver); +} + +/****************************************/ + +module_init(amvdec_real_driver_init_module); +module_exit(amvdec_real_driver_remove_module); + +MODULE_DESCRIPTION("AMLOGIC REAL Video Decoder Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/real/vreal.h b/drivers/amlogic/media_modules/frame_provider/decoder/real/vreal.h new file mode 100644 index 000000000000..734cc6f09a5a --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/real/vreal.h @@ -0,0 +1,26 @@ +/* + * drivers/amlogic/amports/vreal.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef VREAL_H +#define VREAL_H + +#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ +/* TODO: move to register headers */ +#define VPP_VD1_POSTBLEND (1 << 10) +#endif + +#endif /* VREAL_H */ diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/Makefile b/drivers/amlogic/media_modules/frame_provider/decoder/utils/Makefile new file mode 100644 index 000000000000..92eadc3e6ff2 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/Makefile @@ -0,0 +1,4 @@ +obj-m += decoder_common.o +decoder_common-objs += utils.o vdec.o vdec_input.o amvdec.o +decoder_common-objs += decoder_mmu_box.o decoder_bmmu_box.o +decoder_common-objs += config_parser.o secprot.o vdec_profile.o diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/amvdec.c b/drivers/amlogic/media_modules/frame_provider/decoder/utils/amvdec.c new file mode 100644 index 000000000000..7289fece7d21 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/amvdec.c @@ -0,0 +1,1107 @@ +/* + * drivers/amlogic/media/frame_provider/decoder/utils/amvdec.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vdec.h" + +#ifdef CONFIG_PM +#include +#endif + +#ifdef CONFIG_WAKELOCK +#include +#endif +#include "../../../stream_input/amports/amports_priv.h" + +/* #include */ +/* #include */ +#include +#include "amvdec.h" +#include +#include "firmware.h" +#include + +#define MC_SIZE (4096 * 16) + +#ifdef CONFIG_WAKELOCK +static struct wake_lock amvdec_lock; +struct timer_list amvdevtimer; +#define WAKE_CHECK_INTERVAL (100*HZ/100) +#endif +#define AMVDEC_USE_STATIC_MEMORY +static void *mc_addr; +static dma_addr_t mc_addr_map; + +#ifdef CONFIG_WAKELOCK +static int video_running; +static int video_stated_changed = 1; +#endif + +static void amvdec_pg_enable(bool enable) +{ + ulong timeout; + + if (enable) { + AMVDEC_CLK_GATE_ON(MDEC_CLK_PIC_DC); + AMVDEC_CLK_GATE_ON(MDEC_CLK_DBLK); + AMVDEC_CLK_GATE_ON(MC_CLK); + AMVDEC_CLK_GATE_ON(IQIDCT_CLK); + /* AMVDEC_CLK_GATE_ON(VLD_CLK); */ + AMVDEC_CLK_GATE_ON(AMRISC); + /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6TVD */ + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) + WRITE_VREG(GCLK_EN, 0x3ff); + /* #endif */ + CLEAR_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 31); + } else { + + AMVDEC_CLK_GATE_OFF(AMRISC); + timeout = jiffies + HZ / 10; + + while (READ_VREG(MDEC_PIC_DC_STATUS) != 0) { + if (time_after(jiffies, timeout)) { + WRITE_VREG_BITS(MDEC_PIC_DC_CTRL, 1, 0, 1); + WRITE_VREG_BITS(MDEC_PIC_DC_CTRL, 0, 0, 1); + READ_VREG(MDEC_PIC_DC_STATUS); + READ_VREG(MDEC_PIC_DC_STATUS); + READ_VREG(MDEC_PIC_DC_STATUS); + break; + } + } + + AMVDEC_CLK_GATE_OFF(MDEC_CLK_PIC_DC); + timeout = jiffies + HZ / 10; + + while (READ_VREG(DBLK_STATUS) & 1) { + if (time_after(jiffies, timeout)) { + WRITE_VREG(DBLK_CTRL, 3); + WRITE_VREG(DBLK_CTRL, 0); + READ_VREG(DBLK_STATUS); + READ_VREG(DBLK_STATUS); + READ_VREG(DBLK_STATUS); + break; + } + } + AMVDEC_CLK_GATE_OFF(MDEC_CLK_DBLK); + timeout = jiffies + HZ / 10; + + while (READ_VREG(MC_STATUS0) & 1) { + if (time_after(jiffies, timeout)) { + SET_VREG_MASK(MC_CTRL1, 0x9); + CLEAR_VREG_MASK(MC_CTRL1, 0x9); + READ_VREG(MC_STATUS0); + READ_VREG(MC_STATUS0); + READ_VREG(MC_STATUS0); + break; + } + } + AMVDEC_CLK_GATE_OFF(MC_CLK); + timeout = jiffies + HZ / 10; + while (READ_VREG(DCAC_DMA_CTRL) & 0x8000) { + if (time_after(jiffies, timeout)) + break; + } + AMVDEC_CLK_GATE_OFF(IQIDCT_CLK); + /* AMVDEC_CLK_GATE_OFF(VLD_CLK); */ + } +} + +static void amvdec2_pg_enable(bool enable) +{ + if (has_vdec2()) { + ulong timeout; + + if (!vdec_on(VDEC_2)) + return; + if (enable) { + /* WRITE_VREG(VDEC2_GCLK_EN, 0x3ff); */ + } else { + timeout = jiffies + HZ / 10; + + while (READ_VREG(VDEC2_MDEC_PIC_DC_STATUS) != 0) { + if (time_after(jiffies, timeout)) { + WRITE_VREG_BITS(VDEC2_MDEC_PIC_DC_CTRL, + 1, 0, 1); + WRITE_VREG_BITS(VDEC2_MDEC_PIC_DC_CTRL, + 0, 0, 1); + READ_VREG(VDEC2_MDEC_PIC_DC_STATUS); + READ_VREG(VDEC2_MDEC_PIC_DC_STATUS); + READ_VREG(VDEC2_MDEC_PIC_DC_STATUS); + break; + } + } + + timeout = jiffies + HZ / 10; + + while (READ_VREG(VDEC2_DBLK_STATUS) & 1) { + if (time_after(jiffies, timeout)) { + WRITE_VREG(VDEC2_DBLK_CTRL, 3); + WRITE_VREG(VDEC2_DBLK_CTRL, 0); + READ_VREG(VDEC2_DBLK_STATUS); + READ_VREG(VDEC2_DBLK_STATUS); + READ_VREG(VDEC2_DBLK_STATUS); + break; + } + } + + timeout = jiffies + HZ / 10; + + while (READ_VREG(VDEC2_DCAC_DMA_CTRL) & 0x8000) { + if (time_after(jiffies, timeout)) + break; + } + } + } +} + +static void amhevc_pg_enable(bool enable) +{ + if (has_hevc_vdec()) { + ulong timeout; + + if (!vdec_on(VDEC_HEVC)) + return; + if (enable) { + /* WRITE_VREG(VDEC2_GCLK_EN, 0x3ff); */ + } else { + timeout = jiffies + HZ / 10; + + while (READ_VREG(HEVC_MDEC_PIC_DC_STATUS) != 0) { + if (time_after(jiffies, timeout)) { + WRITE_VREG_BITS(HEVC_MDEC_PIC_DC_CTRL, + 1, 0, 1); + WRITE_VREG_BITS(HEVC_MDEC_PIC_DC_CTRL, + 0, 0, 1); + READ_VREG(HEVC_MDEC_PIC_DC_STATUS); + READ_VREG(HEVC_MDEC_PIC_DC_STATUS); + READ_VREG(HEVC_MDEC_PIC_DC_STATUS); + break; + } + } + + timeout = jiffies + HZ / 10; + + while (READ_VREG(HEVC_DBLK_STATUS) & 1) { + if (time_after(jiffies, timeout)) { + WRITE_VREG(HEVC_DBLK_CTRL, 3); + WRITE_VREG(HEVC_DBLK_CTRL, 0); + READ_VREG(HEVC_DBLK_STATUS); + READ_VREG(HEVC_DBLK_STATUS); + READ_VREG(HEVC_DBLK_STATUS); + break; + } + } + + timeout = jiffies + HZ / 10; + + while (READ_VREG(HEVC_DCAC_DMA_CTRL) & 0x8000) { + if (time_after(jiffies, timeout)) + break; + } + } + } +} + +#ifdef CONFIG_WAKELOCK +int amvdec_wake_lock(void) +{ + wake_lock(&amvdec_lock); + return 0; +} + +int amvdec_wake_unlock(void) +{ + wake_unlock(&amvdec_lock); + return 0; +} +#else +#define amvdec_wake_lock() +#define amvdec_wake_unlock() +#endif + +static s32 am_vdec_loadmc_ex(struct vdec_s *vdec, + const char *name, char *def, s32(*load)(const u32 *)) +{ + int err; + + if (!vdec->mc_loaded) { + if (!def) { + err = get_decoder_firmware_data(vdec->format, + name, (u8 *)(vdec->mc), + (4096 * 4 * 4)); + if (err <= 0) + return -1; + } else + memcpy((char *)vdec->mc, def, sizeof(vdec->mc)); + + vdec->mc_loaded = true; + } + + err = (*load)(vdec->mc); + if (err < 0) { + pr_err("loading firmware %s to vdec ram failed!\n", name); + return err; + } + pr_debug("loading firmware %s to vdec ram ok!\n", name); + return err; +} + +static s32 am_vdec_loadmc_buf_ex(struct vdec_s *vdec, + char *buf, int size, s32(*load)(const u32 *)) +{ + int err; + + if (!vdec->mc_loaded) { + memcpy((u8 *)(vdec->mc), buf, size); + vdec->mc_loaded = true; + } + + err = (*load)(vdec->mc); + if (err < 0) { + pr_err("loading firmware to vdec ram failed!\n"); + return err; + } + pr_debug("loading firmware to vdec ram ok!\n"); + return err; +} + +static s32 am_loadmc_ex(enum vformat_e type, + const char *name, char *def, s32(*load)(const u32 *)) +{ + char *mc_addr = vmalloc(4096 * 16); + char *pmc_addr = def; + int err; + + if (!def && mc_addr) { + int loaded; + + loaded = get_decoder_firmware_data(type, + name, mc_addr, (4096 * 16)); + if (loaded > 0) + pmc_addr = mc_addr; + } + if (!pmc_addr) { + vfree(mc_addr); + return -1; + } + err = (*load)((u32 *) pmc_addr); + if (err < 0) { + pr_err("loading firmware %s to vdec ram failed!\n", name); + return err; + } + vfree(mc_addr); + pr_debug("loading firmware %s to vdec ram ok!\n", name); + return err; +} + +static s32 amvdec_loadmc(const u32 *p) +{ + ulong timeout; + s32 ret = 0; + +#ifdef AMVDEC_USE_STATIC_MEMORY + if (mc_addr == NULL) { +#else + { +#endif + mc_addr = kmalloc(MC_SIZE, GFP_KERNEL); + } + + if (!mc_addr) + return -ENOMEM; + + memcpy(mc_addr, p, MC_SIZE); + + mc_addr_map = dma_map_single(get_vdec_device(), + mc_addr, MC_SIZE, DMA_TO_DEVICE); + + WRITE_VREG(MPSR, 0); + WRITE_VREG(CPSR, 0); + + /* Read CBUS register for timing */ + timeout = READ_VREG(MPSR); + timeout = READ_VREG(MPSR); + + timeout = jiffies + HZ; + + WRITE_VREG(IMEM_DMA_ADR, mc_addr_map); + WRITE_VREG(IMEM_DMA_COUNT, 0x1000); + WRITE_VREG(IMEM_DMA_CTRL, (0x8000 | (7 << 16))); + + while (READ_VREG(IMEM_DMA_CTRL) & 0x8000) { + if (time_before(jiffies, timeout)) + schedule(); + else { + pr_err("vdec load mc error\n"); + ret = -EBUSY; + break; + } + } + + dma_unmap_single(get_vdec_device(), + mc_addr_map, MC_SIZE, DMA_TO_DEVICE); + +#ifndef AMVDEC_USE_STATIC_MEMORY + kfree(mc_addr); + mc_addr = NULL; +#endif + + return ret; +} + +s32 optee_load_fw(enum vformat_e type, const char *fw_name) +{ + s32 ret = -1; + unsigned int format = FIRMWARE_MAX; + unsigned int vdec = OPTEE_VDEC_LEGENCY; + char *name = __getname(); + + sprintf(name, "%s", fw_name ? fw_name : "null"); + + switch ((u32)type) { + case VFORMAT_VC1: + format = VIDEO_DEC_VC1; + break; + + case VFORMAT_AVS: + if (!strcmp(name, "avs_no_cabac")) + format = VIDEO_DEC_AVS_NOCABAC; + else + format = VIDEO_DEC_AVS; + break; + + case VFORMAT_MPEG12: + format = VIDEO_DEC_MPEG12; + break; + + case VFORMAT_MJPEG: + format = VIDEO_DEC_MJPEG; + break; + + case VFORMAT_VP9: + if (!strcmp(name, "vp9_mc")) + format = VIDEO_DEC_VP9; + else + format = VIDEO_DEC_VP9_MMU; + break; + + case VFORMAT_AVS2: + format = VIDEO_DEC_AVS2_MMU; + vdec = OPTEE_VDEC_HEVC; + break; + + case VFORMAT_HEVC: + if (!strcmp(name, "vh265_mc")) + format = VIDEO_DEC_HEVC; + else + format = VIDEO_DEC_HEVC_MMU; + break; + + case VFORMAT_REAL: + if (!strcmp(name, "vreal_mc_8")) + format = VIDEO_DEC_REAL_V8; + else if (!strcmp(name, "vreal_mc_9")) + format = VIDEO_DEC_REAL_V9; + break; + + case VFORMAT_MPEG4: + if (!strcmp(name, "vmpeg4_mc_311")) + format = VIDEO_DEC_MPEG4_3; + else if (!strcmp(name, "vmpeg4_mc_4")) + format = VIDEO_DEC_MPEG4_4; + else if (!strcmp(name, "vmpeg4_mc_5")) + format = VIDEO_DEC_MPEG4_5; + else if (!strcmp(name, "h263_mc")) + format = VIDEO_DEC_FORMAT_H263; + break; + + default: + if (!strcmp(name, "vh265_mc")) + format = VIDEO_DEC_HEVC; + else if (!strcmp(name, "vh265_mc_mmu")) + format = VIDEO_DEC_HEVC_MMU; + else if (!strcmp(name, "vmmjpeg_mc")) + format = VIDEO_DEC_MJPEG_MULTI; + else + pr_info("unknow dec format\n"); + break; + } + + if (format < FIRMWARE_MAX) + ret = tee_load_video_fw(format, vdec); + + __putname(name); + + return ret; +} +EXPORT_SYMBOL(optee_load_fw); + +s32 amvdec_loadmc_ex(enum vformat_e type, const char *name, char *def) +{ + if (tee_enabled()) + return optee_load_fw(type, name); + else + return am_loadmc_ex(type, name, def, &amvdec_loadmc); +} +EXPORT_SYMBOL(amvdec_loadmc_ex); + +s32 amvdec_vdec_loadmc_ex(struct vdec_s *vdec, const char *name, char *def) +{ + if (tee_enabled()) + return optee_load_fw(FIRMWARE_MAX, name); + else + return am_vdec_loadmc_ex(vdec, name, def, &amvdec_loadmc); +} +EXPORT_SYMBOL(amvdec_vdec_loadmc_ex); + +s32 amvdec_vdec_loadmc_buf_ex(struct vdec_s *vdec, char *buf, int size) +{ + return am_vdec_loadmc_buf_ex(vdec, buf, size, &amvdec_loadmc); +} +EXPORT_SYMBOL(amvdec_vdec_loadmc_buf_ex); + +static s32 amvdec2_loadmc(const u32 *p) +{ + if (has_vdec2()) { + ulong timeout; + s32 ret = 0; + +#ifdef AMVDEC_USE_STATIC_MEMORY + if (mc_addr == NULL) { +#else + { +#endif + mc_addr = kmalloc(MC_SIZE, GFP_KERNEL); + } + + if (!mc_addr) + return -ENOMEM; + + memcpy(mc_addr, p, MC_SIZE); + + mc_addr_map = dma_map_single(get_vdec_device(), + mc_addr, MC_SIZE, DMA_TO_DEVICE); + + WRITE_VREG(VDEC2_MPSR, 0); + WRITE_VREG(VDEC2_CPSR, 0); + + /* Read CBUS register for timing */ + timeout = READ_VREG(VDEC2_MPSR); + timeout = READ_VREG(VDEC2_MPSR); + + timeout = jiffies + HZ; + + WRITE_VREG(VDEC2_IMEM_DMA_ADR, mc_addr_map); + WRITE_VREG(VDEC2_IMEM_DMA_COUNT, 0x1000); + WRITE_VREG(VDEC2_IMEM_DMA_CTRL, (0x8000 | (7 << 16))); + + while (READ_VREG(VDEC2_IMEM_DMA_CTRL) & 0x8000) { + if (time_before(jiffies, timeout)) + schedule(); + else { + pr_err("vdec2 load mc error\n"); + ret = -EBUSY; + break; + } + } + + dma_unmap_single(get_vdec_device(), + mc_addr_map, MC_SIZE, DMA_TO_DEVICE); + +#ifndef AMVDEC_USE_STATIC_MEMORY + kfree(mc_addr); + mc_addr = NULL; +#endif + + return ret; + } else + return 0; +} + +s32 amvdec2_loadmc_ex(enum vformat_e type, const char *name, char *def) +{ + if (has_vdec2()) + return am_loadmc_ex(type, name, def, &amvdec2_loadmc); + else + return 0; +} +EXPORT_SYMBOL(amvdec2_loadmc_ex); + +s32 amhcodec_loadmc(const u32 *p) +{ +#ifdef AMVDEC_USE_STATIC_MEMORY + if (mc_addr == NULL) { +#else + { +#endif + mc_addr = kmalloc(MC_SIZE, GFP_KERNEL); + } + + if (!mc_addr) + return -ENOMEM; + + memcpy(mc_addr, p, MC_SIZE); + + mc_addr_map = dma_map_single(get_vdec_device(), + mc_addr, MC_SIZE, DMA_TO_DEVICE); + + WRITE_VREG(HCODEC_IMEM_DMA_ADR, mc_addr_map); + WRITE_VREG(HCODEC_IMEM_DMA_COUNT, 0x100); + WRITE_VREG(HCODEC_IMEM_DMA_CTRL, (0x8000 | (7 << 16))); + + while (READ_VREG(HCODEC_IMEM_DMA_CTRL) & 0x8000) + udelay(1000); + + dma_unmap_single(get_vdec_device(), + mc_addr_map, MC_SIZE, DMA_TO_DEVICE); + +#ifndef AMVDEC_USE_STATIC_MEMORY + kfree(mc_addr); +#endif + + return 0; +} +EXPORT_SYMBOL(amhcodec_loadmc); + +s32 amhcodec_loadmc_ex(enum vformat_e type, const char *name, char *def) +{ + return am_loadmc_ex(type, name, def, &amhcodec_loadmc); +} +EXPORT_SYMBOL(amhcodec_loadmc_ex); + +static s32 amhevc_loadmc(const u32 *p) +{ + ulong timeout; + s32 ret = 0; + + if (has_hevc_vdec()) { +#ifdef AMVDEC_USE_STATIC_MEMORY + if (mc_addr == NULL) { +#else + { +#endif + mc_addr = kmalloc(MC_SIZE, GFP_KERNEL); + } + + if (!mc_addr) + return -ENOMEM; + + memcpy(mc_addr, p, MC_SIZE); + + mc_addr_map = + dma_map_single(get_vdec_device(), + mc_addr, MC_SIZE, DMA_TO_DEVICE); + + WRITE_VREG(HEVC_MPSR, 0); + WRITE_VREG(HEVC_CPSR, 0); + + /* Read CBUS register for timing */ + timeout = READ_VREG(HEVC_MPSR); + timeout = READ_VREG(HEVC_MPSR); + + timeout = jiffies + HZ; + + WRITE_VREG(HEVC_IMEM_DMA_ADR, mc_addr_map); + WRITE_VREG(HEVC_IMEM_DMA_COUNT, 0x1000); + WRITE_VREG(HEVC_IMEM_DMA_CTRL, (0x8000 | (7 << 16))); + + while (READ_VREG(HEVC_IMEM_DMA_CTRL) & 0x8000) { + if (time_before(jiffies, timeout)) + schedule(); + else { + pr_err("vdec2 load mc error\n"); + ret = -EBUSY; + break; + } + } + + dma_unmap_single(get_vdec_device(), + mc_addr_map, MC_SIZE, DMA_TO_DEVICE); + +#ifndef AMVDEC_USE_STATIC_MEMORY + kfree(mc_addr); + mc_addr = NULL; +#endif + } + + return ret; +} + +s32 amhevc_loadmc_ex(enum vformat_e type, const char *name, char *def) +{ + if (has_hevc_vdec()) + if (tee_enabled()) + return optee_load_fw(type, name); + else + return am_loadmc_ex(type, name, def, &amhevc_loadmc); + else + return 0; +} +EXPORT_SYMBOL(amhevc_loadmc_ex); + +s32 amhevc_vdec_loadmc_ex(struct vdec_s *vdec, const char *name, char *def) +{ + if (has_hevc_vdec()) + if (tee_enabled()) + return optee_load_fw(FIRMWARE_MAX, name); + else + return am_vdec_loadmc_ex(vdec, name, def, &amhevc_loadmc); + else + return 0; +} +EXPORT_SYMBOL(amhevc_vdec_loadmc_ex); + +void amvdec_start(void) +{ +#ifdef CONFIG_WAKELOCK + amvdec_wake_lock(); +#endif + + /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M6) { + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + + WRITE_VREG(DOS_SW_RESET0, (1 << 12) | (1 << 11)); + WRITE_VREG(DOS_SW_RESET0, 0); + + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + } else { + /* #else */ + /* additional cbus dummy register reading for timing control */ + READ_RESET_REG(RESET0_REGISTER); + READ_RESET_REG(RESET0_REGISTER); + READ_RESET_REG(RESET0_REGISTER); + READ_RESET_REG(RESET0_REGISTER); + + WRITE_RESET_REG(RESET0_REGISTER, RESET_VCPU | RESET_CCPU); + + READ_RESET_REG(RESET0_REGISTER); + READ_RESET_REG(RESET0_REGISTER); + READ_RESET_REG(RESET0_REGISTER); + } + /* #endif */ + + WRITE_VREG(MPSR, 0x0001); +} +EXPORT_SYMBOL(amvdec_start); + +void amvdec2_start(void) +{ + if (has_vdec2()) { +#ifdef CONFIG_WAKELOCK + amvdec_wake_lock(); +#endif + + READ_VREG(DOS_SW_RESET2); + READ_VREG(DOS_SW_RESET2); + READ_VREG(DOS_SW_RESET2); + + WRITE_VREG(DOS_SW_RESET2, (1 << 12) | (1 << 11)); + WRITE_VREG(DOS_SW_RESET2, 0); + + READ_VREG(DOS_SW_RESET2); + READ_VREG(DOS_SW_RESET2); + READ_VREG(DOS_SW_RESET2); + + WRITE_VREG(VDEC2_MPSR, 0x0001); + } +} +EXPORT_SYMBOL(amvdec2_start); + +void amhcodec_start(void) +{ + WRITE_VREG(HCODEC_MPSR, 0x0001); +} +EXPORT_SYMBOL(amhcodec_start); + +void amhevc_start(void) +{ + + if (has_hevc_vdec()) { +#ifdef CONFIG_WAKELOCK + amvdec_wake_lock(); +#endif + + READ_VREG(DOS_SW_RESET3); + READ_VREG(DOS_SW_RESET3); + READ_VREG(DOS_SW_RESET3); + + WRITE_VREG(DOS_SW_RESET3, (1 << 12) | (1 << 11)); + WRITE_VREG(DOS_SW_RESET3, 0); + + READ_VREG(DOS_SW_RESET3); + READ_VREG(DOS_SW_RESET3); + READ_VREG(DOS_SW_RESET3); + + WRITE_VREG(HEVC_MPSR, 0x0001); + } +} +EXPORT_SYMBOL(amhevc_start); + +void amvdec_stop(void) +{ + ulong timeout = jiffies + HZ; + + WRITE_VREG(MPSR, 0); + WRITE_VREG(CPSR, 0); + + while (READ_VREG(IMEM_DMA_CTRL) & 0x8000) { + if (time_after(jiffies, timeout)) + break; + } + + /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M6) { + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + + WRITE_VREG(DOS_SW_RESET0, (1 << 12) | (1 << 11)); + WRITE_VREG(DOS_SW_RESET0, 0); + + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + READ_VREG(DOS_SW_RESET0); + } else { + /* #else */ + WRITE_RESET_REG(RESET0_REGISTER, RESET_VCPU | RESET_CCPU); + + /* additional cbus dummy register reading for timing control */ + READ_RESET_REG(RESET0_REGISTER); + READ_RESET_REG(RESET0_REGISTER); + READ_RESET_REG(RESET0_REGISTER); + READ_RESET_REG(RESET0_REGISTER); + } + /* #endif */ + +#ifdef CONFIG_WAKELOCK + amvdec_wake_unlock(); +#endif +} +EXPORT_SYMBOL(amvdec_stop); + +void amvdec2_stop(void) +{ + if (has_vdec2()) { + ulong timeout = jiffies + HZ; + + WRITE_VREG(VDEC2_MPSR, 0); + WRITE_VREG(VDEC2_CPSR, 0); + + while (READ_VREG(VDEC2_IMEM_DMA_CTRL) & 0x8000) { + if (time_after(jiffies, timeout)) + break; + } + + READ_VREG(DOS_SW_RESET2); + READ_VREG(DOS_SW_RESET2); + READ_VREG(DOS_SW_RESET2); + +#ifdef CONFIG_WAKELOCK + amvdec_wake_unlock(); +#endif + } +} +EXPORT_SYMBOL(amvdec2_stop); + +void amhcodec_stop(void) +{ + WRITE_VREG(HCODEC_MPSR, 0); +} +EXPORT_SYMBOL(amhcodec_stop); + +void amhevc_stop(void) +{ + if (has_hevc_vdec()) { + ulong timeout = jiffies + HZ; + + WRITE_VREG(HEVC_MPSR, 0); + WRITE_VREG(HEVC_CPSR, 0); + + while (READ_VREG(HEVC_IMEM_DMA_CTRL) & 0x8000) { + if (time_after(jiffies, timeout)) + break; + } + + READ_VREG(DOS_SW_RESET3); + READ_VREG(DOS_SW_RESET3); + READ_VREG(DOS_SW_RESET3); + +#ifdef CONFIG_WAKELOCK + amvdec_wake_unlock(); +#endif + } +} +EXPORT_SYMBOL(amhevc_stop); + +void amvdec_enable(void) +{ + amvdec_pg_enable(true); +} +EXPORT_SYMBOL(amvdec_enable); + +void amvdec_disable(void) +{ + amvdec_pg_enable(false); +} +EXPORT_SYMBOL(amvdec_disable); + +void amvdec2_enable(void) +{ + if (has_vdec2()) + amvdec2_pg_enable(true); +} +EXPORT_SYMBOL(amvdec2_enable); + +void amvdec2_disable(void) +{ + if (has_vdec2()) + amvdec2_pg_enable(false); +} +EXPORT_SYMBOL(amvdec2_disable); + +void amhevc_enable(void) +{ + if (has_hevc_vdec()) + amhevc_pg_enable(true); +} +EXPORT_SYMBOL(amhevc_enable); + +void amhevc_disable(void) +{ + if (has_hevc_vdec()) + amhevc_pg_enable(false); +} +EXPORT_SYMBOL(amhevc_disable); + +#ifdef CONFIG_PM +int amvdec_suspend(struct platform_device *dev, pm_message_t event) +{ + amvdec_pg_enable(false); + + /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6TVD */ + if (has_vdec2()) + amvdec2_pg_enable(false); + /* #endif */ + + if (has_hevc_vdec()) + amhevc_pg_enable(false); + /*vdec_set_suspend_clk(1, 0);*//*DEBUG_TMP*/ + return 0; +} +EXPORT_SYMBOL(amvdec_suspend); + +int amvdec_resume(struct platform_device *dev) +{ + amvdec_pg_enable(true); + + /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6TVD */ + if (has_vdec2()) + amvdec2_pg_enable(true); + /* #endif */ + + /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ + if (has_hevc_vdec()) + amhevc_pg_enable(true); + /* #endif */ + /*vdec_set_suspend_clk(0, 0);*//*DEBUG_TMP*/ + return 0; +} +EXPORT_SYMBOL(amvdec_resume); + +int amhevc_suspend(struct platform_device *dev, pm_message_t event) +{ + if (has_hevc_vdec()) { + amhevc_pg_enable(false); + /*vdec_set_suspend_clk(1, 1);*//*DEBUG_TMP*/ + } + return 0; +} +EXPORT_SYMBOL(amhevc_suspend); + +int amhevc_resume(struct platform_device *dev) +{ + if (has_hevc_vdec()) { + amhevc_pg_enable(true); + /*vdec_set_suspend_clk(0, 1);*//*DEBUG_TMP*/ + } + return 0; +} +EXPORT_SYMBOL(amhevc_resume); + + +#endif + +#ifdef CONFIG_WAKELOCK + +static int vdec_is_paused(void) +{ + static unsigned long old_wp = -1, old_rp = -1, old_level = -1; + unsigned long wp, rp, level; + static int paused_time; + + /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ + if (has_hevc_vdec()) { + if ((vdec_on(VDEC_HEVC)) + && (READ_VREG(HEVC_STREAM_CONTROL) & 1)) { + wp = READ_VREG(HEVC_STREAM_WR_PTR); + rp = READ_VREG(HEVC_STREAM_RD_PTR); + level = READ_VREG(HEVC_STREAM_LEVEL); + } else { + wp = READ_VREG(VLD_MEM_VIFIFO_WP); + rp = READ_VREG(VLD_MEM_VIFIFO_RP); + level = READ_VREG(VLD_MEM_VIFIFO_LEVEL); + } + } else + /* #endif */ + { + wp = READ_VREG(VLD_MEM_VIFIFO_WP); + rp = READ_VREG(VLD_MEM_VIFIFO_RP); + level = READ_VREG(VLD_MEM_VIFIFO_LEVEL); + } + /*have data,but output buffer is full */ + if ((rp == old_rp && level > 1024) || + (rp == old_rp && wp == old_wp && level == old_level)) { + /*no write && not read */ + paused_time++; + } else { + paused_time = 0; + } + old_wp = wp; old_rp = rp; old_level = level; + if (paused_time > 10) + return 1; + return 0; +} + +int amvdev_pause(void) +{ + video_running = 0; + video_stated_changed = 1; + return 0; +} +EXPORT_SYMBOL(amvdev_pause); + +int amvdev_resume(void) +{ + video_running = 1; + video_stated_changed = 1; + return 0; +} +EXPORT_SYMBOL(amvdev_resume); + +static void vdec_paused_check_timer(unsigned long arg) +{ + if (video_stated_changed) { + if (!video_running) { + if (vdec_is_paused()) { + pr_info("vdec paused and release wakelock now\n"); + amvdec_wake_unlock(); + video_stated_changed = 0; + } + } else { + amvdec_wake_lock(); + video_stated_changed = 0; + } + } + mod_timer(&amvdevtimer, jiffies + WAKE_CHECK_INTERVAL); +} +#else +int amvdev_pause(void) +{ + return 0; +} + +int amvdev_resume(void) +{ + return 0; +} +#endif + +int amvdec_init(void) +{ +#ifdef CONFIG_WAKELOCK + /* + *wake_lock_init(&amvdec_lock, WAKE_LOCK_IDLE, "amvdec_lock"); + *tmp mark for compile, no "WAKE_LOCK_IDLE" definition in kernel 3.8 + */ + wake_lock_init(&amvdec_lock, /*WAKE_LOCK_IDLE */ WAKE_LOCK_SUSPEND, + "amvdec_lock"); + + init_timer(&amvdevtimer); + + amvdevtimer.data = (ulong) &amvdevtimer; + amvdevtimer.function = vdec_paused_check_timer; +#endif + return 0; +} +EXPORT_SYMBOL(amvdec_init); + +void amvdec_exit(void) +{ +#ifdef CONFIG_WAKELOCK + del_timer_sync(&amvdevtimer); +#endif +} +EXPORT_SYMBOL(amvdec_exit); + +#if 0 +int __init amvdec_init(void) +{ +#ifdef CONFIG_WAKELOCK + /* + *wake_lock_init(&amvdec_lock, WAKE_LOCK_IDLE, "amvdec_lock"); + *tmp mark for compile, no "WAKE_LOCK_IDLE" definition in kernel 3.8 + */ + wake_lock_init(&amvdec_lock, /*WAKE_LOCK_IDLE */ WAKE_LOCK_SUSPEND, + "amvdec_lock"); + + init_timer(&amvdevtimer); + + amvdevtimer.data = (ulong) &amvdevtimer; + amvdevtimer.function = vdec_paused_check_timer; +#endif + return 0; +} + +static void __exit amvdec_exit(void) +{ +#ifdef CONFIG_WAKELOCK + del_timer_sync(&amvdevtimer); +#endif +} + +module_init(amvdec_init); +module_exit(amvdec_exit); +#endif + +MODULE_DESCRIPTION("Amlogic Video Decoder Utility Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Tim Yao "); diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/amvdec.h b/drivers/amlogic/media_modules/frame_provider/decoder/utils/amvdec.h new file mode 100644 index 000000000000..8a269ad977ab --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/amvdec.h @@ -0,0 +1,88 @@ +/* + * drivers/amlogic/media/frame_provider/decoder/utils/amvdec.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef AMVDEC_H +#define AMVDEC_H +#include +#include +#include "vdec.h" + +#define UCODE_ALIGN 8 +#define UCODE_ALIGN_MASK 7UL + +struct amvdec_dec_reg_s { + unsigned long mem_start; + unsigned long mem_end; + struct device *cma_dev; + struct dec_sysinfo *dec_sysinfo; +}; /*amvdec_dec_reg_t */ + +struct vdec_s; + +extern void amvdec_start(void); +extern void amvdec_stop(void); +extern void amvdec_enable(void); +extern void amvdec_disable(void); +s32 amvdec_loadmc_ex(enum vformat_e type, const char *name, char *def); +s32 amvdec_vdec_loadmc_ex(struct vdec_s *vdec, const char *name, char *def); + +extern void amvdec2_start(void); +extern void amvdec2_stop(void); +extern void amvdec2_enable(void); +extern void amvdec2_disable(void); +s32 amvdec2_loadmc_ex(enum vformat_e type, const char *name, char *def); + +extern void amhevc_start(void); +extern void amhevc_stop(void); +extern void amhevc_enable(void); +extern void amhevc_disable(void); +s32 amhevc_loadmc_ex(enum vformat_e type, const char *name, char *def); +s32 amhevc_vdec_loadmc_ex(struct vdec_s *vdec, const char *name, char *def); +s32 amvdec_vdec_loadmc_buf_ex(struct vdec_s *vdec, char *buf, int size); + +extern void amhcodec_start(void); +extern void amhcodec_stop(void); +s32 amhcodec_loadmc(const u32 *p); +s32 amhcodec_loadmc_ex(enum vformat_e type, const char *name, char *def); + +extern int amvdev_pause(void); +extern int amvdev_resume(void); + +#ifdef CONFIG_PM +extern int amvdec_suspend(struct platform_device *dev, pm_message_t event); +extern int amvdec_resume(struct platform_device *dec); +extern int amhevc_suspend(struct platform_device *dev, pm_message_t event); +extern int amhevc_resume(struct platform_device *dec); + +#endif + +int amvdec_init(void); +void amvdec_exit(void); + +#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ +#define AMVDEC_CLK_GATE_ON(a) +#define AMVDEC_CLK_GATE_OFF(a) +#else +#define AMVDEC_CLK_GATE_ON(a) CLK_GATE_ON(a) +#define AMVDEC_CLK_GATE_OFF(a) CLK_GATE_OFF(a) +#endif + +/* TODO: move to register headers */ +#define RESET_VCPU (1<<7) +#define RESET_CCPU (1<<8) + +#endif /* AMVDEC_H */ diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/config_parser.c b/drivers/amlogic/media_modules/frame_provider/decoder/utils/config_parser.c new file mode 100644 index 000000000000..9a65620795aa --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/config_parser.c @@ -0,0 +1,64 @@ +/* + * drivers/amlogic/amports/config_parser.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#include +#include +#include +#include + +#include "config_parser.h" +/* + *sample config: + *configs: width:1920;height:1080; + *need:width + *ok: return 0; + **val = value; + */ +int get_config_int(const char *configs, const char *need, int *val) +{ + const char *str; + int ret; + int lval = 0; + *val = 0; + + if (!configs || !need) + return -1; + str = strstr(configs, need); + if (str != NULL) { + if (str > configs && str[-1] != ';') { + /* + * if not the first config val. + * make sure before is ';' + * to recognize: + * ;crop_width:100 + * ;width:100 + */ + return -2; + } + str += strlen(need); + if (str[0] != ':' || str[1] == '\0') + return -3; + ret = sscanf(str, ":%d", &lval); + if (ret == 1) { + *val = lval; + return 0; + } + } + + return -4; +} +EXPORT_SYMBOL(get_config_int); + diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/config_parser.h b/drivers/amlogic/media_modules/frame_provider/decoder/utils/config_parser.h new file mode 100644 index 000000000000..9746cafdb59e --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/config_parser.h @@ -0,0 +1,21 @@ +/* + * drivers/amlogic/amports/config_parser.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#ifndef CONFIG_PARSER_HHH_ +#define CONFIG_PARSER_HHH_ +int get_config_int(const char *configs, const char *need, int *val); + +#endif/*CONFIG_PARSER_HHH_*/ diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/decoder_bmmu_box.c b/drivers/amlogic/media_modules/frame_provider/decoder/utils/decoder_bmmu_box.c new file mode 100644 index 000000000000..fe00832b061c --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/decoder_bmmu_box.c @@ -0,0 +1,536 @@ +/* + * drivers/amlogic/amports/decoder/decoder_bmmu_box.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "decoder_bmmu_box.h" +#include + +struct decoder_bmmu_box { + int max_mm_num; + const char *name; + int channel_id; + struct mutex mutex; + struct list_head list; + int total_size; + int change_size_on_need_smaller; + int align2n; /*can overwite on idx alloc */ + int mem_flags; /*can overwite on idx alloc */ + struct codec_mm_s *mm_list[1]; +}; + +struct decoder_bmmu_box_mgr { + int num; + struct mutex mutex; + struct list_head box_list; +}; +static struct decoder_bmmu_box_mgr global_blk_mgr; +static struct decoder_bmmu_box_mgr *get_decoder_bmmu_box_mgr(void) +{ + return &global_blk_mgr; +} + +static int decoder_bmmu_box_mgr_add_box(struct decoder_bmmu_box *box) +{ + struct decoder_bmmu_box_mgr *mgr = get_decoder_bmmu_box_mgr(); + + mutex_lock(&mgr->mutex); + list_add_tail(&box->list, &mgr->box_list); + mutex_unlock(&mgr->mutex); + return 0; +} + +static int decoder_bmmu_box_mgr_del_box(struct decoder_bmmu_box *box) +{ + struct decoder_bmmu_box_mgr *mgr = get_decoder_bmmu_box_mgr(); + + mutex_lock(&mgr->mutex); + list_del(&box->list); + mutex_unlock(&mgr->mutex); + return 0; +} + +void *decoder_bmmu_box_alloc_box(const char *name, + int channel_id, int max_num, + int aligned, int mem_flags) +/*min_size_M:wait alloc this size*/ +{ + struct decoder_bmmu_box *box; + int size; + int tvp_flags; + tvp_flags = (mem_flags & CODEC_MM_FLAGS_TVP) ? + CODEC_MM_FLAGS_TVP : 0; + + pr_debug("decoder_bmmu_box_alloc_box, tvp_flags = %x\n", tvp_flags); + + size = sizeof(struct decoder_bmmu_box) + sizeof(struct codec_mm_s *) * + max_num; + box = kmalloc(size, GFP_KERNEL); + if (!box) { + pr_err("can't alloc decoder buffers box!!!\n"); + return NULL; + } + memset(box, 0, size); + box->max_mm_num = max_num; + box->name = name; + box->channel_id = channel_id; + box->align2n = aligned; + box->mem_flags = mem_flags | tvp_flags; + mutex_init(&box->mutex); + INIT_LIST_HEAD(&box->list); + decoder_bmmu_box_mgr_add_box(box); + return (void *)box; +} +EXPORT_SYMBOL(decoder_bmmu_box_alloc_box); + +int decoder_bmmu_box_alloc_idx(void *handle, int idx, int size, int aligned_2n, + int mem_flags) +/*align& flags if -1 user box default.*/ +{ + struct decoder_bmmu_box *box = handle; + struct codec_mm_s *mm; + int align = aligned_2n; + int memflags = mem_flags; + + if (!box || idx < 0 || idx >= box->max_mm_num) { + pr_err("can't alloc mmu box(%p),idx:%d\n", + box, idx); + return -1; + } + if (align == -1) + align = box->align2n; + if (memflags == -1) + memflags = box->mem_flags; + + mutex_lock(&box->mutex); + mm = box->mm_list[idx]; + if (mm) { + int invalid = 0; + + if (mm->page_count * PAGE_SIZE < size) { + /*size is small. */ + invalid = 1; + } else if (box->change_size_on_need_smaller && + (mm->buffer_size > (size << 1))) { + /*size is too large. */ + invalid = 2; + } else if (mm->phy_addr & ((1 << align) - 1)) { + /*addr is not align */ + invalid = 4; + } + if (invalid) { + box->total_size -= mm->buffer_size; + codec_mm_release(mm, box->name); + box->mm_list[idx] = NULL; + mm = NULL; + } + } + if (!mm) { + mm = codec_mm_alloc(box->name, size, align, memflags); + if (mm) { + box->mm_list[idx] = mm; + box->total_size += mm->buffer_size; + mm->ins_id = box->channel_id; + mm->ins_buffer_id = idx; + } + } + mutex_unlock(&box->mutex); + return mm ? 0 : -ENOMEM; +} + +int decoder_bmmu_box_free_idx(void *handle, int idx) +{ + struct decoder_bmmu_box *box = handle; + struct codec_mm_s *mm; + + if (!box || idx < 0 || idx >= box->max_mm_num) { + pr_err("can't free idx of box(%p),idx:%d in (%d-%d)\n", + box, idx, 0, + box->max_mm_num - 1); + return -1; + } + mutex_lock(&box->mutex); + mm = box->mm_list[idx]; + if (mm) { + box->total_size -= mm->buffer_size; + codec_mm_release(mm, box->name); + box->mm_list[idx] = NULL; + mm = NULL; + } + mutex_unlock(&box->mutex); + return 0; +} +EXPORT_SYMBOL(decoder_bmmu_box_free_idx); + +int decoder_bmmu_box_free(void *handle) +{ + struct decoder_bmmu_box *box = handle; + struct codec_mm_s *mm; + int i; + + if (!box) { + pr_err("can't free box of NULL box!\n"); + return -1; + } + mutex_lock(&box->mutex); + for (i = 0; i < box->max_mm_num; i++) { + mm = box->mm_list[i]; + if (mm) { + codec_mm_release(mm, box->name); + box->mm_list[i] = NULL; + } + } + mutex_unlock(&box->mutex); + decoder_bmmu_box_mgr_del_box(box); + kfree(box); + return 0; +} +EXPORT_SYMBOL(decoder_bmmu_box_free); + +void *decoder_bmmu_box_get_mem_handle(void *box_handle, int idx) +{ + struct decoder_bmmu_box *box = box_handle; + + if (!box || idx < 0 || idx >= box->max_mm_num) + return NULL; + return box->mm_list[idx]; +} +EXPORT_SYMBOL(decoder_bmmu_box_get_mem_handle); + +int decoder_bmmu_box_get_mem_size(void *box_handle, int idx) +{ + struct decoder_bmmu_box *box = box_handle; + int size = 0; + + if (!box || idx < 0 || idx >= box->max_mm_num) + return 0; + mutex_lock(&box->mutex); + if (box->mm_list[idx] != NULL) + size = box->mm_list[idx]->buffer_size; + mutex_unlock(&box->mutex); + return size; +} + + +unsigned long decoder_bmmu_box_get_phy_addr(void *box_handle, int idx) +{ + struct decoder_bmmu_box *box = box_handle; + struct codec_mm_s *mm; + + if (!box || idx < 0 || idx >= box->max_mm_num) + return 0; + mm = box->mm_list[idx]; + if (!mm) + return 0; + return mm->phy_addr; +} +EXPORT_SYMBOL(decoder_bmmu_box_get_phy_addr); + +void *decoder_bmmu_box_get_virt_addr(void *box_handle, int idx) +{ + struct decoder_bmmu_box *box = box_handle; + struct codec_mm_s *mm; + + if (!box || idx < 0 || idx >= box->max_mm_num) + return NULL; + mm = box->mm_list[idx]; + if (!mm) + return 0; + return codec_mm_phys_to_virt(mm->phy_addr); +} + +/*flags: &0x1 for wait,*/ +int decoder_bmmu_box_check_and_wait_size(int size, int flags) +{ + if ((flags & BMMU_ALLOC_FLAGS_CAN_CLEAR_KEEPER) && + codec_mm_get_free_size() < size) { + pr_err("CMA force free keep,for size = %d\n", size); + /*need free others? + */ + try_free_keep_video(1); + } + + return codec_mm_enough_for_size(size, + flags & BMMU_ALLOC_FLAGS_WAIT); +} + +int decoder_bmmu_box_alloc_idx_wait( + void *handle, int idx, + int size, int aligned_2n, + int mem_flags, + int wait_flags) +{ + int have_space; + int ret = -1; + + if (decoder_bmmu_box_get_mem_size(handle, idx) >= size) + return 0;/*have alloced memery before.*/ + have_space = decoder_bmmu_box_check_and_wait_size( + size, + wait_flags); + if (have_space) { + ret = decoder_bmmu_box_alloc_idx(handle, + idx, size, aligned_2n, mem_flags); + } else { + try_free_keep_video(1); + ret = -ENOMEM; + } + return ret; +} +EXPORT_SYMBOL(decoder_bmmu_box_alloc_idx_wait); + +int decoder_bmmu_box_alloc_buf_phy( + void *handle, int idx, + int size, unsigned char *driver_name, + unsigned long *buf_phy_addr) +{ + if (!decoder_bmmu_box_check_and_wait_size( + size, + 1)) { + pr_info("%s not enough buf for buf_idx = %d\n", + driver_name, idx); + return -ENOMEM; + } + if (!decoder_bmmu_box_alloc_idx_wait( + handle, + idx, + size, + -1, + -1, + BMMU_ALLOC_FLAGS_WAITCLEAR + )) { + *buf_phy_addr = + decoder_bmmu_box_get_phy_addr( + handle, + idx); + /* + *pr_info("%s malloc buf_idx = %d addr = %ld size = %d\n", + * driver_name, idx, *buf_phy_addr, size); + */ + } else { + pr_info("%s malloc failed %d\n", driver_name, idx); + return -ENOMEM; + } + + return 0; +} +EXPORT_SYMBOL(decoder_bmmu_box_alloc_buf_phy); + +static int decoder_bmmu_box_dump(struct decoder_bmmu_box *box, void *buf, + int size) +{ + char *pbuf = buf; + char sbuf[512]; + int tsize = 0; + int s; + int i; + if (!buf) { + pbuf = sbuf; + size = 100000; + } +#define BUFPRINT(args...) \ + do {\ + s = snprintf(pbuf, size - tsize, args);\ + tsize += s;\ + pbuf += s; \ + } while (0) + + for (i = 0; i < box->max_mm_num; i++) { + struct codec_mm_s *mm = box->mm_list[i]; + if (buf && (size - tsize) < 256) { + BUFPRINT("\n\t**NOT END**\n"); + break; + } + if (mm) { + BUFPRINT("code mem[%d]:%p, addr=%p, size=%d,from=%d\n", + i, + (void *)mm, + (void *)mm->phy_addr, + mm->buffer_size, + mm->from_flags); + if (!buf) { + pr_info("%s", sbuf); + pbuf = sbuf; + } + } + } +#undef BUFPRINT + + return tsize; +} + +static int decoder_bmmu_box_dump_all(void *buf, int size) +{ + struct decoder_bmmu_box_mgr *mgr = get_decoder_bmmu_box_mgr(); + char *pbuf = buf; + char sbuf[512]; + int tsize = 0; + int s; + int i; + struct list_head *head, *list; + if (!buf) { + pbuf = sbuf; + size = 100000; + } +#define BUFPRINT(args...) \ + do {\ + s = snprintf(pbuf, size - tsize, args);\ + tsize += s;\ + pbuf += s; \ + } while (0) + + mutex_lock(&mgr->mutex); + head = &mgr->box_list; + list = head->next; + i = 0; + while (list != head) { + struct decoder_bmmu_box *box; + + box = list_entry(list, struct decoder_bmmu_box, list); + BUFPRINT("box[%d]: %s, %splayer_id:%d, max_num:%d, size:%d\n", + i, box->name, + (box->mem_flags & CODEC_MM_FLAGS_TVP) ? + "TVP mode " : "", + box->channel_id, + box->max_mm_num, + box->total_size); + if (buf) { + s = decoder_bmmu_box_dump(box, pbuf, size - tsize); + if (s > 0) { + tsize += s; + pbuf += s; + } + } else { + pr_info("%s", sbuf); + pbuf = sbuf; + tsize += decoder_bmmu_box_dump(box, NULL, 0); + } + list = list->next; + i++; + } + mutex_unlock(&mgr->mutex); + +#undef BUFPRINT + if (!buf) + pr_info("%s", sbuf); + return tsize; +} + +static ssize_t box_dump_show(struct class *class, struct class_attribute *attr, + char *buf) +{ + ssize_t ret = 0; + + ret = decoder_bmmu_box_dump_all(buf, PAGE_SIZE); + return ret; +} + +static ssize_t box_debug_show(struct class *class, + struct class_attribute *attr, + char *buf) +{ + ssize_t size = 0; + size += sprintf(buf, "box debug help:\n"); + size += sprintf(buf + size, "echo n > debug\n"); + size += sprintf(buf + size, "n==0: clear all debugs)\n"); + size += sprintf(buf + size, + "n=1: dump all box\n"); + + return size; +} + + +static ssize_t box_debug_store(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size) +{ + unsigned val; + ssize_t ret; + val = -1; + ret = sscanf(buf, "%d", &val); + if (ret != 1) + return -EINVAL; + switch (val) { + case 1: + decoder_bmmu_box_dump_all(NULL , 0); + break; + default: + pr_err("unknow cmd! %d\n", val); + } + return size; + +} + + + +static struct class_attribute decoder_bmmu_box_class_attrs[] = { + __ATTR_RO(box_dump), + __ATTR(debug, S_IRUGO | S_IWUSR | S_IWGRP, + box_debug_show, box_debug_store), + __ATTR_NULL +}; + +static struct class decoder_bmmu_box_class = { + .name = "decoder_bmmu_box", + .class_attrs = decoder_bmmu_box_class_attrs, + }; + +int decoder_bmmu_box_init(void) +{ + int r; + + memset(&global_blk_mgr, 0, sizeof(global_blk_mgr)); + INIT_LIST_HEAD(&global_blk_mgr.box_list); + mutex_init(&global_blk_mgr.mutex); + r = class_register(&decoder_bmmu_box_class); + return r; +} +EXPORT_SYMBOL(decoder_bmmu_box_init); + +void decoder_bmmu_box_exit(void) +{ + class_unregister(&decoder_bmmu_box_class); + pr_info("dec bmmu box exit.\n"); +} + +#if 0 +static int __init decoder_bmmu_box_init(void) +{ + int r; + + memset(&global_blk_mgr, 0, sizeof(global_blk_mgr)); + INIT_LIST_HEAD(&global_blk_mgr.box_list); + mutex_init(&global_blk_mgr.mutex); + r = class_register(&decoder_bmmu_box_class); + return r; +} + +module_init(decoder_bmmu_box_init); +#endif diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/decoder_bmmu_box.h b/drivers/amlogic/media_modules/frame_provider/decoder/utils/decoder_bmmu_box.h new file mode 100644 index 000000000000..8744da147cef --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/decoder_bmmu_box.h @@ -0,0 +1,67 @@ +/* + * drivers/amlogic/amports/decoder/decoder_bmmu_box.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef DECODER_BLOCK_BUFFER_BOX +#define DECODER_BLOCK_BUFFER_BOX + +void *decoder_bmmu_box_alloc_box(const char *name, + int channel_id, + int max_num, + int aligned, + int mem_flags); + +int decoder_bmmu_box_alloc_idx( + void *handle, int idx, int size, + int aligned_2n, int mem_flags); + +int decoder_bmmu_box_free_idx(void *handle, int idx); +int decoder_bmmu_box_free(void *handle); +void *decoder_bmmu_box_get_mem_handle( + void *box_handle, int idx); + +unsigned long decoder_bmmu_box_get_phy_addr( + void *box_handle, int idx); + +void *decoder_bmmu_box_get_virt_addr( + void *box_handle, int idx); + +/*flags: &0x1 for wait,*/ +int decoder_bmmu_box_check_and_wait_size( + int size, int flags); + +int decoder_bmmu_box_alloc_buf_phy( + void *handle, int idx, + int size, unsigned char *driver_name, + unsigned long *buf_phy_addr); + +#define BMMU_ALLOC_FLAGS_WAIT (1 << 0) +#define BMMU_ALLOC_FLAGS_CAN_CLEAR_KEEPER (1 << 1) +#define BMMU_ALLOC_FLAGS_WAITCLEAR \ + (BMMU_ALLOC_FLAGS_WAIT |\ + BMMU_ALLOC_FLAGS_CAN_CLEAR_KEEPER) + +int decoder_bmmu_box_alloc_idx_wait( + void *handle, int idx, + int size, int aligned_2n, + int mem_flags, + int wait_flags); + +int decoder_bmmu_box_init(void); +void decoder_bmmu_box_exit(void); + +#endif + diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/decoder_mmu_box.c b/drivers/amlogic/media_modules/frame_provider/decoder/utils/decoder_mmu_box.c new file mode 100644 index 000000000000..6135394b5735 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/decoder_mmu_box.c @@ -0,0 +1,395 @@ +/* + * drivers/amlogic/media/frame_provider/decoder/utils/decoder_mmu_box.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +struct decoder_mmu_box { + int max_sc_num; + const char *name; + int channel_id; + int tvp_mode; + struct mutex mutex; + struct list_head list; + struct codec_mm_scatter *sc_list[1]; +}; +#define MAX_KEEP_FRAME 4 +#define START_KEEP_ID 0x9 +#define MAX_KEEP_ID (INT_MAX - 1) +struct decoder_mmu_box_mgr { + int num; + struct mutex mutex; + struct codec_mm_scatter *keep_sc[MAX_KEEP_FRAME]; + int keep_id[MAX_KEEP_FRAME]; + int next_id;/*id for keep & free.*/ + struct list_head box_list; +}; +static struct decoder_mmu_box_mgr global_mgr; +static struct decoder_mmu_box_mgr *get_decoder_mmu_box_mgr(void) +{ + return &global_mgr; +} + +static int decoder_mmu_box_mgr_add_box(struct decoder_mmu_box *box) +{ + struct decoder_mmu_box_mgr *mgr = get_decoder_mmu_box_mgr(); + + mutex_lock(&mgr->mutex); + list_add_tail(&box->list, &mgr->box_list); + mutex_unlock(&mgr->mutex); + return 0; +} + +static int decoder_mmu_box_mgr_del_box(struct decoder_mmu_box *box) +{ + struct decoder_mmu_box_mgr *mgr = get_decoder_mmu_box_mgr(); + + mutex_lock(&mgr->mutex); + list_del(&box->list); + mutex_unlock(&mgr->mutex); + return 0; +} + + + +void *decoder_mmu_box_alloc_box(const char *name, + int channel_id, + int max_num, + int min_size_M, + int mem_flags) +/*min_size_M:wait alloc this size*/ +{ + struct decoder_mmu_box *box; + int size; + + pr_debug("decoder_mmu_box_alloc_box, mem_flags = 0x%x\n", mem_flags); + + size = sizeof(struct decoder_mmu_box) + + sizeof(struct codec_mm_scatter *) * + max_num; + box = kmalloc(size, GFP_KERNEL); + if (!box) { + pr_err("can't alloc decoder buffers box!!!\n"); + return NULL; + } + memset(box, 0, size); + box->max_sc_num = max_num; + box->name = name; + box->channel_id = channel_id; + box->tvp_mode = mem_flags; + + mutex_init(&box->mutex); + INIT_LIST_HEAD(&box->list); + decoder_mmu_box_mgr_add_box(box); + codec_mm_scatter_mgt_delay_free_swith(1, 2000, + min_size_M, box->tvp_mode); + return (void *)box; +} +EXPORT_SYMBOL(decoder_mmu_box_alloc_box); + +int decoder_mmu_box_alloc_idx( + void *handle, int idx, int num_pages, + unsigned int *mmu_index_adr) +{ + struct decoder_mmu_box *box = handle; + struct codec_mm_scatter *sc; + int ret; + int i; + + if (!box || idx < 0 || idx >= box->max_sc_num) { + pr_err("can't alloc mmu box(%p),idx:%d\n", + box, idx); + return -1; + } + mutex_lock(&box->mutex); + sc = box->sc_list[idx]; + if (sc) { + if (sc->page_max_cnt >= num_pages) + ret = codec_mm_scatter_alloc_want_pages(sc, + num_pages); + else { + codec_mm_scatter_dec_owner_user(sc, 0); + box->sc_list[idx] = NULL; + sc = NULL; + } + + } + if (!sc) { + sc = codec_mm_scatter_alloc(num_pages + 64, num_pages, + box->tvp_mode); + if (!sc) { + mutex_unlock(&box->mutex); + pr_err("alloc mmu failed, need pages=%d\n", + num_pages); + return -1; + } + box->sc_list[idx] = sc; + } + + for (i = 0; i < num_pages; i++) + mmu_index_adr[i] = PAGE_INDEX(sc->pages_list[i]); + mmu_index_adr[num_pages] = 0; + + mutex_unlock(&box->mutex); + + return 0; +} +EXPORT_SYMBOL(decoder_mmu_box_alloc_idx); + +int decoder_mmu_box_free_idx_tail( + void *handle, int idx, + int start_release_index) +{ + struct decoder_mmu_box *box = handle; + struct codec_mm_scatter *sc; + + if (!box || idx < 0 || idx >= box->max_sc_num) { + pr_err("can't free tail mmu box(%p),idx:%d in (%d-%d)\n", + box, idx, 0, + box->max_sc_num - 1); + return -1; + } + mutex_lock(&box->mutex); + sc = box->sc_list[idx]; + if (sc && start_release_index < sc->page_cnt) + codec_mm_scatter_free_tail_pages_fast(sc, + start_release_index); + mutex_unlock(&box->mutex); + return 0; +} +EXPORT_SYMBOL(decoder_mmu_box_free_idx_tail); + +int decoder_mmu_box_free_idx(void *handle, int idx) +{ + struct decoder_mmu_box *box = handle; + struct codec_mm_scatter *sc; + + if (!box || idx < 0 || idx >= box->max_sc_num) { + pr_err("can't free idx of box(%p),idx:%d in (%d-%d)\n", + box, idx, 0, + box->max_sc_num - 1); + return -1; + } + mutex_lock(&box->mutex); + sc = box->sc_list[idx]; + if (sc && sc->page_cnt > 0) { + codec_mm_scatter_dec_owner_user(sc, 0); + box->sc_list[idx] = NULL; + } mutex_unlock(&box->mutex); + return 0; +} +EXPORT_SYMBOL(decoder_mmu_box_free_idx); + +int decoder_mmu_box_free(void *handle) +{ + struct decoder_mmu_box *box = handle; + struct codec_mm_scatter *sc; + int i; + + if (!box) { + pr_err("can't free box of NULL box!\n"); + return -1; + } + mutex_lock(&box->mutex); + for (i = 0; i < box->max_sc_num; i++) { + sc = box->sc_list[i]; + if (sc) { + codec_mm_scatter_dec_owner_user(sc, 200); + box->sc_list[i] = NULL; + } + } + mutex_unlock(&box->mutex); + decoder_mmu_box_mgr_del_box(box); + codec_mm_scatter_mgt_delay_free_swith(0, 2000, 0, box->tvp_mode); + kfree(box); + return 0; +} +EXPORT_SYMBOL(decoder_mmu_box_free); + +void *decoder_mmu_box_get_mem_handle(void *box_handle, int idx) +{ + struct decoder_mmu_box *box = box_handle; + + if (!box || idx < 0 || idx >= box->max_sc_num) + return NULL; + return box->sc_list[idx]; +} +EXPORT_SYMBOL(decoder_mmu_box_get_mem_handle); + +static int decoder_mmu_box_dump(struct decoder_mmu_box *box, + void *buf, int size) +{ + char *pbuf = buf; + char sbuf[512]; + int tsize = 0; + int s; + int i; + + if (!buf) { + pbuf = sbuf; + size = 100000; + } + #define BUFPRINT(args...) \ + do {\ + s = snprintf(pbuf, size - tsize, args);\ + tsize += s;\ + pbuf += s; \ + } while (0) + + for (i = 0; i < box->max_sc_num; i++) { + struct codec_mm_scatter *sc = box->sc_list[i]; + + if (sc) { + BUFPRINT("sc mem[%d]:%p, size=%d\n", + i, sc, + sc->page_cnt << PAGE_SHIFT); + } + } +#undef BUFPRINT + if (!buf) + pr_info("%s", sbuf); + + return tsize; +} + +static int decoder_mmu_box_dump_all(void *buf, int size) +{ + struct decoder_mmu_box_mgr *mgr = get_decoder_mmu_box_mgr(); + char *pbuf = buf; + char sbuf[512]; + int tsize = 0; + int s; + int i; + struct list_head *head, *list; + + if (!pbuf) { + pbuf = sbuf; + size = 100000; + } + + #define BUFPRINT(args...) \ + do {\ + s = snprintf(pbuf, size - tsize, args);\ + tsize += s;\ + pbuf += s; \ + } while (0) + + mutex_lock(&mgr->mutex); + head = &mgr->box_list; + list = head->next; + i = 0; + while (list != head) { + struct decoder_mmu_box *box; + box = list_entry(list, struct decoder_mmu_box, + list); + BUFPRINT("box[%d]: %s, %splayer_id:%d, max_num:%d\n", + i, + box->name, + box->tvp_mode ? "TVP mode " : "", + box->channel_id, + box->max_sc_num); + if (buf) { + s += decoder_mmu_box_dump(box, pbuf, size - tsize); + if (s > 0) { + tsize += s; + pbuf += s; + } + } else { + pr_info("%s", sbuf); + pbuf = sbuf; + tsize += decoder_mmu_box_dump(box, NULL, 0); + } + list = list->next; + i++; + } + mutex_unlock(&mgr->mutex); + + +#undef BUFPRINT + if (!buf) + pr_info("%s", sbuf); + return tsize; +} + + + +static ssize_t +box_dump_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + ssize_t ret = 0; + + ret = decoder_mmu_box_dump_all(buf, PAGE_SIZE); + return ret; +} + + + +static struct class_attribute decoder_mmu_box_class_attrs[] = { + __ATTR_RO(box_dump), + __ATTR_NULL +}; + +static struct class decoder_mmu_box_class = { + .name = "decoder_mmu_box", + .class_attrs = decoder_mmu_box_class_attrs, +}; + +int decoder_mmu_box_init(void) +{ + int r; + + memset(&global_mgr, 0, sizeof(global_mgr)); + INIT_LIST_HEAD(&global_mgr.box_list); + mutex_init(&global_mgr.mutex); + global_mgr.next_id = START_KEEP_ID; + r = class_register(&decoder_mmu_box_class); + return r; +} +EXPORT_SYMBOL(decoder_mmu_box_init); + +void decoder_mmu_box_exit(void) +{ + class_unregister(&decoder_mmu_box_class); + pr_info("dec mmu box exit.\n"); +} + +#if 0 +static int __init decoder_mmu_box_init(void) +{ + int r; + + memset(&global_mgr, 0, sizeof(global_mgr)); + INIT_LIST_HEAD(&global_mgr.box_list); + mutex_init(&global_mgr.mutex); + global_mgr.next_id = START_KEEP_ID; + r = class_register(&decoder_mmu_box_class); + return r; +} + +module_init(decoder_mmu_box_init); +#endif diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/decoder_mmu_box.h b/drivers/amlogic/media_modules/frame_provider/decoder/utils/decoder_mmu_box.h new file mode 100644 index 000000000000..4aa9bf5ba781 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/decoder_mmu_box.h @@ -0,0 +1,46 @@ +/* + * drivers/amlogic/media/frame_provider/decoder/utils/decoder_mmu_box.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef DECODER_BUFFER_BOX +#define DECODER_BUFFER_BOX + +void *decoder_mmu_box_alloc_box(const char *name, + int channel_id, + int max_num, + int min_size_M, + int mem_flags); + +int decoder_mmu_box_alloc_idx( + void *handle, int idx, int num_pages, + unsigned int *mmu_index_adr); + +int decoder_mmu_box_free_idx_tail(void *handle, int idx, + int start_release_index); + +int decoder_mmu_box_free_idx(void *handle, int idx); + +int decoder_mmu_box_free(void *handle); + +int decoder_mmu_box_move_keep_idx(void *box_handle, + int keep_idx); +int decoder_mmu_box_free_keep(int keep_id); +int decoder_mmu_box_free_all_keep(void); +void *decoder_mmu_box_get_mem_handle(void *box_handle, int idx); +int decoder_mmu_box_init(void); +void decoder_mmu_box_exit(void); + +#endif diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/firmware.h b/drivers/amlogic/media_modules/frame_provider/decoder/utils/firmware.h new file mode 100644 index 000000000000..17f64e430b72 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/firmware.h @@ -0,0 +1,21 @@ +#ifndef __VIDEO_FIRMWARE_HEADER_ +#define __VIDEO_FIRMWARE_HEADER_ + +#include "../../../common/firmware/firmware_type.h" +#include + +#define FW_LOAD_FORCE (0x1) +#define FW_LOAD_TRY (0X2) + +struct firmware_s { + unsigned int len; + char data[0]; +}; + +extern int get_decoder_firmware_data(enum vformat_e type, + const char *file_name, char *buf, int size); +extern int get_data_from_name(const char *name, char *buf); +extern int get_firmware_data(unsigned int foramt, char *buf); +extern int video_fw_reload(int mode); + +#endif diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/secprot.c b/drivers/amlogic/media_modules/frame_provider/decoder/utils/secprot.c new file mode 100644 index 000000000000..1d14e2c39bef --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/secprot.c @@ -0,0 +1,43 @@ +/* + * drivers/amlogic/amports/arch/secprot.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * +*/ + +#include "secprot.h" + +int tee_config_device_secure(int dev_id, int secure) +{ + int ret = 0; + register unsigned x0 asm("x0"); + register unsigned x1 asm("x1"); + register unsigned x2 asm("x2"); + + x0 = OPTEE_SMC_CONFIG_DEVICE_SECURE; + x1 = dev_id; + x2 = secure; + + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + __asmeq("%2", "x1") + __asmeq("%3", "x2") + "smc #0\n" + : "=r"(x0) + : "r"(x0), "r"(x1), "r"(x2)); + ret = x0; + + return ret; +} + diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/secprot.h b/drivers/amlogic/media_modules/frame_provider/decoder/utils/secprot.h new file mode 100644 index 000000000000..f8fc5da845e9 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/secprot.h @@ -0,0 +1,39 @@ +/* + * drivers/amlogic/amports/arch/secprot.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * +*/ + +#ifndef __SECPROT_H_ +#define __SECPROT_H_ + +#define DMC_DEV_TYPE_NON_SECURE 0 +#define DMC_DEV_TYPE_SECURE 1 + +#define DMC_DEV_ID_GPU 1 +#define DMC_DEV_ID_HEVC 4 +#define DMC_DEV_ID_PARSER 7 +#define DMC_DEV_ID_VPU 8 +#define DMC_DEV_ID_VDEC 13 +#define DMC_DEV_ID_HCODEC 14 +#define DMC_DEV_ID_GE2D 15 + +#define OPTEE_SMC_CONFIG_DEVICE_SECURE 0xb200000e + +#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" + +extern int tee_config_device_secure(int dev_id, int secure); + +#endif /* __SECPROT_H_ */ + diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/utils.c b/drivers/amlogic/media_modules/frame_provider/decoder/utils/utils.c new file mode 100644 index 000000000000..667b6f14bec7 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/utils.c @@ -0,0 +1,71 @@ +/* + * drivers/amlogic/media/frame_provider/decoder/utils/utils.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vdec.h" +#include "vdec_input.h" +#include +#include "amvdec.h" +#include "decoder_mmu_box.h" +#include "decoder_bmmu_box.h" +#include "vdec_profile.h" + +static int __init decoder_common_init(void) +{ + /*vdec init.*/ + vdec_module_init(); + + /*amvdec init.*/ + amvdec_init(); + + /*mmu box init.*/ + decoder_mmu_box_init();/*exit?*/ + decoder_bmmu_box_init(); + + vdec_profile_init_debugfs(); + + return 0; +} + +static void __exit decoder_common_exit(void) +{ + /*vdec exit.*/ + vdec_module_exit(); + + /*amvdec exit.*/ + amvdec_exit(); + + decoder_mmu_box_exit(); + decoder_bmmu_box_exit(); + + vdec_profile_exit_debugfs(); +} + +module_init(decoder_common_init); +module_exit(decoder_common_exit); diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec.c b/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec.c new file mode 100644 index 000000000000..e7fb7514ea55 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec.c @@ -0,0 +1,3861 @@ +/* + * drivers/amlogic/media/frame_provider/decoder/utils/vdec.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +/*for VDEC_DEBUG_SUPPORT*/ +#include + +#include +#include "vdec.h" +#include "vdec_trace.h" +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC +#include "vdec_profile.h" +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../../stream_input/amports/amports_priv.h" + +#include +#include "../utils/amvdec.h" +#include "vdec_input.h" + +#include "../../../common/media_clock/clk/clk.h" +#include +#include +#include +#include +#include +#include +#include "secprot.h" + +static DEFINE_MUTEX(vdec_mutex); + +#define MC_SIZE (4096 * 4) +#define CMA_ALLOC_SIZE SZ_64M +#define MEM_NAME "vdec_prealloc" +static int inited_vcodec_num; +#define jiffies_ms div64_u64(get_jiffies_64() * 1000, HZ) +static int poweron_clock_level; +static int keep_vdec_mem; +static unsigned int debug_trace_num = 16 * 20; +static int step_mode; +static unsigned int clk_config; + +static int hevc_max_reset_count; +#define MAX_INSTANCE_MUN 9 + +static int no_powerdown; +static DEFINE_SPINLOCK(vdec_spin_lock); + +#define HEVC_TEST_LIMIT 100 +#define GXBB_REV_A_MINOR 0xA + +struct am_reg { + char *name; + int offset; +}; + +struct vdec_isr_context_s { + int index; + int irq; + irq_handler_t dev_isr; + irq_handler_t dev_threaded_isr; + void *dev_id; + struct vdec_s *vdec; +}; + +struct vdec_core_s { + struct list_head connected_vdec_list; + spinlock_t lock; + struct ida ida; + atomic_t vdec_nr; + struct vdec_s *vfm_vdec; + struct vdec_s *active_vdec; + struct vdec_s *hint_fr_vdec; + struct platform_device *vdec_core_platform_device; + struct device *cma_dev; + struct semaphore sem; + struct task_struct *thread; + struct workqueue_struct *vdec_core_wq; + + unsigned long sched_mask; + struct vdec_isr_context_s isr_context[VDEC_IRQ_MAX]; + int power_ref_count[VDEC_MAX]; +}; + +static struct vdec_core_s *vdec_core; + +static const char * const vdec_status_string[] = { + "VDEC_STATUS_UNINITIALIZED", + "VDEC_STATUS_DISCONNECTED", + "VDEC_STATUS_CONNECTED", + "VDEC_STATUS_ACTIVE" +}; + +static int debugflags; + +int vdec_get_debug_flags(void) +{ + return debugflags; +} +EXPORT_SYMBOL(vdec_get_debug_flags); + +unsigned char is_mult_inc(unsigned int type) +{ + unsigned char ret = 0; + if (vdec_get_debug_flags() & 0xf000) + ret = (vdec_get_debug_flags() & 0x1000) + ? 1 : 0; + else if (type & PORT_TYPE_DECODER_SCHED) + ret = 1; + return ret; +} +EXPORT_SYMBOL(is_mult_inc); + +static const bool cores_with_input[VDEC_MAX] = { + true, /* VDEC_1 */ + false, /* VDEC_HCODEC */ + false, /* VDEC_2 */ + true, /* VDEC_HEVC / VDEC_HEVC_FRONT */ + false, /* VDEC_HEVC_BACK */ +}; + +static const int cores_int[VDEC_MAX] = { + VDEC_IRQ_1, + VDEC_IRQ_2, + VDEC_IRQ_0, + VDEC_IRQ_0, + VDEC_IRQ_HEVC_BACK +}; + +unsigned long vdec_core_lock(struct vdec_core_s *core) +{ + unsigned long flags; + + spin_lock_irqsave(&core->lock, flags); + + return flags; +} + +void vdec_core_unlock(struct vdec_core_s *core, unsigned long flags) +{ + spin_unlock_irqrestore(&core->lock, flags); +} + +static int get_canvas(unsigned int index, unsigned int base) +{ + int start; + int canvas_index = index * base; + + if ((base > 4) || (base == 0)) + return -1; + + if ((AMVDEC_CANVAS_START_INDEX + canvas_index + base - 1) + <= AMVDEC_CANVAS_MAX1) { + start = AMVDEC_CANVAS_START_INDEX + base * index; + } else { + canvas_index -= (AMVDEC_CANVAS_MAX1 - + AMVDEC_CANVAS_START_INDEX + 1) / base * base; + if (canvas_index <= AMVDEC_CANVAS_MAX2) + start = canvas_index / base; + else + return -1; + } + + if (base == 1) { + return start; + } else if (base == 2) { + return ((start + 1) << 16) | ((start + 1) << 8) | start; + } else if (base == 3) { + return ((start + 2) << 16) | ((start + 1) << 8) | start; + } else if (base == 4) { + return (((start + 3) << 24) | (start + 2) << 16) | + ((start + 1) << 8) | start; + } + + return -1; +} + + +int vdec_status(struct vdec_s *vdec, struct vdec_info *vstatus) +{ + if (vdec && vdec->dec_status) + return vdec->dec_status(vdec, vstatus); + + return -1; +} +EXPORT_SYMBOL(vdec_status); + +int vdec_set_trickmode(struct vdec_s *vdec, unsigned long trickmode) +{ + int r; + + if (vdec->set_trickmode) { + r = vdec->set_trickmode(vdec, trickmode); + + if ((r == 0) && (vdec->slave) && (vdec->slave->set_trickmode)) + r = vdec->slave->set_trickmode(vdec->slave, + trickmode); + return r; + } + + return -1; +} +EXPORT_SYMBOL(vdec_set_trickmode); + +int vdec_set_isreset(struct vdec_s *vdec, int isreset) +{ + vdec->is_reset = isreset; + pr_info("is_reset=%d\n", isreset); + if (vdec->set_isreset) + return vdec->set_isreset(vdec, isreset); + return 0; +} +EXPORT_SYMBOL(vdec_set_isreset); + +int vdec_set_dv_metawithel(struct vdec_s *vdec, int isdvmetawithel) +{ + vdec->dolby_meta_with_el = isdvmetawithel; + pr_info("isdvmetawithel=%d\n", isdvmetawithel); + return 0; +} +EXPORT_SYMBOL(vdec_set_dv_metawithel); + +void vdec_set_no_powerdown(int flag) +{ + no_powerdown = flag; + pr_info("no_powerdown=%d\n", no_powerdown); + return; +} +EXPORT_SYMBOL(vdec_set_no_powerdown); + +void vdec_count_info(struct vdec_info *vs, unsigned int err, + unsigned int offset) +{ + if (err) + vs->error_frame_count++; + if (offset) { + if (0 == vs->frame_count) { + vs->offset = 0; + vs->samp_cnt = 0; + } + vs->frame_data = offset > vs->total_data ? + offset - vs->total_data : vs->total_data - offset; + vs->total_data = offset; + if (vs->samp_cnt < 96000 * 2) { /* 2s */ + if (0 == vs->samp_cnt) + vs->offset = offset; + vs->samp_cnt += vs->frame_dur; + } else { + vs->bit_rate = (offset - vs->offset) / 2; + /*pr_info("bitrate : %u\n",vs->bit_rate);*/ + vs->samp_cnt = 0; + } + vs->frame_count++; + } + /*pr_info("size : %u, offset : %u, dur : %u, cnt : %u\n", + vs->offset,offset,vs->frame_dur,vs->samp_cnt);*/ + return; +} +EXPORT_SYMBOL(vdec_count_info); +int vdec_is_support_4k(void) +{ + return !is_meson_gxl_package_805X(); +} +EXPORT_SYMBOL(vdec_is_support_4k); + +/* + * clk_config: + *0:default + *1:no gp0_pll; + *2:always used gp0_pll; + *>=10:fixed n M clk; + *== 100 , 100M clks; + */ +unsigned int get_vdec_clk_config_settings(void) +{ + return clk_config; +} +void update_vdec_clk_config_settings(unsigned int config) +{ + clk_config = config; +} +EXPORT_SYMBOL(update_vdec_clk_config_settings); + +static bool hevc_workaround_needed(void) +{ + return (get_cpu_type() == MESON_CPU_MAJOR_ID_GXBB) && + (get_meson_cpu_version(MESON_CPU_VERSION_LVL_MINOR) + == GXBB_REV_A_MINOR); +} + +struct device *get_codec_cma_device(void) +{ + return vdec_core->cma_dev; +} + +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC +static const char * const vdec_device_name[] = { + "amvdec_mpeg12", "ammvdec_mpeg12", + "amvdec_mpeg4", "ammvdec_mpeg4", + "amvdec_h264", "ammvdec_h264", + "amvdec_mjpeg", "ammvdec_mjpeg", + "amvdec_real", "ammvdec_real", + "amjpegdec", "ammjpegdec", + "amvdec_vc1", "ammvdec_vc1", + "amvdec_avs", "ammvdec_avs", + "amvdec_yuv", "ammvdec_yuv", + "amvdec_h264mvc", "ammvdec_h264mvc", + "amvdec_h264_4k2k", "ammvdec_h264_4k2k", + "amvdec_h265", "ammvdec_h265", + "amvenc_avc", "amvenc_avc", + "jpegenc", "jpegenc", + "amvdec_vp9", "ammvdec_vp9", + "amvdec_avs2", "ammvdec_avs2" +}; + + +#else + +static const char * const vdec_device_name[] = { + "amvdec_mpeg12", + "amvdec_mpeg4", + "amvdec_h264", + "amvdec_mjpeg", + "amvdec_real", + "amjpegdec", + "amvdec_vc1", + "amvdec_avs", + "amvdec_yuv", + "amvdec_h264mvc", + "amvdec_h264_4k2k", + "amvdec_h265", + "amvenc_avc", + "jpegenc", + "amvdec_vp9", + "amvdec_avs2" +}; + +#endif + +#ifdef VDEC_DEBUG_SUPPORT +static u64 get_current_clk(void) +{ + /*struct timespec xtime = current_kernel_time(); + u64 usec = xtime.tv_sec * 1000000; + usec += xtime.tv_nsec / 1000; + */ + u64 usec = sched_clock(); + return usec; +} + +static void inc_profi_count(unsigned long mask, u32 *count) +{ + enum vdec_type_e type; + + for (type = VDEC_1; type < VDEC_MAX; type++) { + if (mask & (1 << type)) + count[type]++; + } +} + +static void update_profi_clk_run(struct vdec_s *vdec, + unsigned long mask, u64 clk) +{ + enum vdec_type_e type; + + for (type = VDEC_1; type < VDEC_MAX; type++) { + if (mask & (1 << type)) { + vdec->start_run_clk[type] = clk; + if (vdec->profile_start_clk[type] == 0) + vdec->profile_start_clk[type] = clk; + vdec->total_clk[type] = clk + - vdec->profile_start_clk[type]; + /*pr_info("set start_run_clk %ld\n", + vdec->start_run_clk);*/ + + } + } +} + +static void update_profi_clk_stop(struct vdec_s *vdec, + unsigned long mask, u64 clk) +{ + enum vdec_type_e type; + + for (type = VDEC_1; type < VDEC_MAX; type++) { + if (mask & (1 << type)) { + if (vdec->start_run_clk[type] == 0) + pr_info("error, start_run_clk[%d] not set\n", type); + + /*pr_info("update run_clk type %d, %ld, %ld, %ld\n", + type, + clk, + vdec->start_run_clk[type], + vdec->run_clk[type]);*/ + vdec->run_clk[type] += + (clk - vdec->start_run_clk[type]); + } + } +} + +#endif + +int vdec_set_decinfo(struct vdec_s *vdec, struct dec_sysinfo *p) +{ + if (copy_from_user((void *)&vdec->sys_info_store, (void *)p, + sizeof(struct dec_sysinfo))) + return -EFAULT; + + return 0; +} +EXPORT_SYMBOL(vdec_set_decinfo); + +/* construct vdec strcture */ +struct vdec_s *vdec_create(struct stream_port_s *port, + struct vdec_s *master) +{ + struct vdec_s *vdec; + int type = VDEC_TYPE_SINGLE; + int id; + if (is_mult_inc(port->type)) + type = (port->type & PORT_TYPE_FRAME) ? + VDEC_TYPE_FRAME_BLOCK : + VDEC_TYPE_STREAM_PARSER; + + id = ida_simple_get(&vdec_core->ida, + 0, MAX_INSTANCE_MUN, GFP_KERNEL); + if (id < 0) { + pr_info("vdec_create request id failed!ret =%d\n", id); + return NULL; + } + vdec = vzalloc(sizeof(struct vdec_s)); + + /* TBD */ + if (vdec) { + vdec->magic = 0x43454456; + vdec->id = -1; + vdec->type = type; + vdec->port = port; + vdec->sys_info = &vdec->sys_info_store; + + INIT_LIST_HEAD(&vdec->list); + + atomic_inc(&vdec_core->vdec_nr); + vdec->id = id; + vdec_input_init(&vdec->input, vdec); + if (master) { + vdec->master = master; + master->slave = vdec; + master->sched = 1; + } + } + + pr_debug("vdec_create instance %p, total %d\n", vdec, + atomic_read(&vdec_core->vdec_nr)); + + //trace_vdec_create(vdec); /*DEBUG_TMP*/ + + return vdec; +} +EXPORT_SYMBOL(vdec_create); + +int vdec_set_format(struct vdec_s *vdec, int format) +{ + vdec->format = format; + vdec->port_flag |= PORT_FLAG_VFORMAT; + + if (vdec->slave) { + vdec->slave->format = format; + vdec->slave->port_flag |= PORT_FLAG_VFORMAT; + } + + //trace_vdec_set_format(vdec, format);/*DEBUG_TMP*/ + + return 0; +} +EXPORT_SYMBOL(vdec_set_format); + +int vdec_set_pts(struct vdec_s *vdec, u32 pts) +{ + vdec->pts = pts; + vdec->pts64 = div64_u64((u64)pts * 100, 9); + vdec->pts_valid = true; + //trace_vdec_set_pts(vdec, (u64)pts);/*DEBUG_TMP*/ + return 0; +} +EXPORT_SYMBOL(vdec_set_pts); + +int vdec_set_pts64(struct vdec_s *vdec, u64 pts64) +{ + vdec->pts64 = pts64; + vdec->pts = (u32)div64_u64(pts64 * 9, 100); + vdec->pts_valid = true; + + //trace_vdec_set_pts64(vdec, pts64);/*DEBUG_TMP*/ + return 0; +} +EXPORT_SYMBOL(vdec_set_pts64); + +void vdec_set_status(struct vdec_s *vdec, int status) +{ + //trace_vdec_set_status(vdec, status);/*DEBUG_TMP*/ + vdec->status = status; +} +EXPORT_SYMBOL(vdec_set_status); + +void vdec_set_next_status(struct vdec_s *vdec, int status) +{ + //trace_vdec_set_next_status(vdec, status);/*DEBUG_TMP*/ + vdec->next_status = status; +} +EXPORT_SYMBOL(vdec_set_next_status); + +int vdec_set_video_path(struct vdec_s *vdec, int video_path) +{ + vdec->frame_base_video_path = video_path; + return 0; +} +EXPORT_SYMBOL(vdec_set_video_path); + +int vdec_set_receive_id(struct vdec_s *vdec, int receive_id) +{ + vdec->vf_receiver_inst = receive_id; + return 0; +} +EXPORT_SYMBOL(vdec_set_receive_id); + +/* add frame data to input chain */ +int vdec_write_vframe(struct vdec_s *vdec, const char *buf, size_t count) +{ + return vdec_input_add_frame(&vdec->input, buf, count); +} +EXPORT_SYMBOL(vdec_write_vframe); + +/* add a work queue thread for vdec*/ +void vdec_schedule_work(struct work_struct *work) +{ + if (vdec_core->vdec_core_wq) + queue_work(vdec_core->vdec_core_wq, work); + else + schedule_work(work); +} +EXPORT_SYMBOL(vdec_schedule_work); + +static struct vdec_s *vdec_get_associate(struct vdec_s *vdec) +{ + if (vdec->master) + return vdec->master; + else if (vdec->slave) + return vdec->slave; + return NULL; +} + +static void vdec_sync_input_read(struct vdec_s *vdec) +{ + if (!vdec_stream_based(vdec)) + return; + + if (vdec_dual(vdec)) { + u32 me, other; + if (vdec->input.target == VDEC_INPUT_TARGET_VLD) { + me = READ_VREG(VLD_MEM_VIFIFO_WRAP_COUNT); + other = + vdec_get_associate(vdec)->input.stream_cookie; + if (me > other) + return; + else if (me == other) { + me = READ_VREG(VLD_MEM_VIFIFO_RP); + other = + vdec_get_associate(vdec)->input.swap_rp; + if (me > other) { + WRITE_PARSER_REG(PARSER_VIDEO_RP, + vdec_get_associate(vdec)-> + input.swap_rp); + return; + } + } + WRITE_PARSER_REG(PARSER_VIDEO_RP, + READ_VREG(VLD_MEM_VIFIFO_RP)); + } else if (vdec->input.target == VDEC_INPUT_TARGET_HEVC) { + me = READ_VREG(HEVC_SHIFT_BYTE_COUNT); + if (((me & 0x80000000) == 0) && + (vdec->input.streaming_rp & 0x80000000)) + me += 1ULL << 32; + other = vdec_get_associate(vdec)->input.streaming_rp; + if (me > other) { + WRITE_PARSER_REG(PARSER_VIDEO_RP, + vdec_get_associate(vdec)-> + input.swap_rp); + return; + } + + WRITE_PARSER_REG(PARSER_VIDEO_RP, + READ_VREG(HEVC_STREAM_RD_PTR)); + } + } else if (vdec->input.target == VDEC_INPUT_TARGET_VLD) { + WRITE_PARSER_REG(PARSER_VIDEO_RP, + READ_VREG(VLD_MEM_VIFIFO_RP)); + } else if (vdec->input.target == VDEC_INPUT_TARGET_HEVC) { + WRITE_PARSER_REG(PARSER_VIDEO_RP, + READ_VREG(HEVC_STREAM_RD_PTR)); + } +} + +static void vdec_sync_input_write(struct vdec_s *vdec) +{ + if (!vdec_stream_based(vdec)) + return; + + if (vdec->input.target == VDEC_INPUT_TARGET_VLD) { + WRITE_VREG(VLD_MEM_VIFIFO_WP, + READ_PARSER_REG(PARSER_VIDEO_WP)); + } else if (vdec->input.target == VDEC_INPUT_TARGET_HEVC) { + WRITE_VREG(HEVC_STREAM_WR_PTR, + READ_PARSER_REG(PARSER_VIDEO_WP)); + } +} + +/* + *get next frame from input chain + */ +/* + *THE VLD_FIFO is 512 bytes and Video buffer level + * empty interrupt is set to 0x80 bytes threshold + */ +#define VLD_PADDING_SIZE 1024 +#define HEVC_PADDING_SIZE (1024*16) +int vdec_prepare_input(struct vdec_s *vdec, struct vframe_chunk_s **p) +{ + struct vdec_input_s *input = &vdec->input; + struct vframe_chunk_s *chunk = NULL; + struct vframe_block_list_s *block = NULL; + int dummy; + + /* full reset to HW input */ + if (input->target == VDEC_INPUT_TARGET_VLD) { + WRITE_VREG(VLD_MEM_VIFIFO_CONTROL, 0); + + /* reset VLD fifo for all vdec */ + WRITE_VREG(DOS_SW_RESET0, (1<<5) | (1<<4) | (1<<3)); + WRITE_VREG(DOS_SW_RESET0, 0); + + dummy = READ_RESET_REG(RESET0_REGISTER); + WRITE_VREG(POWER_CTL_VLD, 1 << 4); + } else if (input->target == VDEC_INPUT_TARGET_HEVC) { +#if 0 + /*move to driver*/ + if (input_frame_based(input)) + WRITE_VREG(HEVC_STREAM_CONTROL, 0); + + /* + * 2: assist + * 3: parser + * 4: parser_state + * 8: dblk + * 11:mcpu + * 12:ccpu + * 13:ddr + * 14:iqit + * 15:ipp + * 17:qdct + * 18:mpred + * 19:sao + * 24:hevc_afifo + */ + WRITE_VREG(DOS_SW_RESET3, + (1<<3)|(1<<4)|(1<<8)|(1<<11)|(1<<12)|(1<<14)|(1<<15)| + (1<<17)|(1<<18)|(1<<19)); + WRITE_VREG(DOS_SW_RESET3, 0); +#endif + } + + /* + *setup HW decoder input buffer (VLD context) + * based on input->type and input->target + */ + if (input_frame_based(input)) { + chunk = vdec_input_next_chunk(&vdec->input); + + if (chunk == NULL) { + *p = NULL; + return -1; + } + + block = chunk->block; + + if (input->target == VDEC_INPUT_TARGET_VLD) { + WRITE_VREG(VLD_MEM_VIFIFO_START_PTR, block->start); + WRITE_VREG(VLD_MEM_VIFIFO_END_PTR, block->start + + block->size - 8); + WRITE_VREG(VLD_MEM_VIFIFO_CURR_PTR, + round_down(block->start + chunk->offset, + VDEC_FIFO_ALIGN)); + + WRITE_VREG(VLD_MEM_VIFIFO_CONTROL, 1); + WRITE_VREG(VLD_MEM_VIFIFO_CONTROL, 0); + + /* set to manual mode */ + WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, 2); + WRITE_VREG(VLD_MEM_VIFIFO_RP, + round_down(block->start + chunk->offset, + VDEC_FIFO_ALIGN)); + dummy = chunk->offset + chunk->size + + VLD_PADDING_SIZE; + if (dummy >= block->size) + dummy -= block->size; + WRITE_VREG(VLD_MEM_VIFIFO_WP, + round_down(block->start + dummy, + VDEC_FIFO_ALIGN)); + + WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, 3); + WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, 2); + + WRITE_VREG(VLD_MEM_VIFIFO_CONTROL, + (0x11 << 16) | (1<<10) | (7<<3)); + + } else if (input->target == VDEC_INPUT_TARGET_HEVC) { + WRITE_VREG(HEVC_STREAM_START_ADDR, block->start); + WRITE_VREG(HEVC_STREAM_END_ADDR, block->start + + block->size); + WRITE_VREG(HEVC_STREAM_RD_PTR, block->start + + chunk->offset); + dummy = chunk->offset + chunk->size + + HEVC_PADDING_SIZE; + if (dummy >= block->size) + dummy -= block->size; + WRITE_VREG(HEVC_STREAM_WR_PTR, + round_down(block->start + dummy, + VDEC_FIFO_ALIGN)); + + /* set endian */ + SET_VREG_MASK(HEVC_STREAM_CONTROL, 7 << 4); + } + + *p = chunk; + return chunk->size; + + } else { + /* stream based */ + u32 rp = 0, wp = 0, fifo_len = 0; + int size; + bool swap_valid = input->swap_valid; + unsigned long swap_page_phys = input->swap_page_phys; + + if (vdec_dual(vdec) && + ((vdec->flag & VDEC_FLAG_SELF_INPUT_CONTEXT) == 0)) { + /* keep using previous input context */ + struct vdec_s *master = (vdec->slave) ? + vdec : vdec->master; + if (master->input.last_swap_slave) { + swap_valid = master->slave->input.swap_valid; + swap_page_phys = + master->slave->input.swap_page_phys; + } else { + swap_valid = master->input.swap_valid; + swap_page_phys = master->input.swap_page_phys; + } + } + + if (swap_valid) { + if (input->target == VDEC_INPUT_TARGET_VLD) { + if (vdec->format == VFORMAT_H264) + SET_VREG_MASK(POWER_CTL_VLD, + (1 << 9)); + + WRITE_VREG(VLD_MEM_VIFIFO_CONTROL, 0); + + /* restore read side */ + WRITE_VREG(VLD_MEM_SWAP_ADDR, + swap_page_phys); + WRITE_VREG(VLD_MEM_SWAP_CTL, 1); + + while (READ_VREG(VLD_MEM_SWAP_CTL) & (1<<7)) + ; + WRITE_VREG(VLD_MEM_SWAP_CTL, 0); + + /* restore wrap count */ + WRITE_VREG(VLD_MEM_VIFIFO_WRAP_COUNT, + input->stream_cookie); + + rp = READ_VREG(VLD_MEM_VIFIFO_RP); + fifo_len = READ_VREG(VLD_MEM_VIFIFO_LEVEL); + + /* enable */ + WRITE_VREG(VLD_MEM_VIFIFO_CONTROL, + (0x11 << 16) | (1<<10)); + + /* sync with front end */ + vdec_sync_input_read(vdec); + vdec_sync_input_write(vdec); + + wp = READ_VREG(VLD_MEM_VIFIFO_WP); + } else if (input->target == VDEC_INPUT_TARGET_HEVC) { + SET_VREG_MASK(HEVC_STREAM_CONTROL, 1); + + /* restore read side */ + WRITE_VREG(HEVC_STREAM_SWAP_ADDR, + swap_page_phys); + WRITE_VREG(HEVC_STREAM_SWAP_CTRL, 1); + + while (READ_VREG(HEVC_STREAM_SWAP_CTRL) + & (1<<7)) + ; + WRITE_VREG(HEVC_STREAM_SWAP_CTRL, 0); + + /* restore stream offset */ + WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, + input->stream_cookie); + + rp = READ_VREG(HEVC_STREAM_RD_PTR); + fifo_len = (READ_VREG(HEVC_STREAM_FIFO_CTL) + >> 16) & 0x7f; + + + /* enable */ + + /* sync with front end */ + vdec_sync_input_read(vdec); + vdec_sync_input_write(vdec); + + wp = READ_VREG(HEVC_STREAM_WR_PTR); + + /*pr_info("vdec: restore context\r\n");*/ + } + + } else { + if (input->target == VDEC_INPUT_TARGET_VLD) { + WRITE_VREG(VLD_MEM_VIFIFO_START_PTR, + input->start); + WRITE_VREG(VLD_MEM_VIFIFO_END_PTR, + input->start + input->size - 8); + WRITE_VREG(VLD_MEM_VIFIFO_CURR_PTR, + input->start); + + WRITE_VREG(VLD_MEM_VIFIFO_CONTROL, 1); + WRITE_VREG(VLD_MEM_VIFIFO_CONTROL, 0); + + /* set to manual mode */ + WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, 2); + WRITE_VREG(VLD_MEM_VIFIFO_RP, input->start); + WRITE_VREG(VLD_MEM_VIFIFO_WP, + READ_PARSER_REG(PARSER_VIDEO_WP)); + + rp = READ_VREG(VLD_MEM_VIFIFO_RP); + + /* enable */ + WRITE_VREG(VLD_MEM_VIFIFO_CONTROL, + (0x11 << 16) | (1<<10)); + + wp = READ_VREG(VLD_MEM_VIFIFO_WP); + + } else if (input->target == VDEC_INPUT_TARGET_HEVC) { + WRITE_VREG(HEVC_STREAM_START_ADDR, + input->start); + WRITE_VREG(HEVC_STREAM_END_ADDR, + input->start + input->size); + WRITE_VREG(HEVC_STREAM_RD_PTR, + input->start); + WRITE_VREG(HEVC_STREAM_WR_PTR, + READ_PARSER_REG(PARSER_VIDEO_WP)); + + rp = READ_VREG(HEVC_STREAM_RD_PTR); + wp = READ_VREG(HEVC_STREAM_WR_PTR); + fifo_len = (READ_VREG(HEVC_STREAM_FIFO_CTL) + >> 16) & 0x7f; + + /* enable */ + } + } + *p = NULL; + if (wp >= rp) + size = wp - rp + fifo_len; + else + size = wp + input->size - rp + fifo_len; + if (size < 0) { + pr_info("%s error: input->size %x wp %x rp %x fifo_len %x => size %x\r\n", + __func__, input->size, wp, rp, fifo_len, size); + size = 0; + } + return size; + } +} +EXPORT_SYMBOL(vdec_prepare_input); + +void vdec_enable_input(struct vdec_s *vdec) +{ + struct vdec_input_s *input = &vdec->input; + + if (vdec->status != VDEC_STATUS_ACTIVE) + return; + + if (input->target == VDEC_INPUT_TARGET_VLD) + SET_VREG_MASK(VLD_MEM_VIFIFO_CONTROL, (1<<2) | (1<<1)); + else if (input->target == VDEC_INPUT_TARGET_HEVC) { + SET_VREG_MASK(HEVC_STREAM_CONTROL, 1); + if (vdec_stream_based(vdec)) + CLEAR_VREG_MASK(HEVC_STREAM_CONTROL, 7 << 4); + else + SET_VREG_MASK(HEVC_STREAM_CONTROL, 7 << 4); + SET_VREG_MASK(HEVC_STREAM_FIFO_CTL, (1<<29)); + } +} +EXPORT_SYMBOL(vdec_enable_input); + +int vdec_set_input_buffer(struct vdec_s *vdec, u32 start, u32 size) +{ + int r = vdec_input_set_buffer(&vdec->input, start, size); + + if (r) + return r; + + if (vdec->slave) + r = vdec_input_set_buffer(&vdec->slave->input, start, size); + + return r; +} +EXPORT_SYMBOL(vdec_set_input_buffer); + +/* + * vdec_eos returns the possibility that there are + * more input can be used by decoder through vdec_prepare_input + * Note: this function should be called prior to vdec_vframe_dirty + * by decoder driver to determine if EOS happens for stream based + * decoding when there is no sufficient data for a frame + */ +bool vdec_has_more_input(struct vdec_s *vdec) +{ + struct vdec_input_s *input = &vdec->input; + + if (!input->eos) + return true; + + if (input_frame_based(input)) + return vdec_input_next_input_chunk(input) != NULL; + else { + if (input->target == VDEC_INPUT_TARGET_VLD) + return READ_VREG(VLD_MEM_VIFIFO_WP) != + READ_PARSER_REG(PARSER_VIDEO_WP); + else { + return (READ_VREG(HEVC_STREAM_WR_PTR) & ~0x3) != + (READ_PARSER_REG(PARSER_VIDEO_WP) & ~0x3); + } + } +} +EXPORT_SYMBOL(vdec_has_more_input); + +void vdec_set_prepare_level(struct vdec_s *vdec, int level) +{ + vdec->input.prepare_level = level; +} +EXPORT_SYMBOL(vdec_set_prepare_level); + +void vdec_set_flag(struct vdec_s *vdec, u32 flag) +{ + vdec->flag = flag; +} +EXPORT_SYMBOL(vdec_set_flag); + +void vdec_set_eos(struct vdec_s *vdec, bool eos) +{ + vdec->input.eos = eos; + + if (vdec->slave) + vdec->slave->input.eos = eos; +} +EXPORT_SYMBOL(vdec_set_eos); + +#ifdef VDEC_DEBUG_SUPPORT +void vdec_set_step_mode(void) +{ + step_mode = 0x1ff; +} +EXPORT_SYMBOL(vdec_set_step_mode); +#endif + +void vdec_set_next_sched(struct vdec_s *vdec, struct vdec_s *next_vdec) +{ + if (vdec && next_vdec) { + vdec->sched = 0; + next_vdec->sched = 1; + } +} +EXPORT_SYMBOL(vdec_set_next_sched); + +/* + * Swap Context: S0 S1 S2 S3 S4 + * Sample sequence: M S M M S + * Master Context: S0 S0 S2 S3 S3 + * Slave context: NA S1 S1 S2 S4 + * ^ + * ^ + * ^ + * the tricky part + * If there are back to back decoding of master or slave + * then the context of the counter part should be updated + * with current decoder. In this example, S1 should be + * updated to S2. + * This is done by swap the swap_page and related info + * between two layers. + */ +static void vdec_borrow_input_context(struct vdec_s *vdec) +{ + struct page *swap_page; + unsigned long swap_page_phys; + struct vdec_input_s *me; + struct vdec_input_s *other; + + if (!vdec_dual(vdec)) + return; + + me = &vdec->input; + other = &vdec_get_associate(vdec)->input; + + /* swap the swap_context, borrow counter part's + * swap context storage and update all related info. + * After vdec_vframe_dirty, vdec_save_input_context + * will be called to update current vdec's + * swap context + */ + swap_page = other->swap_page; + other->swap_page = me->swap_page; + me->swap_page = swap_page; + + swap_page_phys = other->swap_page_phys; + other->swap_page_phys = me->swap_page_phys; + me->swap_page_phys = swap_page_phys; + + other->swap_rp = me->swap_rp; + other->streaming_rp = me->streaming_rp; + other->stream_cookie = me->stream_cookie; + other->swap_valid = me->swap_valid; +} + +void vdec_vframe_dirty(struct vdec_s *vdec, struct vframe_chunk_s *chunk) +{ + if (chunk) + chunk->flag |= VFRAME_CHUNK_FLAG_CONSUMED; + + if (vdec_stream_based(vdec)) { + vdec->input.swap_needed = true; + + if (vdec_dual(vdec)) { + vdec_get_associate(vdec)->input.dirty_count = 0; + vdec->input.dirty_count++; + if (vdec->input.dirty_count > 1) { + vdec->input.dirty_count = 1; + vdec_borrow_input_context(vdec); + } + } + + /* for stream based mode, we update read and write pointer + * also in case decoder wants to keep working on decoding + * for more frames while input front end has more data + */ + vdec_sync_input_read(vdec); + vdec_sync_input_write(vdec); + + vdec->need_more_data |= VDEC_NEED_MORE_DATA_DIRTY; + vdec->need_more_data &= ~VDEC_NEED_MORE_DATA; + } +} +EXPORT_SYMBOL(vdec_vframe_dirty); + +bool vdec_need_more_data(struct vdec_s *vdec) +{ + if (vdec_stream_based(vdec)) + return vdec->need_more_data & VDEC_NEED_MORE_DATA; + + return false; +} +EXPORT_SYMBOL(vdec_need_more_data); + + +void hevc_wait_ddr(void) +{ + unsigned long flags; + spin_lock_irqsave(&vdec_spin_lock, flags); + codec_dmcbus_write(DMC_REQ_CTRL, + codec_dmcbus_read(DMC_REQ_CTRL) & (~(1 << 4))); + spin_unlock_irqrestore(&vdec_spin_lock, flags); + + while (!(codec_dmcbus_read(DMC_CHAN_STS) + & (1 << 4))) + ; +} + +void vdec_save_input_context(struct vdec_s *vdec) +{ + struct vdec_input_s *input = &vdec->input; + +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + vdec_profile(vdec, VDEC_PROFILE_EVENT_SAVE_INPUT); +#endif + + if (input->target == VDEC_INPUT_TARGET_VLD) + WRITE_VREG(VLD_MEM_VIFIFO_CONTROL, 1<<15); + + if (input_stream_based(input) && (input->swap_needed)) { + if (input->target == VDEC_INPUT_TARGET_VLD) { + WRITE_VREG(VLD_MEM_SWAP_ADDR, + input->swap_page_phys); + WRITE_VREG(VLD_MEM_SWAP_CTL, 3); + while (READ_VREG(VLD_MEM_SWAP_CTL) & (1<<7)) + ; + WRITE_VREG(VLD_MEM_SWAP_CTL, 0); + vdec->input.stream_cookie = + READ_VREG(VLD_MEM_VIFIFO_WRAP_COUNT); + vdec->input.swap_rp = + READ_VREG(VLD_MEM_VIFIFO_RP); + vdec->input.total_rd_count = + (u64)vdec->input.stream_cookie * + vdec->input.size + vdec->input.swap_rp - + READ_VREG(VLD_MEM_VIFIFO_BYTES_AVAIL); + } else if (input->target == VDEC_INPUT_TARGET_HEVC) { + WRITE_VREG(HEVC_STREAM_SWAP_ADDR, + input->swap_page_phys); + WRITE_VREG(HEVC_STREAM_SWAP_CTRL, 3); + + while (READ_VREG(HEVC_STREAM_SWAP_CTRL) & (1<<7)) + ; + WRITE_VREG(HEVC_STREAM_SWAP_CTRL, 0); + + vdec->input.stream_cookie = + READ_VREG(HEVC_SHIFT_BYTE_COUNT); + vdec->input.swap_rp = + READ_VREG(HEVC_STREAM_RD_PTR); + if (((vdec->input.stream_cookie & 0x80000000) == 0) && + (vdec->input.streaming_rp & 0x80000000)) + vdec->input.streaming_rp += 1ULL << 32; + vdec->input.streaming_rp &= 0xffffffffULL << 32; + vdec->input.streaming_rp |= vdec->input.stream_cookie; + vdec->input.total_rd_count = vdec->input.streaming_rp; + } + + input->swap_valid = true; + input->swap_needed = false; + /*pr_info("vdec: save context\r\n");*/ + + vdec_sync_input_read(vdec); + + if (vdec_dual(vdec)) { + struct vdec_s *master = (vdec->slave) ? + vdec : vdec->master; + master->input.last_swap_slave = (master->slave == vdec); + /* pr_info("master->input.last_swap_slave = %d\n", + master->input.last_swap_slave); */ + } + + hevc_wait_ddr(); + } +} +EXPORT_SYMBOL(vdec_save_input_context); + +void vdec_clean_input(struct vdec_s *vdec) +{ + struct vdec_input_s *input = &vdec->input; + + while (!list_empty(&input->vframe_chunk_list)) { + struct vframe_chunk_s *chunk = + vdec_input_next_chunk(input); + if (chunk->flag & VFRAME_CHUNK_FLAG_CONSUMED) + vdec_input_release_chunk(input, chunk); + else + break; + } + vdec_save_input_context(vdec); +} +EXPORT_SYMBOL(vdec_clean_input); + +int vdec_sync_input(struct vdec_s *vdec) +{ + struct vdec_input_s *input = &vdec->input; + u32 rp = 0, wp = 0, fifo_len = 0; + int size; + + vdec_sync_input_read(vdec); + vdec_sync_input_write(vdec); + if (input->target == VDEC_INPUT_TARGET_VLD) { + rp = READ_VREG(VLD_MEM_VIFIFO_RP); + wp = READ_VREG(VLD_MEM_VIFIFO_WP); + + } else if (input->target == VDEC_INPUT_TARGET_HEVC) { + rp = READ_VREG(HEVC_STREAM_RD_PTR); + wp = READ_VREG(HEVC_STREAM_WR_PTR); + fifo_len = (READ_VREG(HEVC_STREAM_FIFO_CTL) + >> 16) & 0x7f; + } + if (wp >= rp) + size = wp - rp + fifo_len; + else + size = wp + input->size - rp + fifo_len; + if (size < 0) { + pr_info("%s error: input->size %x wp %x rp %x fifo_len %x => size %x\r\n", + __func__, input->size, wp, rp, fifo_len, size); + size = 0; + } + return size; + +} +EXPORT_SYMBOL(vdec_sync_input); + +const char *vdec_status_str(struct vdec_s *vdec) +{ + return vdec->status < ARRAY_SIZE(vdec_status_string) ? + vdec_status_string[vdec->status] : "INVALID"; +} + +const char *vdec_type_str(struct vdec_s *vdec) +{ + switch (vdec->type) { + case VDEC_TYPE_SINGLE: + return "VDEC_TYPE_SINGLE"; + case VDEC_TYPE_STREAM_PARSER: + return "VDEC_TYPE_STREAM_PARSER"; + case VDEC_TYPE_FRAME_BLOCK: + return "VDEC_TYPE_FRAME_BLOCK"; + case VDEC_TYPE_FRAME_CIRCULAR: + return "VDEC_TYPE_FRAME_CIRCULAR"; + default: + return "VDEC_TYPE_INVALID"; + } +} + +const char *vdec_device_name_str(struct vdec_s *vdec) +{ + return vdec_device_name[vdec->format * 2 + 1]; +} +EXPORT_SYMBOL(vdec_device_name_str); + +void walk_vdec_core_list(char *s) +{ + struct vdec_s *vdec; + struct vdec_core_s *core = vdec_core; + unsigned long flags; + + pr_info("%s --->\n", s); + + flags = vdec_core_lock(vdec_core); + + if (list_empty(&core->connected_vdec_list)) { + pr_info("connected vdec list empty\n"); + } else { + list_for_each_entry(vdec, &core->connected_vdec_list, list) { + pr_info("\tvdec (%p), status = %s\n", vdec, + vdec_status_str(vdec)); + } + } + + vdec_core_unlock(vdec_core, flags); +} +EXPORT_SYMBOL(walk_vdec_core_list); + +/* insert vdec to vdec_core for scheduling, + * for dual running decoders, connect/disconnect always runs in pairs + */ +int vdec_connect(struct vdec_s *vdec) +{ + unsigned long flags; + + //trace_vdec_connect(vdec);/*DEBUG_TMP*/ + + if (vdec->status != VDEC_STATUS_DISCONNECTED) + return 0; + + vdec_set_status(vdec, VDEC_STATUS_CONNECTED); + vdec_set_next_status(vdec, VDEC_STATUS_CONNECTED); + + init_completion(&vdec->inactive_done); + + if (vdec->slave) { + vdec_set_status(vdec->slave, VDEC_STATUS_CONNECTED); + vdec_set_next_status(vdec->slave, VDEC_STATUS_CONNECTED); + + init_completion(&vdec->slave->inactive_done); + } + + flags = vdec_core_lock(vdec_core); + + list_add_tail(&vdec->list, &vdec_core->connected_vdec_list); + + if (vdec->slave) { + list_add_tail(&vdec->slave->list, + &vdec_core->connected_vdec_list); + } + + vdec_core_unlock(vdec_core, flags); + + up(&vdec_core->sem); + + return 0; +} +EXPORT_SYMBOL(vdec_connect); + +/* remove vdec from vdec_core scheduling */ +int vdec_disconnect(struct vdec_s *vdec) +{ +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + vdec_profile(vdec, VDEC_PROFILE_EVENT_DISCONNECT); +#endif + //trace_vdec_disconnect(vdec);/*DEBUG_TMP*/ + + if ((vdec->status != VDEC_STATUS_CONNECTED) && + (vdec->status != VDEC_STATUS_ACTIVE)) { + return 0; + } + + /* + *when a vdec is under the management of scheduler + * the status change will only be from vdec_core_thread + */ + vdec_set_next_status(vdec, VDEC_STATUS_DISCONNECTED); + + if (vdec->slave) + vdec_set_next_status(vdec->slave, VDEC_STATUS_DISCONNECTED); + else if (vdec->master) + vdec_set_next_status(vdec->master, VDEC_STATUS_DISCONNECTED); + + up(&vdec_core->sem); + + wait_for_completion(&vdec->inactive_done); + + if (vdec->slave) + wait_for_completion(&vdec->slave->inactive_done); + else if (vdec->master) + wait_for_completion(&vdec->master->inactive_done); + + return 0; +} +EXPORT_SYMBOL(vdec_disconnect); + +/* release vdec structure */ +int vdec_destroy(struct vdec_s *vdec) +{ + //trace_vdec_destroy(vdec);/*DEBUG_TMP*/ + + vdec_input_release(&vdec->input); + +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + vdec_profile_flush(vdec); +#endif + ida_simple_remove(&vdec_core->ida, vdec->id); + vfree(vdec); + + atomic_dec(&vdec_core->vdec_nr); + + return 0; +} +EXPORT_SYMBOL(vdec_destroy); + +/* + * Only support time sliced decoding for frame based input, + * so legacy decoder can exist with time sliced decoder. + */ +static const char *get_dev_name(bool use_legacy_vdec, int format) +{ +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + if (use_legacy_vdec) + return vdec_device_name[format * 2]; + else + return vdec_device_name[format * 2 + 1]; +#else + return vdec_device_name[format]; +#endif +} + +/* + *register vdec_device + * create output, vfm or create ionvideo output + */ +s32 vdec_init(struct vdec_s *vdec, int is_4k) +{ + int r = 0; + struct vdec_s *p = vdec; + const char *dev_name; + int id = PLATFORM_DEVID_AUTO;/*if have used my self*/ + + dev_name = get_dev_name(vdec_single(vdec), vdec->format); + + if (dev_name == NULL) + return -ENODEV; + + pr_info("vdec_init, dev_name:%s, vdec_type=%s\n", + dev_name, vdec_type_str(vdec)); + + /* + *todo: VFM patch control should be configurable, + * for now all stream based input uses default VFM path. + */ + if (vdec_stream_based(vdec) && !vdec_dual(vdec)) { + if (vdec_core->vfm_vdec == NULL) { + pr_debug("vdec_init set vfm decoder %p\n", vdec); + vdec_core->vfm_vdec = vdec; + } else { + pr_info("vdec_init vfm path busy.\n"); + return -EBUSY; + } + } + + mutex_lock(&vdec_mutex); + inited_vcodec_num++; + mutex_unlock(&vdec_mutex); + + vdec_input_set_type(&vdec->input, vdec->type, + (vdec->format == VFORMAT_HEVC || + vdec->format == VFORMAT_AVS2 || + vdec->format == VFORMAT_VP9) ? + VDEC_INPUT_TARGET_HEVC : + VDEC_INPUT_TARGET_VLD); + + p->cma_dev = vdec_core->cma_dev; + p->get_canvas = get_canvas; + atomic_set(&p->inirq_flag, 0); + atomic_set(&p->inirq_thread_flag, 0); + /* todo */ + if (!vdec_dual(vdec)) + p->use_vfm_path = vdec_stream_based(vdec); + /* vdec_dev_reg.flag = 0; */ + if (vdec->id >= 0) + id = vdec->id; + p->dev = platform_device_register_data( + &vdec_core->vdec_core_platform_device->dev, + dev_name, + id, + &p, sizeof(struct vdec_s *)); + + if (IS_ERR(p->dev)) { + r = PTR_ERR(p->dev); + pr_err("vdec: Decoder device %s register failed (%d)\n", + dev_name, r); + + mutex_lock(&vdec_mutex); + inited_vcodec_num--; + mutex_unlock(&vdec_mutex); + + goto error; + } else if (!p->dev->dev.driver) { + pr_info("vdec: Decoder device %s driver probe failed.\n", + dev_name); + r = -ENODEV; + + goto error; + } + + if ((p->type == VDEC_TYPE_FRAME_BLOCK) && (p->run == NULL)) { + r = -ENODEV; + pr_err("vdec: Decoder device not handled (%s)\n", dev_name); + + mutex_lock(&vdec_mutex); + inited_vcodec_num--; + mutex_unlock(&vdec_mutex); + + goto error; + } + + if (p->use_vfm_path) { + vdec->vf_receiver_inst = -1; + vdec->vfm_map_id[0] = 0; + } else if (!vdec_dual(vdec)) { + /* create IONVIDEO instance and connect decoder's + * vf_provider interface to it + */ + if (p->type != VDEC_TYPE_FRAME_BLOCK) { + r = -ENODEV; + pr_err("vdec: Incorrect decoder type\n"); + + mutex_lock(&vdec_mutex); + inited_vcodec_num--; + mutex_unlock(&vdec_mutex); + + goto error; + } + if (p->frame_base_video_path == FRAME_BASE_PATH_IONVIDEO) { +#if 1 + r = ionvideo_assign_map(&vdec->vf_receiver_name, + &vdec->vf_receiver_inst); +#else + /* + * temporarily just use decoder instance ID as iondriver ID + * to solve OMX iondriver instance number check time sequence + * only the limitation is we can NOT mix different video + * decoders since same ID will be used for different decoder + * formats. + */ + vdec->vf_receiver_inst = p->dev->id; + r = ionvideo_assign_map(&vdec->vf_receiver_name, + &vdec->vf_receiver_inst); +#endif + if (r < 0) { + pr_err("IonVideo frame receiver allocation failed.\n"); + + mutex_lock(&vdec_mutex); + inited_vcodec_num--; + mutex_unlock(&vdec_mutex); + + goto error; + } + + snprintf(vdec->vfm_map_chain, VDEC_MAP_NAME_SIZE, + "%s %s", vdec->vf_provider_name, + vdec->vf_receiver_name); + snprintf(vdec->vfm_map_id, VDEC_MAP_NAME_SIZE, + "vdec-map-%d", vdec->id); + } else if (p->frame_base_video_path == + FRAME_BASE_PATH_AMLVIDEO_AMVIDEO) { + snprintf(vdec->vfm_map_chain, VDEC_MAP_NAME_SIZE, + "%s %s", vdec->vf_provider_name, + "amlvideo deinterlace amvideo"); + snprintf(vdec->vfm_map_id, VDEC_MAP_NAME_SIZE, + "vdec-map-%d", vdec->id); + } else if (p->frame_base_video_path == + FRAME_BASE_PATH_AMLVIDEO1_AMVIDEO2) { + snprintf(vdec->vfm_map_chain, VDEC_MAP_NAME_SIZE, + "%s %s", vdec->vf_provider_name, + "ppmgr amlvideo.1 amvide2"); + snprintf(vdec->vfm_map_id, VDEC_MAP_NAME_SIZE, + "vdec-map-%d", vdec->id); + } + + if (vfm_map_add(vdec->vfm_map_id, + vdec->vfm_map_chain) < 0) { + r = -ENOMEM; + pr_err("Decoder pipeline map creation failed %s.\n", + vdec->vfm_map_id); + vdec->vfm_map_id[0] = 0; + + mutex_lock(&vdec_mutex); + inited_vcodec_num--; + mutex_unlock(&vdec_mutex); + + goto error; + } + + pr_debug("vfm map %s created\n", vdec->vfm_map_id); + + /* + *assume IONVIDEO driver already have a few vframe_receiver + * registered. + * 1. Call iondriver function to allocate a IONVIDEO path and + * provide receiver's name and receiver op. + * 2. Get decoder driver's provider name from driver instance + * 3. vfm_map_add(name, " + * "), e.g. + * vfm_map_add("vdec_ion_map_0", "mpeg4_0 iondriver_1"); + * 4. vf_reg_provider and vf_reg_receiver + * Note: the decoder provider's op uses vdec as op_arg + * the iondriver receiver's op uses iondev device as + * op_arg + */ + + } + + if (!vdec_single(vdec)) { + vf_reg_provider(&p->vframe_provider); + + vf_notify_receiver(p->vf_provider_name, + VFRAME_EVENT_PROVIDER_START, + vdec); + + if (vdec_core->hint_fr_vdec == NULL) + vdec_core->hint_fr_vdec = vdec; + + if (vdec_core->hint_fr_vdec == vdec) { + if (p->sys_info->rate != 0) { + if (!vdec->is_reset) + vf_notify_receiver(p->vf_provider_name, + VFRAME_EVENT_PROVIDER_FR_HINT, + (void *) + ((unsigned long) + p->sys_info->rate)); + vdec->fr_hint_state = VDEC_HINTED; + } else { + vdec->fr_hint_state = VDEC_NEED_HINT; + } + } + } + + p->dolby_meta_with_el = 0; + pr_debug("vdec_init, vf_provider_name = %s\n", p->vf_provider_name); + vdec_input_prepare_bufs(/*prepared buffer for fast playing.*/ + &vdec->input, + vdec->sys_info->width, + vdec->sys_info->height); + /* vdec is now ready to be active */ + vdec_set_status(vdec, VDEC_STATUS_DISCONNECTED); + + return 0; + +error: + return r; +} +EXPORT_SYMBOL(vdec_init); + +/* vdec_create/init/release/destroy are applied to both dual running decoders + */ +void vdec_release(struct vdec_s *vdec) +{ + //trace_vdec_release(vdec);/*DEBUG_TMP*/ +#ifdef VDEC_DEBUG_SUPPORT + if (step_mode) { + pr_info("VDEC_DEBUG: in step_mode, wait release\n"); + while (step_mode) + udelay(10); + pr_info("VDEC_DEBUG: step_mode is clear\n"); + } +#endif + vdec_disconnect(vdec); + + if (vdec->vframe_provider.name) { + if (!vdec_single(vdec)) { + if (vdec_core->hint_fr_vdec == vdec + && vdec->fr_hint_state == VDEC_HINTED + && !vdec->is_reset) + vf_notify_receiver( + vdec->vf_provider_name, + VFRAME_EVENT_PROVIDER_FR_END_HINT, + NULL); + vdec->fr_hint_state = VDEC_NO_NEED_HINT; + } + vf_unreg_provider(&vdec->vframe_provider); + } + + if (vdec_core->vfm_vdec == vdec) + vdec_core->vfm_vdec = NULL; + + if (vdec_core->hint_fr_vdec == vdec) + vdec_core->hint_fr_vdec = NULL; + + if (vdec->vf_receiver_inst >= 0) { + if (vdec->vfm_map_id[0]) { + vfm_map_remove(vdec->vfm_map_id); + vdec->vfm_map_id[0] = 0; + } + } + + while ((atomic_read(&vdec->inirq_flag) > 0) + || (atomic_read(&vdec->inirq_thread_flag) > 0)) + schedule(); + + platform_device_unregister(vdec->dev); + vdec_destroy(vdec); + + mutex_lock(&vdec_mutex); + inited_vcodec_num--; + mutex_unlock(&vdec_mutex); + + pr_debug("vdec_release instance %p, total %d\n", vdec, + atomic_read(&vdec_core->vdec_nr)); +} +EXPORT_SYMBOL(vdec_release); + +/* For dual running decoders, vdec_reset is only called with master vdec. + */ +int vdec_reset(struct vdec_s *vdec) +{ + //trace_vdec_reset(vdec); /*DEBUG_TMP*/ + + vdec_disconnect(vdec); + + if (vdec->vframe_provider.name) + vf_unreg_provider(&vdec->vframe_provider); + + if ((vdec->slave) && (vdec->slave->vframe_provider.name)) + vf_unreg_provider(&vdec->slave->vframe_provider); + + if (vdec->reset) { + vdec->reset(vdec); + if (vdec->slave) + vdec->slave->reset(vdec->slave); + } + + vdec_input_release(&vdec->input); + + vf_reg_provider(&vdec->vframe_provider); + vf_notify_receiver(vdec->vf_provider_name, + VFRAME_EVENT_PROVIDER_START, vdec); + + if (vdec->slave) { + vf_reg_provider(&vdec->slave->vframe_provider); + vf_notify_receiver(vdec->slave->vf_provider_name, + VFRAME_EVENT_PROVIDER_START, vdec->slave); + } + + vdec_connect(vdec); + + return 0; +} +EXPORT_SYMBOL(vdec_reset); + +void vdec_free_cmabuf(void) +{ + mutex_lock(&vdec_mutex); + + if (inited_vcodec_num > 0) { + mutex_unlock(&vdec_mutex); + return; + } + mutex_unlock(&vdec_mutex); +} + +int vdec_core_request(struct vdec_s *vdec, unsigned long mask) +{ + vdec->core_mask |= mask; + + if (vdec->slave) + vdec->slave->core_mask |= mask; + + return 0; +} +EXPORT_SYMBOL(vdec_core_request); + +int vdec_core_release(struct vdec_s *vdec, unsigned long mask) +{ + vdec->core_mask &= ~mask; + + if (vdec->slave) + vdec->slave->core_mask &= ~mask; + + return 0; +} +EXPORT_SYMBOL(vdec_core_release); + +const bool vdec_core_with_input(unsigned long mask) +{ + enum vdec_type_e type; + + for (type = VDEC_1; type < VDEC_MAX; type++) { + if ((mask & (1 << type)) && cores_with_input[type]) + return true; + } + + return false; +} + +void vdec_core_finish_run(struct vdec_s *vdec, unsigned long mask) +{ + unsigned long i; + unsigned long t = mask; + + while (t) { + i = __ffs(t); + clear_bit(i, &vdec->active_mask); + t &= ~(1 << i); + } + + if (vdec->active_mask == 0) + vdec_set_status(vdec, VDEC_STATUS_CONNECTED); +} +EXPORT_SYMBOL(vdec_core_finish_run); +/* + * find what core resources are available for vdec + */ +static unsigned long vdec_schedule_mask(struct vdec_s *vdec, + unsigned long active_mask) +{ + unsigned long mask = vdec->core_mask & + ~CORE_MASK_COMBINE; + + if (vdec->core_mask & CORE_MASK_COMBINE) { + /* combined cores must be granted together */ + if ((mask & ~active_mask) == mask) + return mask; + else + return 0; + } else + return mask & ~vdec->sched_mask & ~active_mask; +} + +/* + *Decoder callback + * Each decoder instance uses this callback to notify status change, e.g. when + * decoder finished using HW resource. + * a sample callback from decoder's driver is following: + * + * if (hw->vdec_cb) { + * vdec_set_next_status(vdec, VDEC_STATUS_CONNECTED); + * hw->vdec_cb(vdec, hw->vdec_cb_arg); + * } + */ +static void vdec_callback(struct vdec_s *vdec, void *data) +{ + struct vdec_core_s *core = (struct vdec_core_s *)data; + +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + vdec_profile(vdec, VDEC_PROFILE_EVENT_CB); +#endif + + up(&core->sem); +} + +static irqreturn_t vdec_isr(int irq, void *dev_id) +{ + struct vdec_isr_context_s *c = + (struct vdec_isr_context_s *)dev_id; + struct vdec_s *vdec = vdec_core->active_vdec; + irqreturn_t ret = IRQ_HANDLED; + if (vdec) + atomic_set(&vdec->inirq_flag, 1); + if (c->dev_isr) { + ret = c->dev_isr(irq, c->dev_id); + goto isr_done; + } + + if ((c != &vdec_core->isr_context[VDEC_IRQ_0]) && + (c != &vdec_core->isr_context[VDEC_IRQ_1]) && + (c != &vdec_core->isr_context[VDEC_IRQ_HEVC_BACK])) { +#if 0 + pr_warn("vdec interrupt w/o a valid receiver\n"); +#endif + goto isr_done; + } + + if (!vdec) { +#if 0 + pr_warn("vdec interrupt w/o an active instance running. core = %p\n", + core); +#endif + goto isr_done; + } + + if (!vdec->irq_handler) { +#if 0 + pr_warn("vdec instance has no irq handle.\n"); +#endif + goto isr_done; + } + + ret = vdec->irq_handler(vdec, c->index); +isr_done: + if (vdec) + atomic_set(&vdec->inirq_flag, 0); + return ret; +} + +static irqreturn_t vdec_thread_isr(int irq, void *dev_id) +{ + struct vdec_isr_context_s *c = + (struct vdec_isr_context_s *)dev_id; + struct vdec_s *vdec = vdec_core->active_vdec; + irqreturn_t ret = IRQ_HANDLED; + if (vdec) + atomic_set(&vdec->inirq_thread_flag, 1); + if (c->dev_threaded_isr) { + ret = c->dev_threaded_isr(irq, c->dev_id); + goto thread_isr_done; + } + if (!vdec) + goto thread_isr_done; + + if (!vdec->threaded_irq_handler) + goto thread_isr_done; + ret = vdec->threaded_irq_handler(vdec, c->index); +thread_isr_done: + if (vdec) + atomic_set(&vdec->inirq_thread_flag, 0); + return ret; +} + +unsigned long vdec_ready_to_run(struct vdec_s *vdec, unsigned long mask) +{ + unsigned long ready_mask; + struct vdec_input_s *input = &vdec->input; + if ((vdec->status != VDEC_STATUS_CONNECTED) && + (vdec->status != VDEC_STATUS_ACTIVE)) + return false; + + if (!vdec->run_ready) + return false; + + if ((vdec->slave || vdec->master) && + (vdec->sched == 0)) + return false; +#ifdef VDEC_DEBUG_SUPPORT + inc_profi_count(mask, vdec->check_count); +#endif + if (vdec_core_with_input(mask)) { + /* check frame based input underrun */ + if (input && !input->eos && input_frame_based(input) + && (!vdec_input_next_chunk(input))) { +#ifdef VDEC_DEBUG_SUPPORT + inc_profi_count(mask, vdec->input_underrun_count); +#endif + return false; + } + /* check streaming prepare level threshold if not EOS */ + if (input && input_stream_based(input) && !input->eos) { + u32 rp, wp, level; + + rp = READ_PARSER_REG(PARSER_VIDEO_RP); + wp = READ_PARSER_REG(PARSER_VIDEO_WP); + if (wp < rp) + level = input->size + wp - rp; + else + level = wp - rp; + + if ((level < input->prepare_level) && + (pts_get_rec_num(PTS_TYPE_VIDEO, + vdec->input.total_rd_count) < 2)) { + vdec->need_more_data |= VDEC_NEED_MORE_DATA; +#ifdef VDEC_DEBUG_SUPPORT + inc_profi_count(mask, vdec->input_underrun_count); + if (step_mode & 0x200) { + if ((step_mode & 0xff) == vdec->id) { + step_mode |= 0xff; + return mask; + } + } +#endif + return false; + } else if (level > input->prepare_level) + vdec->need_more_data &= ~VDEC_NEED_MORE_DATA; + } + } + + if (step_mode) { + if ((step_mode & 0xff) != vdec->id) + return 0; + step_mode |= 0xff; /*VDEC_DEBUG_SUPPORT*/ + } + + /*step_mode &= ~0xff; not work for id of 0, removed*/ + +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + vdec_profile(vdec, VDEC_PROFILE_EVENT_CHK_RUN_READY); +#endif + + ready_mask = vdec->run_ready(vdec, mask) & mask; +#ifdef VDEC_DEBUG_SUPPORT + if (ready_mask != mask) + inc_profi_count(ready_mask ^ mask, vdec->not_run_ready_count); +#endif +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + if (ready_mask) + vdec_profile(vdec, VDEC_PROFILE_EVENT_RUN_READY); +#endif + + return ready_mask; +} + +/* bridge on/off vdec's interrupt processing to vdec core */ +static void vdec_route_interrupt(struct vdec_s *vdec, unsigned long mask, + bool enable) +{ + enum vdec_type_e type; + + for (type = VDEC_1; type < VDEC_MAX; type++) { + if (mask & (1 << type)) { + struct vdec_isr_context_s *c = + &vdec_core->isr_context[cores_int[type]]; + if (enable) + c->vdec = vdec; + else if (c->vdec == vdec) + c->vdec = NULL; + } + } +} + +/* + * Set up secure protection for each decoder instance running. + * Note: The operation from REE side only resets memory access + * to a default policy and even a non_secure type will still be + * changed to secure type automatically when secure source is + * detected inside TEE. + * Perform need_more_data checking and set flag is decoder + * is not consuming data. + */ +void vdec_prepare_run(struct vdec_s *vdec, unsigned long mask) +{ + struct vdec_input_s *input = &vdec->input; + int secure = (vdec_secure(vdec)) ? DMC_DEV_TYPE_SECURE : + DMC_DEV_TYPE_NON_SECURE; + + vdec_route_interrupt(vdec, mask, true); + + if (!vdec_core_with_input(mask)) + return; + + if (input->target == VDEC_INPUT_TARGET_VLD) + tee_config_device_secure(DMC_DEV_ID_VDEC, secure); + else if (input->target == VDEC_INPUT_TARGET_HEVC) + tee_config_device_secure(DMC_DEV_ID_HEVC, secure); + + if (vdec_stream_based(vdec) && + ((vdec->need_more_data & VDEC_NEED_MORE_DATA_RUN) && + (vdec->need_more_data & VDEC_NEED_MORE_DATA_DIRTY) == 0)) { + vdec->need_more_data |= VDEC_NEED_MORE_DATA; + } + + vdec->need_more_data |= VDEC_NEED_MORE_DATA_RUN; + vdec->need_more_data &= ~VDEC_NEED_MORE_DATA_DIRTY; +} + +/* struct vdec_core_shread manages all decoder instance in active list. When + * a vdec is added into the active list, it can onlt be in two status: + * VDEC_STATUS_CONNECTED(the decoder does not own HW resource and ready to run) + * VDEC_STATUS_ACTIVE(the decoder owns HW resources and is running). + * Removing a decoder from active list is only performed within core thread. + * Adding a decoder into active list is performed from user thread. + */ +static int vdec_core_thread(void *data) +{ + struct vdec_core_s *core = (struct vdec_core_s *)data; + + struct sched_param param = {.sched_priority = MAX_RT_PRIO - 1}; + + sched_setscheduler(current, SCHED_FIFO, ¶m); + + allow_signal(SIGTERM); + + while (down_interruptible(&core->sem) == 0) { + struct vdec_s *vdec, *tmp, *worker; + unsigned long sched_mask = 0; + LIST_HEAD(disconnecting_list); + + if (kthread_should_stop()) + break; + + /* clean up previous active vdec's input */ + list_for_each_entry(vdec, &core->connected_vdec_list, list) { + unsigned long mask = vdec->sched_mask & + (vdec->active_mask ^ vdec->sched_mask); + + vdec_route_interrupt(vdec, mask, false); + +#ifdef VDEC_DEBUG_SUPPORT + update_profi_clk_stop(vdec, mask, get_current_clk()); +#endif + /* + * If decoder released some core resources (mask), then + * check if these core resources are associated + * with any input side and do input clean up accordingly + */ + if (vdec_core_with_input(mask)) { + struct vdec_input_s *input = &vdec->input; + while (!list_empty( + &input->vframe_chunk_list)) { + struct vframe_chunk_s *chunk = + vdec_input_next_chunk(input); + if (chunk->flag & + VFRAME_CHUNK_FLAG_CONSUMED) + vdec_input_release_chunk(input, + chunk); + else + break; + } + + vdec_save_input_context(vdec); + } + + vdec->sched_mask &= ~mask; + core->sched_mask &= ~mask; + } + + /* + *todo: + * this is the case when the decoder is in active mode and + * the system side wants to stop it. Currently we rely on + * the decoder instance to go back to VDEC_STATUS_CONNECTED + * from VDEC_STATUS_ACTIVE by its own. However, if for some + * reason the decoder can not exist by itself (dead decoding + * or whatever), then we may have to add another vdec API + * to kill the vdec and release its HW resource and make it + * become inactive again. + * if ((core->active_vdec) && + * (core->active_vdec->status == VDEC_STATUS_DISCONNECTED)) { + * } + */ + + /* check disconnected decoders */ + list_for_each_entry_safe(vdec, tmp, + &core->connected_vdec_list, list) { + if ((vdec->status == VDEC_STATUS_CONNECTED) && + (vdec->next_status == VDEC_STATUS_DISCONNECTED)) { + if (core->active_vdec == vdec) + core->active_vdec = NULL; + list_move(&vdec->list, &disconnecting_list); + } + } + + /* elect next vdec to be scheduled */ + vdec = core->active_vdec; + if (vdec) { + vdec = list_entry(vdec->list.next, struct vdec_s, list); + list_for_each_entry_from(vdec, + &core->connected_vdec_list, list) { + sched_mask = vdec_schedule_mask(vdec, + core->sched_mask); + if (!sched_mask) + continue; + sched_mask = vdec_ready_to_run(vdec, + sched_mask); + if (sched_mask) + break; + } + + if (&vdec->list == &core->connected_vdec_list) + vdec = NULL; + } + + if (!vdec) { + /* search from beginning */ + list_for_each_entry(vdec, + &core->connected_vdec_list, list) { + sched_mask = vdec_schedule_mask(vdec, + core->sched_mask); + if (vdec == core->active_vdec) { + if (!sched_mask) { + vdec = NULL; + break; + } + + sched_mask = vdec_ready_to_run(vdec, + sched_mask); + + if (!sched_mask) { + vdec = NULL; + break; + } + break; + } + + if (!sched_mask) + continue; + + sched_mask = vdec_ready_to_run(vdec, + sched_mask); + if (sched_mask) + break; + } + + if (&vdec->list == &core->connected_vdec_list) + vdec = NULL; + } + + worker = vdec; + + if (vdec) { + unsigned long mask = sched_mask; + unsigned long i; + + /* setting active_mask should be atomic. + * it can be modified by decoder driver callbacks. + */ + while (sched_mask) { + i = __ffs(sched_mask); + set_bit(i, &vdec->active_mask); + sched_mask &= ~(1 << i); + } + + /* vdec's sched_mask is only set from core thread */ + vdec->sched_mask |= mask; + + vdec_set_status(vdec, VDEC_STATUS_ACTIVE); + + core->sched_mask |= mask; + core->active_vdec = vdec; +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + vdec_profile(vdec, VDEC_PROFILE_EVENT_RUN); +#endif + vdec_prepare_run(vdec, mask); +#ifdef VDEC_DEBUG_SUPPORT + inc_profi_count(mask, vdec->run_count); + update_profi_clk_run(vdec, mask, get_current_clk()); +#endif + vdec->run(vdec, mask, vdec_callback, core); + + + /* we have some cores scheduled, keep working until + * all vdecs are checked with no cores to schedule + */ + up(&core->sem); + } + + /* remove disconnected decoder from active list */ + list_for_each_entry_safe(vdec, tmp, &disconnecting_list, list) { + list_del(&vdec->list); + vdec_set_status(vdec, VDEC_STATUS_DISCONNECTED); + complete(&vdec->inactive_done); + } + + /* if there is no new work scheduled and nothing + * is running, sleep 20ms + */ + if ((!worker) && (!core->sched_mask)) { + usleep_range(1000, 2000); + up(&core->sem); + } + + } + + return 0; +} + +#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ +static bool test_hevc(u32 decomp_addr, u32 us_delay) +{ + int i; + + /* SW_RESET IPP */ + WRITE_VREG(HEVCD_IPP_TOP_CNTL, 1); + WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0); + + /* initialize all canvas table */ + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0); + for (i = 0; i < 32; i++) + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, + 0x1 | (i << 8) | decomp_addr); + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 1); + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (0<<1) | 1); + for (i = 0; i < 32; i++) + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0); + + /* Initialize mcrcc */ + WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); + WRITE_VREG(HEVCD_MCRCC_CTL2, 0x0); + WRITE_VREG(HEVCD_MCRCC_CTL3, 0x0); + WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); + + /* Decomp initialize */ + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x0); + WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0x0); + + /* Frame level initialization */ + WRITE_VREG(HEVCD_IPP_TOP_FRMCONFIG, 0x100 | (0x100 << 16)); + WRITE_VREG(HEVCD_IPP_TOP_TILECONFIG3, 0x0); + WRITE_VREG(HEVCD_IPP_TOP_LCUCONFIG, 0x1 << 5); + WRITE_VREG(HEVCD_IPP_BITDEPTH_CONFIG, 0x2 | (0x2 << 2)); + + WRITE_VREG(HEVCD_IPP_CONFIG, 0x0); + WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE, 0x0); + + /* Enable SWIMP mode */ + WRITE_VREG(HEVCD_IPP_SWMPREDIF_CONFIG, 0x1); + + /* Enable frame */ + WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x2); + WRITE_VREG(HEVCD_IPP_TOP_FRMCTL, 0x1); + + /* Send SW-command CTB info */ + WRITE_VREG(HEVCD_IPP_SWMPREDIF_CTBINFO, 0x1 << 31); + + /* Send PU_command */ + WRITE_VREG(HEVCD_IPP_SWMPREDIF_PUINFO0, (0x4 << 9) | (0x4 << 16)); + WRITE_VREG(HEVCD_IPP_SWMPREDIF_PUINFO1, 0x1 << 3); + WRITE_VREG(HEVCD_IPP_SWMPREDIF_PUINFO2, 0x0); + WRITE_VREG(HEVCD_IPP_SWMPREDIF_PUINFO3, 0x0); + + udelay(us_delay); + + WRITE_VREG(HEVCD_IPP_DBG_SEL, 0x2 << 4); + + return (READ_VREG(HEVCD_IPP_DBG_DATA) & 3) == 1; +} + +void vdec_power_reset(void) +{ + /* enable vdec1 isolation */ + WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, + READ_AOREG(AO_RTI_GEN_PWR_ISO0) | 0xc0); + /* power off vdec1 memories */ + WRITE_VREG(DOS_MEM_PD_VDEC, 0xffffffffUL); + /* vdec1 power off */ + WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, + READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) | 0xc); + + if (has_vdec2()) { + /* enable vdec2 isolation */ + WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, + READ_AOREG(AO_RTI_GEN_PWR_ISO0) | 0x300); + /* power off vdec2 memories */ + WRITE_VREG(DOS_MEM_PD_VDEC2, 0xffffffffUL); + /* vdec2 power off */ + WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, + READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) | 0x30); + } + + if (has_hdec()) { + /* enable hcodec isolation */ + WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, + READ_AOREG(AO_RTI_GEN_PWR_ISO0) | 0x30); + /* power off hcodec memories */ + WRITE_VREG(DOS_MEM_PD_HCODEC, 0xffffffffUL); + /* hcodec power off */ + WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, + READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) | 3); + } + + if (has_hevc_vdec()) { + /* enable hevc isolation */ + WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, + READ_AOREG(AO_RTI_GEN_PWR_ISO0) | 0xc00); + /* power off hevc memories */ + WRITE_VREG(DOS_MEM_PD_HEVC, 0xffffffffUL); + /* hevc power off */ + WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, + READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) | 0xc0); + } +} +EXPORT_SYMBOL(vdec_power_reset); + +void vdec_poweron(enum vdec_type_e core) +{ + void *decomp_addr = NULL; + dma_addr_t decomp_dma_addr; + u32 decomp_addr_aligned = 0; + int hevc_loop = 0; + + if (core >= VDEC_MAX) + return; + + mutex_lock(&vdec_mutex); + + vdec_core->power_ref_count[core]++; + if (vdec_core->power_ref_count[core] > 1) { + mutex_unlock(&vdec_mutex); + return; + } + + if (vdec_on(core)) { + mutex_unlock(&vdec_mutex); + return; + } + + if (hevc_workaround_needed() && + (core == VDEC_HEVC)) { + decomp_addr = codec_mm_dma_alloc_coherent(MEM_NAME, + SZ_64K + SZ_4K, &decomp_dma_addr, GFP_KERNEL, 0); + + if (decomp_addr) { + decomp_addr_aligned = ALIGN(decomp_dma_addr, SZ_64K); + memset((u8 *)decomp_addr + + (decomp_addr_aligned - decomp_dma_addr), + 0xff, SZ_4K); + } else + pr_err("vdec: alloc HEVC gxbb decomp buffer failed.\n"); + } + + if (core == VDEC_1) { + /* vdec1 power on */ + WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, + READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) & ~0xc); + /* wait 10uS */ + udelay(10); + /* vdec1 soft reset */ + WRITE_VREG(DOS_SW_RESET0, 0xfffffffc); + WRITE_VREG(DOS_SW_RESET0, 0); + /* enable vdec1 clock */ + /* + *add power on vdec clock level setting,only for m8 chip, + * m8baby and m8m2 can dynamic adjust vdec clock, + * power on with default clock level + */ + vdec_clock_hi_enable(); + /* power up vdec memories */ + WRITE_VREG(DOS_MEM_PD_VDEC, 0); + /* remove vdec1 isolation */ + WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, + READ_AOREG(AO_RTI_GEN_PWR_ISO0) & ~0xC0); + /* reset DOS top registers */ + WRITE_VREG(DOS_VDEC_MCRCC_STALL_CTRL, 0); + if (get_cpu_type() >= + MESON_CPU_MAJOR_ID_GXBB) { + /* + *enable VDEC_1 DMC request + */ + unsigned long flags; + + spin_lock_irqsave(&vdec_spin_lock, flags); + codec_dmcbus_write(DMC_REQ_CTRL, + codec_dmcbus_read(DMC_REQ_CTRL) | (1 << 13)); + spin_unlock_irqrestore(&vdec_spin_lock, flags); + } + } else if (core == VDEC_2) { + if (has_vdec2()) { + /* vdec2 power on */ + WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, + READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) & + ~0x30); + /* wait 10uS */ + udelay(10); + /* vdec2 soft reset */ + WRITE_VREG(DOS_SW_RESET2, 0xffffffff); + WRITE_VREG(DOS_SW_RESET2, 0); + /* enable vdec1 clock */ + vdec2_clock_hi_enable(); + /* power up vdec memories */ + WRITE_VREG(DOS_MEM_PD_VDEC2, 0); + /* remove vdec2 isolation */ + WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, + READ_AOREG(AO_RTI_GEN_PWR_ISO0) & + ~0x300); + /* reset DOS top registers */ + WRITE_VREG(DOS_VDEC2_MCRCC_STALL_CTRL, 0); + } + } else if (core == VDEC_HCODEC) { + if (has_hdec()) { + /* hcodec power on */ + WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, + READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) & + ~0x3); + /* wait 10uS */ + udelay(10); + /* hcodec soft reset */ + WRITE_VREG(DOS_SW_RESET1, 0xffffffff); + WRITE_VREG(DOS_SW_RESET1, 0); + /* enable hcodec clock */ + hcodec_clock_enable(); + /* power up hcodec memories */ + WRITE_VREG(DOS_MEM_PD_HCODEC, 0); + /* remove hcodec isolation */ + WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, + READ_AOREG(AO_RTI_GEN_PWR_ISO0) & + ~0x30); + } + } else if (core == VDEC_HEVC) { + if (has_hevc_vdec()) { + bool hevc_fixed = false; + + while (!hevc_fixed) { + /* hevc power on */ + WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, + READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) & + ~0xc0); + /* wait 10uS */ + udelay(10); + /* hevc soft reset */ + WRITE_VREG(DOS_SW_RESET3, 0xffffffff); + WRITE_VREG(DOS_SW_RESET3, 0); + /* enable hevc clock */ + hevc_clock_hi_enable(); + hevc_back_clock_hi_enable(); + /* power up hevc memories */ + WRITE_VREG(DOS_MEM_PD_HEVC, 0); + /* remove hevc isolation */ + WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, + READ_AOREG(AO_RTI_GEN_PWR_ISO0) & + ~0xc00); + + if (!hevc_workaround_needed()) + break; + + if (decomp_addr) + hevc_fixed = test_hevc( + decomp_addr_aligned, 20); + + if (!hevc_fixed) { + hevc_loop++; + + mutex_unlock(&vdec_mutex); + + if (hevc_loop >= HEVC_TEST_LIMIT) { + pr_warn("hevc power sequence over limit\n"); + pr_warn("=====================================================\n"); + pr_warn(" This chip is identified to have HW failure.\n"); + pr_warn(" Please contact sqa-platform to replace the platform.\n"); + pr_warn("=====================================================\n"); + + panic("Force panic for chip detection !!!\n"); + + break; + } + + vdec_poweroff(VDEC_HEVC); + + mdelay(10); + + mutex_lock(&vdec_mutex); + } + } + + if (hevc_loop > hevc_max_reset_count) + hevc_max_reset_count = hevc_loop; + + WRITE_VREG(DOS_SW_RESET3, 0xffffffff); + udelay(10); + WRITE_VREG(DOS_SW_RESET3, 0); + } + } + + if (decomp_addr) + codec_mm_dma_free_coherent(MEM_NAME, + SZ_64K + SZ_4K, decomp_addr, decomp_dma_addr, 0); + + mutex_unlock(&vdec_mutex); +} +EXPORT_SYMBOL(vdec_poweron); + +void vdec_poweroff(enum vdec_type_e core) +{ + if (core >= VDEC_MAX) + return; + + mutex_lock(&vdec_mutex); + + vdec_core->power_ref_count[core]--; + if (vdec_core->power_ref_count[core] > 0) { + mutex_unlock(&vdec_mutex); + return; + } + + if (core == VDEC_1) { + if (get_cpu_type() >= + MESON_CPU_MAJOR_ID_GXBB) { + /* disable VDEC_1 DMC REQ*/ + unsigned long flags; + + spin_lock_irqsave(&vdec_spin_lock, flags); + codec_dmcbus_write(DMC_REQ_CTRL, + codec_dmcbus_read(DMC_REQ_CTRL) & (~(1 << 13))); + spin_unlock_irqrestore(&vdec_spin_lock, flags); + udelay(10); + } + /* enable vdec1 isolation */ + WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, + READ_AOREG(AO_RTI_GEN_PWR_ISO0) | 0xc0); + /* power off vdec1 memories */ + WRITE_VREG(DOS_MEM_PD_VDEC, 0xffffffffUL); + /* disable vdec1 clock */ + vdec_clock_off(); + /* vdec1 power off */ + WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, + READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) | 0xc); + } else if (core == VDEC_2) { + if (has_vdec2()) { + /* enable vdec2 isolation */ + WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, + READ_AOREG(AO_RTI_GEN_PWR_ISO0) | + 0x300); + /* power off vdec2 memories */ + WRITE_VREG(DOS_MEM_PD_VDEC2, 0xffffffffUL); + /* disable vdec2 clock */ + vdec2_clock_off(); + /* vdec2 power off */ + WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, + READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) | + 0x30); + } + } else if (core == VDEC_HCODEC) { + if (has_hdec()) { + /* enable hcodec isolation */ + WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, + READ_AOREG(AO_RTI_GEN_PWR_ISO0) | + 0x30); + /* power off hcodec memories */ + WRITE_VREG(DOS_MEM_PD_HCODEC, 0xffffffffUL); + /* disable hcodec clock */ + hcodec_clock_off(); + /* hcodec power off */ + WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, + READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) | 3); + } + } else if (core == VDEC_HEVC) { + if (has_hevc_vdec()) { + if (no_powerdown == 0) { + /* enable hevc isolation */ + WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, + READ_AOREG(AO_RTI_GEN_PWR_ISO0) | + 0xc00); + /* power off hevc memories */ + WRITE_VREG(DOS_MEM_PD_HEVC, 0xffffffffUL); + + /* disable hevc clock */ + hevc_clock_off(); + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) + hevc_back_clock_off(); + + /* hevc power off */ + WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, + READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) | + 0xc0); + } else { + pr_info("!!!!!!!!not power down\n"); + hevc_reset_core(NULL); + no_powerdown = 0; + } + } + } + mutex_unlock(&vdec_mutex); +} +EXPORT_SYMBOL(vdec_poweroff); + +bool vdec_on(enum vdec_type_e core) +{ + bool ret = false; + + if (core == VDEC_1) { + if (((READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) & 0xc) == 0) && + (READ_HHI_REG(HHI_VDEC_CLK_CNTL) & 0x100)) + ret = true; + } else if (core == VDEC_2) { + if (has_vdec2()) { + if (((READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) & 0x30) == 0) && + (READ_HHI_REG(HHI_VDEC2_CLK_CNTL) & 0x100)) + ret = true; + } + } else if (core == VDEC_HCODEC) { + if (has_hdec()) { + if (((READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) & 0x3) == 0) && + (READ_HHI_REG(HHI_VDEC_CLK_CNTL) & 0x1000000)) + ret = true; + } + } else if (core == VDEC_HEVC) { + if (has_hevc_vdec()) { + if (((READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) & 0xc0) == 0) && + (READ_HHI_REG(HHI_VDEC2_CLK_CNTL) & 0x1000000)) + ret = true; + } + } + + return ret; +} +EXPORT_SYMBOL(vdec_on); + +#elif 0 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6TVD */ +void vdec_poweron(enum vdec_type_e core) +{ + ulong flags; + + spin_lock_irqsave(&lock, flags); + + if (core == VDEC_1) { + /* vdec1 soft reset */ + WRITE_VREG(DOS_SW_RESET0, 0xfffffffc); + WRITE_VREG(DOS_SW_RESET0, 0); + /* enable vdec1 clock */ + vdec_clock_enable(); + /* reset DOS top registers */ + WRITE_VREG(DOS_VDEC_MCRCC_STALL_CTRL, 0); + } else if (core == VDEC_2) { + /* vdec2 soft reset */ + WRITE_VREG(DOS_SW_RESET2, 0xffffffff); + WRITE_VREG(DOS_SW_RESET2, 0); + /* enable vdec2 clock */ + vdec2_clock_enable(); + /* reset DOS top registers */ + WRITE_VREG(DOS_VDEC2_MCRCC_STALL_CTRL, 0); + } else if (core == VDEC_HCODEC) { + /* hcodec soft reset */ + WRITE_VREG(DOS_SW_RESET1, 0xffffffff); + WRITE_VREG(DOS_SW_RESET1, 0); + /* enable hcodec clock */ + hcodec_clock_enable(); + } + + spin_unlock_irqrestore(&lock, flags); +} + +void vdec_poweroff(enum vdec_type_e core) +{ + ulong flags; + + spin_lock_irqsave(&lock, flags); + + if (core == VDEC_1) { + /* disable vdec1 clock */ + vdec_clock_off(); + } else if (core == VDEC_2) { + /* disable vdec2 clock */ + vdec2_clock_off(); + } else if (core == VDEC_HCODEC) { + /* disable hcodec clock */ + hcodec_clock_off(); + } + + spin_unlock_irqrestore(&lock, flags); +} + +bool vdec_on(enum vdec_type_e core) +{ + bool ret = false; + + if (core == VDEC_1) { + if (READ_HHI_REG(HHI_VDEC_CLK_CNTL) & 0x100) + ret = true; + } else if (core == VDEC_2) { + if (READ_HHI_REG(HHI_VDEC2_CLK_CNTL) & 0x100) + ret = true; + } else if (core == VDEC_HCODEC) { + if (READ_HHI_REG(HHI_VDEC_CLK_CNTL) & 0x1000000) + ret = true; + } + + return ret; +} +#endif + +int vdec_source_changed(int format, int width, int height, int fps) +{ + /* todo: add level routines for clock adjustment per chips */ + int ret = -1; + static int on_setting; + + if (on_setting > 0) + return ret;/*on changing clk,ignore this change*/ + + if (vdec_source_get(VDEC_1) == width * height * fps) + return ret; + + + on_setting = 1; + ret = vdec_source_changed_for_clk_set(format, width, height, fps); + pr_debug("vdec1 video changed to %d x %d %d fps clk->%dMHZ\n", + width, height, fps, vdec_clk_get(VDEC_1)); + on_setting = 0; + return ret; + +} +EXPORT_SYMBOL(vdec_source_changed); + +void hevc_reset_core(struct vdec_s *vdec) +{ + unsigned long flags; + WRITE_VREG(HEVC_STREAM_CONTROL, 0); + spin_lock_irqsave(&vdec_spin_lock, flags); + codec_dmcbus_write(DMC_REQ_CTRL, + codec_dmcbus_read(DMC_REQ_CTRL) & (~(1 << 4))); + spin_unlock_irqrestore(&vdec_spin_lock, flags); + + while (!(codec_dmcbus_read(DMC_CHAN_STS) + & (1 << 4))) + ; + + if (vdec == NULL || input_frame_based(vdec)) + WRITE_VREG(HEVC_STREAM_CONTROL, 0); + + /* + * 2: assist + * 3: parser + * 4: parser_state + * 8: dblk + * 11:mcpu + * 12:ccpu + * 13:ddr + * 14:iqit + * 15:ipp + * 17:qdct + * 18:mpred + * 19:sao + * 24:hevc_afifo + */ + WRITE_VREG(DOS_SW_RESET3, + (1<<3)|(1<<4)|(1<<8)|(1<<11)| + (1<<12)|(1<<13)|(1<<14)|(1<<15)| + (1<<17)|(1<<18)|(1<<19)|(1<<24)); + + WRITE_VREG(DOS_SW_RESET3, 0); + + + spin_lock_irqsave(&vdec_spin_lock, flags); + codec_dmcbus_write(DMC_REQ_CTRL, + codec_dmcbus_read(DMC_REQ_CTRL) | (1 << 4)); + spin_unlock_irqrestore(&vdec_spin_lock, flags); + +} +EXPORT_SYMBOL(hevc_reset_core); + +int vdec2_source_changed(int format, int width, int height, int fps) +{ + int ret = -1; + static int on_setting; + + if (has_vdec2()) { + /* todo: add level routines for clock adjustment per chips */ + if (on_setting != 0) + return ret;/*on changing clk,ignore this change*/ + + if (vdec_source_get(VDEC_2) == width * height * fps) + return ret; + + on_setting = 1; + ret = vdec_source_changed_for_clk_set(format, + width, height, fps); + pr_debug("vdec2 video changed to %d x %d %d fps clk->%dMHZ\n", + width, height, fps, vdec_clk_get(VDEC_2)); + on_setting = 0; + return ret; + } + return 0; +} +EXPORT_SYMBOL(vdec2_source_changed); + +int hevc_source_changed(int format, int width, int height, int fps) +{ + /* todo: add level routines for clock adjustment per chips */ + int ret = -1; + static int on_setting; + + if (on_setting != 0) + return ret;/*on changing clk,ignore this change*/ + + if (vdec_source_get(VDEC_HEVC) == width * height * fps) + return ret; + + on_setting = 1; + ret = vdec_source_changed_for_clk_set(format, width, height, fps); + pr_debug("hevc video changed to %d x %d %d fps clk->%dMHZ\n", + width, height, fps, vdec_clk_get(VDEC_HEVC)); + on_setting = 0; + + return ret; +} +EXPORT_SYMBOL(hevc_source_changed); + +static struct am_reg am_risc[] = { + {"MSP", 0x300}, + {"MPSR", 0x301}, + {"MCPU_INT_BASE", 0x302}, + {"MCPU_INTR_GRP", 0x303}, + {"MCPU_INTR_MSK", 0x304}, + {"MCPU_INTR_REQ", 0x305}, + {"MPC-P", 0x306}, + {"MPC-D", 0x307}, + {"MPC_E", 0x308}, + {"MPC_W", 0x309}, + {"CSP", 0x320}, + {"CPSR", 0x321}, + {"CCPU_INT_BASE", 0x322}, + {"CCPU_INTR_GRP", 0x323}, + {"CCPU_INTR_MSK", 0x324}, + {"CCPU_INTR_REQ", 0x325}, + {"CPC-P", 0x326}, + {"CPC-D", 0x327}, + {"CPC_E", 0x328}, + {"CPC_W", 0x329}, + {"AV_SCRATCH_0", 0x09c0}, + {"AV_SCRATCH_1", 0x09c1}, + {"AV_SCRATCH_2", 0x09c2}, + {"AV_SCRATCH_3", 0x09c3}, + {"AV_SCRATCH_4", 0x09c4}, + {"AV_SCRATCH_5", 0x09c5}, + {"AV_SCRATCH_6", 0x09c6}, + {"AV_SCRATCH_7", 0x09c7}, + {"AV_SCRATCH_8", 0x09c8}, + {"AV_SCRATCH_9", 0x09c9}, + {"AV_SCRATCH_A", 0x09ca}, + {"AV_SCRATCH_B", 0x09cb}, + {"AV_SCRATCH_C", 0x09cc}, + {"AV_SCRATCH_D", 0x09cd}, + {"AV_SCRATCH_E", 0x09ce}, + {"AV_SCRATCH_F", 0x09cf}, + {"AV_SCRATCH_G", 0x09d0}, + {"AV_SCRATCH_H", 0x09d1}, + {"AV_SCRATCH_I", 0x09d2}, + {"AV_SCRATCH_J", 0x09d3}, + {"AV_SCRATCH_K", 0x09d4}, + {"AV_SCRATCH_L", 0x09d5}, + {"AV_SCRATCH_M", 0x09d6}, + {"AV_SCRATCH_N", 0x09d7}, +}; + +static ssize_t amrisc_regs_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + char *pbuf = buf; + struct am_reg *regs = am_risc; + int rsize = sizeof(am_risc) / sizeof(struct am_reg); + int i; + unsigned int val; + ssize_t ret; + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) { + mutex_lock(&vdec_mutex); + if (!vdec_on(VDEC_1)) { + mutex_unlock(&vdec_mutex); + pbuf += sprintf(pbuf, "amrisc is power off\n"); + ret = pbuf - buf; + return ret; + } + } else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M6) { + /*TODO:M6 define */ + /* + * switch_mod_gate_by_type(MOD_VDEC, 1); + */ + amports_switch_gate("vdec", 1); + } + pbuf += sprintf(pbuf, "amrisc registers show:\n"); + for (i = 0; i < rsize; i++) { + val = READ_VREG(regs[i].offset); + pbuf += sprintf(pbuf, "%s(%#x)\t:%#x(%d)\n", + regs[i].name, regs[i].offset, val, val); + } + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) + mutex_unlock(&vdec_mutex); + else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M6) { + /*TODO:M6 define */ + /* + * switch_mod_gate_by_type(MOD_VDEC, 0); + */ + amports_switch_gate("vdec", 0); + } + ret = pbuf - buf; + return ret; +} + +static ssize_t dump_trace_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + int i; + char *pbuf = buf; + ssize_t ret; + u16 *trace_buf = kmalloc(debug_trace_num * 2, GFP_KERNEL); + + if (!trace_buf) { + pbuf += sprintf(pbuf, "No Memory bug\n"); + ret = pbuf - buf; + return ret; + } + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) { + mutex_lock(&vdec_mutex); + if (!vdec_on(VDEC_1)) { + mutex_unlock(&vdec_mutex); + kfree(trace_buf); + pbuf += sprintf(pbuf, "amrisc is power off\n"); + ret = pbuf - buf; + return ret; + } + } else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M6) { + /*TODO:M6 define */ + /* + * switch_mod_gate_by_type(MOD_VDEC, 1); + */ + amports_switch_gate("vdec", 1); + } + pr_info("dump trace steps:%d start\n", debug_trace_num); + i = 0; + while (i <= debug_trace_num - 16) { + trace_buf[i] = READ_VREG(MPC_E); + trace_buf[i + 1] = READ_VREG(MPC_E); + trace_buf[i + 2] = READ_VREG(MPC_E); + trace_buf[i + 3] = READ_VREG(MPC_E); + trace_buf[i + 4] = READ_VREG(MPC_E); + trace_buf[i + 5] = READ_VREG(MPC_E); + trace_buf[i + 6] = READ_VREG(MPC_E); + trace_buf[i + 7] = READ_VREG(MPC_E); + trace_buf[i + 8] = READ_VREG(MPC_E); + trace_buf[i + 9] = READ_VREG(MPC_E); + trace_buf[i + 10] = READ_VREG(MPC_E); + trace_buf[i + 11] = READ_VREG(MPC_E); + trace_buf[i + 12] = READ_VREG(MPC_E); + trace_buf[i + 13] = READ_VREG(MPC_E); + trace_buf[i + 14] = READ_VREG(MPC_E); + trace_buf[i + 15] = READ_VREG(MPC_E); + i += 16; + }; + pr_info("dump trace steps:%d finished\n", debug_trace_num); + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) + mutex_unlock(&vdec_mutex); + else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M6) { + /*TODO:M6 define */ + /* + * switch_mod_gate_by_type(MOD_VDEC, 0); + */ + amports_switch_gate("vdec", 0); + } + for (i = 0; i < debug_trace_num; i++) { + if (i % 4 == 0) { + if (i % 16 == 0) + pbuf += sprintf(pbuf, "\n"); + else if (i % 8 == 0) + pbuf += sprintf(pbuf, " "); + else /* 4 */ + pbuf += sprintf(pbuf, " "); + } + pbuf += sprintf(pbuf, "%04x:", trace_buf[i]); + } + while (i < debug_trace_num) + ; + kfree(trace_buf); + pbuf += sprintf(pbuf, "\n"); + ret = pbuf - buf; + return ret; +} + +static ssize_t clock_level_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + char *pbuf = buf; + size_t ret; + + pbuf += sprintf(pbuf, "%dMHZ\n", vdec_clk_get(VDEC_1)); + + if (has_vdec2()) + pbuf += sprintf(pbuf, "%dMHZ\n", vdec_clk_get(VDEC_2)); + + if (has_hevc_vdec()) + pbuf += sprintf(pbuf, "%dMHZ\n", vdec_clk_get(VDEC_HEVC)); + + ret = pbuf - buf; + return ret; +} + +static ssize_t store_poweron_clock_level(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size) +{ + unsigned int val; + ssize_t ret; + + /*ret = sscanf(buf, "%d", &val);*/ + ret = kstrtoint(buf, 0, &val); + + if (ret != 0) + return -EINVAL; + poweron_clock_level = val; + return size; +} + +static ssize_t show_poweron_clock_level(struct class *class, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", poweron_clock_level); +} + +/* + *if keep_vdec_mem == 1 + *always don't release + *vdec 64 memory for fast play. + */ +static ssize_t store_keep_vdec_mem(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size) +{ + unsigned int val; + ssize_t ret; + + /*ret = sscanf(buf, "%d", &val);*/ + ret = kstrtoint(buf, 0, &val); + if (ret != 0) + return -EINVAL; + keep_vdec_mem = val; + return size; +} + +static ssize_t show_keep_vdec_mem(struct class *class, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", keep_vdec_mem); +} + +#ifdef VDEC_DEBUG_SUPPORT +static ssize_t store_debug(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size) +{ + struct vdec_s *vdec; + struct vdec_core_s *core = vdec_core; + unsigned long flags; + + unsigned id; + unsigned val; + ssize_t ret; + char cbuf[32]; + + cbuf[0] = 0; + ret = sscanf(buf, "%s %x %x", cbuf, &id, &val); + /*pr_info( + "%s(%s)=>ret %ld: %s, %x, %x\n", + __func__, buf, ret, cbuf, id, val);*/ + if (strcmp(cbuf, "schedule") == 0) { + pr_info("VDEC_DEBUG: force schedule\n"); + up(&core->sem); + } else if (strcmp(cbuf, "power_off") == 0) { + pr_info("VDEC_DEBUG: power off core %d\n", id); + vdec_poweroff(id); + } else if (strcmp(cbuf, "power_on") == 0) { + pr_info("VDEC_DEBUG: power_on core %d\n", id); + vdec_poweron(id); + } else if (strcmp(cbuf, "wr") == 0) { + pr_info("VDEC_DEBUG: WRITE_VREG(0x%x, 0x%x)\n", + id, val); + WRITE_VREG(id, val); + } else if (strcmp(cbuf, "rd") == 0) { + pr_info("VDEC_DEBUG: READ_VREG(0x%x) = 0x%x\n", + id, READ_VREG(id)); + } else if (strcmp(cbuf, "read_hevc_clk_reg") == 0) { + pr_info( + "VDEC_DEBUG: HHI_VDEC4_CLK_CNTL = 0x%x, HHI_VDEC2_CLK_CNTL = 0x%x\n", + READ_HHI_REG(HHI_VDEC4_CLK_CNTL), + READ_HHI_REG(HHI_VDEC2_CLK_CNTL)); + } + + flags = vdec_core_lock(vdec_core); + + list_for_each_entry(vdec, + &core->connected_vdec_list, list) { + pr_info("vdec: status %d, id %d\n", vdec->status, vdec->id); + if (((vdec->status == VDEC_STATUS_CONNECTED + || vdec->status == VDEC_STATUS_ACTIVE)) && + (vdec->id == id)) { + /*to add*/ + break; + } + } + vdec_core_unlock(vdec_core, flags); + return size; +} + +static ssize_t show_debug(struct class *class, + struct class_attribute *attr, char *buf) +{ + char *pbuf = buf; + struct vdec_s *vdec; + struct vdec_core_s *core = vdec_core; + unsigned long flags = vdec_core_lock(vdec_core); + + pbuf += sprintf(pbuf, + "============== help:\n"); + pbuf += sprintf(pbuf, + "'echo xxx > debug' usuage:\n"); + pbuf += sprintf(pbuf, + "schedule - trigger schedule thread to run\n"); + pbuf += sprintf(pbuf, + "power_off core_num - call vdec_poweroff(core_num)\n"); + pbuf += sprintf(pbuf, + "power_on core_num - call vdec_poweron(core_num)\n"); + pbuf += sprintf(pbuf, + "wr adr val - call WRITE_VREG(adr, val)\n"); + pbuf += sprintf(pbuf, + "rd adr - call READ_VREG(adr)\n"); + pbuf += sprintf(pbuf, + "read_hevc_clk_reg - read HHI register for hevc clk\n"); + pbuf += sprintf(pbuf, + "===================\n"); + + pbuf += sprintf(pbuf, + "name(core)\tschedule_count\trun_count\tinput_underrun\tdecbuf_not_ready\trun_time\n"); + list_for_each_entry(vdec, + &core->connected_vdec_list, list) { + enum vdec_type_e type; + if ((vdec->status == VDEC_STATUS_CONNECTED + || vdec->status == VDEC_STATUS_ACTIVE)) { + for (type = VDEC_1; type < VDEC_MAX; type++) { + if (vdec->core_mask & (1 << type)) { + pbuf += sprintf(pbuf, "%s(%d):", + vdec->vf_provider_name, type); + pbuf += sprintf(pbuf, "\t%d", + vdec->check_count[type]); + pbuf += sprintf(pbuf, "\t%d", + vdec->run_count[type]); + pbuf += sprintf(pbuf, "\t%d", + vdec->input_underrun_count[type]); + pbuf += sprintf(pbuf, "\t%d", + vdec->not_run_ready_count[type]); + pbuf += sprintf(pbuf, + "\t%d%%\n", + vdec->total_clk[type] == 0 ? 0 : + (u32)((vdec->run_clk[type] * 100) + / vdec->total_clk[type])); + } + } + } + } + + vdec_core_unlock(vdec_core, flags); + return pbuf - buf; + +} +#endif + +/*irq num as same as .dts*/ +/* + * interrupts = <0 3 1 + * 0 23 1 + * 0 32 1 + * 0 43 1 + * 0 44 1 + * 0 45 1>; + * interrupt-names = "vsync", + * "demux", + * "parser", + * "mailbox_0", + * "mailbox_1", + * "mailbox_2"; + */ +s32 vdec_request_threaded_irq(enum vdec_irq_num num, + irq_handler_t handler, + irq_handler_t thread_fn, + unsigned long irqflags, + const char *devname, void *dev) +{ + s32 res_irq; + s32 ret = 0; + + if (num >= VDEC_IRQ_MAX) { + pr_err("[%s] request irq error, irq num too big!", __func__); + return -EINVAL; + } + + if (vdec_core->isr_context[num].irq < 0) { + res_irq = platform_get_irq( + vdec_core->vdec_core_platform_device, num); + if (res_irq < 0) { + pr_err("[%s] get irq error!", __func__); + return -EINVAL; + } + + vdec_core->isr_context[num].irq = res_irq; + vdec_core->isr_context[num].dev_isr = handler; + vdec_core->isr_context[num].dev_threaded_isr = thread_fn; + vdec_core->isr_context[num].dev_id = dev; + + ret = request_threaded_irq(res_irq, + vdec_isr, + vdec_thread_isr, + (thread_fn) ? IRQF_ONESHOT : irqflags, + devname, + &vdec_core->isr_context[num]); + + if (ret) { + vdec_core->isr_context[num].irq = -1; + vdec_core->isr_context[num].dev_isr = NULL; + vdec_core->isr_context[num].dev_threaded_isr = NULL; + vdec_core->isr_context[num].dev_id = NULL; + + pr_err("vdec irq register error for %s.\n", devname); + return -EIO; + } + } else { + vdec_core->isr_context[num].dev_isr = handler; + vdec_core->isr_context[num].dev_threaded_isr = thread_fn; + vdec_core->isr_context[num].dev_id = dev; + } + + return ret; +} +EXPORT_SYMBOL(vdec_request_threaded_irq); + +s32 vdec_request_irq(enum vdec_irq_num num, irq_handler_t handler, + const char *devname, void *dev) +{ + pr_debug("vdec_request_irq %p, %s\n", handler, devname); + + return vdec_request_threaded_irq(num, + handler, + NULL,/*no thread_fn*/ + IRQF_SHARED, + devname, + dev); +} +EXPORT_SYMBOL(vdec_request_irq); + +void vdec_free_irq(enum vdec_irq_num num, void *dev) +{ + if (num >= VDEC_IRQ_MAX) { + pr_err("[%s] request irq error, irq num too big!", __func__); + return; + } + /* + *assume amrisc is stopped already and there is no mailbox interrupt + * when we reset pointers here. + */ + vdec_core->isr_context[num].dev_isr = NULL; + vdec_core->isr_context[num].dev_threaded_isr = NULL; + vdec_core->isr_context[num].dev_id = NULL; + synchronize_irq(vdec_core->isr_context[num].irq); +} +EXPORT_SYMBOL(vdec_free_irq); + +struct vdec_s *vdec_get_default_vdec_for_userdata(void) +{ + struct vdec_s *vdec; + struct vdec_s *ret_vdec; + struct vdec_core_s *core = vdec_core; + unsigned long flags; + int id; + + flags = vdec_core_lock(vdec_core); + + id = 0x10000000; + ret_vdec = NULL; + if (!list_empty(&core->connected_vdec_list)) { + list_for_each_entry(vdec, &core->connected_vdec_list, list) { + if (vdec->id < id) { + id = vdec->id; + ret_vdec = vdec; + } + } + } + + vdec_core_unlock(vdec_core, flags); + + return ret_vdec; +} +EXPORT_SYMBOL(vdec_get_default_vdec_for_userdata); + +int vdec_read_user_data(struct vdec_s *vdec, + struct userdata_param_t *p_userdata_param) +{ + int ret = 0; + + if (!vdec) + vdec = vdec_get_default_vdec_for_userdata(); + + if (vdec) { + if (vdec->user_data_read) + ret = vdec->user_data_read(vdec, p_userdata_param); + } + return ret; +} +EXPORT_SYMBOL(vdec_read_user_data); + +int vdec_wakeup_userdata_poll(struct vdec_s *vdec) +{ + /*if (vdec && vdec == vdec_get_default_vdec_for_userdata()) + amstream_wakeup_userdata_poll();*/ //DEBUG_TMP + + return 0; +} +EXPORT_SYMBOL(vdec_wakeup_userdata_poll); + +void vdec_reset_userdata_fifo(struct vdec_s *vdec, int bInit) +{ + if (!vdec) + vdec = vdec_get_default_vdec_for_userdata(); + + if (vdec) { + if (vdec->reset_userdata_fifo) + vdec->reset_userdata_fifo(vdec, bInit); + } +} +EXPORT_SYMBOL(vdec_reset_userdata_fifo); + +static int dump_mode; +static ssize_t dump_risc_mem_store(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size)/*set*/ +{ + unsigned int val; + ssize_t ret; + char dump_mode_str[4] = "PRL"; + + /*ret = sscanf(buf, "%d", &val);*/ + ret = kstrtoint(buf, 0, &val); + + if (ret != 0) + return -EINVAL; + dump_mode = val & 0x3; + pr_info("set dump mode to %d,%c_mem\n", + dump_mode, dump_mode_str[dump_mode]); + return size; +} +static u32 read_amrisc_reg(int reg) +{ + WRITE_VREG(0x31b, reg); + return READ_VREG(0x31c); +} + +static void dump_pmem(void) +{ + int i; + + WRITE_VREG(0x301, 0x8000); + WRITE_VREG(0x31d, 0); + pr_info("start dump amrisc pmem of risc\n"); + for (i = 0; i < 0xfff; i++) { + /*same as .o format*/ + pr_info("%08x // 0x%04x:\n", read_amrisc_reg(i), i); + } +} + +static void dump_lmem(void) +{ + int i; + + WRITE_VREG(0x301, 0x8000); + WRITE_VREG(0x31d, 2); + pr_info("start dump amrisc lmem\n"); + for (i = 0; i < 0x3ff; i++) { + /*same as */ + pr_info("[%04x] = 0x%08x:\n", i, read_amrisc_reg(i)); + } +} + +static ssize_t dump_risc_mem_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + char *pbuf = buf; + int ret; + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) { + mutex_lock(&vdec_mutex); + if (!vdec_on(VDEC_1)) { + mutex_unlock(&vdec_mutex); + pbuf += sprintf(pbuf, "amrisc is power off\n"); + ret = pbuf - buf; + return ret; + } + } else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M6) { + /*TODO:M6 define */ + /* + * switch_mod_gate_by_type(MOD_VDEC, 1); + */ + amports_switch_gate("vdec", 1); + } + /*start do**/ + switch (dump_mode) { + case 0: + dump_pmem(); + break; + case 2: + dump_lmem(); + break; + default: + break; + } + + /*done*/ + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) + mutex_unlock(&vdec_mutex); + else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M6) { + /*TODO:M6 define */ + /* + * switch_mod_gate_by_type(MOD_VDEC, 0); + */ + amports_switch_gate("vdec", 0); + } + return sprintf(buf, "done\n"); +} + +static ssize_t core_show(struct class *class, struct class_attribute *attr, + char *buf) +{ + struct vdec_core_s *core = vdec_core; + char *pbuf = buf; + + if (list_empty(&core->connected_vdec_list)) + pbuf += sprintf(pbuf, "connected vdec list empty\n"); + else { + struct vdec_s *vdec; + + pbuf += sprintf(pbuf, + " Core: last_sched %p, sched_mask %lx\n", + core->active_vdec, + core->sched_mask); + + list_for_each_entry(vdec, &core->connected_vdec_list, list) { + pbuf += sprintf(pbuf, + "\tvdec.%d (%p (%s)), status = %s,\ttype = %s, \tactive_mask = %lx\n", + vdec->id, + vdec, + vdec_device_name[vdec->format * 2], + vdec_status_str(vdec), + vdec_type_str(vdec), + vdec->active_mask); + } + } + + return pbuf - buf; +} + +static ssize_t vdec_status_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + char *pbuf = buf; + struct vdec_s *vdec; + struct vdec_info vs; + unsigned char vdec_num = 0; + struct vdec_core_s *core = vdec_core; + unsigned long flags = vdec_core_lock(vdec_core); + + if (list_empty(&core->connected_vdec_list)) { + pbuf += sprintf(pbuf, "No vdec.\n"); + goto out; + } + + list_for_each_entry(vdec, &core->connected_vdec_list, list) { + if (VDEC_STATUS_CONNECTED == vdec->status) { + memset(&vs, 0, sizeof(vs)); + if (vdec_status(vdec, &vs)) { + pbuf += sprintf(pbuf, "err.\n"); + goto out; + } + pbuf += sprintf(pbuf, + "vdec channel %u statistics:\n", + vdec_num); + pbuf += sprintf(pbuf, + "%13s : %s\n", "device name", + vs.vdec_name); + pbuf += sprintf(pbuf, + "%13s : %u\n", "frame width", + vs.frame_width); + pbuf += sprintf(pbuf, + "%13s : %u\n", "frame height", + vs.frame_height); + pbuf += sprintf(pbuf, + "%13s : %u %s\n", "frame rate", + vs.frame_rate, "fps"); + pbuf += sprintf(pbuf, + "%13s : %u %s\n", "bit rate", + vs.bit_rate / 1024 * 8, "kbps"); + pbuf += sprintf(pbuf, + "%13s : %u\n", "status", + vs.status); + pbuf += sprintf(pbuf, + "%13s : %u\n", "frame dur", + vs.frame_dur); + pbuf += sprintf(pbuf, + "%13s : %u %s\n", "frame data", + vs.frame_data / 1024, "KB"); + pbuf += sprintf(pbuf, + "%13s : %u\n", "frame count", + vs.frame_count); + pbuf += sprintf(pbuf, + "%13s : %u\n", "drop count", + vs.drop_frame_count); + pbuf += sprintf(pbuf, + "%13s : %u\n", "fra err count", + vs.error_frame_count); + pbuf += sprintf(pbuf, + "%13s : %u\n", "hw err count", + vs.error_count); + pbuf += sprintf(pbuf, + "%13s : %llu %s\n\n", "total data", + vs.total_data / 1024, "KB"); + + vdec_num++; + } + } +out: + vdec_core_unlock(vdec_core, flags); + return pbuf - buf; +} + +static ssize_t dump_vdec_blocks_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + struct vdec_core_s *core = vdec_core; + char *pbuf = buf; + + if (list_empty(&core->connected_vdec_list)) + pbuf += sprintf(pbuf, "connected vdec list empty\n"); + else { + struct vdec_s *vdec; + list_for_each_entry(vdec, &core->connected_vdec_list, list) { + pbuf += vdec_input_dump_blocks(&vdec->input, + pbuf, PAGE_SIZE - (pbuf - buf)); + } + } + + return pbuf - buf; +} +static ssize_t dump_vdec_chunks_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + struct vdec_core_s *core = vdec_core; + char *pbuf = buf; + + if (list_empty(&core->connected_vdec_list)) + pbuf += sprintf(pbuf, "connected vdec list empty\n"); + else { + struct vdec_s *vdec; + list_for_each_entry(vdec, &core->connected_vdec_list, list) { + pbuf += vdec_input_dump_chunks(&vdec->input, + pbuf, PAGE_SIZE - (pbuf - buf)); + } + } + + return pbuf - buf; +} + +static ssize_t dump_decoder_state_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + char *pbuf = buf; + struct vdec_s *vdec; + struct vdec_core_s *core = vdec_core; + unsigned long flags = vdec_core_lock(vdec_core); + + if (list_empty(&core->connected_vdec_list)) { + pbuf += sprintf(pbuf, "No vdec.\n"); + } else { + list_for_each_entry(vdec, + &core->connected_vdec_list, list) { + if ((vdec->status == VDEC_STATUS_CONNECTED + || vdec->status == VDEC_STATUS_ACTIVE) + && vdec->dump_state) + vdec->dump_state(vdec); + } + } + vdec_core_unlock(vdec_core, flags); + + return pbuf - buf; +} + + + +static struct class_attribute vdec_class_attrs[] = { + __ATTR_RO(amrisc_regs), + __ATTR_RO(dump_trace), + __ATTR_RO(clock_level), + __ATTR(poweron_clock_level, S_IRUGO | S_IWUSR | S_IWGRP, + show_poweron_clock_level, store_poweron_clock_level), + __ATTR(dump_risc_mem, S_IRUGO | S_IWUSR | S_IWGRP, + dump_risc_mem_show, dump_risc_mem_store), + __ATTR(keep_vdec_mem, S_IRUGO | S_IWUSR | S_IWGRP, + show_keep_vdec_mem, store_keep_vdec_mem), + __ATTR_RO(core), + __ATTR_RO(vdec_status), + __ATTR_RO(dump_vdec_blocks), + __ATTR_RO(dump_vdec_chunks), + __ATTR_RO(dump_decoder_state), +#ifdef VDEC_DEBUG_SUPPORT + __ATTR(debug, S_IRUGO | S_IWUSR | S_IWGRP, + show_debug, store_debug), +#endif + __ATTR_NULL +}; + +static struct class vdec_class = { + .name = "vdec", + .class_attrs = vdec_class_attrs, + }; + +struct device *get_vdec_device(void) +{ + return &vdec_core->vdec_core_platform_device->dev; +} +EXPORT_SYMBOL(get_vdec_device); + +static int vdec_probe(struct platform_device *pdev) +{ + s32 i, r; + + vdec_core = (struct vdec_core_s *)devm_kzalloc(&pdev->dev, + sizeof(struct vdec_core_s), GFP_KERNEL); + if (vdec_core == NULL) { + pr_err("vdec core allocation failed.\n"); + return -ENOMEM; + } + + atomic_set(&vdec_core->vdec_nr, 0); + sema_init(&vdec_core->sem, 1); + + r = class_register(&vdec_class); + if (r) { + pr_info("vdec class create fail.\n"); + return r; + } + + vdec_core->vdec_core_platform_device = pdev; + + platform_set_drvdata(pdev, vdec_core); + + for (i = 0; i < VDEC_IRQ_MAX; i++) { + vdec_core->isr_context[i].index = i; + vdec_core->isr_context[i].irq = -1; + } + + r = vdec_request_threaded_irq(VDEC_IRQ_0, NULL, NULL, + IRQF_ONESHOT, "vdec-0", NULL); + if (r < 0) { + pr_err("vdec interrupt request failed\n"); + return r; + } + + r = vdec_request_threaded_irq(VDEC_IRQ_1, NULL, NULL, + IRQF_ONESHOT, "vdec-1", NULL); + if (r < 0) { + pr_err("vdec interrupt request failed\n"); + return r; + } +#if 0 + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) { + r = vdec_request_threaded_irq(VDEC_IRQ_HEVC_BACK, NULL, NULL, + IRQF_ONESHOT, "vdec-hevc_back", NULL); + if (r < 0) { + pr_err("vdec interrupt request failed\n"); + return r; + } + } +#endif + r = of_reserved_mem_device_init(&pdev->dev); + if (r == 0) + pr_info("vdec_probe done\n"); + + vdec_core->cma_dev = &pdev->dev; + + if (get_cpu_type() < MESON_CPU_MAJOR_ID_M8) { + /* default to 250MHz */ + vdec_clock_hi_enable(); + } + + if (get_cpu_type() == MESON_CPU_MAJOR_ID_GXBB) { + /* set vdec dmc request to urgent */ + WRITE_DMCREG(DMC_AM5_CHAN_CTRL, 0x3f203cf); + } + INIT_LIST_HEAD(&vdec_core->connected_vdec_list); + spin_lock_init(&vdec_core->lock); + ida_init(&vdec_core->ida); + vdec_core->thread = kthread_run(vdec_core_thread, vdec_core, + "vdec-core"); + + vdec_core->vdec_core_wq = create_singlethread_workqueue("threadvdec"); + + return 0; +} + +static int vdec_remove(struct platform_device *pdev) +{ + int i; + + for (i = 0; i < VDEC_IRQ_MAX; i++) { + if (vdec_core->isr_context[i].irq >= 0) { + free_irq(vdec_core->isr_context[i].irq, + &vdec_core->isr_context[i]); + vdec_core->isr_context[i].irq = -1; + vdec_core->isr_context[i].dev_isr = NULL; + vdec_core->isr_context[i].dev_threaded_isr = NULL; + vdec_core->isr_context[i].dev_id = NULL; + } + } + + kthread_stop(vdec_core->thread); + + destroy_workqueue(vdec_core->vdec_core_wq); + class_unregister(&vdec_class); + + return 0; +} + +static const struct of_device_id amlogic_vdec_dt_match[] = { + { + .compatible = "amlogic, vdec", + }, + {}, +}; + +static struct mconfig vdec_configs[] = { + MC_PU32("debug_trace_num", &debug_trace_num), + MC_PI32("hevc_max_reset_count", &hevc_max_reset_count), + MC_PU32("clk_config", &clk_config), + MC_PI32("step_mode", &step_mode), + MC_PI32("poweron_clock_level", &poweron_clock_level), +}; +static struct mconfig_node vdec_node; + +static struct platform_driver vdec_driver = { + .probe = vdec_probe, + .remove = vdec_remove, + .driver = { + .name = "vdec", + .of_match_table = amlogic_vdec_dt_match, + } +}; + +int vdec_module_init(void) +{ + if (platform_driver_register(&vdec_driver)) { + pr_info("failed to register vdec module\n"); + return -ENODEV; + } + INIT_REG_NODE_CONFIGS("media.decoder", &vdec_node, + "vdec", vdec_configs, CONFIG_FOR_RW); + return 0; +} +EXPORT_SYMBOL(vdec_module_init); + +void vdec_module_exit(void) +{ + platform_driver_unregister(&vdec_driver); +} +EXPORT_SYMBOL(vdec_module_exit); + +#if 0 +static int __init vdec_module_init(void) +{ + if (platform_driver_register(&vdec_driver)) { + pr_info("failed to register vdec module\n"); + return -ENODEV; + } + INIT_REG_NODE_CONFIGS("media.decoder", &vdec_node, + "vdec", vdec_configs, CONFIG_FOR_RW); + return 0; +} + +static void __exit vdec_module_exit(void) +{ + platform_driver_unregister(&vdec_driver); +} +#endif + +static int vdec_mem_device_init(struct reserved_mem *rmem, struct device *dev) +{ + vdec_core->cma_dev = dev; + + return 0; +} + +static const struct reserved_mem_ops rmem_vdec_ops = { + .device_init = vdec_mem_device_init, +}; + +static int __init vdec_mem_setup(struct reserved_mem *rmem) +{ + rmem->ops = &rmem_vdec_ops; + pr_info("vdec: reserved mem setup\n"); + + return 0; +} + +RESERVEDMEM_OF_DECLARE(vdec, "amlogic, vdec-memory", vdec_mem_setup); +/* +uint force_hevc_clock_cntl; +EXPORT_SYMBOL(force_hevc_clock_cntl); + +module_param(force_hevc_clock_cntl, uint, 0664); +*/ +module_param(debug_trace_num, uint, 0664); +module_param(hevc_max_reset_count, int, 0664); +module_param(clk_config, uint, 0664); +module_param(step_mode, int, 0664); +module_param(debugflags, int, 0664); + +/* +*module_init(vdec_module_init); +*module_exit(vdec_module_exit); +*/ +#define CREATE_TRACE_POINTS +#include "vdec_trace.h" +MODULE_DESCRIPTION("AMLOGIC vdec driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Tim Yao "); diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec.h b/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec.h new file mode 100644 index 000000000000..90158f300eae --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec.h @@ -0,0 +1,420 @@ +/* + * drivers/amlogic/media/frame_provider/decoder/utils/vdec.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef VDEC_H +#define VDEC_H +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/*#define CONFIG_AM_VDEC_DV*/ + +#include "vdec_input.h" + +s32 vdec_dev_register(void); +s32 vdec_dev_unregister(void); + +int vdec_source_changed(int format, int width, int height, int fps); +int vdec2_source_changed(int format, int width, int height, int fps); +int hevc_source_changed(int format, int width, int height, int fps); +struct device *get_vdec_device(void); +int vdec_module_init(void); +void vdec_module_exit(void); + +#define VDEC_DEBUG_SUPPORT + +#define DEC_FLAG_HEVC_WORKAROUND 0x01 + +#define VDEC_FIFO_ALIGN 8 + +enum vdec_type_e { + VDEC_1 = 0, + VDEC_HCODEC, + VDEC_2, + VDEC_HEVC, + VDEC_HEVCB, + VDEC_MAX +}; + +#define CORE_MASK_VDEC_1 (1 << VDEC_1) +#define CORE_MASK_HCODEC (1 << VDEC_HCODEC) +#define CORE_MASK_VDEC_2 (1 << VDEC_2) +#define CORE_MASK_HEVC (1 << VDEC_HEVC) +#define CORE_MASK_HEVC_FRONT (1 << VDEC_HEVC) +#define CORE_MASK_HEVC_BACK (1 << VDEC_HEVCB) +#define CORE_MASK_COMBINE (1UL << 31) + +extern void vdec2_power_mode(int level); +extern void vdec_poweron(enum vdec_type_e core); +extern void vdec_poweroff(enum vdec_type_e core); +extern bool vdec_on(enum vdec_type_e core); +extern void vdec_power_reset(void); + +/*irq num as same as .dts*/ + +/* + * interrupts = <0 3 1 + * 0 23 1 + * 0 32 1 + * 0 43 1 + * 0 44 1 + * 0 45 1>; + * interrupt-names = "vsync", + * "demux", + * "parser", + * "mailbox_0", + * "mailbox_1", + * "mailbox_2"; + */ +enum vdec_irq_num { + VSYNC_IRQ = 0, + DEMUX_IRQ, + PARSER_IRQ, + VDEC_IRQ_0, + VDEC_IRQ_1, + VDEC_IRQ_2, + VDEC_IRQ_HEVC_BACK, + VDEC_IRQ_MAX, +}; + +enum vdec_fr_hint_state { + VDEC_NO_NEED_HINT = 0, + VDEC_NEED_HINT, + VDEC_HINTED, +}; +extern s32 vdec_request_threaded_irq(enum vdec_irq_num num, + irq_handler_t handler, + irq_handler_t thread_fn, + unsigned long irqflags, + const char *devname, void *dev); +extern s32 vdec_request_irq(enum vdec_irq_num num, irq_handler_t handler, + const char *devname, void *dev); +extern void vdec_free_irq(enum vdec_irq_num num, void *dev); + +extern void dma_contiguous_early_fixup(phys_addr_t base, unsigned long size); +unsigned int get_vdec_clk_config_settings(void); +void update_vdec_clk_config_settings(unsigned int config); +//unsigned int get_mmu_mode(void);//DEBUG_TMP + +struct vdec_s; +enum vformat_t; + +/* stream based with single instance decoder driver */ +#define VDEC_TYPE_SINGLE 0 + +/* stream based with multi-instance decoder with HW resouce sharing */ +#define VDEC_TYPE_STREAM_PARSER 1 + +/* frame based with multi-instance decoder, input block list based */ +#define VDEC_TYPE_FRAME_BLOCK 2 + +/* frame based with multi-instance decoder, single circular input block */ +#define VDEC_TYPE_FRAME_CIRCULAR 3 + +/* decoder status: uninitialized */ +#define VDEC_STATUS_UNINITIALIZED 0 + +/* decoder status: before the decoder can start consuming data */ +#define VDEC_STATUS_DISCONNECTED 1 + +/* decoder status: decoder should become disconnected once it's not active */ +#define VDEC_STATUS_CONNECTED 2 + +/* decoder status: decoder owns HW resource and is running */ +#define VDEC_STATUS_ACTIVE 3 + +#define VDEC_PROVIDER_NAME_SIZE 16 +#define VDEC_RECEIVER_NAME_SIZE 16 +#define VDEC_MAP_NAME_SIZE 45 + +#define VDEC_FLAG_OTHER_INPUT_CONTEXT 0x0 +#define VDEC_FLAG_SELF_INPUT_CONTEXT 0x01 + +#define VDEC_NEED_MORE_DATA_RUN 0x01 +#define VDEC_NEED_MORE_DATA_DIRTY 0x02 +#define VDEC_NEED_MORE_DATA 0x04 + +struct vdec_s { + u32 magic; + struct list_head list; + unsigned long core_mask; + unsigned long active_mask; + unsigned long sched_mask; + int id; + + struct vdec_s *master; + struct vdec_s *slave; + struct stream_port_s *port; + int status; + int next_status; + int type; + int port_flag; + int format; + u32 pts; + u64 pts64; + bool pts_valid; + int flag; + int sched; + int need_more_data; + + struct completion inactive_done; + + /* config (temp) */ + unsigned long mem_start; + unsigned long mem_end; + + void *mm_blk_handle; + + struct device *cma_dev; + struct platform_device *dev; + struct dec_sysinfo sys_info_store; + struct dec_sysinfo *sys_info; + + /* input */ + struct vdec_input_s input; + + /* mc cache */ + u32 mc[4096 * 4]; + bool mc_loaded; + + /* frame provider/receiver interface */ + char vf_provider_name[VDEC_PROVIDER_NAME_SIZE]; + struct vframe_provider_s vframe_provider; + char *vf_receiver_name; + char vfm_map_id[VDEC_MAP_NAME_SIZE]; + char vfm_map_chain[VDEC_MAP_NAME_SIZE]; + int vf_receiver_inst; + enum FRAME_BASE_VIDEO_PATH frame_base_video_path; + enum vdec_fr_hint_state fr_hint_state; + bool use_vfm_path; + char config[PAGE_SIZE]; + int config_len; + bool is_reset; + bool dolby_meta_with_el; + + /* canvas */ + int (*get_canvas)(unsigned int index, unsigned int base); + + int (*dec_status)(struct vdec_s *vdec, struct vdec_info *vstatus); + int (*set_trickmode)(struct vdec_s *vdec, unsigned long trickmode); + int (*set_isreset)(struct vdec_s *vdec, int isreset); + + unsigned long (*run_ready)(struct vdec_s *vdec, unsigned long mask); + void (*run)(struct vdec_s *vdec, unsigned long mask, + void (*callback)(struct vdec_s *, void *), void *); + void (*reset)(struct vdec_s *vdec); + void (*dump_state)(struct vdec_s *vdec); + irqreturn_t (*irq_handler)(struct vdec_s *vdec, int irq); + irqreturn_t (*threaded_irq_handler)(struct vdec_s *vdec, int irq); + + int (*user_data_read)(struct vdec_s *vdec, + struct userdata_param_t *puserdata_para); + void (*reset_userdata_fifo)(struct vdec_s *vdec, int bInit); + + /* private */ + void *private; /* decoder per instance specific data */ +#ifdef VDEC_DEBUG_SUPPORT + u64 profile_start_clk[VDEC_MAX]; + u64 total_clk[VDEC_MAX]; + u32 check_count[VDEC_MAX]; + u32 not_run_ready_count[VDEC_MAX]; + u32 input_underrun_count[VDEC_MAX]; + u32 run_count[VDEC_MAX]; + u64 run_clk[VDEC_MAX]; + u64 start_run_clk[VDEC_MAX]; +#endif + atomic_t inirq_thread_flag; + atomic_t inirq_flag; +}; + +/* common decoder vframe provider name to use default vfm path */ +#define VFM_DEC_PROVIDER_NAME "decoder" +#define VFM_DEC_DVBL_PROVIDER_NAME "dvbldec" +#define VFM_DEC_DVEL_PROVIDER_NAME "dveldec" + +#define hw_to_vdec(hw) ((struct vdec_s *) \ + (platform_get_drvdata(hw->platform_dev))) + +#define canvas_y(canvas) ((canvas) & 0xff) +#define canvas_u(canvas) (((canvas) >> 8) & 0xff) +#define canvas_v(canvas) (((canvas) >> 16) & 0xff) +#define canvas_y2(canvas) (((canvas) >> 16) & 0xff) +#define canvas_u2(canvas) (((canvas) >> 24) & 0xff) + +#define vdec_frame_based(vdec) \ + (((vdec)->type == VDEC_TYPE_FRAME_BLOCK) || \ + ((vdec)->type == VDEC_TYPE_FRAME_CIRCULAR)) +#define vdec_stream_based(vdec) \ + (((vdec)->type == VDEC_TYPE_STREAM_PARSER) || \ + ((vdec)->type == VDEC_TYPE_SINGLE)) +#define vdec_single(vdec) \ + ((vdec)->type == VDEC_TYPE_SINGLE) +#define vdec_dual(vdec) \ + (((vdec)->port->type & PORT_TYPE_DUALDEC) ||\ + (vdec_get_debug_flags() & 0x100)) +#define vdec_secure(vdec) \ + (((vdec)->port_flag & PORT_FLAG_DRM)) + +/* construct vdec strcture */ +extern struct vdec_s *vdec_create(struct stream_port_s *port, + struct vdec_s *master); + +/* set video format */ +extern int vdec_set_format(struct vdec_s *vdec, int format); + +/* set PTS */ +extern int vdec_set_pts(struct vdec_s *vdec, u32 pts); + +extern int vdec_set_pts64(struct vdec_s *vdec, u64 pts64); + +/* set vfm map when use frame base decoder */ +extern int vdec_set_video_path(struct vdec_s *vdec, int video_path); + +/* set receive id when receive is ionvideo or amlvideo */ +extern int vdec_set_receive_id(struct vdec_s *vdec, int receive_id); + +/* add frame data to input chain */ +extern int vdec_write_vframe(struct vdec_s *vdec, const char *buf, + size_t count); + +/* mark the vframe_chunk as consumed */ +extern void vdec_vframe_dirty(struct vdec_s *vdec, + struct vframe_chunk_s *chunk); + +/* prepare decoder input */ +extern int vdec_prepare_input(struct vdec_s *vdec, struct vframe_chunk_s **p); + +/* clean decoder input */ +extern void vdec_clean_input(struct vdec_s *vdec); + +/* sync decoder input */ +extern int vdec_sync_input(struct vdec_s *vdec); + +/* enable decoder input */ +extern void vdec_enable_input(struct vdec_s *vdec); + +/* set decoder input prepare level */ +extern void vdec_set_prepare_level(struct vdec_s *vdec, int level); + +/* set vdec input */ +extern int vdec_set_input_buffer(struct vdec_s *vdec, u32 start, u32 size); + +/* check if decoder can get more input */ +extern bool vdec_has_more_input(struct vdec_s *vdec); + +/* allocate input chain + * register vdec_device + * create output, vfm or create ionvideo output + * insert vdec to vdec_manager for scheduling + */ +extern int vdec_connect(struct vdec_s *vdec); + +/* remove vdec from vdec_manager scheduling + * release input chain + * disconnect video output from ionvideo + */ +extern int vdec_disconnect(struct vdec_s *vdec); + +/* release vdec structure */ +extern int vdec_destroy(struct vdec_s *vdec); + +/* reset vdec */ +extern int vdec_reset(struct vdec_s *vdec); + +extern void vdec_set_status(struct vdec_s *vdec, int status); + +extern void vdec_set_next_status(struct vdec_s *vdec, int status); + +extern int vdec_set_decinfo(struct vdec_s *vdec, struct dec_sysinfo *p); + +extern int vdec_init(struct vdec_s *vdec, int is_4k); + +extern void vdec_release(struct vdec_s *vdec); + +extern int vdec_status(struct vdec_s *vdec, struct vdec_info *vstatus); + +extern int vdec_set_trickmode(struct vdec_s *vdec, unsigned long trickmode); + +extern int vdec_set_isreset(struct vdec_s *vdec, int isreset); + +extern int vdec_set_dv_metawithel(struct vdec_s *vdec, int isdvmetawithel); + +extern void vdec_set_no_powerdown(int flag); + +extern int vdec_is_support_4k(void); +extern void vdec_set_flag(struct vdec_s *vdec, u32 flag); + +extern void vdec_set_eos(struct vdec_s *vdec, bool eos); + +extern void vdec_set_next_sched(struct vdec_s *vdec, struct vdec_s *next_vdec); + +extern const char *vdec_status_str(struct vdec_s *vdec); + +extern const char *vdec_type_str(struct vdec_s *vdec); + +extern const char *vdec_device_name_str(struct vdec_s *vdec); + +extern void vdec_schedule_work(struct work_struct *work); + +extern void vdec_count_info(struct vdec_info *vs, unsigned int err, + unsigned int offset); + +extern bool vdec_need_more_data(struct vdec_s *vdec); + +extern void hevc_reset_core(struct vdec_s *vdec); + +extern void vdec_set_suspend_clk(int mode, int hevc); + +extern unsigned long vdec_ready_to_run(struct vdec_s *vdec, unsigned long mask); + +extern void vdec_prepare_run(struct vdec_s *vdec, unsigned long mask); + +extern int vdec_core_request(struct vdec_s *vdec, unsigned long mask); + +extern int vdec_core_release(struct vdec_s *vdec, unsigned long mask); + +extern const bool vdec_core_with_input(unsigned long mask); + +extern void vdec_core_finish_run(struct vdec_s *vdec, unsigned long mask); + +#ifdef VDEC_DEBUG_SUPPORT +extern void vdec_set_step_mode(void); +#endif + +int vdec_read_user_data(struct vdec_s *vdec, + struct userdata_param_t *p_userdata_param); + +int vdec_wakeup_userdata_poll(struct vdec_s *vdec); + +void vdec_reset_userdata_fifo(struct vdec_s *vdec, int bInit); + +#ifdef VDEC_DEBUG_SUPPORT +extern void vdec_set_step_mode(void); +#endif +int vdec_get_debug_flags(void); + +unsigned char is_mult_inc(unsigned int); + +#endif /* VDEC_H */ diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec_input.c b/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec_input.c new file mode 100644 index 000000000000..439e513677d3 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec_input.c @@ -0,0 +1,940 @@ +/* + * drivers/amlogic/media/frame_provider/decoder/utils/vdec_input.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include + +#include "../../../stream_input/amports/amports_priv.h" +#include "vdec.h" +#include "vdec_input.h" + +#define VFRAME_BLOCK_SIZE (512 * SZ_1K)/*512 for 1080p default init.*/ +#define VFRAME_BLOCK_SIZE_4K (2 * SZ_1M) /*2M for 4K default.*/ +#define VFRAME_BLOCK_SIZE_MAX (4 * SZ_1M) + +#define VFRAME_BLOCK_PAGEALIGN 4 +#define VFRAME_BLOCK_MIN_LEVEL (2 * SZ_1M) +#define VFRAME_BLOCK_MAX_LEVEL (8 * SZ_1M) +#define VFRAME_BLOCK_MAX_TOTAL_SIZE (16 * SZ_1M) + +/* +2s for OMX +*/ +#define MAX_FRAME_DURATION_S 2 + + +#define VFRAME_BLOCK_HOLE (SZ_64K) + +#define MIN_FRAME_PADDING_SIZE ((u32)(L1_CACHE_BYTES)) + +#define EXTRA_PADDING_SIZE (16 * SZ_1K) /*HEVC_PADDING_SIZE*/ + +#define MEM_NAME "VFRAME_INPUT" +static int vdec_input_get_duration_u64(struct vdec_input_s *input); +static struct vframe_block_list_s * + vdec_input_alloc_new_block(struct vdec_input_s *input); + +static int vframe_chunk_fill(struct vdec_input_s *input, + struct vframe_chunk_s *chunk, const char *buf, + size_t count, struct vframe_block_list_s *block) +{ + u8 *p = (u8 *)block->start_virt + block->wp; + int total_size = count + chunk->pading_size; + if (block->type == VDEC_TYPE_FRAME_BLOCK) { + if (copy_from_user(p, buf, count)) + return -EFAULT; + + p += count; + + memset(p, 0, chunk->pading_size); + + dma_sync_single_for_device(get_vdec_device(), + block->start + block->wp, + total_size, DMA_TO_DEVICE); + + } else if (block->type == VDEC_TYPE_FRAME_CIRCULAR) { + size_t len = min((size_t)(block->size - block->wp), count); + u32 wp; + + if (copy_from_user(p, buf, len)) + return -EFAULT; + + dma_sync_single_for_device(get_vdec_device(), + block->start + block->wp, + len, DMA_TO_DEVICE); + + p += len; + + if (count > len) { + p = (u8 *)block->start_virt; + if (copy_from_user(p, buf, count - len)) + return -EFAULT; + + dma_sync_single_for_device(get_vdec_device(), + block->start, + count-len, DMA_TO_DEVICE); + + p += count - len; + } + + wp = block->wp + count; + if (wp >= block->size) + wp -= block->size; + + len = min(block->size - wp, chunk->pading_size); + + memset(p, 0, len); + + dma_sync_single_for_device(get_vdec_device(), + block->start + wp, + len, DMA_TO_DEVICE); + + if (chunk->pading_size > len) { + p = (u8 *)block->start_virt; + + memset(p, 0, count - len); + + dma_sync_single_for_device(get_vdec_device(), + block->start, + chunk->pading_size - len, DMA_TO_DEVICE); + } + } + + return 0; +} + +static inline u32 vframe_block_space(struct vframe_block_list_s *block) +{ + if (block->type == VDEC_TYPE_FRAME_BLOCK) { + return block->size - block->wp; + } else { + return (block->rp >= block->wp) ? + (block->rp - block->wp) : + (block->rp - block->wp + block->size); + } +} + +static void vframe_block_add_chunk(struct vframe_block_list_s *block, + struct vframe_chunk_s *chunk) +{ + block->wp += chunk->size + chunk->pading_size; + if (block->wp >= block->size) + block->wp -= block->size; + block->data_size += chunk->size; + block->chunk_count++; + chunk->block = block; + block->input->wr_block = block; + chunk->sequence = block->input->sequence; + block->input->sequence++; +} + +static void vframe_block_free_block(struct vframe_block_list_s *block) +{ + if (block->addr) { + codec_mm_free_for_dma(MEM_NAME, block->addr); + } + /* + *pr_err("free block %d, size=%d\n", block->id, block->size); + */ + kfree(block); +} + +static int vframe_block_init_alloc_storage(struct vdec_input_s *input, + struct vframe_block_list_s *block) +{ + int alloc_size = input->default_block_size; + block->magic = 0x4b434c42; + block->input = input; + block->type = input->type; + + /* + * todo: for different type use different size + */ + alloc_size = PAGE_ALIGN(alloc_size); + block->addr = codec_mm_alloc_for_dma_ex( + MEM_NAME, + alloc_size/PAGE_SIZE, + VFRAME_BLOCK_PAGEALIGN, + CODEC_MM_FLAGS_DMA_CPU | CODEC_MM_FLAGS_FOR_VDECODER, + input->id, + block->id); + + if (!block->addr) { + pr_err("Input block allocation failed\n"); + return -ENOMEM; + } + + block->start_virt = (void *)codec_mm_phys_to_virt(block->addr); + block->start = block->addr; + block->size = alloc_size; + + return 0; +} + +void vdec_input_init(struct vdec_input_s *input, struct vdec_s *vdec) +{ + INIT_LIST_HEAD(&input->vframe_block_list); + INIT_LIST_HEAD(&input->vframe_block_free_list); + INIT_LIST_HEAD(&input->vframe_chunk_list); + spin_lock_init(&input->lock); + input->id = vdec->id; + input->block_nums = 0; + input->vdec = vdec; + input->block_id_seq = 0; + input->size = 0; + input->default_block_size = VFRAME_BLOCK_SIZE; +} +int vdec_input_prepare_bufs(struct vdec_input_s *input, + int frame_width, int frame_height) +{ + struct vframe_block_list_s *block; + int i; + unsigned long flags; + + if (input->size > 0) + return 0; + if (frame_width * frame_height >= 1920 * 1088) { + /*have add data before. ignore prepare buffers.*/ + input->default_block_size = VFRAME_BLOCK_SIZE_4K; + } + /*prepared 3 buffers for smooth start.*/ + for (i = 0; i < 3; i++) { + block = vdec_input_alloc_new_block(input); + if (!block) + break; + flags = vdec_input_lock(input); + list_move_tail(&block->list, + &input->vframe_block_free_list); + input->wr_block = NULL; + vdec_input_unlock(input, flags); + } + return 0; +} + +static int vdec_input_dump_block_locked( + struct vframe_block_list_s *block, + char *buf, int size) +{ + char *pbuf = buf; + char sbuf[512]; + int tsize = 0; + int s; + if (!pbuf) { + pbuf = sbuf; + size = 512; + } + #define BUFPRINT(args...) \ + do {\ + s = snprintf(pbuf, size - tsize, args);\ + tsize += s;\ + pbuf += s; \ + } while (0) + + BUFPRINT("\tblock:[%d:%p]-addr=%p,vstart=%p,type=%d\n", + block->id, + block, + (void *)block->addr, + (void *)block->start_virt, + block->type); + BUFPRINT("\t-blocksize=%d,data=%d,wp=%d,rp=%d,chunk_count=%d\n", + block->size, + block->data_size, + block->wp, + block->rp, + block->chunk_count); + /* + BUFPRINT("\tlist=%p,next=%p,prev=%p\n", + &block->list, + block->list.next, + block->list.prev); + */ + #undef BUFPRINT + if (!buf) + pr_info("%s", sbuf); + return tsize; +} + +int vdec_input_dump_blocks(struct vdec_input_s *input, + char *bufs, int size) +{ + struct list_head *p, *tmp; + unsigned long flags; + char *lbuf = bufs; + char sbuf[256]; + int s = 0; + + if (size <= 0) + return 0; + if (!bufs) + lbuf = sbuf; + s += snprintf(lbuf + s, size - s, + "blocks:vdec-%d id:%d,bufsize=%d,dsize=%d,frames:%d,dur:%dms\n", + input->id, + input->block_nums, + input->size, + input->data_size, + input->have_frame_num, + vdec_input_get_duration_u64(input)/1000); + if (bufs) + lbuf += s; + else { + pr_info("%s", sbuf); + lbuf = NULL; + } + + flags = vdec_input_lock(input); + /* dump input blocks */ + list_for_each_safe(p, tmp, &input->vframe_block_list) { + struct vframe_block_list_s *block = list_entry( + p, struct vframe_block_list_s, list); + if (bufs != NULL) { + lbuf = bufs + s; + if (size - s < 128) + break; + } + s += vdec_input_dump_block_locked(block, lbuf, size - s); + } + list_for_each_safe(p, tmp, &input->vframe_block_free_list) { + struct vframe_block_list_s *block = list_entry( + p, struct vframe_block_list_s, list); + if (bufs != NULL) { + lbuf = bufs + s; + if (size - s < 128) + break; + } + s += vdec_input_dump_block_locked(block, lbuf, size - s); + } + vdec_input_unlock(input, flags); + return s; +} + +static int vdec_input_dump_chunk_locked( + struct vframe_chunk_s *chunk, + char *buf, int size) +{ + char *pbuf = buf; + char sbuf[512]; + int tsize = 0; + int s; + if (!pbuf) { + pbuf = sbuf; + size = 512; + } + #define BUFPRINT(args...) \ + do {\ + s = snprintf(pbuf, size - tsize, args);\ + tsize += s;\ + pbuf += s; \ + } while (0) + + BUFPRINT( + "\t[%lld:%p]-off=%d,size:%d,p:%d,\tpts64=%lld,addr=%p\n", + chunk->sequence, + chunk->block, + chunk->offset, + chunk->size, + chunk->pading_size, + chunk->pts64, + (void *)(chunk->block->addr + chunk->offset)); + /* + BUFPRINT("\tlist=%p,next=%p,prev=%p\n", + &chunk->list, + chunk->list.next, + chunk->list.prev); + */ + #undef BUFPRINT + if (!buf) + pr_info("%s", sbuf); + return tsize; +} + +int vdec_input_dump_chunks(struct vdec_input_s *input, + char *bufs, int size) +{ + + struct list_head *p, *tmp; + unsigned long flags; + char *lbuf = bufs; + char sbuf[256]; + int s = 0; + if (size <= 0) + return 0; + if (!bufs) + lbuf = sbuf; + snprintf(lbuf + s, size - s, + "blocks:vdec-%d id:%d,bufsize=%d,dsize=%d,frames:%d,maxframe:%d\n", + input->id, + input->block_nums, + input->size, + input->data_size, + input->have_frame_num, + input->frame_max_size); + if (bufs) + lbuf += s; + if (!bufs) { + pr_info("%s", sbuf); + lbuf = NULL; + } + flags = vdec_input_lock(input); + /*dump chunks list infos.*/ + list_for_each_safe(p, tmp, &input->vframe_chunk_list) { + struct vframe_chunk_s *chunk = list_entry( + p, struct vframe_chunk_s, list); + if (bufs != NULL) + lbuf = bufs + s; + s += vdec_input_dump_chunk_locked(chunk, lbuf, size - s); + } + vdec_input_unlock(input, flags); + return s; +} + + + +int vdec_input_set_buffer(struct vdec_input_s *input, u32 start, u32 size) +{ + if (input_frame_based(input)) + return -EINVAL; + + input->start = start; + input->size = size; + input->swap_rp = start; + + if (vdec_secure(input->vdec)) + input->swap_page_phys = codec_mm_alloc_for_dma("SWAP", + 1, 0, CODEC_MM_FLAGS_TVP); + else { + input->swap_page = alloc_page(GFP_KERNEL); + if (input->swap_page) { + input->swap_page_phys = + page_to_phys(input->swap_page); + } + } + + if (input->swap_page_phys == 0) + return -ENOMEM; + + return 0; +} +EXPORT_SYMBOL(vdec_input_set_buffer); + +void vdec_input_set_type(struct vdec_input_s *input, int type, int target) +{ + input->type = type; + input->target = target; + if (type == VDEC_TYPE_FRAME_CIRCULAR) { + /*alway used max block.*/ + input->default_block_size = VFRAME_BLOCK_SIZE_MAX; + } +} +EXPORT_SYMBOL(vdec_input_set_type); + +int vdec_input_get_status(struct vdec_input_s *input, + struct vdec_input_status_s *status) +{ + unsigned long flags; + + if (input->vdec == NULL) + return -EINVAL; + + flags = vdec_input_lock(input); + + if (list_empty(&input->vframe_block_list)) { + status->size = VFRAME_BLOCK_SIZE; + status->data_len = 0; + status->free_len = VFRAME_BLOCK_SIZE; + status->read_pointer = 0; + } else { + int r = VFRAME_BLOCK_MAX_LEVEL - vdec_input_level(input) + - VFRAME_BLOCK_HOLE; + status->size = input->size; + status->data_len = vdec_input_level(input); + status->free_len = (r > 0) ? r : 0; + status->read_pointer = input->total_rd_count; + } + + vdec_input_unlock(input, flags); + + return 0; +} +EXPORT_SYMBOL(vdec_input_get_status); + +static void vdec_input_add_block(struct vdec_input_s *input, + struct vframe_block_list_s *block) +{ + unsigned long flags; + + flags = vdec_input_lock(input); + block->wp = 0; + block->id = input->block_id_seq++; + list_add_tail(&block->list, &input->vframe_block_list); + input->size += block->size; + input->block_nums++; + input->wr_block = block; + vdec_input_unlock(input, flags); +} + +static inline void vdec_input_del_block_locked(struct vdec_input_s *input, + struct vframe_block_list_s *block) +{ + list_del(&block->list); + input->size -= block->size; + input->block_nums--; +} + +int vdec_input_level(struct vdec_input_s *input) +{ + return input->total_wr_count - input->total_rd_count; +} +EXPORT_SYMBOL(vdec_input_level); + +static struct vframe_block_list_s * + vdec_input_alloc_new_block(struct vdec_input_s *input) +{ + struct vframe_block_list_s *block; + block = kzalloc(sizeof(struct vframe_block_list_s), + GFP_KERNEL); + if (block == NULL) { + input->no_mem_err_cnt++; + pr_err("vframe_block structure allocation failed\n"); + return NULL; + } + + if (vframe_block_init_alloc_storage(input, + block) != 0) { + kfree(block); + pr_err("vframe_block storage allocation failed\n"); + return NULL; + } + + INIT_LIST_HEAD(&block->list); + + vdec_input_add_block(input, block); + + /* + *pr_info("vdec-%d:new block id=%d, total_blocks:%d, size=%d\n", + * input->id, + * block->id, + * input->block_nums, + * block->size); + */ + if (0 && input->size > VFRAME_BLOCK_MAX_LEVEL * 2) { + /* + used + */ + pr_info( + "input[%d] reach max: size:%d, blocks:%d", + input->id, + input->size, + input->block_nums); + pr_info("level:%d, wr:%lld,rd:%lld\n", + vdec_input_level(input), + input->total_wr_count, + input->total_rd_count); + vdec_input_dump_blocks(input, NULL, 0); + } + return block; +} +static int vdec_input_get_duration_u64(struct vdec_input_s *input) +{ + int duration = (input->last_inpts_u64 - input->last_comsumed_pts_u64); + if (input->last_in_nopts_cnt > 0 && + input->last_comsumed_pts_u64 > 0 && + input->last_duration > 0) { + duration += (input->last_in_nopts_cnt - + input->last_comsumed_no_pts_cnt) * + input->last_duration; + } + if (duration > 1000 * 1000000)/*> 1000S,I think jumped.*/ + duration = 0; + if (duration <= 0 && input->last_duration > 0) { + /*..*/ + duration = input->last_duration * input->have_frame_num; + } + if (duration < 0) + duration = 0; + return duration; +} +/* + ret >= 13: have enough buffer, blocked add more buffers +*/ +static int vdec_input_have_blocks_enough(struct vdec_input_s *input) +{ + int ret = 0; + if (vdec_input_level(input) > VFRAME_BLOCK_MIN_LEVEL) + ret += 1; + if (vdec_input_level(input) >= VFRAME_BLOCK_MAX_LEVEL) + ret += 2; + if (vdec_input_get_duration_u64(input) > MAX_FRAME_DURATION_S) + ret += 4; + if (input->have_frame_num > 30) + ret += 8; + else + ret -= 8;/*not enough frames.*/ + if (input->size >= VFRAME_BLOCK_MAX_TOTAL_SIZE) + ret += 100;/*always bloced add more buffers.*/ + + return ret; +} +static int vdec_input_get_free_block( + struct vdec_input_s *input, + int size,/*frame size + pading*/ + struct vframe_block_list_s **block_ret) +{ + struct vframe_block_list_s *to_freeblock = NULL; + struct vframe_block_list_s *block = NULL; + unsigned long flags; + flags = vdec_input_lock(input); + /*get from free list.*/ + if (!list_empty(&input->vframe_block_free_list)) { + block = list_entry(input->vframe_block_free_list.next, + struct vframe_block_list_s, list); + if (block->size < (size)) { + vdec_input_del_block_locked(input, block); + to_freeblock = block; + block = NULL; + } else { + list_move_tail(&block->list, + &input->vframe_block_list); + input->wr_block = block;/*swith to new block*/ + } + } + vdec_input_unlock(input, flags); + if (to_freeblock) { + /*free the small block.*/ + vframe_block_free_block(to_freeblock); + } + if (block) { + *block_ret = block; + return 0; + } + + if (vdec_input_have_blocks_enough(input) > 13) { + /*buf fulled */ + return -EAGAIN; + } + if (input->no_mem_err_cnt > 3) { + /*alloced failed more times. + */ + return -EAGAIN; + } + if (input->default_block_size <= + size * 2) { + int def_size = input->default_block_size; + do { + def_size *= 2; + } while ((def_size <= 2 * size) && + (def_size <= VFRAME_BLOCK_SIZE_MAX)); + if (def_size < size) + def_size = ALIGN(size + 64, (1 << 17)); + /*128k aligned,same as codec_mm*/ + input->default_block_size = def_size; + } + block = vdec_input_alloc_new_block(input); + if (!block) { + input->no_mem_err_cnt++; + return -EAGAIN; + } + input->no_mem_err_cnt = 0; + *block_ret = block; + return 0; +} + +int vdec_input_add_frame(struct vdec_input_s *input, const char *buf, + size_t count) +{ + unsigned long flags; + struct vframe_chunk_s *chunk; + struct vdec_s *vdec = input->vdec; + struct vframe_block_list_s *block; + int need_pading_size = MIN_FRAME_PADDING_SIZE; + +#if 0 + if (add_count == 0) { + add_count++; + memcpy(sps, buf, 30); + return 30; + } else if (add_count == 1) { + add_count++; + memcpy(pps, buf, 8); + return 8; + } + add_count++; +#endif + +#if 0 + pr_info("vdec_input_add_frame add %p, count=%d\n", buf, (int)count); + + if (count >= 8) { + pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n", + buf[0], buf[1], buf[2], buf[3], + buf[4], buf[5], buf[6], buf[7]); + } + if (count >= 16) { + pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n", + buf[8], buf[9], buf[10], buf[11], + buf[12], buf[13], buf[14], buf[15]); + } + if (count >= 24) { + pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n", + buf[16], buf[17], buf[18], buf[19], + buf[20], buf[21], buf[22], buf[23]); + } + if (count >= 32) { + pr_info("%02x %02x %02x %02x %02x %02x %02x %02x\n", + buf[24], buf[25], buf[26], buf[27], + buf[28], buf[29], buf[30], buf[31]); + } +#endif + if (input_stream_based(input)) + return -EINVAL; + if (count < PAGE_SIZE) { + need_pading_size = PAGE_ALIGN(count + need_pading_size) - + count; + } else { + /*to 64 bytes aligned;*/ + if (count & 0x3f) + need_pading_size += 64 - (count & 0x3f); + } + block = input->wr_block; + if (block && + (vframe_block_space(block) > (count + need_pading_size))) { + /*this block have enough buffers. + do nothings. + */ + } else if (block && (block->type == VDEC_TYPE_FRAME_CIRCULAR)) { + /*in circular module. + only one block,.*/ + return -EAGAIN; + } else if (block != NULL) { + /*have block but not enough space. + recycle the no enough blocks.*/ + flags = vdec_input_lock(input); + if (input->wr_block == block && + block->chunk_count == 0) { + block->rp = 0; + block->wp = 0; + /*block no data move to freelist*/ + list_move_tail(&block->list, + &input->vframe_block_free_list); + input->wr_block = NULL; + } + vdec_input_unlock(input, flags); + block = NULL; + } + if (!block) {/*try new block.*/ + int ret = vdec_input_get_free_block(input, + count + need_pading_size + EXTRA_PADDING_SIZE, + &block); + if (ret < 0)/*no enough block now.*/ + return ret; + } + + chunk = kzalloc(sizeof(struct vframe_chunk_s), GFP_KERNEL); + + if (!chunk) { + pr_err("vframe_chunk structure allocation failed\n"); + return -ENOMEM; + } + + chunk->magic = 0x4b554843; + if (vdec->pts_valid) { + chunk->pts = vdec->pts; + chunk->pts64 = vdec->pts64; + } + if (vdec->pts_valid && + input->last_inpts_u64 > 0 && + input->last_in_nopts_cnt == 0) { + int d = (int)(chunk->pts64 - input->last_inpts_u64); + if (d > 0 && (d < input->last_duration)) + input->last_duration = d; + /* alwasy: used the smallest duration; + if 60fps->30 fps. + maybe have warning value. + */ + } + chunk->pts_valid = vdec->pts_valid; + vdec->pts_valid = false; + chunk->offset = block->wp; + chunk->size = count; + chunk->pading_size = need_pading_size; + INIT_LIST_HEAD(&chunk->list); + + if (vframe_chunk_fill(input, chunk, buf, count, block)) { + pr_err("vframe_chunk_fill failed\n"); + kfree(chunk); + return -EFAULT; + } + + flags = vdec_input_lock(input); + + vframe_block_add_chunk(block, chunk); + + list_add_tail(&chunk->list, &input->vframe_chunk_list); + input->data_size += chunk->size; + input->have_frame_num++; + if (chunk->pts_valid) { + input->last_inpts_u64 = chunk->pts64; + input->last_in_nopts_cnt = 0; + } else { + /*nopts*/ + input->last_in_nopts_cnt++; + } + vdec_input_unlock(input, flags); + if (chunk->size > input->frame_max_size) + input->frame_max_size = chunk->size; + input->total_wr_count += count; + +#if 0 + if (add_count == 2) + input->total_wr_count += 38; +#endif + + return count; +} +EXPORT_SYMBOL(vdec_input_add_frame); + +struct vframe_chunk_s *vdec_input_next_chunk(struct vdec_input_s *input) +{ + struct vframe_chunk_s *chunk = NULL; + unsigned long flags; + flags = vdec_input_lock(input); + if (!list_empty(&input->vframe_chunk_list)) { + chunk = list_first_entry(&input->vframe_chunk_list, + struct vframe_chunk_s, list); + } + vdec_input_unlock(input, flags); + return chunk; +} +EXPORT_SYMBOL(vdec_input_next_chunk); + +struct vframe_chunk_s *vdec_input_next_input_chunk( + struct vdec_input_s *input) +{ + struct vframe_chunk_s *chunk = NULL; + struct list_head *p; + unsigned long flags; + flags = vdec_input_lock(input); + + list_for_each(p, &input->vframe_chunk_list) { + struct vframe_chunk_s *c = list_entry( + p, struct vframe_chunk_s, list); + if ((c->flag & VFRAME_CHUNK_FLAG_CONSUMED) == 0) { + chunk = c; + break; + } + } + vdec_input_unlock(input, flags); + return chunk; +} +EXPORT_SYMBOL(vdec_input_next_input_chunk); + +void vdec_input_release_chunk(struct vdec_input_s *input, + struct vframe_chunk_s *chunk) +{ + unsigned long flags; + struct vframe_block_list_s *block = chunk->block; + struct vframe_block_list_s *tofreeblock = NULL; + flags = vdec_input_lock(input); + + list_del(&chunk->list); + input->have_frame_num--; + if (chunk->pts_valid) { + input->last_comsumed_no_pts_cnt = 0; + input->last_comsumed_pts_u64 = chunk->pts64; + } else + input->last_comsumed_no_pts_cnt++; + block->rp += chunk->size; + if (block->rp >= block->size) + block->rp -= block->size; + block->data_size -= chunk->size; + block->chunk_count--; + input->data_size -= chunk->size; + input->total_rd_count += chunk->size; + if (block->chunk_count == 0 && + input->wr_block != block) {/*don't free used block*/ + if (block->size < input->default_block_size) { + vdec_input_del_block_locked(input, block); + tofreeblock = block; + } else { + block->rp = 0; + block->wp = 0; + list_move_tail(&block->list, + &input->vframe_block_free_list); + } + } + + vdec_input_unlock(input, flags); + if (tofreeblock) + vframe_block_free_block(tofreeblock); + kfree(chunk); +} +EXPORT_SYMBOL(vdec_input_release_chunk); + +unsigned long vdec_input_lock(struct vdec_input_s *input) +{ + unsigned long flags; + + spin_lock_irqsave(&input->lock, flags); + + return flags; +} +EXPORT_SYMBOL(vdec_input_lock); + +void vdec_input_unlock(struct vdec_input_s *input, unsigned long flags) +{ + spin_unlock_irqrestore(&input->lock, flags); +} +EXPORT_SYMBOL(vdec_input_unlock); + +void vdec_input_release(struct vdec_input_s *input) +{ + struct list_head *p, *tmp; + + /* release chunk data */ + list_for_each_safe(p, tmp, &input->vframe_chunk_list) { + struct vframe_chunk_s *chunk = list_entry( + p, struct vframe_chunk_s, list); + vdec_input_release_chunk(input, chunk); + } + list_for_each_safe(p, tmp, &input->vframe_block_list) { + /*should never here.*/ + list_move_tail(p, &input->vframe_block_free_list); + } + /* release input blocks */ + list_for_each_safe(p, tmp, &input->vframe_block_free_list) { + struct vframe_block_list_s *block = list_entry( + p, struct vframe_block_list_s, list); + vdec_input_del_block_locked(input, block); + vframe_block_free_block(block); + } + + /* release swap pages */ + if (input->swap_page_phys) { + if (vdec_secure(input->vdec)) + codec_mm_free_for_dma("SWAP", input->swap_page_phys); + else + __free_page(input->swap_page); + input->swap_page = NULL; + input->swap_page_phys = 0; + } + input->swap_valid = false; +} +EXPORT_SYMBOL(vdec_input_release); + diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec_input.h b/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec_input.h new file mode 100644 index 000000000000..d95e13f97c42 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec_input.h @@ -0,0 +1,164 @@ +/* + * drivers/amlogic/media/frame_provider/decoder/utils/vdec_input.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef VDEC_INPUT_H +#define VDEC_INPUT_H + +struct vdec_s; +struct vdec_input_s; + +struct vframe_block_list_s { + u32 magic; + int id; + struct list_head list; + ulong start; + void *start_virt; + ulong addr; + int type; + u32 size; + u32 wp; + u32 rp; + int data_size; + int chunk_count; + struct vdec_input_s *input; +}; + +#define VFRAME_CHUNK_FLAG_CONSUMED 0x0001 + +struct vframe_chunk_s { + u32 magic; + struct list_head list; + int flag; + u32 offset; + u32 size; + u32 pts; + u32 pading_size; + u64 pts64; + bool pts_valid; + u64 sequence; + struct vframe_block_list_s *block; +}; + +#define VDEC_INPUT_TARGET_VLD 0 +#define VDEC_INPUT_TARGET_HEVC 1 + +struct vdec_input_s { + struct list_head vframe_block_list; + struct list_head vframe_chunk_list; + struct list_head vframe_block_free_list; + struct vframe_block_list_s *wr_block; + int have_free_blocks; + int no_mem_err_cnt;/*when alloc no mem cnt++*/ + int block_nums; + int block_id_seq; + int id; + spinlock_t lock; + int type; + int target; + struct vdec_s *vdec; + bool swap_valid; + bool swap_needed; + bool eos; + struct page *swap_page; + unsigned long swap_page_phys; + u64 total_wr_count; + u64 total_rd_count; + u64 streaming_rp; + u32 swap_rp; + bool last_swap_slave; + int dirty_count; + u64 sequence; + unsigned start; + unsigned size; + int default_block_size; + int data_size; + int frame_max_size; + int prepare_level; +/*for check frame delay.*/ + u64 last_inpts_u64; + u64 last_comsumed_pts_u64; + int last_in_nopts_cnt; + int last_comsumed_no_pts_cnt; + int last_duration; +/*for check frame delay.*/ + int have_frame_num; + int stream_cookie; /* wrap count for vld_mem and + HEVC_SHIFT_BYTE_COUNT for hevc */ +}; + +struct vdec_input_status_s { + int size; + int data_len; + int free_len; + int read_pointer; +}; + +#define input_frame_based(input) \ + (((input)->type == VDEC_TYPE_FRAME_BLOCK) || \ + ((input)->type == VDEC_TYPE_FRAME_CIRCULAR)) +#define input_stream_based(input) \ + (((input)->type == VDEC_TYPE_STREAM_PARSER) || \ + ((input)->type == VDEC_TYPE_SINGLE)) + +/* Initialize vdec_input structure */ +extern void vdec_input_init(struct vdec_input_s *input, struct vdec_s *vdec); +extern int vdec_input_prepare_bufs(struct vdec_input_s *input, + int frame_width, int frame_height); + +/* Get available input data size */ +extern int vdec_input_level(struct vdec_input_s *input); + +/* Set input type and target */ +extern void vdec_input_set_type(struct vdec_input_s *input, int type, + int target); + +/* Set stream buffer information for stream based input */ +extern int vdec_input_set_buffer(struct vdec_input_s *input, u32 start, + u32 size); + +/* Add enqueue video data into decoder's input */ +extern int vdec_input_add_frame(struct vdec_input_s *input, const char *buf, + size_t count); + +/* Peek next frame data from decoder's input */ +extern struct vframe_chunk_s *vdec_input_next_chunk( + struct vdec_input_s *input); + +/* Peek next frame data from decoder's input, not marked as consumed */ +extern struct vframe_chunk_s *vdec_input_next_input_chunk( + struct vdec_input_s *input); + +/* Consume next frame data from decoder's input */ +extern void vdec_input_release_chunk(struct vdec_input_s *input, + struct vframe_chunk_s *chunk); + +/* Get decoder input buffer status */ +extern int vdec_input_get_status(struct vdec_input_s *input, + struct vdec_input_status_s *status); + +extern unsigned long vdec_input_lock(struct vdec_input_s *input); + +extern void vdec_input_unlock(struct vdec_input_s *input, unsigned long lock); + +/* release all resource for decoder's input */ +extern void vdec_input_release(struct vdec_input_s *input); +int vdec_input_dump_chunks(struct vdec_input_s *input, + char *bufs, int size); +int vdec_input_dump_blocks(struct vdec_input_s *input, + char *bufs, int size); + +#endif /* VDEC_INPUT_H */ diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec_profile.c b/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec_profile.c new file mode 100644 index 000000000000..77eb4e30f116 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec_profile.c @@ -0,0 +1,258 @@ +/* + * drivers/amlogic/amports/vdec_profile.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * +*/ + +#include +#include +#include +#include + +#include +#include "vdec_profile.h" +#include "vdec.h" + +#define ISA_TIMERE 0x2662 +#define ISA_TIMERE_HI 0x2663 + +#define PROFILE_REC_SIZE 40 + +static DEFINE_MUTEX(vdec_profile_mutex); +static int rec_wp; +static bool rec_wrapped; + +struct dentry *root, *event; + +struct vdec_profile_rec_s { + struct vdec_s *vdec; + u64 timestamp; + int event; + int para1; + int para2; +}; + +static struct vdec_profile_rec_s recs[PROFILE_REC_SIZE]; +static const char *event_name[VDEC_PROFILE_MAX_EVENT] = { + "run", + "cb", + "save_input", + "check run ready", + "run ready", + "disconnect", + "dec_work", + "info" +}; + +#if 0 /* get time from hardware. */ +static u64 get_us_time_hw(void) +{ + u32 lo, hi1, hi2; + int offset = 0; + + /* txlx, g12a isa register base is 0x3c00 */ + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXLX) + offset = 0x1600; + + do { + hi1 = READ_MPEG_REG(ISA_TIMERE_HI + offset); + lo = READ_MPEG_REG(ISA_TIMERE + offset); + hi2 = READ_MPEG_REG(ISA_TIMERE_HI + offset); + } while (hi1 != hi2); + + return (((u64)hi1) << 32) | lo; +} +#endif + +static u64 get_us_time_system(void) +{ + struct timeval tv; + + do_gettimeofday(&tv); + + return div64_u64(timeval_to_ns(&tv), 1000); +} + +void vdec_profile_more(struct vdec_s *vdec, int event, int para1, int para2) +{ + mutex_lock(&vdec_profile_mutex); + + recs[rec_wp].vdec = vdec; + recs[rec_wp].timestamp = get_us_time_system(); + recs[rec_wp].event = event; + recs[rec_wp].para1 = para1; + recs[rec_wp].para2 = para2; + + rec_wp++; + if (rec_wp == PROFILE_REC_SIZE) { + rec_wrapped = true; + rec_wp = 0; + } + + mutex_unlock(&vdec_profile_mutex); +} +EXPORT_SYMBOL(vdec_profile_more); + +void vdec_profile(struct vdec_s *vdec, int event) +{ + vdec_profile_more(vdec, event, 0 , 0); +} +EXPORT_SYMBOL(vdec_profile); + +void vdec_profile_flush(struct vdec_s *vdec) +{ + int i; + + mutex_lock(&vdec_profile_mutex); + + for (i = 0; i < PROFILE_REC_SIZE; i++) { + if (recs[i].vdec == vdec) + recs[i].vdec = NULL; + } + + mutex_unlock(&vdec_profile_mutex); +} + +static const char *event_str(int event) +{ + if (event < VDEC_PROFILE_MAX_EVENT) + return event_name[event]; + + return "INVALID"; +} + +static int vdec_profile_dbg_show(struct seq_file *m, void *v) +{ + int i, end; + u64 base_timestamp; + + mutex_lock(&vdec_profile_mutex); + + if (rec_wrapped) { + i = rec_wp; + end = rec_wp; + } else { + i = 0; + end = rec_wp; + } + + base_timestamp = recs[i].timestamp; + while (1) { + if ((!rec_wrapped) && (i == end)) + break; + + if (recs[i].vdec) { + seq_printf(m, "[%s:%d] \t%016llu us : %s (%d,%d)\n", + vdec_device_name_str(recs[i].vdec), + recs[i].vdec->id, + recs[i].timestamp - base_timestamp, + event_str(recs[i].event), + recs[i].para1, + recs[i].para2 + ); + } else { + seq_printf(m, "[%s:%d] \t%016llu us : %s (%d,%d)\n", + "N/A", + 0, + recs[i].timestamp - base_timestamp, + event_str(recs[i].event), + recs[i].para1, + recs[i].para2 + ); + } + if (++i == PROFILE_REC_SIZE) + i = 0; + + if (rec_wrapped && (i == end)) + break; + } + + mutex_unlock(&vdec_profile_mutex); + + return 0; +} + +static int vdec_profile_dbg_open(struct inode *inode, struct file *file) +{ + return single_open(file, vdec_profile_dbg_show, NULL); +} + +static const struct file_operations event_dbg_fops = { + .open = vdec_profile_dbg_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +#if 0 /*DEBUG_TMP*/ +static int __init vdec_profile_init_debugfs(void) +{ + struct dentry *root, *event; + + root = debugfs_create_dir("vdec_profile", NULL); + if (IS_ERR(root) || !root) + goto err; + + event = debugfs_create_file("event", 0400, root, NULL, + &event_dbg_fops); + if (!event) + goto err_1; + + mutex_init(&vdec_profile_mutex); + + return 0; + +err_1: + debugfs_remove(root); +err: + pr_err("Can not create debugfs for vdec_profile\n"); + return 0; +} + +#endif + +int vdec_profile_init_debugfs(void) +{ + struct dentry *root, *event; + + root = debugfs_create_dir("vdec_profile", NULL); + if (IS_ERR(root) || !root) + goto err; + + event = debugfs_create_file("event", 0400, root, NULL, + &event_dbg_fops); + if (!event) + goto err_1; + + mutex_init(&vdec_profile_mutex); + + return 0; + +err_1: + debugfs_remove(root); +err: + pr_err("Can not create debugfs for vdec_profile\n"); + return 0; +} +EXPORT_SYMBOL(vdec_profile_init_debugfs); + +void vdec_profile_exit_debugfs(void) +{ + debugfs_remove(event); + debugfs_remove(root); +} +EXPORT_SYMBOL(vdec_profile_exit_debugfs); + +/*module_init(vdec_profile_init_debugfs);*/ + diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec_profile.h b/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec_profile.h new file mode 100644 index 000000000000..34f3beed3231 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec_profile.h @@ -0,0 +1,40 @@ +/* + * drivers/amlogic/amports/vdec_profile.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * +*/ + +#ifndef VDEC_PROFILE_H +#define VDEC_PROFILE_H + +struct vdec_s; + +#define VDEC_PROFILE_EVENT_RUN 0 +#define VDEC_PROFILE_EVENT_CB 1 +#define VDEC_PROFILE_EVENT_SAVE_INPUT 2 +#define VDEC_PROFILE_EVENT_CHK_RUN_READY 3 +#define VDEC_PROFILE_EVENT_RUN_READY 4 +#define VDEC_PROFILE_EVENT_DISCONNECT 5 +#define VDEC_PROFILE_EVENT_DEC_WORK 6 +#define VDEC_PROFILE_EVENT_INFO 7 +#define VDEC_PROFILE_MAX_EVENT 8 + +extern void vdec_profile(struct vdec_s *vdec, int event); +extern void vdec_profile_more(struct vdec_s *vdec, int event, int para1, int para2); +extern void vdec_profile_flush(struct vdec_s *vdec); + +int vdec_profile_init_debugfs(void); +void vdec_profile_exit_debugfs(void); + +#endif /* VDEC_PROFILE_H */ diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec_trace.h b/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec_trace.h new file mode 100644 index 000000000000..e09518ef7d90 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec_trace.h @@ -0,0 +1,149 @@ +/* + * drivers/amlogic/amports/vdec_trace.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * +*/ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM vdec + +#if !defined(_VDEC_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _VDEC_TRACE_H + +#include + +struct vdec_s; + +/* single lifecycle events */ +DECLARE_EVENT_CLASS(vdec_event_class, + TP_PROTO(struct vdec_s *vdec), + TP_ARGS(vdec), + TP_STRUCT__entry( + __field(struct vdec_s *, vdec) + ), + TP_fast_assign( + __entry->vdec = vdec; + ), + TP_printk("[%p]", __entry->vdec) +); + +#define DEFINE_VDEC_EVENT(name) \ +DEFINE_EVENT(vdec_event_class, name, \ + TP_PROTO(struct vdec_s *vdec), \ + TP_ARGS(vdec)) + +DEFINE_VDEC_EVENT(vdec_create); +DEFINE_VDEC_EVENT(vdec_connect); +DEFINE_VDEC_EVENT(vdec_disconnect); +DEFINE_VDEC_EVENT(vdec_destroy); +DEFINE_VDEC_EVENT(vdec_reset); +DEFINE_VDEC_EVENT(vdec_release); + +/* set format event */ +#define format_name(format) \ + __print_symbolic(format, \ + {0, "MPEG"}, \ + {1, "MPEG4"}, \ + {2, "H264"}, \ + {3, "MJPEG"}, \ + {4, "REAL"}, \ + {5, "JPEG"}, \ + {6, "VC1"}, \ + {7, "AVS"}, \ + {8, "YUV"}, \ + {9, "H264MVC"}, \ + {10, "H264_4K2K"}, \ + {11, "H265"}, \ + {12, "ENC_AVC"}, \ + {13, "ENC_JPEG"}, \ + {14, "VP9"}) + +TRACE_EVENT(vdec_set_format, + TP_PROTO(struct vdec_s *vdec, int format), + TP_ARGS(vdec, format), + TP_STRUCT__entry( + __field(struct vdec_s *, vdec) + __field(int, format) + ), + TP_fast_assign( + __entry->vdec = vdec; + __entry->format = format; + ), + TP_printk("[%p]:%s", __entry->vdec, + format_name(__entry->format)) +); + +/* status events */ +#define status_name(status) \ + __print_symbolic(status, \ + {0, "UNINITIALIZED"}, \ + {1, "DISCONNECTED"}, \ + {2, "CONNECTED"}, \ + {3, "ACTIVE"}) + +DECLARE_EVENT_CLASS(vdec_status_class, + TP_PROTO(struct vdec_s *vdec, int state), + TP_ARGS(vdec, state), + TP_STRUCT__entry( + __field(struct vdec_s *, vdec) + __field(int, state) + ), + TP_fast_assign( + __entry->vdec = vdec; + __entry->state = state; + ), + TP_printk("[%p]:%s", __entry->vdec, status_name(__entry->state)) +); + +#define DEFINE_STATUS_EVENT(name) \ +DEFINE_EVENT(vdec_status_class, name, \ + TP_PROTO(struct vdec_s *vdec, int status), \ + TP_ARGS(vdec, status)) + +DEFINE_STATUS_EVENT(vdec_set_status); +DEFINE_STATUS_EVENT(vdec_set_next_status); + +/* set pts events */ +DECLARE_EVENT_CLASS(vdec_pts_class, + TP_PROTO(struct vdec_s *vdec, u64 pts), + TP_ARGS(vdec, pts), + TP_STRUCT__entry( + __field(struct vdec_s *, vdec) + __field(u64, pts) + ), + TP_fast_assign( + __entry->vdec = vdec; + __entry->pts = pts; + ), + TP_printk("[%p]%llu", __entry->vdec, __entry->pts) +); + +#define DEFINE_PTS_EVENT(name) \ +DEFINE_EVENT(vdec_pts_class, name, \ + TP_PROTO(struct vdec_s *vdec, u64 pts), \ + TP_ARGS(vdec, pts)) + +DEFINE_PTS_EVENT(vdec_set_pts); +DEFINE_PTS_EVENT(vdec_set_pts64); + +#endif /* _VDEC_TRACE_H */ + +/* +#undef TRACE_INCLUDE_PATH +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_PATH . +#define TRACE_INCLUDE_FILE vdec_trace +#include +*/ +/**/ //DEBUG_TMP diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/vc1/Makefile b/drivers/amlogic/media_modules/frame_provider/decoder/vc1/Makefile new file mode 100644 index 000000000000..b43a6002e1b2 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/vc1/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_AMLOGIC_MEDIA_VDEC_VC1) += amvdec_vc1.o +amvdec_vc1-objs += vvc1.o diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/vc1/vvc1.c b/drivers/amlogic/media_modules/frame_provider/decoder/vc1/vvc1.c new file mode 100644 index 000000000000..49517eebf562 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/vc1/vvc1.c @@ -0,0 +1,1255 @@ +/* + * drivers/amlogic/amports/vvc1.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "../utils/amvdec.h" +#include "../utils/vdec.h" +#include +#include "../../../stream_input/amports/amports_priv.h" +#include "../utils/decoder_mmu_box.h" +#include "../utils/decoder_bmmu_box.h" +#include +#include +#include "../utils/firmware.h" +#include + +#define DRIVER_NAME "amvdec_vc1" +#define MODULE_NAME "amvdec_vc1" + +#define DEBUG_PTS +#if 1 /* //MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ +#define NV21 +#endif + +#define I_PICTURE 0 +#define P_PICTURE 1 +#define B_PICTURE 2 + +#define ORI_BUFFER_START_ADDR 0x01000000 + +#define INTERLACE_FLAG 0x80 +#define BOTTOM_FIELD_FIRST_FLAG 0x40 + +/* protocol registers */ +#define VC1_PIC_RATIO AV_SCRATCH_0 +#define VC1_ERROR_COUNT AV_SCRATCH_6 +#define VC1_SOS_COUNT AV_SCRATCH_7 +#define VC1_BUFFERIN AV_SCRATCH_8 +#define VC1_BUFFEROUT AV_SCRATCH_9 +#define VC1_REPEAT_COUNT AV_SCRATCH_A +#define VC1_TIME_STAMP AV_SCRATCH_B +#define VC1_OFFSET_REG AV_SCRATCH_C +#define MEM_OFFSET_REG AV_SCRATCH_F + +#define VF_POOL_SIZE 16 +#define DECODE_BUFFER_NUM_MAX 4 +#define WORKSPACE_SIZE (2 * SZ_1M) +#define MAX_BMMU_BUFFER_NUM (DECODE_BUFFER_NUM_MAX + 1) +#define VF_BUFFER_IDX(n) (1 + n) +#define DCAC_BUFF_START_ADDR 0x01f00000 + + +#define PUT_INTERVAL (HZ/100) + +#if 1 /* /MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ +/* TODO: move to register headers */ +#define VPP_VD1_POSTBLEND (1 << 10) +#define MEM_FIFO_CNT_BIT 16 +#define MEM_LEVEL_CNT_BIT 18 +#endif +static struct vdec_info *gvs; + +static struct vframe_s *vvc1_vf_peek(void *); +static struct vframe_s *vvc1_vf_get(void *); +static void vvc1_vf_put(struct vframe_s *, void *); +static int vvc1_vf_states(struct vframe_states *states, void *); +static int vvc1_event_cb(int type, void *data, void *private_data); + +static int vvc1_prot_init(void); +static void vvc1_local_init(void); + +static const char vvc1_dec_id[] = "vvc1-dev"; + +#define PROVIDER_NAME "decoder.vc1" +static const struct vframe_operations_s vvc1_vf_provider = { + .peek = vvc1_vf_peek, + .get = vvc1_vf_get, + .put = vvc1_vf_put, + .event_cb = vvc1_event_cb, + .vf_states = vvc1_vf_states, +}; +static void *mm_blk_handle; +static struct vframe_provider_s vvc1_vf_prov; + +static DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE); +static DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE); +static DECLARE_KFIFO(recycle_q, struct vframe_s *, VF_POOL_SIZE); + +static struct vframe_s vfpool[VF_POOL_SIZE]; +static struct vframe_s vfpool2[VF_POOL_SIZE]; +static int cur_pool_idx; + +static s32 vfbuf_use[DECODE_BUFFER_NUM_MAX]; +static struct timer_list recycle_timer; +static u32 stat; +static u32 buf_size = 32 * 1024 * 1024; +static u32 buf_offset; +static u32 avi_flag; +static u32 vvc1_ratio; +static u32 vvc1_format; + +static u32 intra_output; +static u32 frame_width, frame_height, frame_dur; +static u32 saved_resolution; +static u32 pts_by_offset = 1; +static u32 total_frame; +static u32 next_pts; +static u64 next_pts_us64; +static bool is_reset; +static struct work_struct set_clk_work; + +#ifdef DEBUG_PTS +static u32 pts_hit, pts_missed, pts_i_hit, pts_i_missed; +#endif +static DEFINE_SPINLOCK(lock); + +static struct dec_sysinfo vvc1_amstream_dec_info; + +struct frm_s { + int state; + u32 start_pts; + int num; + u32 end_pts; + u32 rate; + u32 trymax; +}; + +static struct frm_s frm; + +enum { + RATE_MEASURE_START_PTS = 0, + RATE_MEASURE_END_PTS, + RATE_MEASURE_DONE +}; +#define RATE_MEASURE_NUM 8 +#define RATE_CORRECTION_THRESHOLD 5 +#define RATE_24_FPS 3755 /* 23.97 */ +#define RATE_30_FPS 3003 /* 29.97 */ +#define DUR2PTS(x) ((x)*90/96) +#define PTS2DUR(x) ((x)*96/90) + +static inline int pool_index(struct vframe_s *vf) +{ + if ((vf >= &vfpool[0]) && (vf <= &vfpool[VF_POOL_SIZE - 1])) + return 0; + else if ((vf >= &vfpool2[0]) && (vf <= &vfpool2[VF_POOL_SIZE - 1])) + return 1; + else + return -1; +} + +static inline bool close_to(int a, int b, int m) +{ + return abs(a - b) < m; +} + +static inline u32 index2canvas(u32 index) +{ + const u32 canvas_tab[DECODE_BUFFER_NUM_MAX] = { +#if 1 /* ALWASY.MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ + 0x010100, 0x030302, 0x050504, 0x070706/*, + 0x090908, 0x0b0b0a, 0x0d0d0c, 0x0f0f0e*/ +#else + 0x020100, 0x050403, 0x080706, 0x0b0a09 +#endif + }; + + return canvas_tab[index]; +} + +static void set_aspect_ratio(struct vframe_s *vf, unsigned int pixel_ratio) +{ + int ar = 0; + + if (vvc1_ratio == 0) { + /* always stretch to 16:9 */ + vf->ratio_control |= (0x90 << DISP_RATIO_ASPECT_RATIO_BIT); + } else if (pixel_ratio > 0x0f) { + ar = (vvc1_amstream_dec_info.height * (pixel_ratio & 0xff) * + vvc1_ratio) / (vvc1_amstream_dec_info.width * + (pixel_ratio >> 8)); + } else { + switch (pixel_ratio) { + case 0: + ar = (vvc1_amstream_dec_info.height * vvc1_ratio) / + vvc1_amstream_dec_info.width; + break; + case 1: + ar = (vf->height * vvc1_ratio) / vf->width; + break; + case 2: + ar = (vf->height * 11 * vvc1_ratio) / (vf->width * 12); + break; + case 3: + ar = (vf->height * 11 * vvc1_ratio) / (vf->width * 10); + break; + case 4: + ar = (vf->height * 11 * vvc1_ratio) / (vf->width * 16); + break; + case 5: + ar = (vf->height * 33 * vvc1_ratio) / (vf->width * 40); + break; + case 6: + ar = (vf->height * 11 * vvc1_ratio) / (vf->width * 24); + break; + case 7: + ar = (vf->height * 11 * vvc1_ratio) / (vf->width * 20); + break; + case 8: + ar = (vf->height * 11 * vvc1_ratio) / (vf->width * 32); + break; + case 9: + ar = (vf->height * 33 * vvc1_ratio) / (vf->width * 80); + break; + case 10: + ar = (vf->height * 11 * vvc1_ratio) / (vf->width * 18); + break; + case 11: + ar = (vf->height * 11 * vvc1_ratio) / (vf->width * 15); + break; + case 12: + ar = (vf->height * 33 * vvc1_ratio) / (vf->width * 64); + break; + case 13: + ar = (vf->height * 99 * vvc1_ratio) / + (vf->width * 160); + break; + default: + ar = (vf->height * vvc1_ratio) / vf->width; + break; + } + } + + ar = min(ar, DISP_RATIO_ASPECT_RATIO_MAX); + + vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT); + /*vf->ratio_control |= DISP_RATIO_FORCECONFIG | DISP_RATIO_KEEPRATIO;*/ +} + +static irqreturn_t vvc1_isr(int irq, void *dev_id) +{ + u32 reg; + struct vframe_s *vf = NULL; + u32 repeat_count; + u32 picture_type; + u32 buffer_index; + unsigned int pts, pts_valid = 0, offset; + u32 v_width, v_height; + u64 pts_us64 = 0; + + reg = READ_VREG(VC1_BUFFEROUT); + + if (reg) { + v_width = READ_VREG(AV_SCRATCH_J); + v_height = READ_VREG(AV_SCRATCH_K); + + if (v_width && v_width <= 4096 + && (v_width != vvc1_amstream_dec_info.width)) { + pr_info("frame width changed %d to %d\n", + vvc1_amstream_dec_info.width, v_width); + vvc1_amstream_dec_info.width = v_width; + frame_width = v_width; + } + if (v_height && v_height <= 4096 + && (v_height != vvc1_amstream_dec_info.height)) { + pr_info("frame height changed %d to %d\n", + vvc1_amstream_dec_info.height, v_height); + vvc1_amstream_dec_info.height = v_height; + frame_height = v_height; + } + + if (pts_by_offset) { + offset = READ_VREG(VC1_OFFSET_REG); + if (pts_lookup_offset_us64( + PTS_TYPE_VIDEO, + offset, &pts, 0, &pts_us64) == 0) { + pts_valid = 1; +#ifdef DEBUG_PTS + pts_hit++; +#endif + } else { +#ifdef DEBUG_PTS + pts_missed++; +#endif + } + } + + repeat_count = READ_VREG(VC1_REPEAT_COUNT); + buffer_index = ((reg & 0x7) - 1) & 3; + picture_type = (reg >> 3) & 7; + + if (buffer_index >= DECODE_BUFFER_NUM_MAX) { + pr_info("fatal error, invalid buffer index."); + return IRQ_HANDLED; + } + + if ((intra_output == 0) && (picture_type != 0)) { + WRITE_VREG(VC1_BUFFERIN, ~(1 << buffer_index)); + WRITE_VREG(VC1_BUFFEROUT, 0); + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + return IRQ_HANDLED; + } + + intra_output = 1; + +#ifdef DEBUG_PTS + if (picture_type == I_PICTURE) { + /* pr_info("I offset 0x%x, + *pts_valid %d\n", offset, pts_valid); + */ + if (!pts_valid) + pts_i_missed++; + else + pts_i_hit++; + } +#endif + + if ((pts_valid) && (frm.state != RATE_MEASURE_DONE)) { + if (frm.state == RATE_MEASURE_START_PTS) { + frm.start_pts = pts; + frm.state = RATE_MEASURE_END_PTS; + frm.trymax = RATE_MEASURE_NUM; + } else if (frm.state == RATE_MEASURE_END_PTS) { + if (frm.num >= frm.trymax) { + frm.end_pts = pts; + frm.rate = (frm.end_pts - + frm.start_pts) / frm.num; + pr_info("frate before=%d,%d,num=%d\n", + frm.rate, + DUR2PTS(vvc1_amstream_dec_info.rate), + frm.num); + /* check if measured rate is same as + * settings from upper layer + * and correct it if necessary + */ + if ((close_to(frm.rate, RATE_30_FPS, + RATE_CORRECTION_THRESHOLD) && + close_to( + DUR2PTS( + vvc1_amstream_dec_info.rate), + RATE_24_FPS, + RATE_CORRECTION_THRESHOLD)) + || + (close_to( + frm.rate, RATE_24_FPS, + RATE_CORRECTION_THRESHOLD) + && + close_to(DUR2PTS( + vvc1_amstream_dec_info.rate), + RATE_30_FPS, + RATE_CORRECTION_THRESHOLD))) { + pr_info( + "vvc1: frate from %d to %d\n", + vvc1_amstream_dec_info.rate, + PTS2DUR(frm.rate)); + + vvc1_amstream_dec_info.rate = + PTS2DUR(frm.rate); + frm.state = RATE_MEASURE_DONE; + } else if (close_to(frm.rate, + DUR2PTS( + vvc1_amstream_dec_info.rate), + RATE_CORRECTION_THRESHOLD)) + frm.state = RATE_MEASURE_DONE; + else { + +/* maybe still have problem, + * try next double frames.... + */ + frm.state = RATE_MEASURE_DONE; + frm.start_pts = pts; + frm.state = + RATE_MEASURE_END_PTS; + /*60 fps*60 S */ + frm.num = 0; + } + } + } + } + + if (frm.state != RATE_MEASURE_DONE) + frm.num += (repeat_count > 1) ? repeat_count : 1; + if (vvc1_amstream_dec_info.rate == 0) + vvc1_amstream_dec_info.rate = PTS2DUR(frm.rate); + + if (reg & INTERLACE_FLAG) { /* interlace */ + if (kfifo_get(&newframe_q, &vf) == 0) { + pr_info + ("fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + vf->signal_type = 0; + vf->index = buffer_index; + vf->width = vvc1_amstream_dec_info.width; + vf->height = vvc1_amstream_dec_info.height; + vf->bufWidth = 1920; + vf->flag = 0; + + if (pts_valid) { + vf->pts = pts; + vf->pts_us64 = pts_us64; + if ((repeat_count > 1) && avi_flag) { + vf->duration = + vvc1_amstream_dec_info.rate * + repeat_count >> 1; + next_pts = pts + + (vvc1_amstream_dec_info.rate * + repeat_count >> 1) * 15 / 16; + next_pts_us64 = pts_us64 + + ((vvc1_amstream_dec_info.rate * + repeat_count >> 1) * 15 / 16) * + 100 / 9; + } else { + vf->duration = + vvc1_amstream_dec_info.rate >> 1; + next_pts = 0; + next_pts_us64 = 0; + } + } else { + vf->pts = next_pts; + vf->pts_us64 = next_pts_us64; + if ((repeat_count > 1) && avi_flag) { + vf->duration = + vvc1_amstream_dec_info.rate * + repeat_count >> 1; + if (next_pts != 0) { + next_pts += ((vf->duration) - + ((vf->duration) >> 4)); + } + if (next_pts_us64 != 0) { + next_pts_us64 += + ((vf->duration) - + ((vf->duration) >> 4)) * + 100 / 9; + } + } else { + vf->duration = + vvc1_amstream_dec_info.rate >> 1; + next_pts = 0; + next_pts_us64 = 0; + } + } + + vf->duration_pulldown = 0; + vf->type = (reg & BOTTOM_FIELD_FIRST_FLAG) ? + VIDTYPE_INTERLACE_BOTTOM : VIDTYPE_INTERLACE_TOP; +#ifdef NV21 + vf->type |= VIDTYPE_VIU_NV21; +#endif + vf->canvas0Addr = vf->canvas1Addr = + index2canvas(buffer_index); + vf->orientation = 0; + vf->type_original = vf->type; + set_aspect_ratio(vf, READ_VREG(VC1_PIC_RATIO)); + + vfbuf_use[buffer_index]++; + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + buffer_index); + + kfifo_put(&display_q, (const struct vframe_s *)vf); + + vf_notify_receiver( + PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + + if (kfifo_get(&newframe_q, &vf) == 0) { + pr_info + ("fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + vf->signal_type = 0; + vf->index = buffer_index; + vf->width = vvc1_amstream_dec_info.width; + vf->height = vvc1_amstream_dec_info.height; + vf->bufWidth = 1920; + vf->flag = 0; + + vf->pts = next_pts; + vf->pts_us64 = next_pts_us64; + if ((repeat_count > 1) && avi_flag) { + vf->duration = + vvc1_amstream_dec_info.rate * + repeat_count >> 1; + if (next_pts != 0) { + next_pts += + ((vf->duration) - + ((vf->duration) >> 4)); + } + if (next_pts_us64 != 0) { + next_pts_us64 += ((vf->duration) - + ((vf->duration) >> 4)) * 100 / 9; + } + } else { + vf->duration = + vvc1_amstream_dec_info.rate >> 1; + next_pts = 0; + next_pts_us64 = 0; + } + + vf->duration_pulldown = 0; + vf->type = (reg & BOTTOM_FIELD_FIRST_FLAG) ? + VIDTYPE_INTERLACE_TOP : VIDTYPE_INTERLACE_BOTTOM; +#ifdef NV21 + vf->type |= VIDTYPE_VIU_NV21; +#endif + vf->canvas0Addr = vf->canvas1Addr = + index2canvas(buffer_index); + vf->orientation = 0; + vf->type_original = vf->type; + set_aspect_ratio(vf, READ_VREG(VC1_PIC_RATIO)); + + vfbuf_use[buffer_index]++; + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + buffer_index); + + kfifo_put(&display_q, (const struct vframe_s *)vf); + + vf_notify_receiver( + PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + } else { /* progressive */ + if (kfifo_get(&newframe_q, &vf) == 0) { + pr_info + ("fatal error, no available buffer slot."); + return IRQ_HANDLED; + } + vf->signal_type = 0; + vf->index = buffer_index; + vf->width = vvc1_amstream_dec_info.width; + vf->height = vvc1_amstream_dec_info.height; + vf->bufWidth = 1920; + vf->flag = 0; + + if (pts_valid) { + vf->pts = pts; + vf->pts_us64 = pts_us64; + if ((repeat_count > 1) && avi_flag) { + vf->duration = + vvc1_amstream_dec_info.rate * + repeat_count; + next_pts = + pts + + (vvc1_amstream_dec_info.rate * + repeat_count) * 15 / 16; + next_pts_us64 = pts_us64 + + ((vvc1_amstream_dec_info.rate * + repeat_count) * 15 / 16) * + 100 / 9; + } else { + vf->duration = + vvc1_amstream_dec_info.rate; + next_pts = 0; + next_pts_us64 = 0; + } + } else { + vf->pts = next_pts; + vf->pts_us64 = next_pts_us64; + if ((repeat_count > 1) && avi_flag) { + vf->duration = + vvc1_amstream_dec_info.rate * + repeat_count; + if (next_pts != 0) { + next_pts += ((vf->duration) - + ((vf->duration) >> 4)); + } + if (next_pts_us64 != 0) { + next_pts_us64 += + ((vf->duration) - + ((vf->duration) >> 4)) * + 100 / 9; + } + } else { + vf->duration = + vvc1_amstream_dec_info.rate; + next_pts = 0; + next_pts_us64 = 0; + } + } + + vf->duration_pulldown = 0; +#ifdef NV21 + vf->type = + VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD | + VIDTYPE_VIU_NV21; +#else + vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD; +#endif + vf->canvas0Addr = vf->canvas1Addr = + index2canvas(buffer_index); + vf->orientation = 0; + vf->type_original = vf->type; + set_aspect_ratio(vf, READ_VREG(VC1_PIC_RATIO)); + + vfbuf_use[buffer_index]++; + vf->mem_handle = + decoder_bmmu_box_get_mem_handle( + mm_blk_handle, + buffer_index); + kfifo_put(&display_q, (const struct vframe_s *)vf); + + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_VFRAME_READY, + NULL); + } + frame_dur = vvc1_amstream_dec_info.rate; + total_frame++; + + /*count info*/ + gvs->frame_dur = frame_dur; + vdec_count_info(gvs, 0, offset); + + /* pr_info("PicType = %d, PTS = 0x%x, repeat + *count %d\n", picture_type, vf->pts, repeat_count); + */ + WRITE_VREG(VC1_BUFFEROUT, 0); + } + + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + return IRQ_HANDLED; +} + +static struct vframe_s *vvc1_vf_peek(void *op_arg) +{ + struct vframe_s *vf; + + if (kfifo_peek(&display_q, &vf)) + return vf; + + return NULL; +} + +static struct vframe_s *vvc1_vf_get(void *op_arg) +{ + struct vframe_s *vf; + + if (kfifo_get(&display_q, &vf)) + return vf; + + return NULL; +} + +static void vvc1_vf_put(struct vframe_s *vf, void *op_arg) +{ + if (pool_index(vf) == cur_pool_idx) + kfifo_put(&recycle_q, (const struct vframe_s *)vf); +} + +static int vvc1_vf_states(struct vframe_states *states, void *op_arg) +{ + unsigned long flags; + + spin_lock_irqsave(&lock, flags); + + states->vf_pool_size = VF_POOL_SIZE; + states->buf_free_num = kfifo_len(&newframe_q); + states->buf_avail_num = kfifo_len(&display_q); + states->buf_recycle_num = kfifo_len(&recycle_q); + + spin_unlock_irqrestore(&lock, flags); + + return 0; +} + +static int vvc1_event_cb(int type, void *data, void *private_data) +{ + if (type & VFRAME_EVENT_RECEIVER_RESET) { + unsigned long flags; + + amvdec_stop(); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_light_unreg_provider(&vvc1_vf_prov); +#endif + spin_lock_irqsave(&lock, flags); + vvc1_local_init(); + vvc1_prot_init(); + spin_unlock_irqrestore(&lock, flags); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_reg_provider(&vvc1_vf_prov); +#endif + amvdec_start(); + } + return 0; +} + +int vvc1_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus) +{ + vstatus->frame_width = vvc1_amstream_dec_info.width; + vstatus->frame_height = vvc1_amstream_dec_info.height; + if (vvc1_amstream_dec_info.rate != 0) + vstatus->frame_rate = 96000 / vvc1_amstream_dec_info.rate; + else + vstatus->frame_rate = -1; + vstatus->error_count = READ_VREG(AV_SCRATCH_C); + vstatus->status = stat; + vstatus->bit_rate = gvs->bit_rate; + vstatus->frame_dur = vvc1_amstream_dec_info.rate; + vstatus->frame_data = gvs->frame_data; + vstatus->total_data = gvs->total_data; + vstatus->frame_count = gvs->frame_count; + vstatus->error_frame_count = gvs->error_frame_count; + vstatus->drop_frame_count = gvs->drop_frame_count; + vstatus->total_data = gvs->total_data; + vstatus->samp_cnt = gvs->samp_cnt; + vstatus->offset = gvs->offset; + snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name), + "%s", DRIVER_NAME); + + return 0; +} + +int vvc1_set_isreset(struct vdec_s *vdec, int isreset) +{ + is_reset = isreset; + return 0; +} + +static int vvc1_vdec_info_init(void) +{ + gvs = kzalloc(sizeof(struct vdec_info), GFP_KERNEL); + if (NULL == gvs) { + pr_info("the struct of vdec status malloc failed.\n"); + return -ENOMEM; + } + return 0; +} + +/****************************************/ +static int vvc1_canvas_init(void) +{ + int i, ret; + u32 canvas_width, canvas_height; + u32 alloc_size, decbuf_size, decbuf_y_size, decbuf_uv_size; + unsigned long buf_start; + + if (buf_size <= 0x00400000) { + /* SD only */ + canvas_width = 768; + canvas_height = 576; + decbuf_y_size = 0x80000; + decbuf_uv_size = 0x20000; + decbuf_size = 0x100000; + } else { + /* HD & SD */ + canvas_width = 1920; + canvas_height = 1088; + decbuf_y_size = 0x200000; + decbuf_uv_size = 0x80000; + decbuf_size = 0x300000; + } + + for (i = 0; i < MAX_BMMU_BUFFER_NUM; i++) { + /* workspace mem */ + if (i == (MAX_BMMU_BUFFER_NUM - 1)) + alloc_size = WORKSPACE_SIZE; + else + alloc_size = decbuf_size; + + ret = decoder_bmmu_box_alloc_buf_phy(mm_blk_handle, i, + alloc_size, DRIVER_NAME, &buf_start); + if (ret < 0) + return ret; + if (i == (MAX_BMMU_BUFFER_NUM - 1)) { + buf_offset = buf_start - DCAC_BUFF_START_ADDR; + continue; + } + +#ifdef NV21 + canvas_config(2 * i + 0, + buf_start, + canvas_width, canvas_height, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); + canvas_config(2 * i + 1, + buf_start + + decbuf_y_size, canvas_width, + canvas_height / 2, CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_32X32); +#else + canvas_config(3 * i + 0, + buf_start, + canvas_width, canvas_height, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); + canvas_config(3 * i + 1, + buf_start + + decbuf_y_size, canvas_width / 2, + canvas_height / 2, CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_32X32); + canvas_config(3 * i + 2, + buf_start + + decbuf_y_size + decbuf_uv_size, + canvas_width / 2, canvas_height / 2, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_32X32); +#endif + + } + return 0; +} + +static int vvc1_prot_init(void) +{ + int r; +#if 1 /* /MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ + WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4)); + WRITE_VREG(DOS_SW_RESET0, 0); + + READ_VREG(DOS_SW_RESET0); + + WRITE_VREG(DOS_SW_RESET0, (1 << 7) | (1 << 6) | (1 << 4)); + WRITE_VREG(DOS_SW_RESET0, 0); + + WRITE_VREG(DOS_SW_RESET0, (1 << 9) | (1 << 8)); + WRITE_VREG(DOS_SW_RESET0, 0); + +#else + WRITE_RESET_REG(RESET0_REGISTER, + RESET_IQIDCT | RESET_MC | RESET_VLD_PART); + READ_RESET_REG(RESET0_REGISTER); + WRITE_RESET_REG(RESET0_REGISTER, + RESET_IQIDCT | RESET_MC | RESET_VLD_PART); + + WRITE_RESET_REG(RESET2_REGISTER, RESET_PIC_DC | RESET_DBLK); +#endif + + WRITE_VREG(POWER_CTL_VLD, 0x10); + WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL, 2, MEM_FIFO_CNT_BIT, 2); + WRITE_VREG_BITS(VLD_MEM_VIFIFO_CONTROL, 8, MEM_LEVEL_CNT_BIT, 6); + + r = vvc1_canvas_init(); + + /* index v << 16 | u << 8 | y */ +#ifdef NV21 + WRITE_VREG(AV_SCRATCH_0, 0x010100); + WRITE_VREG(AV_SCRATCH_1, 0x030302); + WRITE_VREG(AV_SCRATCH_2, 0x050504); + WRITE_VREG(AV_SCRATCH_3, 0x070706); +/* WRITE_VREG(AV_SCRATCH_G, 0x090908); + WRITE_VREG(AV_SCRATCH_H, 0x0b0b0a); + WRITE_VREG(AV_SCRATCH_I, 0x0d0d0c); + WRITE_VREG(AV_SCRATCH_J, 0x0f0f0e);*/ +#else + WRITE_VREG(AV_SCRATCH_0, 0x020100); + WRITE_VREG(AV_SCRATCH_1, 0x050403); + WRITE_VREG(AV_SCRATCH_2, 0x080706); + WRITE_VREG(AV_SCRATCH_3, 0x0b0a09); + WRITE_VREG(AV_SCRATCH_G, 0x090908); + WRITE_VREG(AV_SCRATCH_H, 0x0b0b0a); + WRITE_VREG(AV_SCRATCH_I, 0x0d0d0c); + WRITE_VREG(AV_SCRATCH_J, 0x0f0f0e); +#endif + + /* notify ucode the buffer offset */ + WRITE_VREG(AV_SCRATCH_F, buf_offset); + + /* disable PSCALE for hardware sharing */ + WRITE_VREG(PSCALE_CTRL, 0); + + WRITE_VREG(VC1_SOS_COUNT, 0); + WRITE_VREG(VC1_BUFFERIN, 0); + WRITE_VREG(VC1_BUFFEROUT, 0); + + /* clear mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_CLR_REG, 1); + + /* enable mailbox interrupt */ + WRITE_VREG(ASSIST_MBOX1_MASK, 1); + +#ifdef NV21 + SET_VREG_MASK(MDEC_PIC_DC_CTRL, 1 << 17); +#endif + return r; +} + +static void vvc1_local_init(void) +{ + int i; + + /* vvc1_ratio = vvc1_amstream_dec_info.ratio; */ + vvc1_ratio = 0x100; + + avi_flag = (unsigned long) vvc1_amstream_dec_info.param; + + total_frame = 0; + + next_pts = 0; + + next_pts_us64 = 0; + saved_resolution = 0; + frame_width = frame_height = frame_dur = 0; +#ifdef DEBUG_PTS + pts_hit = pts_missed = pts_i_hit = pts_i_missed = 0; +#endif + + memset(&frm, 0, sizeof(frm)); + + for (i = 0; i < DECODE_BUFFER_NUM_MAX; i++) + vfbuf_use[i] = 0; + + INIT_KFIFO(display_q); + INIT_KFIFO(recycle_q); + INIT_KFIFO(newframe_q); + cur_pool_idx ^= 1; + for (i = 0; i < VF_POOL_SIZE; i++) { + const struct vframe_s *vf; + + if (cur_pool_idx == 0) { + vf = &vfpool[i]; + vfpool[i].index = DECODE_BUFFER_NUM_MAX; + } else { + vf = &vfpool2[i]; + vfpool2[i].index = DECODE_BUFFER_NUM_MAX; + } + kfifo_put(&newframe_q, (const struct vframe_s *)vf); + } + if (mm_blk_handle) { + decoder_bmmu_box_free(mm_blk_handle); + mm_blk_handle = NULL; + } + + mm_blk_handle = decoder_bmmu_box_alloc_box( + DRIVER_NAME, + 0, + MAX_BMMU_BUFFER_NUM, + 4 + PAGE_SHIFT, + CODEC_MM_FLAGS_CMA_CLEAR | + CODEC_MM_FLAGS_FOR_VDECODER); +} + +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER +static void vvc1_ppmgr_reset(void) +{ + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_RESET, NULL); + + vvc1_local_init(); + + /* vf_notify_receiver(PROVIDER_NAME, + * VFRAME_EVENT_PROVIDER_START,NULL); + */ + + pr_info("vvc1dec: vf_ppmgr_reset\n"); +} +#endif + +static void vvc1_set_clk(struct work_struct *work) +{ + if (frame_dur > 0 && saved_resolution != + frame_width * frame_height * (96000 / frame_dur)) { + int fps = 96000 / frame_dur; + + saved_resolution = frame_width * frame_height * fps; + vdec_source_changed(VFORMAT_VC1, + frame_width, frame_height, fps); + } +} + +static void vvc1_put_timer_func(unsigned long arg) +{ + struct timer_list *timer = (struct timer_list *)arg; + +#if 1 + if (READ_VREG(VC1_SOS_COUNT) > 10) { + amvdec_stop(); +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vvc1_ppmgr_reset(); +#else + vf_light_unreg_provider(&vvc1_vf_prov); + vvc1_local_init(); + vf_reg_provider(&vvc1_vf_prov); +#endif + vvc1_prot_init(); + amvdec_start(); + } +#endif + + while (!kfifo_is_empty(&recycle_q) && (READ_VREG(VC1_BUFFERIN) == 0)) { + struct vframe_s *vf; + + if (kfifo_get(&recycle_q, &vf)) { + if ((vf->index < DECODE_BUFFER_NUM_MAX) && + (--vfbuf_use[vf->index] == 0)) { + WRITE_VREG(VC1_BUFFERIN, ~(1 << vf->index)); + vf->index = DECODE_BUFFER_NUM_MAX; + } + if (pool_index(vf) == cur_pool_idx) + kfifo_put(&newframe_q, (const struct vframe_s *)vf); + } + } + schedule_work(&set_clk_work); + timer->expires = jiffies + PUT_INTERVAL; + + add_timer(timer); +} + +static s32 vvc1_init(void) +{ + int ret = -1, size = -1; + char *buf = vmalloc(0x1000 * 16); + int fw_type = VIDEO_DEC_VC1; + + if (IS_ERR_OR_NULL(buf)) + return -ENOMEM; + + pr_info("vvc1_init, format %d\n", vvc1_amstream_dec_info.format); + init_timer(&recycle_timer); + + stat |= STAT_TIMER_INIT; + + intra_output = 0; + amvdec_enable(); + + vvc1_local_init(); + + if (vvc1_amstream_dec_info.format == VIDEO_DEC_FORMAT_WMV3) { + pr_info("WMV3 dec format\n"); + vvc1_format = VIDEO_DEC_FORMAT_WMV3; + WRITE_VREG(AV_SCRATCH_4, 0); + } else if (vvc1_amstream_dec_info.format == VIDEO_DEC_FORMAT_WVC1) { + pr_info("WVC1 dec format\n"); + vvc1_format = VIDEO_DEC_FORMAT_WVC1; + WRITE_VREG(AV_SCRATCH_4, 1); + } else + pr_info("not supported VC1 format\n"); + + size = get_firmware_data(fw_type, buf); + if (size < 0) { + amvdec_disable(); + pr_err("get firmware fail."); + vfree(buf); + return -1; + } + + if (size == 1) + pr_info("tee load ok\n"); + else if (amvdec_loadmc_ex(VFORMAT_VC1, NULL, buf) < 0) { + amvdec_disable(); + vfree(buf); + return -EBUSY; + } + + vfree(buf); + + stat |= STAT_MC_LOAD; + + /* enable AMRISC side protocol */ + ret = vvc1_prot_init(); + if (ret < 0) + return ret; + + if (vdec_request_irq(VDEC_IRQ_1, vvc1_isr, + "vvc1-irq", (void *)vvc1_dec_id)) { + amvdec_disable(); + + pr_info("vvc1 irq register error.\n"); + return -ENOENT; + } + + stat |= STAT_ISR_REG; +#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_provider_init(&vvc1_vf_prov, + PROVIDER_NAME, &vvc1_vf_provider, NULL); + vf_reg_provider(&vvc1_vf_prov); + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_START, NULL); +#else + vf_provider_init(&vvc1_vf_prov, + PROVIDER_NAME, &vvc1_vf_provider, NULL); + vf_reg_provider(&vvc1_vf_prov); +#endif + + if (!is_reset) + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_FR_HINT, + (void *) + ((unsigned long)vvc1_amstream_dec_info.rate)); + + stat |= STAT_VF_HOOK; + + recycle_timer.data = (ulong)&recycle_timer; + recycle_timer.function = vvc1_put_timer_func; + recycle_timer.expires = jiffies + PUT_INTERVAL; + + add_timer(&recycle_timer); + + stat |= STAT_TIMER_ARM; + + amvdec_start(); + + stat |= STAT_VDEC_RUN; + + return 0; +} + +static int amvdec_vc1_probe(struct platform_device *pdev) +{ + struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; + + if (pdata == NULL) { + pr_info("amvdec_vc1 memory resource undefined.\n"); + return -EFAULT; + } + + if (pdata->sys_info) + vvc1_amstream_dec_info = *pdata->sys_info; + + pdata->dec_status = vvc1_dec_status; + pdata->set_isreset = vvc1_set_isreset; + is_reset = 0; + + vvc1_vdec_info_init(); + + if (vvc1_init() < 0) { + pr_info("amvdec_vc1 init failed.\n"); + kfree(gvs); + gvs = NULL; + return -ENODEV; + } + INIT_WORK(&set_clk_work, vvc1_set_clk); + return 0; +} + +static int amvdec_vc1_remove(struct platform_device *pdev) +{ + cancel_work_sync(&set_clk_work); + if (stat & STAT_VDEC_RUN) { + amvdec_stop(); + stat &= ~STAT_VDEC_RUN; + } + + if (stat & STAT_ISR_REG) { + vdec_free_irq(VDEC_IRQ_1, (void *)vvc1_dec_id); + stat &= ~STAT_ISR_REG; + } + + if (stat & STAT_TIMER_ARM) { + del_timer_sync(&recycle_timer); + stat &= ~STAT_TIMER_ARM; + } + + if (stat & STAT_VF_HOOK) { + if (!is_reset) + vf_notify_receiver(PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_FR_END_HINT, + NULL); + + vf_unreg_provider(&vvc1_vf_prov); + stat &= ~STAT_VF_HOOK; + } + + amvdec_disable(); + + if (mm_blk_handle) { + decoder_bmmu_box_free(mm_blk_handle); + mm_blk_handle = NULL; + } + +#ifdef DEBUG_PTS + pr_debug("pts hit %d, pts missed %d, i hit %d, missed %d\n", pts_hit, + pts_missed, pts_i_hit, pts_i_missed); + pr_debug("total frame %d, avi_flag %d, rate %d\n", + total_frame, avi_flag, + vvc1_amstream_dec_info.rate); +#endif + kfree(gvs); + gvs = NULL; + + return 0; +} + +/****************************************/ + +static struct platform_driver amvdec_vc1_driver = { + .probe = amvdec_vc1_probe, + .remove = amvdec_vc1_remove, +#ifdef CONFIG_PM + .suspend = amvdec_suspend, + .resume = amvdec_resume, +#endif + .driver = { + .name = DRIVER_NAME, + } +}; + +#if defined(CONFIG_ARCH_MESON) /*meson1 only support progressive */ +static struct codec_profile_t amvdec_vc1_profile = { + .name = "vc1", + .profile = "progressive, wmv3" +}; +#else +static struct codec_profile_t amvdec_vc1_profile = { + .name = "vc1", + .profile = "progressive, interlace, wmv3" +}; +#endif + +static int __init amvdec_vc1_driver_init_module(void) +{ + pr_debug("amvdec_vc1 module init\n"); + + if (platform_driver_register(&amvdec_vc1_driver)) { + pr_err("failed to register amvdec_vc1 driver\n"); + return -ENODEV; + } + vcodec_profile_register(&amvdec_vc1_profile); + return 0; +} + +static void __exit amvdec_vc1_driver_remove_module(void) +{ + pr_debug("amvdec_vc1 module remove.\n"); + + platform_driver_unregister(&amvdec_vc1_driver); +} + +/****************************************/ +module_init(amvdec_vc1_driver_init_module); +module_exit(amvdec_vc1_driver_remove_module); + +MODULE_DESCRIPTION("AMLOGIC VC1 Video Decoder Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Qi Wang "); diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/vp9/Makefile b/drivers/amlogic/media_modules/frame_provider/decoder/vp9/Makefile new file mode 100644 index 000000000000..51edefe1e67d --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/vp9/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_AMLOGIC_MEDIA_VDEC_VP9) += amvdec_vp9.o +amvdec_vp9-objs += vvp9.o diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/vp9/vvp9.c b/drivers/amlogic/media_modules/frame_provider/decoder/vp9/vvp9.c new file mode 100644 index 000000000000..df2880dffd39 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/vp9/vvp9.c @@ -0,0 +1,9755 @@ + /* + * drivers/amlogic/amports/vvp9.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../../stream_input/amports/amports_priv.h" +#include +#include "../utils/decoder_mmu_box.h" +#include "../utils/decoder_bmmu_box.h" + +#define MEM_NAME "codec_vp9" +/* #include */ +#include +#include "../utils/vdec.h" +#include "../utils/amvdec.h" + +#include +#include +#include "../utils/config_parser.h" +#include "../utils/firmware.h" + +#define MIX_STREAM_SUPPORT +#define SUPPORT_4K2K + +#include "vvp9.h" + +#ifdef VP9_10B_MMU +/*#define SUPPORT_FB_DECODING*/ +/*#define FB_DECODING_TEST_SCHEDULE*/ +#endif + +#define HW_MASK_FRONT 0x1 +#define HW_MASK_BACK 0x2 + +#define VP9D_MPP_REFINFO_TBL_ACCCONFIG 0x3442 +#define VP9D_MPP_REFINFO_DATA 0x3443 +#define VP9D_MPP_REF_SCALE_ENBL 0x3441 +#define HEVC_MPRED_CTRL4 0x324c +#define HEVC_CM_HEADER_START_ADDR 0x3628 +#define HEVC_DBLK_CFGB 0x350b +#define HEVCD_MPP_ANC2AXI_TBL_DATA 0x3464 +#define HEVC_SAO_MMU_VH1_ADDR 0x363b +#define HEVC_SAO_MMU_VH0_ADDR 0x363a +#define HEVC_SAO_MMU_STATUS 0x3639 + +#define VP9_10B_DEC_IDLE 0 +#define VP9_10B_DEC_FRAME_HEADER 1 +#define VP9_10B_DEC_SLICE_SEGMENT 2 +#define VP9_10B_DECODE_SLICE 5 +#define VP9_10B_DISCARD_NAL 6 +#define VP9_DUMP_LMEM 7 +#define HEVC_DECPIC_DATA_DONE 0xa +#define HEVC_DECPIC_DATA_ERROR 0xb +#define HEVC_NAL_DECODE_DONE 0xe +#define HEVC_DECODE_BUFEMPTY 0x20 +#define HEVC_DECODE_TIMEOUT 0x21 +#define HEVC_SEARCH_BUFEMPTY 0x22 +#define HEVC_DECODE_OVER_SIZE 0x23 +#define HEVC_S2_DECODING_DONE 0x50 +#define VP9_HEAD_PARSER_DONE 0xf0 +#define VP9_HEAD_SEARCH_DONE 0xf1 +#define VP9_EOS 0xf2 +#define HEVC_ACTION_DONE 0xff + +#define VF_POOL_SIZE 32 + +#undef pr_info +#define pr_info printk + +#define DECODE_MODE_SINGLE ((0x80 << 24) | 0) +#define DECODE_MODE_MULTI_STREAMBASE ((0x80 << 24) | 1) +#define DECODE_MODE_MULTI_FRAMEBASE ((0x80 << 24) | 2) + + +#define VP9_TRIGGER_FRAME_DONE 0x100 +#define VP9_TRIGGER_FRAME_ENABLE 0x200 + +#define MV_MEM_UNIT 0x240 +/*--------------------------------------------------- + * Include "parser_cmd.h" + *--------------------------------------------------- + */ +#define PARSER_CMD_SKIP_CFG_0 0x0000090b + +#define PARSER_CMD_SKIP_CFG_1 0x1b14140f + +#define PARSER_CMD_SKIP_CFG_2 0x001b1910 + +#define PARSER_CMD_NUMBER 37 + +/*#define HEVC_PIC_STRUCT_SUPPORT*/ +/* to remove, fix build error */ + +/*#define CODEC_MM_FLAGS_FOR_VDECODER 0*/ + +#define MULTI_INSTANCE_SUPPORT +#define SUPPORT_10BIT +/* #define ERROR_HANDLE_DEBUG */ +#if 0 /* MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8B*/ +#undef SUPPORT_4K2K +#else +#define SUPPORT_4K2K +#endif + +#ifndef STAT_KTHREAD +#define STAT_KTHREAD 0x40 +#endif + +#ifdef MULTI_INSTANCE_SUPPORT +#define MAX_DECODE_INSTANCE_NUM 9 +#define MULTI_DRIVER_NAME "ammvdec_vp9" + +static unsigned int max_decode_instance_num + = MAX_DECODE_INSTANCE_NUM; +static unsigned int decode_frame_count[MAX_DECODE_INSTANCE_NUM]; +static unsigned int display_frame_count[MAX_DECODE_INSTANCE_NUM]; +static unsigned int max_process_time[MAX_DECODE_INSTANCE_NUM]; +static unsigned int run_count[MAX_DECODE_INSTANCE_NUM]; +static unsigned int input_empty[MAX_DECODE_INSTANCE_NUM]; +static unsigned int not_run_ready[MAX_DECODE_INSTANCE_NUM]; + +static u32 decode_timeout_val = 200; +static int start_decode_buf_level = 0x8000; +#ifdef VP9_10B_MMU +static u32 work_buf_size; /* = 24 * 1024 * 1024*/; +#else +static u32 work_buf_size = 32 * 1024 * 1024; +#endif + +static u32 mv_buf_margin; + +/* DOUBLE_WRITE_MODE is enabled only when NV21 8 bit output is needed */ +/* double_write_mode: 0, no double write + 1, 1:1 ratio + 2, (1/4):(1/4) ratio + 4, (1/2):(1/2) ratio + 0x10, double write only +*/ +static u32 double_write_mode; + +#define DRIVER_NAME "amvdec_vp9" +#define MODULE_NAME "amvdec_vp9" +#define DRIVER_HEADER_NAME "amvdec_vp9_header" + + +#define PUT_INTERVAL (HZ/100) +#define ERROR_SYSTEM_RESET_COUNT 200 + +#define PTS_NORMAL 0 +#define PTS_NONE_REF_USE_DURATION 1 + +#define PTS_MODE_SWITCHING_THRESHOLD 3 +#define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3 + +#define DUR2PTS(x) ((x)*90/96) + +struct VP9Decoder_s; +static int vvp9_vf_states(struct vframe_states *states, void *); +static struct vframe_s *vvp9_vf_peek(void *); +static struct vframe_s *vvp9_vf_get(void *); +static void vvp9_vf_put(struct vframe_s *, void *); +static int vvp9_event_cb(int type, void *data, void *private_data); + +static int vvp9_stop(struct VP9Decoder_s *pbi); +#ifdef MULTI_INSTANCE_SUPPORT +static s32 vvp9_init(struct vdec_s *vdec); +#else +static s32 vvp9_init(struct VP9Decoder_s *pbi); +#endif +static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask); +static int vvp9_local_init(struct VP9Decoder_s *pbi); +static void vvp9_put_timer_func(unsigned long arg); +static void dump_data(struct VP9Decoder_s *pbi, int size); +static unsigned char get_data_check_sum + (struct VP9Decoder_s *pbi, int size); +static void dump_pic_list(struct VP9Decoder_s *pbi); +#ifdef VP9_10B_MMU +static int vp9_alloc_mmu( + struct VP9Decoder_s *pbi, + int cur_buf_idx, + int pic_width, + int pic_height, + unsigned short bit_depth, + unsigned int *mmu_index_adr); +#endif + +static const char vvp9_dec_id[] = "vvp9-dev"; + +#define PROVIDER_NAME "decoder.vp9" +#define MULTI_INSTANCE_PROVIDER_NAME "vdec.vp9" + +static const struct vframe_operations_s vvp9_vf_provider = { + .peek = vvp9_vf_peek, + .get = vvp9_vf_get, + .put = vvp9_vf_put, + .event_cb = vvp9_event_cb, + .vf_states = vvp9_vf_states, +}; + +static struct vframe_provider_s vvp9_vf_prov; + +static u32 bit_depth_luma; +static u32 bit_depth_chroma; +static u32 frame_width; +static u32 frame_height; +static u32 video_signal_type; + +static u32 on_no_keyframe_skiped; + +#define PROB_SIZE (496 * 2 * 4) +#define PROB_BUF_SIZE (0x5000) +#define COUNT_BUF_SIZE (0x300 * 4 * 4) +/*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/ +#define MAX_FRAME_4K_NUM 0x1200 +#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4) + +#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009 + +#ifdef SUPPORT_FB_DECODING +/* register define */ +#define HEVC_ASSIST_HED_FB_W_CTL 0x3006 +#define HEVC_ASSIST_HED_FB_R_CTL 0x3007 +#define HEVC_ASSIST_HED_FB_ADDR 0x3008 +#define HEVC_ASSIST_FB_MMU_MAP_ADDR 0x300a +#define HEVC_ASSIST_FBD_MMU_MAP_ADDR 0x300b + + +#define MAX_STAGE_PAGE_NUM 0x1200 +#define STAGE_MMU_MAP_SIZE (MAX_STAGE_PAGE_NUM * 4) +#endif +static inline int div_r32(int64_t m, int n) +{ +/* + *return (int)(m/n) + */ +#ifndef CONFIG_ARM64 + do_div(m, n); + return (int)m; +#else + return (int)(m/n); +#endif +} + +/*USE_BUF_BLOCK*/ +struct BUF_s { + int index; + unsigned int alloc_flag; + /*buffer */ + unsigned int cma_page_count; + unsigned long alloc_addr; + unsigned long start_adr; + unsigned int size; + + unsigned int free_start_adr; +} /*BUF_t */; + +struct MVBUF_s { + unsigned long start_adr; + unsigned int size; + int used_flag; +} /*MVBUF_t */; + + /* #undef BUFMGR_ONLY to enable hardware configuration */ + +/*#define TEST_WR_PTR_INC*/ +#define WR_PTR_INC_NUM 128 + +#define SIMULATION +#define DOS_PROJECT +#undef MEMORY_MAP_IN_REAL_CHIP + +/*#undef DOS_PROJECT*/ +/*#define MEMORY_MAP_IN_REAL_CHIP*/ + +/*#define BUFFER_MGR_ONLY*/ +/*#define CONFIG_HEVC_CLK_FORCED_ON*/ +/*#define ENABLE_SWAP_TEST*/ +#define MCRCC_ENABLE + +#ifdef VP9_10B_NV21 +#define MEM_MAP_MODE 2 /* 0:linear 1:32x32 2:64x32*/ +#else +#define MEM_MAP_MODE 0 /* 0:linear 1:32x32 2:64x32*/ +#endif + +#define VP9_LPF_LVL_UPDATE +/*#define DBG_LF_PRINT*/ + +#ifdef VP9_10B_NV21 +#else +#define LOSLESS_COMPRESS_MODE +#endif + +#define DOUBLE_WRITE_YSTART_TEMP 0x02000000 +#define DOUBLE_WRITE_CSTART_TEMP 0x02900000 + + + +typedef unsigned int u32; +typedef unsigned short u16; + +#define VP9_DEBUG_BUFMGR 0x01 +#define VP9_DEBUG_BUFMGR_MORE 0x02 +#define VP9_DEBUG_BUFMGR_DETAIL 0x04 +#define VP9_DEBUG_OUT_PTS 0x10 +#define VP9_DEBUG_SEND_PARAM_WITH_REG 0x100 +#define VP9_DEBUG_MERGE 0x200 +#define VP9_DEBUG_DBG_LF_PRINT 0x400 +#define VP9_DEBUG_REG 0x800 +#define VP9_DEBUG_2_STAGE 0x1000 +#define VP9_DEBUG_2_STAGE_MORE 0x2000 +#define VP9_DEBUG_DIS_LOC_ERROR_PROC 0x10000 +#define VP9_DEBUG_DIS_SYS_ERROR_PROC 0x20000 +#define VP9_DEBUG_DUMP_PIC_LIST 0x40000 +#define VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC 0x80000 +#define VP9_DEBUG_NO_TRIGGER_FRAME 0x100000 +#define VP9_DEBUG_LOAD_UCODE_FROM_FILE 0x200000 +#define VP9_DEBUG_FORCE_SEND_AGAIN 0x400000 +#define VP9_DEBUG_DUMP_DATA 0x800000 +#define VP9_DEBUG_CACHE 0x1000000 +#define VP9_DEBUG_CACHE_HIT_RATE 0x2000000 +#define IGNORE_PARAM_FROM_CONFIG 0x8000000 +#ifdef MULTI_INSTANCE_SUPPORT +#define PRINT_FLAG_ERROR 0 +#define PRINT_FLAG_VDEC_STATUS 0x20000000 +#define PRINT_FLAG_VDEC_DETAIL 0x40000000 +#define PRINT_FLAG_VDEC_DATA 0x80000000 +#endif + +static u32 debug; +static bool is_reset; +/*for debug*/ +/* + udebug_flag: + bit 0, enable ucode print + bit 1, enable ucode detail print + bit [31:16] not 0, pos to dump lmem + bit 2, pop bits to lmem + bit [11:8], pre-pop bits for alignment (when bit 2 is 1) +*/ +static u32 udebug_flag; +/* + when udebug_flag[1:0] is not 0 + udebug_pause_pos not 0, + pause position +*/ +static u32 udebug_pause_pos; +/* + when udebug_flag[1:0] is not 0 + and udebug_pause_pos is not 0, + pause only when DEBUG_REG2 is equal to this val +*/ +static u32 udebug_pause_val; + +static u32 udebug_pause_decode_idx; + +#define DEBUG_REG +#ifdef DEBUG_REG +void WRITE_VREG_DBG2(unsigned int adr, unsigned int val) +{ + if (debug & VP9_DEBUG_REG) + pr_info("%s(%x, %x)\n", __func__, adr, val); + if (adr != 0) + WRITE_VREG(adr, val); +} + +#undef WRITE_VREG +#define WRITE_VREG WRITE_VREG_DBG2 +#endif + +#define FRAME_CNT_WINDOW_SIZE 59 +#define RATE_CORRECTION_THRESHOLD 5 +/************************************************** + +VP9 buffer management start + +***************************************************/ +#ifdef VP9_10B_MMU +#define MMU_COMPRESS_HEADER_SIZE 0x48000 +#endif + +#define INVALID_IDX -1 /* Invalid buffer index.*/ + +#define RPM_BEGIN 0x200 +#define RPM_END 0x280 + +union param_u { + struct { + unsigned short data[RPM_END - RPM_BEGIN]; + } l; + struct { + /* from ucode lmem, do not change this struct */ + unsigned short profile; + unsigned short show_existing_frame; + unsigned short frame_to_show_idx; + unsigned short frame_type; /*1 bit*/ + unsigned short show_frame; /*1 bit*/ + unsigned short error_resilient_mode; /*1 bit*/ + unsigned short intra_only; /*1 bit*/ + unsigned short display_size_present; /*1 bit*/ + unsigned short reset_frame_context; + unsigned short refresh_frame_flags; + unsigned short width; + unsigned short height; + unsigned short display_width; + unsigned short display_height; + /* + *bit[11:8] - ref_frame_info_0 (ref(3-bits), ref_frame_sign_bias(1-bit)) + *bit[7:4] - ref_frame_info_1 (ref(3-bits), ref_frame_sign_bias(1-bit)) + *bit[3:0] - ref_frame_info_2 (ref(3-bits), ref_frame_sign_bias(1-bit)) + */ + unsigned short ref_info; + /* + *bit[2]: same_frame_size0 + *bit[1]: same_frame_size1 + *bit[0]: same_frame_size2 + */ + unsigned short same_frame_size; + + unsigned short mode_ref_delta_enabled; + unsigned short ref_deltas[4]; + unsigned short mode_deltas[2]; + unsigned short filter_level; + unsigned short sharpness_level; + unsigned short bit_depth; + unsigned short seg_quant_info[8]; + unsigned short seg_enabled; + unsigned short seg_abs_delta; + /* bit 15: feature enabled; bit 8, sign; bit[5:0], data */ + unsigned short seg_lf_info[8]; + } p; +}; + + +struct vpx_codec_frame_buffer_s { + uint8_t *data; /**< Pointer to the data buffer */ + size_t size; /**< Size of data in bytes */ + void *priv; /**< Frame's private data */ +}; + +enum vpx_color_space_t { + VPX_CS_UNKNOWN = 0, /**< Unknown */ + VPX_CS_BT_601 = 1, /**< BT.601 */ + VPX_CS_BT_709 = 2, /**< BT.709 */ + VPX_CS_SMPTE_170 = 3, /**< SMPTE.170 */ + VPX_CS_SMPTE_240 = 4, /**< SMPTE.240 */ + VPX_CS_BT_2020 = 5, /**< BT.2020 */ + VPX_CS_RESERVED = 6, /**< Reserved */ + VPX_CS_SRGB = 7 /**< sRGB */ +}; /**< alias for enum vpx_color_space */ + +enum vpx_bit_depth_t { + VPX_BITS_8 = 8, /**< 8 bits */ + VPX_BITS_10 = 10, /**< 10 bits */ + VPX_BITS_12 = 12, /**< 12 bits */ +}; + +#define MAX_SLICE_NUM 1024 +struct PIC_BUFFER_CONFIG_s { + int index; + int BUF_index; + int mv_buf_index; + int comp_body_size; + int buf_size; + int vf_ref; + int y_canvas_index; + int uv_canvas_index; +#ifdef MULTI_INSTANCE_SUPPORT + struct canvas_config_s canvas_config[2]; +#endif + int decode_idx; + int slice_type; + int stream_offset; + u32 pts; + u64 pts64; + uint8_t error_mark; + /**/ + int slice_idx; + /*buffer*/ +#ifdef VP9_10B_MMU + unsigned long header_adr; +#endif + unsigned long mpred_mv_wr_start_addr; + unsigned long mc_y_adr; + unsigned long mc_u_v_adr; + unsigned int dw_y_adr; + unsigned int dw_u_v_adr; + int mc_canvas_y; + int mc_canvas_u_v; + + int lcu_total; + /**/ + int y_width; + int y_height; + int y_crop_width; + int y_crop_height; + int y_stride; + + int uv_width; + int uv_height; + int uv_crop_width; + int uv_crop_height; + int uv_stride; + + int alpha_width; + int alpha_height; + int alpha_stride; + + uint8_t *y_buffer; + uint8_t *u_buffer; + uint8_t *v_buffer; + uint8_t *alpha_buffer; + + uint8_t *buffer_alloc; + int buffer_alloc_sz; + int border; + int frame_size; + int subsampling_x; + int subsampling_y; + unsigned int bit_depth; + enum vpx_color_space_t color_space; + + int corrupted; + int flags; + unsigned long cma_alloc_addr; + + int double_write_mode; +} PIC_BUFFER_CONFIG; + +enum BITSTREAM_PROFILE { + PROFILE_0, + PROFILE_1, + PROFILE_2, + PROFILE_3, + MAX_PROFILES +}; + +enum FRAME_TYPE { + KEY_FRAME = 0, + INTER_FRAME = 1, + FRAME_TYPES, +}; + +enum REFERENCE_MODE { + SINGLE_REFERENCE = 0, + COMPOUND_REFERENCE = 1, + REFERENCE_MODE_SELECT = 2, + REFERENCE_MODES = 3, +}; + +#define NONE -1 +#define INTRA_FRAME 0 +#define LAST_FRAME 1 +#define GOLDEN_FRAME 2 +#define ALTREF_FRAME 3 +#define MAX_REF_FRAMES 4 + +#define REFS_PER_FRAME 3 + +#define REF_FRAMES_LOG2 3 +#define REF_FRAMES (1 << REF_FRAMES_LOG2) +#define REF_FRAMES_4K (6) + +/*4 scratch frames for the new frames to support a maximum of 4 cores decoding + *in parallel, 3 for scaled references on the encoder. + *TODO(hkuang): Add ondemand frame buffers instead of hardcoding the number + * // of framebuffers. + *TODO(jkoleszar): These 3 extra references could probably come from the + *normal reference pool. + */ +#define FRAME_BUFFERS (REF_FRAMES + 16) +#define HEADER_FRAME_BUFFERS (FRAME_BUFFERS) +#define MAX_BUF_NUM (FRAME_BUFFERS) +#define MV_BUFFER_NUM FRAME_BUFFERS +#ifdef SUPPORT_FB_DECODING +#define STAGE_MAX_BUFFERS 16 +#else +#define STAGE_MAX_BUFFERS 0 +#endif + +#define FRAME_CONTEXTS_LOG2 2 +#define FRAME_CONTEXTS (1 << FRAME_CONTEXTS_LOG2) +/*buffer + header buffer + workspace*/ +#ifdef MV_USE_FIXED_BUF +#define MAX_BMMU_BUFFER_NUM (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + 1) +#define VF_BUFFER_IDX(n) (n) +#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n) +#define WORK_SPACE_BUF_ID (FRAME_BUFFERS + HEADER_FRAME_BUFFERS) +#else +#define MAX_BMMU_BUFFER_NUM \ + (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM + 1) +#define VF_BUFFER_IDX(n) (n) +#define HEADER_BUFFER_IDX(n) (FRAME_BUFFERS + n) +#define MV_BUFFER_IDX(n) (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + n) +#define WORK_SPACE_BUF_ID \ + (FRAME_BUFFERS + HEADER_FRAME_BUFFERS + MV_BUFFER_NUM) +#endif + +struct RefCntBuffer_s { + int ref_count; + /*MV_REF *mvs;*/ + int mi_rows; + int mi_cols; + struct vpx_codec_frame_buffer_s raw_frame_buffer; + struct PIC_BUFFER_CONFIG_s buf; + +/*The Following variables will only be used in frame parallel decode. + * + *frame_worker_owner indicates which FrameWorker owns this buffer. NULL means + *that no FrameWorker owns, or is decoding, this buffer. + *VP9Worker *frame_worker_owner; + * + *row and col indicate which position frame has been decoded to in real + *pixel unit. They are reset to -1 when decoding begins and set to INT_MAX + *when the frame is fully decoded. + */ + int row; + int col; +} RefCntBuffer; + +struct RefBuffer_s { +/*TODO(dkovalev): idx is not really required and should be removed, now it + *is used in vp9_onyxd_if.c + */ + int idx; + struct PIC_BUFFER_CONFIG_s *buf; + /*struct scale_factors sf;*/ +} RefBuffer; + +struct InternalFrameBuffer_s { + uint8_t *data; + size_t size; + int in_use; +} InternalFrameBuffer; + +struct InternalFrameBufferList_s { + int num_internal_frame_buffers; + struct InternalFrameBuffer_s *int_fb; +} InternalFrameBufferList; + +struct BufferPool_s { +/*Protect BufferPool from being accessed by several FrameWorkers at + *the same time during frame parallel decode. + *TODO(hkuang): Try to use atomic variable instead of locking the whole pool. + * + *Private data associated with the frame buffer callbacks. + *void *cb_priv; + * + *vpx_get_frame_buffer_cb_fn_t get_fb_cb; + *vpx_release_frame_buffer_cb_fn_t release_fb_cb; + */ + + struct RefCntBuffer_s frame_bufs[FRAME_BUFFERS]; + +/*Frame buffers allocated internally by the codec.*/ + struct InternalFrameBufferList_s int_frame_buffers; + unsigned long flags; + spinlock_t lock; + +} BufferPool; + +#define lock_buffer_pool(pool, flags) \ + spin_lock_irqsave(&pool->lock, flags) + +#define unlock_buffer_pool(pool, flags) \ + spin_unlock_irqrestore(&pool->lock, flags) + +struct VP9_Common_s { + enum vpx_color_space_t color_space; + int width; + int height; + int display_width; + int display_height; + int last_width; + int last_height; + + int subsampling_x; + int subsampling_y; + + int use_highbitdepth;/*Marks if we need to use 16bit frame buffers.*/ + + struct PIC_BUFFER_CONFIG_s *frame_to_show; + struct RefCntBuffer_s *prev_frame; + + /*TODO(hkuang): Combine this with cur_buf in macroblockd.*/ + struct RefCntBuffer_s *cur_frame; + + int ref_frame_map[REF_FRAMES]; /* maps fb_idx to reference slot */ + + /*Prepare ref_frame_map for the next frame. + *Only used in frame parallel decode. + */ + int next_ref_frame_map[REF_FRAMES]; + + /* TODO(jkoleszar): could expand active_ref_idx to 4, + *with 0 as intra, and roll new_fb_idx into it. + */ + + /*Each frame can reference REFS_PER_FRAME buffers*/ + struct RefBuffer_s frame_refs[REFS_PER_FRAME]; + + int prev_fb_idx; + int new_fb_idx; +#ifdef VP9_10B_MMU + int cur_fb_idx_mmu; +#endif + /*last frame's frame type for motion search*/ + enum FRAME_TYPE last_frame_type; + enum FRAME_TYPE frame_type; + + int show_frame; + int last_show_frame; + int show_existing_frame; + + /*Flag signaling that the frame is encoded using only INTRA modes.*/ + uint8_t intra_only; + uint8_t last_intra_only; + + int allow_high_precision_mv; + + /*Flag signaling that the frame context should be reset to default + *values. 0 or 1 implies don't reset, 2 reset just the context + *specified in the frame header, 3 reset all contexts. + */ + int reset_frame_context; + + /*MBs, mb_rows/cols is in 16-pixel units; mi_rows/cols is in + * MODE_INFO (8-pixel) units. + */ + int MBs; + int mb_rows, mi_rows; + int mb_cols, mi_cols; + int mi_stride; + + /*Whether to use previous frame's motion vectors for prediction.*/ + int use_prev_frame_mvs; + + int refresh_frame_context; /* Two state 0 = NO, 1 = YES */ + + int ref_frame_sign_bias[MAX_REF_FRAMES]; /* Two state 0, 1 */ + + /*struct loopfilter lf;*/ + /*struct segmentation seg;*/ + + /*TODO(hkuang):Remove this as it is the same as frame_parallel_decode*/ + /* in pbi.*/ + int frame_parallel_decode; /* frame-based threading.*/ + + /*Context probabilities for reference frame prediction*/ + /*MV_REFERENCE_FRAME comp_fixed_ref;*/ + /*MV_REFERENCE_FRAME comp_var_ref[2];*/ + enum REFERENCE_MODE reference_mode; + + /*FRAME_CONTEXT *fc; */ /* this frame entropy */ + /*FRAME_CONTEXT *frame_contexts; */ /*FRAME_CONTEXTS*/ + /*unsigned int frame_context_idx; *//* Context to use/update */ + /*FRAME_COUNTS counts;*/ + + unsigned int current_video_frame; + enum BITSTREAM_PROFILE profile; + + enum vpx_bit_depth_t bit_depth; + + int error_resilient_mode; + int frame_parallel_decoding_mode; + + int byte_alignment; + int skip_loop_filter; + + /*External BufferPool passed from outside.*/ + struct BufferPool_s *buffer_pool; + + int above_context_alloc_cols; + +} VP9_COMMON; + +static void set_canvas(struct VP9Decoder_s *pbi, + struct PIC_BUFFER_CONFIG_s *pic_config); +static int prepare_display_buf(struct VP9Decoder_s *pbi, + struct PIC_BUFFER_CONFIG_s *pic_config); + +static struct PIC_BUFFER_CONFIG_s *get_frame_new_buffer(struct VP9_Common_s *cm) +{ + return &cm->buffer_pool->frame_bufs[cm->new_fb_idx].buf; +} + +static void ref_cnt_fb(struct RefCntBuffer_s *bufs, int *idx, int new_idx) +{ + const int ref_index = *idx; + + if (ref_index >= 0 && bufs[ref_index].ref_count > 0) { + bufs[ref_index].ref_count--; + /*pr_info("[MMU DEBUG 2] dec ref_count[%d] : %d\r\n", + * ref_index, bufs[ref_index].ref_count); + */ + } + + *idx = new_idx; + + bufs[new_idx].ref_count++; + /*pr_info("[MMU DEBUG 3] inc ref_count[%d] : %d\r\n", + * new_idx, bufs[new_idx].ref_count); + */ +} + +int vp9_release_frame_buffer(struct vpx_codec_frame_buffer_s *fb) +{ + struct InternalFrameBuffer_s *const int_fb = + (struct InternalFrameBuffer_s *)fb->priv; + if (int_fb) + int_fb->in_use = 0; + return 0; +} + +static int compute_losless_comp_body_size(int width, int height, + uint8_t is_bit_depth_10); + +static void setup_display_size(struct VP9_Common_s *cm, union param_u *params, + int print_header_info) +{ + cm->display_width = cm->width; + cm->display_height = cm->height; + if (params->p.display_size_present) { + if (print_header_info) + pr_info(" * 1-bit display_size_present read : 1\n"); + cm->display_width = params->p.display_width; + cm->display_height = params->p.display_height; + /*vp9_read_frame_size(rb, &cm->display_width, + * &cm->display_height); + */ + } else { + if (print_header_info) + pr_info(" * 1-bit display_size_present read : 0\n"); + } +} + + +uint8_t print_header_info = 0; + +struct buff_s { + u32 buf_start; + u32 buf_size; + u32 buf_end; +} buff_t; + +struct BuffInfo_s { + u32 max_width; + u32 max_height; + u32 start_adr; + u32 end_adr; + struct buff_s ipp; + struct buff_s sao_abv; + struct buff_s sao_vb; + struct buff_s short_term_rps; + struct buff_s vps; + struct buff_s sps; + struct buff_s pps; + struct buff_s sao_up; + struct buff_s swap_buf; + struct buff_s swap_buf2; + struct buff_s scalelut; + struct buff_s dblk_para; + struct buff_s dblk_data; + struct buff_s seg_map; +#ifdef VP9_10B_MMU + struct buff_s mmu_vbh; + struct buff_s cm_header; +#endif + struct buff_s mpred_above; +#ifdef MV_USE_FIXED_BUF + struct buff_s mpred_mv; +#endif + struct buff_s rpm; + struct buff_s lmem; +} BuffInfo_t; + +#ifdef MULTI_INSTANCE_SUPPORT +#define DEC_RESULT_NONE 0 +#define DEC_RESULT_DONE 1 +#define DEC_RESULT_AGAIN 2 +#define DEC_RESULT_CONFIG_PARAM 3 +#define DEC_RESULT_ERROR 4 +#define DEC_INIT_PICLIST 5 +#define DEC_UNINIT_PICLIST 6 +#define DEC_RESULT_GET_DATA 7 +#define DEC_RESULT_GET_DATA_RETRY 8 +#define DEC_RESULT_EOS 9 +#define DEC_RESULT_FORCE_EXIT 10 + +#define DEC_S1_RESULT_NONE 0 +#define DEC_S1_RESULT_DONE 1 +#define DEC_S1_RESULT_FORCE_EXIT 2 +#define DEC_S1_RESULT_TEST_TRIGGER_DONE 0xf0 + +#ifdef FB_DECODING_TEST_SCHEDULE +#define TEST_SET_NONE 0 +#define TEST_SET_PIC_DONE 1 +#define TEST_SET_S2_DONE 2 +#endif + +static void vp9_work(struct work_struct *work); +#endif +struct loop_filter_info_n; +struct loopfilter; +struct segmentation; + +#ifdef SUPPORT_FB_DECODING +static void mpred_process(struct VP9Decoder_s *pbi); +static void vp9_s1_work(struct work_struct *work); + +struct stage_buf_s { + int index; + unsigned short rpm[RPM_END - RPM_BEGIN]; +}; + +static unsigned int not_run2_ready[MAX_DECODE_INSTANCE_NUM]; + +static unsigned int run2_count[MAX_DECODE_INSTANCE_NUM]; + +#ifdef FB_DECODING_TEST_SCHEDULE +u32 stage_buf_num; /* = 16;*/ +#else +u32 stage_buf_num; +#endif +#endif + +struct VP9Decoder_s { +#ifdef MULTI_INSTANCE_SUPPORT + unsigned char index; + + struct device *cma_dev; + struct platform_device *platform_dev; + void (*vdec_cb)(struct vdec_s *, void *); + void *vdec_cb_arg; + struct vframe_chunk_s *chunk; + int dec_result; + struct work_struct work; + struct work_struct set_clk_work; + u32 start_shift_bytes; + + struct BuffInfo_s work_space_buf_store; + unsigned long buf_start; + u32 buf_size; + u32 cma_alloc_count; + unsigned long cma_alloc_addr; + uint8_t eos; + unsigned long int start_process_time; + unsigned last_lcu_idx; + int decode_timeout_count; + unsigned timeout_num; + + int double_write_mode; +#endif +#ifdef VP9_10B_MMU + long used_4k_num; +#endif + unsigned char m_ins_flag; + char *provider_name; + union param_u param; + int frame_count; + int pic_count; + u32 stat; + struct timer_list timer; + u32 frame_dur; + u32 frame_ar; + int fatal_error; + uint8_t init_flag; + uint8_t process_busy; +#define PROC_STATE_INIT 0 +#define PROC_STATE_DECODESLICE 1 +#define PROC_STATE_SENDAGAIN 2 + uint8_t process_state; + u32 ucode_pause_pos; + + int show_frame_num; +#ifndef VP9_10B_MMU + struct buff_s mc_buf_spec; +#endif + struct dec_sysinfo vvp9_amstream_dec_info; + void *rpm_addr; + void *lmem_addr; + dma_addr_t rpm_phy_addr; + dma_addr_t lmem_phy_addr; + unsigned short *lmem_ptr; + unsigned short *debug_ptr; + + void *prob_buffer_addr; + void *count_buffer_addr; + dma_addr_t prob_buffer_phy_addr; + dma_addr_t count_buffer_phy_addr; + +#if 1 + /*VP9_10B_MMU*/ + void *frame_mmu_map_addr; + dma_addr_t frame_mmu_map_phy_addr; +#endif + unsigned int use_cma_flag; + + struct BUF_s m_BUF[MAX_BUF_NUM]; + struct MVBUF_s m_mv_BUF[MV_BUFFER_NUM]; + u32 used_buf_num; + DECLARE_KFIFO(newframe_q, struct vframe_s *, VF_POOL_SIZE); + DECLARE_KFIFO(display_q, struct vframe_s *, VF_POOL_SIZE); + DECLARE_KFIFO(pending_q, struct vframe_s *, VF_POOL_SIZE); + struct vframe_s vfpool[VF_POOL_SIZE]; + u32 vf_pre_count; + u32 vf_get_count; + u32 vf_put_count; + int buf_num; + int pic_num; + int lcu_size_log2; + unsigned int losless_comp_body_size; + + u32 video_signal_type; + + int pts_mode; + int last_lookup_pts; + int last_pts; + u64 last_lookup_pts_us64; + u64 last_pts_us64; + u64 shift_byte_count; + + u32 pts_unstable; + u32 frame_cnt_window; + u32 pts1, pts2; + u32 last_duration; + u32 duration_from_pts_done; + bool vp9_first_pts_ready; + + u32 shift_byte_count_lo; + u32 shift_byte_count_hi; + int pts_mode_switching_count; + int pts_mode_recovery_count; + + bool get_frame_dur; + u32 saved_resolution; + + /**/ + struct VP9_Common_s common; + struct RefCntBuffer_s *cur_buf; + int refresh_frame_flags; + uint8_t need_resync; + uint8_t hold_ref_buf; + uint8_t ready_for_new_data; + struct BufferPool_s vp9_buffer_pool; + struct BuffInfo_s *work_space_buf; +#ifndef VP9_10B_MMU + struct buff_s *mc_buf; +#endif + unsigned int frame_width; + unsigned int frame_height; + + unsigned short *rpm_ptr; + int init_pic_w; + int init_pic_h; + int lcu_total; + int lcu_size; + + int slice_type; + + int skip_flag; + int decode_idx; + int slice_idx; + uint8_t has_keyframe; + uint8_t wait_buf; + uint8_t error_flag; + + /* bit 0, for decoding; bit 1, for displaying */ + uint8_t ignore_bufmgr_error; + int PB_skip_mode; + int PB_skip_count_after_decoding; + /*hw*/ + + /*lf*/ + int default_filt_lvl; + struct loop_filter_info_n *lfi; + struct loopfilter *lf; + struct segmentation *seg_4lf; + /**/ + struct vdec_info *gvs; + + u32 pre_stream_offset; + + unsigned int dec_status; + u32 last_put_idx; + int new_frame_displayed; + void *mmu_box; + void *bmmu_box; + struct vframe_master_display_colour_s vf_dp; + struct firmware_s *fw; + int max_pic_w; + int max_pic_h; +#ifdef SUPPORT_FB_DECODING + int dec_s1_result; + int s1_test_cmd; + struct work_struct s1_work; + int used_stage_buf_num; + int s1_pos; + int s2_pos; + void *stage_mmu_map_addr; + dma_addr_t stage_mmu_map_phy_addr; + struct stage_buf_s *s1_buf; + struct stage_buf_s *s2_buf; + struct stage_buf_s *stage_bufs + [STAGE_MAX_BUFFERS]; + unsigned char run2_busy; + + int s1_mv_buf_index; + int s1_mv_buf_index_pre; + int s1_mv_buf_index_pre_pre; + unsigned long s1_mpred_mv_wr_start_addr; + unsigned long s1_mpred_mv_wr_start_addr_pre; + unsigned short s1_intra_only; + unsigned short s1_frame_type; + unsigned short s1_width; + unsigned short s1_height; + unsigned short s1_last_show_frame; + union param_u s1_param; + u8 back_not_run_ready; +#endif +} ; + +static void resize_context_buffers(struct VP9Decoder_s *pbi, + struct VP9_Common_s *cm, int width, int height) +{ + if (cm->width != width || cm->height != height) { + /* to do ..*/ + if (pbi != NULL) { + pbi->vp9_first_pts_ready = 0; + pbi->duration_from_pts_done = 0; + } + cm->width = width; + cm->height = height; + pr_info("%s (%d,%d)=>(%d,%d)\r\n", __func__, cm->width, + cm->height, width, height); + } + /* + *if (cm->cur_frame->mvs == NULL || + * cm->mi_rows > cm->cur_frame->mi_rows || + * cm->mi_cols > cm->cur_frame->mi_cols) { + * resize_mv_buffer(cm); + *} + */ +} + +static int valid_ref_frame_size(int ref_width, int ref_height, + int this_width, int this_height) { + return 2 * this_width >= ref_width && + 2 * this_height >= ref_height && + this_width <= 16 * ref_width && + this_height <= 16 * ref_height; +} + +/* + *static int valid_ref_frame_img_fmt(enum vpx_bit_depth_t ref_bit_depth, + * int ref_xss, int ref_yss, + * enum vpx_bit_depth_t this_bit_depth, + * int this_xss, int this_yss) { + * return ref_bit_depth == this_bit_depth && ref_xss == this_xss && + * ref_yss == this_yss; + *} + */ + + +static int setup_frame_size( + struct VP9Decoder_s *pbi, + struct VP9_Common_s *cm, union param_u *params, + unsigned int *mmu_index_adr, + int print_header_info) { + int width, height; + struct BufferPool_s * const pool = cm->buffer_pool; + struct PIC_BUFFER_CONFIG_s *ybf; + int ret = 0; + + width = params->p.width; + height = params->p.height; + /*vp9_read_frame_size(rb, &width, &height);*/ + if (print_header_info) + pr_info(" * 16-bits w read : %d (width : %d)\n", width, height); + if (print_header_info) + pr_info + (" * 16-bits h read : %d (height : %d)\n", width, height); + + WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width); + +#ifdef VP9_10B_MMU + /* if(cm->prev_fb_idx >= 0) release_unused_4k(cm->prev_fb_idx);*/ + /* cm->prev_fb_idx = cm->new_fb_idx;*/ + /*pr_info + ("[DEBUG DEBUG]Before alloc_mmu, prev_fb_idx : %d, new_fb_idx : %d\r\n", + cm->prev_fb_idx, cm->new_fb_idx);*/ + ret = vp9_alloc_mmu(pbi, + cm->new_fb_idx, + params->p.width, + params->p.height, + params->p.bit_depth, + mmu_index_adr); + if (ret != 0) { + pr_err("can't alloc need mmu1,idx %d ret =%d\n", + cm->new_fb_idx, + ret); + return ret; + } + cm->cur_fb_idx_mmu = cm->new_fb_idx; +#endif + + resize_context_buffers(pbi, cm, width, height); + setup_display_size(cm, params, print_header_info); +#if 0 + lock_buffer_pool(pool); + if (vp9_realloc_frame_buffer( + get_frame_new_buffer(cm), cm->width, cm->height, + cm->subsampling_x, cm->subsampling_y, +#if CONFIG_VP9_HIGHBITDEPTH + cm->use_highbitdepth, +#endif + VP9_DEC_BORDER_IN_PIXELS, + cm->byte_alignment, + &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer, + pool->get_fb_cb, pool->cb_priv)) { + unlock_buffer_pool(pool); + vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR, + "Failed to allocate frame buffer"); + } + unlock_buffer_pool(pool); +#else + /* porting */ + ybf = get_frame_new_buffer(cm); + ybf->y_crop_width = width; + ybf->y_crop_height = height; + ybf->bit_depth = params->p.bit_depth; +#endif + pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x; + pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y; + pool->frame_bufs[cm->new_fb_idx].buf.bit_depth = + (unsigned int)cm->bit_depth; + pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space; + return ret; +} + +static int setup_frame_size_with_refs( + struct VP9Decoder_s *pbi, + struct VP9_Common_s *cm, + union param_u *params, + unsigned int *mmu_index_adr, + int print_header_info) { + + int width, height; + int found = 0, i; + int has_valid_ref_frame = 0; + struct PIC_BUFFER_CONFIG_s *ybf; + struct BufferPool_s * const pool = cm->buffer_pool; + int ret = 0; + + for (i = 0; i < REFS_PER_FRAME; ++i) { + if ((params->p.same_frame_size >> + (REFS_PER_FRAME - i - 1)) & 0x1) { + struct PIC_BUFFER_CONFIG_s *const buf = + cm->frame_refs[i].buf; + /*if (print_header_info) + * pr_info + * ("1-bit same_frame_size[%d] read : 1\n", i); + */ + width = buf->y_crop_width; + height = buf->y_crop_height; + /*if (print_header_info) + * pr_info + * (" - same_frame_size width : %d\n", width); + */ + /*if (print_header_info) + * pr_info + * (" - same_frame_size height : %d\n", height); + */ + found = 1; + break; + } else { + /*if (print_header_info) + * pr_info + * ("1-bit same_frame_size[%d] read : 0\n", i); + */ + } + } + + if (!found) { + /*vp9_read_frame_size(rb, &width, &height);*/ + width = params->p.width; + height = params->p.height; + /*if (print_header_info) + * pr_info + * (" * 16-bits w read : %d (width : %d)\n", + * width, height); + *if (print_header_info) + * pr_info + * (" * 16-bits h read : %d (height : %d)\n", + * width, height); + */ + } + + if (width <= 0 || height <= 0) { + pr_err("Error: Invalid frame size\r\n"); + return -1; + } + + params->p.width = width; + params->p.height = height; + + WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width); +#ifdef VP9_10B_MMU + /*if(cm->prev_fb_idx >= 0) release_unused_4k(cm->prev_fb_idx); + cm->prev_fb_idx = cm->new_fb_idx;*/ +/* pr_info + ("[DEBUG DEBUG]Before alloc_mmu, prev_fb_idx : %d, new_fb_idx : %d\r\n", + cm->prev_fb_idx, cm->new_fb_idx);*/ + ret = vp9_alloc_mmu(pbi, cm->new_fb_idx, + params->p.width, params->p.height, + params->p.bit_depth, mmu_index_adr); + if (ret != 0) { + pr_err("can't alloc need mmu,idx %d\r\n", + cm->new_fb_idx); + return ret; + } + cm->cur_fb_idx_mmu = cm->new_fb_idx; +#endif + + /*Check to make sure at least one of frames that this frame references + *has valid dimensions. + */ + for (i = 0; i < REFS_PER_FRAME; ++i) { + struct RefBuffer_s * const ref_frame = &cm->frame_refs[i]; + + has_valid_ref_frame |= + valid_ref_frame_size(ref_frame->buf->y_crop_width, + ref_frame->buf->y_crop_height, + width, height); + } + if (!has_valid_ref_frame) { + pr_err("Error: Referenced frame has invalid size\r\n"); + return -1; + } +#if 0 + for (i = 0; i < REFS_PER_FRAME; ++i) { + struct RefBuffer_s * const ref_frame = + &cm->frame_refs[i]; + if (!valid_ref_frame_img_fmt( + ref_frame->buf->bit_depth, + ref_frame->buf->subsampling_x, + ref_frame->buf->subsampling_y, + cm->bit_depth, + cm->subsampling_x, + cm->subsampling_y)) + pr_err + ("Referenced frame incompatible color fmt\r\n"); + return -1; + } +#endif + resize_context_buffers(pbi, cm, width, height); + setup_display_size(cm, params, print_header_info); + +#if 0 + lock_buffer_pool(pool); + if (vp9_realloc_frame_buffer( + get_frame_new_buffer(cm), cm->width, cm->height, + cm->subsampling_x, cm->subsampling_y, +#if CONFIG_VP9_HIGHBITDEPTH + cm->use_highbitdepth, +#endif + VP9_DEC_BORDER_IN_PIXELS, + cm->byte_alignment, + &pool->frame_bufs[cm->new_fb_idx].raw_frame_buffer, + pool->get_fb_cb, + pool->cb_priv)) { + unlock_buffer_pool(pool); + vpx_internal_error(&cm->error, VPX_CODEC_MEM_ERROR, + "Failed to allocate frame buffer"); + } + unlock_buffer_pool(pool); +#else + /* porting */ + ybf = get_frame_new_buffer(cm); + ybf->y_crop_width = width; + ybf->y_crop_height = height; + ybf->bit_depth = params->p.bit_depth; +#endif + pool->frame_bufs[cm->new_fb_idx].buf.subsampling_x = cm->subsampling_x; + pool->frame_bufs[cm->new_fb_idx].buf.subsampling_y = cm->subsampling_y; + pool->frame_bufs[cm->new_fb_idx].buf.bit_depth = + (unsigned int)cm->bit_depth; + pool->frame_bufs[cm->new_fb_idx].buf.color_space = cm->color_space; + return ret; +} + + + + + +static int vp9_print(struct VP9Decoder_s *pbi, + int flag, const char *fmt, ...) +{ +#define HEVC_PRINT_BUF 256 + unsigned char buf[HEVC_PRINT_BUF]; + int len = 0; + + if (pbi == NULL || + (flag == 0) || + (debug & flag)) { + va_list args; + + va_start(args, fmt); + if (pbi) + len = sprintf(buf, "[%d]", pbi->index); + vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args); + pr_debug("%s", buf); + va_end(args); + } + return 0; +} + +static inline bool close_to(int a, int b, int m) +{ + return (abs(a - b) < m) ? true : false; +} + +#ifdef MULTI_INSTANCE_SUPPORT +static int vp9_print_cont(struct VP9Decoder_s *pbi, + int flag, const char *fmt, ...) +{ + unsigned char buf[HEVC_PRINT_BUF]; + int len = 0; + + if (pbi == NULL || + (flag == 0) || + (debug & flag)) { + va_list args; + + va_start(args, fmt); + vsnprintf(buf + len, HEVC_PRINT_BUF - len, fmt, args); + pr_debug("%s", buf); + va_end(args); + } + return 0; +} + +static void trigger_schedule(struct VP9Decoder_s *pbi) +{ + if (pbi->vdec_cb) + pbi->vdec_cb(hw_to_vdec(pbi), pbi->vdec_cb_arg); +} + +static void reset_process_time(struct VP9Decoder_s *pbi) +{ + if (pbi->start_process_time) { + unsigned process_time = + 1000 * (jiffies - pbi->start_process_time) / HZ; + pbi->start_process_time = 0; + if (process_time > max_process_time[pbi->index]) + max_process_time[pbi->index] = process_time; + } +} + +static void start_process_time(struct VP9Decoder_s *pbi) +{ + pbi->start_process_time = jiffies; + pbi->decode_timeout_count = 0; + pbi->last_lcu_idx = 0; +} + +static void timeout_process(struct VP9Decoder_s *pbi) +{ + pbi->timeout_num++; + amhevc_stop(); + vp9_print(pbi, + 0, "%s decoder timeout\n", __func__); + + pbi->dec_result = DEC_RESULT_DONE; + reset_process_time(pbi); + vdec_schedule_work(&pbi->work); +} + +static u32 get_valid_double_write_mode(struct VP9Decoder_s *pbi) +{ + return (pbi->m_ins_flag && + ((double_write_mode & 0x80000000) == 0)) ? + pbi->double_write_mode : + (double_write_mode & 0x7fffffff); +} + +static int get_double_write_mode(struct VP9Decoder_s *pbi) +{ + u32 valid_dw_mode = get_valid_double_write_mode(pbi); + u32 dw; + if (valid_dw_mode == 0x100) { + struct VP9_Common_s *cm = &pbi->common; + struct PIC_BUFFER_CONFIG_s *cur_pic_config; + int w, h; + + if (!cm->cur_frame) + return 1;/*no valid frame,*/ + cur_pic_config = &cm->cur_frame->buf; + w = cur_pic_config->y_crop_width; + h = cur_pic_config->y_crop_width; + if (w > 1920 && h > 1088) + dw = 0x4; /*1:2*/ + else + dw = 0x1; /*1:1*/ + + return dw; + } + + return valid_dw_mode; +} + +/* for double write buf alloc */ +static int get_double_write_mode_init(struct VP9Decoder_s *pbi) +{ + u32 valid_dw_mode = get_valid_double_write_mode(pbi); + if (valid_dw_mode == 0x100) { + u32 dw; + int w = pbi->init_pic_w; + int h = pbi->init_pic_h; + if (w > 1920 && h > 1088) + dw = 0x4; /*1:2*/ + else + dw = 0x1; /*1:1*/ + + return dw; + } + return valid_dw_mode; +} +#endif + +static int get_double_write_ratio(struct VP9Decoder_s *pbi, + int dw_mode) +{ + int ratio = 1; + if ((dw_mode == 2) || + (dw_mode == 3)) + ratio = 4; + else if (dw_mode == 4) + ratio = 2; + return ratio; +} + +#define MAX_4K_NUM 0x1200 +#ifdef VP9_10B_MMU +int vp9_alloc_mmu( + struct VP9Decoder_s *pbi, + int cur_buf_idx, + int pic_width, + int pic_height, + unsigned short bit_depth, + unsigned int *mmu_index_adr) +{ + int bit_depth_10 = (bit_depth == VPX_BITS_10); + int picture_size; + int cur_mmu_4k_number; + if (!pbi->mmu_box) { + pr_err("error no mmu box!\n"); + return -1; + } + if (bit_depth >= VPX_BITS_12) { + pbi->fatal_error = DECODER_FATAL_ERROR_SIZE_OVERFLOW; + pr_err("fatal_error, un support bit depth 12!\n\n"); + return -1; + } + picture_size = compute_losless_comp_body_size(pic_width, pic_height, + bit_depth_10); + cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12); + if (cur_mmu_4k_number > MAX_4K_NUM) { + pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n", + cur_mmu_4k_number, pic_width, pic_height); + return -1; + } + return decoder_mmu_box_alloc_idx( + pbi->mmu_box, + cur_buf_idx, + cur_mmu_4k_number, + mmu_index_adr); +} +#endif + +#ifndef MV_USE_FIXED_BUF +static void dealloc_mv_bufs(struct VP9Decoder_s *pbi) +{ + int i; + for (i = 0; i < MV_BUFFER_NUM; i++) { + if (pbi->m_mv_BUF[i].start_adr) { + if (debug) + pr_info( + "dealloc mv buf(%d) adr %ld size 0x%x used_flag %d\n", + i, pbi->m_mv_BUF[i].start_adr, + pbi->m_mv_BUF[i].size, + pbi->m_mv_BUF[i].used_flag); + decoder_bmmu_box_free_idx( + pbi->bmmu_box, + MV_BUFFER_IDX(i)); + pbi->m_mv_BUF[i].start_adr = 0; + pbi->m_mv_BUF[i].size = 0; + pbi->m_mv_BUF[i].used_flag = 0; + } + } +} + +static int alloc_mv_buf(struct VP9Decoder_s *pbi, + int i, int size) +{ + int ret = 0; + if (decoder_bmmu_box_alloc_buf_phy + (pbi->bmmu_box, + MV_BUFFER_IDX(i), size, + DRIVER_NAME, + &pbi->m_mv_BUF[i].start_adr) < 0) { + pbi->m_mv_BUF[i].start_adr = 0; + ret = -1; + } else { + pbi->m_mv_BUF[i].size = size; + pbi->m_mv_BUF[i].used_flag = 0; + ret = 0; + if (debug) { + pr_info( + "MV Buffer %d: start_adr %p size %x\n", + i, + (void *)pbi->m_mv_BUF[i].start_adr, + pbi->m_mv_BUF[i].size); + } + } + return ret; +} + +static int init_mv_buf_list(struct VP9Decoder_s *pbi) +{ + int i; + int ret = 0; + int count = MV_BUFFER_NUM; + int pic_width = pbi->init_pic_w; + int pic_height = pbi->init_pic_h; + int lcu_size = 64; /*fixed 64*/ + int pic_width_64 = (pic_width + 63) & (~0x3f); + int pic_height_32 = (pic_height + 31) & (~0x1f); + int pic_width_lcu = (pic_width_64 % lcu_size) ? + pic_width_64 / lcu_size + 1 + : pic_width_64 / lcu_size; + int pic_height_lcu = (pic_height_32 % lcu_size) ? + pic_height_32 / lcu_size + 1 + : pic_height_32 / lcu_size; + int lcu_total = pic_width_lcu * pic_height_lcu; + int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) & + (~0xffff); + if (mv_buf_margin > 0) + count = REF_FRAMES + mv_buf_margin; + + if (pbi->init_pic_w > 2048 && pbi->init_pic_h > 1088) + count = REF_FRAMES_4K + mv_buf_margin; + + if (debug) { + pr_info("%s w:%d, h:%d, count: %d\n", + __func__, pbi->init_pic_w, pbi->init_pic_h, count); + } + + for (i = 0; + i < count && i < MV_BUFFER_NUM; i++) { + if (alloc_mv_buf(pbi, i, size) < 0) { + ret = -1; + break; + } + } + return ret; +} + +static int get_mv_buf(struct VP9Decoder_s *pbi, + int *mv_buf_index, + unsigned long *mpred_mv_wr_start_addr) +{ + int i; + int ret = -1; + for (i = 0; i < MV_BUFFER_NUM; i++) { + if (pbi->m_mv_BUF[i].start_adr && + pbi->m_mv_BUF[i].used_flag == 0) { + pbi->m_mv_BUF[i].used_flag = 1; + ret = i; + break; + } + } + + if (ret >= 0) { + *mv_buf_index = ret; + *mpred_mv_wr_start_addr = + (pbi->m_mv_BUF[ret].start_adr + 0xffff) & + (~0xffff); + if (debug & VP9_DEBUG_BUFMGR_MORE) + pr_info( + "%s => %d (%ld) size 0x%x\n", + __func__, ret, + *mpred_mv_wr_start_addr, + pbi->m_mv_BUF[ret].size); + } else { + pr_info( + "%s: Error, mv buf is not enough\n", + __func__); + } + return ret; +} + +static void put_mv_buf(struct VP9Decoder_s *pbi, + int *mv_buf_index) +{ + int i = *mv_buf_index; + if (i >= MV_BUFFER_NUM) { + if (debug & VP9_DEBUG_BUFMGR_MORE) + pr_info( + "%s: index %d beyond range\n", + __func__, i); + return; + } + if (debug & VP9_DEBUG_BUFMGR_MORE) + pr_info( + "%s(%d): used_flag(%d)\n", + __func__, i, + pbi->m_mv_BUF[i].used_flag); + + *mv_buf_index = -1; + if (pbi->m_mv_BUF[i].start_adr && + pbi->m_mv_BUF[i].used_flag) + pbi->m_mv_BUF[i].used_flag = 0; +} + +static void put_un_used_mv_bufs(struct VP9Decoder_s *pbi) +{ + struct VP9_Common_s *const cm = &pbi->common; + struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs; + int i; + for (i = 0; i < pbi->used_buf_num; ++i) { + if ((frame_bufs[i].ref_count == 0) && + (frame_bufs[i].buf.index != -1) && + (frame_bufs[i].buf.mv_buf_index >= 0) + ) + put_mv_buf(pbi, &frame_bufs[i].buf.mv_buf_index); + } +} + +#ifdef SUPPORT_FB_DECODING +static bool mv_buf_available(struct VP9Decoder_s *pbi) +{ + int i; + bool ret = 0; + for (i = 0; i < MV_BUFFER_NUM; i++) { + if (pbi->m_mv_BUF[i].start_adr && + pbi->m_mv_BUF[i].used_flag == 0) { + ret = 1; + break; + } + } + return ret; +} +#endif +#endif + +#ifdef SUPPORT_FB_DECODING +static void init_stage_buf(struct VP9Decoder_s *pbi) +{ + uint i; + for (i = 0; i < STAGE_MAX_BUFFERS + && i < stage_buf_num; i++) { + pbi->stage_bufs[i] = + vmalloc(sizeof(struct stage_buf_s)); + if (pbi->stage_bufs[i] == NULL) { + vp9_print(pbi, + 0, "%s vmalloc fail\n", __func__); + break; + } + pbi->stage_bufs[i]->index = i; + } + pbi->used_stage_buf_num = i; + pbi->s1_pos = 0; + pbi->s2_pos = 0; + pbi->s1_buf = NULL; + pbi->s2_buf = NULL; + pbi->s1_mv_buf_index = FRAME_BUFFERS; + pbi->s1_mv_buf_index_pre = FRAME_BUFFERS; + pbi->s1_mv_buf_index_pre_pre = FRAME_BUFFERS; + + if (pbi->used_stage_buf_num > 0) + vp9_print(pbi, + 0, "%s 2 stage decoding buf %d\n", + __func__, + pbi->used_stage_buf_num); +} + +static void uninit_stage_buf(struct VP9Decoder_s *pbi) +{ + int i; + for (i = 0; i < pbi->used_stage_buf_num; i++) { + if (pbi->stage_bufs[i]) + vfree(pbi->stage_bufs[i]); + pbi->stage_bufs[i] = NULL; + } + pbi->used_stage_buf_num = 0; + pbi->s1_pos = 0; + pbi->s2_pos = 0; + pbi->s1_buf = NULL; + pbi->s2_buf = NULL; +} + +static int get_s1_buf( + struct VP9Decoder_s *pbi) +{ + struct stage_buf_s *buf = NULL; + int ret = -1; + int buf_page_num = MAX_STAGE_PAGE_NUM; + int next_s1_pos = pbi->s1_pos + 1; + + if (next_s1_pos >= pbi->used_stage_buf_num) + next_s1_pos = 0; + if (next_s1_pos == pbi->s2_pos) { + pbi->s1_buf = NULL; + return ret; + } + + buf = pbi->stage_bufs[pbi->s1_pos]; + ret = decoder_mmu_box_alloc_idx( + pbi->mmu_box, + buf->index, + buf_page_num, + pbi->stage_mmu_map_addr); + if (ret < 0) { + vp9_print(pbi, 0, + "%s decoder_mmu_box_alloc fail for index %d (s1_pos %d s2_pos %d)\n", + __func__, buf->index, + pbi->s1_pos, pbi->s2_pos); + buf = NULL; + } else { + vp9_print(pbi, VP9_DEBUG_2_STAGE, + "%s decoder_mmu_box_alloc %d page for index %d (s1_pos %d s2_pos %d)\n", + __func__, buf_page_num, buf->index, + pbi->s1_pos, pbi->s2_pos); + } + pbi->s1_buf = buf; + return ret; +} + +static void inc_s1_pos(struct VP9Decoder_s *pbi) +{ + struct stage_buf_s *buf = + pbi->stage_bufs[pbi->s1_pos]; + + int used_page_num = +#ifdef FB_DECODING_TEST_SCHEDULE + MAX_STAGE_PAGE_NUM/2; +#else + (READ_VREG(HEVC_ASSIST_HED_FB_W_CTL) >> 16); +#endif + decoder_mmu_box_free_idx_tail(pbi->mmu_box, + FRAME_BUFFERS + buf->index, used_page_num); + + pbi->s1_pos++; + if (pbi->s1_pos >= pbi->used_stage_buf_num) + pbi->s1_pos = 0; + + vp9_print(pbi, VP9_DEBUG_2_STAGE, + "%s (used_page_num %d) for index %d (s1_pos %d s2_pos %d)\n", + __func__, used_page_num, buf->index, + pbi->s1_pos, pbi->s2_pos); +} + +#define s2_buf_available(pbi) (pbi->s1_pos != pbi->s2_pos) + +static int get_s2_buf( + struct VP9Decoder_s *pbi) +{ + int ret = -1; + struct stage_buf_s *buf = NULL; + if (s2_buf_available(pbi)) { + buf = pbi->stage_bufs[pbi->s2_pos]; + vp9_print(pbi, VP9_DEBUG_2_STAGE, + "%s for index %d (s1_pos %d s2_pos %d)\n", + __func__, buf->index, + pbi->s1_pos, pbi->s2_pos); + pbi->s2_buf = buf; + ret = 0; + } + return ret; +} + +static void inc_s2_pos(struct VP9Decoder_s *pbi) +{ + struct stage_buf_s *buf = + pbi->stage_bufs[pbi->s2_pos]; + decoder_mmu_box_free_idx(pbi->mmu_box, + FRAME_BUFFERS + buf->index); + pbi->s2_pos++; + if (pbi->s2_pos >= pbi->used_stage_buf_num) + pbi->s2_pos = 0; + vp9_print(pbi, VP9_DEBUG_2_STAGE, + "%s for index %d (s1_pos %d s2_pos %d)\n", + __func__, buf->index, + pbi->s1_pos, pbi->s2_pos); +} + +static int get_free_stage_buf_num(struct VP9Decoder_s *pbi) +{ + int num; + if (pbi->s1_pos >= pbi->s2_pos) + num = pbi->used_stage_buf_num - + (pbi->s1_pos - pbi->s2_pos) - 1; + else + num = (pbi->s2_pos - pbi->s1_pos) - 1; + return num; +} + +#ifndef FB_DECODING_TEST_SCHEDULE +static DEFINE_SPINLOCK(fb_core_spin_lock); + +static u8 is_s2_decoding_finished(struct VP9Decoder_s *pbi) +{ + /* to do: VLSI review + completion of last LCU decoding in BACK + */ + return 1; +} + +static void start_s1_decoding(struct VP9Decoder_s *pbi) +{ + /* to do: VLSI review + after parser, how to start LCU decoding in BACK + */ +} + +static void fb_reset_core(struct vdec_s *vdec, u32 mask) +{ + /* to do: VLSI review + 1. how to disconnect DMC for FRONT and BACK + 2. reset bit 13, 24, FRONT or BACK ?? + */ + + unsigned long flags; + u32 reset_bits = 0; + if (mask & HW_MASK_FRONT) + WRITE_VREG(HEVC_STREAM_CONTROL, 0); + spin_lock_irqsave(&fb_core_spin_lock, flags); + codec_dmcbus_write(DMC_REQ_CTRL, + codec_dmcbus_read(DMC_REQ_CTRL) & (~(1 << 4))); + spin_unlock_irqrestore(&fb_core_spin_lock, flags); + + while (!(codec_dmcbus_read(DMC_CHAN_STS) + & (1 << 4))) + ; + + if ((mask & HW_MASK_FRONT) && + input_frame_based(vdec)) + WRITE_VREG(HEVC_STREAM_CONTROL, 0); + + /* + * 2: assist + * 3: parser + * 4: parser_state + * 8: dblk + * 11:mcpu + * 12:ccpu + * 13:ddr + * 14:iqit + * 15:ipp + * 17:qdct + * 18:mpred + * 19:sao + * 24:hevc_afifo + */ + if (mask & HW_MASK_FRONT) { + reset_bits = + (1<<3)|(1<<4)|(1<<11)| + (1<<12)|(1<<18); + } + if (mask & HW_MASK_BACK) { + reset_bits = + (1<<8)|(1<<13)|(1<<14)|(1<<15)| + (1<<17)|(1<<19)|(1<<24); + } + WRITE_VREG(DOS_SW_RESET3, reset_bits); +#if 0 + (1<<3)|(1<<4)|(1<<8)|(1<<11)| + (1<<12)|(1<<13)|(1<<14)|(1<<15)| + (1<<17)|(1<<18)|(1<<19)|(1<<24); +#endif + WRITE_VREG(DOS_SW_RESET3, 0); + + + spin_lock_irqsave(&fb_core_spin_lock, flags); + codec_dmcbus_write(DMC_REQ_CTRL, + codec_dmcbus_read(DMC_REQ_CTRL) | (1 << 4)); + spin_unlock_irqrestore(&fb_core_spin_lock, flags); + +} +#endif + +#endif + + +static int get_free_fb(struct VP9Decoder_s *pbi) +{ + struct VP9_Common_s *const cm = &pbi->common; + struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs; + int i; + unsigned long flags; + + lock_buffer_pool(cm->buffer_pool, flags); + if (debug & VP9_DEBUG_BUFMGR_MORE) { + for (i = 0; i < pbi->used_buf_num; ++i) { + pr_info("%s:%d, ref_count %d vf_ref %d index %d\r\n", + __func__, i, frame_bufs[i].ref_count, + frame_bufs[i].buf.vf_ref, + frame_bufs[i].buf.index); + } + } + for (i = 0; i < pbi->used_buf_num; ++i) { + if ((frame_bufs[i].ref_count == 0) && + (frame_bufs[i].buf.vf_ref == 0) && + (frame_bufs[i].buf.index != -1) + ) + break; + } + if (i != pbi->used_buf_num) { + frame_bufs[i].ref_count = 1; + /*pr_info("[MMU DEBUG 1] set ref_count[%d] : %d\r\n", + i, frame_bufs[i].ref_count);*/ + } else { + /* Reset i to be INVALID_IDX to indicate + no free buffer found*/ + i = INVALID_IDX; + } + + unlock_buffer_pool(cm->buffer_pool, flags); + return i; +} + +static int get_free_buf_count(struct VP9Decoder_s *pbi) +{ + struct VP9_Common_s *const cm = &pbi->common; + struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs; + int i; + int free_buf_count = 0; + for (i = 0; i < pbi->used_buf_num; ++i) + if ((frame_bufs[i].ref_count == 0) && + (frame_bufs[i].buf.vf_ref == 0) && + (frame_bufs[i].buf.index != -1) + ) + free_buf_count++; + return free_buf_count; +} + +static void decrease_ref_count(int idx, struct RefCntBuffer_s *const frame_bufs, + struct BufferPool_s *const pool) +{ + if (idx >= 0) { + --frame_bufs[idx].ref_count; + /*pr_info("[MMU DEBUG 7] dec ref_count[%d] : %d\r\n", idx, + * frame_bufs[idx].ref_count); + */ + /*A worker may only get a free framebuffer index when + *calling get_free_fb. But the private buffer is not set up + *until finish decoding header. So any error happens during + *decoding header, the frame_bufs will not have valid priv + *buffer. + */ + + if (frame_bufs[idx].ref_count == 0 && + frame_bufs[idx].raw_frame_buffer.priv) + vp9_release_frame_buffer + (&frame_bufs[idx].raw_frame_buffer); + } +} + +static void generate_next_ref_frames(struct VP9Decoder_s *pbi) +{ + struct VP9_Common_s *const cm = &pbi->common; + struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs; + struct BufferPool_s *const pool = cm->buffer_pool; + int mask, ref_index = 0; + unsigned long flags; + + /* Generate next_ref_frame_map.*/ + lock_buffer_pool(pool, flags); + for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) { + if (mask & 1) { + cm->next_ref_frame_map[ref_index] = cm->new_fb_idx; + ++frame_bufs[cm->new_fb_idx].ref_count; + /*pr_info("[MMU DEBUG 4] inc ref_count[%d] : %d\r\n", + *cm->new_fb_idx, frame_bufs[cm->new_fb_idx].ref_count); + */ + } else + cm->next_ref_frame_map[ref_index] = + cm->ref_frame_map[ref_index]; + /* Current thread holds the reference frame.*/ + if (cm->ref_frame_map[ref_index] >= 0) { + ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count; + /*pr_info + *("[MMU DEBUG 5] inc ref_count[%d] : %d\r\n", + *cm->ref_frame_map[ref_index], + *frame_bufs[cm->ref_frame_map[ref_index]].ref_count); + */ + } + ++ref_index; + } + + for (; ref_index < REF_FRAMES; ++ref_index) { + cm->next_ref_frame_map[ref_index] = + cm->ref_frame_map[ref_index]; + /* Current thread holds the reference frame.*/ + if (cm->ref_frame_map[ref_index] >= 0) { + ++frame_bufs[cm->ref_frame_map[ref_index]].ref_count; + /*pr_info("[MMU DEBUG 6] inc ref_count[%d] : %d\r\n", + *cm->ref_frame_map[ref_index], + *frame_bufs[cm->ref_frame_map[ref_index]].ref_count); + */ + } + } + unlock_buffer_pool(pool, flags); + return; +} + +static void refresh_ref_frames(struct VP9Decoder_s *pbi) + +{ + struct VP9_Common_s *const cm = &pbi->common; + struct BufferPool_s *pool = cm->buffer_pool; + struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs; + int mask, ref_index = 0; + unsigned long flags; + + lock_buffer_pool(pool, flags); + for (mask = pbi->refresh_frame_flags; mask; mask >>= 1) { + const int old_idx = cm->ref_frame_map[ref_index]; + /*Current thread releases the holding of reference frame.*/ + decrease_ref_count(old_idx, frame_bufs, pool); + + /*Release the reference frame in reference map.*/ + if ((mask & 1) && old_idx >= 0) + decrease_ref_count(old_idx, frame_bufs, pool); + cm->ref_frame_map[ref_index] = + cm->next_ref_frame_map[ref_index]; + ++ref_index; + } + + /*Current thread releases the holding of reference frame.*/ + for (; ref_index < REF_FRAMES && !cm->show_existing_frame; + ++ref_index) { + const int old_idx = cm->ref_frame_map[ref_index]; + + decrease_ref_count(old_idx, frame_bufs, pool); + cm->ref_frame_map[ref_index] = + cm->next_ref_frame_map[ref_index]; + } + unlock_buffer_pool(pool, flags); + return; +} +int vp9_bufmgr_process(struct VP9Decoder_s *pbi, union param_u *params) +{ + struct VP9_Common_s *const cm = &pbi->common; + struct BufferPool_s *pool = cm->buffer_pool; + struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs; + int i; + int ret; + + pbi->ready_for_new_data = 0; + + if (pbi->has_keyframe == 0 && + params->p.frame_type != KEY_FRAME){ + on_no_keyframe_skiped++; + return -2; + } + pbi->has_keyframe = 1; + on_no_keyframe_skiped = 0; +/* +#ifdef VP9_10B_MMU + if (!pbi->m_ins_flag) + pbi->used_4k_num = (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16); + if (cm->prev_fb_idx >= 0) { + decoder_mmu_box_free_idx_tail(pbi->mmu_box, + cm->prev_fb_idx, pbi->used_4k_num); + } +#endif +*/ + if (cm->new_fb_idx >= 0 + && frame_bufs[cm->new_fb_idx].ref_count == 0){ + vp9_release_frame_buffer + (&frame_bufs[cm->new_fb_idx].raw_frame_buffer); + } + /*pr_info("Before get_free_fb, prev_fb_idx : %d, new_fb_idx : %d\r\n", + cm->prev_fb_idx, cm->new_fb_idx);*/ +#ifndef MV_USE_FIXED_BUF + put_un_used_mv_bufs(pbi); + if (debug & VP9_DEBUG_BUFMGR_DETAIL) + dump_pic_list(pbi); +#endif + cm->new_fb_idx = get_free_fb(pbi); + if (cm->new_fb_idx == INVALID_IDX) { + pr_info("get_free_fb error\r\n"); + return -1; + } +#ifndef MV_USE_FIXED_BUF +#ifdef SUPPORT_FB_DECODING + if (pbi->used_stage_buf_num == 0) { +#endif + if (get_mv_buf(pbi, + &pool->frame_bufs[cm->new_fb_idx]. + buf.mv_buf_index, + &pool->frame_bufs[cm->new_fb_idx]. + buf.mpred_mv_wr_start_addr + ) < 0) { + pr_info("get_mv_buf fail\r\n"); + return -1; + } + if (debug & VP9_DEBUG_BUFMGR_DETAIL) + dump_pic_list(pbi); +#ifdef SUPPORT_FB_DECODING + } +#endif +#endif + cm->cur_frame = &pool->frame_bufs[cm->new_fb_idx]; + /*if (debug & VP9_DEBUG_BUFMGR) + pr_info("[VP9 DEBUG]%s(get_free_fb): %d\r\n", __func__, + cm->new_fb_idx);*/ + + pbi->cur_buf = &frame_bufs[cm->new_fb_idx]; +#ifdef VP9_10B_MMU + /* moved to after picture size ready + alloc_mmu(cm, params->p.width, params->p.height, + params->p.bit_depth, pbi->frame_mmu_map_addr);*/ + cm->prev_fb_idx = cm->new_fb_idx; +#endif + /*read_uncompressed_header()*/ + cm->last_frame_type = cm->frame_type; + cm->last_intra_only = cm->intra_only; + cm->profile = params->p.profile; + if (cm->profile >= MAX_PROFILES) { + pr_err("Error: Unsupported profile %d\r\n", cm->profile); + return -1; + } + cm->show_existing_frame = params->p.show_existing_frame; + if (cm->show_existing_frame) { + /* Show an existing frame directly.*/ + int frame_to_show_idx = params->p.frame_to_show_idx; + int frame_to_show; + unsigned long flags; + if (frame_to_show_idx >= REF_FRAMES) { + pr_info("frame_to_show_idx %d exceed max index\r\n", + frame_to_show_idx); + return -1; + } + + frame_to_show = cm->ref_frame_map[frame_to_show_idx]; + /*pr_info("frame_to_show %d\r\n", frame_to_show);*/ + lock_buffer_pool(pool, flags); + if (frame_to_show < 0 || + frame_bufs[frame_to_show].ref_count < 1) { + unlock_buffer_pool(pool, flags); + pr_err + ("Error:Buffer %d does not contain a decoded frame", + frame_to_show); + return -1; + } + + ref_cnt_fb(frame_bufs, &cm->new_fb_idx, frame_to_show); + unlock_buffer_pool(pool, flags); + pbi->refresh_frame_flags = 0; + /*cm->lf.filter_level = 0;*/ + cm->show_frame = 1; + + /* + *if (pbi->frame_parallel_decode) { + * for (i = 0; i < REF_FRAMES; ++i) + * cm->next_ref_frame_map[i] = + * cm->ref_frame_map[i]; + *} + */ + /* do not decode, search next start code */ + return 1; + } + cm->frame_type = params->p.frame_type; + cm->show_frame = params->p.show_frame; + cm->error_resilient_mode = params->p.error_resilient_mode; + + + if (cm->frame_type == KEY_FRAME) { + pbi->refresh_frame_flags = (1 << REF_FRAMES) - 1; + + for (i = 0; i < REFS_PER_FRAME; ++i) { + cm->frame_refs[i].idx = INVALID_IDX; + cm->frame_refs[i].buf = NULL; + } + + ret = setup_frame_size(pbi, + cm, params, pbi->frame_mmu_map_addr, + print_header_info); + if (ret) + return -1; + if (pbi->need_resync) { + memset(&cm->ref_frame_map, -1, + sizeof(cm->ref_frame_map)); + pbi->need_resync = 0; + } + } else { + cm->intra_only = cm->show_frame ? 0 : params->p.intra_only; + /*if (print_header_info) { + * if (cm->show_frame) + * pr_info + * ("intra_only set to 0 because of show_frame\n"); + * else + * pr_info + * ("1-bit intra_only read: %d\n", cm->intra_only); + *} + */ + + + cm->reset_frame_context = cm->error_resilient_mode ? + 0 : params->p.reset_frame_context; + if (print_header_info) { + if (cm->error_resilient_mode) + pr_info + ("reset to 0 error_resilient_mode\n"); + else + pr_info + (" * 2-bits reset_frame_context read : %d\n", + cm->reset_frame_context); + } + + if (cm->intra_only) { + if (cm->profile > PROFILE_0) { + /*read_bitdepth_colorspace_sampling(cm, + * rb, print_header_info); + */ + } else { + /*NOTE: The intra-only frame header + *does not include the specification + *of either the color format or + *color sub-sampling + *in profile 0. VP9 specifies that the default + *color format should be YUV 4:2:0 in this + *case (normative). + */ + cm->color_space = VPX_CS_BT_601; + cm->subsampling_y = cm->subsampling_x = 1; + cm->bit_depth = VPX_BITS_8; + cm->use_highbitdepth = 0; + } + + pbi->refresh_frame_flags = + params->p.refresh_frame_flags; + /*if (print_header_info) + * pr_info("*%d-bits refresh_frame read:0x%x\n", + * REF_FRAMES, pbi->refresh_frame_flags); + */ + ret = setup_frame_size(pbi, + cm, + params, + pbi->frame_mmu_map_addr, + print_header_info); + if (ret) + return -1; + if (pbi->need_resync) { + memset(&cm->ref_frame_map, -1, + sizeof(cm->ref_frame_map)); + pbi->need_resync = 0; + } + } else if (pbi->need_resync != 1) { /* Skip if need resync */ + pbi->refresh_frame_flags = + params->p.refresh_frame_flags; + if (print_header_info) + pr_info + ("*%d-bits refresh_frame read:0x%x\n", + REF_FRAMES, pbi->refresh_frame_flags); + for (i = 0; i < REFS_PER_FRAME; ++i) { + const int ref = + (params->p.ref_info >> + (((REFS_PER_FRAME-i-1)*4)+1)) + & 0x7; + const int idx = + cm->ref_frame_map[ref]; + struct RefBuffer_s * const ref_frame = + &cm->frame_refs[i]; + if (print_header_info) + pr_info("*%d-bits ref[%d]read:%d\n", + REF_FRAMES_LOG2, i, ref); + ref_frame->idx = idx; + ref_frame->buf = &frame_bufs[idx].buf; + cm->ref_frame_sign_bias[LAST_FRAME + i] + = (params->p.ref_info >> + ((REFS_PER_FRAME-i-1)*4)) & 0x1; + if (print_header_info) + pr_info("1bit ref_frame_sign_bias"); + /*pr_info + *("%dread: %d\n", + *LAST_FRAME+i, + *cm->ref_frame_sign_bias + *[LAST_FRAME + i]); + */ + /*pr_info + *("[VP9 DEBUG]%s(get ref):%d\r\n", + *__func__, ref_frame->idx); + */ + + } + + ret = setup_frame_size_with_refs( + pbi, + cm, + params, + pbi->frame_mmu_map_addr, + print_header_info); + if (ret) + return -1; + for (i = 0; i < REFS_PER_FRAME; ++i) { + /*struct RefBuffer_s *const ref_buf = + *&cm->frame_refs[i]; + */ + /* to do: + *vp9_setup_scale_factors_for_frame + */ + } + } + } + + get_frame_new_buffer(cm)->bit_depth = cm->bit_depth; + get_frame_new_buffer(cm)->color_space = cm->color_space; + get_frame_new_buffer(cm)->slice_type = cm->frame_type; + + if (pbi->need_resync) { + pr_err + ("Error: Keyframe/intra-only frame required to reset\r\n"); + return -1; + } + generate_next_ref_frames(pbi); + pbi->hold_ref_buf = 1; + +#if 0 + if (frame_is_intra_only(cm) || cm->error_resilient_mode) + vp9_setup_past_independence(cm); + setup_loopfilter(&cm->lf, rb, print_header_info); + setup_quantization(cm, &pbi->mb, rb, print_header_info); + setup_segmentation(&cm->seg, rb, print_header_info); + setup_segmentation_dequant(cm, print_header_info); + + setup_tile_info(cm, rb, print_header_info); + sz = vp9_rb_read_literal(rb, 16); + if (print_header_info) + pr_info(" * 16-bits size read : %d (0x%x)\n", sz, sz); + + if (sz == 0) + vpx_internal_error(&cm->error, VPX_CODEC_CORRUPT_FRAME, + "Invalid header size"); +#endif + /*end read_uncompressed_header()*/ + cm->use_prev_frame_mvs = !cm->error_resilient_mode && + cm->width == cm->last_width && + cm->height == cm->last_height && + !cm->last_intra_only && + cm->last_show_frame && + (cm->last_frame_type != KEY_FRAME); + + /*pr_info + *("set use_prev_frame_mvs to %d (last_width %d last_height %d", + *cm->use_prev_frame_mvs, cm->last_width, cm->last_height); + *pr_info + *(" last_intra_only %d last_show_frame %d last_frame_type %d)\n", + *cm->last_intra_only, cm->last_show_frame, cm->last_frame_type); + */ + return 0; +} + + +void swap_frame_buffers(struct VP9Decoder_s *pbi) +{ + int ref_index = 0; + struct VP9_Common_s *const cm = &pbi->common; + struct BufferPool_s *const pool = cm->buffer_pool; + struct RefCntBuffer_s *const frame_bufs = cm->buffer_pool->frame_bufs; + unsigned long flags; + refresh_ref_frames(pbi); + pbi->hold_ref_buf = 0; + cm->frame_to_show = get_frame_new_buffer(cm); + + /*if (!pbi->frame_parallel_decode || !cm->show_frame) {*/ + lock_buffer_pool(pool, flags); + --frame_bufs[cm->new_fb_idx].ref_count; + /*pr_info("[MMU DEBUG 8] dec ref_count[%d] : %d\r\n", cm->new_fb_idx, + * frame_bufs[cm->new_fb_idx].ref_count); + */ + unlock_buffer_pool(pool, flags); + /*}*/ + + /*Invalidate these references until the next frame starts.*/ + for (ref_index = 0; ref_index < 3; ref_index++) + cm->frame_refs[ref_index].idx = -1; +} + +#if 0 +static void check_resync(vpx_codec_alg_priv_t *const ctx, + const struct VP9Decoder_s *const pbi) +{ + /* Clear resync flag if worker got a key frame or intra only frame.*/ + if (ctx->need_resync == 1 && pbi->need_resync == 0 && + (pbi->common.intra_only || pbi->common.frame_type == KEY_FRAME)) + ctx->need_resync = 0; +} +#endif + +int vp9_get_raw_frame(struct VP9Decoder_s *pbi, struct PIC_BUFFER_CONFIG_s *sd) +{ + struct VP9_Common_s *const cm = &pbi->common; + int ret = -1; + + if (pbi->ready_for_new_data == 1) + return ret; + + pbi->ready_for_new_data = 1; + + /* no raw frame to show!!! */ + if (!cm->show_frame) + return ret; + + pbi->ready_for_new_data = 1; + + *sd = *cm->frame_to_show; + ret = 0; + + return ret; +} + +int vp9_bufmgr_init(struct VP9Decoder_s *pbi, struct BuffInfo_s *buf_spec_i, + struct buff_s *mc_buf_i) { + struct VP9_Common_s *cm = &pbi->common; + + /*memset(pbi, 0, sizeof(struct VP9Decoder_s));*/ + pbi->frame_count = 0; + pbi->pic_count = 0; + pbi->pre_stream_offset = 0; + cm->buffer_pool = &pbi->vp9_buffer_pool; + spin_lock_init(&cm->buffer_pool->lock); + cm->prev_fb_idx = INVALID_IDX; + cm->new_fb_idx = INVALID_IDX; +#ifdef VP9_10B_MMU + pbi->used_4k_num = -1; + cm->cur_fb_idx_mmu = INVALID_IDX; +#endif + pr_debug + ("After vp9_bufmgr_init, prev_fb_idx : %d, new_fb_idx : %d\r\n", + cm->prev_fb_idx, cm->new_fb_idx); + pbi->need_resync = 1; + /* Initialize the references to not point to any frame buffers.*/ + memset(&cm->ref_frame_map, -1, sizeof(cm->ref_frame_map)); + memset(&cm->next_ref_frame_map, -1, sizeof(cm->next_ref_frame_map)); + cm->current_video_frame = 0; + pbi->ready_for_new_data = 1; + + /* private init */ + pbi->work_space_buf = buf_spec_i; +#ifndef VP9_10B_MMU + pbi->mc_buf = mc_buf_i; +#endif + pbi->rpm_addr = NULL; + pbi->lmem_addr = NULL; + + pbi->use_cma_flag = 0; + pbi->decode_idx = 0; + pbi->slice_idx = 0; + /*int m_uiMaxCUWidth = 1<<7;*/ + /*int m_uiMaxCUHeight = 1<<7;*/ + pbi->has_keyframe = 0; + pbi->skip_flag = 0; + pbi->wait_buf = 0; + pbi->error_flag = 0; + + pbi->pts_mode = PTS_NORMAL; + pbi->last_pts = 0; + pbi->last_lookup_pts = 0; + pbi->last_pts_us64 = 0; + pbi->last_lookup_pts_us64 = 0; + pbi->shift_byte_count = 0; + pbi->shift_byte_count_lo = 0; + pbi->shift_byte_count_hi = 0; + pbi->pts_mode_switching_count = 0; + pbi->pts_mode_recovery_count = 0; + + pbi->buf_num = 0; + pbi->pic_num = 0; + + return 0; +} + + +int vp9_bufmgr_postproc(struct VP9Decoder_s *pbi) +{ + struct VP9_Common_s *cm = &pbi->common; + struct PIC_BUFFER_CONFIG_s sd; + + swap_frame_buffers(pbi); + if (!cm->show_existing_frame) { + cm->last_show_frame = cm->show_frame; + cm->prev_frame = cm->cur_frame; +#if 0 + if (cm->seg.enabled && !pbi->frame_parallel_decode) + vp9_swap_current_and_last_seg_map(cm); +#endif + } + cm->last_width = cm->width; + cm->last_height = cm->height; + if (cm->show_frame) + cm->current_video_frame++; + + if (vp9_get_raw_frame(pbi, &sd) == 0) { + /*pr_info("Display frame index %d\r\n", sd.index);*/ + sd.stream_offset = pbi->pre_stream_offset; + prepare_display_buf(pbi, &sd); + pbi->pre_stream_offset = READ_VREG(HEVC_SHIFT_BYTE_COUNT); + } + +/* else + * pr_info + * ("Not display this frame,ready_for_new_data%d show_frame%d\r\n", + * pbi->ready_for_new_data, cm->show_frame); + */ + return 0; +} + +struct VP9Decoder_s vp9_decoder; +union param_u vp9_param; + +/************************************************** + * + *VP9 buffer management end + * + *************************************************** + */ + + +#define HEVC_CM_BODY_START_ADDR 0x3626 +#define HEVC_CM_BODY_LENGTH 0x3627 +#define HEVC_CM_HEADER_LENGTH 0x3629 +#define HEVC_CM_HEADER_OFFSET 0x362b + +#define LOSLESS_COMPRESS_MODE + +/*#define DECOMP_HEADR_SURGENT*/ + +static u32 mem_map_mode; /* 0:linear 1:32x32 2:64x32 ; m8baby test1902 */ +static u32 enable_mem_saving = 1; +static u32 force_w_h; + +static u32 force_fps; + + +const u32 vp9_version = 201602101; +static u32 debug; +static u32 radr; +static u32 rval; +static u32 pop_shorts; +static u32 dbg_cmd; +static u32 dbg_skip_decode_index; +static u32 endian = 0xff0; +#ifdef ERROR_HANDLE_DEBUG +static u32 dbg_nal_skip_flag; + /* bit[0], skip vps; bit[1], skip sps; bit[2], skip pps */ +static u32 dbg_nal_skip_count; +#endif +/*for debug*/ +static u32 decode_pic_begin; +static uint slice_parse_begin; +static u32 step; +#ifdef MIX_STREAM_SUPPORT +#ifdef SUPPORT_4K2K +static u32 buf_alloc_width = 4096; +static u32 buf_alloc_height = 2304; +static u32 vp9_max_pic_w = 4096; +static u32 vp9_max_pic_h = 2304; +#else +static u32 buf_alloc_width = 1920; +static u32 buf_alloc_height = 1088; +static u32 vp9_max_pic_w = 1920; +static u32 vp9_max_pic_h = 1088; + +#endif +static u32 dynamic_buf_num_margin; +#else +static u32 buf_alloc_width; +static u32 buf_alloc_height; +static u32 dynamic_buf_num_margin = 7; +#endif +static u32 buf_alloc_depth = 10; +static u32 buf_alloc_size; +/* + *bit[0]: 0, + * bit[1]: 0, always release cma buffer when stop + * bit[1]: 1, never release cma buffer when stop + *bit[0]: 1, when stop, release cma buffer if blackout is 1; + *do not release cma buffer is blackout is not 1 + * + *bit[2]: 0, when start decoding, check current displayed buffer + * (only for buffer decoded by vp9) if blackout is 0 + * 1, do not check current displayed buffer + * + *bit[3]: 1, if blackout is not 1, do not release current + * displayed cma buffer always. + */ +/* set to 1 for fast play; + * set to 8 for other case of "keep last frame" + */ +static u32 buffer_mode = 1; +/* buffer_mode_dbg: debug only*/ +static u32 buffer_mode_dbg = 0xffff0000; +/**/ + +/* + *bit 0, 1: only display I picture; + *bit 1, 1: only decode I picture; + */ +static u32 i_only_flag; + + +static u32 max_decoding_time; +/* + *error handling + */ +/*error_handle_policy: + *bit 0: 0, auto skip error_skip_nal_count nals before error recovery; + *1, skip error_skip_nal_count nals before error recovery; + *bit 1 (valid only when bit0 == 1): + *1, wait vps/sps/pps after error recovery; + *bit 2 (valid only when bit0 == 0): + *0, auto search after error recovery (vp9_recover() called); + *1, manual search after error recovery + *(change to auto search after get IDR: WRITE_VREG(NAL_SEARCH_CTL, 0x2)) + * + *bit 4: 0, set error_mark after reset/recover + * 1, do not set error_mark after reset/recover + *bit 5: 0, check total lcu for every picture + * 1, do not check total lcu + * + */ + +static u32 error_handle_policy; +/*static u32 parser_sei_enable = 1;*/ + +static u32 max_buf_num = 10; + +static u32 run_ready_min_buf_num = 2; + +static DEFINE_MUTEX(vvp9_mutex); +#ifndef MULTI_INSTANCE_SUPPORT +static struct device *cma_dev; +#endif + +#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0 +#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1 +#define HEVC_SHORT_TERM_RPS HEVC_ASSIST_SCRATCH_2 +#define VP9_ADAPT_PROB_REG HEVC_ASSIST_SCRATCH_3 +#define VP9_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_4 +#define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5 +#define HEVC_SAO_UP HEVC_ASSIST_SCRATCH_6 +#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7 +#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8 +#define VP9_PROB_SWAP_BUFFER HEVC_ASSIST_SCRATCH_9 +#define VP9_COUNT_SWAP_BUFFER HEVC_ASSIST_SCRATCH_A +#define VP9_SEG_MAP_BUFFER HEVC_ASSIST_SCRATCH_B +#define HEVC_SCALELUT HEVC_ASSIST_SCRATCH_D +#define HEVC_WAIT_FLAG HEVC_ASSIST_SCRATCH_E +#define RPM_CMD_REG HEVC_ASSIST_SCRATCH_F +#define LMEM_DUMP_ADR HEVC_ASSIST_SCRATCH_F +#define HEVC_STREAM_SWAP_TEST HEVC_ASSIST_SCRATCH_L +#ifdef MULTI_INSTANCE_SUPPORT +#define HEVC_DECODE_COUNT HEVC_ASSIST_SCRATCH_M +#define HEVC_DECODE_SIZE HEVC_ASSIST_SCRATCH_N +#else +#define HEVC_DECODE_PIC_BEGIN_REG HEVC_ASSIST_SCRATCH_M +#define HEVC_DECODE_PIC_NUM_REG HEVC_ASSIST_SCRATCH_N +#endif +#define DEBUG_REG1 HEVC_ASSIST_SCRATCH_G +#define DEBUG_REG2 HEVC_ASSIST_SCRATCH_H + + +/* + *ucode parser/search control + *bit 0: 0, header auto parse; 1, header manual parse + *bit 1: 0, auto skip for noneseamless stream; 1, no skip + *bit [3:2]: valid when bit1==0; + *0, auto skip nal before first vps/sps/pps/idr; + *1, auto skip nal before first vps/sps/pps + *2, auto skip nal before first vps/sps/pps, + * and not decode until the first I slice (with slice address of 0) + * + *3, auto skip before first I slice (nal_type >=16 && nal_type<=21) + *bit [15:4] nal skip count (valid when bit0 == 1 (manual mode) ) + *bit [16]: for NAL_UNIT_EOS when bit0 is 0: + * 0, send SEARCH_DONE to arm ; 1, do not send SEARCH_DONE to arm + *bit [17]: for NAL_SEI when bit0 is 0: + * 0, do not parse SEI in ucode; 1, parse SEI in ucode + *bit [31:20]: used by ucode for debug purpose + */ +#define NAL_SEARCH_CTL HEVC_ASSIST_SCRATCH_I + /*[31:24] chip feature + 31: 0, use MBOX1; 1, use MBOX0 + */ +#define DECODE_MODE HEVC_ASSIST_SCRATCH_J +#define DECODE_STOP_POS HEVC_ASSIST_SCRATCH_K + +#ifdef MULTI_INSTANCE_SUPPORT +#define RPM_BUF_SIZE (0x400 * 2) +#else +#define RPM_BUF_SIZE (0x80*2) +#endif +#define LMEM_BUF_SIZE (0x400 * 2) + +#define WORK_BUF_SPEC_NUM 2 +static struct BuffInfo_s amvvp9_workbuff_spec[WORK_BUF_SPEC_NUM] = { + { + /* 8M bytes */ + .max_width = 1920, + .max_height = 1088, + .ipp = { + /* IPP work space calculation : + * 4096 * (Y+CbCr+Flags) = 12k, round to 16k + */ + .buf_size = 0x4000, + }, + .sao_abv = { + .buf_size = 0x30000, + }, + .sao_vb = { + .buf_size = 0x30000, + }, + .short_term_rps = { + /* SHORT_TERM_RPS - Max 64 set, 16 entry every set, + * total 64x16x2 = 2048 bytes (0x800) + */ + .buf_size = 0x800, + }, + .vps = { + /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, + * total 0x0800 bytes + */ + .buf_size = 0x800, + }, + .sps = { + /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, + * total 0x0800 bytes + */ + .buf_size = 0x800, + }, + .pps = { + /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, + * total 0x2000 bytes + */ + .buf_size = 0x2000, + }, + .sao_up = { + /* SAO UP STORE AREA - Max 640(10240/16) LCU, + * each has 16 bytes total 0x2800 bytes + */ + .buf_size = 0x2800, + }, + .swap_buf = { + /* 256cyclex64bit = 2K bytes 0x800 + * (only 144 cycles valid) + */ + .buf_size = 0x800, + }, + .swap_buf2 = { + .buf_size = 0x800, + }, + .scalelut = { + /* support up to 32 SCALELUT 1024x32 = + * 32Kbytes (0x8000) + */ + .buf_size = 0x8000, + }, + .dblk_para = { + /* DBLK -> Max 256(4096/16) LCU, + *each para 1024bytes(total:0x40000), + *data 1024bytes(total:0x40000) + */ + .buf_size = 0x80000, + }, + .dblk_data = { + .buf_size = 0x80000, + }, + .seg_map = { + /*4096x2304/64/64 *24 = 0xd800 Bytes*/ + .buf_size = 0xd800, + }, +#ifdef VP9_10B_MMU + .mmu_vbh = { + .buf_size = 0x5000, /*2*16*(more than 2304)/4, 4K*/ + }, +#if 0 + .cm_header = { + /*add one for keeper.*/ + .buf_size = MMU_COMPRESS_HEADER_SIZE * + (FRAME_BUFFERS + 1), + /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */ + }, +#endif +#endif + .mpred_above = { + .buf_size = 0x10000, /* 2 * size of hevc*/ + }, +#ifdef MV_USE_FIXED_BUF + .mpred_mv = {/* 1080p, 0x40000 per buffer */ + .buf_size = 0x40000 * FRAME_BUFFERS, + }, +#endif + .rpm = { + .buf_size = RPM_BUF_SIZE, + }, + .lmem = { + .buf_size = 0x400 * 2, + } + }, + { + .max_width = 4096, + .max_height = 2304, + .ipp = { + /* IPP work space calculation : + * 4096 * (Y+CbCr+Flags) = 12k, round to 16k + */ + .buf_size = 0x4000, + }, + .sao_abv = { + .buf_size = 0x30000, + }, + .sao_vb = { + .buf_size = 0x30000, + }, + .short_term_rps = { + /* SHORT_TERM_RPS - Max 64 set, 16 entry every set, + * total 64x16x2 = 2048 bytes (0x800) + */ + .buf_size = 0x800, + }, + .vps = { + /* VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, + * total 0x0800 bytes + */ + .buf_size = 0x800, + }, + .sps = { + /* SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, + * total 0x0800 bytes + */ + .buf_size = 0x800, + }, + .pps = { + /* PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, + * total 0x2000 bytes + */ + .buf_size = 0x2000, + }, + .sao_up = { + /* SAO UP STORE AREA - Max 640(10240/16) LCU, + * each has 16 bytes total 0x2800 bytes + */ + .buf_size = 0x2800, + }, + .swap_buf = { + /* 256cyclex64bit = 2K bytes 0x800 + * (only 144 cycles valid) + */ + .buf_size = 0x800, + }, + .swap_buf2 = { + .buf_size = 0x800, + }, + .scalelut = { + /* support up to 32 SCALELUT 1024x32 = 32Kbytes + * (0x8000) + */ + .buf_size = 0x8000, + }, + .dblk_para = { + /* DBLK -> Max 256(4096/16) LCU, + *each para 1024bytes(total:0x40000), + *data 1024bytes(total:0x40000) + */ + .buf_size = 0x80000, + }, + .dblk_data = { + .buf_size = 0x80000, + }, + .seg_map = { + /*4096x2304/64/64 *24 = 0xd800 Bytes*/ + .buf_size = 0xd800, + }, +#ifdef VP9_10B_MMU + .mmu_vbh = { + .buf_size = 0x5000,/*2*16*(more than 2304)/4, 4K*/ + }, +#if 0 + .cm_header = { + /*add one for keeper.*/ + .buf_size = MMU_COMPRESS_HEADER_SIZE * + (FRAME_BUFFERS + 1), + /* 0x44000 = ((1088*2*1024*4)/32/4)*(32/8) */ + }, +#endif +#endif + .mpred_above = { + .buf_size = 0x10000, /* 2 * size of hevc*/ + }, +#ifdef MV_USE_FIXED_BUF + .mpred_mv = { + /* .buf_size = 0x100000*16, + * //4k2k , 0x100000 per buffer + */ + /* 4096x2304 , 0x120000 per buffer */ + .buf_size = 0x120000 * FRAME_BUFFERS, + }, +#endif + .rpm = { + .buf_size = RPM_BUF_SIZE, + }, + .lmem = { + .buf_size = 0x400 * 2, + } + } +}; + + +/*Losless compression body buffer size 4K per 64x32 (jt)*/ +int compute_losless_comp_body_size(int width, int height, + uint8_t is_bit_depth_10) +{ + int width_x64; + int height_x32; + int bsize; + + width_x64 = width + 63; + width_x64 >>= 6; + height_x32 = height + 31; + height_x32 >>= 5; +#ifdef VP9_10B_MMU + bsize = (is_bit_depth_10?4096:3200)*width_x64*height_x32; +#else + bsize = (is_bit_depth_10?4096:3072)*width_x64*height_x32; +#endif + if (debug & VP9_DEBUG_BUFMGR_MORE) + pr_info("%s(%d,%d,%d)=>%d\n", + __func__, width, height, + is_bit_depth_10, bsize); + + return bsize; +} + +/* Losless compression header buffer size 32bytes per 128x64 (jt)*/ +static int compute_losless_comp_header_size(int width, int height) +{ + int width_x128; + int height_x64; + int hsize; + + width_x128 = width + 127; + width_x128 >>= 7; + height_x64 = height + 63; + height_x64 >>= 6; + + hsize = 32 * width_x128 * height_x64; + if (debug & VP9_DEBUG_BUFMGR_MORE) + pr_info("%s(%d,%d)=>%d\n", + __func__, width, height, + hsize); + + return hsize; +} + +static void init_buff_spec(struct VP9Decoder_s *pbi, + struct BuffInfo_s *buf_spec) +{ + void *mem_start_virt; + + buf_spec->ipp.buf_start = buf_spec->start_adr; + buf_spec->sao_abv.buf_start = + buf_spec->ipp.buf_start + buf_spec->ipp.buf_size; + + buf_spec->sao_vb.buf_start = + buf_spec->sao_abv.buf_start + buf_spec->sao_abv.buf_size; + buf_spec->short_term_rps.buf_start = + buf_spec->sao_vb.buf_start + buf_spec->sao_vb.buf_size; + buf_spec->vps.buf_start = + buf_spec->short_term_rps.buf_start + + buf_spec->short_term_rps.buf_size; + buf_spec->sps.buf_start = + buf_spec->vps.buf_start + buf_spec->vps.buf_size; + buf_spec->pps.buf_start = + buf_spec->sps.buf_start + buf_spec->sps.buf_size; + buf_spec->sao_up.buf_start = + buf_spec->pps.buf_start + buf_spec->pps.buf_size; + buf_spec->swap_buf.buf_start = + buf_spec->sao_up.buf_start + buf_spec->sao_up.buf_size; + buf_spec->swap_buf2.buf_start = + buf_spec->swap_buf.buf_start + buf_spec->swap_buf.buf_size; + buf_spec->scalelut.buf_start = + buf_spec->swap_buf2.buf_start + buf_spec->swap_buf2.buf_size; + buf_spec->dblk_para.buf_start = + buf_spec->scalelut.buf_start + buf_spec->scalelut.buf_size; + buf_spec->dblk_data.buf_start = + buf_spec->dblk_para.buf_start + buf_spec->dblk_para.buf_size; + buf_spec->seg_map.buf_start = + buf_spec->dblk_data.buf_start + buf_spec->dblk_data.buf_size; +#ifdef VP9_10B_MMU + buf_spec->mmu_vbh.buf_start = + buf_spec->seg_map.buf_start + buf_spec->seg_map.buf_size; + buf_spec->mpred_above.buf_start = + buf_spec->mmu_vbh.buf_start + buf_spec->mmu_vbh.buf_size; +#else + buf_spec->mpred_above.buf_start = + buf_spec->seg_map.buf_start + buf_spec->seg_map.buf_size; +#endif +#ifdef MV_USE_FIXED_BUF + buf_spec->mpred_mv.buf_start = + buf_spec->mpred_above.buf_start + + buf_spec->mpred_above.buf_size; + + buf_spec->rpm.buf_start = + buf_spec->mpred_mv.buf_start + + buf_spec->mpred_mv.buf_size; +#else + buf_spec->rpm.buf_start = + buf_spec->mpred_above.buf_start + + buf_spec->mpred_above.buf_size; + +#endif + buf_spec->lmem.buf_start = + buf_spec->rpm.buf_start + + buf_spec->rpm.buf_size; + buf_spec->end_adr = + buf_spec->lmem.buf_start + + buf_spec->lmem.buf_size; + + if (pbi) { + mem_start_virt = + codec_mm_phys_to_virt(buf_spec->dblk_para.buf_start); + if (mem_start_virt) { + memset(mem_start_virt, 0, buf_spec->dblk_para.buf_size); + codec_mm_dma_flush(mem_start_virt, + buf_spec->dblk_para.buf_size, + DMA_TO_DEVICE); + } else { + /*not virt for tvp playing, + may need clear on ucode.*/ + pr_err("mem_start_virt failed\n"); + } + if (debug) { + pr_info("%s workspace (%x %x) size = %x\n", __func__, + buf_spec->start_adr, buf_spec->end_adr, + buf_spec->end_adr - buf_spec->start_adr); + } + if (debug) { + pr_info("ipp.buf_start :%x\n", + buf_spec->ipp.buf_start); + pr_info("sao_abv.buf_start :%x\n", + buf_spec->sao_abv.buf_start); + pr_info("sao_vb.buf_start :%x\n", + buf_spec->sao_vb.buf_start); + pr_info("short_term_rps.buf_start :%x\n", + buf_spec->short_term_rps.buf_start); + pr_info("vps.buf_start :%x\n", + buf_spec->vps.buf_start); + pr_info("sps.buf_start :%x\n", + buf_spec->sps.buf_start); + pr_info("pps.buf_start :%x\n", + buf_spec->pps.buf_start); + pr_info("sao_up.buf_start :%x\n", + buf_spec->sao_up.buf_start); + pr_info("swap_buf.buf_start :%x\n", + buf_spec->swap_buf.buf_start); + pr_info("swap_buf2.buf_start :%x\n", + buf_spec->swap_buf2.buf_start); + pr_info("scalelut.buf_start :%x\n", + buf_spec->scalelut.buf_start); + pr_info("dblk_para.buf_start :%x\n", + buf_spec->dblk_para.buf_start); + pr_info("dblk_data.buf_start :%x\n", + buf_spec->dblk_data.buf_start); + pr_info("seg_map.buf_start :%x\n", + buf_spec->seg_map.buf_start); + #ifdef VP9_10B_MMU + pr_info("mmu_vbh.buf_start :%x\n", + buf_spec->mmu_vbh.buf_start); + #endif + pr_info("mpred_above.buf_start :%x\n", + buf_spec->mpred_above.buf_start); +#ifdef MV_USE_FIXED_BUF + pr_info("mpred_mv.buf_start :%x\n", + buf_spec->mpred_mv.buf_start); +#endif + if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) { + pr_info("rpm.buf_start :%x\n", + buf_spec->rpm.buf_start); + } + } + } + +} + +/* cache_util.c */ +#define THODIYIL_MCRCC_CANVAS_ALGX 4 + +static u32 mcrcc_cache_alg_flag = THODIYIL_MCRCC_CANVAS_ALGX; + +static void mcrcc_perfcount_reset(void) +{ + if (debug & VP9_DEBUG_CACHE) + pr_info("[cache_util.c] Entered mcrcc_perfcount_reset...\n"); + WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x1); + WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x0); + return; +} + +static unsigned raw_mcr_cnt_total_prev; +static unsigned hit_mcr_0_cnt_total_prev; +static unsigned hit_mcr_1_cnt_total_prev; +static unsigned byp_mcr_cnt_nchcanv_total_prev; +static unsigned byp_mcr_cnt_nchoutwin_total_prev; + +static void mcrcc_get_hitrate(unsigned reset_pre) +{ + unsigned delta_hit_mcr_0_cnt; + unsigned delta_hit_mcr_1_cnt; + unsigned delta_raw_mcr_cnt; + unsigned delta_mcr_cnt_nchcanv; + unsigned delta_mcr_cnt_nchoutwin; + + unsigned tmp; + unsigned raw_mcr_cnt; + unsigned hit_mcr_cnt; + unsigned byp_mcr_cnt_nchoutwin; + unsigned byp_mcr_cnt_nchcanv; + int hitrate; + if (reset_pre) { + raw_mcr_cnt_total_prev = 0; + hit_mcr_0_cnt_total_prev = 0; + hit_mcr_1_cnt_total_prev = 0; + byp_mcr_cnt_nchcanv_total_prev = 0; + byp_mcr_cnt_nchoutwin_total_prev = 0; + } + if (debug & VP9_DEBUG_CACHE) + pr_info("[cache_util.c] Entered mcrcc_get_hitrate...\n"); + WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x0<<1)); + raw_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); + WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x1<<1)); + hit_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); + WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x2<<1)); + byp_mcr_cnt_nchoutwin = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); + WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x3<<1)); + byp_mcr_cnt_nchcanv = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); + + if (debug & VP9_DEBUG_CACHE) + pr_info("raw_mcr_cnt_total: %d\n", + raw_mcr_cnt); + if (debug & VP9_DEBUG_CACHE) + pr_info("hit_mcr_cnt_total: %d\n", + hit_mcr_cnt); + if (debug & VP9_DEBUG_CACHE) + pr_info("byp_mcr_cnt_nchoutwin_total: %d\n", + byp_mcr_cnt_nchoutwin); + if (debug & VP9_DEBUG_CACHE) + pr_info("byp_mcr_cnt_nchcanv_total: %d\n", + byp_mcr_cnt_nchcanv); + + delta_raw_mcr_cnt = raw_mcr_cnt - + raw_mcr_cnt_total_prev; + delta_mcr_cnt_nchcanv = byp_mcr_cnt_nchcanv - + byp_mcr_cnt_nchcanv_total_prev; + delta_mcr_cnt_nchoutwin = byp_mcr_cnt_nchoutwin - + byp_mcr_cnt_nchoutwin_total_prev; + raw_mcr_cnt_total_prev = raw_mcr_cnt; + byp_mcr_cnt_nchcanv_total_prev = byp_mcr_cnt_nchcanv; + byp_mcr_cnt_nchoutwin_total_prev = byp_mcr_cnt_nchoutwin; + + WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x4<<1)); + tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); + if (debug & VP9_DEBUG_CACHE) + pr_info("miss_mcr_0_cnt_total: %d\n", tmp); + WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x5<<1)); + tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); + if (debug & VP9_DEBUG_CACHE) + pr_info("miss_mcr_1_cnt_total: %d\n", tmp); + WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x6<<1)); + tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); + if (debug & VP9_DEBUG_CACHE) + pr_info("hit_mcr_0_cnt_total: %d\n", tmp); + delta_hit_mcr_0_cnt = tmp - hit_mcr_0_cnt_total_prev; + hit_mcr_0_cnt_total_prev = tmp; + WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x7<<1)); + tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA); + if (debug & VP9_DEBUG_CACHE) + pr_info("hit_mcr_1_cnt_total: %d\n", tmp); + delta_hit_mcr_1_cnt = tmp - hit_mcr_1_cnt_total_prev; + hit_mcr_1_cnt_total_prev = tmp; + + if (delta_raw_mcr_cnt != 0) { + hitrate = 100 * delta_hit_mcr_0_cnt + / delta_raw_mcr_cnt; + if (debug & VP9_DEBUG_CACHE) + pr_info("CANV0_HIT_RATE : %d\n", hitrate); + hitrate = 100 * delta_hit_mcr_1_cnt + / delta_raw_mcr_cnt; + if (debug & VP9_DEBUG_CACHE) + pr_info("CANV1_HIT_RATE : %d\n", hitrate); + hitrate = 100 * delta_mcr_cnt_nchcanv + / delta_raw_mcr_cnt; + if (debug & VP9_DEBUG_CACHE) + pr_info("NONCACH_CANV_BYP_RATE : %d\n", hitrate); + hitrate = 100 * delta_mcr_cnt_nchoutwin + / delta_raw_mcr_cnt; + if (debug & VP9_DEBUG_CACHE) + pr_info("CACHE_OUTWIN_BYP_RATE : %d\n", hitrate); + } + + + if (raw_mcr_cnt != 0) { + hitrate = 100 * hit_mcr_cnt / raw_mcr_cnt; + if (debug & VP9_DEBUG_CACHE) + pr_info("MCRCC_HIT_RATE : %d\n", hitrate); + hitrate = 100 * (byp_mcr_cnt_nchoutwin + byp_mcr_cnt_nchcanv) + / raw_mcr_cnt; + if (debug & VP9_DEBUG_CACHE) + pr_info("MCRCC_BYP_RATE : %d\n", hitrate); + } else { + if (debug & VP9_DEBUG_CACHE) + pr_info("MCRCC_HIT_RATE : na\n"); + if (debug & VP9_DEBUG_CACHE) + pr_info("MCRCC_BYP_RATE : na\n"); + } + return; +} + + +static void decomp_perfcount_reset(void) +{ + if (debug & VP9_DEBUG_CACHE) + pr_info("[cache_util.c] Entered decomp_perfcount_reset...\n"); + WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x1); + WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x0); + return; +} + +static void decomp_get_hitrate(void) +{ + unsigned raw_mcr_cnt; + unsigned hit_mcr_cnt; + int hitrate; + if (debug & VP9_DEBUG_CACHE) + pr_info("[cache_util.c] Entered decomp_get_hitrate...\n"); + WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x0<<1)); + raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); + WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x1<<1)); + hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); + + if (debug & VP9_DEBUG_CACHE) + pr_info("hcache_raw_cnt_total: %d\n", raw_mcr_cnt); + if (debug & VP9_DEBUG_CACHE) + pr_info("hcache_hit_cnt_total: %d\n", hit_mcr_cnt); + + if (raw_mcr_cnt != 0) { + hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt; + if (debug & VP9_DEBUG_CACHE) + pr_info("DECOMP_HCACHE_HIT_RATE : %d\n", hitrate); + } else { + if (debug & VP9_DEBUG_CACHE) + pr_info("DECOMP_HCACHE_HIT_RATE : na\n"); + } + WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x2<<1)); + raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); + WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x3<<1)); + hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); + + if (debug & VP9_DEBUG_CACHE) + pr_info("dcache_raw_cnt_total: %d\n", raw_mcr_cnt); + if (debug & VP9_DEBUG_CACHE) + pr_info("dcache_hit_cnt_total: %d\n", hit_mcr_cnt); + + if (raw_mcr_cnt != 0) { + hitrate = hit_mcr_cnt * 100 / raw_mcr_cnt; + if (debug & VP9_DEBUG_CACHE) + pr_info("DECOMP_DCACHE_HIT_RATE : %d\n", hitrate); + } else { + if (debug & VP9_DEBUG_CACHE) + pr_info("DECOMP_DCACHE_HIT_RATE : na\n"); + } + return; +} + +static void decomp_get_comprate(void) +{ + unsigned raw_ucomp_cnt; + unsigned fast_comp_cnt; + unsigned slow_comp_cnt; + int comprate; + + if (debug & VP9_DEBUG_CACHE) + pr_info("[cache_util.c] Entered decomp_get_comprate...\n"); + WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x4<<1)); + fast_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); + WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x5<<1)); + slow_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); + WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x6<<1)); + raw_ucomp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA); + + if (debug & VP9_DEBUG_CACHE) + pr_info("decomp_fast_comp_total: %d\n", fast_comp_cnt); + if (debug & VP9_DEBUG_CACHE) + pr_info("decomp_slow_comp_total: %d\n", slow_comp_cnt); + if (debug & VP9_DEBUG_CACHE) + pr_info("decomp_raw_uncomp_total: %d\n", raw_ucomp_cnt); + + if (raw_ucomp_cnt != 0) { + comprate = (fast_comp_cnt + slow_comp_cnt) + * 100 / raw_ucomp_cnt; + if (debug & VP9_DEBUG_CACHE) + pr_info("DECOMP_COMP_RATIO : %d\n", comprate); + } else { + if (debug & VP9_DEBUG_CACHE) + pr_info("DECOMP_COMP_RATIO : na\n"); + } + return; +} +/* cache_util.c end */ + +/*==================================================== + *======================================================================== + *vp9_prob define + *======================================================================== + */ +#define VP9_PARTITION_START 0 +#define VP9_PARTITION_SIZE_STEP (3 * 4) +#define VP9_PARTITION_ONE_SIZE (4 * VP9_PARTITION_SIZE_STEP) +#define VP9_PARTITION_KEY_START 0 +#define VP9_PARTITION_P_START VP9_PARTITION_ONE_SIZE +#define VP9_PARTITION_SIZE (2 * VP9_PARTITION_ONE_SIZE) +#define VP9_SKIP_START (VP9_PARTITION_START + VP9_PARTITION_SIZE) +#define VP9_SKIP_SIZE 4 /* only use 3*/ +#define VP9_TX_MODE_START (VP9_SKIP_START+VP9_SKIP_SIZE) +#define VP9_TX_MODE_8_0_OFFSET 0 +#define VP9_TX_MODE_8_1_OFFSET 1 +#define VP9_TX_MODE_16_0_OFFSET 2 +#define VP9_TX_MODE_16_1_OFFSET 4 +#define VP9_TX_MODE_32_0_OFFSET 6 +#define VP9_TX_MODE_32_1_OFFSET 9 +#define VP9_TX_MODE_SIZE 12 +#define VP9_COEF_START (VP9_TX_MODE_START+VP9_TX_MODE_SIZE) +#define VP9_COEF_BAND_0_OFFSET 0 +#define VP9_COEF_BAND_1_OFFSET (VP9_COEF_BAND_0_OFFSET + 3 * 3 + 1) +#define VP9_COEF_BAND_2_OFFSET (VP9_COEF_BAND_1_OFFSET + 6 * 3) +#define VP9_COEF_BAND_3_OFFSET (VP9_COEF_BAND_2_OFFSET + 6 * 3) +#define VP9_COEF_BAND_4_OFFSET (VP9_COEF_BAND_3_OFFSET + 6 * 3) +#define VP9_COEF_BAND_5_OFFSET (VP9_COEF_BAND_4_OFFSET + 6 * 3) +#define VP9_COEF_SIZE_ONE_SET 100 /* ((3 +5*6)*3 + 1 padding)*/ +#define VP9_COEF_4X4_START (VP9_COEF_START + 0 * VP9_COEF_SIZE_ONE_SET) +#define VP9_COEF_8X8_START (VP9_COEF_START + 4 * VP9_COEF_SIZE_ONE_SET) +#define VP9_COEF_16X16_START (VP9_COEF_START + 8 * VP9_COEF_SIZE_ONE_SET) +#define VP9_COEF_32X32_START (VP9_COEF_START + 12 * VP9_COEF_SIZE_ONE_SET) +#define VP9_COEF_SIZE_PLANE (2 * VP9_COEF_SIZE_ONE_SET) +#define VP9_COEF_SIZE (4 * 2 * 2 * VP9_COEF_SIZE_ONE_SET) +#define VP9_INTER_MODE_START (VP9_COEF_START+VP9_COEF_SIZE) +#define VP9_INTER_MODE_SIZE 24 /* only use 21 ( #*7)*/ +#define VP9_INTERP_START (VP9_INTER_MODE_START+VP9_INTER_MODE_SIZE) +#define VP9_INTERP_SIZE 8 +#define VP9_INTRA_INTER_START (VP9_INTERP_START+VP9_INTERP_SIZE) +#define VP9_INTRA_INTER_SIZE 4 +#define VP9_INTERP_INTRA_INTER_START VP9_INTERP_START +#define VP9_INTERP_INTRA_INTER_SIZE (VP9_INTERP_SIZE + VP9_INTRA_INTER_SIZE) +#define VP9_COMP_INTER_START \ + (VP9_INTERP_INTRA_INTER_START+VP9_INTERP_INTRA_INTER_SIZE) +#define VP9_COMP_INTER_SIZE 5 +#define VP9_COMP_REF_START (VP9_COMP_INTER_START+VP9_COMP_INTER_SIZE) +#define VP9_COMP_REF_SIZE 5 +#define VP9_SINGLE_REF_START (VP9_COMP_REF_START+VP9_COMP_REF_SIZE) +#define VP9_SINGLE_REF_SIZE 10 +#define VP9_REF_MODE_START VP9_COMP_INTER_START +#define VP9_REF_MODE_SIZE \ + (VP9_COMP_INTER_SIZE+VP9_COMP_REF_SIZE+VP9_SINGLE_REF_SIZE) +#define VP9_IF_Y_MODE_START (VP9_REF_MODE_START+VP9_REF_MODE_SIZE) +#define VP9_IF_Y_MODE_SIZE 36 +#define VP9_IF_UV_MODE_START (VP9_IF_Y_MODE_START+VP9_IF_Y_MODE_SIZE) +#define VP9_IF_UV_MODE_SIZE 92 /* only use 90*/ +#define VP9_MV_JOINTS_START (VP9_IF_UV_MODE_START+VP9_IF_UV_MODE_SIZE) +#define VP9_MV_JOINTS_SIZE 3 +#define VP9_MV_SIGN_0_START (VP9_MV_JOINTS_START+VP9_MV_JOINTS_SIZE) +#define VP9_MV_SIGN_0_SIZE 1 +#define VP9_MV_CLASSES_0_START (VP9_MV_SIGN_0_START+VP9_MV_SIGN_0_SIZE) +#define VP9_MV_CLASSES_0_SIZE 10 +#define VP9_MV_CLASS0_0_START (VP9_MV_CLASSES_0_START+VP9_MV_CLASSES_0_SIZE) +#define VP9_MV_CLASS0_0_SIZE 1 +#define VP9_MV_BITS_0_START (VP9_MV_CLASS0_0_START+VP9_MV_CLASS0_0_SIZE) +#define VP9_MV_BITS_0_SIZE 10 +#define VP9_MV_SIGN_1_START (VP9_MV_BITS_0_START+VP9_MV_BITS_0_SIZE) +#define VP9_MV_SIGN_1_SIZE 1 +#define VP9_MV_CLASSES_1_START \ + (VP9_MV_SIGN_1_START+VP9_MV_SIGN_1_SIZE) +#define VP9_MV_CLASSES_1_SIZE 10 +#define VP9_MV_CLASS0_1_START \ + (VP9_MV_CLASSES_1_START+VP9_MV_CLASSES_1_SIZE) +#define VP9_MV_CLASS0_1_SIZE 1 +#define VP9_MV_BITS_1_START \ + (VP9_MV_CLASS0_1_START+VP9_MV_CLASS0_1_SIZE) +#define VP9_MV_BITS_1_SIZE 10 +#define VP9_MV_CLASS0_FP_0_START \ + (VP9_MV_BITS_1_START+VP9_MV_BITS_1_SIZE) +#define VP9_MV_CLASS0_FP_0_SIZE 9 +#define VP9_MV_CLASS0_FP_1_START \ + (VP9_MV_CLASS0_FP_0_START+VP9_MV_CLASS0_FP_0_SIZE) +#define VP9_MV_CLASS0_FP_1_SIZE 9 +#define VP9_MV_CLASS0_HP_0_START \ + (VP9_MV_CLASS0_FP_1_START+VP9_MV_CLASS0_FP_1_SIZE) +#define VP9_MV_CLASS0_HP_0_SIZE 2 +#define VP9_MV_CLASS0_HP_1_START \ + (VP9_MV_CLASS0_HP_0_START+VP9_MV_CLASS0_HP_0_SIZE) +#define VP9_MV_CLASS0_HP_1_SIZE 2 +#define VP9_MV_START VP9_MV_JOINTS_START +#define VP9_MV_SIZE 72 /*only use 69*/ + +#define VP9_TOTAL_SIZE (VP9_MV_START + VP9_MV_SIZE) + + +/*======================================================================== + * vp9_count_mem define + *======================================================================== + */ +#define VP9_COEF_COUNT_START 0 +#define VP9_COEF_COUNT_BAND_0_OFFSET 0 +#define VP9_COEF_COUNT_BAND_1_OFFSET \ + (VP9_COEF_COUNT_BAND_0_OFFSET + 3*5) +#define VP9_COEF_COUNT_BAND_2_OFFSET \ + (VP9_COEF_COUNT_BAND_1_OFFSET + 6*5) +#define VP9_COEF_COUNT_BAND_3_OFFSET \ + (VP9_COEF_COUNT_BAND_2_OFFSET + 6*5) +#define VP9_COEF_COUNT_BAND_4_OFFSET \ + (VP9_COEF_COUNT_BAND_3_OFFSET + 6*5) +#define VP9_COEF_COUNT_BAND_5_OFFSET \ + (VP9_COEF_COUNT_BAND_4_OFFSET + 6*5) +#define VP9_COEF_COUNT_SIZE_ONE_SET 165 /* ((3 +5*6)*5 */ +#define VP9_COEF_COUNT_4X4_START \ + (VP9_COEF_COUNT_START + 0*VP9_COEF_COUNT_SIZE_ONE_SET) +#define VP9_COEF_COUNT_8X8_START \ + (VP9_COEF_COUNT_START + 4*VP9_COEF_COUNT_SIZE_ONE_SET) +#define VP9_COEF_COUNT_16X16_START \ + (VP9_COEF_COUNT_START + 8*VP9_COEF_COUNT_SIZE_ONE_SET) +#define VP9_COEF_COUNT_32X32_START \ + (VP9_COEF_COUNT_START + 12*VP9_COEF_COUNT_SIZE_ONE_SET) +#define VP9_COEF_COUNT_SIZE_PLANE (2 * VP9_COEF_COUNT_SIZE_ONE_SET) +#define VP9_COEF_COUNT_SIZE (4 * 2 * 2 * VP9_COEF_COUNT_SIZE_ONE_SET) + +#define VP9_INTRA_INTER_COUNT_START \ + (VP9_COEF_COUNT_START+VP9_COEF_COUNT_SIZE) +#define VP9_INTRA_INTER_COUNT_SIZE (4*2) +#define VP9_COMP_INTER_COUNT_START \ + (VP9_INTRA_INTER_COUNT_START+VP9_INTRA_INTER_COUNT_SIZE) +#define VP9_COMP_INTER_COUNT_SIZE (5*2) +#define VP9_COMP_REF_COUNT_START \ + (VP9_COMP_INTER_COUNT_START+VP9_COMP_INTER_COUNT_SIZE) +#define VP9_COMP_REF_COUNT_SIZE (5*2) +#define VP9_SINGLE_REF_COUNT_START \ + (VP9_COMP_REF_COUNT_START+VP9_COMP_REF_COUNT_SIZE) +#define VP9_SINGLE_REF_COUNT_SIZE (10*2) +#define VP9_TX_MODE_COUNT_START \ + (VP9_SINGLE_REF_COUNT_START+VP9_SINGLE_REF_COUNT_SIZE) +#define VP9_TX_MODE_COUNT_SIZE (12*2) +#define VP9_SKIP_COUNT_START \ + (VP9_TX_MODE_COUNT_START+VP9_TX_MODE_COUNT_SIZE) +#define VP9_SKIP_COUNT_SIZE (3*2) +#define VP9_MV_SIGN_0_COUNT_START \ + (VP9_SKIP_COUNT_START+VP9_SKIP_COUNT_SIZE) +#define VP9_MV_SIGN_0_COUNT_SIZE (1*2) +#define VP9_MV_SIGN_1_COUNT_START \ + (VP9_MV_SIGN_0_COUNT_START+VP9_MV_SIGN_0_COUNT_SIZE) +#define VP9_MV_SIGN_1_COUNT_SIZE (1*2) +#define VP9_MV_BITS_0_COUNT_START \ + (VP9_MV_SIGN_1_COUNT_START+VP9_MV_SIGN_1_COUNT_SIZE) +#define VP9_MV_BITS_0_COUNT_SIZE (10*2) +#define VP9_MV_BITS_1_COUNT_START \ + (VP9_MV_BITS_0_COUNT_START+VP9_MV_BITS_0_COUNT_SIZE) +#define VP9_MV_BITS_1_COUNT_SIZE (10*2) +#define VP9_MV_CLASS0_HP_0_COUNT_START \ + (VP9_MV_BITS_1_COUNT_START+VP9_MV_BITS_1_COUNT_SIZE) +#define VP9_MV_CLASS0_HP_0_COUNT_SIZE (2*2) +#define VP9_MV_CLASS0_HP_1_COUNT_START \ + (VP9_MV_CLASS0_HP_0_COUNT_START+VP9_MV_CLASS0_HP_0_COUNT_SIZE) +#define VP9_MV_CLASS0_HP_1_COUNT_SIZE (2*2) +/* Start merge_tree*/ +#define VP9_INTER_MODE_COUNT_START \ + (VP9_MV_CLASS0_HP_1_COUNT_START+VP9_MV_CLASS0_HP_1_COUNT_SIZE) +#define VP9_INTER_MODE_COUNT_SIZE (7*4) +#define VP9_IF_Y_MODE_COUNT_START \ + (VP9_INTER_MODE_COUNT_START+VP9_INTER_MODE_COUNT_SIZE) +#define VP9_IF_Y_MODE_COUNT_SIZE (10*4) +#define VP9_IF_UV_MODE_COUNT_START \ + (VP9_IF_Y_MODE_COUNT_START+VP9_IF_Y_MODE_COUNT_SIZE) +#define VP9_IF_UV_MODE_COUNT_SIZE (10*10) +#define VP9_PARTITION_P_COUNT_START \ + (VP9_IF_UV_MODE_COUNT_START+VP9_IF_UV_MODE_COUNT_SIZE) +#define VP9_PARTITION_P_COUNT_SIZE (4*4*4) +#define VP9_INTERP_COUNT_START \ + (VP9_PARTITION_P_COUNT_START+VP9_PARTITION_P_COUNT_SIZE) +#define VP9_INTERP_COUNT_SIZE (4*3) +#define VP9_MV_JOINTS_COUNT_START \ + (VP9_INTERP_COUNT_START+VP9_INTERP_COUNT_SIZE) +#define VP9_MV_JOINTS_COUNT_SIZE (1 * 4) +#define VP9_MV_CLASSES_0_COUNT_START \ + (VP9_MV_JOINTS_COUNT_START+VP9_MV_JOINTS_COUNT_SIZE) +#define VP9_MV_CLASSES_0_COUNT_SIZE (1*11) +#define VP9_MV_CLASS0_0_COUNT_START \ + (VP9_MV_CLASSES_0_COUNT_START+VP9_MV_CLASSES_0_COUNT_SIZE) +#define VP9_MV_CLASS0_0_COUNT_SIZE (1*2) +#define VP9_MV_CLASSES_1_COUNT_START \ + (VP9_MV_CLASS0_0_COUNT_START+VP9_MV_CLASS0_0_COUNT_SIZE) +#define VP9_MV_CLASSES_1_COUNT_SIZE (1*11) +#define VP9_MV_CLASS0_1_COUNT_START \ + (VP9_MV_CLASSES_1_COUNT_START+VP9_MV_CLASSES_1_COUNT_SIZE) +#define VP9_MV_CLASS0_1_COUNT_SIZE (1*2) +#define VP9_MV_CLASS0_FP_0_COUNT_START \ + (VP9_MV_CLASS0_1_COUNT_START+VP9_MV_CLASS0_1_COUNT_SIZE) +#define VP9_MV_CLASS0_FP_0_COUNT_SIZE (3*4) +#define VP9_MV_CLASS0_FP_1_COUNT_START \ + (VP9_MV_CLASS0_FP_0_COUNT_START+VP9_MV_CLASS0_FP_0_COUNT_SIZE) +#define VP9_MV_CLASS0_FP_1_COUNT_SIZE (3*4) + + +#define DC_PRED 0 /* Average of above and left pixels*/ +#define V_PRED 1 /* Vertical*/ +#define H_PRED 2 /* Horizontal*/ +#define D45_PRED 3 /*Directional 45 deg = round(arctan(1/1) * 180/pi)*/ +#define D135_PRED 4 /* Directional 135 deg = 180 - 45*/ +#define D117_PRED 5 /* Directional 117 deg = 180 - 63*/ +#define D153_PRED 6 /* Directional 153 deg = 180 - 27*/ +#define D207_PRED 7 /* Directional 207 deg = 180 + 27*/ +#define D63_PRED 8 /*Directional 63 deg = round(arctan(2/1) * 180/pi)*/ +#define TM_PRED 9 /*True-motion*/ + +int clip_prob(int p) +{ + return (p > 255) ? 255 : (p < 1) ? 1 : p; +} + +#define ROUND_POWER_OF_TWO(value, n) \ + (((value) + (1 << ((n) - 1))) >> (n)) + +#define MODE_MV_COUNT_SAT 20 +static const int count_to_update_factor[MODE_MV_COUNT_SAT + 1] = { + 0, 6, 12, 19, 25, 32, 38, 44, 51, 57, 64, + 70, 76, 83, 89, 96, 102, 108, 115, 121, 128 +}; + +void vp9_tree_merge_probs(unsigned int *prev_prob, unsigned int *cur_prob, + int coef_node_start, int tree_left, int tree_right, int tree_i, + int node) { + + int prob_32, prob_res, prob_shift; + int pre_prob, new_prob; + int den, m_count, get_prob, factor; + + prob_32 = prev_prob[coef_node_start / 4 * 2]; + prob_res = coef_node_start & 3; + prob_shift = prob_res * 8; + pre_prob = (prob_32 >> prob_shift) & 0xff; + + den = tree_left + tree_right; + + if (den == 0) + new_prob = pre_prob; + else { + m_count = (den < MODE_MV_COUNT_SAT) ? + den : MODE_MV_COUNT_SAT; + get_prob = clip_prob( + div_r32(((int64_t)tree_left * 256 + (den >> 1)), + den)); + /*weighted_prob*/ + factor = count_to_update_factor[m_count]; + new_prob = ROUND_POWER_OF_TWO(pre_prob * (256 - factor) + + get_prob * factor, 8); + } + cur_prob[coef_node_start / 4 * 2] = (cur_prob[coef_node_start / 4 * 2] + & (~(0xff << prob_shift))) | (new_prob << prob_shift); + + /*pr_info(" - [%d][%d] 0x%02X --> 0x%02X (0x%X 0x%X) (%X)\n", + *tree_i, node, pre_prob, new_prob, tree_left, tree_right, + *cur_prob[coef_node_start/4*2]); + */ +} + + +/*void adapt_coef_probs(void)*/ +void adapt_coef_probs(int pic_count, int prev_kf, int cur_kf, int pre_fc, + unsigned int *prev_prob, unsigned int *cur_prob, unsigned int *count) +{ + /* 80 * 64bits = 0xF00 ( use 0x1000 4K bytes) + *unsigned int prev_prob[496*2]; + *unsigned int cur_prob[496*2]; + *0x300 * 128bits = 0x3000 (32K Bytes) + *unsigned int count[0x300*4]; + */ + + int tx_size, coef_tx_size_start, coef_count_tx_size_start; + int plane, coef_plane_start, coef_count_plane_start; + int type, coef_type_start, coef_count_type_start; + int band, coef_band_start, coef_count_band_start; + int cxt_num; + int cxt, coef_cxt_start, coef_count_cxt_start; + int node, coef_node_start, coef_count_node_start; + + int tree_i, tree_left, tree_right; + int mvd_i; + + int count_sat = 24; + /*int update_factor = 112;*/ /*If COEF_MAX_UPDATE_FACTOR_AFTER_KEY, + *use 128 + */ + /* If COEF_MAX_UPDATE_FACTOR_AFTER_KEY, use 128*/ + /*int update_factor = (pic_count == 1) ? 128 : 112;*/ + int update_factor = cur_kf ? 112 : + prev_kf ? 128 : 112; + + int prob_32; + int prob_res; + int prob_shift; + int pre_prob; + + int num, den; + int get_prob; + int m_count; + int factor; + + int new_prob; + + if (debug & VP9_DEBUG_MERGE) + pr_info + ("\n ##adapt_coef_probs (pre_fc : %d ,prev_kf : %d,cur_kf : %d)##\n\n", + pre_fc, prev_kf, cur_kf); + + /*adapt_coef_probs*/ + for (tx_size = 0; tx_size < 4; tx_size++) { + coef_tx_size_start = VP9_COEF_START + + tx_size * 4 * VP9_COEF_SIZE_ONE_SET; + coef_count_tx_size_start = VP9_COEF_COUNT_START + + tx_size * 4 * VP9_COEF_COUNT_SIZE_ONE_SET; + coef_plane_start = coef_tx_size_start; + coef_count_plane_start = coef_count_tx_size_start; + for (plane = 0; plane < 2; plane++) { + coef_type_start = coef_plane_start; + coef_count_type_start = coef_count_plane_start; + for (type = 0; type < 2; type++) { + coef_band_start = coef_type_start; + coef_count_band_start = coef_count_type_start; + for (band = 0; band < 6; band++) { + if (band == 0) + cxt_num = 3; + else + cxt_num = 6; + coef_cxt_start = coef_band_start; + coef_count_cxt_start = + coef_count_band_start; + for (cxt = 0; cxt < cxt_num; cxt++) { + const int n0 = + count[coef_count_cxt_start]; + const int n1 = + count[coef_count_cxt_start + 1]; + const int n2 = + count[coef_count_cxt_start + 2]; + const int neob = + count[coef_count_cxt_start + 3]; + const int nneob = + count[coef_count_cxt_start + 4]; + const unsigned int + branch_ct[3][2] = { + { neob, nneob }, + { n0, n1 + n2 }, + { n1, n2 } + }; + coef_node_start = + coef_cxt_start; + for + (node = 0; node < 3; node++) { + prob_32 = + prev_prob[ + coef_node_start + / 4 * 2]; + prob_res = + coef_node_start & 3; + prob_shift = + prob_res * 8; + pre_prob = + (prob_32 >> prob_shift) + & 0xff; + + /*get_binary_prob*/ + num = + branch_ct[node][0]; + den = + branch_ct[node][0] + + branch_ct[node][1]; + m_count = (den < + count_sat) + ? den : count_sat; + + get_prob = + (den == 0) ? 128u : + clip_prob( + div_r32(((int64_t) + num * 256 + + (den >> 1)), + den)); + + factor = + update_factor * m_count + / count_sat; + new_prob = + ROUND_POWER_OF_TWO + (pre_prob * + (256 - factor) + + get_prob * factor, 8); + + cur_prob[coef_node_start + / 4 * 2] = + (cur_prob + [coef_node_start + / 4 * 2] & (~(0xff << + prob_shift))) | + (new_prob << + prob_shift); + + coef_node_start += 1; + } + + coef_cxt_start = + coef_cxt_start + 3; + coef_count_cxt_start = + coef_count_cxt_start + + 5; + } + if (band == 0) { + coef_band_start += 10; + coef_count_band_start += 15; + } else { + coef_band_start += 18; + coef_count_band_start += 30; + } + } + coef_type_start += VP9_COEF_SIZE_ONE_SET; + coef_count_type_start += + VP9_COEF_COUNT_SIZE_ONE_SET; + } + coef_plane_start += 2 * VP9_COEF_SIZE_ONE_SET; + coef_count_plane_start += + 2 * VP9_COEF_COUNT_SIZE_ONE_SET; + } + } + + if (cur_kf == 0) { + /*mode_mv_merge_probs - merge_intra_inter_prob*/ + for (coef_count_node_start = VP9_INTRA_INTER_COUNT_START; + coef_count_node_start < (VP9_MV_CLASS0_HP_1_COUNT_START + + VP9_MV_CLASS0_HP_1_COUNT_SIZE); coef_count_node_start += 2) { + + if (coef_count_node_start == + VP9_INTRA_INTER_COUNT_START) { + if (debug & VP9_DEBUG_MERGE) + pr_info(" # merge_intra_inter_prob\n"); + coef_node_start = VP9_INTRA_INTER_START; + } else if (coef_count_node_start == + VP9_COMP_INTER_COUNT_START) { + if (debug & VP9_DEBUG_MERGE) + pr_info(" # merge_comp_inter_prob\n"); + coef_node_start = VP9_COMP_INTER_START; + } + /* + *else if (coef_count_node_start == + * VP9_COMP_REF_COUNT_START) { + * pr_info(" # merge_comp_inter_prob\n"); + * coef_node_start = VP9_COMP_REF_START; + *} + *else if (coef_count_node_start == + * VP9_SINGLE_REF_COUNT_START) { + * pr_info(" # merge_comp_inter_prob\n"); + * coef_node_start = VP9_SINGLE_REF_START; + *} + */ + else if (coef_count_node_start == + VP9_TX_MODE_COUNT_START) { + if (debug & VP9_DEBUG_MERGE) + pr_info(" # merge_tx_mode_probs\n"); + coef_node_start = VP9_TX_MODE_START; + } else if (coef_count_node_start == + VP9_SKIP_COUNT_START) { + if (debug & VP9_DEBUG_MERGE) + pr_info(" # merge_skip_probs\n"); + coef_node_start = VP9_SKIP_START; + } else if (coef_count_node_start == + VP9_MV_SIGN_0_COUNT_START) { + if (debug & VP9_DEBUG_MERGE) + pr_info(" # merge_sign_0\n"); + coef_node_start = VP9_MV_SIGN_0_START; + } else if (coef_count_node_start == + VP9_MV_SIGN_1_COUNT_START) { + if (debug & VP9_DEBUG_MERGE) + pr_info(" # merge_sign_1\n"); + coef_node_start = VP9_MV_SIGN_1_START; + } else if (coef_count_node_start == + VP9_MV_BITS_0_COUNT_START) { + if (debug & VP9_DEBUG_MERGE) + pr_info(" # merge_bits_0\n"); + coef_node_start = VP9_MV_BITS_0_START; + } else if (coef_count_node_start == + VP9_MV_BITS_1_COUNT_START) { + if (debug & VP9_DEBUG_MERGE) + pr_info(" # merge_bits_1\n"); + coef_node_start = VP9_MV_BITS_1_START; + } else if (coef_count_node_start == + VP9_MV_CLASS0_HP_0_COUNT_START) { + if (debug & VP9_DEBUG_MERGE) + pr_info(" # merge_class0_hp\n"); + coef_node_start = VP9_MV_CLASS0_HP_0_START; + } + + + den = count[coef_count_node_start] + + count[coef_count_node_start + 1]; + + prob_32 = prev_prob[coef_node_start / 4 * 2]; + prob_res = coef_node_start & 3; + prob_shift = prob_res * 8; + pre_prob = (prob_32 >> prob_shift) & 0xff; + + if (den == 0) + new_prob = pre_prob; + else { + m_count = (den < MODE_MV_COUNT_SAT) ? + den : MODE_MV_COUNT_SAT; + get_prob = + clip_prob( + div_r32(((int64_t)count[coef_count_node_start] + * 256 + (den >> 1)), + den)); + /*weighted_prob*/ + factor = count_to_update_factor[m_count]; + new_prob = + ROUND_POWER_OF_TWO(pre_prob * (256 - factor) + + get_prob * factor, 8); + } + cur_prob[coef_node_start / 4 * 2] = + (cur_prob[coef_node_start / 4 * 2] & + (~(0xff << prob_shift))) + | (new_prob << prob_shift); + + coef_node_start = coef_node_start + 1; + } + if (debug & VP9_DEBUG_MERGE) + pr_info(" # merge_vp9_inter_mode_tree\n"); + coef_node_start = VP9_INTER_MODE_START; + coef_count_node_start = VP9_INTER_MODE_COUNT_START; + for (tree_i = 0; tree_i < 7; tree_i++) { + for (node = 0; node < 3; node++) { + switch (node) { + case 2: + tree_left = + count[coef_count_node_start + 1]; + tree_right = + count[coef_count_node_start + 3]; + break; + case 1: + tree_left = + count[coef_count_node_start + 0]; + tree_right = + count[coef_count_node_start + 1] + + count[coef_count_node_start + 3]; + break; + default: + tree_left = + count[coef_count_node_start + 2]; + tree_right = + count[coef_count_node_start + 0] + + count[coef_count_node_start + 1] + + count[coef_count_node_start + 3]; + break; + + } + + vp9_tree_merge_probs(prev_prob, cur_prob, + coef_node_start, tree_left, tree_right, + tree_i, node); + + coef_node_start = coef_node_start + 1; + } + coef_count_node_start = coef_count_node_start + 4; + } + if (debug & VP9_DEBUG_MERGE) + pr_info(" # merge_vp9_intra_mode_tree\n"); + coef_node_start = VP9_IF_Y_MODE_START; + coef_count_node_start = VP9_IF_Y_MODE_COUNT_START; + for (tree_i = 0; tree_i < 14; tree_i++) { + for (node = 0; node < 9; node++) { + switch (node) { + case 8: + tree_left = + count[coef_count_node_start+D153_PRED]; + tree_right = + count[coef_count_node_start+D207_PRED]; + break; + case 7: + tree_left = + count[coef_count_node_start+D63_PRED]; + tree_right = + count[coef_count_node_start+D207_PRED] + + count[coef_count_node_start+D153_PRED]; + break; + case 6: + tree_left = + count[coef_count_node_start + D45_PRED]; + tree_right = + count[coef_count_node_start+D207_PRED] + + count[coef_count_node_start+D153_PRED] + + count[coef_count_node_start+D63_PRED]; + break; + case 5: + tree_left = + count[coef_count_node_start+D135_PRED]; + tree_right = + count[coef_count_node_start+D117_PRED]; + break; + case 4: + tree_left = + count[coef_count_node_start+H_PRED]; + tree_right = + count[coef_count_node_start+D117_PRED] + + count[coef_count_node_start+D135_PRED]; + break; + case 3: + tree_left = + count[coef_count_node_start+H_PRED] + + count[coef_count_node_start+D117_PRED] + + count[coef_count_node_start+D135_PRED]; + tree_right = + count[coef_count_node_start+D45_PRED] + + count[coef_count_node_start+D207_PRED] + + count[coef_count_node_start+D153_PRED] + + count[coef_count_node_start+D63_PRED]; + break; + case 2: + tree_left = + count[coef_count_node_start+V_PRED]; + tree_right = + count[coef_count_node_start+H_PRED] + + count[coef_count_node_start+D117_PRED] + + count[coef_count_node_start+D135_PRED] + + count[coef_count_node_start+D45_PRED] + + count[coef_count_node_start+D207_PRED] + + count[coef_count_node_start+D153_PRED] + + count[coef_count_node_start+D63_PRED]; + break; + case 1: + tree_left = + count[coef_count_node_start+TM_PRED]; + tree_right = + count[coef_count_node_start+V_PRED] + + count[coef_count_node_start+H_PRED] + + count[coef_count_node_start+D117_PRED] + + count[coef_count_node_start+D135_PRED] + + count[coef_count_node_start+D45_PRED] + + count[coef_count_node_start+D207_PRED] + + count[coef_count_node_start+D153_PRED] + + count[coef_count_node_start+D63_PRED]; + break; + default: + tree_left = + count[coef_count_node_start+DC_PRED]; + tree_right = + count[coef_count_node_start+TM_PRED] + + count[coef_count_node_start+V_PRED] + + count[coef_count_node_start+H_PRED] + + count[coef_count_node_start+D117_PRED] + + count[coef_count_node_start+D135_PRED] + + count[coef_count_node_start+D45_PRED] + + count[coef_count_node_start+D207_PRED] + + count[coef_count_node_start+D153_PRED] + + count[coef_count_node_start+D63_PRED]; + break; + + } + + vp9_tree_merge_probs(prev_prob, cur_prob, + coef_node_start, tree_left, tree_right, + tree_i, node); + + coef_node_start = coef_node_start + 1; + } + coef_count_node_start = coef_count_node_start + 10; + } + + if (debug & VP9_DEBUG_MERGE) + pr_info(" # merge_vp9_partition_tree\n"); + coef_node_start = VP9_PARTITION_P_START; + coef_count_node_start = VP9_PARTITION_P_COUNT_START; + for (tree_i = 0; tree_i < 16; tree_i++) { + for (node = 0; node < 3; node++) { + switch (node) { + case 2: + tree_left = + count[coef_count_node_start + 2]; + tree_right = + count[coef_count_node_start + 3]; + break; + case 1: + tree_left = + count[coef_count_node_start + 1]; + tree_right = + count[coef_count_node_start + 2] + + count[coef_count_node_start + 3]; + break; + default: + tree_left = + count[coef_count_node_start + 0]; + tree_right = + count[coef_count_node_start + 1] + + count[coef_count_node_start + 2] + + count[coef_count_node_start + 3]; + break; + + } + + vp9_tree_merge_probs(prev_prob, cur_prob, + coef_node_start, + tree_left, tree_right, tree_i, node); + + coef_node_start = coef_node_start + 1; + } + coef_count_node_start = coef_count_node_start + 4; + } + + if (debug & VP9_DEBUG_MERGE) + pr_info(" # merge_vp9_switchable_interp_tree\n"); + coef_node_start = VP9_INTERP_START; + coef_count_node_start = VP9_INTERP_COUNT_START; + for (tree_i = 0; tree_i < 4; tree_i++) { + for (node = 0; node < 2; node++) { + switch (node) { + case 1: + tree_left = + count[coef_count_node_start + 1]; + tree_right = + count[coef_count_node_start + 2]; + break; + default: + tree_left = + count[coef_count_node_start + 0]; + tree_right = + count[coef_count_node_start + 1] + + count[coef_count_node_start + 2]; + break; + + } + + vp9_tree_merge_probs(prev_prob, cur_prob, + coef_node_start, + tree_left, tree_right, tree_i, node); + + coef_node_start = coef_node_start + 1; + } + coef_count_node_start = coef_count_node_start + 3; + } + + if (debug & VP9_DEBUG_MERGE) + pr_info("# merge_vp9_mv_joint_tree\n"); + coef_node_start = VP9_MV_JOINTS_START; + coef_count_node_start = VP9_MV_JOINTS_COUNT_START; + for (tree_i = 0; tree_i < 1; tree_i++) { + for (node = 0; node < 3; node++) { + switch (node) { + case 2: + tree_left = + count[coef_count_node_start + 2]; + tree_right = + count[coef_count_node_start + 3]; + break; + case 1: + tree_left = + count[coef_count_node_start + 1]; + tree_right = + count[coef_count_node_start + 2] + + count[coef_count_node_start + 3]; + break; + default: + tree_left = + count[coef_count_node_start + 0]; + tree_right = + count[coef_count_node_start + 1] + + count[coef_count_node_start + 2] + + count[coef_count_node_start + 3]; + break; + } + + vp9_tree_merge_probs(prev_prob, cur_prob, + coef_node_start, + tree_left, tree_right, tree_i, node); + + coef_node_start = coef_node_start + 1; + } + coef_count_node_start = coef_count_node_start + 4; + } + + for (mvd_i = 0; mvd_i < 2; mvd_i++) { + if (debug & VP9_DEBUG_MERGE) + pr_info(" # merge_vp9_mv_class_tree [%d] -\n", mvd_i); + coef_node_start = + mvd_i ? VP9_MV_CLASSES_1_START : VP9_MV_CLASSES_0_START; + coef_count_node_start = + mvd_i ? VP9_MV_CLASSES_1_COUNT_START + : VP9_MV_CLASSES_0_COUNT_START; + tree_i = 0; + for (node = 0; node < 10; node++) { + switch (node) { + case 9: + tree_left = + count[coef_count_node_start + 9]; + tree_right = + count[coef_count_node_start + 10]; + break; + case 8: + tree_left = + count[coef_count_node_start + 7]; + tree_right = + count[coef_count_node_start + 8]; + break; + case 7: + tree_left = + count[coef_count_node_start + 7] + + count[coef_count_node_start + 8]; + tree_right = + count[coef_count_node_start + 9] + + count[coef_count_node_start + 10]; + break; + case 6: + tree_left = + count[coef_count_node_start + 6]; + tree_right = + count[coef_count_node_start + 7] + + count[coef_count_node_start + 8] + + count[coef_count_node_start + 9] + + count[coef_count_node_start + 10]; + break; + case 5: + tree_left = + count[coef_count_node_start + 4]; + tree_right = + count[coef_count_node_start + 5]; + break; + case 4: + tree_left = + count[coef_count_node_start + 4] + + count[coef_count_node_start + 5]; + tree_right = + count[coef_count_node_start + 6] + + count[coef_count_node_start + 7] + + count[coef_count_node_start + 8] + + count[coef_count_node_start + 9] + + count[coef_count_node_start + 10]; + break; + case 3: + tree_left = + count[coef_count_node_start + 2]; + tree_right = + count[coef_count_node_start + 3]; + break; + case 2: + tree_left = + count[coef_count_node_start + 2] + + count[coef_count_node_start + 3]; + tree_right = + count[coef_count_node_start + 4] + + count[coef_count_node_start + 5] + + count[coef_count_node_start + 6] + + count[coef_count_node_start + 7] + + count[coef_count_node_start + 8] + + count[coef_count_node_start + 9] + + count[coef_count_node_start + 10]; + break; + case 1: + tree_left = + count[coef_count_node_start + 1]; + tree_right = + count[coef_count_node_start + 2] + + count[coef_count_node_start + 3] + + count[coef_count_node_start + 4] + + count[coef_count_node_start + 5] + + count[coef_count_node_start + 6] + + count[coef_count_node_start + 7] + + count[coef_count_node_start + 8] + + count[coef_count_node_start + 9] + + count[coef_count_node_start + 10]; + break; + default: + tree_left = + count[coef_count_node_start + 0]; + tree_right = + count[coef_count_node_start + 1] + + count[coef_count_node_start + 2] + + count[coef_count_node_start + 3] + + count[coef_count_node_start + 4] + + count[coef_count_node_start + 5] + + count[coef_count_node_start + 6] + + count[coef_count_node_start + 7] + + count[coef_count_node_start + 8] + + count[coef_count_node_start + 9] + + count[coef_count_node_start + 10]; + break; + + } + + vp9_tree_merge_probs(prev_prob, cur_prob, + coef_node_start, tree_left, tree_right, + tree_i, node); + + coef_node_start = coef_node_start + 1; + } + + if (debug & VP9_DEBUG_MERGE) + pr_info(" # merge_vp9_mv_class0_tree [%d] -\n", mvd_i); + coef_node_start = + mvd_i ? VP9_MV_CLASS0_1_START : VP9_MV_CLASS0_0_START; + coef_count_node_start = + mvd_i ? VP9_MV_CLASS0_1_COUNT_START : + VP9_MV_CLASS0_0_COUNT_START; + tree_i = 0; + node = 0; + tree_left = count[coef_count_node_start + 0]; + tree_right = count[coef_count_node_start + 1]; + + vp9_tree_merge_probs(prev_prob, cur_prob, coef_node_start, + tree_left, tree_right, tree_i, node); + if (debug & VP9_DEBUG_MERGE) + pr_info(" # merge_vp9_mv_fp_tree_class0_fp [%d] -\n", + mvd_i); + coef_node_start = + mvd_i ? VP9_MV_CLASS0_FP_1_START : + VP9_MV_CLASS0_FP_0_START; + coef_count_node_start = + mvd_i ? VP9_MV_CLASS0_FP_1_COUNT_START : + VP9_MV_CLASS0_FP_0_COUNT_START; + for (tree_i = 0; tree_i < 3; tree_i++) { + for (node = 0; node < 3; node++) { + switch (node) { + case 2: + tree_left = + count[coef_count_node_start + 2]; + tree_right = + count[coef_count_node_start + 3]; + break; + case 1: + tree_left = + count[coef_count_node_start + 1]; + tree_right = + count[coef_count_node_start + 2] + + count[coef_count_node_start + 3]; + break; + default: + tree_left = + count[coef_count_node_start + 0]; + tree_right = + count[coef_count_node_start + 1] + + count[coef_count_node_start + 2] + + count[coef_count_node_start + 3]; + break; + + } + + vp9_tree_merge_probs(prev_prob, cur_prob, + coef_node_start, tree_left, tree_right, + tree_i, node); + + coef_node_start = coef_node_start + 1; + } + coef_count_node_start = coef_count_node_start + 4; + } + + } /* for mvd_i (mvd_y or mvd_x)*/ +} + +} + + +static void uninit_mmu_buffers(struct VP9Decoder_s *pbi) +{ +#ifndef MV_USE_FIXED_BUF + dealloc_mv_bufs(pbi); +#endif + decoder_mmu_box_free(pbi->mmu_box); + pbi->mmu_box = NULL; + + if (pbi->bmmu_box) + decoder_bmmu_box_free(pbi->bmmu_box); + pbi->bmmu_box = NULL; +} + +#ifndef VP9_10B_MMU +static void init_buf_list(struct VP9Decoder_s *pbi) +{ + int i; + int buf_size; +#ifndef VP9_10B_MMU + int mc_buffer_end = pbi->mc_buf->buf_start + pbi->mc_buf->buf_size; +#endif + pbi->used_buf_num = max_buf_num; + + if (pbi->used_buf_num > MAX_BUF_NUM) + pbi->used_buf_num = MAX_BUF_NUM; + if (buf_alloc_size > 0) { + buf_size = buf_alloc_size; + if (debug) + pr_info("[Buffer Management] init_buf_list:\n"); + } else { + int pic_width = pbi->init_pic_w; + int pic_height = pbi->init_pic_h; + + /*SUPPORT_10BIT*/ + int losless_comp_header_size = compute_losless_comp_header_size + (pic_width, pic_height); + int losless_comp_body_size = compute_losless_comp_body_size + (pic_width, pic_height, buf_alloc_depth == 10); + int mc_buffer_size = losless_comp_header_size + + losless_comp_body_size; + int mc_buffer_size_h = (mc_buffer_size + 0xffff)>>16; + + int dw_mode = get_double_write_mode_init(pbi); + + if (dw_mode) { + int pic_width_dw = pic_width / + get_double_write_ratio(pbi, dw_mode); + int pic_height_dw = pic_height / + get_double_write_ratio(pbi, dw_mode); + int lcu_size = 64; /*fixed 64*/ + int pic_width_64 = (pic_width_dw + 63) & (~0x3f); + int pic_height_32 = (pic_height_dw + 31) & (~0x1f); + int pic_width_lcu = + (pic_width_64 % lcu_size) ? pic_width_64 / lcu_size + + 1 : pic_width_64 / lcu_size; + int pic_height_lcu = + (pic_height_32 % lcu_size) ? pic_height_32 / lcu_size + + 1 : pic_height_32 / lcu_size; + int lcu_total = pic_width_lcu * pic_height_lcu; + int mc_buffer_size_u_v = lcu_total * lcu_size * lcu_size / 2; + int mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16; + /*64k alignment*/ + buf_size = ((mc_buffer_size_u_v_h << 16) * 3); + } else + buf_size = 0; + + if (mc_buffer_size & 0xffff) { /*64k alignment*/ + mc_buffer_size_h += 1; + } + if ((dw_mode & 0x10) == 0) + buf_size += (mc_buffer_size_h << 16); + if (debug) { + pr_info + ("init_buf_list num %d (width %d height %d):\n", + pbi->used_buf_num, pic_width, pic_height); + } + } + + for (i = 0; i < pbi->used_buf_num; i++) { + if (((i + 1) * buf_size) > pbi->mc_buf->buf_size) + pbi->use_cma_flag = 1; +#ifndef VP9_10B_MMU + pbi->m_BUF[i].alloc_flag = 0; + pbi->m_BUF[i].index = i; + + pbi->use_cma_flag = 1; + if (pbi->use_cma_flag) { + pbi->m_BUF[i].cma_page_count = + PAGE_ALIGN(buf_size) / PAGE_SIZE; + if (decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, + VF_BUFFER_IDX(i), buf_size, DRIVER_NAME, + &pbi->m_BUF[i].alloc_addr) < 0) { + pbi->m_BUF[i].cma_page_count = 0; + if (i <= 5) { + pbi->fatal_error |= + DECODER_FATAL_ERROR_NO_MEM; + } + break; + } + pbi->m_BUF[i].start_adr = pbi->m_BUF[i].alloc_addr; + } else { + pbi->m_BUF[i].cma_page_count = 0; + pbi->m_BUF[i].alloc_addr = 0; + pbi->m_BUF[i].start_adr = + pbi->mc_buf->buf_start + i * buf_size; + } + pbi->m_BUF[i].size = buf_size; + pbi->m_BUF[i].free_start_adr = pbi->m_BUF[i].start_adr; + + if (((pbi->m_BUF[i].start_adr + buf_size) > mc_buffer_end) + && (pbi->m_BUF[i].alloc_addr == 0)) { + if (debug) { + pr_info + ("Max mc buffer or mpred_mv buffer is used\n"); + } + break; + } + + if (debug) { + pr_info("Buffer %d: start_adr %p size %x\n", i, + (void *)pbi->m_BUF[i].start_adr, + pbi->m_BUF[i].size); + } +#endif + } + pbi->buf_num = i; +} +#endif + +static int config_pic(struct VP9Decoder_s *pbi, + struct PIC_BUFFER_CONFIG_s *pic_config) +{ + int ret = -1; + int i; + int pic_width = pbi->init_pic_w; + int pic_height = pbi->init_pic_h; + int lcu_size = 64; /*fixed 64*/ + int pic_width_64 = (pic_width + 63) & (~0x3f); + int pic_height_32 = (pic_height + 31) & (~0x1f); + int pic_width_lcu = (pic_width_64 % lcu_size) ? + pic_width_64 / lcu_size + 1 + : pic_width_64 / lcu_size; + int pic_height_lcu = (pic_height_32 % lcu_size) ? + pic_height_32 / lcu_size + 1 + : pic_height_32 / lcu_size; + int lcu_total = pic_width_lcu * pic_height_lcu; +#ifdef MV_USE_FIXED_BUF + u32 mpred_mv_end = pbi->work_space_buf->mpred_mv.buf_start + + pbi->work_space_buf->mpred_mv.buf_size; +#endif + u32 y_adr = 0; + int buf_size = 0; + + int losless_comp_header_size = + compute_losless_comp_header_size(pic_width, + pic_height); + int losless_comp_body_size = compute_losless_comp_body_size(pic_width, + pic_height, buf_alloc_depth == 10); + int mc_buffer_size = losless_comp_header_size + losless_comp_body_size; + int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16; + int mc_buffer_size_u_v = 0; + int mc_buffer_size_u_v_h = 0; + int dw_mode = get_double_write_mode_init(pbi); + + pbi->lcu_total = lcu_total; + + if (dw_mode) { + int pic_width_dw = pic_width / + get_double_write_ratio(pbi, dw_mode); + int pic_height_dw = pic_height / + get_double_write_ratio(pbi, dw_mode); + + int pic_width_64_dw = (pic_width_dw + 63) & (~0x3f); + int pic_height_32_dw = (pic_height_dw + 31) & (~0x1f); + int pic_width_lcu_dw = (pic_width_64_dw % lcu_size) ? + pic_width_64_dw / lcu_size + 1 + : pic_width_64_dw / lcu_size; + int pic_height_lcu_dw = (pic_height_32_dw % lcu_size) ? + pic_height_32_dw / lcu_size + 1 + : pic_height_32_dw / lcu_size; + int lcu_total_dw = pic_width_lcu_dw * pic_height_lcu_dw; + mc_buffer_size_u_v = lcu_total_dw * lcu_size * lcu_size / 2; + mc_buffer_size_u_v_h = (mc_buffer_size_u_v + 0xffff) >> 16; + /*64k alignment*/ + buf_size = ((mc_buffer_size_u_v_h << 16) * 3); + buf_size = ((buf_size + 0xffff) >> 16) << 16; + } + + if (mc_buffer_size & 0xffff) /*64k alignment*/ + mc_buffer_size_h += 1; +#ifndef VP9_10B_MMU + if ((dw_mode & 0x10) == 0) + buf_size += (mc_buffer_size_h << 16); +#endif + +#ifdef VP9_10B_MMU + pic_config->header_adr = decoder_bmmu_box_get_phy_addr( + pbi->bmmu_box, HEADER_BUFFER_IDX(pic_config->index)); + + if (debug & VP9_DEBUG_BUFMGR_MORE) { + pr_info("MMU header_adr %d: %ld\n", + pic_config->index, pic_config->header_adr); + } +#endif + + i = pic_config->index; +#ifdef MV_USE_FIXED_BUF + if ((pbi->work_space_buf->mpred_mv.buf_start + + (((i + 1) * lcu_total) * MV_MEM_UNIT)) + <= mpred_mv_end + ) { +#endif +#ifndef VP9_10B_MMU + if (debug) { + pr_err("start %x .size=%d\n", + pbi->mc_buf_spec.buf_start + i * buf_size, + buf_size); + } +#endif +#ifndef VP9_10B_MMU + for (i = 0; i < pbi->buf_num; i++) { + y_adr = ((pbi->m_BUF[i].free_start_adr + + 0xffff) >> 16) << 16; + /*64k alignment*/ + if ((y_adr+buf_size) <= (pbi->m_BUF[i].start_adr+ + pbi->m_BUF[i].size)) { + pbi->m_BUF[i].free_start_adr = + y_adr + buf_size; + break; + } + } + if (i < pbi->buf_num) +#else + /*if ((pbi->mc_buf->buf_start + (i + 1) * buf_size) < + pbi->mc_buf->buf_end) + y_adr = pbi->mc_buf->buf_start + i * buf_size; + else {*/ + if (buf_size > 0) { + ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, + VF_BUFFER_IDX(i), + buf_size, DRIVER_NAME, + &pic_config->cma_alloc_addr); + if (ret < 0) { + pr_info( + "decoder_bmmu_box_alloc_buf_phy idx %d size %d fail\n", + VF_BUFFER_IDX(i), + buf_size + ); + return ret; + } + + if (pic_config->cma_alloc_addr) + y_adr = pic_config->cma_alloc_addr; + else { + pr_info( + "decoder_bmmu_box_alloc_buf_phy idx %d size %d return null\n", + VF_BUFFER_IDX(i), + buf_size + ); + return -1; + } + } +#endif + { + /*ensure get_pic_by_POC() + not get the buffer not decoded*/ + pic_config->BUF_index = i; + pic_config->lcu_total = lcu_total; + + pic_config->comp_body_size = losless_comp_body_size; + pic_config->buf_size = buf_size; +#ifndef VP9_10B_MMU + pic_config->mc_y_adr = y_adr; +#endif + pic_config->mc_canvas_y = pic_config->index; + pic_config->mc_canvas_u_v = pic_config->index; +#ifndef VP9_10B_MMU + if (dw_mode & 0x10) { + pic_config->mc_u_v_adr = y_adr + + ((mc_buffer_size_u_v_h << 16) << 1); + + pic_config->mc_canvas_y = + (pic_config->index << 1); + pic_config->mc_canvas_u_v = + (pic_config->index << 1) + 1; + + pic_config->dw_y_adr = y_adr; + pic_config->dw_u_v_adr = pic_config->mc_u_v_adr; + } else +#endif + if (dw_mode) { + pic_config->dw_y_adr = y_adr +#ifndef VP9_10B_MMU + + (mc_buffer_size_h << 16) +#endif + ; + pic_config->dw_u_v_adr = pic_config->dw_y_adr + + ((mc_buffer_size_u_v_h << 16) << 1); +#ifdef VP9_10B_MMU + pic_config->mc_y_adr = pic_config->dw_y_adr; + pic_config->mc_u_v_adr = pic_config->dw_u_v_adr; +#endif + } +#ifdef MV_USE_FIXED_BUF + pic_config->mpred_mv_wr_start_addr = + pbi->work_space_buf->mpred_mv.buf_start + + ((pic_config->index * lcu_total) + * MV_MEM_UNIT); +#endif + if (debug) { + pr_info + ("%s index %d BUF_index %d mc_y_adr %lx ", + __func__, pic_config->index, + pic_config->BUF_index, + pic_config->mc_y_adr); + pr_info + ("comp_body_size %x comp_buf_size %x ", + pic_config->comp_body_size, + pic_config->buf_size); + pr_info + ("mpred_mv_wr_start_adr %ld\n", + pic_config->mpred_mv_wr_start_addr); + pr_info("dw_y_adr %d, pic_config->dw_u_v_adr =%d\n", + pic_config->dw_y_adr, + pic_config->dw_u_v_adr); + } + ret = 0; + } +#ifdef MV_USE_FIXED_BUF + } +#endif + return ret; +} + +static void init_pic_list(struct VP9Decoder_s *pbi) +{ + int i; + struct VP9_Common_s *cm = &pbi->common; + struct PIC_BUFFER_CONFIG_s *pic_config; +#ifdef VP9_10B_MMU + /*alloc VP9 compress header first*/ + for (i = 0; i < pbi->used_buf_num; i++) { + unsigned long buf_addr; + if (decoder_bmmu_box_alloc_buf_phy + (pbi->bmmu_box, + HEADER_BUFFER_IDX(i), MMU_COMPRESS_HEADER_SIZE, + DRIVER_HEADER_NAME, + &buf_addr) < 0){ + pr_info("%s malloc compress header failed %d\n", + DRIVER_HEADER_NAME, i); + pbi->fatal_error |= DECODER_FATAL_ERROR_NO_MEM; + return; + } + } +#endif + for (i = 0; i < pbi->used_buf_num; i++) { + pic_config = &cm->buffer_pool->frame_bufs[i].buf; + pic_config->index = i; + pic_config->BUF_index = -1; + pic_config->mv_buf_index = -1; + if (config_pic(pbi, pic_config) < 0) { + if (debug) + pr_info("Config_pic %d fail\n", + pic_config->index); + pic_config->index = -1; + break; + } + pic_config->y_crop_width = pbi->init_pic_w; + pic_config->y_crop_height = pbi->init_pic_h; + /*set_canvas(pic_config);*/ + } + for (; i < pbi->used_buf_num; i++) { + pic_config = &cm->buffer_pool->frame_bufs[i].buf; + pic_config->index = -1; + pic_config->BUF_index = -1; + pic_config->mv_buf_index = -1; + } + pr_info("%s ok, used_buf_num = %d\n", + __func__, pbi->used_buf_num); + +} + + +static void init_pic_list_hw(struct VP9Decoder_s *pbi) +{ + int i; + struct VP9_Common_s *cm = &pbi->common; + struct PIC_BUFFER_CONFIG_s *pic_config; + /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/ + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, + (0x1 << 1) | (0x1 << 2)); + + + for (i = 0; i < pbi->used_buf_num; i++) { + pic_config = &cm->buffer_pool->frame_bufs[i].buf; + if (pic_config->index < 0) + break; + +#ifdef VP9_10B_MMU + /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, + pic_config->header_adr + | (pic_config->mc_canvas_y << 8)|0x1);*/ + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, pic_config->header_adr >> 5); +#else + /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, + pic_config->mc_y_adr + | (pic_config->mc_canvas_y << 8) | 0x1);*/ + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, pic_config->mc_y_adr >> 5); +#endif +#ifndef LOSLESS_COMPRESS_MODE + /*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, + pic_config->mc_u_v_adr + | (pic_config->mc_canvas_u_v << 8)| 0x1);*/ + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_DATA, pic_config->mc_u_v_adr >> 5); +#endif + + } + WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x1); + + /*Zero out canvas registers in IPP -- avoid simulation X*/ + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (0 << 8) | (0 << 1) | 1); + for (i = 0; i < 32; i++) + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0); +} + + +static void dump_pic_list(struct VP9Decoder_s *pbi) +{ + struct VP9_Common_s *const cm = &pbi->common; + struct PIC_BUFFER_CONFIG_s *pic_config; + int i; + for (i = 0; i < FRAME_BUFFERS; i++) { + pic_config = &cm->buffer_pool->frame_bufs[i].buf; + vp9_print(pbi, 0, + "Buf(%d) index %d mv_buf_index %d ref_count %d vf_ref %d dec_idx %d slice_type %d w/h %d/%d adr%ld\n", + i, + pic_config->index, +#ifndef MV_USE_FIXED_BUF + pic_config->mv_buf_index, +#else + -1, +#endif + cm->buffer_pool-> + frame_bufs[i].ref_count, + pic_config->vf_ref, + pic_config->decode_idx, + pic_config->slice_type, + pic_config->y_crop_width, + pic_config->y_crop_height, + pic_config->cma_alloc_addr + ); + } + return; +} + +static int config_pic_size(struct VP9Decoder_s *pbi, unsigned short bit_depth) +{ +#ifdef LOSLESS_COMPRESS_MODE + unsigned int data32; +#endif + int losless_comp_header_size, losless_comp_body_size; + struct VP9_Common_s *cm = &pbi->common; + struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf; + + frame_width = cur_pic_config->y_crop_width; + frame_height = cur_pic_config->y_crop_height; + cur_pic_config->bit_depth = bit_depth; + cur_pic_config->double_write_mode = get_double_write_mode(pbi); + losless_comp_header_size = + compute_losless_comp_header_size(cur_pic_config->y_crop_width, + cur_pic_config->y_crop_height); + losless_comp_body_size = + compute_losless_comp_body_size(cur_pic_config->y_crop_width, + cur_pic_config->y_crop_height, (bit_depth == VPX_BITS_10)); + cur_pic_config->comp_body_size = losless_comp_body_size; +#ifdef LOSLESS_COMPRESS_MODE + data32 = READ_VREG(HEVC_SAO_CTRL5); + if (bit_depth == VPX_BITS_10) + data32 &= ~(1 << 9); + else + data32 |= (1 << 9); + + WRITE_VREG(HEVC_SAO_CTRL5, data32); + +#ifdef VP9_10B_MMU + /*bit[4] : paged_mem_mode*/ + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4)); +#else + /*bit[3] smem mdoe*/ + if (bit_depth == VPX_BITS_10) + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0 << 3)); + else + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1 << 3)); +#endif + WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5)); + /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/ + WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size); + WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size); + WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size); +#else + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31); +#endif + return 0; +} + +static int config_mc_buffer(struct VP9Decoder_s *pbi, unsigned short bit_depth) +{ + int i; + struct VP9_Common_s *cm = &pbi->common; + struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf; + uint8_t scale_enable = 0; + + if (debug&VP9_DEBUG_BUFMGR_MORE) + pr_info("config_mc_buffer entered .....\n"); + + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (0 << 8) | (0 << 1) | 1); + for (i = 0; i < REFS_PER_FRAME; ++i) { + struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf; + if (!pic_config) + continue; + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, + (pic_config->mc_canvas_u_v << 16) + | (pic_config->mc_canvas_u_v << 8) + | pic_config->mc_canvas_y); + if (debug & VP9_DEBUG_BUFMGR_MORE) + pr_info("refid %x mc_canvas_u_v %x mc_canvas_y %x\n", + i, pic_config->mc_canvas_u_v, + pic_config->mc_canvas_y); + } + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (16 << 8) | (0 << 1) | 1); + for (i = 0; i < REFS_PER_FRAME; ++i) { + struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf; + if (!pic_config) + continue; + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR, + (pic_config->mc_canvas_u_v << 16) + | (pic_config->mc_canvas_u_v << 8) + | pic_config->mc_canvas_y); + } + + /*auto_inc start index:0 field:0*/ + WRITE_VREG(VP9D_MPP_REFINFO_TBL_ACCCONFIG, 0x1 << 2); + /*index 0:last 1:golden 2:altref*/ + for (i = 0; i < REFS_PER_FRAME; i++) { + int ref_pic_body_size; + struct PIC_BUFFER_CONFIG_s *pic_config = cm->frame_refs[i].buf; + if (!pic_config) + continue; + WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_width); + WRITE_VREG(VP9D_MPP_REFINFO_DATA, pic_config->y_crop_height); + + if (pic_config->y_crop_width != cur_pic_config->y_crop_width || + pic_config->y_crop_height != cur_pic_config->y_crop_height) { + scale_enable |= (1 << i); + } + ref_pic_body_size = + compute_losless_comp_body_size(pic_config->y_crop_width, + pic_config->y_crop_height, (bit_depth == VPX_BITS_10)); + WRITE_VREG(VP9D_MPP_REFINFO_DATA, + (pic_config->y_crop_width << 14) + / cur_pic_config->y_crop_width); + WRITE_VREG(VP9D_MPP_REFINFO_DATA, + (pic_config->y_crop_height << 14) + / cur_pic_config->y_crop_height); +#ifdef VP9_10B_MMU + WRITE_VREG(VP9D_MPP_REFINFO_DATA, 0); +#else + WRITE_VREG(VP9D_MPP_REFINFO_DATA, ref_pic_body_size >> 5); +#endif + } + WRITE_VREG(VP9D_MPP_REF_SCALE_ENBL, scale_enable); + return 0; +} + +static void clear_mpred_hw(struct VP9Decoder_s *pbi) +{ + unsigned int data32; + + data32 = READ_VREG(HEVC_MPRED_CTRL4); + data32 &= (~(1 << 6)); + WRITE_VREG(HEVC_MPRED_CTRL4, data32); +} + +static void config_mpred_hw(struct VP9Decoder_s *pbi) +{ + struct VP9_Common_s *cm = &pbi->common; + struct PIC_BUFFER_CONFIG_s *cur_pic_config = &cm->cur_frame->buf; + struct PIC_BUFFER_CONFIG_s *last_frame_pic_config = + &cm->prev_frame->buf; + + unsigned int data32; + int mpred_curr_lcu_x; + int mpred_curr_lcu_y; + int mpred_mv_rd_end_addr; + + + mpred_mv_rd_end_addr = last_frame_pic_config->mpred_mv_wr_start_addr + + (last_frame_pic_config->lcu_total * MV_MEM_UNIT); + + data32 = READ_VREG(HEVC_MPRED_CURR_LCU); + mpred_curr_lcu_x = data32 & 0xffff; + mpred_curr_lcu_y = (data32 >> 16) & 0xffff; + + if (debug & VP9_DEBUG_BUFMGR) + pr_info("cur pic_config index %d col pic_config index %d\n", + cur_pic_config->index, last_frame_pic_config->index); + WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412); + WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, + pbi->work_space_buf->mpred_above.buf_start); + + data32 = READ_VREG(HEVC_MPRED_CTRL4); + + data32 &= (~(1 << 6)); + data32 |= (cm->use_prev_frame_mvs << 6); + WRITE_VREG(HEVC_MPRED_CTRL4, data32); + + WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR, + cur_pic_config->mpred_mv_wr_start_addr); + WRITE_VREG(HEVC_MPRED_MV_WPTR, cur_pic_config->mpred_mv_wr_start_addr); + + WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR, + last_frame_pic_config->mpred_mv_wr_start_addr); + WRITE_VREG(HEVC_MPRED_MV_RPTR, + last_frame_pic_config->mpred_mv_wr_start_addr); + /*data32 = ((pbi->lcu_x_num - pbi->tile_width_lcu)*MV_MEM_UNIT);*/ + /*WRITE_VREG(HEVC_MPRED_MV_WR_ROW_JUMP,data32);*/ + /*WRITE_VREG(HEVC_MPRED_MV_RD_ROW_JUMP,data32);*/ + WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, mpred_mv_rd_end_addr); + +} + +static void config_sao_hw(struct VP9Decoder_s *pbi, union param_u *params) +{ + struct VP9_Common_s *cm = &pbi->common; + struct PIC_BUFFER_CONFIG_s *pic_config = &cm->cur_frame->buf; + + unsigned int data32; + int lcu_size = 64; + int mc_buffer_size_u_v = + pic_config->lcu_total * lcu_size*lcu_size/2; + int mc_buffer_size_u_v_h = + (mc_buffer_size_u_v + 0xffff) >> 16;/*64k alignment*/ + +#ifndef VP9_10B_MMU + if ((get_double_write_mode(pbi) & 0x10) == 0) + WRITE_VREG(HEVC_CM_BODY_START_ADDR, pic_config->mc_y_adr); +#endif + if (get_double_write_mode(pbi)) { + WRITE_VREG(HEVC_SAO_Y_START_ADDR, pic_config->dw_y_adr); + WRITE_VREG(HEVC_SAO_C_START_ADDR, pic_config->dw_u_v_adr); + WRITE_VREG(HEVC_SAO_Y_WPTR, pic_config->dw_y_adr); + WRITE_VREG(HEVC_SAO_C_WPTR, pic_config->dw_u_v_adr); + } else { + WRITE_VREG(HEVC_SAO_Y_START_ADDR, 0xffffffff); + WRITE_VREG(HEVC_SAO_C_START_ADDR, 0xffffffff); + } +#ifdef VP9_10B_MMU + WRITE_VREG(HEVC_CM_HEADER_START_ADDR, pic_config->header_adr); +#endif + data32 = (mc_buffer_size_u_v_h << 16) << 1; + /*pr_info("data32=%x,mc_buffer_size_u_v_h=%x,lcu_total=%x\n", + * data32, mc_buffer_size_u_v_h, pic_config->lcu_total); + */ + WRITE_VREG(HEVC_SAO_Y_LENGTH, data32); + + data32 = (mc_buffer_size_u_v_h << 16); + WRITE_VREG(HEVC_SAO_C_LENGTH, data32); + +#ifdef VP9_10B_NV21 +#ifdef DOS_PROJECT + data32 = READ_VREG(HEVC_SAO_CTRL1); + data32 &= (~0x3000); + /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/ + data32 |= (MEM_MAP_MODE << 12); + data32 &= (~0x3); + data32 |= 0x1; /* [1]:dw_disable [0]:cm_disable*/ + WRITE_VREG(HEVC_SAO_CTRL1, data32); + /*[23:22] dw_v1_ctrl [21:20] dw_v0_ctrl [19:18] dw_h1_ctrl + * [17:16] dw_h0_ctrl + */ + data32 = READ_VREG(HEVC_SAO_CTRL5); + /*set them all 0 for H265_NV21 (no down-scale)*/ + data32 &= ~(0xff << 16); + WRITE_VREG(HEVC_SAO_CTRL5, data32); + data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG); + data32 &= (~0x30); + /*[5:4] address_format 00:linear 01:32x32 10:64x32*/ + data32 |= (MEM_MAP_MODE << 4); + WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32); +#else + /*m8baby test1902*/ + data32 = READ_VREG(HEVC_SAO_CTRL1); + data32 &= (~0x3000); + /*[13:12] axi_aformat, 0-Linear, 1-32x32, 2-64x32*/ + data32 |= (MEM_MAP_MODE << 12); + data32 &= (~0xff0); + /*data32 |= 0x670;*/ /*Big-Endian per 64-bit*/ + data32 |= 0x880; /*.Big-Endian per 64-bit */ + data32 &= (~0x3); + data32 |= 0x1; /*[1]:dw_disable [0]:cm_disable*/ + WRITE_VREG(HEVC_SAO_CTRL1, data32); + /* [23:22] dw_v1_ctrl [21:20] dw_v0_ctrl + *[19:18] dw_h1_ctrl [17:16] dw_h0_ctrl + */ + data32 = READ_VREG(HEVC_SAO_CTRL5); + /* set them all 0 for H265_NV21 (no down-scale)*/ + data32 &= ~(0xff << 16); + WRITE_VREG(HEVC_SAO_CTRL5, data32); + + data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG); + data32 &= (~0x30); + /*[5:4] address_format 00:linear 01:32x32 10:64x32*/ + data32 |= (MEM_MAP_MODE << 4); + data32 &= (~0xF); + data32 |= 0x8; /*Big-Endian per 64-bit*/ + WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32); +#endif +#else + data32 = READ_VREG(HEVC_SAO_CTRL1); + data32 &= (~0x3000); + data32 |= (MEM_MAP_MODE << + 12); + +/* [13:12] axi_aformat, 0-Linear, + * 1-32x32, 2-64x32 + */ + data32 &= (~0xff0); + /* data32 |= 0x670; // Big-Endian per 64-bit */ + data32 |= endian; /* Big-Endian per 64-bit */ + if (get_cpu_type() < MESON_CPU_MAJOR_ID_G12A) { + data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/ + if (get_double_write_mode(pbi) == 0) + data32 |= 0x2; /*disable double write*/ +#ifndef VP9_10B_MMU + else + if (get_double_write_mode(pbi) & 0x10) + data32 |= 0x1; /*disable cm*/ +#endif + } else { /* >= G12A dw write control */ + unsigned int data; + data = READ_VREG(HEVC_DBLK_CFGB); + data &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/ + if (get_double_write_mode(pbi) == 0) + data |= (0x1 << 8); /*enable first write*/ + else if (get_double_write_mode(pbi) == 0x10) + data |= (0x1 << 9); /*double write only*/ + else + data |= ((0x1 << 8) |(0x1 << 9)); + WRITE_VREG(HEVC_DBLK_CFGB, data); + } + WRITE_VREG(HEVC_SAO_CTRL1, data32); + + if (get_double_write_mode(pbi) & 0x10) { + /* [23:22] dw_v1_ctrl + *[21:20] dw_v0_ctrl + *[19:18] dw_h1_ctrl + *[17:16] dw_h0_ctrl + */ + data32 = READ_VREG(HEVC_SAO_CTRL5); + /*set them all 0 for H265_NV21 (no down-scale)*/ + data32 &= ~(0xff << 16); + WRITE_VREG(HEVC_SAO_CTRL5, data32); + } else { + data32 = READ_VREG(HEVC_SAO_CTRL5); + data32 &= (~(0xff << 16)); + if (get_double_write_mode(pbi) == 2 || + get_double_write_mode(pbi) == 3) + data32 |= (0xff<<16); + else if (get_double_write_mode(pbi) == 4) + data32 |= (0x33<<16); + WRITE_VREG(HEVC_SAO_CTRL5, data32); + } + + data32 = READ_VREG(HEVCD_IPP_AXIIF_CONFIG); + data32 &= (~0x30); + /* [5:4] -- address_format 00:linear 01:32x32 10:64x32 */ + data32 |= (mem_map_mode << + 4); + data32 &= (~0xF); + data32 |= 0xf; /* valid only when double write only */ + /*data32 |= 0x8;*/ /* Big-Endian per 64-bit */ + WRITE_VREG(HEVCD_IPP_AXIIF_CONFIG, data32); +#endif +} + +static void vp9_config_work_space_hw(struct VP9Decoder_s *pbi, u32 mask) +{ + struct BuffInfo_s *buf_spec = pbi->work_space_buf; +#ifdef VP9_10B_MMU + unsigned int data32; +#endif + if (debug && pbi->init_flag == 0) + pr_info("%s %x %x %x %x %x %x %x %x %x %x %x %x\n", + __func__, + buf_spec->ipp.buf_start, + buf_spec->start_adr, + buf_spec->short_term_rps.buf_start, + buf_spec->vps.buf_start, + buf_spec->sps.buf_start, + buf_spec->pps.buf_start, + buf_spec->sao_up.buf_start, + buf_spec->swap_buf.buf_start, + buf_spec->swap_buf2.buf_start, + buf_spec->scalelut.buf_start, + buf_spec->dblk_para.buf_start, + buf_spec->dblk_data.buf_start); + + if (mask & HW_MASK_FRONT) { + if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) + WRITE_VREG(HEVC_RPM_BUFFER, (u32)pbi->rpm_phy_addr); + + WRITE_VREG(HEVC_SHORT_TERM_RPS, + buf_spec->short_term_rps.buf_start); + /*WRITE_VREG(HEVC_VPS_BUFFER, buf_spec->vps.buf_start);*/ + /*WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start);*/ + WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start); + WRITE_VREG(HEVC_STREAM_SWAP_BUFFER, + buf_spec->swap_buf.buf_start); + WRITE_VREG(HEVC_STREAM_SWAP_BUFFER2, + buf_spec->swap_buf2.buf_start); + WRITE_VREG(LMEM_DUMP_ADR, (u32)pbi->lmem_phy_addr); + + } + + if (mask & HW_MASK_BACK) { +#ifdef LOSLESS_COMPRESS_MODE + int losless_comp_header_size = + compute_losless_comp_header_size(pbi->init_pic_w, + pbi->init_pic_h); + int losless_comp_body_size = + compute_losless_comp_body_size(pbi->init_pic_w, + pbi->init_pic_h, buf_alloc_depth == 10); +#endif + WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE, + buf_spec->ipp.buf_start); + WRITE_VREG(HEVC_SAO_UP, buf_spec->sao_up.buf_start); + WRITE_VREG(HEVC_SCALELUT, buf_spec->scalelut.buf_start); + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) { + /* cfg_addr_adp*/ + WRITE_VREG(HEVC_DBLK_CFGE, buf_spec->dblk_para.buf_start); + if (debug & VP9_DEBUG_BUFMGR_MORE) + pr_info("Write HEVC_DBLK_CFGE\n"); + } else { + /* cfg_p_addr */ + WRITE_VREG(HEVC_DBLK_CFG4, buf_spec->dblk_para.buf_start); + } + /* cfg_d_addr */ + WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start); + +#ifdef LOSLESS_COMPRESS_MODE +#ifdef VP9_10B_MMU + /*bit[4] : paged_mem_mode*/ + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4)); + WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0); +#else + /*if(cur_pic_config->bit_depth == VPX_BITS_10) + * WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (0<<3)); + */ + /*bit[3] smem mdoe*/ + /*else WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (1<<3));*/ + /*bit[3] smem mdoe*/ + WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, + (losless_comp_body_size >> 5)); +#endif + /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, + (losless_comp_body_size >> 5));*/ + /*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3, + (0xff<<20) | (0xff<<10) | 0xff);*/ + /*8-bit mode */ + WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size); + WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size); + WRITE_VREG(HEVC_CM_HEADER_LENGTH, losless_comp_header_size); +#else + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31); +#endif + +#ifdef VP9_10B_MMU + WRITE_VREG(HEVC_SAO_MMU_VH0_ADDR, buf_spec->mmu_vbh.buf_start); + WRITE_VREG(HEVC_SAO_MMU_VH1_ADDR, buf_spec->mmu_vbh.buf_start + + buf_spec->mmu_vbh.buf_size/2); + /*data32 = READ_VREG(P_HEVC_SAO_CTRL9);*/ + /*data32 |= 0x1;*/ + /*WRITE_VREG(P_HEVC_SAO_CTRL9, data32);*/ + + /* use HEVC_CM_HEADER_START_ADDR */ + data32 = READ_VREG(HEVC_SAO_CTRL5); + data32 |= (1<<10); + WRITE_VREG(HEVC_SAO_CTRL5, data32); +#endif + WRITE_VREG(VP9_SEG_MAP_BUFFER, buf_spec->seg_map.buf_start); + + /**/ + WRITE_VREG(VP9_PROB_SWAP_BUFFER, pbi->prob_buffer_phy_addr); + WRITE_VREG(VP9_COUNT_SWAP_BUFFER, pbi->count_buffer_phy_addr); +#ifdef VP9_10B_MMU + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) + WRITE_VREG(HEVC_ASSIST_MMU_MAP_ADDR, pbi->frame_mmu_map_phy_addr); + else + WRITE_VREG(VP9_MMU_MAP_BUFFER, pbi->frame_mmu_map_phy_addr); +#endif + } + +} + + +#ifdef VP9_LPF_LVL_UPDATE +/* + * Defines, declarations, sub-functions for vp9 de-block loop + filter Thr/Lvl table update + * - struct segmentation is for loop filter only (removed something) + * - function "vp9_loop_filter_init" and "vp9_loop_filter_frame_init" will + be instantiated in C_Entry + * - vp9_loop_filter_init run once before decoding start + * - vp9_loop_filter_frame_init run before every frame decoding start + * - set video format to VP9 is in vp9_loop_filter_init + */ +#define MAX_LOOP_FILTER 63 +#define MAX_REF_LF_DELTAS 4 +#define MAX_MODE_LF_DELTAS 2 +/*#define INTRA_FRAME 0*/ +/*#define LAST_FRAME 1*/ +/*#define MAX_REF_FRAMES 4*/ +#define SEGMENT_DELTADATA 0 +#define SEGMENT_ABSDATA 1 +#define MAX_SEGMENTS 8 +/*.#define SEG_TREE_PROBS (MAX_SEGMENTS-1)*/ +/*no use for loop filter, if this struct for common use, pls add it back*/ +/*#define PREDICTION_PROBS 3*/ +/* no use for loop filter, if this struct for common use, pls add it back*/ + +enum SEG_LVL_FEATURES { + SEG_LVL_ALT_Q = 0, /*Use alternate Quantizer ....*/ + SEG_LVL_ALT_LF = 1, /*Use alternate loop filter value...*/ + SEG_LVL_REF_FRAME = 2, /*Optional Segment reference frame*/ + SEG_LVL_SKIP = 3, /*Optional Segment (0,0) + skip mode*/ + SEG_LVL_MAX = 4 /*Number of features supported*/ +}; + +struct segmentation { + uint8_t enabled; + uint8_t update_map; + uint8_t update_data; + uint8_t abs_delta; + uint8_t temporal_update; + + /*no use for loop filter, if this struct + *for common use, pls add it back + */ + /*vp9_prob tree_probs[SEG_TREE_PROBS]; */ + /* no use for loop filter, if this struct + * for common use, pls add it back + */ + /*vp9_prob pred_probs[PREDICTION_PROBS];*/ + + int16_t feature_data[MAX_SEGMENTS][SEG_LVL_MAX]; + unsigned int feature_mask[MAX_SEGMENTS]; +}; + +struct loop_filter_thresh { + uint8_t mblim; + uint8_t lim; + uint8_t hev_thr; +}; + +struct loop_filter_info_n { + struct loop_filter_thresh lfthr[MAX_LOOP_FILTER + 1]; + uint8_t lvl[MAX_SEGMENTS][MAX_REF_FRAMES][MAX_MODE_LF_DELTAS]; +}; + +struct loopfilter { + int filter_level; + + int sharpness_level; + int last_sharpness_level; + + uint8_t mode_ref_delta_enabled; + uint8_t mode_ref_delta_update; + + /*0 = Intra, Last, GF, ARF*/ + signed char ref_deltas[MAX_REF_LF_DELTAS]; + signed char last_ref_deltas[MAX_REF_LF_DELTAS]; + + /*0 = ZERO_MV, MV*/ + signed char mode_deltas[MAX_MODE_LF_DELTAS]; + signed char last_mode_deltas[MAX_MODE_LF_DELTAS]; +}; + +static int vp9_clamp(int value, int low, int high) +{ + return value < low ? low : (value > high ? high : value); +} + +int segfeature_active(struct segmentation *seg, + int segment_id, + enum SEG_LVL_FEATURES feature_id) { + return seg->enabled && + (seg->feature_mask[segment_id] & (1 << feature_id)); +} + +int get_segdata(struct segmentation *seg, int segment_id, + enum SEG_LVL_FEATURES feature_id) { + return seg->feature_data[segment_id][feature_id]; +} + +static void vp9_update_sharpness(struct loop_filter_info_n *lfi, + int sharpness_lvl) +{ + int lvl; + /*For each possible value for the loop filter fill out limits*/ + for (lvl = 0; lvl <= MAX_LOOP_FILTER; lvl++) { + /*Set loop filter parameters that control sharpness.*/ + int block_inside_limit = lvl >> ((sharpness_lvl > 0) + + (sharpness_lvl > 4)); + + if (sharpness_lvl > 0) { + if (block_inside_limit > (9 - sharpness_lvl)) + block_inside_limit = (9 - sharpness_lvl); + } + + if (block_inside_limit < 1) + block_inside_limit = 1; + + lfi->lfthr[lvl].lim = (uint8_t)block_inside_limit; + lfi->lfthr[lvl].mblim = (uint8_t)(2 * (lvl + 2) + + block_inside_limit); + } +} + +/*instantiate this function once when decode is started*/ +void vp9_loop_filter_init(struct VP9Decoder_s *pbi) +{ + struct loop_filter_info_n *lfi = pbi->lfi; + struct loopfilter *lf = pbi->lf; + struct segmentation *seg_4lf = pbi->seg_4lf; + int i; + + memset(lfi, 0, sizeof(struct loop_filter_info_n)); + memset(lf, 0, sizeof(struct loopfilter)); + memset(seg_4lf, 0, sizeof(struct segmentation)); + lf->sharpness_level = 0; /*init to 0 */ + /*init limits for given sharpness*/ + vp9_update_sharpness(lfi, lf->sharpness_level); + lf->last_sharpness_level = lf->sharpness_level; + /*init hev threshold const vectors (actually no use) + *for (i = 0; i <= MAX_LOOP_FILTER; i++) + * lfi->lfthr[i].hev_thr = (uint8_t)(i >> 4); + */ + + /*Write to register*/ + for (i = 0; i < 32; i++) { + unsigned int thr; + + thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f)<<8) | + (lfi->lfthr[i * 2 + 1].mblim & 0xff); + thr = (thr<<16) | ((lfi->lfthr[i*2].lim & 0x3f)<<8) | + (lfi->lfthr[i * 2].mblim & 0xff); + WRITE_VREG(HEVC_DBLK_CFG9, thr); + } + + /*video format is VP9*/ + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) { + unsigned int data32; + data32 = (0x57 << 8) | /*1st/2nd write both enable*/ + (0x1 << 0); /*vp9 video format*/ + WRITE_VREG(HEVC_DBLK_CFGB, data32); + + if (debug & VP9_DEBUG_BUFMGR_MORE) + pr_info("[DBLK DEBUG] CFGB : 0x%x\n", data32); + } else + WRITE_VREG(HEVC_DBLK_CFGB, 0x40400001); +} + /* perform this function per frame*/ +void vp9_loop_filter_frame_init(struct segmentation *seg, + struct loop_filter_info_n *lfi, struct loopfilter *lf, + int default_filt_lvl) { + int i; + int seg_id; + /*n_shift is the multiplier for lf_deltas + *the multiplier is 1 for when filter_lvl is between 0 and 31; + *2 when filter_lvl is between 32 and 63 + */ + const int scale = 1 << (default_filt_lvl >> 5); + + /*update limits if sharpness has changed*/ + if (lf->last_sharpness_level != lf->sharpness_level) { + vp9_update_sharpness(lfi, lf->sharpness_level); + lf->last_sharpness_level = lf->sharpness_level; + + /*Write to register*/ + for (i = 0; i < 32; i++) { + unsigned int thr; + + thr = ((lfi->lfthr[i * 2 + 1].lim & 0x3f) << 8) + | (lfi->lfthr[i * 2 + 1].mblim & 0xff); + thr = (thr << 16) | ((lfi->lfthr[i * 2].lim & 0x3f) << 8) + | (lfi->lfthr[i * 2].mblim & 0xff); + WRITE_VREG(HEVC_DBLK_CFG9, thr); + } + } + + for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) {/*MAX_SEGMENTS = 8*/ + int lvl_seg = default_filt_lvl; + + if (segfeature_active(seg, seg_id, SEG_LVL_ALT_LF)) { + const int data = get_segdata(seg, seg_id, + SEG_LVL_ALT_LF); + lvl_seg = vp9_clamp(seg->abs_delta == SEGMENT_ABSDATA ? + data : default_filt_lvl + data, + 0, MAX_LOOP_FILTER); +#ifdef DBG_LF_PRINT + pr_info("segfeature_active!!!seg_id=%d,lvl_seg=%d\n", seg_id, lvl_seg); +#endif + } + + if (!lf->mode_ref_delta_enabled) { + /*we could get rid of this if we assume that deltas are set to + *zero when not in use; encoder always uses deltas + */ + memset(lfi->lvl[seg_id], lvl_seg, sizeof(lfi->lvl[seg_id])); + } else { + int ref, mode; + const int intra_lvl = lvl_seg + lf->ref_deltas[INTRA_FRAME] + * scale; +#ifdef DBG_LF_PRINT + pr_info("LF_PRINT:vp9_loop_filter_frame_init,seg_id=%d\n", seg_id); + pr_info("ref_deltas[INTRA_FRAME]=%d\n", lf->ref_deltas[INTRA_FRAME]); +#endif + lfi->lvl[seg_id][INTRA_FRAME][0] = + vp9_clamp(intra_lvl, 0, MAX_LOOP_FILTER); + + for (ref = LAST_FRAME; ref < MAX_REF_FRAMES; ++ref) { + /* LAST_FRAME = 1, MAX_REF_FRAMES = 4*/ + for (mode = 0; mode < MAX_MODE_LF_DELTAS; ++mode) { + /*MAX_MODE_LF_DELTAS = 2*/ + const int inter_lvl = + lvl_seg + lf->ref_deltas[ref] * scale + + lf->mode_deltas[mode] * scale; +#ifdef DBG_LF_PRINT +#endif + lfi->lvl[seg_id][ref][mode] = + vp9_clamp(inter_lvl, 0, + MAX_LOOP_FILTER); + } + } + } + } + +#ifdef DBG_LF_PRINT + /*print out thr/lvl table per frame*/ + for (i = 0; i <= MAX_LOOP_FILTER; i++) { + pr_info("LF_PRINT:(%d)thr=%d,blim=%d,lim=%d\n", + i, lfi->lfthr[i].hev_thr, lfi->lfthr[i].mblim, + lfi->lfthr[i].lim); + } + for (seg_id = 0; seg_id < MAX_SEGMENTS; seg_id++) { + pr_info("LF_PRINT:lvl(seg_id=%d)(mode=0,%d,%d,%d,%d)\n", + seg_id, lfi->lvl[seg_id][0][0], + lfi->lvl[seg_id][1][0], lfi->lvl[seg_id][2][0], + lfi->lvl[seg_id][3][0]); + pr_info("i(mode=1,%d,%d,%d,%d)\n", lfi->lvl[seg_id][0][1], + lfi->lvl[seg_id][1][1], lfi->lvl[seg_id][2][1], + lfi->lvl[seg_id][3][1]); + } +#endif + + /*Write to register */ + for (i = 0; i < 16; i++) { + unsigned int level; + + level = ((lfi->lvl[i >> 1][3][i & 1] & 0x3f) << 24) | + ((lfi->lvl[i >> 1][2][i & 1] & 0x3f) << 16) | + ((lfi->lvl[i >> 1][1][i & 1] & 0x3f) << 8) | + (lfi->lvl[i >> 1][0][i & 1] & 0x3f); + if (!default_filt_lvl) + level = 0; + WRITE_VREG(HEVC_DBLK_CFGA, level); + } +} +/* VP9_LPF_LVL_UPDATE */ +#endif + +static void vp9_init_decoder_hw(struct VP9Decoder_s *pbi, u32 mask) +{ + unsigned int data32; + int i; + const unsigned short parser_cmd[PARSER_CMD_NUMBER] = { + 0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423, + 0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE, + 0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A, + 0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408, + 0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D, + 0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00, + 0x7C00 + }; +#if 0 + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) { + /* Set MCR fetch priorities*/ + data32 = 0x1 | (0x1 << 2) | (0x1 <<3) | + (24 << 4) | (32 << 11) | (24 << 18) | (32 << 25); + WRITE_VREG(HEVCD_MPP_DECOMP_AXIURG_CTL, data32); + } +#endif + /*if (debug & VP9_DEBUG_BUFMGR_MORE) + pr_info("%s\n", __func__);*/ + if (mask & HW_MASK_FRONT) { + data32 = READ_VREG(HEVC_PARSER_INT_CONTROL); +#if 1 + /* set bit 31~29 to 3 if HEVC_STREAM_FIFO_CTL[29] is 1 */ + data32 &= ~(7 << 29); + data32 |= (3 << 29); +#endif + data32 = data32 | + (1 << 24) |/*stream_buffer_empty_int_amrisc_enable*/ + (1 << 22) |/*stream_fifo_empty_int_amrisc_enable*/ + (1 << 7) |/*dec_done_int_cpu_enable*/ + (1 << 4) |/*startcode_found_int_cpu_enable*/ + (0 << 3) |/*startcode_found_int_amrisc_enable*/ + (1 << 0) /*parser_int_enable*/ + ; +#ifdef SUPPORT_FB_DECODING +#ifndef FB_DECODING_TEST_SCHEDULE + /*fed_fb_slice_done_int_cpu_enable*/ + if (pbi->used_stage_buf_num > 0) + data32 |= (1 << 10); +#endif +#endif + WRITE_VREG(HEVC_PARSER_INT_CONTROL, data32); + + data32 = READ_VREG(HEVC_SHIFT_STATUS); + data32 = data32 | + (0 << 1) |/*emulation_check_off VP9 + do not have emulation*/ + (1 << 0)/*startcode_check_on*/ + ; + WRITE_VREG(HEVC_SHIFT_STATUS, data32); + WRITE_VREG(HEVC_SHIFT_CONTROL, + (0 << 14) | /*disable_start_code_protect*/ + (1 << 10) | /*length_zero_startcode_en for VP9*/ + (1 << 9) | /*length_valid_startcode_en for VP9*/ + (3 << 6) | /*sft_valid_wr_position*/ + (2 << 4) | /*emulate_code_length_sub_1*/ + (3 << 1) | /*start_code_length_sub_1 + VP9 use 0x00000001 as startcode (4 Bytes)*/ + (1 << 0) /*stream_shift_enable*/ + ); + + WRITE_VREG(HEVC_CABAC_CONTROL, + (1 << 0)/*cabac_enable*/ + ); + + WRITE_VREG(HEVC_PARSER_CORE_CONTROL, + (1 << 0)/* hevc_parser_core_clk_en*/ + ); + + + WRITE_VREG(HEVC_DEC_STATUS_REG, 0); + + } + + if (mask & HW_MASK_BACK) { + /*Initial IQIT_SCALELUT memory + -- just to avoid X in simulation*/ + + WRITE_VREG(HEVC_IQIT_SCALELUT_WR_ADDR, 0);/*cfg_p_addr*/ + for (i = 0; i < 1024; i++) + WRITE_VREG(HEVC_IQIT_SCALELUT_DATA, 0); + } + + if (mask & HW_MASK_FRONT) { + u32 decode_mode; +#ifdef ENABLE_SWAP_TEST + WRITE_VREG(HEVC_STREAM_SWAP_TEST, 100); +#else + WRITE_VREG(HEVC_STREAM_SWAP_TEST, 0); +#endif +#ifdef MULTI_INSTANCE_SUPPORT + if (!pbi->m_ins_flag) + decode_mode = DECODE_MODE_SINGLE; + else if (vdec_frame_based(hw_to_vdec(pbi))) + decode_mode = DECODE_MODE_MULTI_FRAMEBASE; + else + decode_mode = DECODE_MODE_MULTI_STREAMBASE; +#ifdef SUPPORT_FB_DECODING +#ifndef FB_DECODING_TEST_SCHEDULE + if (pbi->used_stage_buf_num > 0) + decode_mode |= (0x01 << 24); +#endif +#endif + WRITE_VREG(DECODE_MODE, decode_mode); + WRITE_VREG(HEVC_DECODE_SIZE, 0); + WRITE_VREG(HEVC_DECODE_COUNT, 0); +#else + WRITE_VREG(DECODE_MODE, DECODE_MODE_SINGLE); + WRITE_VREG(HEVC_DECODE_PIC_BEGIN_REG, 0); + WRITE_VREG(HEVC_DECODE_PIC_NUM_REG, 0x7fffffff); /*to remove*/ +#endif + /*Send parser_cmd*/ + WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0)); + for (i = 0; i < PARSER_CMD_NUMBER; i++) + WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]); + WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0); + WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1); + WRITE_VREG(HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2); + + + WRITE_VREG(HEVC_PARSER_IF_CONTROL, + /* (1 << 8) |*/ /*sao_sw_pred_enable*/ + (1 << 5) | /*parser_sao_if_en*/ + (1 << 2) | /*parser_mpred_if_en*/ + (1 << 0) /*parser_scaler_if_en*/ + ); + } + + if (mask & HW_MASK_BACK) { + /*Changed to Start MPRED in microcode*/ + /* + pr_info("[test.c] Start MPRED\n"); + WRITE_VREG(HEVC_MPRED_INT_STATUS, + (1<<31) + ); + */ + WRITE_VREG(HEVCD_IPP_TOP_CNTL, + (0 << 1) | /*enable ipp*/ + (1 << 0) /*software reset ipp and mpp*/ + ); + WRITE_VREG(HEVCD_IPP_TOP_CNTL, + (1 << 1) | /*enable ipp*/ + (0 << 0) /*software reset ipp and mpp*/ + ); +#ifdef VP9_10B_NV21 + /*Enable NV21 reference read mode for MC*/ + WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, 0x1 << 31); +#endif + + /*Initialize mcrcc and decomp perf counters*/ + if (mcrcc_cache_alg_flag && + pbi->init_flag == 0) { + mcrcc_perfcount_reset(); + decomp_perfcount_reset(); + } + } + return; +} + + +#ifdef CONFIG_HEVC_CLK_FORCED_ON +static void config_vp9_clk_forced_on(void) +{ + unsigned int rdata32; + /*IQIT*/ + rdata32 = READ_VREG(HEVC_IQIT_CLK_RST_CTRL); + WRITE_VREG(HEVC_IQIT_CLK_RST_CTRL, rdata32 | (0x1 << 2)); + + /* DBLK*/ + rdata32 = READ_VREG(HEVC_DBLK_CFG0); + WRITE_VREG(HEVC_DBLK_CFG0, rdata32 | (0x1 << 2)); + + /* SAO*/ + rdata32 = READ_VREG(HEVC_SAO_CTRL1); + WRITE_VREG(HEVC_SAO_CTRL1, rdata32 | (0x1 << 2)); + + /*MPRED*/ + rdata32 = READ_VREG(HEVC_MPRED_CTRL1); + WRITE_VREG(HEVC_MPRED_CTRL1, rdata32 | (0x1 << 24)); + + /* PARSER*/ + rdata32 = READ_VREG(HEVC_STREAM_CONTROL); + WRITE_VREG(HEVC_STREAM_CONTROL, rdata32 | (0x1 << 15)); + rdata32 = READ_VREG(HEVC_SHIFT_CONTROL); + WRITE_VREG(HEVC_SHIFT_CONTROL, rdata32 | (0x1 << 15)); + rdata32 = READ_VREG(HEVC_CABAC_CONTROL); + WRITE_VREG(HEVC_CABAC_CONTROL, rdata32 | (0x1 << 13)); + rdata32 = READ_VREG(HEVC_PARSER_CORE_CONTROL); + WRITE_VREG(HEVC_PARSER_CORE_CONTROL, rdata32 | (0x1 << 15)); + rdata32 = READ_VREG(HEVC_PARSER_INT_CONTROL); + WRITE_VREG(HEVC_PARSER_INT_CONTROL, rdata32 | (0x1 << 15)); + rdata32 = READ_VREG(HEVC_PARSER_IF_CONTROL); + WRITE_VREG(HEVC_PARSER_IF_CONTROL, + rdata32 | (0x1 << 6) | (0x1 << 3) | (0x1 << 1)); + + /*IPP*/ + rdata32 = READ_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG); + WRITE_VREG(HEVCD_IPP_DYNCLKGATE_CONFIG, rdata32 | 0xffffffff); + + /* MCRCC*/ + rdata32 = READ_VREG(HEVCD_MCRCC_CTL1); + WRITE_VREG(HEVCD_MCRCC_CTL1, rdata32 | (0x1 << 3)); +} +#endif + + +#ifdef MCRCC_ENABLE +static void dump_hit_rate(struct VP9Decoder_s *pbi) +{ + if (debug & VP9_DEBUG_CACHE_HIT_RATE) { + mcrcc_get_hitrate(pbi->m_ins_flag); + decomp_get_hitrate(); + decomp_get_comprate(); + } +} + +static void config_mcrcc_axi_hw(struct VP9Decoder_s *pbi) +{ + unsigned int rdata32; + unsigned short is_inter; + /*pr_info("Entered config_mcrcc_axi_hw...\n");*/ + WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2);/* reset mcrcc*/ + is_inter = ((pbi->common.frame_type != KEY_FRAME) && + (!pbi->common.intra_only)) ? 1 : 0; + if (!is_inter) { /* I-PIC*/ + /*remove reset -- disables clock*/ + WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0); + return; + } + +#if 0 + mcrcc_get_hitrate(); + decomp_get_hitrate(); + decomp_get_comprate(); +#endif + + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (0 << 8) | (1 << 1) | 0); + rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32 = rdata32 & 0xffff; + rdata32 = rdata32 | (rdata32 << 16); + WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32); + /*Programme canvas1 */ + rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32 = rdata32 & 0xffff; + rdata32 = rdata32 | (rdata32 << 16); + WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32); + /*enable mcrcc progressive-mode*/ + WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); +} + +static void config_mcrcc_axi_hw_new(struct VP9Decoder_s *pbi) +{ + u32 curr_picnum = -1; + u32 lastref_picnum = -1; + u32 goldenref_picnum = -1; + u32 altref_picnum = -1; + + u32 lastref_delta_picnum; + u32 goldenref_delta_picnum; + u32 altref_delta_picnum; + + u32 rdata32; + + u32 lastcanvas; + u32 goldencanvas; + u32 altrefcanvas; + + u16 is_inter; + u16 lastref_inref; + u16 goldenref_inref; + u16 altref_inref; + + u32 refcanvas_array[3], utmp; + int deltapicnum_array[3], tmp; + + struct VP9_Common_s *cm = &pbi->common; + struct PIC_BUFFER_CONFIG_s *cur_pic_config + = &cm->cur_frame->buf; + curr_picnum = cur_pic_config->decode_idx; + if (cm->frame_refs[0].buf) + lastref_picnum = cm->frame_refs[0].buf->decode_idx; + if (cm->frame_refs[1].buf) + goldenref_picnum = cm->frame_refs[1].buf->decode_idx; + if (cm->frame_refs[2].buf) + altref_picnum = cm->frame_refs[2].buf->decode_idx; + + lastref_delta_picnum = (lastref_picnum >= curr_picnum) ? + (lastref_picnum - curr_picnum) : (curr_picnum - lastref_picnum); + goldenref_delta_picnum = (goldenref_picnum >= curr_picnum) ? + (goldenref_picnum - curr_picnum) : + (curr_picnum - goldenref_picnum); + altref_delta_picnum = + (altref_picnum >= curr_picnum) ? + (altref_picnum - curr_picnum) : (curr_picnum - altref_picnum); + + lastref_inref = (cm->frame_refs[0].idx != INVALID_IDX) ? 1 : 0; + goldenref_inref = (cm->frame_refs[1].idx != INVALID_IDX) ? 1 : 0; + altref_inref = (cm->frame_refs[2].idx != INVALID_IDX) ? 1 : 0; + + if (debug & VP9_DEBUG_CACHE) + pr_info("%s--0--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n", + __func__, lastref_inref, goldenref_inref, altref_inref); + + WRITE_VREG(HEVCD_MCRCC_CTL1, 0x2); /* reset mcrcc */ + + is_inter = ((pbi->common.frame_type != KEY_FRAME) + && (!pbi->common.intra_only)) ? 1 : 0; + + if (!is_inter) { /* I-PIC */ + /* remove reset -- disables clock */ + WRITE_VREG(HEVCD_MCRCC_CTL1, 0x0); + return; + } + + if (!pbi->m_ins_flag) + dump_hit_rate(pbi); + + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, (0 << 8) | (1<<1) | 0); + lastcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + goldencanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + altrefcanvas = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + + if (debug & VP9_DEBUG_CACHE) + pr_info("[test.c] lastref_canv:%x goldenref_canv:%x altref_canv:%x\n", + lastcanvas, goldencanvas, altrefcanvas); + + altref_inref = ((altref_inref == 1) && + (altrefcanvas != (goldenref_inref + ? goldencanvas : 0xffffffff)) && + (altrefcanvas != (lastref_inref ? + lastcanvas : 0xffffffff))) ? 1 : 0; + goldenref_inref = ((goldenref_inref == 1) && + (goldencanvas != (lastref_inref ? + lastcanvas : 0xffffffff))) ? 1 : 0; + if (debug & VP9_DEBUG_CACHE) + pr_info("[test.c]--1--lastref_inref:%d goldenref_inref:%d altref_inref:%d\n", + lastref_inref, goldenref_inref, altref_inref); + + altref_delta_picnum = altref_inref ? altref_delta_picnum : 0x7fffffff; + goldenref_delta_picnum = goldenref_inref ? + goldenref_delta_picnum : 0x7fffffff; + lastref_delta_picnum = lastref_inref ? + lastref_delta_picnum : 0x7fffffff; + if (debug & VP9_DEBUG_CACHE) + pr_info("[test.c]--1--lastref_delta_picnum:%d goldenref_delta_picnum:%d altref_delta_picnum:%d\n", + lastref_delta_picnum, goldenref_delta_picnum, + altref_delta_picnum); + /*ARRAY SORT HERE DELTA/CANVAS ARRAY SORT -- use DELTA*/ + + refcanvas_array[0] = lastcanvas; + refcanvas_array[1] = goldencanvas; + refcanvas_array[2] = altrefcanvas; + + deltapicnum_array[0] = lastref_delta_picnum; + deltapicnum_array[1] = goldenref_delta_picnum; + deltapicnum_array[2] = altref_delta_picnum; + + /* sort0 : 2-to-1 */ + if (deltapicnum_array[2] < deltapicnum_array[1]) { + utmp = refcanvas_array[2]; + refcanvas_array[2] = refcanvas_array[1]; + refcanvas_array[1] = utmp; + tmp = deltapicnum_array[2]; + deltapicnum_array[2] = deltapicnum_array[1]; + deltapicnum_array[1] = tmp; + } + /* sort1 : 1-to-0 */ + if (deltapicnum_array[1] < deltapicnum_array[0]) { + utmp = refcanvas_array[1]; + refcanvas_array[1] = refcanvas_array[0]; + refcanvas_array[0] = utmp; + tmp = deltapicnum_array[1]; + deltapicnum_array[1] = deltapicnum_array[0]; + deltapicnum_array[0] = tmp; + } + /* sort2 : 2-to-1 */ + if (deltapicnum_array[2] < deltapicnum_array[1]) { + utmp = refcanvas_array[2]; refcanvas_array[2] = + refcanvas_array[1]; refcanvas_array[1] = utmp; + tmp = deltapicnum_array[2]; deltapicnum_array[2] = + deltapicnum_array[1]; deltapicnum_array[1] = tmp; + } + if (mcrcc_cache_alg_flag == + THODIYIL_MCRCC_CANVAS_ALGX) { /*09/15/2017*/ + /* lowest delta_picnum */ + rdata32 = refcanvas_array[0]; + rdata32 = rdata32 & 0xffff; + rdata32 = rdata32 | (rdata32 << 16); + WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32); + + /* 2nd-lowest delta_picnum */ + rdata32 = refcanvas_array[1]; + rdata32 = rdata32 & 0xffff; + rdata32 = rdata32 | (rdata32 << 16); + WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32); + } else { + /* previous version -- LAST/GOLDEN ALWAYS -- before 09/13/2017*/ + WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, + (0 << 8) | (1<<1) | 0); + rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32 = rdata32 & 0xffff; + rdata32 = rdata32 | (rdata32 << 16); + WRITE_VREG(HEVCD_MCRCC_CTL2, rdata32); + + /* Programme canvas1 */ + rdata32 = READ_VREG(HEVCD_MPP_ANC_CANVAS_DATA_ADDR); + rdata32 = rdata32 & 0xffff; + rdata32 = rdata32 | (rdata32 << 16); + WRITE_VREG(HEVCD_MCRCC_CTL3, rdata32); + } + + WRITE_VREG(HEVCD_MCRCC_CTL1, 0xff0); /* enable mcrcc progressive-mode */ + return; +} + +#endif + + +static void free_lf_buf(struct VP9Decoder_s *pbi) +{ + if (pbi->lfi) + vfree(pbi->lfi); + if (pbi->lf) + vfree(pbi->lf); + if (pbi->seg_4lf) + vfree(pbi->seg_4lf); + pbi->lfi = NULL; + pbi->lf = NULL; + pbi->seg_4lf = NULL; +} + +static int alloc_lf_buf(struct VP9Decoder_s *pbi) +{ + pbi->lfi = vmalloc(sizeof(struct loop_filter_info_n)); + pbi->lf = vmalloc(sizeof(struct loopfilter)); + pbi->seg_4lf = vmalloc(sizeof(struct segmentation)); + if (pbi->lfi == NULL || pbi->lf == NULL || pbi->seg_4lf == NULL) { + free_lf_buf(pbi); + pr_err("[test.c] vp9_loop_filter init malloc error!!!\n"); + return -1; + } + return 0; +} + +static void vp9_local_uninit(struct VP9Decoder_s *pbi) +{ + pbi->rpm_ptr = NULL; + pbi->lmem_ptr = NULL; + if (pbi->rpm_addr) { + dma_unmap_single(amports_get_dma_device(), + pbi->rpm_phy_addr, RPM_BUF_SIZE, + DMA_FROM_DEVICE); + kfree(pbi->rpm_addr); + pbi->rpm_addr = NULL; + } + if (pbi->lmem_addr) { + if (pbi->lmem_phy_addr) + dma_free_coherent(amports_get_dma_device(), + LMEM_BUF_SIZE, pbi->lmem_addr, + pbi->lmem_phy_addr); + pbi->lmem_addr = NULL; + } + if (pbi->prob_buffer_addr) { + if (pbi->prob_buffer_phy_addr) + dma_free_coherent(amports_get_dma_device(), + PROB_BUF_SIZE, pbi->prob_buffer_addr, + pbi->prob_buffer_phy_addr); + + pbi->prob_buffer_addr = NULL; + } + if (pbi->count_buffer_addr) { + if (pbi->count_buffer_phy_addr) + dma_free_coherent(amports_get_dma_device(), + COUNT_BUF_SIZE, pbi->count_buffer_addr, + pbi->count_buffer_phy_addr); + + pbi->count_buffer_addr = NULL; + } +#ifdef VP9_10B_MMU + if (pbi->frame_mmu_map_addr) { + if (pbi->frame_mmu_map_phy_addr) + dma_free_coherent(amports_get_dma_device(), + FRAME_MMU_MAP_SIZE, pbi->frame_mmu_map_addr, + pbi->frame_mmu_map_phy_addr); + pbi->frame_mmu_map_addr = NULL; + } +#endif +#ifdef SUPPORT_FB_DECODING + if (pbi->stage_mmu_map_addr) { + if (pbi->stage_mmu_map_phy_addr) + dma_free_coherent(amports_get_dma_device(), + STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS, + pbi->stage_mmu_map_addr, + pbi->stage_mmu_map_phy_addr); + pbi->stage_mmu_map_addr = NULL; + } + + uninit_stage_buf(pbi); +#endif + +#ifdef VP9_LPF_LVL_UPDATE + free_lf_buf(pbi); +#endif + if (pbi->gvs) + vfree(pbi->gvs); + pbi->gvs = NULL; +} + + + + +static int vp9_local_init(struct VP9Decoder_s *pbi) +{ + int ret = -1; + /*int losless_comp_header_size, losless_comp_body_size;*/ + + struct BuffInfo_s *cur_buf_info = NULL; + + memset(&pbi->param, 0, sizeof(union param_u)); + memset(&pbi->common, 0, sizeof(struct VP9_Common_s)); +#ifdef MULTI_INSTANCE_SUPPORT + cur_buf_info = &pbi->work_space_buf_store; +#ifdef SUPPORT_4K2K + if (vdec_is_support_4k()) + memcpy(cur_buf_info, &amvvp9_workbuff_spec[1], /* 4k */ + sizeof(struct BuffInfo_s)); + else + memcpy(cur_buf_info, &amvvp9_workbuff_spec[0],/* 1080p */ + sizeof(struct BuffInfo_s)); +#else + memcpy(cur_buf_info, &amvvp9_workbuff_spec[0], /* 1080p work space */ + sizeof(struct BuffInfo_s)); +#endif + cur_buf_info->start_adr = pbi->buf_start; +#ifndef VP9_10B_MMU + pbi->mc_buf_spec.buf_end = pbi->buf_start + pbi->buf_size; +#endif +#else +/*! MULTI_INSTANCE_SUPPORT*/ +#ifdef SUPPORT_4K2K + if (vdec_is_support_4k()) + cur_buf_info = &amvvp9_workbuff_spec[1];/* 4k2k work space */ + else + cur_buf_info = &amvvp9_workbuff_spec[0];/* 1080p work space */ +#else + cur_buf_info = &amvvp9_workbuff_spec[0]; /* 1080p work space */ +#endif +#endif + + init_buff_spec(pbi, cur_buf_info); +#ifdef VP9_10B_MMU + vp9_bufmgr_init(pbi, cur_buf_info, NULL); +#else + pbi->mc_buf_spec.buf_start = (cur_buf_info->end_adr + 0xffff) + & (~0xffff); + pbi->mc_buf_spec.buf_size = (pbi->mc_buf_spec.buf_end + - pbi->mc_buf_spec.buf_start); + if (debug) { + pr_err("pbi->mc_buf_spec.buf_start %x-%x\n", + pbi->mc_buf_spec.buf_start, + pbi->mc_buf_spec.buf_start + + pbi->mc_buf_spec.buf_size); + } + vp9_bufmgr_init(pbi, cur_buf_info, &pbi->mc_buf_spec); +#endif + + if (!vdec_is_support_4k() + && (buf_alloc_width > 1920 && buf_alloc_height > 1088)) { + buf_alloc_width = 1920; + buf_alloc_height = 1088; + if (pbi->max_pic_w > 1920 && pbi->max_pic_h > 1088) { + pbi->max_pic_w = 1920; + pbi->max_pic_h = 1088; + } + } + pbi->init_pic_w = pbi->max_pic_w ? pbi->max_pic_w : + (buf_alloc_width ? buf_alloc_width : + (pbi->vvp9_amstream_dec_info.width ? + pbi->vvp9_amstream_dec_info.width : + pbi->work_space_buf->max_width)); + pbi->init_pic_h = pbi->max_pic_h ? pbi->max_pic_h : + (buf_alloc_height ? buf_alloc_height : + (pbi->vvp9_amstream_dec_info.height ? + pbi->vvp9_amstream_dec_info.height : + pbi->work_space_buf->max_height)); +#ifndef MV_USE_FIXED_BUF + if (init_mv_buf_list(pbi) < 0) { + pr_err("%s: init_mv_buf_list fail\n", __func__); + return -1; + } +#endif + +#ifndef VP9_10B_MMU + init_buf_list(pbi); +#else + pbi->used_buf_num = max_buf_num; + if (pbi->used_buf_num > MAX_BUF_NUM) + pbi->used_buf_num = MAX_BUF_NUM; + if (pbi->used_buf_num > FRAME_BUFFERS) + pbi->used_buf_num = FRAME_BUFFERS; +#endif + init_pic_list(pbi); + + pbi->pts_unstable = ((unsigned long)(pbi->vvp9_amstream_dec_info.param) + & 0x40) >> 6; + + if ((debug & VP9_DEBUG_SEND_PARAM_WITH_REG) == 0) { + pbi->rpm_addr = kmalloc(RPM_BUF_SIZE, GFP_KERNEL); + if (pbi->rpm_addr == NULL) { + pr_err("%s: failed to alloc rpm buffer\n", __func__); + return -1; + } + + pbi->rpm_phy_addr = dma_map_single(amports_get_dma_device(), + pbi->rpm_addr, RPM_BUF_SIZE, DMA_FROM_DEVICE); + if (dma_mapping_error(amports_get_dma_device(), + pbi->rpm_phy_addr)) { + pr_err("%s: failed to map rpm buffer\n", __func__); + kfree(pbi->rpm_addr); + pbi->rpm_addr = NULL; + return -1; + } + + pbi->rpm_ptr = pbi->rpm_addr; + } + + pbi->lmem_addr = dma_alloc_coherent(amports_get_dma_device(), + LMEM_BUF_SIZE, + &pbi->lmem_phy_addr, GFP_KERNEL); + if (pbi->lmem_addr == NULL) { + pr_err("%s: failed to alloc lmem buffer\n", __func__); + return -1; + } +/* + * pbi->lmem_phy_addr = dma_map_single(amports_get_dma_device(), + * pbi->lmem_addr, LMEM_BUF_SIZE, DMA_BIDIRECTIONAL); + * if (dma_mapping_error(amports_get_dma_device(), + * pbi->lmem_phy_addr)) { + * pr_err("%s: failed to map lmem buffer\n", __func__); + * kfree(pbi->lmem_addr); + * pbi->lmem_addr = NULL; + * return -1; + * } + */ + pbi->lmem_ptr = pbi->lmem_addr; + + pbi->prob_buffer_addr = dma_alloc_coherent(amports_get_dma_device(), + PROB_BUF_SIZE, + &pbi->prob_buffer_phy_addr, GFP_KERNEL); + if (pbi->prob_buffer_addr == NULL) { + pr_err("%s: failed to alloc prob_buffer\n", __func__); + return -1; + } + memset(pbi->prob_buffer_addr, 0, PROB_BUF_SIZE); +/* pbi->prob_buffer_phy_addr = dma_map_single(amports_get_dma_device(), + * pbi->prob_buffer_addr, PROB_BUF_SIZE, DMA_BIDIRECTIONAL); + * if (dma_mapping_error(amports_get_dma_device(), + * pbi->prob_buffer_phy_addr)) { + * pr_err("%s: failed to map prob_buffer\n", __func__); + * kfree(pbi->prob_buffer_addr); + * pbi->prob_buffer_addr = NULL; + * return -1; + * } + */ + pbi->count_buffer_addr = dma_alloc_coherent(amports_get_dma_device(), + COUNT_BUF_SIZE, + &pbi->count_buffer_phy_addr, GFP_KERNEL); + if (pbi->count_buffer_addr == NULL) { + pr_err("%s: failed to alloc count_buffer\n", __func__); + return -1; + } + memset(pbi->count_buffer_addr, 0, COUNT_BUF_SIZE); +/* pbi->count_buffer_phy_addr = dma_map_single(amports_get_dma_device(), + pbi->count_buffer_addr, COUNT_BUF_SIZE, DMA_BIDIRECTIONAL); + if (dma_mapping_error(amports_get_dma_device(), + pbi->count_buffer_phy_addr)) { + pr_err("%s: failed to map count_buffer\n", __func__); + kfree(pbi->count_buffer_addr); + pbi->count_buffer_addr = NULL; + return -1; + } +*/ +#ifdef VP9_10B_MMU + pbi->frame_mmu_map_addr = dma_alloc_coherent(amports_get_dma_device(), + FRAME_MMU_MAP_SIZE, + &pbi->frame_mmu_map_phy_addr, GFP_KERNEL); + if (pbi->frame_mmu_map_addr == NULL) { + pr_err("%s: failed to alloc count_buffer\n", __func__); + return -1; + } + memset(pbi->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE); +/* pbi->frame_mmu_map_phy_addr = dma_map_single(amports_get_dma_device(), + pbi->frame_mmu_map_addr, FRAME_MMU_MAP_SIZE, DMA_BIDIRECTIONAL); + if (dma_mapping_error(amports_get_dma_device(), + pbi->frame_mmu_map_phy_addr)) { + pr_err("%s: failed to map count_buffer\n", __func__); + kfree(pbi->frame_mmu_map_addr); + pbi->frame_mmu_map_addr = NULL; + return -1; + }*/ +#endif + +#ifdef SUPPORT_FB_DECODING + if (pbi->m_ins_flag && stage_buf_num > 0) { + pbi->stage_mmu_map_addr = + dma_alloc_coherent(amports_get_dma_device(), + STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS, + &pbi->stage_mmu_map_phy_addr, GFP_KERNEL); + if (pbi->stage_mmu_map_addr == NULL) { + pr_err("%s: failed to alloc count_buffer\n", __func__); + return -1; + } + memset(pbi->stage_mmu_map_addr, + 0, STAGE_MMU_MAP_SIZE * STAGE_MAX_BUFFERS); + + init_stage_buf(pbi); + } +#endif + + ret = 0; + return ret; +} + +/******************************************** + * Mailbox command + ********************************************/ +#define CMD_FINISHED 0 +#define CMD_ALLOC_VIEW 1 +#define CMD_FRAME_DISPLAY 3 +#define CMD_DEBUG 10 + + +#define DECODE_BUFFER_NUM_MAX 32 +#define DISPLAY_BUFFER_NUM 6 + +#define video_domain_addr(adr) (adr&0x7fffffff) +#define DECODER_WORK_SPACE_SIZE 0x800000 + +#define spec2canvas(x) \ + (((x)->uv_canvas_index << 16) | \ + ((x)->uv_canvas_index << 8) | \ + ((x)->y_canvas_index << 0)) + + +static void set_canvas(struct VP9Decoder_s *pbi, + struct PIC_BUFFER_CONFIG_s *pic_config) +{ + int canvas_w = ALIGN(pic_config->y_crop_width, 64)/4; + int canvas_h = ALIGN(pic_config->y_crop_height, 32)/4; + int blkmode = mem_map_mode; + /*CANVAS_BLKMODE_64X32*/ + if (pic_config->double_write_mode) { + canvas_w = pic_config->y_crop_width / + get_double_write_ratio(pbi, + pic_config->double_write_mode); + canvas_h = pic_config->y_crop_height / + get_double_write_ratio(pbi, + pic_config->double_write_mode); + + if (mem_map_mode == 0) + canvas_w = ALIGN(canvas_w, 32); + else + canvas_w = ALIGN(canvas_w, 64); + canvas_h = ALIGN(canvas_h, 32); + + pic_config->y_canvas_index = 128 + pic_config->index * 2; + pic_config->uv_canvas_index = 128 + pic_config->index * 2 + 1; + + canvas_config_ex(pic_config->y_canvas_index, + pic_config->dw_y_adr, canvas_w, canvas_h, + CANVAS_ADDR_NOWRAP, blkmode, 0x7); + canvas_config_ex(pic_config->uv_canvas_index, + pic_config->dw_u_v_adr, canvas_w, canvas_h, + CANVAS_ADDR_NOWRAP, blkmode, 0x7); +#ifdef MULTI_INSTANCE_SUPPORT + pic_config->canvas_config[0].phy_addr = + pic_config->dw_y_adr; + pic_config->canvas_config[0].width = + canvas_w; + pic_config->canvas_config[0].height = + canvas_h; + pic_config->canvas_config[0].block_mode = + blkmode; + pic_config->canvas_config[0].endian = 7; + + pic_config->canvas_config[1].phy_addr = + pic_config->dw_u_v_adr; + pic_config->canvas_config[1].width = + canvas_w; + pic_config->canvas_config[1].height = + canvas_h; + pic_config->canvas_config[1].block_mode = + blkmode; + pic_config->canvas_config[1].endian = 7; +#endif + } else { + #ifndef VP9_10B_MMU + pic_config->y_canvas_index = 128 + pic_config->index; + pic_config->uv_canvas_index = 128 + pic_config->index; + + canvas_config_ex(pic_config->y_canvas_index, + pic_config->mc_y_adr, canvas_w, canvas_h, + CANVAS_ADDR_NOWRAP, blkmode, 0x7); + canvas_config_ex(pic_config->uv_canvas_index, + pic_config->mc_u_v_adr, canvas_w, canvas_h, + CANVAS_ADDR_NOWRAP, blkmode, 0x7); + #endif + } +} + + +static void set_frame_info(struct VP9Decoder_s *pbi, struct vframe_s *vf) +{ + unsigned int ar; + + vf->duration = pbi->frame_dur; + vf->duration_pulldown = 0; + vf->flag = 0; + vf->prop.master_display_colour = pbi->vf_dp; + vf->signal_type = pbi->video_signal_type; + + ar = min_t(u32, pbi->frame_ar, DISP_RATIO_ASPECT_RATIO_MAX); + vf->ratio_control = (ar << DISP_RATIO_ASPECT_RATIO_BIT); + +} + +static int vvp9_vf_states(struct vframe_states *states, void *op_arg) +{ + struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg; + + states->vf_pool_size = VF_POOL_SIZE; + states->buf_free_num = kfifo_len(&pbi->newframe_q); + states->buf_avail_num = kfifo_len(&pbi->display_q); + + if (step == 2) + states->buf_avail_num = 0; + return 0; +} + +static struct vframe_s *vvp9_vf_peek(void *op_arg) +{ + struct vframe_s *vf[2] = {0, 0}; + struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg; + + if (step == 2) + return NULL; + + if (kfifo_out_peek(&pbi->display_q, (void *)&vf, 2)) { + if (vf[1]) { + vf[0]->next_vf_pts_valid = true; + vf[0]->next_vf_pts = vf[1]->pts; + } else + vf[0]->next_vf_pts_valid = false; + return vf[0]; + } + + return NULL; +} + +static struct vframe_s *vvp9_vf_get(void *op_arg) +{ + struct vframe_s *vf; + struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg; + + if (step == 2) + return NULL; + else if (step == 1) + step = 2; + + if (kfifo_get(&pbi->display_q, &vf)) { + struct vframe_s *next_vf; + uint8_t index = vf->index & 0xff; + if (index >= 0 && index < pbi->used_buf_num) { + pbi->vf_get_count++; + if (debug & VP9_DEBUG_BUFMGR) + pr_info("%s type 0x%x w/h %d/%d, pts %d, %lld\n", + __func__, vf->type, + vf->width, vf->height, + vf->pts, + vf->pts_us64); + + if (kfifo_peek(&pbi->display_q, &next_vf)) { + vf->next_vf_pts_valid = true; + vf->next_vf_pts = next_vf->pts; + } else + vf->next_vf_pts_valid = false; + + return vf; + } + } + return NULL; +} + +static void vvp9_vf_put(struct vframe_s *vf, void *op_arg) +{ + struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)op_arg; + uint8_t index = vf->index & 0xff; + + kfifo_put(&pbi->newframe_q, (const struct vframe_s *)vf); + pbi->vf_put_count++; + if (index >= 0 + && index < pbi->used_buf_num) { + struct VP9_Common_s *cm = &pbi->common; + struct BufferPool_s *pool = cm->buffer_pool; + unsigned long flags; + + lock_buffer_pool(pool, flags); + if (pool->frame_bufs[index].buf.vf_ref > 0) + pool->frame_bufs[index].buf.vf_ref--; + + if (pbi->wait_buf) + WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, + 0x1); + pbi->last_put_idx = index; + pbi->new_frame_displayed++; + unlock_buffer_pool(pool, flags); +#ifdef SUPPORT_FB_DECODING + if (pbi->used_stage_buf_num > 0 && + pbi->back_not_run_ready) + trigger_schedule(pbi); +#endif + } + +} + +static int vvp9_event_cb(int type, void *data, void *private_data) +{ + if (type & VFRAME_EVENT_RECEIVER_RESET) { +#if 0 + unsigned long flags; + + amhevc_stop(); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_light_unreg_provider(&vvp9_vf_prov); +#endif + spin_lock_irqsave(&pbi->lock, flags); + vvp9_local_init(); + vvp9_prot_init(); + spin_unlock_irqrestore(&pbi->lock, flags); +#ifndef CONFIG_AMLOGIC_POST_PROCESS_MANAGER + vf_reg_provider(&vvp9_vf_prov); +#endif + amhevc_start(); +#endif + } + + return 0; +} + +void inc_vf_ref(struct VP9Decoder_s *pbi, int index) +{ + struct VP9_Common_s *cm = &pbi->common; + + cm->buffer_pool->frame_bufs[index].buf.vf_ref++; + + if (debug & VP9_DEBUG_BUFMGR_MORE) + pr_info("%s index = %d new vf_ref = %d\r\n", + __func__, index, + cm->buffer_pool->frame_bufs[index].buf.vf_ref); +} + +static int frame_duration_adapt(struct VP9Decoder_s *pbi, struct vframe_s *vf, u32 valid) +{ + u32 old_duration, pts_duration = 0; + u32 pts = vf->pts; + + if (pbi->get_frame_dur == true) + return true; + + pbi->frame_cnt_window++; + if (!(pbi->vp9_first_pts_ready == 1)) { + if (valid) { + pbi->pts1 = pts; + pbi->frame_cnt_window = 0; + pbi->duration_from_pts_done = 0; + pbi->vp9_first_pts_ready = 1; + } else { + return false; + } + } else { + if (pts < pbi->pts1) { + if (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) { + pbi->pts1 = pts; + pbi->frame_cnt_window = 0; + } + } + + if (valid && (pbi->frame_cnt_window > FRAME_CNT_WINDOW_SIZE) && + (pts > pbi->pts1) && (pbi->duration_from_pts_done == 0)) { + old_duration = pbi->frame_dur; + pbi->pts2 = pts; + pts_duration = (((pbi->pts2 - pbi->pts1) * 16) / + (pbi->frame_cnt_window * 15)); + + if (close_to(pts_duration, old_duration, 2000)) { + pbi->frame_dur = pts_duration; + if ((debug & VP9_DEBUG_OUT_PTS) != 0) + pr_info("use calc duration %d\n", pts_duration); + } + + if (pbi->duration_from_pts_done == 0) { + if (close_to(pts_duration, old_duration, RATE_CORRECTION_THRESHOLD)) { + pbi->duration_from_pts_done = 1; + } else { + if (!close_to(pts_duration, + old_duration, 1000) && + !close_to(pts_duration, + pbi->frame_dur, 1000) && + close_to(pts_duration, + pbi->last_duration, 200)) { + /* frame_dur must + * wrong,recover it. + */ + pbi->frame_dur = pts_duration; + } + pbi->pts1 = pbi->pts2; + pbi->frame_cnt_window = 0; + pbi->duration_from_pts_done = 0; + } + } + pbi->last_duration = pts_duration; + } + } + return true; +} + + +static int prepare_display_buf(struct VP9Decoder_s *pbi, + struct PIC_BUFFER_CONFIG_s *pic_config) +{ + struct vframe_s *vf = NULL; + int stream_offset = pic_config->stream_offset; + unsigned short slice_type = pic_config->slice_type; + u32 pts_valid = 0, pts_us64_valid = 0; + u32 pts_save; + u64 pts_us64_save; + + if (debug & VP9_DEBUG_BUFMGR) + pr_info("%s index = %d\r\n", __func__, pic_config->index); + if (kfifo_get(&pbi->newframe_q, &vf) == 0) { + pr_info("fatal error, no available buffer slot."); + return -1; + } + + if (pic_config->double_write_mode) + set_canvas(pbi, pic_config); + + display_frame_count[pbi->index]++; + if (vf) { +#ifdef MULTI_INSTANCE_SUPPORT + if (vdec_frame_based(hw_to_vdec(pbi))) { + vf->pts = pic_config->pts; + vf->pts_us64 = pic_config->pts64; + if (vf->pts != 0 || vf->pts_us64 != 0) { + pts_valid = 1; + pts_us64_valid = 1; + } else { + pts_valid = 0; + pts_us64_valid = 0; + } + } else +#endif + /* if (pts_lookup_offset(PTS_TYPE_VIDEO, + * stream_offset, &vf->pts, 0) != 0) { + */ + if (pts_lookup_offset_us64 + (PTS_TYPE_VIDEO, stream_offset, &vf->pts, 0, + &vf->pts_us64) != 0) { +#ifdef DEBUG_PTS + pbi->pts_missed++; +#endif + vf->pts = 0; + vf->pts_us64 = 0; + pts_valid = 0; + pts_us64_valid = 0; + } else { +#ifdef DEBUG_PTS + pbi->pts_hit++; +#endif + pts_valid = 1; + pts_us64_valid = 1; + } + + pts_save = vf->pts; + pts_us64_save = vf->pts_us64; + if (pbi->pts_unstable) { + frame_duration_adapt(pbi, vf, pts_valid); + if (pbi->duration_from_pts_done) { + pbi->pts_mode = PTS_NONE_REF_USE_DURATION; + } else { + if (pts_valid || pts_us64_valid) + pbi->pts_mode = PTS_NORMAL; + } + } + + if ((pbi->pts_mode == PTS_NORMAL) && (vf->pts != 0) + && pbi->get_frame_dur) { + int pts_diff = (int)vf->pts - pbi->last_lookup_pts; + + if (pts_diff < 0) { + pbi->pts_mode_switching_count++; + pbi->pts_mode_recovery_count = 0; + + if (pbi->pts_mode_switching_count >= + PTS_MODE_SWITCHING_THRESHOLD) { + pbi->pts_mode = + PTS_NONE_REF_USE_DURATION; + pr_info + ("HEVC: switch to n_d mode.\n"); + } + + } else { + int p = PTS_MODE_SWITCHING_RECOVERY_THREASHOLD; + + pbi->pts_mode_recovery_count++; + if (pbi->pts_mode_recovery_count > p) { + pbi->pts_mode_switching_count = 0; + pbi->pts_mode_recovery_count = 0; + } + } + } + + if (vf->pts != 0) + pbi->last_lookup_pts = vf->pts; + + if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION) + && (slice_type != KEY_FRAME)) + vf->pts = pbi->last_pts + DUR2PTS(pbi->frame_dur); + pbi->last_pts = vf->pts; + + if (vf->pts_us64 != 0) + pbi->last_lookup_pts_us64 = vf->pts_us64; + + if ((pbi->pts_mode == PTS_NONE_REF_USE_DURATION) + && (slice_type != KEY_FRAME)) { + vf->pts_us64 = + pbi->last_pts_us64 + + (DUR2PTS(pbi->frame_dur) * 100 / 9); + } + pbi->last_pts_us64 = vf->pts_us64; + if ((debug & VP9_DEBUG_OUT_PTS) != 0) { + pr_info + ("VP9 dec out pts: pts_mode=%d,dur=%d,pts(%d,%lld)(%d,%lld)\n", + pbi->pts_mode, pbi->frame_dur, vf->pts, + vf->pts_us64, pts_save, pts_us64_save); + } + + if (pbi->pts_mode == PTS_NONE_REF_USE_DURATION) { + vf->disp_pts = vf->pts; + vf->disp_pts_us64 = vf->pts_us64; + vf->pts = pts_save; + vf->pts_us64 = pts_us64_save; + } else { + vf->disp_pts = 0; + vf->disp_pts_us64 = 0; + } + + vf->index = 0xff00 | pic_config->index; + + if (pic_config->double_write_mode & 0x10) { + /* double write only */ + vf->compBodyAddr = 0; + vf->compHeadAddr = 0; + } else { +#ifdef VP9_10B_MMU + vf->compBodyAddr = 0; + vf->compHeadAddr = pic_config->header_adr; +#else + vf->compBodyAddr = pic_config->mc_y_adr; /*body adr*/ + vf->compHeadAddr = pic_config->mc_y_adr + + pic_config->comp_body_size; + /*head adr*/ +#endif + } + if (pic_config->double_write_mode) { + vf->type = VIDTYPE_PROGRESSIVE | + VIDTYPE_VIU_FIELD; + vf->type |= VIDTYPE_VIU_NV21; + if (pic_config->double_write_mode == 3) { + vf->type |= VIDTYPE_COMPRESS; +#ifdef VP9_10B_MMU + vf->type |= VIDTYPE_SCATTER; +#endif + } +#ifdef MULTI_INSTANCE_SUPPORT + if (pbi->m_ins_flag) { + vf->canvas0Addr = vf->canvas1Addr = -1; + vf->plane_num = 2; + vf->canvas0_config[0] = + pic_config->canvas_config[0]; + vf->canvas0_config[1] = + pic_config->canvas_config[1]; + vf->canvas1_config[0] = + pic_config->canvas_config[0]; + vf->canvas1_config[1] = + pic_config->canvas_config[1]; + + } else +#endif + vf->canvas0Addr = vf->canvas1Addr = + spec2canvas(pic_config); + } else { + vf->canvas0Addr = vf->canvas1Addr = 0; + vf->type = VIDTYPE_COMPRESS | VIDTYPE_VIU_FIELD; +#ifdef VP9_10B_MMU + vf->type |= VIDTYPE_SCATTER; +#endif + } + + switch (pic_config->bit_depth) { + case VPX_BITS_8: + vf->bitdepth = BITDEPTH_Y8 | + BITDEPTH_U8 | BITDEPTH_V8; + break; + case VPX_BITS_10: + case VPX_BITS_12: + vf->bitdepth = BITDEPTH_Y10 | + BITDEPTH_U10 | BITDEPTH_V10; + break; + default: + vf->bitdepth = BITDEPTH_Y10 | + BITDEPTH_U10 | BITDEPTH_V10; + break; + } + if ((vf->type & VIDTYPE_COMPRESS) == 0) + vf->bitdepth = + BITDEPTH_Y8 | BITDEPTH_U8 | BITDEPTH_V8; + if (pic_config->bit_depth == VPX_BITS_8) + vf->bitdepth |= BITDEPTH_SAVING_MODE; + + set_frame_info(pbi, vf); + /* if((vf->width!=pic_config->width)| + * (vf->height!=pic_config->height)) + */ + /* pr_info("aaa: %d/%d, %d/%d\n", + vf->width,vf->height, pic_config->width, + pic_config->height); */ + vf->width = pic_config->y_crop_width / + get_double_write_ratio(pbi, + pic_config->double_write_mode); + vf->height = pic_config->y_crop_height / + get_double_write_ratio(pbi, + pic_config->double_write_mode); + if (force_w_h != 0) { + vf->width = (force_w_h >> 16) & 0xffff; + vf->height = force_w_h & 0xffff; + } + vf->compWidth = pic_config->y_crop_width; + vf->compHeight = pic_config->y_crop_height; + if (force_fps & 0x100) { + u32 rate = force_fps & 0xff; + + if (rate) + vf->duration = 96000/rate; + else + vf->duration = 0; + } +#ifdef VP9_10B_MMU + if (vf->type & VIDTYPE_SCATTER) { + vf->mem_handle = decoder_mmu_box_get_mem_handle( + pbi->mmu_box, + pic_config->index); + vf->mem_head_handle = decoder_bmmu_box_get_mem_handle( + pbi->bmmu_box, + HEADER_BUFFER_IDX(pic_config->index)); + } else { + vf->mem_handle = decoder_bmmu_box_get_mem_handle( + pbi->bmmu_box, + VF_BUFFER_IDX(pic_config->index)); + vf->mem_head_handle = decoder_bmmu_box_get_mem_handle( + pbi->bmmu_box, + HEADER_BUFFER_IDX(pic_config->index)); + } +#else + vf->mem_handle = decoder_bmmu_box_get_mem_handle( + pbi->bmmu_box, + VF_BUFFER_IDX(pic_config->index)); +#endif + if (!(pic_config->y_crop_width == 196 + && pic_config->y_crop_height == 196 + && (debug & VP9_DEBUG_NO_TRIGGER_FRAME) == 0 + )) { + inc_vf_ref(pbi, pic_config->index); + kfifo_put(&pbi->display_q, (const struct vframe_s *)vf); + pbi->vf_pre_count++; +#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + /*count info*/ + gvs->frame_dur = pbi->frame_dur; + vdec_count_info(gvs, 0, stream_offset); +#endif + vf_notify_receiver(pbi->provider_name, + VFRAME_EVENT_PROVIDER_VFRAME_READY, NULL); + } else { + pbi->stat |= VP9_TRIGGER_FRAME_DONE; + hevc_source_changed(VFORMAT_VP9, 196, 196, 30); + pr_debug("[%s %d] drop trigger frame width %d height %d state 0x%x\n", + __func__, __LINE__, vf->width, + vf->height, pbi->stat); + } + } + + return 0; +} + +static void get_rpm_param(union param_u *params) +{ + int i; + unsigned int data32; + + if (debug & VP9_DEBUG_BUFMGR) + pr_info("enter %s\r\n", __func__); + for (i = 0; i < 128; i++) { + do { + data32 = READ_VREG(RPM_CMD_REG); + /*pr_info("%x\n", data32);*/ + } while ((data32 & 0x10000) == 0); + params->l.data[i] = data32&0xffff; + /*pr_info("%x\n", data32);*/ + WRITE_VREG(RPM_CMD_REG, 0); + } + if (debug & VP9_DEBUG_BUFMGR) + pr_info("leave %s\r\n", __func__); +} +static void debug_buffer_mgr_more(struct VP9Decoder_s *pbi) +{ + int i; + + if (!(debug & VP9_DEBUG_BUFMGR_MORE)) + return; + pr_info("vp9_param: (%d)\n", pbi->slice_idx); + for (i = 0; i < (RPM_END-RPM_BEGIN); i++) { + pr_info("%04x ", vp9_param.l.data[i]); + if (((i + 1) & 0xf) == 0) + pr_info("\n"); + } + pr_info("=============param==========\r\n"); + pr_info("profile %x\r\n", vp9_param.p.profile); + pr_info("show_existing_frame %x\r\n", + vp9_param.p.show_existing_frame); + pr_info("frame_to_show_idx %x\r\n", + vp9_param.p.frame_to_show_idx); + pr_info("frame_type %x\r\n", vp9_param.p.frame_type); + pr_info("show_frame %x\r\n", vp9_param.p.show_frame); + pr_info("e.r.r.o.r_resilient_mode %x\r\n", + vp9_param.p.error_resilient_mode); + pr_info("intra_only %x\r\n", vp9_param.p.intra_only); + pr_info("display_size_present %x\r\n", + vp9_param.p.display_size_present); + pr_info("reset_frame_context %x\r\n", + vp9_param.p.reset_frame_context); + pr_info("refresh_frame_flags %x\r\n", + vp9_param.p.refresh_frame_flags); + pr_info("bit_depth %x\r\n", vp9_param.p.bit_depth); + pr_info("width %x\r\n", vp9_param.p.width); + pr_info("height %x\r\n", vp9_param.p.height); + pr_info("display_width %x\r\n", vp9_param.p.display_width); + pr_info("display_height %x\r\n", vp9_param.p.display_height); + pr_info("ref_info %x\r\n", vp9_param.p.ref_info); + pr_info("same_frame_size %x\r\n", vp9_param.p.same_frame_size); + if (!(debug & VP9_DEBUG_DBG_LF_PRINT)) + return; + pr_info("mode_ref_delta_enabled: 0x%x\r\n", + vp9_param.p.mode_ref_delta_enabled); + pr_info("sharpness_level: 0x%x\r\n", + vp9_param.p.sharpness_level); + pr_info("ref_deltas: 0x%x, 0x%x, 0x%x, 0x%x\r\n", + vp9_param.p.ref_deltas[0], vp9_param.p.ref_deltas[1], + vp9_param.p.ref_deltas[2], vp9_param.p.ref_deltas[3]); + pr_info("mode_deltas: 0x%x, 0x%x\r\n", vp9_param.p.mode_deltas[0], + vp9_param.p.mode_deltas[1]); + pr_info("filter_level: 0x%x\r\n", vp9_param.p.filter_level); + pr_info("seg_enabled: 0x%x\r\n", vp9_param.p.seg_enabled); + pr_info("seg_abs_delta: 0x%x\r\n", vp9_param.p.seg_abs_delta); + pr_info("seg_lf_feature_enabled: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n", + (vp9_param.p.seg_lf_info[0]>>15 & 1), + (vp9_param.p.seg_lf_info[1]>>15 & 1), + (vp9_param.p.seg_lf_info[2]>>15 & 1), + (vp9_param.p.seg_lf_info[3]>>15 & 1), + (vp9_param.p.seg_lf_info[4]>>15 & 1), + (vp9_param.p.seg_lf_info[5]>>15 & 1), + (vp9_param.p.seg_lf_info[6]>>15 & 1), + (vp9_param.p.seg_lf_info[7]>>15 & 1)); + pr_info("seg_lf_feature_data: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\r\n", + (vp9_param.p.seg_lf_info[0] & 0x13f), + (vp9_param.p.seg_lf_info[1] & 0x13f), + (vp9_param.p.seg_lf_info[2] & 0x13f), + (vp9_param.p.seg_lf_info[3] & 0x13f), + (vp9_param.p.seg_lf_info[4] & 0x13f), + (vp9_param.p.seg_lf_info[5] & 0x13f), + (vp9_param.p.seg_lf_info[6] & 0x13f), + (vp9_param.p.seg_lf_info[7] & 0x13f)); + +} + +#ifdef VP9_10B_MMU +static void vp9_recycle_mmu_buf_tail(struct VP9Decoder_s *pbi) +{ + struct VP9_Common_s *const cm = &pbi->common; + if (cm->cur_fb_idx_mmu != INVALID_IDX) { + if (pbi->used_4k_num == -1) + pbi->used_4k_num = + (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16); + decoder_mmu_box_free_idx_tail(pbi->mmu_box, + cm->cur_fb_idx_mmu, pbi->used_4k_num); + + cm->cur_fb_idx_mmu = INVALID_IDX; + pbi->used_4k_num = -1; + } +} + +#ifdef MULTI_INSTANCE_SUPPORT +static void vp9_recycle_mmu_buf(struct VP9Decoder_s *pbi) +{ + struct VP9_Common_s *const cm = &pbi->common; + if (cm->cur_fb_idx_mmu != INVALID_IDX) { + decoder_mmu_box_free_idx(pbi->mmu_box, + cm->cur_fb_idx_mmu); + + cm->cur_fb_idx_mmu = INVALID_IDX; + pbi->used_4k_num = -1; + } +} +#endif +#endif + +static void dec_again_process(struct VP9Decoder_s *pbi) +{ + amhevc_stop(); + pbi->dec_result = DEC_RESULT_AGAIN; + if (pbi->process_state == + PROC_STATE_DECODESLICE) { + pbi->process_state = + PROC_STATE_SENDAGAIN; + } + reset_process_time(pbi); + vdec_schedule_work(&pbi->work); +} + +int continue_decoding(struct VP9Decoder_s *pbi) +{ + int ret; + int i; + struct VP9_Common_s *const cm = &pbi->common; + debug_buffer_mgr_more(pbi); + + bit_depth_luma = vp9_param.p.bit_depth; + bit_depth_chroma = vp9_param.p.bit_depth; + + if (pbi->process_state != PROC_STATE_SENDAGAIN) { + ret = vp9_bufmgr_process(pbi, &vp9_param); + if (!pbi->m_ins_flag) + pbi->slice_idx++; + } else { + union param_u *params = &vp9_param; +#ifdef VP9_10B_MMU + ret = vp9_alloc_mmu(pbi, + cm->new_fb_idx, + params->p.width, + params->p.height, + params->p.bit_depth, + pbi->frame_mmu_map_addr); + if (ret >= 0) + cm->cur_fb_idx_mmu = cm->new_fb_idx; + else + pr_err("can't alloc need mmu1,idx %d ret =%d\n", + cm->new_fb_idx, + ret); +#else + ret = 0; +#endif + WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, + (params->p.height << 16) | params->p.width); + } + if (ret < 0) { + pr_info("vp9_bufmgr_process=> %d, VP9_10B_DISCARD_NAL\r\n", + ret); + WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL); + cm->show_frame = 0; +#ifdef VP9_10B_MMU + vp9_recycle_mmu_buf(pbi); +#endif +#ifdef MULTI_INSTANCE_SUPPORT + if (pbi->m_ins_flag) { + pbi->dec_result = DEC_RESULT_DONE; +#ifdef SUPPORT_FB_DECODING + if (pbi->used_stage_buf_num == 0) +#endif + amhevc_stop(); + vdec_schedule_work(&pbi->work); + } +#endif + return ret; + } else if (ret == 0) { + struct PIC_BUFFER_CONFIG_s *cur_pic_config + = &cm->cur_frame->buf; + cur_pic_config->decode_idx = pbi->frame_count; + + if (pbi->process_state != PROC_STATE_SENDAGAIN) { + if (!pbi->m_ins_flag) { + pbi->frame_count++; + decode_frame_count[pbi->index] + = pbi->frame_count; + } +#ifdef MULTI_INSTANCE_SUPPORT + if (pbi->chunk) { + cur_pic_config->pts = pbi->chunk->pts; + cur_pic_config->pts64 = pbi->chunk->pts64; + } +#endif + } + /*pr_info("Decode Frame Data %d\n", pbi->frame_count);*/ + config_pic_size(pbi, vp9_param.p.bit_depth); + + if ((pbi->common.frame_type != KEY_FRAME) + && (!pbi->common.intra_only)) { + config_mc_buffer(pbi, vp9_param.p.bit_depth); +#ifdef SUPPORT_FB_DECODING + if (pbi->used_stage_buf_num == 0) +#endif + config_mpred_hw(pbi); + } else { +#ifdef SUPPORT_FB_DECODING + if (pbi->used_stage_buf_num == 0) +#endif + clear_mpred_hw(pbi); + } +#ifdef MCRCC_ENABLE + if (mcrcc_cache_alg_flag) + config_mcrcc_axi_hw_new(pbi); + else + config_mcrcc_axi_hw(pbi); +#endif + config_sao_hw(pbi, &vp9_param); + +#ifdef VP9_LPF_LVL_UPDATE + /* + * Get loop filter related picture level parameters from Parser + */ + pbi->lf->mode_ref_delta_enabled = vp9_param.p.mode_ref_delta_enabled; + pbi->lf->sharpness_level = vp9_param.p.sharpness_level; + for (i = 0; i < 4; i++) + pbi->lf->ref_deltas[i] = vp9_param.p.ref_deltas[i]; + for (i = 0; i < 2; i++) + pbi->lf->mode_deltas[i] = vp9_param.p.mode_deltas[i]; + pbi->default_filt_lvl = vp9_param.p.filter_level; + pbi->seg_4lf->enabled = vp9_param.p.seg_enabled; + pbi->seg_4lf->abs_delta = vp9_param.p.seg_abs_delta; + for (i = 0; i < MAX_SEGMENTS; i++) + pbi->seg_4lf->feature_mask[i] = (vp9_param.p.seg_lf_info[i] & + 0x8000) ? (1 << SEG_LVL_ALT_LF) : 0; + for (i = 0; i < MAX_SEGMENTS; i++) + pbi->seg_4lf->feature_data[i][SEG_LVL_ALT_LF] + = (vp9_param.p.seg_lf_info[i] + & 0x100) ? -(vp9_param.p.seg_lf_info[i] + & 0x3f) : (vp9_param.p.seg_lf_info[i] & 0x3f); + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) { + /*Set pipeline mode*/ + uint32_t lpf_data32 = READ_VREG(HEVC_DBLK_CFGB); + /*dblk pipeline mode=1 for performance*/ + if (vp9_param.p.width >= 1280) + lpf_data32 |= (0x1 << 4); + else + lpf_data32 &= ~(0x3 << 4); + WRITE_VREG(HEVC_DBLK_CFGB, lpf_data32); + } + /* + * Update loop filter Thr/Lvl table for every frame + */ + /*pr_info + ("vp9_loop_filter (run before every frame decoding start)\n");*/ + vp9_loop_filter_frame_init(pbi->seg_4lf, + pbi->lfi, pbi->lf, pbi->default_filt_lvl); +#endif + /*pr_info("HEVC_DEC_STATUS_REG <= VP9_10B_DECODE_SLICE\n");*/ + WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE); + } else { + pr_info("Skip search next start code\n"); + cm->prev_fb_idx = INVALID_IDX; + /*skip, search next start code*/ + WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DECODE_SLICE); + } + pbi->process_state = PROC_STATE_DECODESLICE; +#ifdef VP9_10B_MMU + if (pbi->last_put_idx >= 0 && pbi->last_put_idx < pbi->used_buf_num) { + struct RefCntBuffer_s *frame_bufs = cm->buffer_pool->frame_bufs; + int i = pbi->last_put_idx; + /*free not used buffers.*/ + if ((frame_bufs[i].ref_count == 0) && + (frame_bufs[i].buf.vf_ref == 0) && + (frame_bufs[i].buf.index != -1)) { + decoder_mmu_box_free_idx(pbi->mmu_box, i); + } + pbi->last_put_idx = -1; + } +#endif + return ret; +} + +static irqreturn_t vvp9_isr_thread_fn(int irq, void *data) +{ + struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data; + unsigned int dec_status = pbi->dec_status; + int i; + + /*if (pbi->wait_buf) + * pr_info("set wait_buf to 0\r\n"); + */ + if (pbi->eos) + return IRQ_HANDLED; + pbi->wait_buf = 0; +#ifdef MULTI_INSTANCE_SUPPORT +#ifdef SUPPORT_FB_DECODING +#ifdef FB_DECODING_TEST_SCHEDULE + if (pbi->s1_test_cmd == TEST_SET_PIC_DONE) + dec_status = HEVC_DECPIC_DATA_DONE; + else if (pbi->s1_test_cmd == TEST_SET_S2_DONE + && dec_status == HEVC_DECPIC_DATA_DONE) + dec_status = HEVC_S2_DECODING_DONE; + pbi->s1_test_cmd = TEST_SET_NONE; +#else + /*if (irq != VDEC_IRQ_0) + dec_status = HEVC_S2_DECODING_DONE;*/ +#endif + if (dec_status == HEVC_S2_DECODING_DONE) { + pbi->dec_result = DEC_RESULT_DONE; + vdec_schedule_work(&pbi->work); +#ifdef FB_DECODING_TEST_SCHEDULE + amhevc_stop(); + pbi->dec_s1_result = DEC_S1_RESULT_DONE; + vdec_schedule_work(&pbi->s1_work); +#endif + } else +#endif + if ((dec_status == HEVC_NAL_DECODE_DONE) || + (dec_status == HEVC_SEARCH_BUFEMPTY) || + (dec_status == HEVC_DECODE_BUFEMPTY) + ) { + if (pbi->m_ins_flag) { + reset_process_time(pbi); + if (!vdec_frame_based(hw_to_vdec(pbi))) + dec_again_process(pbi); + else { + pbi->dec_result = DEC_RESULT_GET_DATA; + vdec_schedule_work(&pbi->work); + } + } + pbi->process_busy = 0; + return IRQ_HANDLED; + } else if (dec_status == HEVC_DECPIC_DATA_DONE) { + if (pbi->m_ins_flag) { +#ifdef SUPPORT_FB_DECODING + if (pbi->used_stage_buf_num > 0) { + reset_process_time(pbi); + inc_s1_pos(pbi); + trigger_schedule(pbi); +#ifdef FB_DECODING_TEST_SCHEDULE + pbi->s1_test_cmd = TEST_SET_S2_DONE; +#else + amhevc_stop(); + pbi->dec_s1_result = DEC_S1_RESULT_DONE; + vdec_schedule_work(&pbi->s1_work); +#endif + } else +#endif + { + reset_process_time(pbi); + pbi->dec_result = DEC_RESULT_DONE; + amhevc_stop(); + if (mcrcc_cache_alg_flag) + dump_hit_rate(pbi); + vdec_schedule_work(&pbi->work); + } + } + + pbi->process_busy = 0; + return IRQ_HANDLED; + } +#endif + + if (dec_status == VP9_EOS) { +#ifdef MULTI_INSTANCE_SUPPORT + if (pbi->m_ins_flag) + reset_process_time(pbi); +#endif + + pr_info("VP9_EOS, flush buffer\r\n"); + + vp9_bufmgr_postproc(pbi); + + pr_info("send VP9_10B_DISCARD_NAL\r\n"); + WRITE_VREG(HEVC_DEC_STATUS_REG, VP9_10B_DISCARD_NAL); + pbi->process_busy = 0; +#ifdef MULTI_INSTANCE_SUPPORT + if (pbi->m_ins_flag) { + pbi->dec_result = DEC_RESULT_DONE; + amhevc_stop(); + vdec_schedule_work(&pbi->work); + } +#endif + return IRQ_HANDLED; + } else if (dec_status == HEVC_DECODE_OVER_SIZE) { + pr_info("vp9 decode oversize !!\n"); + debug |= (VP9_DEBUG_DIS_LOC_ERROR_PROC | + VP9_DEBUG_DIS_SYS_ERROR_PROC); + pbi->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW; +#ifdef MULTI_INSTANCE_SUPPORT + if (pbi->m_ins_flag) + reset_process_time(pbi); +#endif + return IRQ_HANDLED; + } + + if (dec_status != VP9_HEAD_PARSER_DONE) { + pbi->process_busy = 0; + return IRQ_HANDLED; + } + +#ifdef MULTI_INSTANCE_SUPPORT + if (pbi->m_ins_flag) + reset_process_time(pbi); +#endif + if (pbi->process_state != PROC_STATE_SENDAGAIN +#ifdef SUPPORT_FB_DECODING + && pbi->used_stage_buf_num == 0 +#endif + ) { +#ifdef VP9_10B_MMU + vp9_recycle_mmu_buf_tail(pbi); +#endif + + if (pbi->frame_count > 0) + vp9_bufmgr_postproc(pbi); + } + + if (debug & VP9_DEBUG_SEND_PARAM_WITH_REG) { + get_rpm_param(&vp9_param); + } else { + dma_sync_single_for_cpu( + amports_get_dma_device(), + pbi->rpm_phy_addr, + RPM_BUF_SIZE, + DMA_FROM_DEVICE); +#ifdef SUPPORT_FB_DECODING + if (pbi->used_stage_buf_num > 0) { + reset_process_time(pbi); + get_s1_buf(pbi); + + if (get_mv_buf(pbi, + &pbi->s1_mv_buf_index, + &pbi->s1_mpred_mv_wr_start_addr + ) < 0) { + vp9_print(pbi, 0, + "%s: Error get_mv_buf fail\n", + __func__); + } + + if (pbi->s1_buf == NULL) { + vp9_print(pbi, 0, + "%s: Error get_s1_buf fail\n", + __func__); + pbi->process_busy = 0; + return IRQ_HANDLED; + } + + for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) { + int ii; + for (ii = 0; ii < 4; ii++) { + pbi->s1_buf->rpm[i + 3 - ii] = + pbi->rpm_ptr[i + 3 - ii]; + pbi->s1_param.l.data[i + ii] = + pbi->rpm_ptr[i + 3 - ii]; + } + } + + mpred_process(pbi); +#ifdef FB_DECODING_TEST_SCHEDULE + pbi->dec_s1_result = + DEC_S1_RESULT_TEST_TRIGGER_DONE; + vdec_schedule_work(&pbi->s1_work); +#else + WRITE_VREG(HEVC_ASSIST_FB_MMU_MAP_ADDR, + pbi->stage_mmu_map_phy_addr + + pbi->s1_buf->index * STAGE_MMU_MAP_SIZE); + + start_s1_decoding(pbi); +#endif + start_process_time(pbi); + pbi->process_busy = 0; + return IRQ_HANDLED; + } else +#endif + for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) { + int ii; + for (ii = 0; ii < 4; ii++) + vp9_param.l.data[i + ii] = + pbi->rpm_ptr[i + 3 - ii]; + } + } + + continue_decoding(pbi); + pbi->process_busy = 0; + +#ifdef MULTI_INSTANCE_SUPPORT + if (pbi->m_ins_flag) + start_process_time(pbi); +#endif + + return IRQ_HANDLED; +} + +static irqreturn_t vvp9_isr(int irq, void *data) +{ + int i; + unsigned int dec_status; + struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)data; + unsigned int adapt_prob_status; + struct VP9_Common_s *const cm = &pbi->common; + uint debug_tag; + + WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1); + + dec_status = READ_VREG(HEVC_DEC_STATUS_REG); + adapt_prob_status = READ_VREG(VP9_ADAPT_PROB_REG); + if (!pbi) + return IRQ_HANDLED; + if (pbi->init_flag == 0) + return IRQ_HANDLED; + if (pbi->process_busy)/*on process.*/ + return IRQ_HANDLED; + pbi->dec_status = dec_status; + pbi->process_busy = 1; + if (debug & VP9_DEBUG_BUFMGR) + pr_info("vp9 isr (%d) dec status = 0x%x, lcu 0x%x shiftbyte 0x%x (%x %x lev %x, wr %x, rd %x)\n", + irq, + dec_status, READ_VREG(HEVC_PARSER_LCU_START), + READ_VREG(HEVC_SHIFT_BYTE_COUNT), + READ_VREG(HEVC_STREAM_START_ADDR), + READ_VREG(HEVC_STREAM_END_ADDR), + READ_VREG(HEVC_STREAM_LEVEL), + READ_VREG(HEVC_STREAM_WR_PTR), + READ_VREG(HEVC_STREAM_RD_PTR) + ); +#ifdef SUPPORT_FB_DECODING + /*if (irq != VDEC_IRQ_0) + return IRQ_WAKE_THREAD;*/ +#endif + + debug_tag = READ_HREG(DEBUG_REG1); + if (debug_tag & 0x10000) { + dma_sync_single_for_cpu( + amports_get_dma_device(), + pbi->lmem_phy_addr, + LMEM_BUF_SIZE, + DMA_FROM_DEVICE); + + pr_info("LMEM:\n", READ_HREG(DEBUG_REG1)); + for (i = 0; i < 0x400; i += 4) { + int ii; + if ((i & 0xf) == 0) + pr_info("%03x: ", i); + for (ii = 0; ii < 4; ii++) { + pr_info("%04x ", + pbi->lmem_ptr[i + 3 - ii]); + } + if (((i + ii) & 0xf) == 0) + pr_info("\n"); + } + + if ((udebug_pause_pos == (debug_tag & 0xffff)) && + (udebug_pause_decode_idx == 0 || + udebug_pause_decode_idx == pbi->slice_idx) && + (udebug_pause_val == 0 || + udebug_pause_val == READ_HREG(DEBUG_REG2))) + pbi->ucode_pause_pos = udebug_pause_pos; + else if (debug_tag & 0x20000) + pbi->ucode_pause_pos = 0xffffffff; + if (pbi->ucode_pause_pos) + reset_process_time(pbi); + else + WRITE_HREG(DEBUG_REG1, 0); + } else if (debug_tag != 0) { + pr_info( + "dbg%x: %x lcu %x\n", READ_HREG(DEBUG_REG1), + READ_HREG(DEBUG_REG2), + READ_VREG(HEVC_PARSER_LCU_START)); + if ((udebug_pause_pos == (debug_tag & 0xffff)) && + (udebug_pause_decode_idx == 0 || + udebug_pause_decode_idx == pbi->slice_idx) && + (udebug_pause_val == 0 || + udebug_pause_val == READ_HREG(DEBUG_REG2))) + pbi->ucode_pause_pos = udebug_pause_pos; + if (pbi->ucode_pause_pos) + reset_process_time(pbi); + else + WRITE_HREG(DEBUG_REG1, 0); + pbi->process_busy = 0; + return IRQ_HANDLED; + } + +#ifdef MULTI_INSTANCE_SUPPORT + if (!pbi->m_ins_flag) { +#endif + if (pbi->error_flag == 1) { + pbi->error_flag = 2; + pbi->process_busy = 0; + return IRQ_HANDLED; + } else if (pbi->error_flag == 3) { + pbi->process_busy = 0; + return IRQ_HANDLED; + } + + if (get_free_buf_count(pbi) <= 0) { + /* + if (pbi->wait_buf == 0) + pr_info("set wait_buf to 1\r\n"); + */ + pbi->wait_buf = 1; + pbi->process_busy = 0; + return IRQ_HANDLED; + } +#ifdef MULTI_INSTANCE_SUPPORT + } +#endif + if ((adapt_prob_status & 0xff) == 0xfd) { + /*VP9_REQ_ADAPT_PROB*/ + int pre_fc = (cm->frame_type == KEY_FRAME) ? 1 : 0; + uint8_t *prev_prob_b = + ((uint8_t *)pbi->prob_buffer_addr) + + ((adapt_prob_status >> 8) * 0x1000); + uint8_t *cur_prob_b = + ((uint8_t *)pbi->prob_buffer_addr) + 0x4000; + uint8_t *count_b = (uint8_t *)pbi->count_buffer_addr; +#ifdef MULTI_INSTANCE_SUPPORT + if (pbi->m_ins_flag) + reset_process_time(pbi); +#endif + adapt_coef_probs(pbi->pic_count, + (cm->last_frame_type == KEY_FRAME), + pre_fc, (adapt_prob_status >> 8), + (unsigned int *)prev_prob_b, + (unsigned int *)cur_prob_b, (unsigned int *)count_b); + + memcpy(prev_prob_b, cur_prob_b, PROB_SIZE); + WRITE_VREG(VP9_ADAPT_PROB_REG, 0); + pbi->pic_count += 1; +#ifdef MULTI_INSTANCE_SUPPORT + if (pbi->m_ins_flag) + start_process_time(pbi); +#endif + + /*return IRQ_HANDLED;*/ + } + return IRQ_WAKE_THREAD; +} + +static void vp9_set_clk(struct work_struct *work) +{ + struct VP9Decoder_s *pbi = container_of(work, + struct VP9Decoder_s, work); + + if (pbi->get_frame_dur && pbi->show_frame_num > 60 && + pbi->frame_dur > 0 && pbi->saved_resolution != + frame_width * frame_height * + (96000 / pbi->frame_dur)) { + int fps = 96000 / pbi->frame_dur; + + if (hevc_source_changed(VFORMAT_VP9, + frame_width, frame_height, fps) > 0) + pbi->saved_resolution = frame_width * + frame_height * fps; + } +} + +static void vvp9_put_timer_func(unsigned long arg) +{ + struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)arg; + struct timer_list *timer = &pbi->timer; + uint8_t empty_flag; + unsigned int buf_level; + + enum receviver_start_e state = RECEIVER_INACTIVE; + + if (pbi->m_ins_flag) { + if (hw_to_vdec(pbi)->next_status + == VDEC_STATUS_DISCONNECTED) { +#ifdef SUPPORT_FB_DECODING + if (pbi->run2_busy) + return; + + pbi->dec_s1_result = DEC_S1_RESULT_FORCE_EXIT; + vdec_schedule_work(&pbi->s1_work); +#endif + pbi->dec_result = DEC_RESULT_FORCE_EXIT; + vdec_schedule_work(&pbi->work); + pr_debug( + "vdec requested to be disconnected\n"); + return; + } + } + if (pbi->init_flag == 0) { + if (pbi->stat & STAT_TIMER_ARM) { + timer->expires = jiffies + PUT_INTERVAL; + add_timer(&pbi->timer); + } + return; + } + if (pbi->m_ins_flag == 0) { + if (vf_get_receiver(pbi->provider_name)) { + state = + vf_notify_receiver(pbi->provider_name, + VFRAME_EVENT_PROVIDER_QUREY_STATE, + NULL); + if ((state == RECEIVER_STATE_NULL) + || (state == RECEIVER_STATE_NONE)) + state = RECEIVER_INACTIVE; + } else + state = RECEIVER_INACTIVE; + + empty_flag = (READ_VREG(HEVC_PARSER_INT_STATUS) >> 6) & 0x1; + /* error watchdog */ + if (empty_flag == 0) { + /* decoder has input */ + if ((debug & VP9_DEBUG_DIS_LOC_ERROR_PROC) == 0) { + + buf_level = READ_VREG(HEVC_STREAM_LEVEL); + /* receiver has no buffer to recycle */ + if ((state == RECEIVER_INACTIVE) && + (kfifo_is_empty(&pbi->display_q) && + buf_level > 0x200) + ) { + WRITE_VREG + (HEVC_ASSIST_MBOX0_IRQ_REG, + 0x1); + } + } + + if ((debug & VP9_DEBUG_DIS_SYS_ERROR_PROC) == 0) { + /* receiver has no buffer to recycle */ + /*if ((state == RECEIVER_INACTIVE) && + * (kfifo_is_empty(&pbi->display_q))) { + *pr_info("vp9 something error,need reset\n"); + *} + */ + } + } + } +#ifdef MULTI_INSTANCE_SUPPORT + else { + if ( + (decode_timeout_val > 0) && + (pbi->start_process_time > 0) && + ((1000 * (jiffies - pbi->start_process_time) / HZ) + > decode_timeout_val) + ) { + int current_lcu_idx = + READ_VREG(HEVC_PARSER_LCU_START) + & 0xffffff; + if (pbi->last_lcu_idx == current_lcu_idx) { + if (pbi->decode_timeout_count > 0) + pbi->decode_timeout_count--; + if (pbi->decode_timeout_count == 0) { + if (input_frame_based( + hw_to_vdec(pbi)) || + (READ_VREG(HEVC_STREAM_LEVEL) > 0x200)) + timeout_process(pbi); + else { + vp9_print(pbi, 0, + "timeout & empty, again\n"); + dec_again_process(pbi); + } + } + } else { + start_process_time(pbi); + pbi->last_lcu_idx = current_lcu_idx; + } + } + } +#endif + + if ((pbi->ucode_pause_pos != 0) && + (pbi->ucode_pause_pos != 0xffffffff) && + udebug_pause_pos != pbi->ucode_pause_pos) { + pbi->ucode_pause_pos = 0; + WRITE_HREG(DEBUG_REG1, 0); + } +#ifdef MULTI_INSTANCE_SUPPORT + if (debug & VP9_DEBUG_FORCE_SEND_AGAIN) { + pr_info( + "Force Send Again\r\n"); + debug &= ~VP9_DEBUG_FORCE_SEND_AGAIN; + reset_process_time(pbi); + pbi->dec_result = DEC_RESULT_AGAIN; + if (pbi->process_state == + PROC_STATE_DECODESLICE) { + pbi->process_state = + PROC_STATE_SENDAGAIN; + } + amhevc_stop(); + + vdec_schedule_work(&pbi->work); + } + + if (debug & VP9_DEBUG_DUMP_DATA) { + debug &= ~VP9_DEBUG_DUMP_DATA; + vp9_print(pbi, 0, + "%s: chunk size 0x%x off 0x%x sum 0x%x\n", + __func__, + pbi->chunk->size, + pbi->chunk->offset, + get_data_check_sum(pbi, pbi->chunk->size) + ); + dump_data(pbi, pbi->chunk->size); + } +#endif + if (debug & VP9_DEBUG_DUMP_PIC_LIST) { + dump_pic_list(pbi); + debug &= ~VP9_DEBUG_DUMP_PIC_LIST; + } + if (debug & VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC) { + WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1); + debug &= ~VP9_DEBUG_TRIG_SLICE_SEGMENT_PROC; + } + /*if (debug & VP9_DEBUG_HW_RESET) { + }*/ + + if (radr != 0) { + if (rval != 0) { + WRITE_VREG(radr, rval); + pr_info("WRITE_VREG(%x,%x)\n", radr, rval); + } else + pr_info("READ_VREG(%x)=%x\n", radr, READ_VREG(radr)); + rval = 0; + radr = 0; + } + if (pop_shorts != 0) { + int i; + u32 sum = 0; + + pr_info("pop stream 0x%x shorts\r\n", pop_shorts); + for (i = 0; i < pop_shorts; i++) { + u32 data = + (READ_HREG(HEVC_SHIFTED_DATA) >> 16); + WRITE_HREG(HEVC_SHIFT_COMMAND, + (1<<7)|16); + if ((i & 0xf) == 0) + pr_info("%04x:", i); + pr_info("%04x ", data); + if (((i + 1) & 0xf) == 0) + pr_info("\r\n"); + sum += data; + } + pr_info("\r\nsum = %x\r\n", sum); + pop_shorts = 0; + } + if (dbg_cmd != 0) { + if (dbg_cmd == 1) { + u32 disp_laddr; + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB && + get_double_write_mode(pbi) == 0) { + disp_laddr = + READ_VCBUS_REG(AFBC_BODY_BADDR) << 4; + } else { + struct canvas_s cur_canvas; + + canvas_read((READ_VCBUS_REG(VD1_IF0_CANVAS0) + & 0xff), &cur_canvas); + disp_laddr = cur_canvas.addr; + } + pr_info("current displayed buffer address %x\r\n", + disp_laddr); + } + dbg_cmd = 0; + } + /*don't changed at start.*/ + schedule_work(&pbi->set_clk_work); + + timer->expires = jiffies + PUT_INTERVAL; + add_timer(timer); +} + + +int vvp9_dec_status(struct vdec_s *vdec, struct vdec_info *vstatus) +{ + struct VP9Decoder_s *vp9 = + (struct VP9Decoder_s *)vdec->private; + vstatus->frame_width = frame_width; + vstatus->frame_height = frame_height; + if (vp9->frame_dur != 0) + vstatus->frame_rate = 96000 / vp9->frame_dur; + else + vstatus->frame_rate = -1; + vstatus->error_count = 0; + vstatus->status = vp9->stat | vp9->fatal_error; + vstatus->frame_dur = vp9->frame_dur; +#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + vstatus->bit_rate = gvs->bit_rate; + vstatus->frame_data = gvs->frame_data; + vstatus->total_data = gvs->total_data; + vstatus->frame_count = gvs->frame_count; + vstatus->error_frame_count = gvs->error_frame_count; + vstatus->drop_frame_count = gvs->drop_frame_count; + vstatus->total_data = gvs->total_data; + vstatus->samp_cnt = gvs->samp_cnt; + vstatus->offset = gvs->offset; + snprintf(vstatus->vdec_name, sizeof(vstatus->vdec_name), + "%s", DRIVER_NAME); +#endif + return 0; +} + +int vvp9_set_isreset(struct vdec_s *vdec, int isreset) +{ + is_reset = isreset; + return 0; +} + +#if 0 +static void VP9_DECODE_INIT(void) +{ + /* enable vp9 clocks */ + WRITE_VREG(DOS_GCLK_EN3, 0xffffffff); + /* *************************************************************** */ + /* Power ON HEVC */ + /* *************************************************************** */ + /* Powerup HEVC */ + WRITE_VREG(AO_RTI_GEN_PWR_SLEEP0, + READ_VREG(AO_RTI_GEN_PWR_SLEEP0) & (~(0x3 << 6))); + WRITE_VREG(DOS_MEM_PD_HEVC, 0x0); + WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) | (0x3ffff << 2)); + WRITE_VREG(DOS_SW_RESET3, READ_VREG(DOS_SW_RESET3) & (~(0x3ffff << 2))); + /* remove isolations */ + WRITE_VREG(AO_RTI_GEN_PWR_ISO0, + READ_VREG(AO_RTI_GEN_PWR_ISO0) & (~(0x3 << 10))); + +} +#endif + +static void vvp9_prot_init(struct VP9Decoder_s *pbi, u32 mask) +{ + unsigned int data32; + /* VP9_DECODE_INIT(); */ + vp9_config_work_space_hw(pbi, mask); + if (mask & HW_MASK_BACK) + init_pic_list_hw(pbi); + + vp9_init_decoder_hw(pbi, mask); + +#ifdef VP9_LPF_LVL_UPDATE + if (mask & HW_MASK_BACK) + vp9_loop_filter_init(pbi); +#endif + + if ((mask & HW_MASK_FRONT) == 0) + return; +#if 1 + if (debug & VP9_DEBUG_BUFMGR_MORE) + pr_info("%s\n", __func__); + data32 = READ_VREG(HEVC_STREAM_CONTROL); + data32 = data32 | + (1 << 0)/*stream_fetch_enable*/ + ; + WRITE_VREG(HEVC_STREAM_CONTROL, data32); + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) { + if (debug & VP9_DEBUG_BUFMGR) + pr_info("[test.c] Config STREAM_FIFO_CTL\n"); + data32 = READ_VREG(HEVC_STREAM_FIFO_CTL); + data32 = data32 | + (1 << 29) // stream_fifo_hole + ; + WRITE_VREG(HEVC_STREAM_FIFO_CTL, data32); + } +#if 0 + data32 = READ_VREG(HEVC_SHIFT_STARTCODE); + if (data32 != 0x00000100) { + pr_info("vp9 prot init error %d\n", __LINE__); + return; + } + data32 = READ_VREG(HEVC_SHIFT_EMULATECODE); + if (data32 != 0x00000300) { + pr_info("vp9 prot init error %d\n", __LINE__); + return; + } + WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x12345678); + WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x9abcdef0); + data32 = READ_VREG(HEVC_SHIFT_STARTCODE); + if (data32 != 0x12345678) { + pr_info("vp9 prot init error %d\n", __LINE__); + return; + } + data32 = READ_VREG(HEVC_SHIFT_EMULATECODE); + if (data32 != 0x9abcdef0) { + pr_info("vp9 prot init error %d\n", __LINE__); + return; + } +#endif + WRITE_VREG(HEVC_SHIFT_STARTCODE, 0x000000001); + WRITE_VREG(HEVC_SHIFT_EMULATECODE, 0x00000300); +#endif + + + + WRITE_VREG(HEVC_WAIT_FLAG, 1); + + /* WRITE_VREG(HEVC_MPSR, 1); */ + + /* clear mailbox interrupt */ + WRITE_VREG(HEVC_ASSIST_MBOX0_CLR_REG, 1); + + /* enable mailbox interrupt */ + WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 1); + + /* disable PSCALE for hardware sharing */ + WRITE_VREG(HEVC_PSCALE_CTRL, 0); + + WRITE_VREG(DEBUG_REG1, 0x0); + /*check vps/sps/pps/i-slice in ucode*/ + WRITE_VREG(NAL_SEARCH_CTL, 0x8); + + WRITE_VREG(DECODE_STOP_POS, udebug_flag); +#ifdef SUPPORT_FB_DECODING +#ifndef FB_DECODING_TEST_SCHEDULE + if (pbi->used_stage_buf_num > 0) { + if (mask & HW_MASK_FRONT) { + data32 = READ_VREG( + HEVC_ASSIST_HED_FB_W_CTL); + data32 = data32 | + (1 << 0) /*hed_fb_wr_en*/ + ; + WRITE_VREG(HEVC_ASSIST_HED_FB_W_CTL, + data32); + } + if (mask & HW_MASK_BACK) { + data32 = READ_VREG( + HEVC_ASSIST_HED_FB_R_CTL); + while (data32 & (1 << 7)) { + /*wait finish*/ + data32 = READ_VREG( + HEVC_ASSIST_HED_FB_R_CTL); + } + data32 &= (~(0x1 << 0)); + /*hed_fb_rd_addr_auto_rd*/ + data32 &= (~(0x1 << 1)); + /*rd_id = 0, hed_rd_map_auto_halt_num, + after wr 2 ready, then start reading*/ + data32 |= (0x2 << 16); + WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL, + data32); + + data32 |= (0x1 << 11); /*hed_rd_map_auto_halt_en*/ + data32 |= (0x1 << 1); /*hed_fb_rd_addr_auto_rd*/ + data32 |= (0x1 << 0); /*hed_fb_rd_en*/ + WRITE_VREG(HEVC_ASSIST_HED_FB_R_CTL, + data32); + } + + } +#endif +#endif +} + +static int vvp9_local_init(struct VP9Decoder_s *pbi) +{ + int i; + int ret; + int width, height; + if (alloc_lf_buf(pbi) < 0) + return -1; + + pbi->gvs = vzalloc(sizeof(struct vdec_info)); + if (NULL == pbi->gvs) { + pr_info("the struct of vdec status malloc failed.\n"); + return -1; + } +#ifdef DEBUG_PTS + pbi->pts_missed = 0; + pbi->pts_hit = 0; +#endif + pbi->new_frame_displayed = 0; + pbi->last_put_idx = -1; + pbi->saved_resolution = 0; + pbi->get_frame_dur = false; + on_no_keyframe_skiped = 0; + pbi->duration_from_pts_done = 0; + pbi->vp9_first_pts_ready = 0; + pbi->frame_cnt_window = 0; + width = pbi->vvp9_amstream_dec_info.width; + height = pbi->vvp9_amstream_dec_info.height; + pbi->frame_dur = + (pbi->vvp9_amstream_dec_info.rate == + 0) ? 3200 : pbi->vvp9_amstream_dec_info.rate; + if (width && height) + pbi->frame_ar = height * 0x100 / width; +/* + *TODO:FOR VERSION + */ + pr_info("vp9: ver (%d,%d) decinfo: %dx%d rate=%d\n", vp9_version, + 0, width, height, pbi->frame_dur); + + if (pbi->frame_dur == 0) + pbi->frame_dur = 96000 / 24; + + INIT_KFIFO(pbi->display_q); + INIT_KFIFO(pbi->newframe_q); + + + for (i = 0; i < VF_POOL_SIZE; i++) { + const struct vframe_s *vf = &pbi->vfpool[i]; + + pbi->vfpool[i].index = -1; + kfifo_put(&pbi->newframe_q, vf); + } + + + ret = vp9_local_init(pbi); + + if (!pbi->pts_unstable) { + pbi->pts_unstable = + (pbi->vvp9_amstream_dec_info.rate == 0)?1:0; + pr_info("set pts unstable\n"); + } + + return ret; +} + + +#ifdef MULTI_INSTANCE_SUPPORT +static s32 vvp9_init(struct vdec_s *vdec) +{ + struct VP9Decoder_s *pbi = (struct VP9Decoder_s *)vdec->private; +#else +static s32 vvp9_init(struct VP9Decoder_s *pbi) +{ +#endif + int ret, size = -1; + int fw_size = 0x1000 * 16; + struct firmware_s *fw = NULL; + + INIT_WORK(&pbi->set_clk_work, vp9_set_clk); + + init_timer(&pbi->timer); + + pbi->stat |= STAT_TIMER_INIT; + if (vvp9_local_init(pbi) < 0) + return -EBUSY; + + fw = vmalloc(sizeof(struct firmware_s) + fw_size); + if (IS_ERR_OR_NULL(fw)) + return -ENOMEM; +#ifdef MULTI_INSTANCE_SUPPORT + if (tee_enabled()) { + size = 1; + pr_debug ("laod\n"); + } else +#endif + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) + size = get_firmware_data(VIDEO_DEC_VP9, fw->data); + else + size = get_firmware_data(VIDEO_DEC_VP9_MMU, fw->data); + + if (size < 0) { + pr_err("get firmware fail.\n"); + vfree(fw); + return -1; + } + + fw->len = fw_size; + +#ifdef MULTI_INSTANCE_SUPPORT + if (pbi->m_ins_flag) { + pbi->timer.data = (ulong) pbi; + pbi->timer.function = vvp9_put_timer_func; + pbi->timer.expires = jiffies + PUT_INTERVAL; + + /*add_timer(&pbi->timer); + + pbi->stat |= STAT_TIMER_ARM; + pbi->stat |= STAT_ISR_REG;*/ + + INIT_WORK(&pbi->work, vp9_work); +#ifdef SUPPORT_FB_DECODING + if (pbi->used_stage_buf_num > 0) + INIT_WORK(&pbi->s1_work, vp9_s1_work); +#endif + pbi->fw = fw; + + return 0; + } +#endif + + amhevc_enable(); + + if (size == 1) { + pr_info ("tee load ok\n"); + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) + ret = tee_load_video_fw((u32)VIDEO_DEC_VP9, 0); + else + ret = tee_load_video_fw((u32)VIDEO_DEC_VP9_MMU, 0); + } else + ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, fw->data); + + if (ret < 0) { + amhevc_disable(); + vfree(fw); + return -EBUSY; + } + + vfree(fw); + + pbi->stat |= STAT_MC_LOAD; + + /* enable AMRISC side protocol */ + vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK); + + if (vdec_request_threaded_irq(VDEC_IRQ_0, + vvp9_isr, + vvp9_isr_thread_fn, + IRQF_ONESHOT,/*run thread on this irq disabled*/ + "vvp9-irq", (void *)pbi)) { + pr_info("vvp9 irq register error.\n"); + amhevc_disable(); + return -ENOENT; + } + + pbi->stat |= STAT_ISR_REG; + + pbi->provider_name = PROVIDER_NAME; +#ifdef MULTI_INSTANCE_SUPPORT + vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME, + &vvp9_vf_provider, pbi); + vf_reg_provider(&vvp9_vf_prov); + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL); + if (pbi->frame_dur != 0) { + if (!is_reset) + vf_notify_receiver(pbi->provider_name, + VFRAME_EVENT_PROVIDER_FR_HINT, + (void *) + ((unsigned long)pbi->frame_dur)); + } +#else + vf_provider_init(&vvp9_vf_prov, PROVIDER_NAME, &vvp9_vf_provider, + pbi); + vf_reg_provider(&vvp9_vf_prov); + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_START, NULL); + if (!is_reset) + vf_notify_receiver(PROVIDER_NAME, VFRAME_EVENT_PROVIDER_FR_HINT, + (void *)((unsigned long)pbi->frame_dur)); +#endif + pbi->stat |= STAT_VF_HOOK; + + pbi->timer.data = (ulong)pbi; + pbi->timer.function = vvp9_put_timer_func; + pbi->timer.expires = jiffies + PUT_INTERVAL; + + + add_timer(&pbi->timer); + + pbi->stat |= STAT_TIMER_ARM; + + /* pbi->stat |= STAT_KTHREAD; */ + + amhevc_start(); + + pbi->stat |= STAT_VDEC_RUN; + + pbi->init_flag = 1; + pbi->process_busy = 0; + pr_info("%d, vvp9_init, RP=0x%x\n", + __LINE__, READ_VREG(HEVC_STREAM_RD_PTR)); + return 0; +} + +static int vmvp9_stop(struct VP9Decoder_s *pbi) +{ + pbi->init_flag = 0; + + if (pbi->stat & STAT_VDEC_RUN) { + amhevc_stop(); + pbi->stat &= ~STAT_VDEC_RUN; + } + if (pbi->stat & STAT_ISR_REG) { + vdec_free_irq(VDEC_IRQ_0, (void *)pbi); + pbi->stat &= ~STAT_ISR_REG; + } + if (pbi->stat & STAT_TIMER_ARM) { + del_timer_sync(&pbi->timer); + pbi->stat &= ~STAT_TIMER_ARM; + } + + if (pbi->stat & STAT_VF_HOOK) { + if (!is_reset) + vf_notify_receiver(pbi->provider_name, + VFRAME_EVENT_PROVIDER_FR_END_HINT, + NULL); + + vf_unreg_provider(&vvp9_vf_prov); + pbi->stat &= ~STAT_VF_HOOK; + } + vp9_local_uninit(pbi); + reset_process_time(pbi); + cancel_work_sync(&pbi->work); +#ifdef SUPPORT_FB_DECODING + if (pbi->used_stage_buf_num > 0) + cancel_work_sync(&pbi->s1_work); +#endif + cancel_work_sync(&pbi->set_clk_work); + uninit_mmu_buffers(pbi); + if (pbi->fw) + vfree(pbi->fw); + pbi->fw = NULL; + return 0; +} + +static int vvp9_stop(struct VP9Decoder_s *pbi) +{ + + pbi->init_flag = 0; + + if (pbi->stat & STAT_VDEC_RUN) { + amhevc_stop(); + pbi->stat &= ~STAT_VDEC_RUN; + } + + if (pbi->stat & STAT_ISR_REG) { +#ifdef MULTI_INSTANCE_SUPPORT + if (!pbi->m_ins_flag) +#endif + WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0); + vdec_free_irq(VDEC_IRQ_0, (void *)pbi); + pbi->stat &= ~STAT_ISR_REG; + } + + if (pbi->stat & STAT_TIMER_ARM) { + del_timer_sync(&pbi->timer); + pbi->stat &= ~STAT_TIMER_ARM; + } + + if (pbi->stat & STAT_VF_HOOK) { + if (!is_reset) + vf_notify_receiver(pbi->provider_name, + VFRAME_EVENT_PROVIDER_FR_END_HINT, + NULL); + + vf_unreg_provider(&vvp9_vf_prov); + pbi->stat &= ~STAT_VF_HOOK; + } + vp9_local_uninit(pbi); + +#ifdef MULTI_INSTANCE_SUPPORT + if (pbi->m_ins_flag) { + cancel_work_sync(&pbi->work); +#ifdef SUPPORT_FB_DECODING + if (pbi->used_stage_buf_num > 0) + cancel_work_sync(&pbi->s1_work); +#endif + } else + amhevc_disable(); +#else + amhevc_disable(); +#endif + cancel_work_sync(&pbi->set_clk_work); + uninit_mmu_buffers(pbi); + + vfree(pbi->fw); + pbi->fw = NULL; + return 0; +} + +static int amvdec_vp9_mmu_init(struct VP9Decoder_s *pbi) +{ + int tvp_flag = vdec_secure(hw_to_vdec(pbi)) ? + CODEC_MM_FLAGS_TVP : 0; + +#ifdef VP9_10B_MMU + int buf_size = 48; + if ((pbi->max_pic_w * pbi->max_pic_h > 1280*736) && + (pbi->max_pic_w * pbi->max_pic_h <= 1920*1088)) { + buf_size = 12; + } else if ((pbi->max_pic_w * pbi->max_pic_h > 0) && + (pbi->max_pic_w * pbi->max_pic_h <= 1280*736)) { + buf_size = 4; + } + pbi->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME, + pbi->index, FRAME_BUFFERS + STAGE_MAX_BUFFERS, + buf_size * SZ_1M, + tvp_flag + ); + if (!pbi->mmu_box) { + pr_err("vp9 alloc mmu box failed!!\n"); + return -1; + } +#endif + pbi->bmmu_box = decoder_bmmu_box_alloc_box( + DRIVER_NAME, + pbi->index, + MAX_BMMU_BUFFER_NUM, + 4 + PAGE_SHIFT, + CODEC_MM_FLAGS_CMA_CLEAR | + CODEC_MM_FLAGS_FOR_VDECODER | + tvp_flag); + if (!pbi->bmmu_box) { + pr_err("vp9 alloc bmmu box failed!!\n"); + return -1; + } + return 0; +} + +static struct VP9Decoder_s *gHevc; + +static int amvdec_vp9_probe(struct platform_device *pdev) +{ + struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; + struct BUF_s BUF[MAX_BUF_NUM]; + struct VP9Decoder_s *pbi; + int ret; +#ifndef MULTI_INSTANCE_SUPPORT + int i; +#endif + pr_debug("%s\n", __func__); + + mutex_lock(&vvp9_mutex); + pbi = vmalloc(sizeof(struct VP9Decoder_s)); + if (pbi == NULL) { + pr_info("\namvdec_vp9 device data allocation failed\n"); + mutex_unlock(&vvp9_mutex); + return -ENOMEM; + } + + gHevc = pbi; + memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM); + memset(pbi, 0, sizeof(struct VP9Decoder_s)); + memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM); + + pbi->init_flag = 0; + pbi->max_pic_w = vp9_max_pic_w; + pbi->max_pic_h = vp9_max_pic_h; + +#ifdef MULTI_INSTANCE_SUPPORT + pbi->eos = 0; + pbi->start_process_time = 0; + pbi->timeout_num = 0; +#endif + pbi->fatal_error = 0; + pbi->show_frame_num = 0; + if (pdata == NULL) { + pr_info("\namvdec_vp9 memory resource undefined.\n"); + vfree(pbi); + mutex_unlock(&vvp9_mutex); + return -EFAULT; + } + pbi->m_ins_flag = 0; +#ifdef MULTI_INSTANCE_SUPPORT + pbi->platform_dev = pdev; + platform_set_drvdata(pdev, pdata); +#endif + if (amvdec_vp9_mmu_init(pbi) < 0) { + vfree(pbi); + mutex_unlock(&vvp9_mutex); + pr_err("vp9 alloc bmmu box failed!!\n"); + return -1; + } + + ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID, + work_buf_size, DRIVER_NAME, &pdata->mem_start); + if (ret < 0) { + uninit_mmu_buffers(pbi); + vfree(pbi); + mutex_unlock(&vvp9_mutex); + return ret; + } + pbi->buf_size = work_buf_size; + +#ifdef MULTI_INSTANCE_SUPPORT + pbi->buf_start = pdata->mem_start; +#else +#ifndef VP9_10B_MMU + pbi->mc_buf_spec.buf_end = pdata->mem_start + pbi->buf_size; +#endif + for (i = 0; i < WORK_BUF_SPEC_NUM; i++) + amvvp9_workbuff_spec[i].start_adr = pdata->mem_start; +#endif + + + if (debug) { + pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n", + pdata->mem_start, pbi->buf_size); + } + + if (pdata->sys_info) + pbi->vvp9_amstream_dec_info = *pdata->sys_info; + else { + pbi->vvp9_amstream_dec_info.width = 0; + pbi->vvp9_amstream_dec_info.height = 0; + pbi->vvp9_amstream_dec_info.rate = 30; + } +#ifdef MULTI_INSTANCE_SUPPORT + pbi->cma_dev = pdata->cma_dev; +#else + cma_dev = pdata->cma_dev; +#endif + +#ifdef MULTI_INSTANCE_SUPPORT + pdata->private = pbi; + pdata->dec_status = vvp9_dec_status; + pdata->set_isreset = vvp9_set_isreset; + is_reset = 0; + if (vvp9_init(pdata) < 0) { +#else + if (vvp9_init(pbi) < 0) { +#endif + pr_info("\namvdec_vp9 init failed.\n"); + vp9_local_uninit(pbi); + uninit_mmu_buffers(pbi); + vfree(pbi); + mutex_unlock(&vvp9_mutex); + return -ENODEV; + } + /*set the max clk for smooth playing...*/ + hevc_source_changed(VFORMAT_VP9, + 4096, 2048, 60); + mutex_unlock(&vvp9_mutex); + + return 0; +} + +static int amvdec_vp9_remove(struct platform_device *pdev) +{ + struct VP9Decoder_s *pbi = gHevc; + + if (debug) + pr_info("amvdec_vp9_remove\n"); + + mutex_lock(&vvp9_mutex); + + vvp9_stop(pbi); + + + hevc_source_changed(VFORMAT_VP9, 0, 0, 0); + + +#ifdef DEBUG_PTS + pr_info("pts missed %ld, pts hit %ld, duration %d\n", + pbi->pts_missed, pbi->pts_hit, pbi->frame_dur); +#endif + vfree(pbi); + mutex_unlock(&vvp9_mutex); + + return 0; +} + +/****************************************/ + +static struct platform_driver amvdec_vp9_driver = { + .probe = amvdec_vp9_probe, + .remove = amvdec_vp9_remove, +#ifdef CONFIG_PM + .suspend = amhevc_suspend, + .resume = amhevc_resume, +#endif + .driver = { + .name = DRIVER_NAME, + } +}; + +static struct codec_profile_t amvdec_vp9_profile = { + .name = "vp9", + .profile = "" +}; + +static unsigned char get_data_check_sum + (struct VP9Decoder_s *pbi, int size) +{ + int jj; + int sum = 0; + u8 *data = ((u8 *)pbi->chunk->block->start_virt) + + pbi->chunk->offset; + for (jj = 0; jj < size; jj++) + sum += data[jj]; + return sum; +} + +static void dump_data(struct VP9Decoder_s *pbi, int size) +{ + int jj; + u8 *data = ((u8 *)pbi->chunk->block->start_virt) + + pbi->chunk->offset; + int padding_size = pbi->chunk->offset & + (VDEC_FIFO_ALIGN - 1); + vp9_print(pbi, 0, "padding: "); + for (jj = padding_size; jj > 0; jj--) + vp9_print_cont(pbi, + 0, + "%02x ", *(data - jj)); + vp9_print_cont(pbi, 0, "data adr %p\n", + data); + + for (jj = 0; jj < size; jj++) { + if ((jj & 0xf) == 0) + vp9_print(pbi, + 0, + "%06x:", jj); + vp9_print_cont(pbi, + 0, + "%02x ", data[jj]); + if (((jj + 1) & 0xf) == 0) + vp9_print(pbi, + 0, + "\n"); + } + vp9_print(pbi, + 0, + "\n"); +} + +static void vp9_work(struct work_struct *work) +{ + struct VP9Decoder_s *pbi = container_of(work, + struct VP9Decoder_s, work); + struct vdec_s *vdec = hw_to_vdec(pbi); + /* finished decoding one frame or error, + * notify vdec core to switch context + */ + vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, + "%s dec_result %d %x %x %x\n", + __func__, + pbi->dec_result, + READ_VREG(HEVC_STREAM_LEVEL), + READ_VREG(HEVC_STREAM_WR_PTR), + READ_VREG(HEVC_STREAM_RD_PTR)); + + if (((pbi->dec_result == DEC_RESULT_GET_DATA) || + (pbi->dec_result == DEC_RESULT_GET_DATA_RETRY)) + && (hw_to_vdec(pbi)->next_status != + VDEC_STATUS_DISCONNECTED)) { + if (!vdec_has_more_input(vdec)) { + pbi->dec_result = DEC_RESULT_EOS; + vdec_schedule_work(&pbi->work); + return; + } + + if (pbi->dec_result == DEC_RESULT_GET_DATA) { + vp9_print(pbi, PRINT_FLAG_VDEC_STATUS, + "%s DEC_RESULT_GET_DATA %x %x %x\n", + __func__, + READ_VREG(HEVC_STREAM_LEVEL), + READ_VREG(HEVC_STREAM_WR_PTR), + READ_VREG(HEVC_STREAM_RD_PTR)); + vdec_vframe_dirty(vdec, pbi->chunk); + vdec_clean_input(vdec); + } + + if (get_free_buf_count(pbi) >= + run_ready_min_buf_num) { + int r; + int decode_size; + r = vdec_prepare_input(vdec, &pbi->chunk); + if (r < 0) { + pbi->dec_result = DEC_RESULT_GET_DATA_RETRY; + + vp9_print(pbi, + PRINT_FLAG_VDEC_DETAIL, + "amvdec_vh265: Insufficient data\n"); + + vdec_schedule_work(&pbi->work); + return; + } + pbi->dec_result = DEC_RESULT_NONE; + vp9_print(pbi, PRINT_FLAG_VDEC_STATUS, + "%s: chunk size 0x%x sum 0x%x\n", + __func__, r, + (debug & PRINT_FLAG_VDEC_STATUS) ? + get_data_check_sum(pbi, r) : 0 + ); + + if (debug & PRINT_FLAG_VDEC_DATA) + dump_data(pbi, pbi->chunk->size); + + decode_size = pbi->chunk->size + + (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1)); + + WRITE_VREG(HEVC_DECODE_SIZE, + READ_VREG(HEVC_DECODE_SIZE) + decode_size); + + vdec_enable_input(vdec); + + WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE); + + start_process_time(pbi); + + } else{ + pbi->dec_result = DEC_RESULT_GET_DATA_RETRY; + + vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, + "amvdec_vh265: Insufficient data\n"); + + vdec_schedule_work(&pbi->work); + } + return; + } else if (pbi->dec_result == DEC_RESULT_DONE) { +#ifdef SUPPORT_FB_DECODING + if (pbi->used_stage_buf_num > 0) { +#ifndef FB_DECODING_TEST_SCHEDULE + if (!is_s2_decoding_finished(pbi)) { + vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, + "s2 decoding not done, check again later\n"); + vdec_schedule_work(&pbi->work); + } +#endif + inc_s2_pos(pbi); + if (mcrcc_cache_alg_flag) + dump_hit_rate(pbi); + } +#endif + /* if (!pbi->ctx_valid) + pbi->ctx_valid = 1; */ + pbi->slice_idx++; + pbi->frame_count++; + pbi->process_state = PROC_STATE_INIT; + decode_frame_count[pbi->index] = pbi->frame_count; + +#ifdef VP9_10B_MMU + pbi->used_4k_num = + (READ_VREG(HEVC_SAO_MMU_STATUS) >> 16); +#endif + vp9_print(pbi, PRINT_FLAG_VDEC_STATUS, + "%s (===> %d) dec_result %d %x %x %x shiftbytes 0x%x decbytes 0x%x\n", + __func__, + pbi->frame_count, + pbi->dec_result, + READ_VREG(HEVC_STREAM_LEVEL), + READ_VREG(HEVC_STREAM_WR_PTR), + READ_VREG(HEVC_STREAM_RD_PTR), + READ_VREG(HEVC_SHIFT_BYTE_COUNT), + READ_VREG(HEVC_SHIFT_BYTE_COUNT) - + pbi->start_shift_bytes + ); + vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk); + } else if (pbi->dec_result == DEC_RESULT_AGAIN) { + /* + stream base: stream buf empty or timeout + frame base: vdec_prepare_input fail + */ +#ifdef VP9_10B_MMU + if (pbi->process_state == PROC_STATE_SENDAGAIN) + vp9_recycle_mmu_buf(pbi); +#endif + if (!vdec_has_more_input(vdec)) { + pbi->dec_result = DEC_RESULT_EOS; + vdec_schedule_work(&pbi->work); + return; + } + } else if (pbi->dec_result == DEC_RESULT_EOS) { + vp9_print(pbi, PRINT_FLAG_VDEC_STATUS, + "%s: end of stream\n", + __func__); + pbi->eos = 1; + vp9_bufmgr_postproc(pbi); + vdec_vframe_dirty(hw_to_vdec(pbi), pbi->chunk); + } else if (pbi->dec_result == DEC_RESULT_FORCE_EXIT) { + vp9_print(pbi, PRINT_FLAG_VDEC_STATUS, + "%s: force exit\n", + __func__); + if (pbi->stat & STAT_VDEC_RUN) { + amhevc_stop(); + pbi->stat &= ~STAT_VDEC_RUN; + } + + if (pbi->stat & STAT_ISR_REG) { +#ifdef MULTI_INSTANCE_SUPPORT + if (!pbi->m_ins_flag) +#endif + WRITE_VREG(HEVC_ASSIST_MBOX0_MASK, 0); + vdec_free_irq(VDEC_IRQ_0, (void *)pbi); + pbi->stat &= ~STAT_ISR_REG; + } + } + if (pbi->stat & STAT_VDEC_RUN) { + amhevc_stop(); + pbi->stat &= ~STAT_VDEC_RUN; + } + + if (pbi->stat & STAT_TIMER_ARM) { + del_timer_sync(&pbi->timer); + pbi->stat &= ~STAT_TIMER_ARM; + } + /* mark itself has all HW resource released and input released */ +#ifdef SUPPORT_FB_DECODING + if (pbi->used_stage_buf_num > 0) + vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_HEVC_BACK); + else + vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1 + | CORE_MASK_HEVC + | CORE_MASK_HEVC_FRONT + | CORE_MASK_HEVC_BACK + ); +#else + vdec_core_finish_run(hw_to_vdec(pbi), CORE_MASK_VDEC_1 + | CORE_MASK_HEVC); +#endif + trigger_schedule(pbi); +} + +static int vp9_hw_ctx_restore(struct VP9Decoder_s *pbi) +{ + /* new to do ... */ +#if (!defined SUPPORT_FB_DECODING) + vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK); +#elif (defined FB_DECODING_TEST_SCHEDULE) + vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK); +#else + if (pbi->used_stage_buf_num > 0) + vvp9_prot_init(pbi, HW_MASK_FRONT); + else + vvp9_prot_init(pbi, HW_MASK_FRONT | HW_MASK_BACK); +#endif + return 0; +} + +static unsigned long run_ready(struct vdec_s *vdec, unsigned long mask) +{ + struct VP9Decoder_s *pbi = + (struct VP9Decoder_s *)vdec->private; + unsigned long ret = 0; + + if (pbi->eos) + return ret; +#ifdef SUPPORT_FB_DECODING + if (pbi->used_stage_buf_num > 0) { + if (mask & CORE_MASK_HEVC_FRONT) { + if (get_free_stage_buf_num(pbi) > 0 + && mv_buf_available(pbi)) + ret |= CORE_MASK_HEVC_FRONT; + } + if (mask & CORE_MASK_HEVC_BACK) { + if (s2_buf_available(pbi) && + (get_free_buf_count(pbi) >= + run_ready_min_buf_num)) { + ret |= CORE_MASK_HEVC_BACK; + pbi->back_not_run_ready = 0; + } else + pbi->back_not_run_ready = 1; +#if 0 + if (get_free_buf_count(pbi) < + run_ready_min_buf_num) + dump_pic_list(pbi); +#endif + } + } else if (get_free_buf_count(pbi) >= + run_ready_min_buf_num) + ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC + | CORE_MASK_HEVC_FRONT + | CORE_MASK_HEVC_BACK; + + if (ret & CORE_MASK_HEVC_FRONT) + not_run_ready[pbi->index] = 0; + else + not_run_ready[pbi->index]++; + + if (ret & CORE_MASK_HEVC_BACK) + not_run2_ready[pbi->index] = 0; + else + not_run2_ready[pbi->index]++; + + vp9_print(pbi, + PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx (%d %d %d %d)\r\n", + __func__, mask, ret, + get_free_stage_buf_num(pbi), + mv_buf_available(pbi), + s2_buf_available(pbi), + get_free_buf_count(pbi) + ); + + return ret; + +#else + if (get_free_buf_count(pbi) >= + run_ready_min_buf_num) + ret = CORE_MASK_VDEC_1 | CORE_MASK_HEVC; + if (ret) + not_run_ready[pbi->index] = 0; + else + not_run_ready[pbi->index]++; + + vp9_print(pbi, + PRINT_FLAG_VDEC_DETAIL, "%s mask %lx=>%lx\r\n", + __func__, mask, ret); + return ret; +#endif +} + +static void run_front(struct vdec_s *vdec) +{ + struct VP9Decoder_s *pbi = + (struct VP9Decoder_s *)vdec->private; + int ret, size; + + run_count[pbi->index]++; + /* pbi->chunk = vdec_prepare_input(vdec); */ +#if (!defined SUPPORT_FB_DECODING) + hevc_reset_core(vdec); +#elif (defined FB_DECODING_TEST_SCHEDULE) + hevc_reset_core(vdec); +#else + if (pbi->used_stage_buf_num > 0) + fb_reset_core(vdec, HW_MASK_FRONT); + else + hevc_reset_core(vdec); +#endif + + size = vdec_prepare_input(vdec, &pbi->chunk); + if (size < 0) { + input_empty[pbi->index]++; + + pbi->dec_result = DEC_RESULT_AGAIN; + + vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, + "ammvdec_vh265: Insufficient data\n"); + + vdec_schedule_work(&pbi->work); + return; + } + input_empty[pbi->index] = 0; + pbi->dec_result = DEC_RESULT_NONE; + pbi->start_shift_bytes = READ_VREG(HEVC_SHIFT_BYTE_COUNT); + + if (debug & PRINT_FLAG_VDEC_STATUS) { + int ii; + vp9_print(pbi, 0, + "%s (%d): size 0x%x (0x%x 0x%x) sum 0x%x (%x %x %x %x %x) bytes 0x%x", + __func__, + pbi->frame_count, size, + pbi->chunk ? pbi->chunk->size : 0, + pbi->chunk ? pbi->chunk->offset : 0, + (vdec_frame_based(vdec) && + (debug & PRINT_FLAG_VDEC_STATUS)) ? + get_data_check_sum(pbi, size) : 0, + READ_VREG(HEVC_STREAM_START_ADDR), + READ_VREG(HEVC_STREAM_END_ADDR), + READ_VREG(HEVC_STREAM_LEVEL), + READ_VREG(HEVC_STREAM_WR_PTR), + READ_VREG(HEVC_STREAM_RD_PTR), + pbi->start_shift_bytes); + if (vdec_frame_based(vdec)) { + u8 *data = ((u8 *)pbi->chunk->block->start_virt) + + pbi->chunk->offset; + vp9_print_cont(pbi, 0, "data adr %p:", + data); + for (ii = 0; ii < 8; ii++) + vp9_print_cont(pbi, 0, "%02x ", + data[ii]); + } + vp9_print_cont(pbi, 0, "\r\n"); + } + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) + ret = amhevc_loadmc_ex(VFORMAT_VP9, "vp9_mc", pbi->fw->data); + else + ret = amhevc_loadmc_ex(VFORMAT_VP9, NULL, pbi->fw->data); + + if (ret < 0) { + amhevc_disable(); + vp9_print(pbi, 0, + "%s: Error amvdec_loadmc fail\n", __func__); + return; + } + + if (vp9_hw_ctx_restore(pbi) < 0) { + vdec_schedule_work(&pbi->work); + return; + } + + vdec_enable_input(vdec); + + WRITE_VREG(HEVC_DEC_STATUS_REG, HEVC_ACTION_DONE); + + if (vdec_frame_based(vdec)) { + if (debug & PRINT_FLAG_VDEC_DATA) + dump_data(pbi, pbi->chunk->size); + + WRITE_VREG(HEVC_SHIFT_BYTE_COUNT, 0); + size = pbi->chunk->size + + (pbi->chunk->offset & (VDEC_FIFO_ALIGN - 1)); + } + WRITE_VREG(HEVC_DECODE_SIZE, size); + WRITE_VREG(HEVC_DECODE_COUNT, pbi->slice_idx); + pbi->init_flag = 1; + + vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, + "%s: start hevc (%x %x %x)\n", + __func__, + READ_VREG(HEVC_DEC_STATUS_REG), + READ_VREG(HEVC_MPC_E), + READ_VREG(HEVC_MPSR)); + + start_process_time(pbi); + mod_timer(&pbi->timer, jiffies); + pbi->stat |= STAT_TIMER_ARM; + pbi->stat |= STAT_ISR_REG; + amhevc_start(); + pbi->stat |= STAT_VDEC_RUN; +} + +#ifdef SUPPORT_FB_DECODING +static void mpred_process(struct VP9Decoder_s *pbi) +{ + union param_u *params = &pbi->s1_param; + unsigned char use_prev_frame_mvs = + !params->p.error_resilient_mode && + params->p.width == pbi->s1_width && + params->p.height == pbi->s1_height && + !pbi->s1_intra_only && + pbi->s1_last_show_frame && + (pbi->s1_frame_type != KEY_FRAME); + pbi->s1_width = params->p.width; + pbi->s1_height = params->p.height; + pbi->s1_frame_type = params->p.frame_type; + pbi->s1_intra_only = + (params->p.show_frame || + params->p.show_existing_frame) + ? 0 : params->p.intra_only; + if ((pbi->s1_frame_type != KEY_FRAME) + && (!pbi->s1_intra_only)) { + unsigned int data32; + int mpred_mv_rd_end_addr; + + mpred_mv_rd_end_addr = + pbi->s1_mpred_mv_wr_start_addr_pre + + (pbi->lcu_total * MV_MEM_UNIT); + + WRITE_VREG(HEVC_MPRED_CTRL3, 0x24122412); + WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, + pbi->work_space_buf-> + mpred_above.buf_start); + + data32 = READ_VREG(HEVC_MPRED_CTRL4); + + data32 &= (~(1 << 6)); + data32 |= (use_prev_frame_mvs << 6); + WRITE_VREG(HEVC_MPRED_CTRL4, data32); + + WRITE_VREG(HEVC_MPRED_MV_WR_START_ADDR, + pbi->s1_mpred_mv_wr_start_addr); + WRITE_VREG(HEVC_MPRED_MV_WPTR, + pbi->s1_mpred_mv_wr_start_addr); + + WRITE_VREG(HEVC_MPRED_MV_RD_START_ADDR, + pbi->s1_mpred_mv_wr_start_addr_pre); + WRITE_VREG(HEVC_MPRED_MV_RPTR, + pbi->s1_mpred_mv_wr_start_addr_pre); + + WRITE_VREG(HEVC_MPRED_MV_RD_END_ADDR, + mpred_mv_rd_end_addr); + + } else + clear_mpred_hw(pbi); + + if (!params->p.show_existing_frame) { + pbi->s1_mpred_mv_wr_start_addr_pre = + pbi->s1_mpred_mv_wr_start_addr; + pbi->s1_last_show_frame = + params->p.show_frame; + if (pbi->s1_mv_buf_index_pre_pre != MV_BUFFER_NUM) + put_mv_buf(pbi, &pbi->s1_mv_buf_index_pre_pre); + pbi->s1_mv_buf_index_pre_pre = + pbi->s1_mv_buf_index_pre; + pbi->s1_mv_buf_index_pre = pbi->s1_mv_buf_index; + } else + put_mv_buf(pbi, &pbi->s1_mv_buf_index); +} + +static void vp9_s1_work(struct work_struct *s1_work) +{ + struct VP9Decoder_s *pbi = container_of(s1_work, + struct VP9Decoder_s, s1_work); + vp9_print(pbi, PRINT_FLAG_VDEC_DETAIL, + "%s dec_s1_result %d\n", + __func__, + pbi->dec_s1_result); + +#ifdef FB_DECODING_TEST_SCHEDULE + if (pbi->dec_s1_result == + DEC_S1_RESULT_TEST_TRIGGER_DONE) { + pbi->s1_test_cmd = TEST_SET_PIC_DONE; + WRITE_VREG(HEVC_ASSIST_MBOX0_IRQ_REG, 0x1); + } +#endif + if (pbi->dec_s1_result == DEC_S1_RESULT_DONE || + pbi->dec_s1_result == DEC_S1_RESULT_FORCE_EXIT) { + + vdec_core_finish_run(hw_to_vdec(pbi), + CORE_MASK_HEVC_FRONT); + + trigger_schedule(pbi); + /*pbi->dec_s1_result = DEC_S1_RESULT_NONE;*/ + } + +} + +static void run_back(struct vdec_s *vdec) +{ + struct VP9Decoder_s *pbi = + (struct VP9Decoder_s *)vdec->private; + int i; + run2_count[pbi->index]++; + if (debug & PRINT_FLAG_VDEC_STATUS) { + vp9_print(pbi, 0, + "%s", __func__); + } + pbi->run2_busy = 1; +#ifndef FB_DECODING_TEST_SCHEDULE + fb_reset_core(vdec, HW_MASK_BACK); + + vvp9_prot_init(pbi, HW_MASK_BACK); +#endif + vp9_recycle_mmu_buf_tail(pbi); + + if (pbi->frame_count > 0) + vp9_bufmgr_postproc(pbi); + + if (get_s2_buf(pbi) >= 0) { + for (i = 0; i < (RPM_END - RPM_BEGIN); i += 4) { + int ii; + for (ii = 0; ii < 4; ii++) + vp9_param.l.data[i + ii] = + pbi->s2_buf->rpm[i + 3 - ii]; + } +#ifndef FB_DECODING_TEST_SCHEDULE + WRITE_VREG(HEVC_ASSIST_FBD_MMU_MAP_ADDR, + pbi->stage_mmu_map_phy_addr + + pbi->s2_buf->index * STAGE_MMU_MAP_SIZE); +#endif + continue_decoding(pbi); + } + pbi->run2_busy = 0; +} +#endif + +static void run(struct vdec_s *vdec, unsigned long mask, + void (*callback)(struct vdec_s *, void *), void *arg) +{ + struct VP9Decoder_s *pbi = + (struct VP9Decoder_s *)vdec->private; + + vp9_print(pbi, + PRINT_FLAG_VDEC_DETAIL, "%s mask %lx\r\n", + __func__, mask); + + run_count[pbi->index]++; + pbi->vdec_cb_arg = arg; + pbi->vdec_cb = callback; +#ifdef SUPPORT_FB_DECODING + if ((mask & CORE_MASK_HEVC) || + (mask & CORE_MASK_HEVC_FRONT)) + run_front(vdec); + + if ((pbi->used_stage_buf_num > 0) + && (mask & CORE_MASK_HEVC_BACK)) + run_back(vdec); +#else + run_front(vdec); +#endif +} + +static void reset(struct vdec_s *vdec) +{ + + struct VP9Decoder_s *pbi = + (struct VP9Decoder_s *)vdec->private; + + vp9_print(pbi, + PRINT_FLAG_VDEC_DETAIL, "%s\r\n", __func__); + +} + +static irqreturn_t vp9_irq_cb(struct vdec_s *vdec, int irq) +{ + struct VP9Decoder_s *pbi = + (struct VP9Decoder_s *)vdec->private; + return vvp9_isr(0, pbi); +} + +static irqreturn_t vp9_threaded_irq_cb(struct vdec_s *vdec, int irq) +{ + struct VP9Decoder_s *pbi = + (struct VP9Decoder_s *)vdec->private; + return vvp9_isr_thread_fn(0, pbi); +} + +static void vp9_dump_state(struct vdec_s *vdec) +{ + struct VP9Decoder_s *pbi = + (struct VP9Decoder_s *)vdec->private; + struct VP9_Common_s *const cm = &pbi->common; + int i; + vp9_print(pbi, 0, "====== %s\n", __func__); + + vp9_print(pbi, 0, + "width/height (%d/%d), used_buf_num %d\n", + cm->width, + cm->height, + pbi->used_buf_num + ); + + vp9_print(pbi, 0, + "is_framebase(%d), eos %d, dec_result 0x%x dec_frm %d disp_frm %d run %d not_run_ready %d input_empty %d\n", + input_frame_based(vdec), + pbi->eos, + pbi->dec_result, + decode_frame_count[pbi->index], + display_frame_count[pbi->index], + run_count[pbi->index], + not_run_ready[pbi->index], + input_empty[pbi->index] + ); + + if (vf_get_receiver(vdec->vf_provider_name)) { + enum receviver_start_e state = + vf_notify_receiver(vdec->vf_provider_name, + VFRAME_EVENT_PROVIDER_QUREY_STATE, + NULL); + vp9_print(pbi, 0, + "\nreceiver(%s) state %d\n", + vdec->vf_provider_name, + state); + } + + vp9_print(pbi, 0, + "%s, newq(%d/%d), dispq(%d/%d), vf prepare/get/put (%d/%d/%d), free_buf_count %d (min %d for run_ready)\n", + __func__, + kfifo_len(&pbi->newframe_q), + VF_POOL_SIZE, + kfifo_len(&pbi->display_q), + VF_POOL_SIZE, + pbi->vf_pre_count, + pbi->vf_get_count, + pbi->vf_put_count, + get_free_buf_count(pbi), + run_ready_min_buf_num + ); + + dump_pic_list(pbi); + + for (i = 0; i < MAX_BUF_NUM; i++) { + vp9_print(pbi, 0, + "mv_Buf(%d) start_adr 0x%x size 0x%x used %d\n", + i, + pbi->m_mv_BUF[i].start_adr, + pbi->m_mv_BUF[i].size, + pbi->m_mv_BUF[i].used_flag); + } + + vp9_print(pbi, 0, + "HEVC_DEC_STATUS_REG=0x%x\n", + READ_VREG(HEVC_DEC_STATUS_REG)); + vp9_print(pbi, 0, + "HEVC_MPC_E=0x%x\n", + READ_VREG(HEVC_MPC_E)); + vp9_print(pbi, 0, + "DECODE_MODE=0x%x\n", + READ_VREG(DECODE_MODE)); + vp9_print(pbi, 0, + "NAL_SEARCH_CTL=0x%x\n", + READ_VREG(NAL_SEARCH_CTL)); + vp9_print(pbi, 0, + "HEVC_PARSER_LCU_START=0x%x\n", + READ_VREG(HEVC_PARSER_LCU_START)); + vp9_print(pbi, 0, + "HEVC_DECODE_SIZE=0x%x\n", + READ_VREG(HEVC_DECODE_SIZE)); + vp9_print(pbi, 0, + "HEVC_SHIFT_BYTE_COUNT=0x%x\n", + READ_VREG(HEVC_SHIFT_BYTE_COUNT)); + vp9_print(pbi, 0, + "HEVC_STREAM_START_ADDR=0x%x\n", + READ_VREG(HEVC_STREAM_START_ADDR)); + vp9_print(pbi, 0, + "HEVC_STREAM_END_ADDR=0x%x\n", + READ_VREG(HEVC_STREAM_END_ADDR)); + vp9_print(pbi, 0, + "HEVC_STREAM_LEVEL=0x%x\n", + READ_VREG(HEVC_STREAM_LEVEL)); + vp9_print(pbi, 0, + "HEVC_STREAM_WR_PTR=0x%x\n", + READ_VREG(HEVC_STREAM_WR_PTR)); + vp9_print(pbi, 0, + "HEVC_STREAM_RD_PTR=0x%x\n", + READ_VREG(HEVC_STREAM_RD_PTR)); + vp9_print(pbi, 0, + "PARSER_VIDEO_RP=0x%x\n", + READ_PARSER_REG(PARSER_VIDEO_RP)); + vp9_print(pbi, 0, + "PARSER_VIDEO_WP=0x%x\n", + READ_PARSER_REG(PARSER_VIDEO_WP)); + + if (input_frame_based(vdec) && + (debug & PRINT_FLAG_VDEC_DATA) + ) { + int jj; + if (pbi->chunk && pbi->chunk->block && + pbi->chunk->size > 0) { + u8 *data = + ((u8 *)pbi->chunk->block->start_virt) + + pbi->chunk->offset; + vp9_print(pbi, 0, + "frame data size 0x%x\n", + pbi->chunk->size); + for (jj = 0; jj < pbi->chunk->size; jj++) { + if ((jj & 0xf) == 0) + vp9_print(pbi, 0, + "%06x:", jj); + vp9_print_cont(pbi, 0, + "%02x ", data[jj]); + if (((jj + 1) & 0xf) == 0) + vp9_print_cont(pbi, 0, + "\n"); + } + } + } + +} + +static int ammvdec_vp9_probe(struct platform_device *pdev) +{ + struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data; + int ret; + int config_val; + struct vframe_content_light_level_s content_light_level; + struct vframe_master_display_colour_s vf_dp; + + struct BUF_s BUF[MAX_BUF_NUM]; + struct VP9Decoder_s *pbi = NULL; + pr_debug("%s\n", __func__); + + if (pdata == NULL) { + pr_info("\nammvdec_vp9 memory resource undefined.\n"); + return -EFAULT; + } + /*pbi = (struct VP9Decoder_s *)devm_kzalloc(&pdev->dev, + sizeof(struct VP9Decoder_s), GFP_KERNEL);*/ + memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s)); + pbi = vmalloc(sizeof(struct VP9Decoder_s)); + if (pbi == NULL) { + pr_info("\nammvdec_vp9 device data allocation failed\n"); + return -ENOMEM; + } + memset(pbi, 0, sizeof(struct VP9Decoder_s)); + pdata->private = pbi; + pdata->dec_status = vvp9_dec_status; + /* pdata->set_trickmode = set_trickmode; */ + pdata->run_ready = run_ready; + pdata->run = run; + pdata->reset = reset; + pdata->irq_handler = vp9_irq_cb; + pdata->threaded_irq_handler = vp9_threaded_irq_cb; + pdata->dump_state = vp9_dump_state; + + memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM); + memset(pbi, 0, sizeof(struct VP9Decoder_s)); + memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM); + + pbi->index = pdev->id; + + if (pdata->use_vfm_path) + snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE, + VFM_DEC_PROVIDER_NAME); + else + snprintf(pdata->vf_provider_name, VDEC_PROVIDER_NAME_SIZE, + MULTI_INSTANCE_PROVIDER_NAME ".%02x", pdev->id & 0xff); + + vf_provider_init(&pdata->vframe_provider, pdata->vf_provider_name, + &vvp9_vf_provider, pbi); + + pbi->provider_name = pdata->vf_provider_name; + platform_set_drvdata(pdev, pdata); + + pbi->platform_dev = pdev; + pbi->video_signal_type = 0; + if (get_cpu_type() < MESON_CPU_MAJOR_ID_TXLX) + pbi->stat |= VP9_TRIGGER_FRAME_ENABLE; +#if 1 + if ((debug & IGNORE_PARAM_FROM_CONFIG) == 0 && + pdata->config && pdata->config_len) { +#ifdef MULTI_INSTANCE_SUPPORT + /*use ptr config for doubel_write_mode, etc*/ + vp9_print(pbi, 0, "pdata->config=%s\n", pdata->config); + if (get_config_int(pdata->config, "vp9_double_write_mode", + &config_val) == 0) + pbi->double_write_mode = config_val; + else + pbi->double_write_mode = double_write_mode; + + /*use ptr config for max_pic_w, etc*/ + if (get_config_int(pdata->config, "vp9_max_pic_w", + &config_val) == 0) { + pbi->max_pic_w = config_val; + } + if (get_config_int(pdata->config, "vp9_max_pic_h", + &config_val) == 0) { + pbi->max_pic_h = config_val; + } +#endif + if (get_config_int(pdata->config, "HDRStaticInfo", + &vf_dp.present_flag) == 0 + && vf_dp.present_flag == 1) { + get_config_int(pdata->config, "mG.x", + &vf_dp.primaries[0][0]); + get_config_int(pdata->config, "mG.y", + &vf_dp.primaries[0][1]); + get_config_int(pdata->config, "mB.x", + &vf_dp.primaries[1][0]); + get_config_int(pdata->config, "mB.y", + &vf_dp.primaries[1][1]); + get_config_int(pdata->config, "mR.x", + &vf_dp.primaries[2][0]); + get_config_int(pdata->config, "mR.y", + &vf_dp.primaries[2][1]); + get_config_int(pdata->config, "mW.x", + &vf_dp.white_point[0]); + get_config_int(pdata->config, "mW.y", + &vf_dp.white_point[1]); + get_config_int(pdata->config, "mMaxDL", + &vf_dp.luminance[0]); + get_config_int(pdata->config, "mMinDL", + &vf_dp.luminance[1]); + vf_dp.content_light_level.present_flag = 1; + get_config_int(pdata->config, "mMaxCLL", + &content_light_level.max_content); + get_config_int(pdata->config, "mMaxFALL", + &content_light_level.max_pic_average); + vf_dp.content_light_level = content_light_level; + pbi->video_signal_type = (1 << 29) + | (5 << 26) /* unspecified */ + | (0 << 25) /* limit */ + | (1 << 24) /* color available */ + | (9 << 16) /* 2020 */ + | (16 << 8) /* 2084 */ + | (9 << 0); /* 2020 */ + } + pbi->vf_dp = vf_dp; + } else +#endif + { + /*pbi->vvp9_amstream_dec_info.width = 0; + pbi->vvp9_amstream_dec_info.height = 0; + pbi->vvp9_amstream_dec_info.rate = 30;*/ + pbi->double_write_mode = double_write_mode; + } + video_signal_type = pbi->video_signal_type; +#if 0 + pbi->buf_start = pdata->mem_start; + pbi->buf_size = pdata->mem_end - pdata->mem_start + 1; +#else + if (amvdec_vp9_mmu_init(pbi) < 0) { + pr_err("vp9 alloc bmmu box failed!!\n"); + /* devm_kfree(&pdev->dev, (void *)pbi); */ + vfree((void *)pbi); + return -1; + } + + pbi->cma_alloc_count = PAGE_ALIGN(work_buf_size) / PAGE_SIZE; + ret = decoder_bmmu_box_alloc_buf_phy(pbi->bmmu_box, WORK_SPACE_BUF_ID, + pbi->cma_alloc_count * PAGE_SIZE, DRIVER_NAME, + &pbi->cma_alloc_addr); + if (ret < 0) { + uninit_mmu_buffers(pbi); + /* devm_kfree(&pdev->dev, (void *)pbi); */ + vfree((void *)pbi); + return ret; + } + pbi->buf_start = pbi->cma_alloc_addr; + pbi->buf_size = work_buf_size; +#endif + pbi->m_ins_flag = 1; + + pbi->init_flag = 0; + pbi->fatal_error = 0; + pbi->show_frame_num = 0; + if (pdata == NULL) { + pr_info("\namvdec_vp9 memory resource undefined.\n"); + uninit_mmu_buffers(pbi); + /* devm_kfree(&pdev->dev, (void *)pbi); */ + vfree((void *)pbi); + return -EFAULT; + } + + if (debug) { + pr_info("===VP9 decoder mem resource 0x%lx size 0x%x\n", + pbi->buf_start, + pbi->buf_size); + } + + if (pdata->sys_info) + pbi->vvp9_amstream_dec_info = *pdata->sys_info; + else { + pbi->vvp9_amstream_dec_info.width = 0; + pbi->vvp9_amstream_dec_info.height = 0; + pbi->vvp9_amstream_dec_info.rate = 30; + } + + pbi->cma_dev = pdata->cma_dev; + if (vvp9_init(pdata) < 0) { + pr_info("\namvdec_vp9 init failed.\n"); + vp9_local_uninit(pbi); + uninit_mmu_buffers(pbi); + /* devm_kfree(&pdev->dev, (void *)pbi); */ + vfree((void *)pbi); + return -ENODEV; + } + vdec_set_prepare_level(pdata, start_decode_buf_level); + hevc_source_changed(VFORMAT_VP9, + 4096, 2048, 60); +#ifdef SUPPORT_FB_DECODING + if (pbi->used_stage_buf_num > 0) + vdec_core_request(pdata, + CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK); + else + vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC + | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK + | CORE_MASK_COMBINE); +#else + vdec_core_request(pdata, CORE_MASK_VDEC_1 | CORE_MASK_HEVC + | CORE_MASK_COMBINE); +#endif + return 0; +} + +static int ammvdec_vp9_remove(struct platform_device *pdev) +{ + struct VP9Decoder_s *pbi = (struct VP9Decoder_s *) + (((struct vdec_s *)(platform_get_drvdata(pdev)))->private); + if (debug) + pr_info("amvdec_vp9_remove\n"); + + vmvp9_stop(pbi); + +#ifdef SUPPORT_FB_DECODING + vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC + | CORE_MASK_HEVC_FRONT | CORE_MASK_HEVC_BACK + ); +#else + vdec_core_release(hw_to_vdec(pbi), CORE_MASK_VDEC_1 | CORE_MASK_HEVC); +#endif + vdec_set_status(hw_to_vdec(pbi), VDEC_STATUS_DISCONNECTED); + + +#ifdef DEBUG_PTS + pr_info("pts missed %ld, pts hit %ld, duration %d\n", + pbi->pts_missed, pbi->pts_hit, pbi->frame_dur); +#endif + /* devm_kfree(&pdev->dev, (void *)pbi); */ + vfree((void *)pbi); + return 0; +} + +static struct platform_driver ammvdec_vp9_driver = { + .probe = ammvdec_vp9_probe, + .remove = ammvdec_vp9_remove, +#ifdef CONFIG_PM + .suspend = amhevc_suspend, + .resume = amhevc_resume, +#endif + .driver = { + .name = MULTI_DRIVER_NAME, + } +}; +#endif +static struct mconfig vp9_configs[] = { + MC_PU32("bit_depth_luma", &bit_depth_luma), + MC_PU32("bit_depth_chroma", &bit_depth_chroma), + MC_PU32("frame_width", &frame_width), + MC_PU32("frame_height", &frame_height), + MC_PU32("debug", &debug), + MC_PU32("radr", &radr), + MC_PU32("rval", &rval), + MC_PU32("pop_shorts", &pop_shorts), + MC_PU32("dbg_cmd", &dbg_cmd), + MC_PU32("dbg_skip_decode_index", &dbg_skip_decode_index), + MC_PU32("endian", &endian), + MC_PU32("step", &step), + MC_PU32("udebug_flag", &udebug_flag), + MC_PU32("decode_pic_begin", &decode_pic_begin), + MC_PU32("slice_parse_begin", &slice_parse_begin), + MC_PU32("i_only_flag", &i_only_flag), + MC_PU32("error_handle_policy", &error_handle_policy), + MC_PU32("buf_alloc_width", &buf_alloc_width), + MC_PU32("buf_alloc_height", &buf_alloc_height), + MC_PU32("buf_alloc_depth", &buf_alloc_depth), + MC_PU32("buf_alloc_size", &buf_alloc_size), + MC_PU32("buffer_mode", &buffer_mode), + MC_PU32("buffer_mode_dbg", &buffer_mode_dbg), + MC_PU32("max_buf_num", &max_buf_num), + MC_PU32("dynamic_buf_num_margin", &dynamic_buf_num_margin), + MC_PU32("mem_map_mode", &mem_map_mode), + MC_PU32("double_write_mode", &double_write_mode), + MC_PU32("enable_mem_saving", &enable_mem_saving), + MC_PU32("force_w_h", &force_w_h), + MC_PU32("force_fps", &force_fps), + MC_PU32("max_decoding_time", &max_decoding_time), + MC_PU32("on_no_keyframe_skiped", &on_no_keyframe_skiped), + MC_PU32("start_decode_buf_level", &start_decode_buf_level), + MC_PU32("decode_timeout_val", &decode_timeout_val), + MC_PU32("vp9_max_pic_w", &vp9_max_pic_w), + MC_PU32("vp9_max_pic_h", &vp9_max_pic_h), +}; +static struct mconfig_node vp9_node; + +static int __init amvdec_vp9_driver_init_module(void) +{ + +#ifdef VP9_10B_MMU + + struct BuffInfo_s *p_buf_info; +#ifdef SUPPORT_4K2K + if (vdec_is_support_4k()) + p_buf_info = &amvvp9_workbuff_spec[1]; + else + p_buf_info = &amvvp9_workbuff_spec[0]; +#else + p_buf_info = &amvvp9_workbuff_spec[0]; +#endif + init_buff_spec(NULL, p_buf_info); + work_buf_size = + (p_buf_info->end_adr - p_buf_info->start_adr + + 0xffff) & (~0xffff); + +#endif + pr_debug("amvdec_vp9 module init\n"); + error_handle_policy = 0; + +#ifdef ERROR_HANDLE_DEBUG + dbg_nal_skip_flag = 0; + dbg_nal_skip_count = 0; +#endif + udebug_flag = 0; + decode_pic_begin = 0; + slice_parse_begin = 0; + step = 0; + buf_alloc_size = 0; +#ifdef MULTI_INSTANCE_SUPPORT + if (platform_driver_register(&ammvdec_vp9_driver)) + pr_err("failed to register ammvdec_vp9 driver\n"); + +#endif + if (platform_driver_register(&amvdec_vp9_driver)) { + pr_err("failed to register amvdec_vp9 driver\n"); + return -ENODEV; + } + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL + /*&& get_cpu_type() != MESON_CPU_MAJOR_ID_GXLX*/) { + if (vdec_is_support_4k()) + amvdec_vp9_profile.profile = + "4k, 10bit, dwrite, compressed"; + else + amvdec_vp9_profile.profile = + "10bit, dwrite, compressed"; + } else { + amvdec_vp9_profile.name = "vp9_unsupport"; + } + + vcodec_profile_register(&amvdec_vp9_profile); + INIT_REG_NODE_CONFIGS("media.decoder", &vp9_node, + "vp9", vp9_configs, CONFIG_FOR_RW); + + return 0; +} + +static void __exit amvdec_vp9_driver_remove_module(void) +{ + pr_debug("amvdec_vp9 module remove.\n"); +#ifdef MULTI_INSTANCE_SUPPORT + platform_driver_unregister(&ammvdec_vp9_driver); +#endif + platform_driver_unregister(&amvdec_vp9_driver); +} + +/****************************************/ + +module_param(bit_depth_luma, uint, 0664); +MODULE_PARM_DESC(bit_depth_luma, "\n amvdec_vp9 bit_depth_luma\n"); + +module_param(bit_depth_chroma, uint, 0664); +MODULE_PARM_DESC(bit_depth_chroma, "\n amvdec_vp9 bit_depth_chroma\n"); + +module_param(frame_width, uint, 0664); +MODULE_PARM_DESC(frame_width, "\n amvdec_vp9 frame_width\n"); + +module_param(frame_height, uint, 0664); +MODULE_PARM_DESC(frame_height, "\n amvdec_vp9 frame_height\n"); + +module_param(debug, uint, 0664); +MODULE_PARM_DESC(debug, "\n amvdec_vp9 debug\n"); + +module_param(radr, uint, 0664); +MODULE_PARM_DESC(radr, "\n radr\n"); + +module_param(rval, uint, 0664); +MODULE_PARM_DESC(rval, "\n rval\n"); + +module_param(pop_shorts, uint, 0664); +MODULE_PARM_DESC(pop_shorts, "\n rval\n"); + +module_param(dbg_cmd, uint, 0664); +MODULE_PARM_DESC(dbg_cmd, "\n dbg_cmd\n"); + +module_param(dbg_skip_decode_index, uint, 0664); +MODULE_PARM_DESC(dbg_skip_decode_index, "\n dbg_skip_decode_index\n"); + +module_param(endian, uint, 0664); +MODULE_PARM_DESC(endian, "\n rval\n"); + +module_param(step, uint, 0664); +MODULE_PARM_DESC(step, "\n amvdec_vp9 step\n"); + +module_param(decode_pic_begin, uint, 0664); +MODULE_PARM_DESC(decode_pic_begin, "\n amvdec_vp9 decode_pic_begin\n"); + +module_param(slice_parse_begin, uint, 0664); +MODULE_PARM_DESC(slice_parse_begin, "\n amvdec_vp9 slice_parse_begin\n"); + +module_param(i_only_flag, uint, 0664); +MODULE_PARM_DESC(i_only_flag, "\n amvdec_vp9 i_only_flag\n"); + +module_param(error_handle_policy, uint, 0664); +MODULE_PARM_DESC(error_handle_policy, "\n amvdec_vp9 error_handle_policy\n"); + +module_param(buf_alloc_width, uint, 0664); +MODULE_PARM_DESC(buf_alloc_width, "\n buf_alloc_width\n"); + +module_param(buf_alloc_height, uint, 0664); +MODULE_PARM_DESC(buf_alloc_height, "\n buf_alloc_height\n"); + +module_param(buf_alloc_depth, uint, 0664); +MODULE_PARM_DESC(buf_alloc_depth, "\n buf_alloc_depth\n"); + +module_param(buf_alloc_size, uint, 0664); +MODULE_PARM_DESC(buf_alloc_size, "\n buf_alloc_size\n"); + +module_param(buffer_mode, uint, 0664); +MODULE_PARM_DESC(buffer_mode, "\n buffer_mode\n"); + +module_param(buffer_mode_dbg, uint, 0664); +MODULE_PARM_DESC(buffer_mode_dbg, "\n buffer_mode_dbg\n"); +/*USE_BUF_BLOCK*/ +module_param(max_buf_num, uint, 0664); +MODULE_PARM_DESC(max_buf_num, "\n max_buf_num\n"); + +module_param(dynamic_buf_num_margin, uint, 0664); +MODULE_PARM_DESC(dynamic_buf_num_margin, "\n dynamic_buf_num_margin\n"); + +module_param(mv_buf_margin, uint, 0664); +MODULE_PARM_DESC(mv_buf_margin, "\n mv_buf_margin\n"); + +module_param(run_ready_min_buf_num, uint, 0664); +MODULE_PARM_DESC(run_ready_min_buf_num, "\n run_ready_min_buf_num\n"); + +/**/ + +module_param(mem_map_mode, uint, 0664); +MODULE_PARM_DESC(mem_map_mode, "\n mem_map_mode\n"); + +#ifdef SUPPORT_10BIT +module_param(double_write_mode, uint, 0664); +MODULE_PARM_DESC(double_write_mode, "\n double_write_mode\n"); + +module_param(enable_mem_saving, uint, 0664); +MODULE_PARM_DESC(enable_mem_saving, "\n enable_mem_saving\n"); + +module_param(force_w_h, uint, 0664); +MODULE_PARM_DESC(force_w_h, "\n force_w_h\n"); +#endif + +module_param(force_fps, uint, 0664); +MODULE_PARM_DESC(force_fps, "\n force_fps\n"); + +module_param(max_decoding_time, uint, 0664); +MODULE_PARM_DESC(max_decoding_time, "\n max_decoding_time\n"); + +module_param(on_no_keyframe_skiped, uint, 0664); +MODULE_PARM_DESC(on_no_keyframe_skiped, "\n on_no_keyframe_skiped\n"); + +module_param(mcrcc_cache_alg_flag, uint, 0664); +MODULE_PARM_DESC(mcrcc_cache_alg_flag, "\n mcrcc_cache_alg_flag\n"); + +#ifdef MULTI_INSTANCE_SUPPORT +module_param(start_decode_buf_level, int, 0664); +MODULE_PARM_DESC(start_decode_buf_level, + "\n vp9 start_decode_buf_level\n"); + +module_param(decode_timeout_val, uint, 0664); +MODULE_PARM_DESC(decode_timeout_val, + "\n vp9 decode_timeout_val\n"); + +module_param(vp9_max_pic_w, uint, 0664); +MODULE_PARM_DESC(vp9_max_pic_w, "\n vp9_max_pic_w\n"); + +module_param(vp9_max_pic_h, uint, 0664); +MODULE_PARM_DESC(vp9_max_pic_h, "\n vp9_max_pic_h\n"); + +module_param_array(decode_frame_count, uint, + &max_decode_instance_num, 0664); + +module_param_array(display_frame_count, uint, + &max_decode_instance_num, 0664); + +module_param_array(max_process_time, uint, + &max_decode_instance_num, 0664); + +module_param_array(run_count, uint, + &max_decode_instance_num, 0664); + +module_param_array(input_empty, uint, + &max_decode_instance_num, 0664); + +module_param_array(not_run_ready, uint, + &max_decode_instance_num, 0664); +#endif + +#ifdef SUPPORT_FB_DECODING +module_param_array(not_run2_ready, uint, + &max_decode_instance_num, 0664); + +module_param_array(run2_count, uint, + &max_decode_instance_num, 0664); + +module_param(stage_buf_num, uint, 0664); +MODULE_PARM_DESC(stage_buf_num, "\n amvdec_h265 stage_buf_num\n"); +#endif + +module_param(udebug_flag, uint, 0664); +MODULE_PARM_DESC(udebug_flag, "\n amvdec_h265 udebug_flag\n"); + +module_param(udebug_pause_pos, uint, 0664); +MODULE_PARM_DESC(udebug_pause_pos, "\n udebug_pause_pos\n"); + +module_param(udebug_pause_val, uint, 0664); +MODULE_PARM_DESC(udebug_pause_val, "\n udebug_pause_val\n"); + +module_param(udebug_pause_decode_idx, uint, 0664); +MODULE_PARM_DESC(udebug_pause_decode_idx, "\n udebug_pause_decode_idx\n"); + +module_init(amvdec_vp9_driver_init_module); +module_exit(amvdec_vp9_driver_remove_module); + +MODULE_DESCRIPTION("AMLOGIC vp9 Video Decoder Driver"); +MODULE_LICENSE("GPL"); + diff --git a/drivers/amlogic/media_modules/frame_provider/decoder/vp9/vvp9.h b/drivers/amlogic/media_modules/frame_provider/decoder/vp9/vvp9.h new file mode 100644 index 000000000000..3f4959ccccc2 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_provider/decoder/vp9/vvp9.h @@ -0,0 +1,23 @@ +/* + * drivers/amlogic/amports/vvp9.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef VVP9_H +#define VVP9_H +#define VP9_10B_MMU +void adapt_coef_probs(int pic_count, int prev_kf, int cur_kf, int pre_fc, +unsigned int *prev_prob, unsigned int *cur_prob, unsigned int *count); +#endif diff --git a/drivers/amlogic/media_modules/frame_sink/Makefile b/drivers/amlogic/media_modules/frame_sink/Makefile new file mode 100644 index 000000000000..2b9754a3947e --- /dev/null +++ b/drivers/amlogic/media_modules/frame_sink/Makefile @@ -0,0 +1 @@ +obj-y += encoder/ diff --git a/drivers/amlogic/media_modules/frame_sink/encoder/Makefile b/drivers/amlogic/media_modules/frame_sink/encoder/Makefile new file mode 100644 index 000000000000..9afecec9265f --- /dev/null +++ b/drivers/amlogic/media_modules/frame_sink/encoder/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_AMLOGIC_MEDIA_VENC_H264) += h264/ +obj-$(CONFIG_AMLOGIC_MEDIA_VENC_H265) += h265/ diff --git a/drivers/amlogic/media_modules/frame_sink/encoder/h264/Makefile b/drivers/amlogic/media_modules/frame_sink/encoder/h264/Makefile new file mode 100644 index 000000000000..c12d7c3d86b2 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_sink/encoder/h264/Makefile @@ -0,0 +1 @@ +obj-m += encoder.o diff --git a/drivers/amlogic/media_modules/frame_sink/encoder/h264/encoder.c b/drivers/amlogic/media_modules/frame_sink/encoder/h264/encoder.c new file mode 100644 index 000000000000..48e701a56ee5 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_sink/encoder/h264/encoder.c @@ -0,0 +1,4275 @@ +/* + * drivers/amlogic/amports/encoder.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "../../../frame_provider/decoder/utils/vdec.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include "encoder.h" +#include "../../../frame_provider/decoder/utils/amvdec.h" +#include +#include "../../../stream_input/amports/amports_priv.h" +#include "../../../frame_provider/decoder/utils/firmware.h" +#include +#ifdef CONFIG_AM_JPEG_ENCODER +#include "jpegenc.h" +#endif + +#define ENCODE_NAME "encoder" +#define AMVENC_CANVAS_INDEX 0xE4 +#define AMVENC_CANVAS_MAX_INDEX 0xEF + +#define MIN_SIZE amvenc_buffspec[0].min_buffsize +#define DUMP_INFO_BYTES_PER_MB 80 + +#define ADJUSTED_QP_FLAG 64 + +static s32 avc_device_major; +static struct device *amvenc_avc_dev; +#define DRIVER_NAME "amvenc_avc" +#define CLASS_NAME "amvenc_avc" +#define DEVICE_NAME "amvenc_avc" + +static struct encode_manager_s encode_manager; + +#define MULTI_SLICE_MC +#define H264_ENC_CBR +/* #define MORE_MODULE_PARAM */ + +#define ENC_CANVAS_OFFSET AMVENC_CANVAS_INDEX + +#define UCODE_MODE_FULL 0 + +/* #define ENABLE_IGNORE_FUNCTION */ + +static u32 ie_me_mb_type; +static u32 ie_me_mode; +static u32 ie_pippeline_block = 3; +static u32 ie_cur_ref_sel; +/* static u32 avc_endian = 6; */ +static u32 clock_level = 5; + +static u32 encode_print_level = LOG_DEBUG; +static u32 no_timeout; +static int nr_mode = -1; +static u32 qp_table_debug; + +static u32 me_mv_merge_ctl = + (0x1 << 31) | /* [31] me_merge_mv_en_16 */ + (0x1 << 30) | /* [30] me_merge_small_mv_en_16 */ + (0x1 << 29) | /* [29] me_merge_flex_en_16 */ + (0x1 << 28) | /* [28] me_merge_sad_en_16 */ + (0x1 << 27) | /* [27] me_merge_mv_en_8 */ + (0x1 << 26) | /* [26] me_merge_small_mv_en_8 */ + (0x1 << 25) | /* [25] me_merge_flex_en_8 */ + (0x1 << 24) | /* [24] me_merge_sad_en_8 */ + /* [23:18] me_merge_mv_diff_16 - MV diff <= n pixel can be merged */ + (0x12 << 18) | + /* [17:12] me_merge_mv_diff_8 - MV diff <= n pixel can be merged */ + (0x2b << 12) | + /* [11:0] me_merge_min_sad - SAD >= 0x180 can be merged with other MV */ + (0x80 << 0); + /* ( 0x4 << 18) | + * // [23:18] me_merge_mv_diff_16 - MV diff <= n pixel can be merged + */ + /* ( 0x3f << 12) | + * // [17:12] me_merge_mv_diff_8 - MV diff <= n pixel can be merged + */ + /* ( 0xc0 << 0); + * // [11:0] me_merge_min_sad - SAD >= 0x180 can be merged with other MV + */ + +static u32 me_mv_weight_01 = (0x40 << 24) | (0x30 << 16) | (0x20 << 8) | 0x30; +static u32 me_mv_weight_23 = (0x40 << 8) | 0x30; +static u32 me_sad_range_inc = 0x03030303; +static u32 me_step0_close_mv = 0x003ffc21; +static u32 me_f_skip_sad; +static u32 me_f_skip_weight; +static u32 me_sad_enough_01;/* 0x00018010; */ +static u32 me_sad_enough_23;/* 0x00000020; */ + +/* [31:0] NUM_ROWS_PER_SLICE_P */ +/* [15:0] NUM_ROWS_PER_SLICE_I */ +static u32 fixed_slice_cfg; + +/* y tnr */ +static unsigned int y_tnr_mc_en = 1; +static unsigned int y_tnr_txt_mode; +static unsigned int y_tnr_mot_sad_margin = 1; +static unsigned int y_tnr_mot_cortxt_rate = 1; +static unsigned int y_tnr_mot_distxt_ofst = 5; +static unsigned int y_tnr_mot_distxt_rate = 4; +static unsigned int y_tnr_mot_dismot_ofst = 4; +static unsigned int y_tnr_mot_frcsad_lock = 8; +static unsigned int y_tnr_mot2alp_frc_gain = 10; +static unsigned int y_tnr_mot2alp_nrm_gain = 216; +static unsigned int y_tnr_mot2alp_dis_gain = 128; +static unsigned int y_tnr_mot2alp_dis_ofst = 32; +static unsigned int y_tnr_alpha_min = 32; +static unsigned int y_tnr_alpha_max = 63; +static unsigned int y_tnr_deghost_os; +/* c tnr */ +static unsigned int c_tnr_mc_en = 1; +static unsigned int c_tnr_txt_mode; +static unsigned int c_tnr_mot_sad_margin = 1; +static unsigned int c_tnr_mot_cortxt_rate = 1; +static unsigned int c_tnr_mot_distxt_ofst = 5; +static unsigned int c_tnr_mot_distxt_rate = 4; +static unsigned int c_tnr_mot_dismot_ofst = 4; +static unsigned int c_tnr_mot_frcsad_lock = 8; +static unsigned int c_tnr_mot2alp_frc_gain = 10; +static unsigned int c_tnr_mot2alp_nrm_gain = 216; +static unsigned int c_tnr_mot2alp_dis_gain = 128; +static unsigned int c_tnr_mot2alp_dis_ofst = 32; +static unsigned int c_tnr_alpha_min = 32; +static unsigned int c_tnr_alpha_max = 63; +static unsigned int c_tnr_deghost_os; +/* y snr */ +static unsigned int y_snr_err_norm = 1; +static unsigned int y_snr_gau_bld_core = 1; +static int y_snr_gau_bld_ofst = -1; +static unsigned int y_snr_gau_bld_rate = 48; +static unsigned int y_snr_gau_alp0_min; +static unsigned int y_snr_gau_alp0_max = 63; +static unsigned int y_bld_beta2alp_rate = 16; +static unsigned int y_bld_beta_min; +static unsigned int y_bld_beta_max = 63; +/* c snr */ +static unsigned int c_snr_err_norm = 1; +static unsigned int c_snr_gau_bld_core = 1; +static int c_snr_gau_bld_ofst = -1; +static unsigned int c_snr_gau_bld_rate = 48; +static unsigned int c_snr_gau_alp0_min; +static unsigned int c_snr_gau_alp0_max = 63; +static unsigned int c_bld_beta2alp_rate = 16; +static unsigned int c_bld_beta_min; +static unsigned int c_bld_beta_max = 63; + +static DEFINE_SPINLOCK(lock); + +#define ADV_MV_LARGE_16x8 1 +#define ADV_MV_LARGE_8x16 1 +#define ADV_MV_LARGE_16x16 1 + +/* me weight offset should not very small, it used by v1 me module. */ +/* the min real sad for me is 16 by hardware. */ +#define ME_WEIGHT_OFFSET 0x520 +#define I4MB_WEIGHT_OFFSET 0x655 +#define I16MB_WEIGHT_OFFSET 0x560 + +#define ADV_MV_16x16_WEIGHT 0x080 +#define ADV_MV_16_8_WEIGHT 0x0e0 +#define ADV_MV_8x8_WEIGHT 0x240 +#define ADV_MV_4x4x4_WEIGHT 0x3000 + +#define IE_SAD_SHIFT_I16 0x001 +#define IE_SAD_SHIFT_I4 0x001 +#define ME_SAD_SHIFT_INTER 0x001 + +#define STEP_2_SKIP_SAD 0 +#define STEP_1_SKIP_SAD 0 +#define STEP_0_SKIP_SAD 0 +#define STEP_2_SKIP_WEIGHT 0 +#define STEP_1_SKIP_WEIGHT 0 +#define STEP_0_SKIP_WEIGHT 0 + +#define ME_SAD_RANGE_0 0x1 /* 0x0 */ +#define ME_SAD_RANGE_1 0x0 +#define ME_SAD_RANGE_2 0x0 +#define ME_SAD_RANGE_3 0x0 + +/* use 0 for v3, 0x18 for v2 */ +#define ME_MV_PRE_WEIGHT_0 0x18 +/* use 0 for v3, 0x18 for v2 */ +#define ME_MV_PRE_WEIGHT_1 0x18 +#define ME_MV_PRE_WEIGHT_2 0x0 +#define ME_MV_PRE_WEIGHT_3 0x0 + +/* use 0 for v3, 0x18 for v2 */ +#define ME_MV_STEP_WEIGHT_0 0x18 +/* use 0 for v3, 0x18 for v2 */ +#define ME_MV_STEP_WEIGHT_1 0x18 +#define ME_MV_STEP_WEIGHT_2 0x0 +#define ME_MV_STEP_WEIGHT_3 0x0 + +#define ME_SAD_ENOUGH_0_DATA 0x00 +#define ME_SAD_ENOUGH_1_DATA 0x04 +#define ME_SAD_ENOUGH_2_DATA 0x11 +#define ADV_MV_8x8_ENOUGH_DATA 0x20 + +/* V4_COLOR_BLOCK_FIX */ +#define V3_FORCE_SKIP_SAD_0 0x10 +/* 4 Blocks */ +#define V3_FORCE_SKIP_SAD_1 0x60 +/* 16 Blocks + V3_SKIP_WEIGHT_2 */ +#define V3_FORCE_SKIP_SAD_2 0x250 +/* almost disable it -- use t_lac_coeff_2 output to F_ZERO is better */ +#define V3_ME_F_ZERO_SAD (ME_WEIGHT_OFFSET + 0x10) + +#define V3_IE_F_ZERO_SAD_I16 (I16MB_WEIGHT_OFFSET + 0x10) +#define V3_IE_F_ZERO_SAD_I4 (I4MB_WEIGHT_OFFSET + 0x20) + +#define V3_SKIP_WEIGHT_0 0x10 +/* 4 Blocks 8 separate search sad can be very low */ +#define V3_SKIP_WEIGHT_1 0x8 /* (4 * ME_MV_STEP_WEIGHT_1 + 0x100) */ +#define V3_SKIP_WEIGHT_2 0x3 + +#define V3_LEVEL_1_F_SKIP_MAX_SAD 0x0 +#define V3_LEVEL_1_SKIP_MAX_SAD 0x6 + +#define I4_ipred_weight_most 0x18 +#define I4_ipred_weight_else 0x28 + +#define C_ipred_weight_V 0x04 +#define C_ipred_weight_H 0x08 +#define C_ipred_weight_DC 0x0c + +#define I16_ipred_weight_V 0x04 +#define I16_ipred_weight_H 0x08 +#define I16_ipred_weight_DC 0x0c + +/* 0x00 same as disable */ +#define v3_left_small_max_ie_sad 0x00 +#define v3_left_small_max_me_sad 0x40 + +#define v5_use_small_diff_cnt 0 +#define v5_simple_mb_inter_all_en 1 +#define v5_simple_mb_inter_8x8_en 1 +#define v5_simple_mb_inter_16_8_en 1 +#define v5_simple_mb_inter_16x16_en 1 +#define v5_simple_mb_intra_en 1 +#define v5_simple_mb_C_en 0 +#define v5_simple_mb_Y_en 1 +#define v5_small_diff_Y 0x10 +#define v5_small_diff_C 0x18 +/* shift 8-bits, 2, 1, 0, -1, -2, -3, -4 */ +#define v5_simple_dq_setting 0x43210fed +#define v5_simple_me_weight_setting 0 + +#ifdef H264_ENC_CBR +#define CBR_TABLE_SIZE 0x800 +#define CBR_SHORT_SHIFT 12 /* same as disable */ +#define CBR_LONG_MB_NUM 2 +#define START_TABLE_ID 8 +#define CBR_LONG_THRESH 4 +#endif + +static u32 v3_mv_sad[64] = { + /* For step0 */ + 0x00000004, + 0x00010008, + 0x00020010, + 0x00030018, + 0x00040020, + 0x00050028, + 0x00060038, + 0x00070048, + 0x00080058, + 0x00090068, + 0x000a0080, + 0x000b0098, + 0x000c00b0, + 0x000d00c8, + 0x000e00e8, + 0x000f0110, + /* For step1 */ + 0x00100002, + 0x00110004, + 0x00120008, + 0x0013000c, + 0x00140010, + 0x00150014, + 0x0016001c, + 0x00170024, + 0x0018002c, + 0x00190034, + 0x001a0044, + 0x001b0054, + 0x001c0064, + 0x001d0074, + 0x001e0094, + 0x001f00b4, + /* For step2 */ + 0x00200006, + 0x0021000c, + 0x0022000c, + 0x00230018, + 0x00240018, + 0x00250018, + 0x00260018, + 0x00270030, + 0x00280030, + 0x00290030, + 0x002a0030, + 0x002b0030, + 0x002c0030, + 0x002d0030, + 0x002e0030, + 0x002f0050, + /* For step2 4x4-8x8 */ + 0x00300001, + 0x00310002, + 0x00320002, + 0x00330004, + 0x00340004, + 0x00350004, + 0x00360004, + 0x00370006, + 0x00380006, + 0x00390006, + 0x003a0006, + 0x003b0006, + 0x003c0006, + 0x003d0006, + 0x003e0006, + 0x003f0006 +}; + +static struct BuffInfo_s amvenc_buffspec[] = { + { + .lev_id = 0, + .max_width = 1920, + .max_height = 1088, + .min_buffsize = 0x1400000, + .dct = { + .buf_start = 0, + .buf_size = 0x800000, /* 1920x1088x4 */ + }, + .dec0_y = { + .buf_start = 0x800000, + .buf_size = 0x300000, + }, + .dec1_y = { + .buf_start = 0xb00000, + .buf_size = 0x300000, + }, + .assit = { + .buf_start = 0xe10000, + .buf_size = 0xc0000, + }, + .bitstream = { + .buf_start = 0xf00000, + .buf_size = 0x100000, + }, + .scale_buff = { + .buf_start = 0x1000000, + .buf_size = 0x300000, + }, + .dump_info = { + .buf_start = 0x1300000, + .buf_size = 0xa0000, /* (1920x1088/256)x80 */ + }, + .cbr_info = { + .buf_start = 0x13b0000, + .buf_size = 0x2000, + } + } +}; + +enum ucode_type_e { + UCODE_GXL, + UCODE_TXL, + UCODE_G12A, + UCODE_MAX +}; + +const char *ucode_name[] = { + "gxl_h264_enc", + "txl_h264_enc_cavlc", + "ga_h264_enc_cabac", +}; + +static void dma_flush(u32 buf_start, u32 buf_size); +static void cache_flush(u32 buf_start, u32 buf_size); + +static const char *select_ucode(u32 ucode_index) +{ + enum ucode_type_e ucode = UCODE_GXL; + + switch (ucode_index) { + case UCODE_MODE_FULL: + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) + ucode = UCODE_G12A; + else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXL) + ucode = UCODE_TXL; + else /* (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) */ + ucode = UCODE_GXL; + break; + break; + default: + break; + } + return (const char *)ucode_name[ucode]; +} + +static void hcodec_prog_qtbl(struct encode_wq_s *wq) +{ + WRITE_HREG(HCODEC_Q_QUANT_CONTROL, + (0 << 23) | /* quant_table_addr */ + (1 << 22)); /* quant_table_addr_update */ + + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_i4[0]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_i4[1]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_i4[2]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_i4[3]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_i4[4]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_i4[5]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_i4[6]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_i4[7]); + + WRITE_HREG(HCODEC_Q_QUANT_CONTROL, + (8 << 23) | /* quant_table_addr */ + (1 << 22)); /* quant_table_addr_update */ + + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_i16[0]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_i16[1]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_i16[2]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_i16[3]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_i16[4]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_i16[5]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_i16[6]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_i16[7]); + + WRITE_HREG(HCODEC_Q_QUANT_CONTROL, + (16 << 23) | /* quant_table_addr */ + (1 << 22)); /* quant_table_addr_update */ + + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_me[0]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_me[1]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_me[2]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_me[3]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_me[4]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_me[5]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_me[6]); + WRITE_HREG(HCODEC_QUANT_TABLE_DATA, + wq->quant_tbl_me[7]); +} + +static void InitEncodeWeight(void) +{ + me_mv_merge_ctl = + (0x1 << 31) | /* [31] me_merge_mv_en_16 */ + (0x1 << 30) | /* [30] me_merge_small_mv_en_16 */ + (0x1 << 29) | /* [29] me_merge_flex_en_16 */ + (0x1 << 28) | /* [28] me_merge_sad_en_16 */ + (0x1 << 27) | /* [27] me_merge_mv_en_8 */ + (0x1 << 26) | /* [26] me_merge_small_mv_en_8 */ + (0x1 << 25) | /* [25] me_merge_flex_en_8 */ + (0x1 << 24) | /* [24] me_merge_sad_en_8 */ + (0x12 << 18) | + /* [23:18] me_merge_mv_diff_16 - MV diff + * <= n pixel can be merged + */ + (0x2b << 12) | + /* [17:12] me_merge_mv_diff_8 - MV diff + * <= n pixel can be merged + */ + (0x80 << 0); + /* [11:0] me_merge_min_sad - SAD + * >= 0x180 can be merged with other MV + */ + + me_mv_weight_01 = (ME_MV_STEP_WEIGHT_1 << 24) | + (ME_MV_PRE_WEIGHT_1 << 16) | + (ME_MV_STEP_WEIGHT_0 << 8) | + (ME_MV_PRE_WEIGHT_0 << 0); + + me_mv_weight_23 = (ME_MV_STEP_WEIGHT_3 << 24) | + (ME_MV_PRE_WEIGHT_3 << 16) | + (ME_MV_STEP_WEIGHT_2 << 8) | + (ME_MV_PRE_WEIGHT_2 << 0); + + me_sad_range_inc = (ME_SAD_RANGE_3 << 24) | + (ME_SAD_RANGE_2 << 16) | + (ME_SAD_RANGE_1 << 8) | + (ME_SAD_RANGE_0 << 0); + + me_step0_close_mv = (0x100 << 10) | + /* me_step0_big_sad -- two MV sad + * diff bigger will use use 1 + */ + (2 << 5) | /* me_step0_close_mv_y */ + (2 << 0); /* me_step0_close_mv_x */ + + me_f_skip_sad = (0x00 << 24) | /* force_skip_sad_3 */ + (STEP_2_SKIP_SAD << 16) | /* force_skip_sad_2 */ + (STEP_1_SKIP_SAD << 8) | /* force_skip_sad_1 */ + (STEP_0_SKIP_SAD << 0); /* force_skip_sad_0 */ + + me_f_skip_weight = (0x00 << 24) | /* force_skip_weight_3 */ + /* force_skip_weight_2 */ + (STEP_2_SKIP_WEIGHT << 16) | + /* force_skip_weight_1 */ + (STEP_1_SKIP_WEIGHT << 8) | + /* force_skip_weight_0 */ + (STEP_0_SKIP_WEIGHT << 0); + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { + me_f_skip_sad = 0; + me_f_skip_weight = 0; + me_mv_weight_01 = 0; + me_mv_weight_23 = 0; + } + + me_sad_enough_01 = (ME_SAD_ENOUGH_1_DATA << 12) | + /* me_sad_enough_1 */ + (ME_SAD_ENOUGH_0_DATA << 0) | + /* me_sad_enough_0 */ + (0 << 12) | /* me_sad_enough_1 */ + (0 << 0); /* me_sad_enough_0 */ + + me_sad_enough_23 = (ADV_MV_8x8_ENOUGH_DATA << 12) | + /* adv_mv_8x8_enough */ + (ME_SAD_ENOUGH_2_DATA << 0) | + /* me_sad_enough_2 */ + (0 << 12) | /* me_sad_enough_3 */ + (0 << 0); /* me_sad_enough_2 */ +} + +/*output stream buffer setting*/ +static void avc_init_output_buffer(struct encode_wq_s *wq) +{ + WRITE_HREG(HCODEC_VLC_VB_MEM_CTL, + ((1 << 31) | (0x3f << 24) | + (0x20 << 16) | (2 << 0))); + WRITE_HREG(HCODEC_VLC_VB_START_PTR, + wq->mem.BitstreamStart); + WRITE_HREG(HCODEC_VLC_VB_WR_PTR, + wq->mem.BitstreamStart); + WRITE_HREG(HCODEC_VLC_VB_SW_RD_PTR, + wq->mem.BitstreamStart); + WRITE_HREG(HCODEC_VLC_VB_END_PTR, + wq->mem.BitstreamEnd); + WRITE_HREG(HCODEC_VLC_VB_CONTROL, 1); + WRITE_HREG(HCODEC_VLC_VB_CONTROL, + ((0 << 14) | (7 << 3) | + (1 << 1) | (0 << 0))); +} + +/*input dct buffer setting*/ +static void avc_init_input_buffer(struct encode_wq_s *wq) +{ + WRITE_HREG(HCODEC_QDCT_MB_START_PTR, + wq->mem.dct_buff_start_addr); + WRITE_HREG(HCODEC_QDCT_MB_END_PTR, + wq->mem.dct_buff_end_addr); + WRITE_HREG(HCODEC_QDCT_MB_WR_PTR, + wq->mem.dct_buff_start_addr); + WRITE_HREG(HCODEC_QDCT_MB_RD_PTR, + wq->mem.dct_buff_start_addr); + WRITE_HREG(HCODEC_QDCT_MB_BUFF, 0); +} + +/*input reference buffer setting*/ +static void avc_init_reference_buffer(s32 canvas) +{ + WRITE_HREG(HCODEC_ANC0_CANVAS_ADDR, canvas); + WRITE_HREG(HCODEC_VLC_HCMD_CONFIG, 0); +} + +static void avc_init_assit_buffer(struct encode_wq_s *wq) +{ + WRITE_HREG(MEM_OFFSET_REG, wq->mem.assit_buffer_offset); +} + +/*deblock buffer setting, same as INI_CANVAS*/ +static void avc_init_dblk_buffer(s32 canvas) +{ + WRITE_HREG(HCODEC_REC_CANVAS_ADDR, canvas); + WRITE_HREG(HCODEC_DBKR_CANVAS_ADDR, canvas); + WRITE_HREG(HCODEC_DBKW_CANVAS_ADDR, canvas); +} + +static void avc_init_encoder(struct encode_wq_s *wq, bool idr) +{ + WRITE_HREG(HCODEC_VLC_TOTAL_BYTES, 0); + WRITE_HREG(HCODEC_VLC_CONFIG, 0x07); + WRITE_HREG(HCODEC_VLC_INT_CONTROL, 0); + + WRITE_HREG(HCODEC_ASSIST_AMR1_INT0, 0x15); + WRITE_HREG(HCODEC_ASSIST_AMR1_INT1, 0x8); + WRITE_HREG(HCODEC_ASSIST_AMR1_INT3, 0x14); + + WRITE_HREG(IDR_PIC_ID, wq->pic.idr_pic_id); + WRITE_HREG(FRAME_NUMBER, + (idr == true) ? 0 : wq->pic.frame_number); + WRITE_HREG(PIC_ORDER_CNT_LSB, + (idr == true) ? 0 : wq->pic.pic_order_cnt_lsb); + + WRITE_HREG(LOG2_MAX_PIC_ORDER_CNT_LSB, + wq->pic.log2_max_pic_order_cnt_lsb); + WRITE_HREG(LOG2_MAX_FRAME_NUM, + wq->pic.log2_max_frame_num); + WRITE_HREG(ANC0_BUFFER_ID, 0); + WRITE_HREG(QPPICTURE, wq->pic.init_qppicture); +} + +static void avc_canvas_init(struct encode_wq_s *wq) +{ + u32 canvas_width, canvas_height; + u32 start_addr = wq->mem.buf_start; + + canvas_width = ((wq->pic.encoder_width + 31) >> 5) << 5; + canvas_height = ((wq->pic.encoder_height + 15) >> 4) << 4; + + canvas_config(ENC_CANVAS_OFFSET, + start_addr + wq->mem.bufspec.dec0_y.buf_start, + canvas_width, canvas_height, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); + canvas_config(1 + ENC_CANVAS_OFFSET, + start_addr + wq->mem.bufspec.dec0_uv.buf_start, + canvas_width, canvas_height / 2, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); + /*here the third plane use the same address as the second plane*/ + canvas_config(2 + ENC_CANVAS_OFFSET, + start_addr + wq->mem.bufspec.dec0_uv.buf_start, + canvas_width, canvas_height / 2, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); + + canvas_config(3 + ENC_CANVAS_OFFSET, + start_addr + wq->mem.bufspec.dec1_y.buf_start, + canvas_width, canvas_height, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); + canvas_config(4 + ENC_CANVAS_OFFSET, + start_addr + wq->mem.bufspec.dec1_uv.buf_start, + canvas_width, canvas_height / 2, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); + /*here the third plane use the same address as the second plane*/ + canvas_config(5 + ENC_CANVAS_OFFSET, + start_addr + wq->mem.bufspec.dec1_uv.buf_start, + canvas_width, canvas_height / 2, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); +} + +static void avc_buffspec_init(struct encode_wq_s *wq) +{ + u32 canvas_width, canvas_height; + u32 start_addr = wq->mem.buf_start; + u32 mb_w = (wq->pic.encoder_width + 15) >> 4; + u32 mb_h = (wq->pic.encoder_height + 15) >> 4; + u32 mbs = mb_w * mb_h; + + canvas_width = ((wq->pic.encoder_width + 31) >> 5) << 5; + canvas_height = ((wq->pic.encoder_height + 15) >> 4) << 4; + + wq->mem.dct_buff_start_addr = start_addr + + wq->mem.bufspec.dct.buf_start; + wq->mem.dct_buff_end_addr = + wq->mem.dct_buff_start_addr + + wq->mem.bufspec.dct.buf_size - 1; + enc_pr(LOG_INFO, "dct_buff_start_addr is 0x%x, wq:%p.\n", + wq->mem.dct_buff_start_addr, (void *)wq); + + wq->mem.bufspec.dec0_uv.buf_start = + wq->mem.bufspec.dec0_y.buf_start + + canvas_width * canvas_height; + wq->mem.bufspec.dec0_uv.buf_size = canvas_width * canvas_height / 2; + wq->mem.bufspec.dec1_uv.buf_start = + wq->mem.bufspec.dec1_y.buf_start + + canvas_width * canvas_height; + wq->mem.bufspec.dec1_uv.buf_size = canvas_width * canvas_height / 2; + wq->mem.assit_buffer_offset = start_addr + + wq->mem.bufspec.assit.buf_start; + enc_pr(LOG_INFO, "assit_buffer_offset is 0x%x, wq: %p.\n", + wq->mem.assit_buffer_offset, (void *)wq); + /*output stream buffer config*/ + wq->mem.BitstreamStart = start_addr + + wq->mem.bufspec.bitstream.buf_start; + wq->mem.BitstreamEnd = + wq->mem.BitstreamStart + + wq->mem.bufspec.bitstream.buf_size - 1; + enc_pr(LOG_INFO, "BitstreamStart is 0x%x, wq: %p.\n", + wq->mem.BitstreamStart, (void *)wq); + + wq->mem.scaler_buff_start_addr = + wq->mem.buf_start + wq->mem.bufspec.scale_buff.buf_start; + wq->mem.dump_info_ddr_start_addr = + wq->mem.buf_start + wq->mem.bufspec.dump_info.buf_start; + enc_pr(LOG_INFO, + "CBR: dump_info_ddr_start_addr:%x.\n", + wq->mem.dump_info_ddr_start_addr); + enc_pr(LOG_INFO, "CBR: buf_start :%d.\n", + wq->mem.buf_start); + enc_pr(LOG_INFO, "CBR: dump_info.buf_start :%d.\n", + wq->mem.bufspec.dump_info.buf_start); + wq->mem.dump_info_ddr_size = + DUMP_INFO_BYTES_PER_MB * mbs; + wq->mem.dump_info_ddr_size = + (wq->mem.dump_info_ddr_size + PAGE_SIZE - 1) + & ~(PAGE_SIZE - 1); + wq->mem.cbr_info_ddr_start_addr = + wq->mem.buf_start + wq->mem.bufspec.cbr_info.buf_start; + wq->mem.cbr_info_ddr_size = + wq->mem.bufspec.cbr_info.buf_size; + + wq->mem.dblk_buf_canvas = + ((ENC_CANVAS_OFFSET + 2) << 16) | + ((ENC_CANVAS_OFFSET + 1) << 8) | + (ENC_CANVAS_OFFSET); + wq->mem.ref_buf_canvas = + ((ENC_CANVAS_OFFSET + 5) << 16) | + ((ENC_CANVAS_OFFSET + 4) << 8) | + (ENC_CANVAS_OFFSET + 3); +} + +static void avc_init_ie_me_parameter(struct encode_wq_s *wq, u32 quant) +{ + ie_cur_ref_sel = 0; + ie_pippeline_block = 12; + /* currently disable half and sub pixel */ + ie_me_mode = + (ie_pippeline_block & IE_PIPPELINE_BLOCK_MASK) << + IE_PIPPELINE_BLOCK_SHIFT; + + WRITE_HREG(IE_ME_MODE, ie_me_mode); + WRITE_HREG(IE_REF_SEL, ie_cur_ref_sel); + WRITE_HREG(IE_ME_MB_TYPE, ie_me_mb_type); +#ifdef MULTI_SLICE_MC + if (fixed_slice_cfg) + WRITE_HREG(FIXED_SLICE_CFG, fixed_slice_cfg); + else if (wq->pic.rows_per_slice != + (wq->pic.encoder_height + 15) >> 4) { + u32 mb_per_slice = (wq->pic.encoder_height + 15) >> 4; + + mb_per_slice = mb_per_slice * wq->pic.rows_per_slice; + WRITE_HREG(FIXED_SLICE_CFG, mb_per_slice); + } else + WRITE_HREG(FIXED_SLICE_CFG, 0); +#else + WRITE_HREG(FIXED_SLICE_CFG, 0); +#endif +} + +/* for temp */ +#define HCODEC_MFDIN_REGC_MBLP (HCODEC_MFDIN_REGB_AMPC + 0x1) +#define HCODEC_MFDIN_REG0D (HCODEC_MFDIN_REGB_AMPC + 0x2) +#define HCODEC_MFDIN_REG0E (HCODEC_MFDIN_REGB_AMPC + 0x3) +#define HCODEC_MFDIN_REG0F (HCODEC_MFDIN_REGB_AMPC + 0x4) +#define HCODEC_MFDIN_REG10 (HCODEC_MFDIN_REGB_AMPC + 0x5) +#define HCODEC_MFDIN_REG11 (HCODEC_MFDIN_REGB_AMPC + 0x6) +#define HCODEC_MFDIN_REG12 (HCODEC_MFDIN_REGB_AMPC + 0x7) +#define HCODEC_MFDIN_REG13 (HCODEC_MFDIN_REGB_AMPC + 0x8) +#define HCODEC_MFDIN_REG14 (HCODEC_MFDIN_REGB_AMPC + 0x9) +#define HCODEC_MFDIN_REG15 (HCODEC_MFDIN_REGB_AMPC + 0xa) +#define HCODEC_MFDIN_REG16 (HCODEC_MFDIN_REGB_AMPC + 0xb) + +static void mfdin_basic(u32 input, u8 iformat, + u8 oformat, u32 picsize_x, u32 picsize_y, + u8 r2y_en, u8 nr, u8 ifmt_extra) +{ + u8 dsample_en; /* Downsample Enable */ + u8 interp_en; /* Interpolation Enable */ + u8 y_size; /* 0:16 Pixels for y direction pickup; 1:8 pixels */ + u8 r2y_mode; /* RGB2YUV Mode, range(0~3) */ + /* mfdin_reg3_canv[25:24]; + * // bytes per pixel in x direction for index0, 0:half 1:1 2:2 3:3 + */ + u8 canv_idx0_bppx; + /* mfdin_reg3_canv[27:26]; + * // bytes per pixel in x direction for index1-2, 0:half 1:1 2:2 3:3 + */ + u8 canv_idx1_bppx; + /* mfdin_reg3_canv[29:28]; + * // bytes per pixel in y direction for index0, 0:half 1:1 2:2 3:3 + */ + u8 canv_idx0_bppy; + /* mfdin_reg3_canv[31:30]; + * // bytes per pixel in y direction for index1-2, 0:half 1:1 2:2 3:3 + */ + u8 canv_idx1_bppy; + u8 ifmt444, ifmt422, ifmt420, linear_bytes4p; + u8 nr_enable; + u8 cfg_y_snr_en; + u8 cfg_y_tnr_en; + u8 cfg_c_snr_en; + u8 cfg_c_tnr_en; + u32 linear_bytesperline; + s32 reg_offset; + bool linear_enable = false; + bool format_err = false; + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXL) { + if ((iformat == 7) && (ifmt_extra > 2)) + format_err = true; + } else if (iformat == 7) + format_err = true; + + if (format_err) { + enc_pr(LOG_ERROR, + "mfdin format err, iformat:%d, ifmt_extra:%d\n", + iformat, ifmt_extra); + return; + } + if (iformat != 7) + ifmt_extra = 0; + + ifmt444 = ((iformat == 1) || (iformat == 5) || (iformat == 8) || + (iformat == 9) || (iformat == 12)) ? 1 : 0; + if (iformat == 7 && ifmt_extra == 1) + ifmt444 = 1; + ifmt422 = ((iformat == 0) || (iformat == 10)) ? 1 : 0; + if (iformat == 7 && ifmt_extra != 1) + ifmt422 = 1; + ifmt420 = ((iformat == 2) || (iformat == 3) || (iformat == 4) || + (iformat == 11)) ? 1 : 0; + dsample_en = ((ifmt444 && (oformat != 2)) || + (ifmt422 && (oformat == 0))) ? 1 : 0; + interp_en = ((ifmt422 && (oformat == 2)) || + (ifmt420 && (oformat != 0))) ? 1 : 0; + y_size = (oformat != 0) ? 1 : 0; + if (iformat == 12) + y_size = 0; + r2y_mode = (r2y_en == 1) ? 1 : 0; /* Fixed to 1 (TODO) */ + canv_idx0_bppx = (iformat == 1) ? 3 : (iformat == 0) ? 2 : 1; + canv_idx1_bppx = (iformat == 4) ? 0 : 1; + canv_idx0_bppy = 1; + canv_idx1_bppy = (iformat == 5) ? 1 : 0; + + if ((iformat == 8) || (iformat == 9) || (iformat == 12)) + linear_bytes4p = 3; + else if (iformat == 10) + linear_bytes4p = 2; + else if (iformat == 11) + linear_bytes4p = 1; + else + linear_bytes4p = 0; + if (iformat == 12) + linear_bytesperline = picsize_x * 4; + else + linear_bytesperline = picsize_x * linear_bytes4p; + + if (iformat < 8) + linear_enable = false; + else + linear_enable = true; + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) { + reg_offset = -8; + /* nr_mode: 0:Disabled 1:SNR Only 2:TNR Only 3:3DNR */ + nr_enable = (nr) ? 1 : 0; + cfg_y_snr_en = ((nr == 1) || (nr == 3)) ? 1 : 0; + cfg_y_tnr_en = ((nr == 2) || (nr == 3)) ? 1 : 0; + cfg_c_snr_en = cfg_y_snr_en; + /* cfg_c_tnr_en = cfg_y_tnr_en; */ + cfg_c_tnr_en = 0; + + /* NR For Y */ + WRITE_HREG((HCODEC_MFDIN_REG0D + reg_offset), + ((cfg_y_snr_en << 0) | + (y_snr_err_norm << 1) | + (y_snr_gau_bld_core << 2) | + (((y_snr_gau_bld_ofst) & 0xff) << 6) | + (y_snr_gau_bld_rate << 14) | + (y_snr_gau_alp0_min << 20) | + (y_snr_gau_alp0_max << 26))); + WRITE_HREG((HCODEC_MFDIN_REG0E + reg_offset), + ((cfg_y_tnr_en << 0) | + (y_tnr_mc_en << 1) | + (y_tnr_txt_mode << 2) | + (y_tnr_mot_sad_margin << 3) | + (y_tnr_alpha_min << 7) | + (y_tnr_alpha_max << 13) | + (y_tnr_deghost_os << 19))); + WRITE_HREG((HCODEC_MFDIN_REG0F + reg_offset), + ((y_tnr_mot_cortxt_rate << 0) | + (y_tnr_mot_distxt_ofst << 8) | + (y_tnr_mot_distxt_rate << 4) | + (y_tnr_mot_dismot_ofst << 16) | + (y_tnr_mot_frcsad_lock << 24))); + WRITE_HREG((HCODEC_MFDIN_REG10 + reg_offset), + ((y_tnr_mot2alp_frc_gain << 0) | + (y_tnr_mot2alp_nrm_gain << 8) | + (y_tnr_mot2alp_dis_gain << 16) | + (y_tnr_mot2alp_dis_ofst << 24))); + WRITE_HREG((HCODEC_MFDIN_REG11 + reg_offset), + ((y_bld_beta2alp_rate << 0) | + (y_bld_beta_min << 8) | + (y_bld_beta_max << 14))); + + /* NR For C */ + WRITE_HREG((HCODEC_MFDIN_REG12 + reg_offset), + ((cfg_y_snr_en << 0) | + (c_snr_err_norm << 1) | + (c_snr_gau_bld_core << 2) | + (((c_snr_gau_bld_ofst) & 0xff) << 6) | + (c_snr_gau_bld_rate << 14) | + (c_snr_gau_alp0_min << 20) | + (c_snr_gau_alp0_max << 26))); + + WRITE_HREG((HCODEC_MFDIN_REG13 + reg_offset), + ((cfg_c_tnr_en << 0) | + (c_tnr_mc_en << 1) | + (c_tnr_txt_mode << 2) | + (c_tnr_mot_sad_margin << 3) | + (c_tnr_alpha_min << 7) | + (c_tnr_alpha_max << 13) | + (c_tnr_deghost_os << 19))); + WRITE_HREG((HCODEC_MFDIN_REG14 + reg_offset), + ((c_tnr_mot_cortxt_rate << 0) | + (c_tnr_mot_distxt_ofst << 8) | + (c_tnr_mot_distxt_rate << 4) | + (c_tnr_mot_dismot_ofst << 16) | + (c_tnr_mot_frcsad_lock << 24))); + WRITE_HREG((HCODEC_MFDIN_REG15 + reg_offset), + ((c_tnr_mot2alp_frc_gain << 0) | + (c_tnr_mot2alp_nrm_gain << 8) | + (c_tnr_mot2alp_dis_gain << 16) | + (c_tnr_mot2alp_dis_ofst << 24))); + + WRITE_HREG((HCODEC_MFDIN_REG16 + reg_offset), + ((c_bld_beta2alp_rate << 0) | + (c_bld_beta_min << 8) | + (c_bld_beta_max << 14))); + + WRITE_HREG((HCODEC_MFDIN_REG1_CTRL + reg_offset), + (iformat << 0) | (oformat << 4) | + (dsample_en << 6) | (y_size << 8) | + (interp_en << 9) | (r2y_en << 12) | + (r2y_mode << 13) | (ifmt_extra << 16) | + (nr_enable << 19)); + WRITE_HREG((HCODEC_MFDIN_REG8_DMBL + reg_offset), + (picsize_x << 14) | (picsize_y << 0)); + } else { + reg_offset = 0; + WRITE_HREG((HCODEC_MFDIN_REG1_CTRL + reg_offset), + (iformat << 0) | (oformat << 4) | + (dsample_en << 6) | (y_size << 8) | + (interp_en << 9) | (r2y_en << 12) | + (r2y_mode << 13)); + WRITE_HREG((HCODEC_MFDIN_REG8_DMBL + reg_offset), + (picsize_x << 12) | (picsize_y << 0)); + } + + if (linear_enable == false) { + WRITE_HREG((HCODEC_MFDIN_REG3_CANV + reg_offset), + (input & 0xffffff) | + (canv_idx1_bppy << 30) | + (canv_idx0_bppy << 28) | + (canv_idx1_bppx << 26) | + (canv_idx0_bppx << 24)); + WRITE_HREG((HCODEC_MFDIN_REG4_LNR0 + reg_offset), + (0 << 16) | (0 << 0)); + WRITE_HREG((HCODEC_MFDIN_REG5_LNR1 + reg_offset), 0); + } else { + WRITE_HREG((HCODEC_MFDIN_REG3_CANV + reg_offset), + (canv_idx1_bppy << 30) | + (canv_idx0_bppy << 28) | + (canv_idx1_bppx << 26) | + (canv_idx0_bppx << 24)); + WRITE_HREG((HCODEC_MFDIN_REG4_LNR0 + reg_offset), + (linear_bytes4p << 16) | (linear_bytesperline << 0)); + WRITE_HREG((HCODEC_MFDIN_REG5_LNR1 + reg_offset), input); + } + + if (iformat == 12) + WRITE_HREG((HCODEC_MFDIN_REG9_ENDN + reg_offset), + (2 << 0) | (1 << 3) | (0 << 6) | + (3 << 9) | (6 << 12) | (5 << 15) | + (4 << 18) | (7 << 21)); + else + WRITE_HREG((HCODEC_MFDIN_REG9_ENDN + reg_offset), + (7 << 0) | (6 << 3) | (5 << 6) | + (4 << 9) | (3 << 12) | (2 << 15) | + (1 << 18) | (0 << 21)); +} + +#ifdef CONFIG_AMLOGIC_MEDIA_GE2D +static int scale_frame(struct encode_wq_s *wq, + struct encode_request_s *request, + struct config_para_ex_s *ge2d_config, + u32 src_addr, bool canvas) +{ + struct ge2d_context_s *context = encode_manager.context; + int src_top, src_left, src_width, src_height; + struct canvas_s cs0, cs1, cs2, cd; + u32 src_canvas, dst_canvas; + u32 src_canvas_w, dst_canvas_w; + u32 src_h = request->src_h; + u32 dst_w = ((wq->pic.encoder_width + 15) >> 4) << 4; + u32 dst_h = ((wq->pic.encoder_height + 15) >> 4) << 4; + int input_format = GE2D_FORMAT_M24_NV21; + + src_top = request->crop_top; + src_left = request->crop_left; + src_width = request->src_w - src_left - request->crop_right; + src_height = request->src_h - src_top - request->crop_bottom; + if (canvas) { + if ((request->fmt == FMT_NV21) + || (request->fmt == FMT_NV12)) { + src_canvas = src_addr & 0xffff; + input_format = GE2D_FORMAT_M24_NV21; + } else { + src_canvas = src_addr & 0xffffff; + input_format = GE2D_FORMAT_M24_YUV420; + } + } else { + if ((request->fmt == FMT_NV21) + || (request->fmt == FMT_NV12)) { + src_canvas_w = + ((request->src_w + 31) >> 5) << 5; + canvas_config(ENC_CANVAS_OFFSET + 9, + src_addr, + src_canvas_w, src_h, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + canvas_config(ENC_CANVAS_OFFSET + 10, + src_addr + src_canvas_w * src_h, + src_canvas_w, src_h / 2, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + src_canvas = + ((ENC_CANVAS_OFFSET + 10) << 8) + | (ENC_CANVAS_OFFSET + 9); + input_format = GE2D_FORMAT_M24_NV21; + } else { + src_canvas_w = + ((request->src_w + 63) >> 6) << 6; + canvas_config(ENC_CANVAS_OFFSET + 9, + src_addr, + src_canvas_w, src_h, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + canvas_config(ENC_CANVAS_OFFSET + 10, + src_addr + src_canvas_w * src_h, + src_canvas_w / 2, src_h / 2, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + canvas_config(ENC_CANVAS_OFFSET + 11, + src_addr + src_canvas_w * src_h * 5 / 4, + src_canvas_w / 2, src_h / 2, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + src_canvas = + ((ENC_CANVAS_OFFSET + 11) << 16) | + ((ENC_CANVAS_OFFSET + 10) << 8) | + (ENC_CANVAS_OFFSET + 9); + input_format = GE2D_FORMAT_M24_YUV420; + } + } + dst_canvas_w = ((dst_w + 31) >> 5) << 5; + canvas_config(ENC_CANVAS_OFFSET + 6, + wq->mem.scaler_buff_start_addr, + dst_canvas_w, dst_h, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); + canvas_config(ENC_CANVAS_OFFSET + 7, + wq->mem.scaler_buff_start_addr + dst_canvas_w * dst_h, + dst_canvas_w, dst_h / 2, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); + dst_canvas = ((ENC_CANVAS_OFFSET + 7) << 8) | + (ENC_CANVAS_OFFSET + 6); + ge2d_config->alu_const_color = 0; + ge2d_config->bitmask_en = 0; + ge2d_config->src1_gb_alpha = 0; + ge2d_config->dst_xy_swap = 0; + canvas_read(src_canvas & 0xff, &cs0); + canvas_read((src_canvas >> 8) & 0xff, &cs1); + canvas_read((src_canvas >> 16) & 0xff, &cs2); + ge2d_config->src_planes[0].addr = cs0.addr; + ge2d_config->src_planes[0].w = cs0.width; + ge2d_config->src_planes[0].h = cs0.height; + ge2d_config->src_planes[1].addr = cs1.addr; + ge2d_config->src_planes[1].w = cs1.width; + ge2d_config->src_planes[1].h = cs1.height; + ge2d_config->src_planes[2].addr = cs2.addr; + ge2d_config->src_planes[2].w = cs2.width; + ge2d_config->src_planes[2].h = cs2.height; + canvas_read(dst_canvas & 0xff, &cd); + ge2d_config->dst_planes[0].addr = cd.addr; + ge2d_config->dst_planes[0].w = cd.width; + ge2d_config->dst_planes[0].h = cd.height; + ge2d_config->src_key.key_enable = 0; + ge2d_config->src_key.key_mask = 0; + ge2d_config->src_key.key_mode = 0; + ge2d_config->src_para.canvas_index = src_canvas; + ge2d_config->src_para.mem_type = CANVAS_TYPE_INVALID; + ge2d_config->src_para.format = input_format | GE2D_LITTLE_ENDIAN; + ge2d_config->src_para.fill_color_en = 0; + ge2d_config->src_para.fill_mode = 0; + ge2d_config->src_para.x_rev = 0; + ge2d_config->src_para.y_rev = 0; + ge2d_config->src_para.color = 0xffffffff; + ge2d_config->src_para.top = 0; + ge2d_config->src_para.left = 0; + ge2d_config->src_para.width = request->src_w; + ge2d_config->src_para.height = request->src_h; + ge2d_config->src2_para.mem_type = CANVAS_TYPE_INVALID; + ge2d_config->dst_para.canvas_index = dst_canvas; + ge2d_config->dst_para.mem_type = CANVAS_TYPE_INVALID; + ge2d_config->dst_para.format = + GE2D_FORMAT_M24_NV21 | GE2D_LITTLE_ENDIAN; + ge2d_config->dst_para.fill_color_en = 0; + ge2d_config->dst_para.fill_mode = 0; + ge2d_config->dst_para.x_rev = 0; + ge2d_config->dst_para.y_rev = 0; + ge2d_config->dst_para.color = 0; + ge2d_config->dst_para.top = 0; + ge2d_config->dst_para.left = 0; + ge2d_config->dst_para.width = dst_w; + ge2d_config->dst_para.height = dst_h; + ge2d_config->dst_para.x_rev = 0; + ge2d_config->dst_para.y_rev = 0; + if (ge2d_context_config_ex(context, ge2d_config) < 0) { + pr_err("++ge2d configing error.\n"); + return -1; + } + stretchblt_noalpha(context, src_left, src_top, src_width, src_height, + 0, 0, wq->pic.encoder_width, wq->pic.encoder_height); + return dst_canvas_w*dst_h * 3 / 2; +} +#endif + +static s32 set_input_format(struct encode_wq_s *wq, + struct encode_request_s *request) +{ + s32 ret = 0; + u8 iformat = MAX_FRAME_FMT, oformat = MAX_FRAME_FMT, r2y_en = 0; + u32 picsize_x, picsize_y, src_addr; + u32 canvas_w = 0; + u32 input = request->src; + u8 ifmt_extra = 0; + + if ((request->fmt == FMT_RGB565) || (request->fmt >= MAX_FRAME_FMT)) + return -1; + + picsize_x = ((wq->pic.encoder_width + 15) >> 4) << 4; + picsize_y = ((wq->pic.encoder_height + 15) >> 4) << 4; + oformat = 0; + if ((request->type == LOCAL_BUFF) + || (request->type == PHYSICAL_BUFF)) { + if ((request->type == LOCAL_BUFF) && + (request->flush_flag & AMVENC_FLUSH_FLAG_INPUT)) + dma_flush(wq->mem.dct_buff_start_addr, + request->framesize); + if (request->type == LOCAL_BUFF) { + input = wq->mem.dct_buff_start_addr; + src_addr = + wq->mem.dct_buff_start_addr; + } else { + src_addr = input; + picsize_y = wq->pic.encoder_height; + } + if (request->scale_enable) { +#ifdef CONFIG_AMLOGIC_MEDIA_GE2D + struct config_para_ex_s ge2d_config; + + memset(&ge2d_config, 0, + sizeof(struct config_para_ex_s)); + scale_frame( + wq, request, + &ge2d_config, + src_addr, + false); + iformat = 2; + r2y_en = 0; + input = ((ENC_CANVAS_OFFSET + 7) << 8) | + (ENC_CANVAS_OFFSET + 6); + ret = 0; + goto MFDIN; +#else + enc_pr(LOG_ERROR, + "Warning: need enable ge2d for scale frame!\n"); + return -1; +#endif + } + if ((request->fmt <= FMT_YUV444_PLANE) || + (request->fmt >= FMT_YUV422_12BIT)) + r2y_en = 0; + else + r2y_en = 1; + + if (request->fmt >= FMT_YUV422_12BIT) { + iformat = 7; + ifmt_extra = request->fmt - FMT_YUV422_12BIT; + if (request->fmt == FMT_YUV422_12BIT) + canvas_w = picsize_x * 24 / 8; + else if (request->fmt == FMT_YUV444_10BIT) + canvas_w = picsize_x * 32 / 8; + else + canvas_w = (picsize_x * 20 + 7) / 8; + canvas_w = ((canvas_w + 31) >> 5) << 5; + canvas_config(ENC_CANVAS_OFFSET + 6, + input, + canvas_w, picsize_y, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + input = ENC_CANVAS_OFFSET + 6; + input = input & 0xff; + } else if (request->fmt == FMT_YUV422_SINGLE) + iformat = 10; + else if ((request->fmt == FMT_YUV444_SINGLE) + || (request->fmt == FMT_RGB888)) { + iformat = 1; + if (request->fmt == FMT_RGB888) + r2y_en = 1; + canvas_w = picsize_x * 3; + canvas_w = ((canvas_w + 31) >> 5) << 5; + canvas_config(ENC_CANVAS_OFFSET + 6, + input, + canvas_w, picsize_y, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + input = ENC_CANVAS_OFFSET + 6; + } else if ((request->fmt == FMT_NV21) + || (request->fmt == FMT_NV12)) { + canvas_w = ((wq->pic.encoder_width + 31) >> 5) << 5; + iformat = (request->fmt == FMT_NV21) ? 2 : 3; + canvas_config(ENC_CANVAS_OFFSET + 6, + input, + canvas_w, picsize_y, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + canvas_config(ENC_CANVAS_OFFSET + 7, + input + canvas_w * picsize_y, + canvas_w, picsize_y / 2, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + input = ((ENC_CANVAS_OFFSET + 7) << 8) | + (ENC_CANVAS_OFFSET + 6); + } else if (request->fmt == FMT_YUV420) { + iformat = 4; + canvas_w = ((wq->pic.encoder_width + 63) >> 6) << 6; + canvas_config(ENC_CANVAS_OFFSET + 6, + input, + canvas_w, picsize_y, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + canvas_config(ENC_CANVAS_OFFSET + 7, + input + canvas_w * picsize_y, + canvas_w / 2, picsize_y / 2, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + canvas_config(ENC_CANVAS_OFFSET + 8, + input + canvas_w * picsize_y * 5 / 4, + canvas_w / 2, picsize_y / 2, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + input = ((ENC_CANVAS_OFFSET + 8) << 16) | + ((ENC_CANVAS_OFFSET + 7) << 8) | + (ENC_CANVAS_OFFSET + 6); + } else if ((request->fmt == FMT_YUV444_PLANE) + || (request->fmt == FMT_RGB888_PLANE)) { + if (request->fmt == FMT_RGB888_PLANE) + r2y_en = 1; + iformat = 5; + canvas_w = ((wq->pic.encoder_width + 31) >> 5) << 5; + canvas_config(ENC_CANVAS_OFFSET + 6, + input, + canvas_w, picsize_y, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + canvas_config(ENC_CANVAS_OFFSET + 7, + input + canvas_w * picsize_y, + canvas_w, picsize_y, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + canvas_config(ENC_CANVAS_OFFSET + 8, + input + canvas_w * picsize_y * 2, + canvas_w, picsize_y, + CANVAS_ADDR_NOWRAP, + CANVAS_BLKMODE_LINEAR); + input = ((ENC_CANVAS_OFFSET + 8) << 16) | + ((ENC_CANVAS_OFFSET + 7) << 8) | + (ENC_CANVAS_OFFSET + 6); + } else if (request->fmt == FMT_RGBA8888) { + r2y_en = 1; + iformat = 12; + } + ret = 0; + } else if (request->type == CANVAS_BUFF) { + r2y_en = 0; + if (request->scale_enable) { +#ifdef CONFIG_AMLOGIC_MEDIA_GE2D + struct config_para_ex_s ge2d_config; + memset(&ge2d_config, 0, + sizeof(struct config_para_ex_s)); + scale_frame( + wq, request, + &ge2d_config, + input, true); + iformat = 2; + r2y_en = 0; + input = ((ENC_CANVAS_OFFSET + 7) << 8) | + (ENC_CANVAS_OFFSET + 6); + ret = 0; + goto MFDIN; +#else + enc_pr(LOG_ERROR, + "Warning: need enable ge2d for scale frame!\n"); + return -1; +#endif + } + if (request->fmt == FMT_YUV422_SINGLE) { + iformat = 0; + input = input & 0xff; + } else if (request->fmt == FMT_YUV444_SINGLE) { + iformat = 1; + input = input & 0xff; + } else if ((request->fmt == FMT_NV21) + || (request->fmt == FMT_NV12)) { + iformat = (request->fmt == FMT_NV21) ? 2 : 3; + input = input & 0xffff; + } else if (request->fmt == FMT_YUV420) { + iformat = 4; + input = input & 0xffffff; + } else if ((request->fmt == FMT_YUV444_PLANE) + || (request->fmt == FMT_RGB888_PLANE)) { + if (request->fmt == FMT_RGB888_PLANE) + r2y_en = 1; + iformat = 5; + input = input & 0xffffff; + } else if ((request->fmt == FMT_YUV422_12BIT) + || (request->fmt == FMT_YUV444_10BIT) + || (request->fmt == FMT_YUV422_10BIT)) { + iformat = 7; + ifmt_extra = request->fmt - FMT_YUV422_12BIT; + input = input & 0xff; + } else + ret = -1; + } +#ifdef CONFIG_AMLOGIC_MEDIA_GE2D +MFDIN: +#endif + if (ret == 0) + mfdin_basic(input, iformat, oformat, + picsize_x, picsize_y, r2y_en, + request->nr_mode, ifmt_extra); + return ret; +} + +#ifdef H264_ENC_CBR +static void ConvertTable2Risc(void *table, u32 len) +{ + u32 i, j; + u16 temp; + u16 *tbl = (u16 *)table; + + if ((len < 8) || (len % 8) || (!table)) { + enc_pr(LOG_ERROR, "ConvertTable2Risc tbl %p, len %d error\n", + table, len); + return; + } + for (i = 0; i < len / 8; i++) { + j = i << 2; + temp = tbl[j]; + tbl[j] = tbl[j + 3]; + tbl[j + 3] = temp; + + temp = tbl[j + 1]; + tbl[j + 1] = tbl[j + 2]; + tbl[j + 2] = temp; + } + +} +#endif + +static void avc_prot_init(struct encode_wq_s *wq, + struct encode_request_s *request, u32 quant, bool IDR) +{ + u32 data32; + u32 pic_width, pic_height; + u32 pic_mb_nr; + u32 pic_mbx, pic_mby; + u32 i_pic_qp, p_pic_qp; + u32 i_pic_qp_c, p_pic_qp_c; + u32 pic_width_in_mb; + u32 slice_qp; + + pic_width = wq->pic.encoder_width; + pic_height = wq->pic.encoder_height; + pic_mb_nr = 0; + pic_mbx = 0; + pic_mby = 0; + i_pic_qp = quant; + p_pic_qp = quant; + + pic_width_in_mb = (pic_width + 15) / 16; + WRITE_HREG(HCODEC_HDEC_MC_OMEM_AUTO, + (1 << 31) | /* use_omem_mb_xy */ + ((pic_width_in_mb - 1) << 16)); /* omem_max_mb_x */ + + WRITE_HREG(HCODEC_VLC_ADV_CONFIG, + /* early_mix_mc_hcmd -- will enable in P Picture */ + (0 << 10) | + (1 << 9) | /* update_top_left_mix */ + (1 << 8) | /* p_top_left_mix */ + /* mv_cal_mixed_type -- will enable in P Picture */ + (0 << 7) | + /* mc_hcmd_mixed_type -- will enable in P Picture */ + (0 << 6) | + (1 << 5) | /* use_separate_int_control */ + (1 << 4) | /* hcmd_intra_use_q_info */ + (1 << 3) | /* hcmd_left_use_prev_info */ + (1 << 2) | /* hcmd_use_q_info */ + (1 << 1) | /* use_q_delta_quant */ + /* detect_I16_from_I4 use qdct detected mb_type */ + (0 << 0)); + + WRITE_HREG(HCODEC_QDCT_ADV_CONFIG, + (1 << 29) | /* mb_info_latch_no_I16_pred_mode */ + (1 << 28) | /* ie_dma_mbxy_use_i_pred */ + (1 << 27) | /* ie_dma_read_write_use_ip_idx */ + (1 << 26) | /* ie_start_use_top_dma_count */ + (1 << 25) | /* i_pred_top_dma_rd_mbbot */ + (1 << 24) | /* i_pred_top_dma_wr_disable */ + /* i_pred_mix -- will enable in P Picture */ + (0 << 23) | + (1 << 22) | /* me_ab_rd_when_intra_in_p */ + (1 << 21) | /* force_mb_skip_run_when_intra */ + /* mc_out_mixed_type -- will enable in P Picture */ + (0 << 20) | + (1 << 19) | /* ie_start_when_quant_not_full */ + (1 << 18) | /* mb_info_state_mix */ + /* mb_type_use_mix_result -- will enable in P Picture */ + (0 << 17) | + /* me_cb_ie_read_enable -- will enable in P Picture */ + (0 << 16) | + /* ie_cur_data_from_me -- will enable in P Picture */ + (0 << 15) | + (1 << 14) | /* rem_per_use_table */ + (0 << 13) | /* q_latch_int_enable */ + (1 << 12) | /* q_use_table */ + (0 << 11) | /* q_start_wait */ + (1 << 10) | /* LUMA_16_LEFT_use_cur */ + (1 << 9) | /* DC_16_LEFT_SUM_use_cur */ + (1 << 8) | /* c_ref_ie_sel_cur */ + (0 << 7) | /* c_ipred_perfect_mode */ + (1 << 6) | /* ref_ie_ul_sel */ + (1 << 5) | /* mb_type_use_ie_result */ + (1 << 4) | /* detect_I16_from_I4 */ + (1 << 3) | /* ie_not_wait_ref_busy */ + (1 << 2) | /* ie_I16_enable */ + (3 << 0)); /* ie_done_sel // fastest when waiting */ + + if (request != NULL) { + WRITE_HREG(HCODEC_IE_WEIGHT, + (request->i16_weight << 16) | + (request->i4_weight << 0)); + WRITE_HREG(HCODEC_ME_WEIGHT, + (request->me_weight << 0)); + WRITE_HREG(HCODEC_SAD_CONTROL_0, + /* ie_sad_offset_I16 */ + (request->i16_weight << 16) | + /* ie_sad_offset_I4 */ + (request->i4_weight << 0)); + WRITE_HREG(HCODEC_SAD_CONTROL_1, + /* ie_sad_shift_I16 */ + (IE_SAD_SHIFT_I16 << 24) | + /* ie_sad_shift_I4 */ + (IE_SAD_SHIFT_I4 << 20) | + /* me_sad_shift_INTER */ + (ME_SAD_SHIFT_INTER << 16) | + /* me_sad_offset_INTER */ + (request->me_weight << 0)); + wq->me_weight = request->me_weight; + wq->i4_weight = request->i4_weight; + wq->i16_weight = request->i16_weight; + } else { + WRITE_HREG(HCODEC_IE_WEIGHT, + (I16MB_WEIGHT_OFFSET << 16) | + (I4MB_WEIGHT_OFFSET << 0)); + WRITE_HREG(HCODEC_ME_WEIGHT, + (ME_WEIGHT_OFFSET << 0)); + WRITE_HREG(HCODEC_SAD_CONTROL_0, + /* ie_sad_offset_I16 */ + (I16MB_WEIGHT_OFFSET << 16) | + /* ie_sad_offset_I4 */ + (I4MB_WEIGHT_OFFSET << 0)); + WRITE_HREG(HCODEC_SAD_CONTROL_1, + /* ie_sad_shift_I16 */ + (IE_SAD_SHIFT_I16 << 24) | + /* ie_sad_shift_I4 */ + (IE_SAD_SHIFT_I4 << 20) | + /* me_sad_shift_INTER */ + (ME_SAD_SHIFT_INTER << 16) | + /* me_sad_offset_INTER */ + (ME_WEIGHT_OFFSET << 0)); + } + + WRITE_HREG(HCODEC_ADV_MV_CTL0, + (ADV_MV_LARGE_16x8 << 31) | + (ADV_MV_LARGE_8x16 << 30) | + (ADV_MV_8x8_WEIGHT << 16) | /* adv_mv_8x8_weight */ + /* adv_mv_4x4x4_weight should be set bigger */ + (ADV_MV_4x4x4_WEIGHT << 0)); + WRITE_HREG(HCODEC_ADV_MV_CTL1, + /* adv_mv_16x16_weight */ + (ADV_MV_16x16_WEIGHT << 16) | + (ADV_MV_LARGE_16x16 << 15) | + (ADV_MV_16_8_WEIGHT << 0)); /* adv_mv_16_8_weight */ + + hcodec_prog_qtbl(wq); + if (IDR) { + i_pic_qp = + wq->quant_tbl_i4[0] & 0xff; + i_pic_qp += + wq->quant_tbl_i16[0] & 0xff; + i_pic_qp /= 2; + p_pic_qp = i_pic_qp; + } else { + i_pic_qp = + wq->quant_tbl_i4[0] & 0xff; + i_pic_qp += + wq->quant_tbl_i16[0] & 0xff; + p_pic_qp = wq->quant_tbl_me[0] & 0xff; + slice_qp = (i_pic_qp + p_pic_qp) / 3; + i_pic_qp = slice_qp; + p_pic_qp = i_pic_qp; + } +#ifdef H264_ENC_CBR + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { + data32 = READ_HREG(HCODEC_SAD_CONTROL_1); + data32 = data32 & 0xffff; /* remove sad shift */ + WRITE_HREG(HCODEC_SAD_CONTROL_1, data32); + WRITE_HREG(H264_ENC_CBR_TABLE_ADDR, + wq->mem.cbr_info_ddr_start_addr); + WRITE_HREG(H264_ENC_CBR_MB_SIZE_ADDR, + wq->mem.cbr_info_ddr_start_addr + + CBR_TABLE_SIZE); + WRITE_HREG(H264_ENC_CBR_CTL, + (wq->cbr_info.start_tbl_id << 28) | + (wq->cbr_info.short_shift << 24) | + (wq->cbr_info.long_mb_num << 16) | + (wq->cbr_info.long_th << 0)); + WRITE_HREG(H264_ENC_CBR_REGION_SIZE, + (wq->cbr_info.block_w << 16) | + (wq->cbr_info.block_h << 0)); + } +#endif + + WRITE_HREG(HCODEC_QDCT_VLC_QUANT_CTL_0, + (0 << 19) | /* vlc_delta_quant_1 */ + (i_pic_qp << 13) | /* vlc_quant_1 */ + (0 << 6) | /* vlc_delta_quant_0 */ + (i_pic_qp << 0)); /* vlc_quant_0 */ + WRITE_HREG(HCODEC_QDCT_VLC_QUANT_CTL_1, + (14 << 6) | /* vlc_max_delta_q_neg */ + (13 << 0)); /* vlc_max_delta_q_pos */ + WRITE_HREG(HCODEC_VLC_PIC_SIZE, + pic_width | (pic_height << 16)); + WRITE_HREG(HCODEC_VLC_PIC_POSITION, + (pic_mb_nr << 16) | + (pic_mby << 8) | + (pic_mbx << 0)); + + /* synopsys parallel_case full_case */ + switch (i_pic_qp) { + case 0: + i_pic_qp_c = 0; + break; + case 1: + i_pic_qp_c = 1; + break; + case 2: + i_pic_qp_c = 2; + break; + case 3: + i_pic_qp_c = 3; + break; + case 4: + i_pic_qp_c = 4; + break; + case 5: + i_pic_qp_c = 5; + break; + case 6: + i_pic_qp_c = 6; + break; + case 7: + i_pic_qp_c = 7; + break; + case 8: + i_pic_qp_c = 8; + break; + case 9: + i_pic_qp_c = 9; + break; + case 10: + i_pic_qp_c = 10; + break; + case 11: + i_pic_qp_c = 11; + break; + case 12: + i_pic_qp_c = 12; + break; + case 13: + i_pic_qp_c = 13; + break; + case 14: + i_pic_qp_c = 14; + break; + case 15: + i_pic_qp_c = 15; + break; + case 16: + i_pic_qp_c = 16; + break; + case 17: + i_pic_qp_c = 17; + break; + case 18: + i_pic_qp_c = 18; + break; + case 19: + i_pic_qp_c = 19; + break; + case 20: + i_pic_qp_c = 20; + break; + case 21: + i_pic_qp_c = 21; + break; + case 22: + i_pic_qp_c = 22; + break; + case 23: + i_pic_qp_c = 23; + break; + case 24: + i_pic_qp_c = 24; + break; + case 25: + i_pic_qp_c = 25; + break; + case 26: + i_pic_qp_c = 26; + break; + case 27: + i_pic_qp_c = 27; + break; + case 28: + i_pic_qp_c = 28; + break; + case 29: + i_pic_qp_c = 29; + break; + case 30: + i_pic_qp_c = 29; + break; + case 31: + i_pic_qp_c = 30; + break; + case 32: + i_pic_qp_c = 31; + break; + case 33: + i_pic_qp_c = 32; + break; + case 34: + i_pic_qp_c = 32; + break; + case 35: + i_pic_qp_c = 33; + break; + case 36: + i_pic_qp_c = 34; + break; + case 37: + i_pic_qp_c = 34; + break; + case 38: + i_pic_qp_c = 35; + break; + case 39: + i_pic_qp_c = 35; + break; + case 40: + i_pic_qp_c = 36; + break; + case 41: + i_pic_qp_c = 36; + break; + case 42: + i_pic_qp_c = 37; + break; + case 43: + i_pic_qp_c = 37; + break; + case 44: + i_pic_qp_c = 37; + break; + case 45: + i_pic_qp_c = 38; + break; + case 46: + i_pic_qp_c = 38; + break; + case 47: + i_pic_qp_c = 38; + break; + case 48: + i_pic_qp_c = 39; + break; + case 49: + i_pic_qp_c = 39; + break; + case 50: + i_pic_qp_c = 39; + break; + default: + i_pic_qp_c = 39; + break; + } + + /* synopsys parallel_case full_case */ + switch (p_pic_qp) { + case 0: + p_pic_qp_c = 0; + break; + case 1: + p_pic_qp_c = 1; + break; + case 2: + p_pic_qp_c = 2; + break; + case 3: + p_pic_qp_c = 3; + break; + case 4: + p_pic_qp_c = 4; + break; + case 5: + p_pic_qp_c = 5; + break; + case 6: + p_pic_qp_c = 6; + break; + case 7: + p_pic_qp_c = 7; + break; + case 8: + p_pic_qp_c = 8; + break; + case 9: + p_pic_qp_c = 9; + break; + case 10: + p_pic_qp_c = 10; + break; + case 11: + p_pic_qp_c = 11; + break; + case 12: + p_pic_qp_c = 12; + break; + case 13: + p_pic_qp_c = 13; + break; + case 14: + p_pic_qp_c = 14; + break; + case 15: + p_pic_qp_c = 15; + break; + case 16: + p_pic_qp_c = 16; + break; + case 17: + p_pic_qp_c = 17; + break; + case 18: + p_pic_qp_c = 18; + break; + case 19: + p_pic_qp_c = 19; + break; + case 20: + p_pic_qp_c = 20; + break; + case 21: + p_pic_qp_c = 21; + break; + case 22: + p_pic_qp_c = 22; + break; + case 23: + p_pic_qp_c = 23; + break; + case 24: + p_pic_qp_c = 24; + break; + case 25: + p_pic_qp_c = 25; + break; + case 26: + p_pic_qp_c = 26; + break; + case 27: + p_pic_qp_c = 27; + break; + case 28: + p_pic_qp_c = 28; + break; + case 29: + p_pic_qp_c = 29; + break; + case 30: + p_pic_qp_c = 29; + break; + case 31: + p_pic_qp_c = 30; + break; + case 32: + p_pic_qp_c = 31; + break; + case 33: + p_pic_qp_c = 32; + break; + case 34: + p_pic_qp_c = 32; + break; + case 35: + p_pic_qp_c = 33; + break; + case 36: + p_pic_qp_c = 34; + break; + case 37: + p_pic_qp_c = 34; + break; + case 38: + p_pic_qp_c = 35; + break; + case 39: + p_pic_qp_c = 35; + break; + case 40: + p_pic_qp_c = 36; + break; + case 41: + p_pic_qp_c = 36; + break; + case 42: + p_pic_qp_c = 37; + break; + case 43: + p_pic_qp_c = 37; + break; + case 44: + p_pic_qp_c = 37; + break; + case 45: + p_pic_qp_c = 38; + break; + case 46: + p_pic_qp_c = 38; + break; + case 47: + p_pic_qp_c = 38; + break; + case 48: + p_pic_qp_c = 39; + break; + case 49: + p_pic_qp_c = 39; + break; + case 50: + p_pic_qp_c = 39; + break; + default: + p_pic_qp_c = 39; + break; + } + WRITE_HREG(HCODEC_QDCT_Q_QUANT_I, + (i_pic_qp_c << 22) | + (i_pic_qp << 16) | + ((i_pic_qp_c % 6) << 12) | + ((i_pic_qp_c / 6) << 8) | + ((i_pic_qp % 6) << 4) | + ((i_pic_qp / 6) << 0)); + + WRITE_HREG(HCODEC_QDCT_Q_QUANT_P, + (p_pic_qp_c << 22) | + (p_pic_qp << 16) | + ((p_pic_qp_c % 6) << 12) | + ((p_pic_qp_c / 6) << 8) | + ((p_pic_qp % 6) << 4) | + ((p_pic_qp / 6) << 0)); + +#ifdef ENABLE_IGNORE_FUNCTION + WRITE_HREG(HCODEC_IGNORE_CONFIG, + (1 << 31) | /* ignore_lac_coeff_en */ + (1 << 26) | /* ignore_lac_coeff_else (<1) */ + (1 << 21) | /* ignore_lac_coeff_2 (<1) */ + (2 << 16) | /* ignore_lac_coeff_1 (<2) */ + (1 << 15) | /* ignore_cac_coeff_en */ + (1 << 10) | /* ignore_cac_coeff_else (<1) */ + (1 << 5) | /* ignore_cac_coeff_2 (<1) */ + (3 << 0)); /* ignore_cac_coeff_1 (<2) */ + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) + WRITE_HREG(HCODEC_IGNORE_CONFIG_2, + (1 << 31) | /* ignore_t_lac_coeff_en */ + (1 << 26) | /* ignore_t_lac_coeff_else (<1) */ + (2 << 21) | /* ignore_t_lac_coeff_2 (<2) */ + (6 << 16) | /* ignore_t_lac_coeff_1 (<6) */ + (1<<15) | /* ignore_cdc_coeff_en */ + (0<<14) | /* ignore_t_lac_coeff_else_le_3 */ + (1<<13) | /* ignore_t_lac_coeff_else_le_4 */ + (1<<12) | /* ignore_cdc_only_when_empty_cac_inter */ + (1<<11) | /* ignore_cdc_only_when_one_empty_inter */ + /* ignore_cdc_range_max_inter 0-0, 1-1, 2-2, 3-3 */ + (2<<9) | + /* ignore_cdc_abs_max_inter 0-1, 1-2, 2-3, 3-4 */ + (0<<7) | + /* ignore_cdc_only_when_empty_cac_intra */ + (1<<5) | + /* ignore_cdc_only_when_one_empty_intra */ + (1<<4) | + /* ignore_cdc_range_max_intra 0-0, 1-1, 2-2, 3-3 */ + (1<<2) | + /* ignore_cdc_abs_max_intra 0-1, 1-2, 2-3, 3-4 */ + (0<<0)); + else + WRITE_HREG(HCODEC_IGNORE_CONFIG_2, + (1 << 31) | /* ignore_t_lac_coeff_en */ + (1 << 26) | /* ignore_t_lac_coeff_else (<1) */ + (1 << 21) | /* ignore_t_lac_coeff_2 (<1) */ + (5 << 16) | /* ignore_t_lac_coeff_1 (<5) */ + (0 << 0)); +#else + WRITE_HREG(HCODEC_IGNORE_CONFIG, 0); + WRITE_HREG(HCODEC_IGNORE_CONFIG_2, 0); +#endif + + WRITE_HREG(HCODEC_QDCT_MB_CONTROL, + (1 << 9) | /* mb_info_soft_reset */ + (1 << 0)); /* mb read buffer soft reset */ + + WRITE_HREG(HCODEC_QDCT_MB_CONTROL, + (1 << 28) | /* ignore_t_p8x8 */ + (0 << 27) | /* zero_mc_out_null_non_skipped_mb */ + (0 << 26) | /* no_mc_out_null_non_skipped_mb */ + (0 << 25) | /* mc_out_even_skipped_mb */ + (0 << 24) | /* mc_out_wait_cbp_ready */ + (0 << 23) | /* mc_out_wait_mb_type_ready */ + (1 << 29) | /* ie_start_int_enable */ + (1 << 19) | /* i_pred_enable */ + (1 << 20) | /* ie_sub_enable */ + (1 << 18) | /* iq_enable */ + (1 << 17) | /* idct_enable */ + (1 << 14) | /* mb_pause_enable */ + (1 << 13) | /* q_enable */ + (1 << 12) | /* dct_enable */ + (1 << 10) | /* mb_info_en */ + (0 << 3) | /* endian */ + (0 << 1) | /* mb_read_en */ + (0 << 0)); /* soft reset */ + + WRITE_HREG(HCODEC_SAD_CONTROL, + (0 << 3) | /* ie_result_buff_enable */ + (1 << 2) | /* ie_result_buff_soft_reset */ + (0 << 1) | /* sad_enable */ + (1 << 0)); /* sad soft reset */ + WRITE_HREG(HCODEC_IE_RESULT_BUFFER, 0); + + WRITE_HREG(HCODEC_SAD_CONTROL, + (1 << 3) | /* ie_result_buff_enable */ + (0 << 2) | /* ie_result_buff_soft_reset */ + (1 << 1) | /* sad_enable */ + (0 << 0)); /* sad soft reset */ + + WRITE_HREG(HCODEC_IE_CONTROL, + (1 << 30) | /* active_ul_block */ + (0 << 1) | /* ie_enable */ + (1 << 0)); /* ie soft reset */ + + WRITE_HREG(HCODEC_IE_CONTROL, + (1 << 30) | /* active_ul_block */ + (0 << 1) | /* ie_enable */ + (0 << 0)); /* ie soft reset */ + + WRITE_HREG(HCODEC_ME_SKIP_LINE, + (8 << 24) | /* step_3_skip_line */ + (8 << 18) | /* step_2_skip_line */ + (2 << 12) | /* step_1_skip_line */ + (0 << 6) | /* step_0_skip_line */ + (0 << 0)); + + WRITE_HREG(HCODEC_ME_MV_MERGE_CTL, me_mv_merge_ctl); + WRITE_HREG(HCODEC_ME_STEP0_CLOSE_MV, me_step0_close_mv); + WRITE_HREG(HCODEC_ME_SAD_ENOUGH_01, me_sad_enough_01); + WRITE_HREG(HCODEC_ME_SAD_ENOUGH_23, me_sad_enough_23); + WRITE_HREG(HCODEC_ME_F_SKIP_SAD, me_f_skip_sad); + WRITE_HREG(HCODEC_ME_F_SKIP_WEIGHT, me_f_skip_weight); + WRITE_HREG(HCODEC_ME_MV_WEIGHT_01, me_mv_weight_01); + WRITE_HREG(HCODEC_ME_MV_WEIGHT_23, me_mv_weight_23); + WRITE_HREG(HCODEC_ME_SAD_RANGE_INC, me_sad_range_inc); + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXL) { + WRITE_HREG(HCODEC_V5_SIMPLE_MB_CTL, 0); + WRITE_HREG(HCODEC_V5_SIMPLE_MB_CTL, + (v5_use_small_diff_cnt << 7) | + (v5_simple_mb_inter_all_en << 6) | + (v5_simple_mb_inter_8x8_en << 5) | + (v5_simple_mb_inter_16_8_en << 4) | + (v5_simple_mb_inter_16x16_en << 3) | + (v5_simple_mb_intra_en << 2) | + (v5_simple_mb_C_en << 1) | + (v5_simple_mb_Y_en << 0)); + WRITE_HREG(HCODEC_V5_MB_DIFF_SUM, 0); + WRITE_HREG(HCODEC_V5_SMALL_DIFF_CNT, + (v5_small_diff_C<<16) | + (v5_small_diff_Y<<0)); + WRITE_HREG(HCODEC_V5_SIMPLE_MB_DQUANT, + v5_simple_dq_setting); + WRITE_HREG(HCODEC_V5_SIMPLE_MB_ME_WEIGHT, + v5_simple_me_weight_setting); + /* txlx can remove it */ + WRITE_HREG(HCODEC_QDCT_CONFIG, 1 << 0); + } + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) { + WRITE_HREG(HCODEC_V4_FORCE_SKIP_CFG, + (i_pic_qp << 26) | /* v4_force_q_r_intra */ + (i_pic_qp << 20) | /* v4_force_q_r_inter */ + (0 << 19) | /* v4_force_q_y_enable */ + (5 << 16) | /* v4_force_qr_y */ + (6 << 12) | /* v4_force_qp_y */ + (0 << 0)); /* v4_force_skip_sad */ + + /* V3 Force skip */ + WRITE_HREG(HCODEC_V3_SKIP_CONTROL, + (1 << 31) | /* v3_skip_enable */ + (0 << 30) | /* v3_step_1_weight_enable */ + (1 << 28) | /* v3_mv_sad_weight_enable */ + (1 << 27) | /* v3_ipred_type_enable */ + (V3_FORCE_SKIP_SAD_1 << 12) | + (V3_FORCE_SKIP_SAD_0 << 0)); + WRITE_HREG(HCODEC_V3_SKIP_WEIGHT, + (V3_SKIP_WEIGHT_1 << 16) | + (V3_SKIP_WEIGHT_0 << 0)); + WRITE_HREG(HCODEC_V3_L1_SKIP_MAX_SAD, + (V3_LEVEL_1_F_SKIP_MAX_SAD << 16) | + (V3_LEVEL_1_SKIP_MAX_SAD << 0)); + WRITE_HREG(HCODEC_V3_L2_SKIP_WEIGHT, + (V3_FORCE_SKIP_SAD_2 << 16) | + (V3_SKIP_WEIGHT_2 << 0)); + if (request != NULL) { + unsigned int off1, off2; + + off1 = V3_IE_F_ZERO_SAD_I4 - I4MB_WEIGHT_OFFSET; + off2 = V3_IE_F_ZERO_SAD_I16 + - I16MB_WEIGHT_OFFSET; + WRITE_HREG(HCODEC_V3_F_ZERO_CTL_0, + ((request->i16_weight + off2) << 16) | + ((request->i4_weight + off1) << 0)); + off1 = V3_ME_F_ZERO_SAD - ME_WEIGHT_OFFSET; + WRITE_HREG(HCODEC_V3_F_ZERO_CTL_1, + (0 << 25) | + /* v3_no_ver_when_top_zero_en */ + (0 << 24) | + /* v3_no_hor_when_left_zero_en */ + (3 << 16) | /* type_hor break */ + ((request->me_weight + off1) << 0)); + } else { + WRITE_HREG(HCODEC_V3_F_ZERO_CTL_0, + (V3_IE_F_ZERO_SAD_I16 << 16) | + (V3_IE_F_ZERO_SAD_I4 << 0)); + WRITE_HREG(HCODEC_V3_F_ZERO_CTL_1, + (0 << 25) | + /* v3_no_ver_when_top_zero_en */ + (0 << 24) | + /* v3_no_hor_when_left_zero_en */ + (3 << 16) | /* type_hor break */ + (V3_ME_F_ZERO_SAD << 0)); + } + } else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { + /* V3 Force skip */ + WRITE_HREG(HCODEC_V3_SKIP_CONTROL, + (1 << 31) | /* v3_skip_enable */ + (0 << 30) | /* v3_step_1_weight_enable */ + (1 << 28) | /* v3_mv_sad_weight_enable */ + (1 << 27) | /* v3_ipred_type_enable */ + (0 << 12) | /* V3_FORCE_SKIP_SAD_1 */ + (0 << 0)); /* V3_FORCE_SKIP_SAD_0 */ + WRITE_HREG(HCODEC_V3_SKIP_WEIGHT, + (V3_SKIP_WEIGHT_1 << 16) | + (V3_SKIP_WEIGHT_0 << 0)); + WRITE_HREG(HCODEC_V3_L1_SKIP_MAX_SAD, + (V3_LEVEL_1_F_SKIP_MAX_SAD << 16) | + (V3_LEVEL_1_SKIP_MAX_SAD << 0)); + WRITE_HREG(HCODEC_V3_L2_SKIP_WEIGHT, + (0 << 16) | /* V3_FORCE_SKIP_SAD_2 */ + (V3_SKIP_WEIGHT_2 << 0)); + WRITE_HREG(HCODEC_V3_F_ZERO_CTL_0, + (0 << 16) | /* V3_IE_F_ZERO_SAD_I16 */ + (0 << 0)); /* V3_IE_F_ZERO_SAD_I4 */ + WRITE_HREG(HCODEC_V3_F_ZERO_CTL_1, + (0 << 25) | /* v3_no_ver_when_top_zero_en */ + (0 << 24) | /* v3_no_hor_when_left_zero_en */ + (3 << 16) | /* type_hor break */ + (0 << 0)); /* V3_ME_F_ZERO_SAD */ + } + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { + int i; + /* MV SAD Table */ + for (i = 0; i < 64; i++) + WRITE_HREG(HCODEC_V3_MV_SAD_TABLE, + v3_mv_sad[i]); + + /* IE PRED SAD Table*/ + WRITE_HREG(HCODEC_V3_IPRED_TYPE_WEIGHT_0, + (C_ipred_weight_H << 24) | + (C_ipred_weight_V << 16) | + (I4_ipred_weight_else << 8) | + (I4_ipred_weight_most << 0)); + WRITE_HREG(HCODEC_V3_IPRED_TYPE_WEIGHT_1, + (I16_ipred_weight_DC << 24) | + (I16_ipred_weight_H << 16) | + (I16_ipred_weight_V << 8) | + (C_ipred_weight_DC << 0)); + WRITE_HREG(HCODEC_V3_LEFT_SMALL_MAX_SAD, + (v3_left_small_max_me_sad << 16) | + (v3_left_small_max_ie_sad << 0)); + } + WRITE_HREG(HCODEC_IE_DATA_FEED_BUFF_INFO, 0); + + WRITE_HREG(HCODEC_CURR_CANVAS_CTRL, 0); + data32 = READ_HREG(HCODEC_VLC_CONFIG); + data32 = data32 | (1 << 0); /* set pop_coeff_even_all_zero */ + WRITE_HREG(HCODEC_VLC_CONFIG, data32); + + WRITE_HREG(INFO_DUMP_START_ADDR, + wq->mem.dump_info_ddr_start_addr); + + /* clear mailbox interrupt */ + WRITE_HREG(HCODEC_IRQ_MBOX_CLR, 1); + + /* enable mailbox interrupt */ + WRITE_HREG(HCODEC_IRQ_MBOX_MASK, 1); +} + +void amvenc_reset(void) +{ + READ_VREG(DOS_SW_RESET1); + READ_VREG(DOS_SW_RESET1); + READ_VREG(DOS_SW_RESET1); + WRITE_VREG(DOS_SW_RESET1, + (1 << 2) | (1 << 6) | + (1 << 7) | (1 << 8) | + (1 << 14) | (1 << 16) | + (1 << 17)); + WRITE_VREG(DOS_SW_RESET1, 0); + READ_VREG(DOS_SW_RESET1); + READ_VREG(DOS_SW_RESET1); + READ_VREG(DOS_SW_RESET1); +} + +void amvenc_start(void) +{ + READ_VREG(DOS_SW_RESET1); + READ_VREG(DOS_SW_RESET1); + READ_VREG(DOS_SW_RESET1); + WRITE_VREG(DOS_SW_RESET1, + (1 << 12) | (1 << 11)); + WRITE_VREG(DOS_SW_RESET1, 0); + + READ_VREG(DOS_SW_RESET1); + READ_VREG(DOS_SW_RESET1); + READ_VREG(DOS_SW_RESET1); + + WRITE_HREG(HCODEC_MPSR, 0x0001); +} + +void amvenc_stop(void) +{ + ulong timeout = jiffies + HZ; + + WRITE_HREG(HCODEC_MPSR, 0); + WRITE_HREG(HCODEC_CPSR, 0); + while (READ_HREG(HCODEC_IMEM_DMA_CTRL) & 0x8000) { + if (time_after(jiffies, timeout)) + break; + } + READ_VREG(DOS_SW_RESET1); + READ_VREG(DOS_SW_RESET1); + READ_VREG(DOS_SW_RESET1); + + WRITE_VREG(DOS_SW_RESET1, + (1 << 12) | (1 << 11) | + (1 << 2) | (1 << 6) | + (1 << 7) | (1 << 8) | + (1 << 14) | (1 << 16) | + (1 << 17)); + + WRITE_VREG(DOS_SW_RESET1, 0); + + READ_VREG(DOS_SW_RESET1); + READ_VREG(DOS_SW_RESET1); + READ_VREG(DOS_SW_RESET1); +} + +static void __iomem *mc_addr; +static u32 mc_addr_map; +#define MC_SIZE (4096 * 8) +s32 amvenc_loadmc(const char *p, struct encode_wq_s *wq) +{ + ulong timeout; + s32 ret = 0; + + /* use static mempry*/ + if (mc_addr == NULL) { + mc_addr = kmalloc(MC_SIZE, GFP_KERNEL); + if (!mc_addr) { + enc_pr(LOG_ERROR, "avc loadmc iomap mc addr error.\n"); + return -ENOMEM; + } + } + + enc_pr(LOG_ALL, "avc encode ucode name is %s\n", p); + ret = get_data_from_name(p, (u8 *)mc_addr); + if (ret < 0) { + enc_pr(LOG_ERROR, + "avc microcode fail ret=%d, name: %s, wq:%p.\n", + ret, p, (void *)wq); + } + + mc_addr_map = dma_map_single( + &encode_manager.this_pdev->dev, + mc_addr, MC_SIZE, DMA_TO_DEVICE); + + /* mc_addr_map = wq->mem.assit_buffer_offset; */ + /* mc_addr = ioremap_wc(mc_addr_map, MC_SIZE); */ + /* memcpy(mc_addr, p, MC_SIZE); */ + enc_pr(LOG_ALL, "address 0 is 0x%x\n", *((u32 *)mc_addr)); + enc_pr(LOG_ALL, "address 1 is 0x%x\n", *((u32 *)mc_addr + 1)); + enc_pr(LOG_ALL, "address 2 is 0x%x\n", *((u32 *)mc_addr + 2)); + enc_pr(LOG_ALL, "address 3 is 0x%x\n", *((u32 *)mc_addr + 3)); + WRITE_HREG(HCODEC_MPSR, 0); + WRITE_HREG(HCODEC_CPSR, 0); + + /* Read CBUS register for timing */ + timeout = READ_HREG(HCODEC_MPSR); + timeout = READ_HREG(HCODEC_MPSR); + + timeout = jiffies + HZ; + + WRITE_HREG(HCODEC_IMEM_DMA_ADR, mc_addr_map); + WRITE_HREG(HCODEC_IMEM_DMA_COUNT, 0x1000); + WRITE_HREG(HCODEC_IMEM_DMA_CTRL, (0x8000 | (7 << 16))); + + while (READ_HREG(HCODEC_IMEM_DMA_CTRL) & 0x8000) { + if (time_before(jiffies, timeout)) + schedule(); + else { + enc_pr(LOG_ERROR, "hcodec load mc error\n"); + ret = -EBUSY; + break; + } + } + dma_unmap_single( + &encode_manager.this_pdev->dev, + mc_addr_map, MC_SIZE, DMA_TO_DEVICE); + return ret; +} + +const u32 fix_mc[] __aligned(8) = { + 0x0809c05a, 0x06696000, 0x0c780000, 0x00000000 +}; + + +/* + * DOS top level register access fix. + * When hcodec is running, a protocol register HCODEC_CCPU_INTR_MSK + * is set to make hcodec access one CBUS out of DOS domain once + * to work around a HW bug for 4k2k dual decoder implementation. + * If hcodec is not running, then a ucode is loaded and executed + * instead. + */ +void amvenc_dos_top_reg_fix(void) +{ + bool hcodec_on; + ulong flags; + + spin_lock_irqsave(&lock, flags); + + hcodec_on = vdec_on(VDEC_HCODEC); + + if ((hcodec_on) && (READ_VREG(HCODEC_MPSR) & 1)) { + WRITE_HREG(HCODEC_CCPU_INTR_MSK, 1); + spin_unlock_irqrestore(&lock, flags); + return; + } + + if (!hcodec_on) + vdec_poweron(VDEC_HCODEC); + + amhcodec_loadmc(fix_mc); + + amhcodec_start(); + + udelay(1000); + + amhcodec_stop(); + + if (!hcodec_on) + vdec_poweroff(VDEC_HCODEC); + + spin_unlock_irqrestore(&lock, flags); +} + +bool amvenc_avc_on(void) +{ + bool hcodec_on; + ulong flags; + + spin_lock_irqsave(&lock, flags); + + hcodec_on = vdec_on(VDEC_HCODEC); + hcodec_on &= (encode_manager.wq_count > 0); + + spin_unlock_irqrestore(&lock, flags); + return hcodec_on; +} + +static s32 avc_poweron(u32 clock) +{ + ulong flags; + u32 data32; + + data32 = 0; + + amports_switch_gate("vdec", 1); + + spin_lock_irqsave(&lock, flags); + + WRITE_AOREG(AO_RTI_PWR_CNTL_REG0, + (READ_AOREG(AO_RTI_PWR_CNTL_REG0) & (~0x18))); + udelay(10); + /* Powerup HCODEC */ + /* [1:0] HCODEC */ + WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, + (READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) & (~0x3))); + udelay(10); + + WRITE_VREG(DOS_SW_RESET1, 0xffffffff); + WRITE_VREG(DOS_SW_RESET1, 0); + + /* Enable Dos internal clock gating */ + hvdec_clock_enable(clock); + + /* Powerup HCODEC memories */ + WRITE_VREG(DOS_MEM_PD_HCODEC, 0x0); + + /* Remove HCODEC ISO */ + WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, + (READ_AOREG(AO_RTI_GEN_PWR_ISO0) & (~0x30))); + udelay(10); + /* Disable auto-clock gate */ + WRITE_VREG(DOS_GEN_CTRL0, + (READ_VREG(DOS_GEN_CTRL0) | 0x1)); + WRITE_VREG(DOS_GEN_CTRL0, + (READ_VREG(DOS_GEN_CTRL0) & 0xFFFFFFFE)); + + spin_unlock_irqrestore(&lock, flags); + + mdelay(10); + return 0; +} + +static s32 avc_poweroff(void) +{ + ulong flags; + + spin_lock_irqsave(&lock, flags); + + /* enable HCODEC isolation */ + WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, + READ_AOREG(AO_RTI_GEN_PWR_ISO0) | 0x30); + /* power off HCODEC memories */ + WRITE_VREG(DOS_MEM_PD_HCODEC, 0xffffffffUL); + + /* disable HCODEC clock */ + hvdec_clock_disable(); + + /* HCODEC power off */ + WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, + READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) | 0x3); + + spin_unlock_irqrestore(&lock, flags); + + /* release DOS clk81 clock gating */ + amports_switch_gate("vdec", 0); + return 0; +} + +static s32 reload_mc(struct encode_wq_s *wq) +{ + const char *p = select_ucode(encode_manager.ucode_index); + + amvenc_stop(); + + WRITE_VREG(DOS_SW_RESET1, 0xffffffff); + WRITE_VREG(DOS_SW_RESET1, 0); + + udelay(10); + + WRITE_HREG(HCODEC_ASSIST_MMC_CTRL1, 0x32); + enc_pr(LOG_INFO, "reload microcode\n"); + + if (amvenc_loadmc(p, wq) < 0) + return -EBUSY; + return 0; +} + +static void encode_isr_tasklet(ulong data) +{ + struct encode_manager_s *manager = (struct encode_manager_s *)data; + + enc_pr(LOG_INFO, "encoder is done %d\n", manager->encode_hw_status); + if (((manager->encode_hw_status == ENCODER_IDR_DONE) + || (manager->encode_hw_status == ENCODER_NON_IDR_DONE) + || (manager->encode_hw_status == ENCODER_SEQUENCE_DONE) + || (manager->encode_hw_status == ENCODER_PICTURE_DONE)) + && (manager->process_irq)) { + wake_up_interruptible(&manager->event.hw_complete); + } +} + +/* irq function */ +static irqreturn_t enc_isr(s32 irq_number, void *para) +{ + struct encode_manager_s *manager = (struct encode_manager_s *)para; + + WRITE_HREG(HCODEC_IRQ_MBOX_CLR, 1); + + manager->encode_hw_status = READ_HREG(ENCODER_STATUS); + if ((manager->encode_hw_status == ENCODER_IDR_DONE) + || (manager->encode_hw_status == ENCODER_NON_IDR_DONE) + || (manager->encode_hw_status == ENCODER_SEQUENCE_DONE) + || (manager->encode_hw_status == ENCODER_PICTURE_DONE)) { + enc_pr(LOG_ALL, "encoder stage is %d\n", + manager->encode_hw_status); + } + + if (((manager->encode_hw_status == ENCODER_IDR_DONE) + || (manager->encode_hw_status == ENCODER_NON_IDR_DONE) + || (manager->encode_hw_status == ENCODER_SEQUENCE_DONE) + || (manager->encode_hw_status == ENCODER_PICTURE_DONE)) + && (!manager->process_irq)) { + manager->process_irq = true; + if (manager->encode_hw_status != ENCODER_SEQUENCE_DONE) + manager->need_reset = true; + tasklet_schedule(&manager->encode_tasklet); + } + return IRQ_HANDLED; +} + +static s32 convert_request(struct encode_wq_s *wq, u32 *cmd_info) +{ + int i = 0; + u8 *ptr; + u32 data_offset; + u32 cmd = cmd_info[0]; + + if (!wq) + return -1; + memset(&wq->request, 0, sizeof(struct encode_request_s)); + wq->request.me_weight = ME_WEIGHT_OFFSET; + wq->request.i4_weight = I4MB_WEIGHT_OFFSET; + wq->request.i16_weight = I16MB_WEIGHT_OFFSET; + + if (cmd == ENCODER_SEQUENCE) { + wq->request.cmd = cmd; + wq->request.ucode_mode = cmd_info[1]; + wq->request.quant = cmd_info[2]; + wq->request.flush_flag = cmd_info[3]; + wq->request.timeout = cmd_info[4]; + wq->request.timeout = 5000; /* 5000 ms */ + } else if ((cmd == ENCODER_IDR) || (cmd == ENCODER_NON_IDR)) { + wq->request.cmd = cmd; + wq->request.ucode_mode = cmd_info[1]; + wq->request.type = cmd_info[2]; + wq->request.fmt = cmd_info[3]; + wq->request.src = cmd_info[4]; + wq->request.framesize = cmd_info[5]; + wq->request.quant = cmd_info[6]; + wq->request.flush_flag = cmd_info[7]; + wq->request.timeout = cmd_info[8]; + wq->request.crop_top = cmd_info[9]; + wq->request.crop_bottom = cmd_info[10]; + wq->request.crop_left = cmd_info[11]; + wq->request.crop_right = cmd_info[12]; + wq->request.src_w = cmd_info[13]; + wq->request.src_h = cmd_info[14]; + wq->request.scale_enable = cmd_info[15]; + wq->request.nr_mode = + (nr_mode > 0) ? nr_mode : cmd_info[16]; + if (cmd == ENCODER_IDR) + wq->request.nr_mode = 0; + + data_offset = 17 + + (sizeof(wq->quant_tbl_i4) + + sizeof(wq->quant_tbl_i16) + + sizeof(wq->quant_tbl_me)) / 4; + + if (wq->request.quant == ADJUSTED_QP_FLAG) { + ptr = (u8 *) &cmd_info[17]; + memcpy(wq->quant_tbl_i4, ptr, + sizeof(wq->quant_tbl_i4)); + ptr += sizeof(wq->quant_tbl_i4); + memcpy(wq->quant_tbl_i16, ptr, + sizeof(wq->quant_tbl_i16)); + ptr += sizeof(wq->quant_tbl_i16); + memcpy(wq->quant_tbl_me, ptr, + sizeof(wq->quant_tbl_me)); + wq->request.i4_weight -= + cmd_info[data_offset++]; + wq->request.i16_weight -= + cmd_info[data_offset++]; + wq->request.me_weight -= + cmd_info[data_offset++]; + if (qp_table_debug) { + u8 *qp_tb = (u8 *)(&wq->quant_tbl_i4[0]); + + for (i = 0; i < 32; i++) { + enc_pr(LOG_INFO, "%d ", *qp_tb); + qp_tb++; + } + enc_pr(LOG_INFO, "\n"); + + qp_tb = (u8 *)(&wq->quant_tbl_i16[0]); + for (i = 0; i < 32; i++) { + enc_pr(LOG_INFO, "%d ", *qp_tb); + qp_tb++; + } + enc_pr(LOG_INFO, "\n"); + + qp_tb = (u8 *)(&wq->quant_tbl_me[0]); + for (i = 0; i < 32; i++) { + enc_pr(LOG_INFO, "%d ", *qp_tb); + qp_tb++; + } + enc_pr(LOG_INFO, "\n"); + } + } else { + memset(wq->quant_tbl_me, wq->request.quant, + sizeof(wq->quant_tbl_me)); + memset(wq->quant_tbl_i4, wq->request.quant, + sizeof(wq->quant_tbl_i4)); + memset(wq->quant_tbl_i16, wq->request.quant, + sizeof(wq->quant_tbl_i16)); + data_offset += 3; + } +#ifdef H264_ENC_CBR + wq->cbr_info.block_w = cmd_info[data_offset++]; + wq->cbr_info.block_h = cmd_info[data_offset++]; + wq->cbr_info.long_th = cmd_info[data_offset++]; + wq->cbr_info.start_tbl_id = cmd_info[data_offset++]; + wq->cbr_info.short_shift = CBR_SHORT_SHIFT; + wq->cbr_info.long_mb_num = CBR_LONG_MB_NUM; +#endif + } else { + enc_pr(LOG_ERROR, "error cmd = %d, wq: %p.\n", + cmd, (void *)wq); + return -1; + } + wq->request.parent = wq; + return 0; +} + +void amvenc_avc_start_cmd(struct encode_wq_s *wq, + struct encode_request_s *request) +{ + u32 reload_flag = 0; + + if (request->ucode_mode != encode_manager.ucode_index) { + encode_manager.ucode_index = request->ucode_mode; + if (reload_mc(wq)) { + enc_pr(LOG_ERROR, + "reload mc fail, wq:%p\n", (void *)wq); + return; + } + reload_flag = 1; + encode_manager.need_reset = true; + } + + wq->hw_status = 0; + wq->output_size = 0; + wq->ucode_index = encode_manager.ucode_index; + + ie_me_mode = (0 & ME_PIXEL_MODE_MASK) << ME_PIXEL_MODE_SHIFT; + if (encode_manager.need_reset) { + encode_manager.need_reset = false; + encode_manager.encode_hw_status = ENCODER_IDLE; + amvenc_reset(); + avc_canvas_init(wq); + avc_init_encoder(wq, + (request->cmd == ENCODER_IDR) ? true : false); + avc_init_input_buffer(wq); + avc_init_output_buffer(wq); + avc_prot_init(wq, request, request->quant, + (request->cmd == ENCODER_IDR) ? true : false); + avc_init_assit_buffer(wq); + enc_pr(LOG_INFO, + "begin to new frame, request->cmd: %d, ucode mode: %d, wq:%p.\n", + request->cmd, request->ucode_mode, (void *)wq); + } + if ((request->cmd == ENCODER_IDR) || + (request->cmd == ENCODER_NON_IDR)) { + avc_init_dblk_buffer(wq->mem.dblk_buf_canvas); + avc_init_reference_buffer(wq->mem.ref_buf_canvas); + } + if ((request->cmd == ENCODER_IDR) || + (request->cmd == ENCODER_NON_IDR)) + set_input_format(wq, request); + if (request->cmd == ENCODER_IDR) + ie_me_mb_type = HENC_MB_Type_I4MB; + else if (request->cmd == ENCODER_NON_IDR) + ie_me_mb_type = + (HENC_SKIP_RUN_AUTO << 16) | + (HENC_MB_Type_AUTO << 4) | + (HENC_MB_Type_AUTO << 0); + else + ie_me_mb_type = 0; + avc_init_ie_me_parameter(wq, request->quant); + +#ifdef MULTI_SLICE_MC + if (fixed_slice_cfg) + WRITE_HREG(FIXED_SLICE_CFG, fixed_slice_cfg); + else if (wq->pic.rows_per_slice != + (wq->pic.encoder_height + 15) >> 4) { + u32 mb_per_slice = (wq->pic.encoder_height + 15) >> 4; + + mb_per_slice = mb_per_slice * wq->pic.rows_per_slice; + WRITE_HREG(FIXED_SLICE_CFG, mb_per_slice); + } else + WRITE_HREG(FIXED_SLICE_CFG, 0); +#else + WRITE_HREG(FIXED_SLICE_CFG, 0); +#endif + + encode_manager.encode_hw_status = request->cmd; + wq->hw_status = request->cmd; + WRITE_HREG(ENCODER_STATUS, request->cmd); + if ((request->cmd == ENCODER_IDR) + || (request->cmd == ENCODER_NON_IDR) + || (request->cmd == ENCODER_SEQUENCE) + || (request->cmd == ENCODER_PICTURE)) + encode_manager.process_irq = false; + + if (reload_flag) + amvenc_start(); + enc_pr(LOG_ALL, "amvenc_avc_start cmd, wq:%p.\n", (void *)wq); +} + +static void dma_flush(u32 buf_start, u32 buf_size) +{ + if ((buf_start == 0) || (buf_size == 0)) + return; + dma_sync_single_for_device( + &encode_manager.this_pdev->dev, buf_start, + buf_size, DMA_TO_DEVICE); +} + +static void cache_flush(u32 buf_start, u32 buf_size) +{ + if ((buf_start == 0) || (buf_size == 0)) + return; + dma_sync_single_for_cpu( + &encode_manager.this_pdev->dev, buf_start, + buf_size, DMA_FROM_DEVICE); +} + +static u32 getbuffer(struct encode_wq_s *wq, u32 type) +{ + u32 ret = 0; + + switch (type) { + case ENCODER_BUFFER_INPUT: + ret = wq->mem.dct_buff_start_addr; + break; + case ENCODER_BUFFER_REF0: + ret = wq->mem.dct_buff_start_addr + + wq->mem.bufspec.dec0_y.buf_start; + break; + case ENCODER_BUFFER_REF1: + ret = wq->mem.dct_buff_start_addr + + wq->mem.bufspec.dec1_y.buf_start; + break; + case ENCODER_BUFFER_OUTPUT: + ret = wq->mem.BitstreamStart; + break; + case ENCODER_BUFFER_DUMP: + ret = wq->mem.dump_info_ddr_start_addr; + break; + case ENCODER_BUFFER_CBR: + ret = wq->mem.cbr_info_ddr_start_addr; + break; + default: + break; + } + return ret; +} + +s32 amvenc_avc_start(struct encode_wq_s *wq, u32 clock) +{ + const char *p = select_ucode(encode_manager.ucode_index); + + avc_poweron(clock); + avc_canvas_init(wq); + + WRITE_HREG(HCODEC_ASSIST_MMC_CTRL1, 0x32); + + if (amvenc_loadmc(p, wq) < 0) + return -EBUSY; + + encode_manager.need_reset = true; + encode_manager.process_irq = false; + encode_manager.encode_hw_status = ENCODER_IDLE; + amvenc_reset(); + avc_init_encoder(wq, true); + avc_init_input_buffer(wq); /* dct buffer setting */ + avc_init_output_buffer(wq); /* output stream buffer */ + + ie_me_mode = (0 & ME_PIXEL_MODE_MASK) << ME_PIXEL_MODE_SHIFT; + avc_prot_init(wq, NULL, wq->pic.init_qppicture, true); + if (request_irq(encode_manager.irq_num, enc_isr, IRQF_SHARED, + "enc-irq", (void *)&encode_manager) == 0) + encode_manager.irq_requested = true; + else + encode_manager.irq_requested = false; + + /* decoder buffer , need set before each frame start */ + avc_init_dblk_buffer(wq->mem.dblk_buf_canvas); + /* reference buffer , need set before each frame start */ + avc_init_reference_buffer(wq->mem.ref_buf_canvas); + avc_init_assit_buffer(wq); /* assitant buffer for microcode */ + ie_me_mb_type = 0; + avc_init_ie_me_parameter(wq, wq->pic.init_qppicture); + WRITE_HREG(ENCODER_STATUS, ENCODER_IDLE); + +#ifdef MULTI_SLICE_MC + if (fixed_slice_cfg) + WRITE_HREG(FIXED_SLICE_CFG, fixed_slice_cfg); + else if (wq->pic.rows_per_slice != + (wq->pic.encoder_height + 15) >> 4) { + u32 mb_per_slice = (wq->pic.encoder_height + 15) >> 4; + + mb_per_slice = mb_per_slice * wq->pic.rows_per_slice; + WRITE_HREG(FIXED_SLICE_CFG, mb_per_slice); + } else + WRITE_HREG(FIXED_SLICE_CFG, 0); +#else + WRITE_HREG(FIXED_SLICE_CFG, 0); +#endif + amvenc_start(); + return 0; +} + +void amvenc_avc_stop(void) +{ + if ((encode_manager.irq_num >= 0) && + (encode_manager.irq_requested == true)) { + free_irq(encode_manager.irq_num, &encode_manager); + encode_manager.irq_requested = false; + } + amvenc_stop(); + avc_poweroff(); +} + +static s32 avc_init(struct encode_wq_s *wq) +{ + s32 r = 0; + + encode_manager.ucode_index = wq->ucode_index; + r = amvenc_avc_start(wq, clock_level); + + enc_pr(LOG_DEBUG, + "init avc encode. microcode %d, ret=%d, wq:%p.\n", + encode_manager.ucode_index, r, (void *)wq); + return 0; +} + +static s32 amvenc_avc_light_reset(struct encode_wq_s *wq, u32 value) +{ + s32 r = 0; + + amvenc_avc_stop(); + + mdelay(value); + + encode_manager.ucode_index = UCODE_MODE_FULL; + r = amvenc_avc_start(wq, clock_level); + + enc_pr(LOG_DEBUG, + "amvenc_avc_light_reset finish, wq:%p. ret=%d\n", + (void *)wq, r); + return r; +} + +#ifdef CONFIG_CMA +static u32 checkCMA(void) +{ + u32 ret; + + if (encode_manager.cma_pool_size > 0) { + ret = encode_manager.cma_pool_size; + ret = ret / MIN_SIZE; + } else + ret = 0; + return ret; +} +#endif + +/* file operation */ +static s32 amvenc_avc_open(struct inode *inode, struct file *file) +{ + s32 r = 0; + struct encode_wq_s *wq = NULL; + + file->private_data = NULL; + enc_pr(LOG_DEBUG, "avc open\n"); +#ifdef CONFIG_AM_JPEG_ENCODER + if (jpegenc_on() == true) { + enc_pr(LOG_ERROR, + "hcodec in use for JPEG Encode now.\n"); + return -EBUSY; + } +#endif + +#ifdef CONFIG_CMA + if ((encode_manager.use_reserve == false) && + (encode_manager.check_cma == false)) { + encode_manager.max_instance = checkCMA(); + if (encode_manager.max_instance > 0) { + enc_pr(LOG_DEBUG, + "amvenc_avc check CMA pool success, max instance: %d.\n", + encode_manager.max_instance); + } else { + enc_pr(LOG_ERROR, + "amvenc_avc CMA pool too small.\n"); + } + encode_manager.check_cma = true; + } +#endif + + wq = create_encode_work_queue(); + if (wq == NULL) { + enc_pr(LOG_ERROR, "amvenc_avc create instance fail.\n"); + return -EBUSY; + } + +#ifdef CONFIG_CMA + if (encode_manager.use_reserve == false) { + wq->mem.buf_start = codec_mm_alloc_for_dma(ENCODE_NAME, + MIN_SIZE >> PAGE_SHIFT, 0, + CODEC_MM_FLAGS_CPU); + if (wq->mem.buf_start) { + wq->mem.buf_size = MIN_SIZE; + enc_pr(LOG_DEBUG, + "allocating phys 0x%x, size %dk, wq:%p.\n", + wq->mem.buf_start, + wq->mem.buf_size >> 10, (void *)wq); + } else { + enc_pr(LOG_ERROR, + "CMA failed to allocate dma buffer for %s, wq:%p.\n", + encode_manager.this_pdev->name, + (void *)wq); + destroy_encode_work_queue(wq); + return -ENOMEM; + } + } +#endif + + if (wq->mem.buf_start == 0 || + wq->mem.buf_size < MIN_SIZE) { + enc_pr(LOG_ERROR, + "alloc mem failed, start: 0x%x, size:0x%x, wq:%p.\n", + wq->mem.buf_start, + wq->mem.buf_size, (void *)wq); + destroy_encode_work_queue(wq); + return -ENOMEM; + } + + memcpy(&wq->mem.bufspec, &amvenc_buffspec[0], + sizeof(struct BuffInfo_s)); + + enc_pr(LOG_DEBUG, + "amvenc_avc memory config success, buff start:0x%x, size is 0x%x, wq:%p.\n", + wq->mem.buf_start, wq->mem.buf_size, (void *)wq); + + file->private_data = (void *) wq; + return r; +} + +static s32 amvenc_avc_release(struct inode *inode, struct file *file) +{ + struct encode_wq_s *wq = (struct encode_wq_s *)file->private_data; + + if (wq) { + enc_pr(LOG_DEBUG, "avc release, wq:%p\n", (void *)wq); + destroy_encode_work_queue(wq); + } + return 0; +} + +static long amvenc_avc_ioctl(struct file *file, u32 cmd, ulong arg) +{ + long r = 0; + u32 amrisc_cmd = 0; + struct encode_wq_s *wq = (struct encode_wq_s *)file->private_data; +#define MAX_ADDR_INFO_SIZE 50 + u32 addr_info[MAX_ADDR_INFO_SIZE + 4]; + ulong argV; + u32 buf_start; + s32 canvas = -1; + struct canvas_s dst; + + switch (cmd) { + case AMVENC_AVC_IOC_GET_ADDR: + if ((wq->mem.ref_buf_canvas & 0xff) == (ENC_CANVAS_OFFSET)) + put_user(1, (u32 *)arg); + else + put_user(2, (u32 *)arg); + break; + case AMVENC_AVC_IOC_INPUT_UPDATE: + break; + case AMVENC_AVC_IOC_NEW_CMD: + if (copy_from_user(addr_info, (void *)arg, + MAX_ADDR_INFO_SIZE * sizeof(u32))) { + enc_pr(LOG_ERROR, + "avc get new cmd error, wq:%p.\n", (void *)wq); + return -1; + } + r = convert_request(wq, addr_info); + if (r == 0) + r = encode_wq_add_request(wq); + if (r) { + enc_pr(LOG_ERROR, + "avc add new request error, wq:%p.\n", + (void *)wq); + } + break; + case AMVENC_AVC_IOC_GET_STAGE: + put_user(wq->hw_status, (u32 *)arg); + break; + case AMVENC_AVC_IOC_GET_OUTPUT_SIZE: + addr_info[0] = wq->output_size; + addr_info[1] = wq->me_weight; + addr_info[2] = wq->i4_weight; + addr_info[3] = wq->i16_weight; + r = copy_to_user((u32 *)arg, + addr_info, 4 * sizeof(u32)); + break; + case AMVENC_AVC_IOC_CONFIG_INIT: + if (copy_from_user(addr_info, (void *)arg, + MAX_ADDR_INFO_SIZE * sizeof(u32))) { + enc_pr(LOG_ERROR, + "avc config init error, wq:%p.\n", (void *)wq); + return -1; + } + wq->ucode_index = UCODE_MODE_FULL; +#ifdef MULTI_SLICE_MC + wq->pic.rows_per_slice = addr_info[1]; + enc_pr(LOG_DEBUG, + "avc init -- rows_per_slice: %d, wq: %p.\n", + wq->pic.rows_per_slice, (void *)wq); +#endif + enc_pr(LOG_DEBUG, + "avc init as mode %d, wq: %p.\n", + wq->ucode_index, (void *)wq); + + if (addr_info[2] > wq->mem.bufspec.max_width || + addr_info[3] > wq->mem.bufspec.max_height) { + enc_pr(LOG_ERROR, + "avc config init- encode size %dx%d is larger than supported (%dx%d). wq:%p.\n", + addr_info[2], addr_info[3], + wq->mem.bufspec.max_width, + wq->mem.bufspec.max_height, (void *)wq); + return -1; + } + wq->pic.encoder_width = addr_info[2]; + wq->pic.encoder_height = addr_info[3]; + if (wq->pic.encoder_width * + wq->pic.encoder_height >= 1280 * 720) + clock_level = 6; + else + clock_level = 5; + avc_buffspec_init(wq); + complete(&encode_manager.event.request_in_com); + addr_info[1] = wq->mem.bufspec.dct.buf_start; + addr_info[2] = wq->mem.bufspec.dct.buf_size; + addr_info[3] = wq->mem.bufspec.bitstream.buf_start; + addr_info[4] = wq->mem.bufspec.bitstream.buf_size; + addr_info[5] = wq->mem.bufspec.scale_buff.buf_start; + addr_info[6] = wq->mem.bufspec.scale_buff.buf_size; + addr_info[7] = wq->mem.bufspec.dump_info.buf_start; + addr_info[8] = wq->mem.bufspec.dump_info.buf_size; + addr_info[9] = wq->mem.bufspec.cbr_info.buf_start; + addr_info[10] = wq->mem.bufspec.cbr_info.buf_size; + r = copy_to_user((u32 *)arg, addr_info, 11*sizeof(u32)); + break; + case AMVENC_AVC_IOC_FLUSH_CACHE: + if (copy_from_user(addr_info, (void *)arg, + MAX_ADDR_INFO_SIZE * sizeof(u32))) { + enc_pr(LOG_ERROR, + "avc flush cache error, wq: %p.\n", (void *)wq); + return -1; + } + buf_start = getbuffer(wq, addr_info[0]); + dma_flush(buf_start + addr_info[1], + addr_info[2] - addr_info[1]); + break; + case AMVENC_AVC_IOC_FLUSH_DMA: + if (copy_from_user(addr_info, (void *)arg, + MAX_ADDR_INFO_SIZE * sizeof(u32))) { + enc_pr(LOG_ERROR, + "avc flush dma error, wq:%p.\n", (void *)wq); + return -1; + } + buf_start = getbuffer(wq, addr_info[0]); + cache_flush(buf_start + addr_info[1], + addr_info[2] - addr_info[1]); + break; + case AMVENC_AVC_IOC_GET_BUFFINFO: + put_user(wq->mem.buf_size, (u32 *)arg); + break; + case AMVENC_AVC_IOC_GET_DEVINFO: + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) { + /* send the same id as GXTVBB to upper*/ + r = copy_to_user((s8 *)arg, AMVENC_DEVINFO_GXTVBB, + strlen(AMVENC_DEVINFO_GXTVBB)); + } else if (get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB) { + r = copy_to_user((s8 *)arg, AMVENC_DEVINFO_GXTVBB, + strlen(AMVENC_DEVINFO_GXTVBB)); + } else if (get_cpu_type() == MESON_CPU_MAJOR_ID_GXBB) { + r = copy_to_user((s8 *)arg, AMVENC_DEVINFO_GXBB, + strlen(AMVENC_DEVINFO_GXBB)); + } else if (get_cpu_type() == MESON_CPU_MAJOR_ID_MG9TV) { + r = copy_to_user((s8 *)arg, AMVENC_DEVINFO_G9, + strlen(AMVENC_DEVINFO_G9)); + } else { + r = copy_to_user((s8 *)arg, AMVENC_DEVINFO_M8, + strlen(AMVENC_DEVINFO_M8)); + } + break; + case AMVENC_AVC_IOC_SUBMIT: + get_user(amrisc_cmd, ((u32 *)arg)); + if (amrisc_cmd == ENCODER_IDR) { + wq->pic.idr_pic_id++; + if (wq->pic.idr_pic_id > 65535) + wq->pic.idr_pic_id = 0; + wq->pic.pic_order_cnt_lsb = 2; + wq->pic.frame_number = 1; + } else if (amrisc_cmd == ENCODER_NON_IDR) { + wq->pic.frame_number++; + wq->pic.pic_order_cnt_lsb += 2; + if (wq->pic.frame_number > 65535) + wq->pic.frame_number = 0; + } + amrisc_cmd = wq->mem.dblk_buf_canvas; + wq->mem.dblk_buf_canvas = wq->mem.ref_buf_canvas; + /* current dblk buffer as next reference buffer */ + wq->mem.ref_buf_canvas = amrisc_cmd; + break; + case AMVENC_AVC_IOC_READ_CANVAS: + get_user(argV, ((u32 *)arg)); + canvas = argV; + if (canvas & 0xff) { + canvas_read(canvas & 0xff, &dst); + addr_info[0] = dst.addr; + if ((canvas & 0xff00) >> 8) + canvas_read((canvas & 0xff00) >> 8, &dst); + if ((canvas & 0xff0000) >> 16) + canvas_read((canvas & 0xff0000) >> 16, &dst); + addr_info[1] = dst.addr - addr_info[0] + + dst.width * dst.height; + } else { + addr_info[0] = 0; + addr_info[1] = 0; + } + dma_flush(dst.addr, dst.width * dst.height * 3 / 2); + r = copy_to_user((u32 *)arg, addr_info, 2 * sizeof(u32)); + break; + case AMVENC_AVC_IOC_MAX_INSTANCE: + put_user(encode_manager.max_instance, (u32 *)arg); + break; + default: + r = -1; + break; + } + return r; +} + +#ifdef CONFIG_COMPAT +static long amvenc_avc_compat_ioctl(struct file *filp, + unsigned int cmd, unsigned long args) +{ + unsigned long ret; + + args = (unsigned long)compat_ptr(args); + ret = amvenc_avc_ioctl(filp, cmd, args); + return ret; +} +#endif + +static s32 avc_mmap(struct file *filp, struct vm_area_struct *vma) +{ + struct encode_wq_s *wq = (struct encode_wq_s *)filp->private_data; + ulong off = vma->vm_pgoff << PAGE_SHIFT; + ulong vma_size = vma->vm_end - vma->vm_start; + + if (vma_size == 0) { + enc_pr(LOG_ERROR, "vma_size is 0, wq:%p.\n", (void *)wq); + return -EAGAIN; + } + if (!off) + off += wq->mem.buf_start; + enc_pr(LOG_ALL, + "vma_size is %ld , off is %ld, wq:%p.\n", + vma_size, off, (void *)wq); + vma->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP | VM_IO; + /* vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); */ + if (remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT, + vma->vm_end - vma->vm_start, vma->vm_page_prot)) { + enc_pr(LOG_ERROR, + "set_cached: failed remap_pfn_range, wq:%p.\n", + (void *)wq); + return -EAGAIN; + } + return 0; +} + +static u32 amvenc_avc_poll(struct file *file, poll_table *wait_table) +{ + struct encode_wq_s *wq = (struct encode_wq_s *)file->private_data; + + poll_wait(file, &wq->request_complete, wait_table); + + if (atomic_read(&wq->request_ready)) { + atomic_dec(&wq->request_ready); + return POLLIN | POLLRDNORM; + } + return 0; +} + +static const struct file_operations amvenc_avc_fops = { + .owner = THIS_MODULE, + .open = amvenc_avc_open, + .mmap = avc_mmap, + .release = amvenc_avc_release, + .unlocked_ioctl = amvenc_avc_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = amvenc_avc_compat_ioctl, +#endif + .poll = amvenc_avc_poll, +}; + +/* work queue function */ +static s32 encode_process_request(struct encode_manager_s *manager, + struct encode_queue_item_s *pitem) +{ + s32 ret = 0; + struct encode_wq_s *wq = pitem->request.parent; + struct encode_request_s *request = &pitem->request; + u32 timeout = (request->timeout == 0) ? + 1 : msecs_to_jiffies(request->timeout); + u32 buf_start = 0; + u32 size = 0; + u32 flush_size = ((wq->pic.encoder_width + 31) >> 5 << 5) * + ((wq->pic.encoder_height + 15) >> 4 << 4) * 3 / 2; + +#ifdef H264_ENC_CBR + if (request->cmd == ENCODER_IDR || request->cmd == ENCODER_NON_IDR) { + if (request->flush_flag & AMVENC_FLUSH_FLAG_CBR + && get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { + void *vaddr = + phys_to_virt(wq->mem.cbr_info_ddr_start_addr); + ConvertTable2Risc(vaddr, 0xa00); + buf_start = getbuffer(wq, ENCODER_BUFFER_CBR); + dma_flush(buf_start, wq->mem.cbr_info_ddr_size); + } + } +#endif + +Again: + amvenc_avc_start_cmd(wq, request); + + if (no_timeout) { + wait_event_interruptible(manager->event.hw_complete, + (manager->encode_hw_status == ENCODER_IDR_DONE + || manager->encode_hw_status == ENCODER_NON_IDR_DONE + || manager->encode_hw_status == ENCODER_SEQUENCE_DONE + || manager->encode_hw_status == ENCODER_PICTURE_DONE)); + } else { + wait_event_interruptible_timeout(manager->event.hw_complete, + ((manager->encode_hw_status == ENCODER_IDR_DONE) + || (manager->encode_hw_status == ENCODER_NON_IDR_DONE) + || (manager->encode_hw_status == ENCODER_SEQUENCE_DONE) + || (manager->encode_hw_status == ENCODER_PICTURE_DONE)), + timeout); + } + + if ((request->cmd == ENCODER_SEQUENCE) && + (manager->encode_hw_status == ENCODER_SEQUENCE_DONE)) { + wq->sps_size = READ_HREG(HCODEC_VLC_TOTAL_BYTES); + wq->hw_status = manager->encode_hw_status; + request->cmd = ENCODER_PICTURE; + goto Again; + } else if ((request->cmd == ENCODER_PICTURE) && + (manager->encode_hw_status == ENCODER_PICTURE_DONE)) { + wq->pps_size = + READ_HREG(HCODEC_VLC_TOTAL_BYTES) - wq->sps_size; + wq->hw_status = manager->encode_hw_status; + if (request->flush_flag & AMVENC_FLUSH_FLAG_OUTPUT) { + buf_start = getbuffer(wq, ENCODER_BUFFER_OUTPUT); + cache_flush(buf_start, + wq->sps_size + wq->pps_size); + } + wq->output_size = (wq->sps_size << 16) | wq->pps_size; + } else { + wq->hw_status = manager->encode_hw_status; + if ((manager->encode_hw_status == ENCODER_IDR_DONE) || + (manager->encode_hw_status == ENCODER_NON_IDR_DONE)) { + wq->output_size = READ_HREG(HCODEC_VLC_TOTAL_BYTES); + if (request->flush_flag & AMVENC_FLUSH_FLAG_OUTPUT) { + buf_start = getbuffer(wq, + ENCODER_BUFFER_OUTPUT); + cache_flush(buf_start, wq->output_size); + } + if (request->flush_flag & + AMVENC_FLUSH_FLAG_DUMP) { + buf_start = getbuffer(wq, + ENCODER_BUFFER_DUMP); + size = wq->mem.dump_info_ddr_size; + cache_flush(buf_start, size); + //enc_pr(LOG_DEBUG, "CBR flush dump_info done"); + } + if (request->flush_flag & + AMVENC_FLUSH_FLAG_REFERENCE) { + u32 ref_id = ENCODER_BUFFER_REF0; + + if ((wq->mem.ref_buf_canvas & 0xff) == + (ENC_CANVAS_OFFSET)) + ref_id = ENCODER_BUFFER_REF0; + else + ref_id = ENCODER_BUFFER_REF1; + buf_start = getbuffer(wq, ref_id); + cache_flush(buf_start, flush_size); + } + } else { + manager->encode_hw_status = ENCODER_ERROR; + enc_pr(LOG_DEBUG, "avc encode light reset --- "); + enc_pr(LOG_DEBUG, + "frame type: %s, size: %dx%d, wq: %p\n", + (request->cmd == ENCODER_IDR) ? "IDR" : "P", + wq->pic.encoder_width, + wq->pic.encoder_height, (void *)wq); + enc_pr(LOG_DEBUG, + "mb info: 0x%x, encode status: 0x%x, dct status: 0x%x ", + READ_HREG(HCODEC_VLC_MB_INFO), + READ_HREG(ENCODER_STATUS), + READ_HREG(HCODEC_QDCT_STATUS_CTRL)); + enc_pr(LOG_DEBUG, + "vlc status: 0x%x, me status: 0x%x, risc pc:0x%x, debug:0x%x\n", + READ_HREG(HCODEC_VLC_STATUS_CTRL), + READ_HREG(HCODEC_ME_STATUS), + READ_HREG(HCODEC_MPC_E), + READ_HREG(DEBUG_REG)); + amvenc_avc_light_reset(wq, 30); + } + } + atomic_inc(&wq->request_ready); + wake_up_interruptible(&wq->request_complete); + return ret; +} + +s32 encode_wq_add_request(struct encode_wq_s *wq) +{ + struct encode_queue_item_s *pitem = NULL; + struct list_head *head = NULL; + struct encode_wq_s *tmp = NULL; + bool find = false; + + spin_lock(&encode_manager.event.sem_lock); + + head = &encode_manager.wq; + list_for_each_entry(tmp, head, list) { + if ((wq == tmp) && (wq != NULL)) { + find = true; + break; + } + } + + if (find == false) { + enc_pr(LOG_ERROR, "current wq (%p) doesn't register.\n", + (void *)wq); + goto error; + } + + if (list_empty(&encode_manager.free_queue)) { + enc_pr(LOG_ERROR, "work queue no space, wq:%p.\n", + (void *)wq); + goto error; + } + + pitem = list_entry(encode_manager.free_queue.next, + struct encode_queue_item_s, list); + if (IS_ERR(pitem)) + goto error; + + memcpy(&pitem->request, &wq->request, sizeof(struct encode_request_s)); + memset(&wq->request, 0, sizeof(struct encode_request_s)); + wq->hw_status = 0; + wq->output_size = 0; + pitem->request.parent = wq; + list_move_tail(&pitem->list, &encode_manager.process_queue); + spin_unlock(&encode_manager.event.sem_lock); + + enc_pr(LOG_INFO, + "add new work ok, cmd:%d, ucode mode: %d, wq:%p.\n", + pitem->request.cmd, pitem->request.ucode_mode, + (void *)wq); + complete(&encode_manager.event.request_in_com);/* new cmd come in */ + return 0; +error: + spin_unlock(&encode_manager.event.sem_lock); + return -1; +} + +struct encode_wq_s *create_encode_work_queue(void) +{ + struct encode_wq_s *encode_work_queue = NULL; + bool done = false; + u32 i, max_instance; + struct Buff_s *reserve_buff; + + encode_work_queue = kzalloc(sizeof(struct encode_wq_s), GFP_KERNEL); + if (IS_ERR(encode_work_queue)) { + enc_pr(LOG_ERROR, "can't create work queue\n"); + return NULL; + } + max_instance = encode_manager.max_instance; + encode_work_queue->pic.init_qppicture = 26; + encode_work_queue->pic.log2_max_frame_num = 4; + encode_work_queue->pic.log2_max_pic_order_cnt_lsb = 4; + encode_work_queue->pic.idr_pic_id = 0; + encode_work_queue->pic.frame_number = 0; + encode_work_queue->pic.pic_order_cnt_lsb = 0; + encode_work_queue->ucode_index = UCODE_MODE_FULL; + +#ifdef H264_ENC_CBR + encode_work_queue->cbr_info.block_w = 16; + encode_work_queue->cbr_info.block_h = 9; + encode_work_queue->cbr_info.long_th = CBR_LONG_THRESH; + encode_work_queue->cbr_info.start_tbl_id = START_TABLE_ID; + encode_work_queue->cbr_info.short_shift = CBR_SHORT_SHIFT; + encode_work_queue->cbr_info.long_mb_num = CBR_LONG_MB_NUM; +#endif + init_waitqueue_head(&encode_work_queue->request_complete); + atomic_set(&encode_work_queue->request_ready, 0); + spin_lock(&encode_manager.event.sem_lock); + if (encode_manager.wq_count < encode_manager.max_instance) { + list_add_tail(&encode_work_queue->list, &encode_manager.wq); + encode_manager.wq_count++; + if (encode_manager.use_reserve == true) { + for (i = 0; i < max_instance; i++) { + reserve_buff = &encode_manager.reserve_buff[i]; + if (reserve_buff->used == false) { + encode_work_queue->mem.buf_start = + reserve_buff->buf_start; + encode_work_queue->mem.buf_size = + reserve_buff->buf_size; + reserve_buff->used = true; + done = true; + break; + } + } + } else + done = true; + } + spin_unlock(&encode_manager.event.sem_lock); + if (done == false) { + kfree(encode_work_queue); + encode_work_queue = NULL; + enc_pr(LOG_ERROR, "too many work queue!\n"); + } + return encode_work_queue; /* find it */ +} + +static void _destroy_encode_work_queue(struct encode_manager_s *manager, + struct encode_wq_s **wq, + struct encode_wq_s *encode_work_queue, + bool *find) +{ + struct list_head *head; + struct encode_wq_s *wp_tmp = NULL; + u32 i, max_instance; + struct Buff_s *reserve_buff; + u32 buf_start = encode_work_queue->mem.buf_start; + + max_instance = manager->max_instance; + head = &manager->wq; + list_for_each_entry_safe((*wq), wp_tmp, head, list) { + if ((*wq) && (*wq == encode_work_queue)) { + list_del(&(*wq)->list); + if (manager->use_reserve == true) { + for (i = 0; i < max_instance; i++) { + reserve_buff = + &manager->reserve_buff[i]; + if (reserve_buff->used == true && + buf_start == + reserve_buff->buf_start) { + reserve_buff->used = false; + break; + } + } + } + *find = true; + manager->wq_count--; + enc_pr(LOG_DEBUG, + "remove encode_work_queue %p success, %s line %d.\n", + (void *)encode_work_queue, + __func__, __LINE__); + break; + } + } +} + +s32 destroy_encode_work_queue(struct encode_wq_s *encode_work_queue) +{ + struct encode_queue_item_s *pitem, *tmp; + struct encode_wq_s *wq = NULL; + bool find = false; + + struct list_head *head; + + if (encode_work_queue) { + spin_lock(&encode_manager.event.sem_lock); + if (encode_manager.current_wq == encode_work_queue) { + encode_manager.remove_flag = true; + spin_unlock(&encode_manager.event.sem_lock); + enc_pr(LOG_DEBUG, + "warning--Destroy the running queue, should not be here.\n"); + wait_for_completion( + &encode_manager.event.process_complete); + spin_lock(&encode_manager.event.sem_lock); + } /* else we can delete it safely. */ + + head = &encode_manager.process_queue; + list_for_each_entry_safe(pitem, tmp, head, list) { + if (pitem && pitem->request.parent == + encode_work_queue) { + pitem->request.parent = NULL; + enc_pr(LOG_DEBUG, + "warning--remove not process request, should not be here.\n"); + list_move_tail(&pitem->list, + &encode_manager.free_queue); + } + } + + _destroy_encode_work_queue(&encode_manager, &wq, + encode_work_queue, &find); + spin_unlock(&encode_manager.event.sem_lock); +#ifdef CONFIG_CMA + if (encode_work_queue->mem.buf_start) { + codec_mm_free_for_dma( + ENCODE_NAME, + encode_work_queue->mem.buf_start); + encode_work_queue->mem.buf_start = 0; + + } +#endif + kfree(encode_work_queue); + complete(&encode_manager.event.request_in_com); + } + return 0; +} + +static s32 encode_monitor_thread(void *data) +{ + struct encode_manager_s *manager = (struct encode_manager_s *)data; + struct encode_queue_item_s *pitem = NULL; + struct sched_param param = {.sched_priority = MAX_RT_PRIO - 1 }; + s32 ret = 0; + + enc_pr(LOG_DEBUG, "encode workqueue monitor start.\n"); + sched_setscheduler(current, SCHED_FIFO, ¶m); + allow_signal(SIGTERM); + /* setup current_wq here. */ + while (manager->process_queue_state != ENCODE_PROCESS_QUEUE_STOP) { + if (kthread_should_stop()) + break; + + ret = wait_for_completion_interruptible( + &manager->event.request_in_com); + + if (ret == -ERESTARTSYS) + break; + + if (kthread_should_stop()) + break; + if (manager->inited == false) { + spin_lock(&manager->event.sem_lock); + if (!list_empty(&manager->wq)) { + struct encode_wq_s *first_wq = + list_entry(manager->wq.next, + struct encode_wq_s, list); + manager->current_wq = first_wq; + spin_unlock(&manager->event.sem_lock); + if (first_wq) { +#ifdef CONFIG_AMLOGIC_MEDIA_GE2D + if (!manager->context) + manager->context = + create_ge2d_work_queue(); +#endif + avc_init(first_wq); + manager->inited = true; + } + spin_lock(&manager->event.sem_lock); + manager->current_wq = NULL; + spin_unlock(&manager->event.sem_lock); + if (manager->remove_flag) { + complete( + &manager + ->event.process_complete); + manager->remove_flag = false; + } + } else + spin_unlock(&manager->event.sem_lock); + continue; + } + + spin_lock(&manager->event.sem_lock); + pitem = NULL; + if (list_empty(&manager->wq)) { + spin_unlock(&manager->event.sem_lock); + manager->inited = false; + amvenc_avc_stop(); +#ifdef CONFIG_AMLOGIC_MEDIA_GE2D + if (manager->context) { + destroy_ge2d_work_queue(manager->context); + manager->context = NULL; + } +#endif + enc_pr(LOG_DEBUG, "power off encode.\n"); + continue; + } else if (!list_empty(&manager->process_queue)) { + pitem = list_entry(manager->process_queue.next, + struct encode_queue_item_s, list); + list_del(&pitem->list); + manager->current_item = pitem; + manager->current_wq = pitem->request.parent; + } + spin_unlock(&manager->event.sem_lock); + + if (pitem) { + encode_process_request(manager, pitem); + spin_lock(&manager->event.sem_lock); + list_add_tail(&pitem->list, &manager->free_queue); + manager->current_item = NULL; + manager->last_wq = manager->current_wq; + manager->current_wq = NULL; + spin_unlock(&manager->event.sem_lock); + } + if (manager->remove_flag) { + complete(&manager->event.process_complete); + manager->remove_flag = false; + } + } + while (!kthread_should_stop()) + msleep(20); + + enc_pr(LOG_DEBUG, "exit encode_monitor_thread.\n"); + return 0; +} + +static s32 encode_start_monitor(void) +{ + s32 ret = 0; + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) { + y_tnr_mot2alp_nrm_gain = 216; + y_tnr_mot2alp_dis_gain = 144; + c_tnr_mot2alp_nrm_gain = 216; + c_tnr_mot2alp_dis_gain = 144; + } else { + /* more tnr */ + y_tnr_mot2alp_nrm_gain = 144; + y_tnr_mot2alp_dis_gain = 96; + c_tnr_mot2alp_nrm_gain = 144; + c_tnr_mot2alp_dis_gain = 96; + } + + enc_pr(LOG_DEBUG, "encode start monitor.\n"); + encode_manager.process_queue_state = ENCODE_PROCESS_QUEUE_START; + encode_manager.encode_thread = kthread_run(encode_monitor_thread, + &encode_manager, "encode_monitor"); + if (IS_ERR(encode_manager.encode_thread)) { + ret = PTR_ERR(encode_manager.encode_thread); + encode_manager.process_queue_state = ENCODE_PROCESS_QUEUE_STOP; + enc_pr(LOG_ERROR, + "encode monitor : failed to start kthread (%d)\n", ret); + } + return ret; +} + +static s32 encode_stop_monitor(void) +{ + enc_pr(LOG_DEBUG, "stop encode monitor thread\n"); + if (encode_manager.encode_thread) { + spin_lock(&encode_manager.event.sem_lock); + if (!list_empty(&encode_manager.wq)) { + u32 count = encode_manager.wq_count; + + spin_unlock(&encode_manager.event.sem_lock); + enc_pr(LOG_ERROR, + "stop encode monitor thread error, active wq (%d) is not 0.\n", + count); + return -1; + } + spin_unlock(&encode_manager.event.sem_lock); + encode_manager.process_queue_state = ENCODE_PROCESS_QUEUE_STOP; + send_sig(SIGTERM, encode_manager.encode_thread, 1); + complete(&encode_manager.event.request_in_com); + kthread_stop(encode_manager.encode_thread); + encode_manager.encode_thread = NULL; + kfree(mc_addr); + mc_addr = NULL; + } + return 0; +} + +static s32 encode_wq_init(void) +{ + u32 i = 0; + struct encode_queue_item_s *pitem = NULL; + + enc_pr(LOG_DEBUG, "encode_wq_init.\n"); + encode_manager.irq_requested = false; + + spin_lock_init(&encode_manager.event.sem_lock); + init_completion(&encode_manager.event.request_in_com); + init_waitqueue_head(&encode_manager.event.hw_complete); + init_completion(&encode_manager.event.process_complete); + INIT_LIST_HEAD(&encode_manager.process_queue); + INIT_LIST_HEAD(&encode_manager.free_queue); + INIT_LIST_HEAD(&encode_manager.wq); + + tasklet_init(&encode_manager.encode_tasklet, + encode_isr_tasklet, + (ulong)&encode_manager); + + for (i = 0; i < MAX_ENCODE_REQUEST; i++) { + pitem = kcalloc(1, + sizeof(struct encode_queue_item_s), + GFP_KERNEL); + if (IS_ERR(pitem)) { + enc_pr(LOG_ERROR, "can't request queue item memory.\n"); + return -1; + } + pitem->request.parent = NULL; + list_add_tail(&pitem->list, &encode_manager.free_queue); + } + encode_manager.current_wq = NULL; + encode_manager.last_wq = NULL; + encode_manager.encode_thread = NULL; + encode_manager.current_item = NULL; + encode_manager.wq_count = 0; + encode_manager.remove_flag = false; + InitEncodeWeight(); + if (encode_start_monitor()) { + enc_pr(LOG_ERROR, "encode create thread error.\n"); + return -1; + } + return 0; +} + +static s32 encode_wq_uninit(void) +{ + struct encode_queue_item_s *pitem, *tmp; + struct list_head *head; + u32 count = 0; + s32 r = -1; + + enc_pr(LOG_DEBUG, "uninit encode wq.\n"); + if (encode_stop_monitor() == 0) { + if ((encode_manager.irq_num >= 0) && + (encode_manager.irq_requested == true)) { + free_irq(encode_manager.irq_num, &encode_manager); + encode_manager.irq_requested = false; + } + spin_lock(&encode_manager.event.sem_lock); + head = &encode_manager.process_queue; + list_for_each_entry_safe(pitem, tmp, head, list) { + if (pitem) { + list_del(&pitem->list); + kfree(pitem); + count++; + } + } + head = &encode_manager.free_queue; + list_for_each_entry_safe(pitem, tmp, head, list) { + if (pitem) { + list_del(&pitem->list); + kfree(pitem); + count++; + } + } + spin_unlock(&encode_manager.event.sem_lock); + if (count == MAX_ENCODE_REQUEST) + r = 0; + else { + enc_pr(LOG_ERROR, "lost some request item %d.\n", + MAX_ENCODE_REQUEST - count); + } + } + return r; +} + +static ssize_t encode_status_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + u32 process_count = 0; + u32 free_count = 0; + struct encode_queue_item_s *pitem = NULL; + struct encode_wq_s *current_wq = NULL; + struct encode_wq_s *last_wq = NULL; + struct list_head *head = NULL; + s32 irq_num = 0; + u32 hw_status = 0; + u32 process_queue_state = 0; + u32 wq_count = 0; + u32 ucode_index; + bool need_reset; + bool process_irq; + bool inited; + bool use_reserve; + struct Buff_s reserve_mem; + u32 max_instance; +#ifdef CONFIG_CMA + bool check_cma = false; +#endif + + spin_lock(&encode_manager.event.sem_lock); + head = &encode_manager.free_queue; + list_for_each_entry(pitem, head, list) { + free_count++; + if (free_count > MAX_ENCODE_REQUEST) + break; + } + + head = &encode_manager.process_queue; + list_for_each_entry(pitem, head, list) { + process_count++; + if (free_count > MAX_ENCODE_REQUEST) + break; + } + + current_wq = encode_manager.current_wq; + last_wq = encode_manager.last_wq; + pitem = encode_manager.current_item; + irq_num = encode_manager.irq_num; + hw_status = encode_manager.encode_hw_status; + process_queue_state = encode_manager.process_queue_state; + wq_count = encode_manager.wq_count; + ucode_index = encode_manager.ucode_index; + need_reset = encode_manager.need_reset; + process_irq = encode_manager.process_irq; + inited = encode_manager.inited; + use_reserve = encode_manager.use_reserve; + reserve_mem.buf_start = encode_manager.reserve_mem.buf_start; + reserve_mem.buf_size = encode_manager.reserve_mem.buf_size; + + max_instance = encode_manager.max_instance; +#ifdef CONFIG_CMA + check_cma = encode_manager.check_cma; +#endif + + spin_unlock(&encode_manager.event.sem_lock); + + enc_pr(LOG_DEBUG, + "encode process queue count: %d, free queue count: %d.\n", + process_count, free_count); + enc_pr(LOG_DEBUG, + "encode curent wq: %p, last wq: %p, wq count: %d, max_instance: %d.\n", + current_wq, last_wq, wq_count, max_instance); + if (current_wq) + enc_pr(LOG_DEBUG, + "encode curent wq -- encode width: %d, encode height: %d.\n", + current_wq->pic.encoder_width, + current_wq->pic.encoder_height); + enc_pr(LOG_DEBUG, + "encode curent pitem: %p, ucode_index: %d, hw_status: %d, need_reset: %s, process_irq: %s.\n", + pitem, ucode_index, hw_status, need_reset ? "true" : "false", + process_irq ? "true" : "false"); + enc_pr(LOG_DEBUG, + "encode irq num: %d, inited: %s, process_queue_state: %d.\n", + irq_num, inited ? "true" : "false", process_queue_state); + if (use_reserve) { + enc_pr(LOG_DEBUG, + "encode use reserve memory, buffer start: 0x%x, size: %d MB.\n", + reserve_mem.buf_start, + reserve_mem.buf_size / SZ_1M); + } else { +#ifdef CONFIG_CMA + enc_pr(LOG_DEBUG, "encode check cma: %s.\n", + check_cma ? "true" : "false"); +#endif + } + return snprintf(buf, 40, "encode max instance: %d\n", max_instance); +} + +static struct class_attribute amvenc_class_attrs[] = { + __ATTR(encode_status, + S_IRUGO | S_IWUSR, + encode_status_show, + NULL), + __ATTR_NULL +}; + +static struct class amvenc_avc_class = { + .name = CLASS_NAME, + .class_attrs = amvenc_class_attrs, +}; + +s32 init_avc_device(void) +{ + s32 r = 0; + + r = register_chrdev(0, DEVICE_NAME, &amvenc_avc_fops); + if (r <= 0) { + enc_pr(LOG_ERROR, "register amvenc_avc device error.\n"); + return r; + } + avc_device_major = r; + + r = class_register(&amvenc_avc_class); + if (r < 0) { + enc_pr(LOG_ERROR, "error create amvenc_avc class.\n"); + return r; + } + + amvenc_avc_dev = device_create(&amvenc_avc_class, NULL, + MKDEV(avc_device_major, 0), NULL, + DEVICE_NAME); + + if (IS_ERR(amvenc_avc_dev)) { + enc_pr(LOG_ERROR, "create amvenc_avc device error.\n"); + class_unregister(&amvenc_avc_class); + return -1; + } + return r; +} + +s32 uninit_avc_device(void) +{ + if (amvenc_avc_dev) + device_destroy(&amvenc_avc_class, MKDEV(avc_device_major, 0)); + + class_destroy(&amvenc_avc_class); + + unregister_chrdev(avc_device_major, DEVICE_NAME); + return 0; +} + +static s32 avc_mem_device_init(struct reserved_mem *rmem, struct device *dev) +{ + s32 r; + struct resource res; + + if (!rmem) { + enc_pr(LOG_ERROR, + "Can not obtain I/O memory, and will allocate avc buffer!\n"); + r = -EFAULT; + return r; + } + res.start = (phys_addr_t)rmem->base; + res.end = res.start + (phys_addr_t)rmem->size - 1; + encode_manager.reserve_mem.buf_start = res.start; + encode_manager.reserve_mem.buf_size = res.end - res.start + 1; + + if (encode_manager.reserve_mem.buf_size >= + amvenc_buffspec[0].min_buffsize) { + encode_manager.max_instance = + encode_manager.reserve_mem.buf_size / + amvenc_buffspec[0].min_buffsize; + if (encode_manager.max_instance > MAX_ENCODE_INSTANCE) + encode_manager.max_instance = MAX_ENCODE_INSTANCE; + encode_manager.reserve_buff = kzalloc( + encode_manager.max_instance * + sizeof(struct Buff_s), GFP_KERNEL); + if (encode_manager.reserve_buff) { + u32 i; + struct Buff_s *reserve_buff; + u32 max_instance = encode_manager.max_instance; + + for (i = 0; i < max_instance; i++) { + reserve_buff = &encode_manager.reserve_buff[i]; + reserve_buff->buf_start = + i * + amvenc_buffspec[0] + .min_buffsize + + encode_manager.reserve_mem.buf_start; + reserve_buff->buf_size = + encode_manager.reserve_mem.buf_start; + reserve_buff->used = false; + } + encode_manager.use_reserve = true; + r = 0; + enc_pr(LOG_DEBUG, + "amvenc_avc use reserve memory, buff start: 0x%x, size: 0x%x, max instance is %d\n", + encode_manager.reserve_mem.buf_start, + encode_manager.reserve_mem.buf_size, + encode_manager.max_instance); + } else { + enc_pr(LOG_ERROR, + "amvenc_avc alloc reserve buffer pointer fail. max instance is %d.\n", + encode_manager.max_instance); + encode_manager.max_instance = 0; + encode_manager.reserve_mem.buf_start = 0; + encode_manager.reserve_mem.buf_size = 0; + r = -ENOMEM; + } + } else { + enc_pr(LOG_ERROR, + "amvenc_avc memory resource too small, size is 0x%x. Need 0x%x bytes at least.\n", + encode_manager.reserve_mem.buf_size, + amvenc_buffspec[0] + .min_buffsize); + encode_manager.reserve_mem.buf_start = 0; + encode_manager.reserve_mem.buf_size = 0; + r = -ENOMEM; + } + return r; +} + +static s32 amvenc_avc_probe(struct platform_device *pdev) +{ + /* struct resource mem; */ + s32 res_irq; + s32 idx; + s32 r; + + enc_pr(LOG_INFO, "amvenc_avc probe start.\n"); + + encode_manager.this_pdev = pdev; +#ifdef CONFIG_CMA + encode_manager.check_cma = false; +#endif + encode_manager.reserve_mem.buf_start = 0; + encode_manager.reserve_mem.buf_size = 0; + encode_manager.use_reserve = false; + encode_manager.max_instance = 0; + encode_manager.reserve_buff = NULL; + + idx = of_reserved_mem_device_init(&pdev->dev); + if (idx != 0) { + enc_pr(LOG_DEBUG, + "amvenc_avc_probe -- reserved memory config fail.\n"); + } + + if (encode_manager.use_reserve == false) { +#ifndef CONFIG_CMA + enc_pr(LOG_ERROR, + "amvenc_avc memory is invaild, probe fail!\n"); + return -EFAULT; +#else + encode_manager.cma_pool_size = + (codec_mm_get_total_size() > (MIN_SIZE * 3)) ? + (MIN_SIZE * 3) : codec_mm_get_total_size(); + enc_pr(LOG_DEBUG, + "amvenc_avc - cma memory pool size: %d MB\n", + (u32)encode_manager.cma_pool_size / SZ_1M); +#endif + } + + res_irq = platform_get_irq(pdev, 0); + if (res_irq < 0) { + enc_pr(LOG_ERROR, "[%s] get irq error!", __func__); + return -EINVAL; + } + + encode_manager.irq_num = res_irq; + if (encode_wq_init()) { + kfree(encode_manager.reserve_buff); + encode_manager.reserve_buff = NULL; + enc_pr(LOG_ERROR, "encode work queue init error.\n"); + return -EFAULT; + } + + r = init_avc_device(); + enc_pr(LOG_INFO, "amvenc_avc probe end.\n"); + return r; +} + +static s32 amvenc_avc_remove(struct platform_device *pdev) +{ + kfree(encode_manager.reserve_buff); + encode_manager.reserve_buff = NULL; + if (encode_wq_uninit()) + enc_pr(LOG_ERROR, "encode work queue uninit error.\n"); + uninit_avc_device(); + enc_pr(LOG_INFO, "amvenc_avc remove.\n"); + return 0; +} + +static const struct of_device_id amlogic_avcenc_dt_match[] = { + { + .compatible = "amlogic, amvenc_avc", + }, + {}, +}; + +static struct platform_driver amvenc_avc_driver = { + .probe = amvenc_avc_probe, + .remove = amvenc_avc_remove, + .driver = { + .name = DRIVER_NAME, + .of_match_table = amlogic_avcenc_dt_match, + } +}; + +static struct codec_profile_t amvenc_avc_profile = { + .name = "avc", + .profile = "" +}; + +static s32 __init amvenc_avc_driver_init_module(void) +{ + enc_pr(LOG_INFO, "amvenc_avc module init\n"); + + if (platform_driver_register(&amvenc_avc_driver)) { + enc_pr(LOG_ERROR, + "failed to register amvenc_avc driver\n"); + return -ENODEV; + } + vcodec_profile_register(&amvenc_avc_profile); + return 0; +} + +static void __exit amvenc_avc_driver_remove_module(void) +{ + enc_pr(LOG_INFO, "amvenc_avc module remove.\n"); + + platform_driver_unregister(&amvenc_avc_driver); +} + +static const struct reserved_mem_ops rmem_avc_ops = { + .device_init = avc_mem_device_init, +}; + +static s32 __init avc_mem_setup(struct reserved_mem *rmem) +{ + rmem->ops = &rmem_avc_ops; + enc_pr(LOG_DEBUG, "amvenc_avc reserved mem setup.\n"); + return 0; +} + +module_param(fixed_slice_cfg, uint, 0664); +MODULE_PARM_DESC(fixed_slice_cfg, "\n fixed_slice_cfg\n"); + +module_param(clock_level, uint, 0664); +MODULE_PARM_DESC(clock_level, "\n clock_level\n"); + +module_param(encode_print_level, uint, 0664); +MODULE_PARM_DESC(encode_print_level, "\n encode_print_level\n"); + +module_param(no_timeout, uint, 0664); +MODULE_PARM_DESC(no_timeout, "\n no_timeout flag for process request\n"); + +module_param(nr_mode, int, 0664); +MODULE_PARM_DESC(nr_mode, "\n nr_mode option\n"); + +module_param(qp_table_debug, uint, 0664); +MODULE_PARM_DESC(qp_table_debug, "\n print qp table\n"); + +#ifdef MORE_MODULE_PARAM +module_param(me_mv_merge_ctl, uint, 0664); +MODULE_PARM_DESC(me_mv_merge_ctl, "\n me_mv_merge_ctl\n"); + +module_param(me_step0_close_mv, uint, 0664); +MODULE_PARM_DESC(me_step0_close_mv, "\n me_step0_close_mv\n"); + +module_param(me_f_skip_sad, uint, 0664); +MODULE_PARM_DESC(me_f_skip_sad, "\n me_f_skip_sad\n"); + +module_param(me_f_skip_weight, uint, 0664); +MODULE_PARM_DESC(me_f_skip_weight, "\n me_f_skip_weight\n"); + +module_param(me_mv_weight_01, uint, 0664); +MODULE_PARM_DESC(me_mv_weight_01, "\n me_mv_weight_01\n"); + +module_param(me_mv_weight_23, uint, 0664); +MODULE_PARM_DESC(me_mv_weight_23, "\n me_mv_weight_23\n"); + +module_param(me_sad_range_inc, uint, 0664); +MODULE_PARM_DESC(me_sad_range_inc, "\n me_sad_range_inc\n"); + +module_param(me_sad_enough_01, uint, 0664); +MODULE_PARM_DESC(me_sad_enough_01, "\n me_sad_enough_01\n"); + +module_param(me_sad_enough_23, uint, 0664); +MODULE_PARM_DESC(me_sad_enough_23, "\n me_sad_enough_23\n"); + +module_param(y_tnr_mc_en, uint, 0664); +MODULE_PARM_DESC(y_tnr_mc_en, "\n y_tnr_mc_en option\n"); +module_param(y_tnr_txt_mode, uint, 0664); +MODULE_PARM_DESC(y_tnr_txt_mode, "\n y_tnr_txt_mode option\n"); +module_param(y_tnr_mot_sad_margin, uint, 0664); +MODULE_PARM_DESC(y_tnr_mot_sad_margin, "\n y_tnr_mot_sad_margin option\n"); +module_param(y_tnr_mot_cortxt_rate, uint, 0664); +MODULE_PARM_DESC(y_tnr_mot_cortxt_rate, "\n y_tnr_mot_cortxt_rate option\n"); +module_param(y_tnr_mot_distxt_ofst, uint, 0664); +MODULE_PARM_DESC(y_tnr_mot_distxt_ofst, "\n y_tnr_mot_distxt_ofst option\n"); +module_param(y_tnr_mot_distxt_rate, uint, 0664); +MODULE_PARM_DESC(y_tnr_mot_distxt_rate, "\n y_tnr_mot_distxt_rate option\n"); +module_param(y_tnr_mot_dismot_ofst, uint, 0664); +MODULE_PARM_DESC(y_tnr_mot_dismot_ofst, "\n y_tnr_mot_dismot_ofst option\n"); +module_param(y_tnr_mot_frcsad_lock, uint, 0664); +MODULE_PARM_DESC(y_tnr_mot_frcsad_lock, "\n y_tnr_mot_frcsad_lock option\n"); +module_param(y_tnr_mot2alp_frc_gain, uint, 0664); +MODULE_PARM_DESC(y_tnr_mot2alp_frc_gain, "\n y_tnr_mot2alp_frc_gain option\n"); +module_param(y_tnr_mot2alp_nrm_gain, uint, 0664); +MODULE_PARM_DESC(y_tnr_mot2alp_nrm_gain, "\n y_tnr_mot2alp_nrm_gain option\n"); +module_param(y_tnr_mot2alp_dis_gain, uint, 0664); +MODULE_PARM_DESC(y_tnr_mot2alp_dis_gain, "\n y_tnr_mot2alp_dis_gain option\n"); +module_param(y_tnr_mot2alp_dis_ofst, uint, 0664); +MODULE_PARM_DESC(y_tnr_mot2alp_dis_ofst, "\n y_tnr_mot2alp_dis_ofst option\n"); +module_param(y_tnr_alpha_min, uint, 0664); +MODULE_PARM_DESC(y_tnr_alpha_min, "\n y_tnr_alpha_min option\n"); +module_param(y_tnr_alpha_max, uint, 0664); +MODULE_PARM_DESC(y_tnr_alpha_max, "\n y_tnr_alpha_max option\n"); +module_param(y_tnr_deghost_os, uint, 0664); +MODULE_PARM_DESC(y_tnr_deghost_os, "\n y_tnr_deghost_os option\n"); + +module_param(c_tnr_mc_en, uint, 0664); +MODULE_PARM_DESC(c_tnr_mc_en, "\n c_tnr_mc_en option\n"); +module_param(c_tnr_txt_mode, uint, 0664); +MODULE_PARM_DESC(c_tnr_txt_mode, "\n c_tnr_txt_mode option\n"); +module_param(c_tnr_mot_sad_margin, uint, 0664); +MODULE_PARM_DESC(c_tnr_mot_sad_margin, "\n c_tnr_mot_sad_margin option\n"); +module_param(c_tnr_mot_cortxt_rate, uint, 0664); +MODULE_PARM_DESC(c_tnr_mot_cortxt_rate, "\n c_tnr_mot_cortxt_rate option\n"); +module_param(c_tnr_mot_distxt_ofst, uint, 0664); +MODULE_PARM_DESC(c_tnr_mot_distxt_ofst, "\n c_tnr_mot_distxt_ofst option\n"); +module_param(c_tnr_mot_distxt_rate, uint, 0664); +MODULE_PARM_DESC(c_tnr_mot_distxt_rate, "\n c_tnr_mot_distxt_rate option\n"); +module_param(c_tnr_mot_dismot_ofst, uint, 0664); +MODULE_PARM_DESC(c_tnr_mot_dismot_ofst, "\n c_tnr_mot_dismot_ofst option\n"); +module_param(c_tnr_mot_frcsad_lock, uint, 0664); +MODULE_PARM_DESC(c_tnr_mot_frcsad_lock, "\n c_tnr_mot_frcsad_lock option\n"); +module_param(c_tnr_mot2alp_frc_gain, uint, 0664); +MODULE_PARM_DESC(c_tnr_mot2alp_frc_gain, "\n c_tnr_mot2alp_frc_gain option\n"); +module_param(c_tnr_mot2alp_nrm_gain, uint, 0664); +MODULE_PARM_DESC(c_tnr_mot2alp_nrm_gain, "\n c_tnr_mot2alp_nrm_gain option\n"); +module_param(c_tnr_mot2alp_dis_gain, uint, 0664); +MODULE_PARM_DESC(c_tnr_mot2alp_dis_gain, "\n c_tnr_mot2alp_dis_gain option\n"); +module_param(c_tnr_mot2alp_dis_ofst, uint, 0664); +MODULE_PARM_DESC(c_tnr_mot2alp_dis_ofst, "\n c_tnr_mot2alp_dis_ofst option\n"); +module_param(c_tnr_alpha_min, uint, 0664); +MODULE_PARM_DESC(c_tnr_alpha_min, "\n c_tnr_alpha_min option\n"); +module_param(c_tnr_alpha_max, uint, 0664); +MODULE_PARM_DESC(c_tnr_alpha_max, "\n c_tnr_alpha_max option\n"); +module_param(c_tnr_deghost_os, uint, 0664); +MODULE_PARM_DESC(c_tnr_deghost_os, "\n c_tnr_deghost_os option\n"); + +module_param(y_snr_err_norm, uint, 0664); +MODULE_PARM_DESC(y_snr_err_norm, "\n y_snr_err_norm option\n"); +module_param(y_snr_gau_bld_core, uint, 0664); +MODULE_PARM_DESC(y_snr_gau_bld_core, "\n y_snr_gau_bld_core option\n"); +module_param(y_snr_gau_bld_ofst, int, 0664); +MODULE_PARM_DESC(y_snr_gau_bld_ofst, "\n y_snr_gau_bld_ofst option\n"); +module_param(y_snr_gau_bld_rate, uint, 0664); +MODULE_PARM_DESC(y_snr_gau_bld_rate, "\n y_snr_gau_bld_rate option\n"); +module_param(y_snr_gau_alp0_min, uint, 0664); +MODULE_PARM_DESC(y_snr_gau_alp0_min, "\n y_snr_gau_alp0_min option\n"); +module_param(y_snr_gau_alp0_max, uint, 0664); +MODULE_PARM_DESC(y_snr_gau_alp0_max, "\n y_snr_gau_alp0_max option\n"); +module_param(y_bld_beta2alp_rate, uint, 0664); +MODULE_PARM_DESC(y_bld_beta2alp_rate, "\n y_bld_beta2alp_rate option\n"); +module_param(y_bld_beta_min, uint, 0664); +MODULE_PARM_DESC(y_bld_beta_min, "\n y_bld_beta_min option\n"); +module_param(y_bld_beta_max, uint, 0664); +MODULE_PARM_DESC(y_bld_beta_max, "\n y_bld_beta_max option\n"); + +module_param(c_snr_err_norm, uint, 0664); +MODULE_PARM_DESC(c_snr_err_norm, "\n c_snr_err_norm option\n"); +module_param(c_snr_gau_bld_core, uint, 0664); +MODULE_PARM_DESC(c_snr_gau_bld_core, "\n c_snr_gau_bld_core option\n"); +module_param(c_snr_gau_bld_ofst, int, 0664); +MODULE_PARM_DESC(c_snr_gau_bld_ofst, "\n c_snr_gau_bld_ofst option\n"); +module_param(c_snr_gau_bld_rate, uint, 0664); +MODULE_PARM_DESC(c_snr_gau_bld_rate, "\n c_snr_gau_bld_rate option\n"); +module_param(c_snr_gau_alp0_min, uint, 0664); +MODULE_PARM_DESC(c_snr_gau_alp0_min, "\n c_snr_gau_alp0_min option\n"); +module_param(c_snr_gau_alp0_max, uint, 0664); +MODULE_PARM_DESC(c_snr_gau_alp0_max, "\n c_snr_gau_alp0_max option\n"); +module_param(c_bld_beta2alp_rate, uint, 0664); +MODULE_PARM_DESC(c_bld_beta2alp_rate, "\n c_bld_beta2alp_rate option\n"); +module_param(c_bld_beta_min, uint, 0664); +MODULE_PARM_DESC(c_bld_beta_min, "\n c_bld_beta_min option\n"); +module_param(c_bld_beta_max, uint, 0664); +MODULE_PARM_DESC(c_bld_beta_max, "\n c_bld_beta_max option\n"); +#endif + +module_init(amvenc_avc_driver_init_module); +module_exit(amvenc_avc_driver_remove_module); +RESERVEDMEM_OF_DECLARE(amvenc_avc, "amlogic, amvenc-memory", avc_mem_setup); + +MODULE_DESCRIPTION("AMLOGIC AVC Video Encoder Driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("simon.zheng "); diff --git a/drivers/amlogic/media_modules/frame_sink/encoder/h264/encoder.h b/drivers/amlogic/media_modules/frame_sink/encoder/h264/encoder.h new file mode 100644 index 000000000000..1c3ade4427d7 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_sink/encoder/h264/encoder.h @@ -0,0 +1,468 @@ +/* + * drivers/amlogic/amports/encoder.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __H264_H__ +#define __H264_H__ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_AMLOGIC_MEDIA_GE2D +#include +#endif + +#define AMVENC_DEVINFO_M8 "AML-M8" +#define AMVENC_DEVINFO_G9 "AML-G9" +#define AMVENC_DEVINFO_GXBB "AML-GXBB" +#define AMVENC_DEVINFO_GXTVBB "AML-GXTVBB" +#define AMVENC_DEVINFO_GXL "AML-GXL" + +#define HCODEC_IRQ_MBOX_CLR HCODEC_ASSIST_MBOX2_CLR_REG +#define HCODEC_IRQ_MBOX_MASK HCODEC_ASSIST_MBOX2_MASK + +/* M8: 2550/10 = 255M GX: 2000/10 = 200M */ +#define HDEC_L0() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ + (2 << 25) | (1 << 16) | (1 << 24) | \ + (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) +/* M8: 2550/8 = 319M GX: 2000/8 = 250M */ +#define HDEC_L1() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ + (0 << 25) | (1 << 16) | (1 << 24) | \ + (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) +/* M8: 2550/7 = 364M GX: 2000/7 = 285M */ +#define HDEC_L2() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ + (3 << 25) | (0 << 16) | (1 << 24) | \ + (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) +/* M8: 2550/6 = 425M GX: 2000/6 = 333M */ +#define HDEC_L3() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ + (1 << 25) | (1 << 16) | (1 << 24) | \ + (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) +/* M8: 2550/5 = 510M GX: 2000/5 = 400M */ +#define HDEC_L4() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ + (2 << 25) | (0 << 16) | (1 << 24) | \ + (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) +/* M8: 2550/4 = 638M GX: 2000/4 = 500M */ +#define HDEC_L5() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ + (0 << 25) | (0 << 16) | (1 << 24) | \ + (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) +/* M8: 2550/3 = 850M GX: 2000/3 = 667M */ +#define HDEC_L6() WRITE_HHI_REG(HHI_VDEC_CLK_CNTL, \ + (1 << 25) | (0 << 16) | (1 << 24) | \ + (0xffff & READ_HHI_REG(HHI_VDEC_CLK_CNTL))) + +#define hvdec_clock_enable(level) \ + do { \ + if (level == 0) \ + HDEC_L0(); \ + else if (level == 1) \ + HDEC_L1(); \ + else if (level == 2) \ + HDEC_L2(); \ + else if (level == 3) \ + HDEC_L3(); \ + else if (level == 4) \ + HDEC_L4(); \ + else if (level == 5) \ + HDEC_L5(); \ + else if (level == 6) \ + HDEC_L6(); \ + WRITE_VREG_BITS(DOS_GCLK_EN0, 0x7fff, 12, 15); \ + } while (0) + +#define hvdec_clock_disable() \ + do { \ + WRITE_VREG_BITS(DOS_GCLK_EN0, 0, 12, 15); \ + WRITE_HHI_REG_BITS(HHI_VDEC_CLK_CNTL, 0, 24, 1); \ + } while (0) + +#define LOG_ALL 0 +#define LOG_INFO 1 +#define LOG_DEBUG 2 +#define LOG_ERROR 3 + +#define enc_pr(level, x...) \ + do { \ + if (level >= encode_print_level) \ + printk(x); \ + } while (0) + +#define AMVENC_AVC_IOC_MAGIC 'E' + +#define AMVENC_AVC_IOC_GET_DEVINFO _IOW(AMVENC_AVC_IOC_MAGIC, 0xf0, u32) +#define AMVENC_AVC_IOC_MAX_INSTANCE _IOW(AMVENC_AVC_IOC_MAGIC, 0xf1, u32) + +#define AMVENC_AVC_IOC_GET_ADDR _IOW(AMVENC_AVC_IOC_MAGIC, 0x00, u32) +#define AMVENC_AVC_IOC_INPUT_UPDATE _IOW(AMVENC_AVC_IOC_MAGIC, 0x01, u32) +#define AMVENC_AVC_IOC_NEW_CMD _IOW(AMVENC_AVC_IOC_MAGIC, 0x02, u32) +#define AMVENC_AVC_IOC_GET_STAGE _IOW(AMVENC_AVC_IOC_MAGIC, 0x03, u32) +#define AMVENC_AVC_IOC_GET_OUTPUT_SIZE _IOW(AMVENC_AVC_IOC_MAGIC, 0x04, u32) +#define AMVENC_AVC_IOC_CONFIG_INIT _IOW(AMVENC_AVC_IOC_MAGIC, 0x05, u32) +#define AMVENC_AVC_IOC_FLUSH_CACHE _IOW(AMVENC_AVC_IOC_MAGIC, 0x06, u32) +#define AMVENC_AVC_IOC_FLUSH_DMA _IOW(AMVENC_AVC_IOC_MAGIC, 0x07, u32) +#define AMVENC_AVC_IOC_GET_BUFFINFO _IOW(AMVENC_AVC_IOC_MAGIC, 0x08, u32) +#define AMVENC_AVC_IOC_SUBMIT _IOW(AMVENC_AVC_IOC_MAGIC, 0x09, u32) +#define AMVENC_AVC_IOC_READ_CANVAS _IOW(AMVENC_AVC_IOC_MAGIC, 0x0a, u32) + + +#define IE_PIPPELINE_BLOCK_SHIFT 0 +#define IE_PIPPELINE_BLOCK_MASK 0x1f +#define ME_PIXEL_MODE_SHIFT 5 +#define ME_PIXEL_MODE_MASK 0x3 + +enum amvenc_mem_type_e { + LOCAL_BUFF = 0, + CANVAS_BUFF, + PHYSICAL_BUFF, + MAX_BUFF_TYPE +}; + +enum amvenc_frame_fmt_e { + FMT_YUV422_SINGLE = 0, + FMT_YUV444_SINGLE, + FMT_NV21, + FMT_NV12, + FMT_YUV420, + FMT_YUV444_PLANE, + FMT_RGB888, + FMT_RGB888_PLANE, + FMT_RGB565, + FMT_RGBA8888, + FMT_YUV422_12BIT, + FMT_YUV444_10BIT, + FMT_YUV422_10BIT, + MAX_FRAME_FMT +}; + +#define MAX_ENCODE_REQUEST 8 /* 64 */ + +#define MAX_ENCODE_INSTANCE 8 /* 64 */ + +#define ENCODE_PROCESS_QUEUE_START 0 +#define ENCODE_PROCESS_QUEUE_STOP 1 + +#define AMVENC_FLUSH_FLAG_INPUT 0x1 +#define AMVENC_FLUSH_FLAG_OUTPUT 0x2 +#define AMVENC_FLUSH_FLAG_REFERENCE 0x4 +#define AMVENC_FLUSH_FLAG_INTRA_INFO 0x8 +#define AMVENC_FLUSH_FLAG_INTER_INFO 0x10 +#define AMVENC_FLUSH_FLAG_QP 0x20 +#define AMVENC_FLUSH_FLAG_DUMP 0x40 +#define AMVENC_FLUSH_FLAG_CBR 0x80 + +#define ENCODER_BUFFER_INPUT 0 +#define ENCODER_BUFFER_REF0 1 +#define ENCODER_BUFFER_REF1 2 +#define ENCODER_BUFFER_OUTPUT 3 +#define ENCODER_BUFFER_INTER_INFO 4 +#define ENCODER_BUFFER_INTRA_INFO 5 +#define ENCODER_BUFFER_QP 6 +#define ENCODER_BUFFER_DUMP 7 +#define ENCODER_BUFFER_CBR 8 + +struct encode_wq_s; + +struct encode_request_s { + u32 quant; + u32 cmd; + u32 ucode_mode; + + u32 src; + + u32 framesize; + + u32 me_weight; + u32 i4_weight; + u32 i16_weight; + + u32 crop_top; + u32 crop_bottom; + u32 crop_left; + u32 crop_right; + u32 src_w; + u32 src_h; + u32 scale_enable; + + u32 nr_mode; + u32 flush_flag; + u32 timeout; + enum amvenc_mem_type_e type; + enum amvenc_frame_fmt_e fmt; + struct encode_wq_s *parent; +}; + +struct encode_queue_item_s { + struct list_head list; + struct encode_request_s request; +}; + +struct Buff_s { + u32 buf_start; + u32 buf_size; + bool used; +}; + +struct BuffInfo_s { + u32 lev_id; + u32 min_buffsize; + u32 max_width; + u32 max_height; + struct Buff_s dct; + struct Buff_s dec0_y; + struct Buff_s dec0_uv; + struct Buff_s dec1_y; + struct Buff_s dec1_uv; + struct Buff_s assit; + struct Buff_s bitstream; + struct Buff_s scale_buff; + struct Buff_s dump_info; + struct Buff_s cbr_info; +}; + +struct encode_meminfo_s { + u32 buf_start; + u32 buf_size; + + u32 BitstreamStart; + u32 BitstreamEnd; + + /*input buffer define*/ + u32 dct_buff_start_addr; + u32 dct_buff_end_addr; + + /*microcode assitant buffer*/ + u32 assit_buffer_offset; + + u32 scaler_buff_start_addr; + + u32 dump_info_ddr_start_addr; + u32 dump_info_ddr_size; + + u32 cbr_info_ddr_start_addr; + u32 cbr_info_ddr_size; + + s32 dblk_buf_canvas; + s32 ref_buf_canvas; + struct BuffInfo_s bufspec; +#ifdef CONFIG_CMA + struct page *venc_pages; +#endif +}; + +struct encode_picinfo_s { + u32 encoder_width; + u32 encoder_height; + + u32 rows_per_slice; + + u32 idr_pic_id; /* need reset as 0 for IDR */ + u32 frame_number; /* need plus each frame */ + /* need reset as 0 for IDR and plus 2 for NON-IDR */ + u32 pic_order_cnt_lsb; + + u32 log2_max_pic_order_cnt_lsb; + u32 log2_max_frame_num; + u32 init_qppicture; +}; + +struct encode_cbr_s { + u16 block_w; + u16 block_h; + u16 long_th; + u8 start_tbl_id; + u8 short_shift; + u8 long_mb_num; +}; + +struct encode_wq_s { + struct list_head list; + + /* dev info */ + u32 ucode_index; + u32 hw_status; + u32 output_size; + + u32 sps_size; + u32 pps_size; + + u32 me_weight; + u32 i4_weight; + u32 i16_weight; + + u32 quant_tbl_i4[8]; + u32 quant_tbl_i16[8]; + u32 quant_tbl_me[8]; + + struct encode_meminfo_s mem; + struct encode_picinfo_s pic; + struct encode_request_s request; + struct encode_cbr_s cbr_info; + atomic_t request_ready; + wait_queue_head_t request_complete; +}; + +struct encode_event_s { + wait_queue_head_t hw_complete; + struct completion process_complete; + spinlock_t sem_lock; /* for queue switch and create destroy queue. */ + struct completion request_in_com; +}; + +struct encode_manager_s { + struct list_head wq; + struct list_head process_queue; + struct list_head free_queue; + + u32 encode_hw_status; + u32 process_queue_state; + s32 irq_num; + u32 wq_count; + u32 ucode_index; + u32 max_instance; +#ifdef CONFIG_AMLOGIC_MEDIA_GE2D + struct ge2d_context_s *context; +#endif + bool irq_requested; + bool need_reset; + bool process_irq; + bool inited; /* power on encode */ + bool remove_flag; /* remove wq; */ + bool uninit_flag; /* power off encode */ + bool use_reserve; + +#ifdef CONFIG_CMA + bool check_cma; + ulong cma_pool_size; +#endif + struct platform_device *this_pdev; + struct Buff_s *reserve_buff; + struct encode_wq_s *current_wq; + struct encode_wq_s *last_wq; + struct encode_queue_item_s *current_item; + struct task_struct *encode_thread; + struct Buff_s reserve_mem; + struct encode_event_s event; + struct tasklet_struct encode_tasklet; +}; + +extern s32 encode_wq_add_request(struct encode_wq_s *wq); +extern struct encode_wq_s *create_encode_work_queue(void); +extern s32 destroy_encode_work_queue(struct encode_wq_s *encode_work_queue); + +/******************************************** + * AV Scratch Register Re-Define + ****************************************** * + */ +#define ENCODER_STATUS HCODEC_HENC_SCRATCH_0 +#define MEM_OFFSET_REG HCODEC_HENC_SCRATCH_1 +#define DEBUG_REG HCODEC_HENC_SCRATCH_2 +#define IDR_PIC_ID HCODEC_HENC_SCRATCH_5 +#define FRAME_NUMBER HCODEC_HENC_SCRATCH_6 +#define PIC_ORDER_CNT_LSB HCODEC_HENC_SCRATCH_7 +#define LOG2_MAX_PIC_ORDER_CNT_LSB HCODEC_HENC_SCRATCH_8 +#define LOG2_MAX_FRAME_NUM HCODEC_HENC_SCRATCH_9 +#define ANC0_BUFFER_ID HCODEC_HENC_SCRATCH_A +#define QPPICTURE HCODEC_HENC_SCRATCH_B + +#define IE_ME_MB_TYPE HCODEC_HENC_SCRATCH_D + +/* bit 0-4, IE_PIPPELINE_BLOCK + * bit 5 me half pixel in m8 + * disable i4x4 in gxbb + * bit 6 me step2 sub pixel in m8 + * disable i16x16 in gxbb + */ +#define IE_ME_MODE HCODEC_HENC_SCRATCH_E +#define IE_REF_SEL HCODEC_HENC_SCRATCH_F + +/* [31:0] NUM_ROWS_PER_SLICE_P */ +/* [15:0] NUM_ROWS_PER_SLICE_I */ +#define FIXED_SLICE_CFG HCODEC_HENC_SCRATCH_L + +/* For GX */ +#define INFO_DUMP_START_ADDR HCODEC_HENC_SCRATCH_I + +/* For CBR */ +#define H264_ENC_CBR_TABLE_ADDR HCODEC_HENC_SCRATCH_3 +#define H264_ENC_CBR_MB_SIZE_ADDR HCODEC_HENC_SCRATCH_4 +/* Bytes(Float) * 256 */ +#define H264_ENC_CBR_CTL HCODEC_HENC_SCRATCH_G +/* [31:28] : init qp table idx */ +/* [27:24] : short_term adjust shift */ +/* [23:16] : Long_term MB_Number between adjust, */ +/* [15:0] Long_term adjust threshold(Bytes) */ +#define H264_ENC_CBR_TARGET_SIZE HCODEC_HENC_SCRATCH_H +/* Bytes(Float) * 256 */ +#define H264_ENC_CBR_PREV_BYTES HCODEC_HENC_SCRATCH_J +#define H264_ENC_CBR_REGION_SIZE HCODEC_HENC_SCRATCH_J + +/* --------------------------------------------------- */ +/* ENCODER_STATUS define */ +/* --------------------------------------------------- */ +#define ENCODER_IDLE 0 +#define ENCODER_SEQUENCE 1 +#define ENCODER_PICTURE 2 +#define ENCODER_IDR 3 +#define ENCODER_NON_IDR 4 +#define ENCODER_MB_HEADER 5 +#define ENCODER_MB_DATA 6 + +#define ENCODER_SEQUENCE_DONE 7 +#define ENCODER_PICTURE_DONE 8 +#define ENCODER_IDR_DONE 9 +#define ENCODER_NON_IDR_DONE 10 +#define ENCODER_MB_HEADER_DONE 11 +#define ENCODER_MB_DATA_DONE 12 + +#define ENCODER_NON_IDR_INTRA 13 +#define ENCODER_NON_IDR_INTER 14 + +#define ENCODER_ERROR 0xff + +/******************************************** + * defines for H.264 mb_type + ******************************************* + */ +#define HENC_MB_Type_PBSKIP 0x0 +#define HENC_MB_Type_PSKIP 0x0 +#define HENC_MB_Type_BSKIP_DIRECT 0x0 +#define HENC_MB_Type_P16x16 0x1 +#define HENC_MB_Type_P16x8 0x2 +#define HENC_MB_Type_P8x16 0x3 +#define HENC_MB_Type_SMB8x8 0x4 +#define HENC_MB_Type_SMB8x4 0x5 +#define HENC_MB_Type_SMB4x8 0x6 +#define HENC_MB_Type_SMB4x4 0x7 +#define HENC_MB_Type_P8x8 0x8 +#define HENC_MB_Type_I4MB 0x9 +#define HENC_MB_Type_I16MB 0xa +#define HENC_MB_Type_IBLOCK 0xb +#define HENC_MB_Type_SI4MB 0xc +#define HENC_MB_Type_I8MB 0xd +#define HENC_MB_Type_IPCM 0xe +#define HENC_MB_Type_AUTO 0xf + +#define HENC_MB_CBP_AUTO 0xff +#define HENC_SKIP_RUN_AUTO 0xffff + + +extern bool amvenc_avc_on(void); +#endif diff --git a/drivers/amlogic/media_modules/frame_sink/encoder/h265/Makefile b/drivers/amlogic/media_modules/frame_sink/encoder/h265/Makefile new file mode 100644 index 000000000000..e7414bfb8614 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_sink/encoder/h265/Makefile @@ -0,0 +1 @@ +obj-m += vpu.o diff --git a/drivers/amlogic/media_modules/frame_sink/encoder/h265/vmm.h b/drivers/amlogic/media_modules/frame_sink/encoder/h265/vmm.h new file mode 100644 index 000000000000..3c9c6d8734f8 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_sink/encoder/h265/vmm.h @@ -0,0 +1,665 @@ +/* + * vmm.h + * + * memory allocator for VPU + * + * Copyright (C) 2006 - 2013 CHIPS&MEDIA INC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __CNM_VIDEO_MEMORY_MANAGEMENT_H__ +#define __CNM_VIDEO_MEMORY_MANAGEMENT_H__ + +#define VMEM_PAGE_SIZE (16 * 1024) +#define MAKE_KEY(_a, _b) (((vmem_key_t)_a) << 32 | _b) +#define KEY_TO_VALUE(_key) (_key >> 32) + +#define VMEM_P_ALLOC(_x) vmalloc(_x) +#define VMEM_P_FREE(_x) vfree(_x) + +#define VMEM_ASSERT \ + pr_info("VMEM_ASSERT at %s:%d\n", __FILE__, __LINE__) + + +#define VMEM_HEIGHT(_tree) (_tree == NULL ? -1 : _tree->height) + +#define MAX(_a, _b) (_a >= _b ? _a : _b) + +struct avl_node_t; +#define vmem_key_t unsigned long long + +struct vmem_info_t { + ulong total_pages; + ulong alloc_pages; + ulong free_pages; + ulong page_size; +}; + +struct page_t { + s32 pageno; + ulong addr; + s32 used; + s32 alloc_pages; + s32 first_pageno; +}; + +struct avl_node_t { + vmem_key_t key; + s32 height; + struct page_t *page; + struct avl_node_t *left; + struct avl_node_t *right; +}; + +struct video_mm_t { + struct avl_node_t *free_tree; + struct avl_node_t *alloc_tree; + struct page_t *page_list; + s32 num_pages; + ulong base_addr; + ulong mem_size; + s32 free_page_count; + s32 alloc_page_count; +}; + +enum rotation_dir_t { + LEFT, + RIGHT +}; + +struct avl_node_data_t { + s32 key; + struct page_t *page; +}; + +static struct avl_node_t *make_avl_node( + vmem_key_t key, + struct page_t *page) +{ + struct avl_node_t *node = + (struct avl_node_t *)VMEM_P_ALLOC(sizeof(struct avl_node_t)); + node->key = key; + node->page = page; + node->height = 0; + node->left = NULL; + node->right = NULL; + return node; +} + +static s32 get_balance_factor(struct avl_node_t *tree) +{ + s32 factor = 0; + + if (tree) + factor = VMEM_HEIGHT(tree->right) - VMEM_HEIGHT(tree->left); + return factor; +} + +/* + * Left Rotation + * + * A B + * \ / \ + * B => A C + * / \ \ + * D C D + * + */ +static struct avl_node_t *rotation_left(struct avl_node_t *tree) +{ + struct avl_node_t *rchild; + struct avl_node_t *lchild; + + if (tree == NULL) + return NULL; + + rchild = tree->right; + if (rchild == NULL) + return tree; + + lchild = rchild->left; + rchild->left = tree; + tree->right = lchild; + + tree->height = + MAX(VMEM_HEIGHT(tree->left), VMEM_HEIGHT(tree->right)) + 1; + rchild->height = + MAX(VMEM_HEIGHT(rchild->left), VMEM_HEIGHT(rchild->right)) + 1; + return rchild; +} + + +/* + * Reft Rotation + * + * A B + * \ / \ + * B => D A + * / \ / + * D C C + * + */ +static struct avl_node_t *rotation_right(struct avl_node_t *tree) +{ + struct avl_node_t *rchild; + struct avl_node_t *lchild; + + if (tree == NULL) + return NULL; + + lchild = tree->left; + if (lchild == NULL) + return NULL; + + rchild = lchild->right; + lchild->right = tree; + tree->left = rchild; + + tree->height = + MAX(VMEM_HEIGHT(tree->left), + VMEM_HEIGHT(tree->right)) + 1; + lchild->height = + MAX(VMEM_HEIGHT(lchild->left), + VMEM_HEIGHT(lchild->right)) + 1; + return lchild; +} + +static struct avl_node_t *do_balance(struct avl_node_t *tree) +{ + s32 bfactor = 0, child_bfactor; + + bfactor = get_balance_factor(tree); + if (bfactor >= 2) { + child_bfactor = get_balance_factor(tree->right); + if (child_bfactor == 1 || child_bfactor == 0) { + tree = rotation_left(tree); + } else if (child_bfactor == -1) { + tree->right = rotation_right(tree->right); + tree = rotation_left(tree); + } else { + pr_info( + "invalid balancing factor: %d\n", + child_bfactor); + VMEM_ASSERT; + return NULL; + } + } else if (bfactor <= -2) { + child_bfactor = get_balance_factor(tree->left); + if (child_bfactor == -1 || child_bfactor == 0) { + tree = rotation_right(tree); + } else if (child_bfactor == 1) { + tree->left = rotation_left(tree->left); + tree = rotation_right(tree); + } else { + pr_info( + "invalid balancing factor: %d\n", + child_bfactor); + VMEM_ASSERT; + return NULL; + } + } + return tree; +} + +static struct avl_node_t *unlink_end_node( + struct avl_node_t *tree, + s32 dir, + struct avl_node_t **found_node) +{ + struct avl_node_t *node; + *found_node = NULL; + + if (tree == NULL) + return NULL; + + if (dir == LEFT) { + if (tree->left == NULL) { + *found_node = tree; + return NULL; + } + } else { + if (tree->right == NULL) { + *found_node = tree; + return NULL; + } + } + + if (dir == LEFT) { + node = tree->left; + tree->left = unlink_end_node(tree->left, LEFT, found_node); + if (tree->left == NULL) { + tree->left = (*found_node)->right; + (*found_node)->left = NULL; + (*found_node)->right = NULL; + } + } else { + node = tree->right; + tree->right = unlink_end_node(tree->right, RIGHT, found_node); + if (tree->right == NULL) { + tree->right = (*found_node)->left; + (*found_node)->left = NULL; + (*found_node)->right = NULL; + } + } + tree->height = + MAX(VMEM_HEIGHT(tree->left), VMEM_HEIGHT(tree->right)) + 1; + return do_balance(tree); +} + + +static struct avl_node_t *avltree_insert( + struct avl_node_t *tree, + vmem_key_t key, + struct page_t *page) +{ + if (tree == NULL) { + tree = make_avl_node(key, page); + } else { + if (key >= tree->key) + tree->right = + avltree_insert(tree->right, key, page); + else + tree->left = + avltree_insert(tree->left, key, page); + } + tree = do_balance(tree); + tree->height = + MAX(VMEM_HEIGHT(tree->left), VMEM_HEIGHT(tree->right)) + 1; + return tree; +} + +static struct avl_node_t *do_unlink(struct avl_node_t *tree) +{ + struct avl_node_t *node; + struct avl_node_t *end_node; + + node = unlink_end_node(tree->right, LEFT, &end_node); + if (node) { + tree->right = node; + } else { + node = + unlink_end_node(tree->left, RIGHT, &end_node); + if (node) + tree->left = node; + } + + if (node == NULL) { + node = tree->right ? tree->right : tree->left; + end_node = node; + } + + if (end_node) { + end_node->left = + (tree->left != end_node) ? + tree->left : end_node->left; + end_node->right = + (tree->right != end_node) ? + tree->right : end_node->right; + end_node->height = + MAX(VMEM_HEIGHT(end_node->left), + VMEM_HEIGHT(end_node->right)) + 1; + } + tree = end_node; + return tree; +} + +static struct avl_node_t *avltree_remove( + struct avl_node_t *tree, + struct avl_node_t **found_node, + vmem_key_t key) +{ + *found_node = NULL; + if (tree == NULL) { + pr_info("failed to find key %d\n", (s32)key); + return NULL; + } + + if (key == tree->key) { + *found_node = tree; + tree = do_unlink(tree); + } else if (key > tree->key) { + tree->right = + avltree_remove(tree->right, found_node, key); + } else { + tree->left = + avltree_remove(tree->left, found_node, key); + } + + if (tree) + tree->height = + MAX(VMEM_HEIGHT(tree->left), + VMEM_HEIGHT(tree->right)) + 1; + + tree = do_balance(tree); + return tree; +} + +void avltree_free(struct avl_node_t *tree) +{ + if (tree == NULL) + return; + if (tree->left == NULL && tree->right == NULL) { + VMEM_P_FREE(tree); + return; + } + + avltree_free(tree->left); + tree->left = NULL; + avltree_free(tree->right); + tree->right = NULL; + VMEM_P_FREE(tree); +} + +static struct avl_node_t *remove_approx_value( + struct avl_node_t *tree, + struct avl_node_t **found, + vmem_key_t key) +{ + *found = NULL; + if (tree == NULL) + return NULL; + + if (key == tree->key) { + *found = tree; + tree = do_unlink(tree); + } else if (key > tree->key) { + tree->right = remove_approx_value(tree->right, found, key); + } else { + tree->left = remove_approx_value(tree->left, found, key); + if (*found == NULL) { + *found = tree; + tree = do_unlink(tree); + } + } + if (tree) + tree->height = + MAX(VMEM_HEIGHT(tree->left), + VMEM_HEIGHT(tree->right)) + 1; + tree = do_balance(tree); + return tree; +} + +static void set_blocks_free( + struct video_mm_t *mm, + s32 pageno, + s32 npages) +{ + s32 last_pageno = pageno + npages - 1; + s32 i; + struct page_t *page; + struct page_t *last_page; + + if (npages == 0) + VMEM_ASSERT; + + if (last_pageno >= mm->num_pages) { + pr_info( + "set_blocks_free: invalid last page number: %d\n", + last_pageno); + VMEM_ASSERT; + return; + } + + for (i = pageno; i <= last_pageno; i++) { + mm->page_list[i].used = 0; + mm->page_list[i].alloc_pages = 0; + mm->page_list[i].first_pageno = -1; + } + + page = &mm->page_list[pageno]; + page->alloc_pages = npages; + last_page = &mm->page_list[last_pageno]; + last_page->first_pageno = pageno; + mm->free_tree = + avltree_insert(mm->free_tree, MAKE_KEY(npages, pageno), page); +} + +static void set_blocks_alloc( + struct video_mm_t *mm, + s32 pageno, + s32 npages) +{ + s32 last_pageno = pageno + npages - 1; + s32 i; + struct page_t *page; + struct page_t *last_page; + + if (last_pageno >= mm->num_pages) { + pr_info( + "set_blocks_free: invalid last page number: %d\n", + last_pageno); + VMEM_ASSERT; + return; + } + + for (i = pageno; i <= last_pageno; i++) { + mm->page_list[i].used = 1; + mm->page_list[i].alloc_pages = 0; + mm->page_list[i].first_pageno = -1; + } + + page = &mm->page_list[pageno]; + page->alloc_pages = npages; + last_page = &mm->page_list[last_pageno]; + last_page->first_pageno = pageno; + mm->alloc_tree = + avltree_insert(mm->alloc_tree, MAKE_KEY(page->addr, 0), page); +} + + +s32 vmem_init(struct video_mm_t *mm, ulong addr, ulong size) +{ + s32 i; + + if (mm == NULL) + return -1; + + mm->base_addr = (addr + (VMEM_PAGE_SIZE - 1)) + & ~(VMEM_PAGE_SIZE - 1); + mm->mem_size = size & ~VMEM_PAGE_SIZE; + mm->num_pages = mm->mem_size / VMEM_PAGE_SIZE; + mm->free_tree = NULL; + mm->alloc_tree = NULL; + mm->free_page_count = mm->num_pages; + mm->alloc_page_count = 0; + mm->page_list = + (struct page_t *)VMEM_P_ALLOC( + mm->num_pages * sizeof(struct page_t)); + if (mm->page_list == NULL) { + pr_err("%s:%d failed to kmalloc(%ld)\n", + __func__, __LINE__, + mm->num_pages * sizeof(struct page_t)); + return -1; + } + + for (i = 0; i < mm->num_pages; i++) { + mm->page_list[i].pageno = i; + mm->page_list[i].addr = + mm->base_addr + i * VMEM_PAGE_SIZE; + mm->page_list[i].alloc_pages = 0; + mm->page_list[i].used = 0; + mm->page_list[i].first_pageno = -1; + } + set_blocks_free(mm, 0, mm->num_pages); + return 0; +} + +s32 vmem_exit(struct video_mm_t *mm) +{ + if (mm == NULL) { + pr_info("vmem_exit: invalid handle\n"); + return -1; + } + + if (mm->free_tree) + avltree_free(mm->free_tree); + if (mm->alloc_tree) + avltree_free(mm->alloc_tree); + + if (mm->page_list) { + VMEM_P_FREE(mm->page_list); + mm->page_list = NULL; + } + + mm->base_addr = 0; + mm->mem_size = 0; + mm->num_pages = 0; + mm->page_list = NULL; + mm->free_tree = NULL; + mm->alloc_tree = NULL; + mm->free_page_count = 0; + mm->alloc_page_count = 0; + return 0; +} + +ulong vmem_alloc(struct video_mm_t *mm, s32 size, ulong pid) +{ + struct avl_node_t *node; + struct page_t *free_page; + s32 npages, free_size; + s32 alloc_pageno; + ulong ptr; + + if (mm == NULL) { + pr_info("vmem_alloc: invalid handle\n"); + return -1; + } + + if (size <= 0) + return -1; + + npages = (size + VMEM_PAGE_SIZE - 1) / VMEM_PAGE_SIZE; + mm->free_tree = remove_approx_value(mm->free_tree, + &node, MAKE_KEY(npages, 0)); + + if (node == NULL) + return -1; + + free_page = node->page; + free_size = KEY_TO_VALUE(node->key); + alloc_pageno = free_page->pageno; + set_blocks_alloc(mm, alloc_pageno, npages); + if (npages != free_size) { + s32 free_pageno = alloc_pageno + npages; + + set_blocks_free(mm, free_pageno, (free_size-npages)); + } + VMEM_P_FREE(node); + + ptr = mm->page_list[alloc_pageno].addr; + mm->alloc_page_count += npages; + mm->free_page_count -= npages; + return ptr; +} + +s32 vmem_free(struct video_mm_t *mm, ulong ptr, ulong pid) +{ + ulong addr; + struct avl_node_t *found; + struct page_t *page; + s32 pageno, prev_free_pageno, next_free_pageno; + s32 prev_size, next_size; + s32 merge_page_no, merge_page_size, free_page_size; + + if (mm == NULL) { + pr_info("vmem_free: invalid handle\n"); + return -1; + } + + addr = ptr; + mm->alloc_tree = avltree_remove(mm->alloc_tree, &found, + MAKE_KEY(addr, 0)); + + if (found == NULL) { + pr_info("vmem_free: 0x%08x not found\n", (s32)addr); + VMEM_ASSERT; + return -1; + } + + /* find previous free block */ + page = found->page; + pageno = page->pageno; + free_page_size = page->alloc_pages; + prev_free_pageno = pageno - 1; + prev_size = -1; + if (prev_free_pageno >= 0) { + if (mm->page_list[prev_free_pageno].used == 0) { + prev_free_pageno = + mm->page_list[prev_free_pageno].first_pageno; + prev_size = + mm->page_list[prev_free_pageno].alloc_pages; + } + } + + /* find next free block */ + next_free_pageno = pageno + page->alloc_pages; + next_free_pageno = + (next_free_pageno == mm->num_pages) ? -1 : next_free_pageno; + next_size = -1; + if (next_free_pageno >= 0) { + if (mm->page_list[next_free_pageno].used == 0) { + next_size = + mm->page_list[next_free_pageno].alloc_pages; + } + } + VMEM_P_FREE(found); + + /* merge */ + merge_page_no = page->pageno; + merge_page_size = page->alloc_pages; + if (prev_size >= 0) { + mm->free_tree = avltree_remove(mm->free_tree, &found, + MAKE_KEY(prev_size, prev_free_pageno)); + if (found == NULL) { + VMEM_ASSERT; + return -1; + } + merge_page_no = found->page->pageno; + merge_page_size += found->page->alloc_pages; + VMEM_P_FREE(found); + } + if (next_size >= 0) { + mm->free_tree = avltree_remove(mm->free_tree, &found, + MAKE_KEY(next_size, next_free_pageno)); + if (found == NULL) { + VMEM_ASSERT; + return -1; + } + merge_page_size += found->page->alloc_pages; + VMEM_P_FREE(found); + } + page->alloc_pages = 0; + page->first_pageno = -1; + set_blocks_free(mm, merge_page_no, merge_page_size); + mm->alloc_page_count -= free_page_size; + mm->free_page_count += free_page_size; + return 0; +} + +s32 vmem_get_info(struct video_mm_t *mm, struct vmem_info_t *info) +{ + if (mm == NULL) { + pr_info("vmem_get_info: invalid handle\n"); + return -1; + } + + if (info == NULL) + return -1; + + info->total_pages = mm->num_pages; + info->alloc_pages = mm->alloc_page_count; + info->free_pages = mm->free_page_count; + info->page_size = VMEM_PAGE_SIZE; + return 0; +} +#endif /* __CNM_VIDEO_MEMORY_MANAGEMENT_H__ */ diff --git a/drivers/amlogic/media_modules/frame_sink/encoder/h265/vpu.c b/drivers/amlogic/media_modules/frame_sink/encoder/h265/vpu.c new file mode 100644 index 000000000000..3345b0a23e07 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_sink/encoder/h265/vpu.c @@ -0,0 +1,2040 @@ +/* + * vpu.c + * + * linux device driver for VPU. + * + * Copyright (C) 2006 - 2013 CHIPS&MEDIA INC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "../../../common/media_clock/switch/amports_gate.h" + +#include "vpu.h" +#include "vmm.h" + +/* definitions to be changed as customer configuration */ +/* if you want to have clock gating scheme frame by frame */ +/* #define VPU_SUPPORT_CLOCK_CONTROL */ + +#define VPU_PLATFORM_DEVICE_NAME "HevcEnc" +#define VPU_DEV_NAME "HevcEnc" +#define VPU_CLASS_NAME "HevcEnc" + +#ifndef VM_RESERVED /*for kernel up to 3.7.0 version*/ +#define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP) +#endif + +#define VPU_INIT_VIDEO_MEMORY_SIZE_IN_BYTE (64 * SZ_1M) + +#define LOG_ALL 0 +#define LOG_INFO 1 +#define LOG_DEBUG 2 +#define LOG_ERROR 3 + +#define enc_pr(level, x...) \ + do { \ + if (level >= print_level) \ + printk(x); \ + } while (0) + +static s32 print_level = LOG_DEBUG; +static s32 clock_level = 4; + +static struct video_mm_t s_vmem; +static struct vpudrv_buffer_t s_video_memory = {0}; +static bool use_reserve; +static ulong cma_pool_size; + +/* end customer definition */ +static struct vpudrv_buffer_t s_instance_pool = {0}; +static struct vpudrv_buffer_t s_common_memory = {0}; +static struct vpu_drv_context_t s_vpu_drv_context; +static s32 s_vpu_major; +static struct device *hevcenc_dev; + +static s32 s_vpu_open_ref_count; +static s32 s_vpu_irq; +static bool s_vpu_irq_requested; + +static struct vpudrv_buffer_t s_vpu_register = {0}; + +static s32 s_interrupt_flag; +static wait_queue_head_t s_interrupt_wait_q; + +static spinlock_t s_vpu_lock = __SPIN_LOCK_UNLOCKED(s_vpu_lock); +static DEFINE_SEMAPHORE(s_vpu_sem); +static struct list_head s_vbp_head = LIST_HEAD_INIT(s_vbp_head); +static struct list_head s_inst_list_head = LIST_HEAD_INIT(s_inst_list_head); +static struct tasklet_struct hevc_tasklet; +static struct platform_device *hevc_pdev; + +static struct vpu_bit_firmware_info_t s_bit_firmware_info[MAX_NUM_VPU_CORE]; + +static void dma_flush(u32 buf_start, u32 buf_size) +{ + if (hevc_pdev) + dma_sync_single_for_device( + &hevc_pdev->dev, buf_start, + buf_size, DMA_TO_DEVICE); +} + +static void cache_flush(u32 buf_start, u32 buf_size) +{ + if (hevc_pdev) + dma_sync_single_for_cpu( + &hevc_pdev->dev, buf_start, + buf_size, DMA_FROM_DEVICE); +} + +s32 vpu_hw_reset(void) +{ + enc_pr(LOG_DEBUG, "request vpu reset from application.\n"); + return 0; +} + +s32 vpu_clk_config(u32 enable) +{ + if (enable) { + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) + HevcEnc_MoreClock_enable(); + HevcEnc_clock_enable(clock_level); + } else { + HevcEnc_clock_disable(); + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) + HevcEnc_MoreClock_disable(); + } + return 0; +} + +static s32 vpu_alloc_dma_buffer(struct vpudrv_buffer_t *vb) +{ + if (!vb) + return -1; + + vb->phys_addr = (ulong)vmem_alloc(&s_vmem, vb->size, 0); + if ((ulong)vb->phys_addr == (ulong)-1) { + enc_pr(LOG_ERROR, + "Physical memory allocation error size=%d\n", vb->size); + return -1; + } + + vb->base = (ulong)(s_video_memory.base + + (vb->phys_addr - s_video_memory.phys_addr)); + return 0; +} + +static void vpu_free_dma_buffer(struct vpudrv_buffer_t *vb) +{ + if (!vb) + return; + + if (vb->base) + vmem_free(&s_vmem, vb->phys_addr, 0); +} + +static s32 vpu_free_instances(struct file *filp) +{ + struct vpudrv_instanace_list_t *vil, *n; + struct vpudrv_instance_pool_t *vip; + void *vip_base; + + enc_pr(LOG_DEBUG, "vpu_free_instances\n"); + + list_for_each_entry_safe(vil, n, &s_inst_list_head, list) { + if (vil->filp == filp) { + vip_base = (void *)s_instance_pool.base; + enc_pr(LOG_INFO, + "free_instances instIdx=%d, coreIdx=%d, vip_base=%p\n", + (s32)vil->inst_idx, + (s32)vil->core_idx, + vip_base); + vip = (struct vpudrv_instance_pool_t *)vip_base; + if (vip) { + /* only first 4 byte is key point + * (inUse of CodecInst in vpuapi) + * to free the corresponding instance. + */ + memset(&vip->codecInstPool[vil->inst_idx], + 0x00, 4); + } + s_vpu_open_ref_count--; + list_del(&vil->list); + kfree(vil); + } + } + return 1; +} + +static s32 vpu_free_buffers(struct file *filp) +{ + struct vpudrv_buffer_pool_t *pool, *n; + struct vpudrv_buffer_t vb; + + enc_pr(LOG_DEBUG, "vpu_free_buffers\n"); + + list_for_each_entry_safe(pool, n, &s_vbp_head, list) { + if (pool->filp == filp) { + vb = pool->vb; + if (vb.base) { + vpu_free_dma_buffer(&vb); + list_del(&pool->list); + kfree(pool); + } + } + } + return 0; +} + +static u32 vpu_is_buffer_cached(struct file *filp, ulong vm_pgoff) +{ + struct vpudrv_buffer_pool_t *pool, *n; + struct vpudrv_buffer_t vb; + bool find = false; + u32 cached = 0; + + enc_pr(LOG_ALL, "[+]vpu_is_buffer_cached\n"); + spin_lock(&s_vpu_lock); + list_for_each_entry_safe(pool, n, &s_vbp_head, list) { + if (pool->filp == filp) { + vb = pool->vb; + if (((vb.phys_addr >> PAGE_SHIFT) == vm_pgoff) + && find == false){ + cached = vb.cached; + find = true; + } + } + } + spin_unlock(&s_vpu_lock); + enc_pr(LOG_ALL, "[-]vpu_is_buffer_cached, ret:%d\n", cached); + return cached; +} + +static void hevcenc_isr_tasklet(ulong data) +{ + struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)data; + + enc_pr(LOG_INFO, "hevcenc_isr_tasklet interruput:0x%08lx\n", + dev->interrupt_reason); + if (dev->interrupt_reason) { + /* notify the interrupt to user space */ + if (dev->async_queue) { + enc_pr(LOG_ALL, "kill_fasync e %s\n", __func__); + kill_fasync(&dev->async_queue, SIGIO, POLL_IN); + } + s_interrupt_flag = 1; + wake_up_interruptible(&s_interrupt_wait_q); + } + enc_pr(LOG_ALL, "[-]%s\n", __func__); +} + +static irqreturn_t vpu_irq_handler(s32 irq, void *dev_id) +{ + struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)dev_id; + /* this can be removed. + * it also work in VPU_WaitInterrupt of API function + */ + u32 core; + ulong interrupt_reason = 0; + + enc_pr(LOG_ALL, "[+]%s\n", __func__); + + for (core = 0; core < MAX_NUM_VPU_CORE; core++) { + if (s_bit_firmware_info[core].size == 0) { + /* it means that we didn't get an information + * the current core from API layer. + * No core activated. + */ + enc_pr(LOG_ERROR, + "s_bit_firmware_info[core].size is zero\n"); + continue; + } + if (ReadVpuRegister(W4_VPU_VPU_INT_STS)) { + interrupt_reason = ReadVpuRegister(W4_VPU_INT_REASON); + WriteVpuRegister(W4_VPU_INT_REASON_CLEAR, + interrupt_reason); + WriteVpuRegister(W4_VPU_VINT_CLEAR, 0x1); + dev->interrupt_reason |= interrupt_reason; + } + enc_pr(LOG_INFO, + "intr_reason: 0x%08lx\n", dev->interrupt_reason); + } + if (dev->interrupt_reason) + tasklet_schedule(&hevc_tasklet); + enc_pr(LOG_ALL, "[-]%s\n", __func__); + return IRQ_HANDLED; +} + +static s32 vpu_open(struct inode *inode, struct file *filp) +{ + bool alloc_buffer = false; + s32 r = 0; + + enc_pr(LOG_DEBUG, "[+] %s\n", __func__); + spin_lock(&s_vpu_lock); + s_vpu_drv_context.open_count++; + if (s_vpu_drv_context.open_count == 1) { + alloc_buffer = true; + } else { + r = -EBUSY; + s_vpu_drv_context.open_count--; + spin_unlock(&s_vpu_lock); + goto Err; + } + filp->private_data = (void *)(&s_vpu_drv_context); + spin_unlock(&s_vpu_lock); + if (alloc_buffer && !use_reserve) { +#ifdef CONFIG_CMA + s_video_memory.size = VPU_INIT_VIDEO_MEMORY_SIZE_IN_BYTE; + s_video_memory.phys_addr = + (ulong)codec_mm_alloc_for_dma(VPU_DEV_NAME, + VPU_INIT_VIDEO_MEMORY_SIZE_IN_BYTE >> PAGE_SHIFT, 0, + CODEC_MM_FLAGS_CPU); + if (s_video_memory.phys_addr) + s_video_memory.base = + (ulong)phys_to_virt(s_video_memory.phys_addr); + else + s_video_memory.base = 0; + if (s_video_memory.base) { + enc_pr(LOG_DEBUG, + "allocating phys 0x%lx, virt addr 0x%lx, size %dk\n", + s_video_memory.phys_addr, + s_video_memory.base, + s_video_memory.size >> 10); + if (vmem_init(&s_vmem, + s_video_memory.phys_addr, + s_video_memory.size) < 0) { + enc_pr(LOG_ERROR, "fail to init vmem system\n"); + r = -ENOMEM; + codec_mm_free_for_dma( + VPU_DEV_NAME, + (u32)s_video_memory.phys_addr); + vmem_exit(&s_vmem); + memset(&s_video_memory, 0, + sizeof(struct vpudrv_buffer_t)); + memset(&s_vmem, 0, + sizeof(struct video_mm_t)); + } + } else { + enc_pr(LOG_ERROR, + "CMA failed to allocate dma buffer for %s, phys: 0x%lx\n", + VPU_DEV_NAME, s_video_memory.phys_addr); + if (s_video_memory.phys_addr) + codec_mm_free_for_dma( + VPU_DEV_NAME, + (u32)s_video_memory.phys_addr); + s_video_memory.phys_addr = 0; + r = -ENOMEM; + } +#else + enc_pr(LOG_ERROR, + "No CMA and reserved memory for HevcEnc!!!\n"); + r = -ENOMEM; +#endif + } else if (!s_video_memory.base) { + enc_pr(LOG_ERROR, + "HevcEnc memory is not malloced!!!\n"); + r = -ENOMEM; + } + if (alloc_buffer) { + ulong flags; + u32 data32; + + if ((s_vpu_irq >= 0) && (s_vpu_irq_requested == false)) { + s32 err; + + err = request_irq(s_vpu_irq, vpu_irq_handler, 0, + "HevcEnc-irq", (void *)(&s_vpu_drv_context)); + if (err) { + enc_pr(LOG_ERROR, + "fail to register interrupt handler\n"); + return -EFAULT; + } + s_vpu_irq_requested = true; + } + amports_switch_gate("vdec", 1); + spin_lock_irqsave(&s_vpu_lock, flags); + WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, + READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) & ~(0x3<<24)); + udelay(10); + + if (get_cpu_type() <= MESON_CPU_MAJOR_ID_TXLX) { + data32 = 0x700; + data32 |= READ_VREG(DOS_SW_RESET4); + WRITE_VREG(DOS_SW_RESET4, data32); + data32 &= ~0x700; + WRITE_VREG(DOS_SW_RESET4, data32); + } else { + data32 = 0xf00; + data32 |= READ_VREG(DOS_SW_RESET4); + WRITE_VREG(DOS_SW_RESET4, data32); + data32 &= ~0xf00; + WRITE_VREG(DOS_SW_RESET4, data32); + } + + WRITE_MPEG_REG(RESET0_REGISTER, data32 & ~(1<<21)); + WRITE_MPEG_REG(RESET0_REGISTER, data32 | (1<<21)); + READ_MPEG_REG(RESET0_REGISTER); + READ_MPEG_REG(RESET0_REGISTER); + READ_MPEG_REG(RESET0_REGISTER); + READ_MPEG_REG(RESET0_REGISTER); +#ifndef VPU_SUPPORT_CLOCK_CONTROL + vpu_clk_config(1); +#endif + /* Enable wave420l_vpu_idle_rise_irq, + * Disable wave420l_vpu_idle_fall_irq + */ + WRITE_VREG(DOS_WAVE420L_CNTL_STAT, 0x1); + WRITE_VREG(DOS_MEM_PD_WAVE420L, 0x0); + + WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, + READ_AOREG(AO_RTI_GEN_PWR_ISO0) & ~(0x3<<12)); + udelay(10); + + spin_unlock_irqrestore(&s_vpu_lock, flags); + } +Err: + enc_pr(LOG_DEBUG, "[-] %s, ret: %d\n", __func__, r); + return r; +} + +static long vpu_ioctl(struct file *filp, u32 cmd, ulong arg) +{ + s32 ret = 0; + struct vpu_drv_context_t *dev = + (struct vpu_drv_context_t *)filp->private_data; + + switch (cmd) { + case VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY: + { + struct vpudrv_buffer_pool_t *vbp; + + enc_pr(LOG_ALL, + "[+]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n"); + ret = down_interruptible(&s_vpu_sem); + if (ret == 0) { + vbp = kzalloc(sizeof(*vbp), GFP_KERNEL); + if (!vbp) { + up(&s_vpu_sem); + return -ENOMEM; + } + + ret = copy_from_user(&(vbp->vb), + (struct vpudrv_buffer_t *)arg, + sizeof(struct vpudrv_buffer_t)); + if (ret) { + kfree(vbp); + up(&s_vpu_sem); + return -EFAULT; + } + + ret = vpu_alloc_dma_buffer(&(vbp->vb)); + if (ret == -1) { + ret = -ENOMEM; + kfree(vbp); + up(&s_vpu_sem); + break; + } + ret = copy_to_user((void __user *)arg, + &(vbp->vb), + sizeof(struct vpudrv_buffer_t)); + if (ret) { + kfree(vbp); + ret = -EFAULT; + up(&s_vpu_sem); + break; + } + + vbp->filp = filp; + spin_lock(&s_vpu_lock); + list_add(&vbp->list, &s_vbp_head); + spin_unlock(&s_vpu_lock); + + up(&s_vpu_sem); + } + enc_pr(LOG_ALL, + "[-]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n"); + } + break; + case VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY32: + { + struct vpudrv_buffer_pool_t *vbp; + struct compat_vpudrv_buffer_t buf32; + + enc_pr(LOG_ALL, + "[+]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY32\n"); + ret = down_interruptible(&s_vpu_sem); + if (ret == 0) { + vbp = kzalloc(sizeof(*vbp), GFP_KERNEL); + if (!vbp) { + up(&s_vpu_sem); + return -ENOMEM; + } + + ret = copy_from_user(&buf32, + (struct compat_vpudrv_buffer_t *)arg, + sizeof(struct compat_vpudrv_buffer_t)); + if (ret) { + kfree(vbp); + up(&s_vpu_sem); + return -EFAULT; + } + + vbp->vb.size = buf32.size; + vbp->vb.cached = buf32.cached; + vbp->vb.phys_addr = + (ulong)buf32.phys_addr; + vbp->vb.base = + (ulong)buf32.base; + vbp->vb.virt_addr = + (ulong)buf32.virt_addr; + ret = vpu_alloc_dma_buffer(&(vbp->vb)); + if (ret == -1) { + ret = -ENOMEM; + kfree(vbp); + up(&s_vpu_sem); + break; + } + + buf32.size = vbp->vb.size; + buf32.phys_addr = + (compat_ulong_t)vbp->vb.phys_addr; + buf32.base = + (compat_ulong_t)vbp->vb.base; + buf32.virt_addr = + (compat_ulong_t)vbp->vb.virt_addr; + + ret = copy_to_user((void __user *)arg, + &buf32, + sizeof(struct compat_vpudrv_buffer_t)); + if (ret) { + kfree(vbp); + ret = -EFAULT; + up(&s_vpu_sem); + break; + } + + vbp->filp = filp; + spin_lock(&s_vpu_lock); + list_add(&vbp->list, &s_vbp_head); + spin_unlock(&s_vpu_lock); + + up(&s_vpu_sem); + } + enc_pr(LOG_ALL, + "[-]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY32\n"); + } + break; + case VDI_IOCTL_FREE_PHYSICALMEMORY: + { + struct vpudrv_buffer_pool_t *vbp, *n; + struct vpudrv_buffer_t vb; + + enc_pr(LOG_ALL, + "[+]VDI_IOCTL_FREE_PHYSICALMEMORY\n"); + ret = down_interruptible(&s_vpu_sem); + if (ret == 0) { + ret = copy_from_user(&vb, + (struct vpudrv_buffer_t *)arg, + sizeof(struct vpudrv_buffer_t)); + if (ret) { + up(&s_vpu_sem); + return -EACCES; + } + + if (vb.base) + vpu_free_dma_buffer(&vb); + + spin_lock(&s_vpu_lock); + list_for_each_entry_safe(vbp, n, + &s_vbp_head, list) { + if (vbp->vb.base == vb.base) { + list_del(&vbp->list); + kfree(vbp); + break; + } + } + spin_unlock(&s_vpu_lock); + up(&s_vpu_sem); + } + enc_pr(LOG_ALL, + "[-]VDI_IOCTL_FREE_PHYSICALMEMORY\n"); + } + break; + case VDI_IOCTL_FREE_PHYSICALMEMORY32: + { + struct vpudrv_buffer_pool_t *vbp, *n; + struct compat_vpudrv_buffer_t buf32; + struct vpudrv_buffer_t vb; + + enc_pr(LOG_ALL, + "[+]VDI_IOCTL_FREE_PHYSICALMEMORY32\n"); + ret = down_interruptible(&s_vpu_sem); + if (ret == 0) { + ret = copy_from_user(&buf32, + (struct compat_vpudrv_buffer_t *)arg, + sizeof(struct compat_vpudrv_buffer_t)); + if (ret) { + up(&s_vpu_sem); + return -EACCES; + } + + vb.size = buf32.size; + vb.phys_addr = + (ulong)buf32.phys_addr; + vb.base = + (ulong)buf32.base; + vb.virt_addr = + (ulong)buf32.virt_addr; + + if (vb.base) + vpu_free_dma_buffer(&vb); + + spin_lock(&s_vpu_lock); + list_for_each_entry_safe(vbp, n, + &s_vbp_head, list) { + if ((compat_ulong_t)vbp->vb.base + == buf32.base) { + list_del(&vbp->list); + kfree(vbp); + break; + } + } + spin_unlock(&s_vpu_lock); + up(&s_vpu_sem); + } + enc_pr(LOG_ALL, + "[-]VDI_IOCTL_FREE_PHYSICALMEMORY32\n"); + } + break; + case VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO: + { + enc_pr(LOG_ALL, + "[+]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n"); + if (s_video_memory.base != 0) { + ret = copy_to_user((void __user *)arg, + &s_video_memory, + sizeof(struct vpudrv_buffer_t)); + if (ret != 0) + ret = -EFAULT; + } else { + ret = -EFAULT; + } + enc_pr(LOG_ALL, + "[-]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n"); + } + break; + case VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO32: + { + struct compat_vpudrv_buffer_t buf32; + + enc_pr(LOG_ALL, + "[+]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO32\n"); + + buf32.size = s_video_memory.size; + buf32.phys_addr = + (compat_ulong_t)s_video_memory.phys_addr; + buf32.base = + (compat_ulong_t)s_video_memory.base; + buf32.virt_addr = + (compat_ulong_t)s_video_memory.virt_addr; + if (s_video_memory.base != 0) { + ret = copy_to_user((void __user *)arg, + &buf32, + sizeof(struct compat_vpudrv_buffer_t)); + if (ret != 0) + ret = -EFAULT; + } else { + ret = -EFAULT; + } + enc_pr(LOG_ALL, + "[-]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO32\n"); + } + break; + case VDI_IOCTL_WAIT_INTERRUPT: + { + struct vpudrv_intr_info_t info; + + enc_pr(LOG_ALL, + "[+]VDI_IOCTL_WAIT_INTERRUPT\n"); + ret = copy_from_user(&info, + (struct vpudrv_intr_info_t *)arg, + sizeof(struct vpudrv_intr_info_t)); + if (ret != 0) + return -EFAULT; + + ret = wait_event_interruptible_timeout( + s_interrupt_wait_q, + s_interrupt_flag != 0, + msecs_to_jiffies(info.timeout)); + if (!ret) { + ret = -ETIME; + break; + } + if (dev->interrupt_reason & (1 << W4_INT_ENC_PIC)) { + u32 start, end, size, core = 0; + + start = ReadVpuRegister(W4_BS_RD_PTR); + end = ReadVpuRegister(W4_BS_WR_PTR); + size = ReadVpuRegister(W4_RET_ENC_PIC_BYTE); + enc_pr(LOG_INFO, "flush output buffer, "); + enc_pr(LOG_INFO, + "start:0x%x, end:0x%x, size:0x%x\n", + start, end, size); + if (end - start > size && end > start) + size = end - start; + if (size > 0) + cache_flush(start, size); + } + + if (signal_pending(current)) { + ret = -ERESTARTSYS; + break; + } + + enc_pr(LOG_INFO, + "s_interrupt_flag(%d), reason(0x%08lx)\n", + s_interrupt_flag, dev->interrupt_reason); + + info.intr_reason = dev->interrupt_reason; + s_interrupt_flag = 0; + dev->interrupt_reason = 0; + ret = copy_to_user((void __user *)arg, + &info, sizeof(struct vpudrv_intr_info_t)); + enc_pr(LOG_ALL, + "[-]VDI_IOCTL_WAIT_INTERRUPT\n"); + if (ret != 0) + return -EFAULT; + } + break; + case VDI_IOCTL_SET_CLOCK_GATE: + { + u32 clkgate; + + enc_pr(LOG_ALL, + "[+]VDI_IOCTL_SET_CLOCK_GATE\n"); + if (get_user(clkgate, (u32 __user *) arg)) + return -EFAULT; +#ifdef VPU_SUPPORT_CLOCK_CONTROL + vpu_clk_config(clkgate); +#endif + enc_pr(LOG_ALL, + "[-]VDI_IOCTL_SET_CLOCK_GATE\n"); + } + break; + case VDI_IOCTL_GET_INSTANCE_POOL: + { + enc_pr(LOG_ALL, + "[+]VDI_IOCTL_GET_INSTANCE_POOL\n"); + ret = down_interruptible(&s_vpu_sem); + if (ret != 0) + break; + + if (s_instance_pool.base != 0) { + ret = copy_to_user((void __user *)arg, + &s_instance_pool, + sizeof(struct vpudrv_buffer_t)); + ret = (ret != 0) ? -EFAULT : 0; + } else { + ret = copy_from_user(&s_instance_pool, + (struct vpudrv_buffer_t *)arg, + sizeof(struct vpudrv_buffer_t)); + if (ret == 0) { + s_instance_pool.size = + PAGE_ALIGN( + s_instance_pool.size); + s_instance_pool.base = + (ulong)vmalloc( + s_instance_pool.size); + s_instance_pool.phys_addr = + s_instance_pool.base; + if (s_instance_pool.base == 0) { + ret = -EFAULT; + up(&s_vpu_sem); + break; + } + /*clearing memory*/ + memset((void *)s_instance_pool.base, + 0, s_instance_pool.size); + ret = copy_to_user((void __user *)arg, + &s_instance_pool, + sizeof(struct vpudrv_buffer_t)); + if (ret != 0) + ret = -EFAULT; + } else + ret = -EFAULT; + } + up(&s_vpu_sem); + enc_pr(LOG_ALL, + "[-]VDI_IOCTL_GET_INSTANCE_POOL\n"); + } + break; + case VDI_IOCTL_GET_INSTANCE_POOL32: + { + struct compat_vpudrv_buffer_t buf32; + + enc_pr(LOG_ALL, + "[+]VDI_IOCTL_GET_INSTANCE_POOL32\n"); + ret = down_interruptible(&s_vpu_sem); + if (ret != 0) + break; + if (s_instance_pool.base != 0) { + buf32.size = s_instance_pool.size; + buf32.phys_addr = + (compat_ulong_t) + s_instance_pool.phys_addr; + buf32.base = + (compat_ulong_t) + s_instance_pool.base; + buf32.virt_addr = + (compat_ulong_t) + s_instance_pool.virt_addr; + ret = copy_to_user((void __user *)arg, + &buf32, + sizeof(struct compat_vpudrv_buffer_t)); + ret = (ret != 0) ? -EFAULT : 0; + } else { + ret = copy_from_user(&buf32, + (struct compat_vpudrv_buffer_t *)arg, + sizeof(struct compat_vpudrv_buffer_t)); + if (ret == 0) { + s_instance_pool.size = buf32.size; + s_instance_pool.size = + PAGE_ALIGN( + s_instance_pool.size); + s_instance_pool.base = + (ulong)vmalloc( + s_instance_pool.size); + s_instance_pool.phys_addr = + s_instance_pool.base; + buf32.size = + s_instance_pool.size; + buf32.phys_addr = + (compat_ulong_t) + s_instance_pool.phys_addr; + buf32.base = + (compat_ulong_t) + s_instance_pool.base; + buf32.virt_addr = + (compat_ulong_t) + s_instance_pool.virt_addr; + if (s_instance_pool.base == 0) { + ret = -EFAULT; + up(&s_vpu_sem); + break; + } + /*clearing memory*/ + memset((void *)s_instance_pool.base, + 0x0, s_instance_pool.size); + ret = copy_to_user((void __user *)arg, + &buf32, + sizeof( + struct compat_vpudrv_buffer_t)); + if (ret != 0) + ret = -EFAULT; + } else + ret = -EFAULT; + } + up(&s_vpu_sem); + enc_pr(LOG_ALL, + "[-]VDI_IOCTL_GET_INSTANCE_POOL32\n"); + } + break; + case VDI_IOCTL_GET_COMMON_MEMORY: + { + enc_pr(LOG_ALL, + "[+]VDI_IOCTL_GET_COMMON_MEMORY\n"); + if (s_common_memory.base != 0) { + ret = copy_to_user((void __user *)arg, + &s_common_memory, + sizeof(struct vpudrv_buffer_t)); + if (ret != 0) + ret = -EFAULT; + } else { + ret = copy_from_user(&s_common_memory, + (struct vpudrv_buffer_t *)arg, + sizeof(struct vpudrv_buffer_t)); + if (ret != 0) { + ret = -EFAULT; + break; + } + if (vpu_alloc_dma_buffer( + &s_common_memory) != -1) { + ret = copy_to_user((void __user *)arg, + &s_common_memory, + sizeof(struct vpudrv_buffer_t)); + if (ret != 0) + ret = -EFAULT; + } else + ret = -EFAULT; + } + enc_pr(LOG_ALL, + "[-]VDI_IOCTL_GET_COMMON_MEMORY\n"); + } + break; + case VDI_IOCTL_GET_COMMON_MEMORY32: + { + struct compat_vpudrv_buffer_t buf32; + + enc_pr(LOG_ALL, + "[+]VDI_IOCTL_GET_COMMON_MEMORY32\n"); + + buf32.size = s_common_memory.size; + buf32.phys_addr = + (compat_ulong_t) + s_common_memory.phys_addr; + buf32.base = + (compat_ulong_t) + s_common_memory.base; + buf32.virt_addr = + (compat_ulong_t) + s_common_memory.virt_addr; + if (s_common_memory.base != 0) { + ret = copy_to_user((void __user *)arg, + &buf32, + sizeof(struct compat_vpudrv_buffer_t)); + if (ret != 0) + ret = -EFAULT; + } else { + ret = copy_from_user(&buf32, + (struct compat_vpudrv_buffer_t *)arg, + sizeof(struct compat_vpudrv_buffer_t)); + if (ret != 0) { + ret = -EFAULT; + break; + } + s_common_memory.size = buf32.size; + if (vpu_alloc_dma_buffer( + &s_common_memory) != -1) { + buf32.size = + s_common_memory.size; + buf32.phys_addr = + (compat_ulong_t) + s_common_memory.phys_addr; + buf32.base = + (compat_ulong_t) + s_common_memory.base; + buf32.virt_addr = + (compat_ulong_t) + s_common_memory.virt_addr; + ret = copy_to_user((void __user *)arg, + &buf32, + sizeof( + struct compat_vpudrv_buffer_t)); + if (ret != 0) + ret = -EFAULT; + } else + ret = -EFAULT; + } + enc_pr(LOG_ALL, + "[-]VDI_IOCTL_GET_COMMON_MEMORY32\n"); + } + break; + case VDI_IOCTL_OPEN_INSTANCE: + { + struct vpudrv_inst_info_t inst_info; + struct vpudrv_instanace_list_t *vil, *n; + + vil = kzalloc(sizeof(*vil), GFP_KERNEL); + if (!vil) + return -ENOMEM; + + if (copy_from_user(&inst_info, + (struct vpudrv_inst_info_t *)arg, + sizeof(struct vpudrv_inst_info_t))) + return -EFAULT; + + vil->inst_idx = inst_info.inst_idx; + vil->core_idx = inst_info.core_idx; + vil->filp = filp; + + spin_lock(&s_vpu_lock); + list_add(&vil->list, &s_inst_list_head); + + /* counting the current open instance number */ + inst_info.inst_open_count = 0; + list_for_each_entry_safe(vil, n, + &s_inst_list_head, list) { + if (vil->core_idx == inst_info.core_idx) + inst_info.inst_open_count++; + } + + /* flag just for that vpu is in opened or closed */ + s_vpu_open_ref_count++; + spin_unlock(&s_vpu_lock); + + if (copy_to_user((void __user *)arg, + &inst_info, + sizeof(struct vpudrv_inst_info_t))) { + kfree(vil); + return -EFAULT; + } + + enc_pr(LOG_DEBUG, + "VDI_IOCTL_OPEN_INSTANCE "); + enc_pr(LOG_DEBUG, + "core_idx=%d, inst_idx=%d, ", + (u32)inst_info.core_idx, + (u32)inst_info.inst_idx); + enc_pr(LOG_DEBUG, + "s_vpu_open_ref_count=%d, inst_open_count=%d\n", + s_vpu_open_ref_count, + inst_info.inst_open_count); + } + break; + case VDI_IOCTL_CLOSE_INSTANCE: + { + struct vpudrv_inst_info_t inst_info; + struct vpudrv_instanace_list_t *vil, *n; + + enc_pr(LOG_ALL, + "[+]VDI_IOCTL_CLOSE_INSTANCE\n"); + if (copy_from_user(&inst_info, + (struct vpudrv_inst_info_t *)arg, + sizeof(struct vpudrv_inst_info_t))) + return -EFAULT; + + spin_lock(&s_vpu_lock); + list_for_each_entry_safe(vil, n, + &s_inst_list_head, list) { + if (vil->inst_idx == inst_info.inst_idx && + vil->core_idx == inst_info.core_idx) { + list_del(&vil->list); + kfree(vil); + break; + } + } + + /* counting the current open instance number */ + inst_info.inst_open_count = 0; + list_for_each_entry_safe(vil, n, + &s_inst_list_head, list) { + if (vil->core_idx == inst_info.core_idx) + inst_info.inst_open_count++; + } + + /* flag just for that vpu is in opened or closed */ + s_vpu_open_ref_count--; + spin_unlock(&s_vpu_lock); + + if (copy_to_user((void __user *)arg, + &inst_info, + sizeof(struct vpudrv_inst_info_t))) + return -EFAULT; + + enc_pr(LOG_DEBUG, + "VDI_IOCTL_CLOSE_INSTANCE "); + enc_pr(LOG_DEBUG, + "core_idx=%d, inst_idx=%d, ", + (u32)inst_info.core_idx, + (u32)inst_info.inst_idx); + enc_pr(LOG_DEBUG, + "s_vpu_open_ref_count=%d, inst_open_count=%d\n", + s_vpu_open_ref_count, + inst_info.inst_open_count); + } + break; + case VDI_IOCTL_GET_INSTANCE_NUM: + { + struct vpudrv_inst_info_t inst_info; + struct vpudrv_instanace_list_t *vil, *n; + + enc_pr(LOG_ALL, + "[+]VDI_IOCTL_GET_INSTANCE_NUM\n"); + + ret = copy_from_user(&inst_info, + (struct vpudrv_inst_info_t *)arg, + sizeof(struct vpudrv_inst_info_t)); + if (ret != 0) + break; + + inst_info.inst_open_count = 0; + + spin_lock(&s_vpu_lock); + list_for_each_entry_safe(vil, n, + &s_inst_list_head, list) { + if (vil->core_idx == inst_info.core_idx) + inst_info.inst_open_count++; + } + spin_unlock(&s_vpu_lock); + + ret = copy_to_user((void __user *)arg, + &inst_info, + sizeof(struct vpudrv_inst_info_t)); + + enc_pr(LOG_DEBUG, + "VDI_IOCTL_GET_INSTANCE_NUM "); + enc_pr(LOG_DEBUG, + "core_idx=%d, inst_idx=%d, open_count=%d\n", + (u32)inst_info.core_idx, + (u32)inst_info.inst_idx, + inst_info.inst_open_count); + } + break; + case VDI_IOCTL_RESET: + { + vpu_hw_reset(); + } + break; + case VDI_IOCTL_GET_REGISTER_INFO: + { + enc_pr(LOG_ALL, + "[+]VDI_IOCTL_GET_REGISTER_INFO\n"); + ret = copy_to_user((void __user *)arg, + &s_vpu_register, + sizeof(struct vpudrv_buffer_t)); + if (ret != 0) + ret = -EFAULT; + enc_pr(LOG_ALL, + "[-]VDI_IOCTL_GET_REGISTER_INFO "); + enc_pr(LOG_ALL, + "s_vpu_register.phys_addr=0x%lx, ", + s_vpu_register.phys_addr); + enc_pr(LOG_ALL, + "s_vpu_register.virt_addr=0x%lx, ", + s_vpu_register.virt_addr); + enc_pr(LOG_ALL, + "s_vpu_register.size=0x%x\n", + s_vpu_register.size); + } + break; + case VDI_IOCTL_GET_REGISTER_INFO32: + { + struct compat_vpudrv_buffer_t buf32; + + enc_pr(LOG_ALL, + "[+]VDI_IOCTL_GET_REGISTER_INFO32\n"); + + buf32.size = s_vpu_register.size; + buf32.phys_addr = + (compat_ulong_t) + s_vpu_register.phys_addr; + buf32.base = + (compat_ulong_t) + s_vpu_register.base; + buf32.virt_addr = + (compat_ulong_t) + s_vpu_register.virt_addr; + ret = copy_to_user((void __user *)arg, + &buf32, + sizeof( + struct compat_vpudrv_buffer_t)); + if (ret != 0) + ret = -EFAULT; + enc_pr(LOG_ALL, + "[-]VDI_IOCTL_GET_REGISTER_INFO32 "); + enc_pr(LOG_ALL, + "s_vpu_register.phys_addr=0x%lx, ", + s_vpu_register.phys_addr); + enc_pr(LOG_ALL, + "s_vpu_register.virt_addr=0x%lx, ", + s_vpu_register.virt_addr); + enc_pr(LOG_ALL, + "s_vpu_register.size=0x%x\n", + s_vpu_register.size); + } + break; + case VDI_IOCTL_FLUSH_BUFFER32: + { + struct vpudrv_buffer_pool_t *pool, *n; + struct compat_vpudrv_buffer_t buf32; + struct vpudrv_buffer_t vb; + bool find = false; + u32 cached = 0; + + enc_pr(LOG_ALL, + "[+]VDI_IOCTL_FLUSH_BUFFER32\n"); + + ret = copy_from_user(&buf32, + (struct compat_vpudrv_buffer_t *)arg, + sizeof(struct compat_vpudrv_buffer_t)); + if (ret) + return -EFAULT; + spin_lock(&s_vpu_lock); + list_for_each_entry_safe(pool, n, + &s_vbp_head, list) { + if (pool->filp == filp) { + vb = pool->vb; + if (((compat_ulong_t)vb.phys_addr + == buf32.phys_addr) + && find == false){ + cached = vb.cached; + find = true; + } + } + } + spin_unlock(&s_vpu_lock); + if (find && cached) + dma_flush( + (u32)buf32.phys_addr, + (u32)buf32.size); + enc_pr(LOG_ALL, + "[-]VDI_IOCTL_FLUSH_BUFFER32\n"); + } + break; + case VDI_IOCTL_FLUSH_BUFFER: + { + struct vpudrv_buffer_pool_t *pool, *n; + struct vpudrv_buffer_t vb, buf; + bool find = false; + u32 cached = 0; + + enc_pr(LOG_ALL, + "[+]VDI_IOCTL_FLUSH_BUFFER\n"); + + ret = copy_from_user(&buf, + (struct vpudrv_buffer_t *)arg, + sizeof(struct vpudrv_buffer_t)); + if (ret) + return -EFAULT; + spin_lock(&s_vpu_lock); + list_for_each_entry_safe(pool, n, + &s_vbp_head, list) { + if (pool->filp == filp) { + vb = pool->vb; + if ((vb.phys_addr + == buf.phys_addr) + && find == false){ + cached = vb.cached; + find = true; + } + } + } + spin_unlock(&s_vpu_lock); + if (find && cached) + dma_flush( + (u32)buf.phys_addr, + (u32)buf.size); + enc_pr(LOG_ALL, + "[-]VDI_IOCTL_FLUSH_BUFFER\n"); + } + break; + default: + { + enc_pr(LOG_ERROR, + "No such IOCTL, cmd is %d\n", cmd); + } + break; + } + return ret; +} + +#ifdef CONFIG_COMPAT +static long vpu_compat_ioctl(struct file *filp, u32 cmd, ulong arg) +{ + long ret; + + arg = (ulong)compat_ptr(arg); + ret = vpu_ioctl(filp, cmd, arg); + return ret; +} +#endif + +static ssize_t vpu_write(struct file *filp, + const char *buf, + size_t len, + loff_t *ppos) +{ + enc_pr(LOG_INFO, "vpu_write len=%d\n", (int)len); + + if (!buf) { + enc_pr(LOG_ERROR, "vpu_write buf = NULL error\n"); + return -EFAULT; + } + + if (len == sizeof(struct vpu_bit_firmware_info_t)) { + struct vpu_bit_firmware_info_t *bit_firmware_info; + + bit_firmware_info = + kmalloc(sizeof(struct vpu_bit_firmware_info_t), + GFP_KERNEL); + if (!bit_firmware_info) { + enc_pr(LOG_ERROR, + "vpu_write bit_firmware_info allocation error\n"); + return -EFAULT; + } + + if (copy_from_user(bit_firmware_info, buf, len)) { + enc_pr(LOG_ERROR, + "vpu_write copy_from_user error for bit_firmware_info\n"); + return -EFAULT; + } + + if (bit_firmware_info->size == + sizeof(struct vpu_bit_firmware_info_t)) { + enc_pr(LOG_INFO, + "vpu_write set bit_firmware_info coreIdx=0x%x, ", + bit_firmware_info->core_idx); + enc_pr(LOG_INFO, + "reg_base_offset=0x%x size=0x%x, bit_code[0]=0x%x\n", + bit_firmware_info->reg_base_offset, + bit_firmware_info->size, + bit_firmware_info->bit_code[0]); + + if (bit_firmware_info->core_idx + > MAX_NUM_VPU_CORE) { + enc_pr(LOG_ERROR, + "vpu_write coreIdx[%d] is ", + bit_firmware_info->core_idx); + enc_pr(LOG_ERROR, + "exceeded than MAX_NUM_VPU_CORE[%d]\n", + MAX_NUM_VPU_CORE); + return -ENODEV; + } + + memcpy((void *)&s_bit_firmware_info + [bit_firmware_info->core_idx], + bit_firmware_info, + sizeof(struct vpu_bit_firmware_info_t)); + kfree(bit_firmware_info); + return len; + } + kfree(bit_firmware_info); + } + return -1; +} + +static s32 vpu_release(struct inode *inode, struct file *filp) +{ + s32 ret = 0; + ulong flags; + + enc_pr(LOG_DEBUG, "vpu_release\n"); + ret = down_interruptible(&s_vpu_sem); + if (ret == 0) { + vpu_free_buffers(filp); + vpu_free_instances(filp); + s_vpu_drv_context.open_count--; + if (s_vpu_drv_context.open_count == 0) { + if (s_instance_pool.base) { + enc_pr(LOG_DEBUG, "free instance pool\n"); + vfree((const void *)s_instance_pool.base); + s_instance_pool.base = 0; + } + if (s_common_memory.base) { + enc_pr(LOG_DEBUG, "free common memory\n"); + vpu_free_dma_buffer(&s_common_memory); + s_common_memory.base = 0; + } + + if (s_video_memory.base && !use_reserve) { + codec_mm_free_for_dma( + VPU_DEV_NAME, + (u32)s_video_memory.phys_addr); + vmem_exit(&s_vmem); + memset(&s_video_memory, + 0, sizeof(struct vpudrv_buffer_t)); + memset(&s_vmem, + 0, sizeof(struct video_mm_t)); + } + if ((s_vpu_irq >= 0) && (s_vpu_irq_requested == true)) { + free_irq(s_vpu_irq, &s_vpu_drv_context); + s_vpu_irq_requested = false; + } + spin_lock_irqsave(&s_vpu_lock, flags); + WRITE_AOREG(AO_RTI_GEN_PWR_ISO0, + READ_AOREG(AO_RTI_GEN_PWR_ISO0) | (0x3<<12)); + udelay(10); + + WRITE_VREG(DOS_MEM_PD_WAVE420L, 0xffffffff); +#ifndef VPU_SUPPORT_CLOCK_CONTROL + vpu_clk_config(0); +#endif + WRITE_AOREG(AO_RTI_GEN_PWR_SLEEP0, + READ_AOREG(AO_RTI_GEN_PWR_SLEEP0) | (0x3<<24)); + udelay(10); + spin_unlock_irqrestore(&s_vpu_lock, flags); + amports_switch_gate("vdec", 0); + } + } + up(&s_vpu_sem); + return 0; +} + +static s32 vpu_fasync(s32 fd, struct file *filp, s32 mode) +{ + struct vpu_drv_context_t *dev = + (struct vpu_drv_context_t *)filp->private_data; + return fasync_helper(fd, filp, mode, &dev->async_queue); +} + +static s32 vpu_map_to_register(struct file *fp, struct vm_area_struct *vm) +{ + ulong pfn; + + vm->vm_flags |= VM_IO | VM_RESERVED; + vm->vm_page_prot = + pgprot_noncached(vm->vm_page_prot); + pfn = s_vpu_register.phys_addr >> PAGE_SHIFT; + return remap_pfn_range(vm, vm->vm_start, pfn, + vm->vm_end - vm->vm_start, + vm->vm_page_prot) ? -EAGAIN : 0; +} + +static s32 vpu_map_to_physical_memory( + struct file *fp, struct vm_area_struct *vm) +{ + vm->vm_flags |= VM_IO | VM_RESERVED; + if (vm->vm_pgoff == + (s_common_memory.phys_addr >> PAGE_SHIFT)) { + vm->vm_page_prot = + pgprot_noncached(vm->vm_page_prot); + } else { + if (vpu_is_buffer_cached(fp, vm->vm_pgoff) == 0) + vm->vm_page_prot = + pgprot_noncached(vm->vm_page_prot); + } + /* vm->vm_page_prot = pgprot_writecombine(vm->vm_page_prot); */ + return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, + vm->vm_end - vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0; +} + +static s32 vpu_map_to_instance_pool_memory( + struct file *fp, struct vm_area_struct *vm) +{ + s32 ret; + long length = vm->vm_end - vm->vm_start; + ulong start = vm->vm_start; + s8 *vmalloc_area_ptr = (s8 *)s_instance_pool.base; + ulong pfn; + + vm->vm_flags |= VM_RESERVED; + + /* loop over all pages, map it page individually */ + while (length > 0) { + pfn = vmalloc_to_pfn(vmalloc_area_ptr); + ret = remap_pfn_range(vm, start, pfn, + PAGE_SIZE, PAGE_SHARED); + if (ret < 0) + return ret; + start += PAGE_SIZE; + vmalloc_area_ptr += PAGE_SIZE; + length -= PAGE_SIZE; + } + return 0; +} + +/* + * @brief memory map interface for vpu file operation + * @return 0 on success or negative error code on error + */ +static s32 vpu_mmap(struct file *fp, struct vm_area_struct *vm) +{ + /* if (vm->vm_pgoff == (s_vpu_register.phys_addr >> PAGE_SHIFT)) */ + if ((vm->vm_end - vm->vm_start == s_vpu_register.size + 1) && + (vm->vm_pgoff == 0)) { + vm->vm_pgoff = (s_vpu_register.phys_addr >> PAGE_SHIFT); + return vpu_map_to_register(fp, vm); + } + + if (vm->vm_pgoff == 0) + return vpu_map_to_instance_pool_memory(fp, vm); + + return vpu_map_to_physical_memory(fp, vm); +} + +static const struct file_operations vpu_fops = { + .owner = THIS_MODULE, + .open = vpu_open, + .release = vpu_release, + .write = vpu_write, + .unlocked_ioctl = vpu_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = vpu_compat_ioctl, +#endif + .fasync = vpu_fasync, + .mmap = vpu_mmap, +}; + +static ssize_t hevcenc_status_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return snprintf(buf, 40, "hevcenc_status_show\n"); +} + +static struct class_attribute hevcenc_class_attrs[] = { + __ATTR(encode_status, + S_IRUGO | S_IWUSR, + hevcenc_status_show, + NULL), + __ATTR_NULL +}; + +static struct class hevcenc_class = { + .name = VPU_CLASS_NAME, + .class_attrs = hevcenc_class_attrs, +}; + +s32 init_HevcEnc_device(void) +{ + s32 r = 0; + + r = register_chrdev(0, VPU_DEV_NAME, &vpu_fops); + if (r <= 0) { + enc_pr(LOG_ERROR, "register hevcenc device error.\n"); + return r; + } + s_vpu_major = r; + + r = class_register(&hevcenc_class); + if (r < 0) { + enc_pr(LOG_ERROR, "error create hevcenc class.\n"); + return r; + } + + hevcenc_dev = device_create(&hevcenc_class, NULL, + MKDEV(s_vpu_major, 0), NULL, + VPU_DEV_NAME); + + if (IS_ERR(hevcenc_dev)) { + enc_pr(LOG_ERROR, "create hevcenc device error.\n"); + class_unregister(&hevcenc_class); + return -1; + } + return r; +} + +s32 uninit_HevcEnc_device(void) +{ + if (hevcenc_dev) + device_destroy(&hevcenc_class, MKDEV(s_vpu_major, 0)); + + class_destroy(&hevcenc_class); + + unregister_chrdev(s_vpu_major, VPU_DEV_NAME); + return 0; +} + +static s32 hevc_mem_device_init( + struct reserved_mem *rmem, struct device *dev) +{ + s32 r; + + if (!rmem) { + enc_pr(LOG_ERROR, + "Can not obtain I/O memory, will allocate hevc buffer!\n"); + r = -EFAULT; + return r; + } + + if ((!rmem->base) || + (rmem->size < VPU_INIT_VIDEO_MEMORY_SIZE_IN_BYTE)) { + enc_pr(LOG_ERROR, + "memory range error, 0x%lx - 0x%lx\n", + (ulong)rmem->base, (ulong)rmem->size); + r = -EFAULT; + return r; + } + r = 0; + s_video_memory.size = rmem->size; + s_video_memory.phys_addr = (ulong)rmem->base; + s_video_memory.base = + (ulong)phys_to_virt(s_video_memory.phys_addr); + if (!s_video_memory.base) { + enc_pr(LOG_ERROR, "fail to remap video memory "); + enc_pr(LOG_ERROR, + "physical phys_addr=0x%lx, base=0x%lx, size=0x%x\n", + (ulong)s_video_memory.phys_addr, + (ulong)s_video_memory.base, + (u32)s_video_memory.size); + s_video_memory.phys_addr = 0; + r = -EFAULT; + } + return r; +} + +static s32 vpu_probe(struct platform_device *pdev) +{ + s32 err = 0, irq, reg_count, idx; + struct resource res; + struct device_node *np, *child; + + enc_pr(LOG_DEBUG, "vpu_probe\n"); + + s_vpu_major = 0; + use_reserve = false; + s_vpu_irq = -1; + cma_pool_size = 0; + s_vpu_irq_requested = false; + s_vpu_open_ref_count = 0; + hevcenc_dev = NULL; + hevc_pdev = NULL; + memset(&s_video_memory, 0, sizeof(struct vpudrv_buffer_t)); + memset(&s_vpu_register, 0, sizeof(struct vpudrv_buffer_t)); + memset(&s_vmem, 0, sizeof(struct video_mm_t)); + memset(&s_bit_firmware_info[0], 0, sizeof(s_bit_firmware_info)); + memset(&res, 0, sizeof(struct resource)); + + idx = of_reserved_mem_device_init(&pdev->dev); + if (idx != 0) { + enc_pr(LOG_DEBUG, + "HevcEnc reserved memory config fail.\n"); + } else if (s_video_memory.phys_addr) { + use_reserve = true; + } + + if (use_reserve == false) { +#ifndef CONFIG_CMA + enc_pr(LOG_ERROR, + "HevcEnc reserved memory is invaild, probe fail!\n"); + err = -EFAULT; + goto ERROR_PROVE_DEVICE; +#else + cma_pool_size = + (codec_mm_get_total_size() > + (VPU_INIT_VIDEO_MEMORY_SIZE_IN_BYTE)) ? + (VPU_INIT_VIDEO_MEMORY_SIZE_IN_BYTE) : + codec_mm_get_total_size(); + enc_pr(LOG_DEBUG, + "HevcEnc - cma memory pool size: %d MB\n", + (u32)cma_pool_size / SZ_1M); +#endif + } + + /* get interrupt resource */ + irq = platform_get_irq_byname(pdev, "wave420l_irq"); + if (irq < 0) { + enc_pr(LOG_ERROR, "get HevcEnc irq resource error\n"); + err = -ENXIO; + goto ERROR_PROVE_DEVICE; + } + s_vpu_irq = irq; + enc_pr(LOG_DEBUG, "HevcEnc - wave420l_irq: %d\n", s_vpu_irq); +#if 0 + rstc = devm_reset_control_get(&pdev->dev, "HevcEnc"); + if (IS_ERR(rstc)) { + enc_pr(LOG_ERROR, + "get HevcEnc rstc error: %lx\n", PTR_ERR(rstc)); + rstc = NULL; + err = -ENOENT; + goto ERROR_PROVE_DEVICE; + } + reset_control_assert(rstc); + s_vpu_rstc = rstc; + + clk = clk_get(&pdev->dev, "clk_HevcEnc"); + if (IS_ERR(clk)) { + enc_pr(LOG_ERROR, "cannot get clock\n"); + clk = NULL; + err = -ENOENT; + goto ERROR_PROVE_DEVICE; + } + s_vpu_clk = clk; +#endif + +#ifdef VPU_SUPPORT_CLOCK_CONTROL +#else + vpu_clk_config(1); +#endif + + np = pdev->dev.of_node; + reg_count = 0; + for_each_child_of_node(np, child) { + if (of_address_to_resource(child, 0, &res) + || (reg_count > 1)) { + enc_pr(LOG_ERROR, + "no reg ranges or more reg ranges %d\n", + reg_count); + err = -ENXIO; + goto ERROR_PROVE_DEVICE; + } + /* if platform driver is implemented */ + if (res.start != 0) { + s_vpu_register.phys_addr = res.start; + s_vpu_register.virt_addr = + (ulong)ioremap_nocache( + res.start, resource_size(&res)); + s_vpu_register.size = res.end - res.start; + enc_pr(LOG_DEBUG, + "vpu base address get from platform driver "); + enc_pr(LOG_DEBUG, + "physical base addr=0x%lx, virtual base=0x%lx\n", + s_vpu_register.phys_addr, + s_vpu_register.virt_addr); + } else { + s_vpu_register.phys_addr = VPU_REG_BASE_ADDR; + s_vpu_register.virt_addr = + (ulong)ioremap_nocache( + s_vpu_register.phys_addr, VPU_REG_SIZE); + s_vpu_register.size = VPU_REG_SIZE; + enc_pr(LOG_DEBUG, + "vpu base address get from defined value "); + enc_pr(LOG_DEBUG, + "physical base addr=0x%lx, virtual base=0x%lx\n", + s_vpu_register.phys_addr, + s_vpu_register.virt_addr); + } + reg_count++; + } + + /* get the major number of the character device */ + if (init_HevcEnc_device()) { + err = -EBUSY; + enc_pr(LOG_ERROR, "could not allocate major number\n"); + goto ERROR_PROVE_DEVICE; + } + enc_pr(LOG_INFO, "SUCCESS alloc_chrdev_region\n"); + + init_waitqueue_head(&s_interrupt_wait_q); + tasklet_init(&hevc_tasklet, + hevcenc_isr_tasklet, + (ulong)&s_vpu_drv_context); + s_common_memory.base = 0; + s_instance_pool.base = 0; + + if (use_reserve == true) { + if (vmem_init(&s_vmem, s_video_memory.phys_addr, + s_video_memory.size) < 0) { + enc_pr(LOG_ERROR, "fail to init vmem system\n"); + goto ERROR_PROVE_DEVICE; + } + enc_pr(LOG_DEBUG, + "success to probe vpu device with video memory "); + enc_pr(LOG_DEBUG, + "phys_addr=0x%lx, base = 0x%lx\n", + (ulong)s_video_memory.phys_addr, + (ulong)s_video_memory.base); + } else + enc_pr(LOG_DEBUG, + "success to probe vpu device with video memory from cma\n"); + hevc_pdev = pdev; + return 0; + +ERROR_PROVE_DEVICE: + if (s_vpu_register.virt_addr) { + iounmap((void *)s_vpu_register.virt_addr); + memset(&s_vpu_register, 0, sizeof(struct vpudrv_buffer_t)); + } + + if (s_video_memory.base) { + vmem_exit(&s_vmem); + memset(&s_video_memory, 0, sizeof(struct vpudrv_buffer_t)); + memset(&s_vmem, 0, sizeof(struct video_mm_t)); + } + + vpu_clk_config(0); + + if (s_vpu_irq_requested == true) { + if (s_vpu_irq >= 0) { + free_irq(s_vpu_irq, &s_vpu_drv_context); + s_vpu_irq = -1; + } + s_vpu_irq_requested = false; + } + uninit_HevcEnc_device(); + return err; +} + +static s32 vpu_remove(struct platform_device *pdev) +{ + enc_pr(LOG_DEBUG, "vpu_remove\n"); + + if (s_instance_pool.base) { + vfree((const void *)s_instance_pool.base); + s_instance_pool.base = 0; + } + + if (s_common_memory.base) { + vpu_free_dma_buffer(&s_common_memory); + s_common_memory.base = 0; + } + + if (s_video_memory.base) { + if (!use_reserve) + codec_mm_free_for_dma( + VPU_DEV_NAME, + (u32)s_video_memory.phys_addr); + vmem_exit(&s_vmem); + memset(&s_video_memory, + 0, sizeof(struct vpudrv_buffer_t)); + memset(&s_vmem, + 0, sizeof(struct video_mm_t)); + } + + if (s_vpu_irq_requested == true) { + if (s_vpu_irq >= 0) { + free_irq(s_vpu_irq, &s_vpu_drv_context); + s_vpu_irq = -1; + } + s_vpu_irq_requested = false; + } + + if (s_vpu_register.virt_addr) { + iounmap((void *)s_vpu_register.virt_addr); + memset(&s_vpu_register, + 0, sizeof(struct vpudrv_buffer_t)); + } + hevc_pdev = NULL; + vpu_clk_config(0); + + uninit_HevcEnc_device(); + return 0; +} + +#ifdef CONFIG_PM +static void Wave4BitIssueCommand(u32 core, u32 cmd) +{ + WriteVpuRegister(W4_VPU_BUSY_STATUS, 1); + WriteVpuRegister(W4_CORE_INDEX, 0); + /* coreIdx = ReadVpuRegister(W4_VPU_BUSY_STATUS); */ + /* coreIdx = 0; */ + /* WriteVpuRegister(W4_INST_INDEX, + * (instanceIndex & 0xffff) | (codecMode << 16)); + */ + WriteVpuRegister(W4_COMMAND, cmd); + WriteVpuRegister(W4_VPU_HOST_INT_REQ, 1); +} + +static s32 vpu_suspend(struct platform_device *pdev, pm_message_t state) +{ + u32 core; + ulong timeout = jiffies + HZ; /* vpu wait timeout to 1sec */ + + enc_pr(LOG_DEBUG, "vpu_suspend\n"); + + vpu_clk_config(1); + + if (s_vpu_open_ref_count > 0) { + for (core = 0; core < MAX_NUM_VPU_CORE; core++) { + if (s_bit_firmware_info[core].size == 0) + continue; + while (ReadVpuRegister(W4_VPU_BUSY_STATUS)) { + if (time_after(jiffies, timeout)) { + enc_pr(LOG_ERROR, + "SLEEP_VPU BUSY timeout"); + goto DONE_SUSPEND; + } + } + Wave4BitIssueCommand(core, W4_CMD_SLEEP_VPU); + + while (ReadVpuRegister(W4_VPU_BUSY_STATUS)) { + if (time_after(jiffies, timeout)) { + enc_pr(LOG_ERROR, + "SLEEP_VPU BUSY timeout"); + goto DONE_SUSPEND; + } + } + if (ReadVpuRegister(W4_RET_SUCCESS) == 0) { + enc_pr(LOG_ERROR, + "SLEEP_VPU failed [0x%x]", + ReadVpuRegister(W4_RET_FAIL_REASON)); + goto DONE_SUSPEND; + } + } + } + + vpu_clk_config(0); + return 0; + +DONE_SUSPEND: + vpu_clk_config(0); + return -EAGAIN; +} +static s32 vpu_resume(struct platform_device *pdev) +{ + u32 i; + u32 core; + u32 val; + ulong timeout = jiffies + HZ; /* vpu wait timeout to 1sec */ + ulong code_base; + u32 code_size; + u32 remap_size; + u32 regVal; + u32 hwOption = 0; + + enc_pr(LOG_DEBUG, "vpu_resume\n"); + + vpu_clk_config(1); + + for (core = 0; core < MAX_NUM_VPU_CORE; core++) { + if (s_bit_firmware_info[core].size == 0) + continue; + code_base = s_common_memory.phys_addr; + /* ALIGN TO 4KB */ + code_size = (s_common_memory.size & ~0xfff); + if (code_size < s_bit_firmware_info[core].size * 2) + goto DONE_WAKEUP; + + /*---- LOAD BOOT CODE */ + for (i = 0; i < 512; i += 2) { + val = s_bit_firmware_info[core].bit_code[i]; + val |= (s_bit_firmware_info[core].bit_code[i+1] << 16); + WriteVpu(code_base+(i*2), val); + } + + regVal = 0; + WriteVpuRegister(W4_PO_CONF, regVal); + + /* Reset All blocks */ + regVal = 0x7ffffff; + WriteVpuRegister(W4_VPU_RESET_REQ, regVal); + + /* Waiting reset done */ + while (ReadVpuRegister(W4_VPU_RESET_STATUS)) { + if (time_after(jiffies, timeout)) + goto DONE_WAKEUP; + } + + WriteVpuRegister(W4_VPU_RESET_REQ, 0); + + /* remap page size */ + remap_size = (code_size >> 12) & 0x1ff; + regVal = 0x80000000 | (W4_REMAP_CODE_INDEX<<12) + | (0 << 16) | (1<<11) | remap_size; + WriteVpuRegister(W4_VPU_REMAP_CTRL, regVal); + /* DO NOT CHANGE! */ + WriteVpuRegister(W4_VPU_REMAP_VADDR, 0x00000000); + WriteVpuRegister(W4_VPU_REMAP_PADDR, code_base); + WriteVpuRegister(W4_ADDR_CODE_BASE, code_base); + WriteVpuRegister(W4_CODE_SIZE, code_size); + WriteVpuRegister(W4_CODE_PARAM, 0); + WriteVpuRegister(W4_INIT_VPU_TIME_OUT_CNT, timeout); + WriteVpuRegister(W4_HW_OPTION, hwOption); + + /* Interrupt */ + regVal = (1 << W4_INT_DEC_PIC_HDR); + regVal |= (1 << W4_INT_DEC_PIC); + regVal |= (1 << W4_INT_QUERY_DEC); + regVal |= (1 << W4_INT_SLEEP_VPU); + regVal |= (1 << W4_INT_BSBUF_EMPTY); + regVal = 0xfffffefe; + WriteVpuRegister(W4_VPU_VINT_ENABLE, regVal); + Wave4BitIssueCommand(core, W4_CMD_INIT_VPU); + WriteVpuRegister(W4_VPU_REMAP_CORE_START, 1); + while (ReadVpuRegister(W4_VPU_BUSY_STATUS)) { + if (time_after(jiffies, timeout)) + goto DONE_WAKEUP; + } + + if (ReadVpuRegister(W4_RET_SUCCESS) == 0) { + enc_pr(LOG_ERROR, + "WAKEUP_VPU failed [0x%x]", + ReadVpuRegister(W4_RET_FAIL_REASON)); + goto DONE_WAKEUP; + } + } + + if (s_vpu_open_ref_count == 0) + vpu_clk_config(0); +DONE_WAKEUP: + if (s_vpu_open_ref_count > 0) + vpu_clk_config(1); + return 0; +} +#else +#define vpu_suspend NULL +#define vpu_resume NULL +#endif /* !CONFIG_PM */ + +static const struct of_device_id cnm_hevcenc_dt_match[] = { + { + .compatible = "cnm, HevcEnc", + }, + {}, +}; + +static struct platform_driver vpu_driver = { + .driver = { + .name = VPU_PLATFORM_DEVICE_NAME, + .of_match_table = cnm_hevcenc_dt_match, + }, + .probe = vpu_probe, + .remove = vpu_remove, + .suspend = vpu_suspend, + .resume = vpu_resume, +}; + +static s32 __init vpu_init(void) +{ + s32 res; + + enc_pr(LOG_DEBUG, "vpu_init\n"); + + if ((get_cpu_type() != MESON_CPU_MAJOR_ID_GXM) + && (get_cpu_type() != MESON_CPU_MAJOR_ID_G12A) + && (get_cpu_type() != MESON_CPU_MAJOR_ID_GXLX) + && (get_cpu_type() != MESON_CPU_MAJOR_ID_G12B)) { + enc_pr(LOG_DEBUG, + "The chip is not support hevc encoder\n"); + return -1; + } + if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A) { + if ((READ_EFUSE_REG(EFUSE_LIC2) >> 12) & 1) { + enc_pr(LOG_DEBUG, + "Chip efuse disabled H265\n"); + return -1; + } + } + + res = platform_driver_register(&vpu_driver); + enc_pr(LOG_INFO, + "end vpu_init result=0x%x\n", res); + return res; +} + +static void __exit vpu_exit(void) +{ + enc_pr(LOG_DEBUG, "vpu_exit\n"); + if (get_cpu_type() == MESON_CPU_MAJOR_ID_GXM) + platform_driver_unregister(&vpu_driver); +} + +static const struct reserved_mem_ops rmem_hevc_ops = { + .device_init = hevc_mem_device_init, +}; + +static s32 __init hevc_mem_setup(struct reserved_mem *rmem) +{ + rmem->ops = &rmem_hevc_ops; + enc_pr(LOG_DEBUG, "HevcEnc reserved mem setup.\n"); + return 0; +} + +module_param(print_level, uint, 0664); +MODULE_PARM_DESC(print_level, "\n print_level\n"); + +module_param(clock_level, uint, 0664); +MODULE_PARM_DESC(clock_level, "\n clock_level\n"); + +MODULE_AUTHOR("Amlogic using C&M VPU, Inc."); +MODULE_DESCRIPTION("VPU linux driver"); +MODULE_LICENSE("GPL"); + +module_init(vpu_init); +module_exit(vpu_exit); +RESERVEDMEM_OF_DECLARE(cnm_hevc, "cnm, HevcEnc-memory", hevc_mem_setup); diff --git a/drivers/amlogic/media_modules/frame_sink/encoder/h265/vpu.h b/drivers/amlogic/media_modules/frame_sink/encoder/h265/vpu.h new file mode 100644 index 000000000000..9c29a430f4e0 --- /dev/null +++ b/drivers/amlogic/media_modules/frame_sink/encoder/h265/vpu.h @@ -0,0 +1,306 @@ +/* + * vpu.h + * + * linux device driver for VPU. + * + * Copyright (C) 2006 - 2013 CHIPS&MEDIA INC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __VPU_DRV_H__ +#define __VPU_DRV_H__ + +#include +#include +#include + +#define MAX_INST_HANDLE_SIZE (32*1024) +#define MAX_NUM_INSTANCE 4 +#define MAX_NUM_VPU_CORE 1 + +#define W4_CMD_INIT_VPU (0x0001) +#define W4_CMD_SLEEP_VPU (0x0400) +#define W4_CMD_WAKEUP_VPU (0x0800) + +/* GXM: 2000/10 = 200M */ +#define HevcEnc_L0() WRITE_HHI_REG(HHI_WAVE420L_CLK_CNTL, \ + (3 << 25) | (1 << 16) | (3 << 9) | (1 << 0)) +/* GXM: 2000/8 = 250M */ +#define HevcEnc_L1() WRITE_HHI_REG(HHI_WAVE420L_CLK_CNTL, \ + (1 << 25) | (1 << 16) | (1 << 9) | (1 << 0)) +/* GXM: 2000/7 = 285M */ +#define HevcEnc_L2() WRITE_HHI_REG(HHI_WAVE420L_CLK_CNTL, \ + (4 << 25) | (0 << 16) | (4 << 9) | (0 << 0)) +/*GXM: 2000/6 = 333M */ +#define HevcEnc_L3() WRITE_HHI_REG(HHI_WAVE420L_CLK_CNTL, \ + (2 << 25) | (1 << 16) | (2 << 9) | (1 << 0)) +/* GXM: 2000/5 = 400M */ +#define HevcEnc_L4() WRITE_HHI_REG(HHI_WAVE420L_CLK_CNTL, \ + (3 << 25) | (0 << 16) | (3 << 9) | (0 << 0)) +/* GXM: 2000/4 = 500M */ +#define HevcEnc_L5() WRITE_HHI_REG(HHI_WAVE420L_CLK_CNTL, \ + (1 << 25) | (0 << 16) | (1 << 9) | (0 << 0)) +/* GXM: 2000/3 = 667M */ +#define HevcEnc_L6() WRITE_HHI_REG(HHI_WAVE420L_CLK_CNTL, \ + (2 << 25) | (0 << 16) | (2 << 9) | (0 << 0)) + +#define HevcEnc_clock_enable(level) \ + do { \ + WRITE_HHI_REG(HHI_WAVE420L_CLK_CNTL, \ + READ_HHI_REG(HHI_WAVE420L_CLK_CNTL) \ + & (~(1 << 8)) & (~(1 << 24))); \ + if (level == 0) \ + HevcEnc_L0(); \ + else if (level == 1) \ + HevcEnc_L1(); \ + else if (level == 2) \ + HevcEnc_L2(); \ + else if (level == 3) \ + HevcEnc_L3(); \ + else if (level == 4) \ + HevcEnc_L4(); \ + else if (level == 5) \ + HevcEnc_L5(); \ + else if (level == 6) \ + HevcEnc_L6(); \ + WRITE_HHI_REG(HHI_WAVE420L_CLK_CNTL, \ + READ_HHI_REG(HHI_WAVE420L_CLK_CNTL) \ + | (1 << 8) | (1 << 24)); \ + } while (0) + +#define HevcEnc_clock_disable() \ + WRITE_HHI_REG(HHI_WAVE420L_CLK_CNTL, \ + READ_HHI_REG(HHI_WAVE420L_CLK_CNTL) \ + & (~(1 << 8)) & (~(1 << 24))) + +/* ACLK 667MHZ */ +#define HevcEnc_MoreClock_enable() \ + do { \ + WRITE_HHI_REG(HHI_WAVE420L_CLK_CNTL2, \ + READ_HHI_REG(HHI_WAVE420L_CLK_CNTL2) \ + & (~(1 << 8))); \ + WRITE_HHI_REG(HHI_WAVE420L_CLK_CNTL2, \ + (2 << 9) | (0 << 0)); \ + WRITE_HHI_REG(HHI_WAVE420L_CLK_CNTL2, \ + READ_HHI_REG(HHI_WAVE420L_CLK_CNTL2) \ + | (1 << 8)); \ + } while (0) + +#define HevcEnc_MoreClock_disable() \ + WRITE_HHI_REG(HHI_WAVE420L_CLK_CNTL2, \ + READ_HHI_REG(HHI_WAVE420L_CLK_CNTL2) \ + & (~(1 << 8))) + +struct compat_vpudrv_buffer_t { + u32 size; + u32 cached; + compat_ulong_t phys_addr; + compat_ulong_t base; /* kernel logical address in use kernel */ + compat_ulong_t virt_addr; /* virtual user space address */ +}; + +struct vpudrv_buffer_t { + u32 size; + u32 cached; + ulong phys_addr; + ulong base; /* kernel logical address in use kernel */ + ulong virt_addr; /* virtual user space address */ +}; + +struct vpu_bit_firmware_info_t { + u32 size; /* size of this structure*/ + u32 core_idx; + u32 reg_base_offset; + u16 bit_code[512]; +}; + +struct vpudrv_inst_info_t { + u32 core_idx; + u32 inst_idx; + s32 inst_open_count; /* for output only*/ +}; + +struct vpudrv_intr_info_t { + u32 timeout; + s32 intr_reason; +}; + +struct vpu_drv_context_t { + struct fasync_struct *async_queue; + ulong interrupt_reason; + u32 open_count; /*!<< device reference count. Not instance count */ +}; + +/* To track the allocated memory buffer */ +struct vpudrv_buffer_pool_t { + struct list_head list; + struct vpudrv_buffer_t vb; + struct file *filp; +}; + +/* To track the instance index and buffer in instance pool */ +struct vpudrv_instanace_list_t { + struct list_head list; + ulong inst_idx; + ulong core_idx; + struct file *filp; +}; + +struct vpudrv_instance_pool_t { + u8 codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE]; +}; + +#define VPUDRV_BUF_LEN struct vpudrv_buffer_t +#define VPUDRV_BUF_LEN32 struct compat_vpudrv_buffer_t +#define VPUDRV_INST_LEN struct vpudrv_inst_info_t + +#define VDI_MAGIC 'V' +#define VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY \ + _IOW(VDI_MAGIC, 0, VPUDRV_BUF_LEN) + +#define VDI_IOCTL_FREE_PHYSICALMEMORY \ + _IOW(VDI_MAGIC, 1, VPUDRV_BUF_LEN) + +#define VDI_IOCTL_WAIT_INTERRUPT \ + _IOW(VDI_MAGIC, 2, struct vpudrv_intr_info_t) + +#define VDI_IOCTL_SET_CLOCK_GATE \ + _IOW(VDI_MAGIC, 3, u32) + +#define VDI_IOCTL_RESET \ + _IOW(VDI_MAGIC, 4, u32) + +#define VDI_IOCTL_GET_INSTANCE_POOL \ + _IOW(VDI_MAGIC, 5, VPUDRV_BUF_LEN) + +#define VDI_IOCTL_GET_COMMON_MEMORY \ + _IOW(VDI_MAGIC, 6, VPUDRV_BUF_LEN) + +#define VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO \ + _IOW(VDI_MAGIC, 8, VPUDRV_BUF_LEN) + +#define VDI_IOCTL_OPEN_INSTANCE \ + _IOW(VDI_MAGIC, 9, VPUDRV_INST_LEN) + +#define VDI_IOCTL_CLOSE_INSTANCE \ + _IOW(VDI_MAGIC, 10, VPUDRV_INST_LEN) + +#define VDI_IOCTL_GET_INSTANCE_NUM \ + _IOW(VDI_MAGIC, 11, VPUDRV_INST_LEN) + +#define VDI_IOCTL_GET_REGISTER_INFO \ + _IOW(VDI_MAGIC, 12, VPUDRV_BUF_LEN) + +#define VDI_IOCTL_FLUSH_BUFFER \ + _IOW(VDI_MAGIC, 13, VPUDRV_BUF_LEN) + +#define VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY32 \ + _IOW(VDI_MAGIC, 0, VPUDRV_BUF_LEN32) + +#define VDI_IOCTL_FREE_PHYSICALMEMORY32 \ + _IOW(VDI_MAGIC, 1, VPUDRV_BUF_LEN32) + +#define VDI_IOCTL_GET_INSTANCE_POOL32 \ + _IOW(VDI_MAGIC, 5, VPUDRV_BUF_LEN32) + +#define VDI_IOCTL_GET_COMMON_MEMORY32 \ + _IOW(VDI_MAGIC, 6, VPUDRV_BUF_LEN32) + +#define VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO32 \ + _IOW(VDI_MAGIC, 8, VPUDRV_BUF_LEN32) + +#define VDI_IOCTL_GET_REGISTER_INFO32 \ + _IOW(VDI_MAGIC, 12, VPUDRV_BUF_LEN32) + +#define VDI_IOCTL_FLUSH_BUFFER32 \ + _IOW(VDI_MAGIC, 13, VPUDRV_BUF_LEN32) + +enum { + W4_INT_INIT_VPU = 0, + W4_INT_DEC_PIC_HDR = 1, + W4_INT_SET_PARAM = 1, + W4_INT_ENC_INIT_SEQ = 1, + W4_INT_FINI_SEQ = 2, + W4_INT_DEC_PIC = 3, + W4_INT_ENC_PIC = 3, + W4_INT_SET_FRAMEBUF = 4, + W4_INT_FLUSH_DEC = 5, + W4_INT_ENC_SLICE_INT = 7, + W4_INT_GET_FW_VERSION = 8, + W4_INT_QUERY_DEC = 9, + W4_INT_SLEEP_VPU = 10, + W4_INT_WAKEUP_VPU = 11, + W4_INT_CHANGE_INT = 12, + W4_INT_CREATE_INSTANCE = 14, + W4_INT_BSBUF_EMPTY = 15, + /*!<< Bitstream buffer empty[dec]/full[enc] */ +}; + +/* WAVE4 registers */ +#define VPU_REG_BASE_ADDR 0xc8810000 +#define VPU_REG_SIZE (0x4000 * MAX_NUM_VPU_CORE) + +#define W4_REG_BASE 0x0000 +#define W4_VPU_BUSY_STATUS (W4_REG_BASE + 0x0070) +#define W4_VPU_INT_REASON_CLEAR (W4_REG_BASE + 0x0034) +#define W4_VPU_VINT_CLEAR (W4_REG_BASE + 0x003C) +#define W4_VPU_VPU_INT_STS (W4_REG_BASE + 0x0044) +#define W4_VPU_INT_REASON (W4_REG_BASE + 0x004c) + +#define W4_RET_SUCCESS (W4_REG_BASE + 0x0110) +#define W4_RET_FAIL_REASON (W4_REG_BASE + 0x0114) + +/* WAVE4 INIT, WAKEUP */ +#define W4_PO_CONF (W4_REG_BASE + 0x0000) +#define W4_VCPU_CUR_PC (W4_REG_BASE + 0x0004) + +#define W4_VPU_VINT_ENABLE (W4_REG_BASE + 0x0048) + +#define W4_VPU_RESET_REQ (W4_REG_BASE + 0x0050) +#define W4_VPU_RESET_STATUS (W4_REG_BASE + 0x0054) + +#define W4_VPU_REMAP_CTRL (W4_REG_BASE + 0x0060) +#define W4_VPU_REMAP_VADDR (W4_REG_BASE + 0x0064) +#define W4_VPU_REMAP_PADDR (W4_REG_BASE + 0x0068) +#define W4_VPU_REMAP_CORE_START (W4_REG_BASE + 0x006C) +#define W4_VPU_BUSY_STATUS (W4_REG_BASE + 0x0070) + +#define W4_HW_OPTION (W4_REG_BASE + 0x0124) +#define W4_CODE_SIZE (W4_REG_BASE + 0x011C) +/* Note: W4_INIT_CODE_BASE_ADDR should be aligned to 4KB */ +#define W4_ADDR_CODE_BASE (W4_REG_BASE + 0x0118) +#define W4_CODE_PARAM (W4_REG_BASE + 0x0120) +#define W4_INIT_VPU_TIME_OUT_CNT (W4_REG_BASE + 0x0134) + +/* WAVE4 Wave4BitIssueCommand */ +#define W4_CORE_INDEX (W4_REG_BASE + 0x0104) +#define W4_INST_INDEX (W4_REG_BASE + 0x0108) +#define W4_COMMAND (W4_REG_BASE + 0x0100) +#define W4_VPU_HOST_INT_REQ (W4_REG_BASE + 0x0038) + +#define W4_BS_RD_PTR (W4_REG_BASE + 0x0130) +#define W4_BS_WR_PTR (W4_REG_BASE + 0x0134) +#define W4_RET_ENC_PIC_BYTE (W4_REG_BASE + 0x01C8) + +#define W4_REMAP_CODE_INDEX 0 + +#define ReadVpuRegister(addr) \ + readl((void __iomem *)(s_vpu_register.virt_addr \ + + s_bit_firmware_info[core].reg_base_offset + addr)) + +#define WriteVpuRegister(addr, val) \ + writel((u32)val, (void __iomem *)(s_vpu_register.virt_addr \ + + s_bit_firmware_info[core].reg_base_offset + addr)) + +#define WriteVpu(addr, val) writel((u32)val, (void __iomem *)addr) +#endif diff --git a/drivers/amlogic/media_modules/include/dummy-for-git-empty-dir b/drivers/amlogic/media_modules/include/dummy-for-git-empty-dir new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/drivers/amlogic/media_modules/stream_input/Makefile b/drivers/amlogic/media_modules/stream_input/Makefile new file mode 100644 index 000000000000..fdc41621e46f --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/Makefile @@ -0,0 +1,17 @@ +obj-m += stream_input.o + +stream_input-objs += amports/amstream.o +stream_input-objs += amports/amstream_profile.o +stream_input-objs += amports/adec.o +stream_input-objs += parser/thread_rw.o +stream_input-objs += parser/streambuf.o +stream_input-objs += parser/esparser.o +stream_input-objs += parser/tsdemux.o +stream_input-objs += parser/psparser.o +stream_input-objs += parser/rmparser.o + +obj-y += parser/hw_demux/ +obj-y += tv_frontend/ +# obj-y += box-frontend/avl6211/ +# obj-y += box-frontend/atbm8881/ +# obj-y += box-frontend/avl68xx/ \ No newline at end of file diff --git a/drivers/amlogic/media_modules/stream_input/amports/Makefile b/drivers/amlogic/media_modules/stream_input/amports/Makefile new file mode 100644 index 000000000000..55fbdce8aa7a --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/amports/Makefile @@ -0,0 +1,2 @@ +obj-y += amports.o +amports-objs += amstream.o amstream_profile.o adec.o diff --git a/drivers/amlogic/media_modules/stream_input/amports/adec.c b/drivers/amlogic/media_modules/stream_input/amports/adec.c new file mode 100644 index 000000000000..b1bd0726fad8 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/amports/adec.c @@ -0,0 +1,393 @@ +/* + * drivers/amlogic/media/stream_input/amports/adec.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../parser/streambuf.h" +#include +#include +#include "amports_priv.h" + +#define INFO_VALID ((astream_dev) && (astream_dev->format)) + +struct astream_device_s { + char *name; + char *format; + s32 channum; + s32 samplerate; + s32 datawidth; + int offset; + + struct device dev; +}; + +static char *astream_format[] = { + "amadec_mpeg", + "amadec_pcm_s16le", + "amadec_aac", + "amadec_ac3", + "amadec_alaw", + "amadec_mulaw", + "amadec_dts", + "amadec_pcm_s16be", + "amadec_flac", + "amadec_cook", + "amadec_pcm_u8", + "amadec_adpcm", + "amadec_amr", + "amadec_raac", + "amadec_wma", + "amadec_wmapro", + "amadec_pcm_bluray", + "amadec_alac", + "amadec_vorbis", + "amadec_aac_latm", + "amadec_ape", + "amadec_eac3", + "amadec_pcm_widi", + "amadec_dra", + "amadec_sipr", + "amadec_truehd", + "amadec_mpeg1", + "amadec_mpeg2", + "amadec_wmavoi", + "amadec_wmalossless", + "amadec_pcm_s24le", + "adec_max" +}; + +static const char *na_string = "NA"; +static struct astream_device_s *astream_dev; + +static ssize_t format_show(struct class *class, struct class_attribute *attr, + char *buf) +{ + if (INFO_VALID && astream_dev->format) + return sprintf(buf, "%s\n", astream_dev->format); + else + return sprintf(buf, "%s\n", na_string); +} + +static ssize_t channum_show(struct class *class, struct class_attribute *attr, + char *buf) +{ + if (INFO_VALID) + return sprintf(buf, "%u\n", astream_dev->channum); + else + return sprintf(buf, "%s\n", na_string); +} + +static ssize_t samplerate_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + if (INFO_VALID) + return sprintf(buf, "%u\n", astream_dev->samplerate); + else + return sprintf(buf, "%s\n", na_string); +} + +static ssize_t datawidth_show(struct class *class, + struct class_attribute *attr, + char *buf) +{ + if (INFO_VALID) + return sprintf(buf, "%u\n", astream_dev->datawidth); + else + return sprintf(buf, "%s\n", na_string); +} + +static ssize_t pts_show(struct class *class, struct class_attribute *attr, + char *buf) +{ + u32 pts; + u32 pts_margin = 0; + + if (astream_dev->samplerate <= 12000) + pts_margin = 512; + + if (INFO_VALID && (pts_lookup(PTS_TYPE_AUDIO, &pts, pts_margin) >= 0)) + return sprintf(buf, "0x%x\n", pts); + else + return sprintf(buf, "%s\n", na_string); +} + +static ssize_t addr_offset_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", astream_dev->offset); +} + +static struct class_attribute astream_class_attrs[] = { + __ATTR_RO(format), + __ATTR_RO(samplerate), + __ATTR_RO(channum), + __ATTR_RO(datawidth), + __ATTR_RO(pts), + __ATTR_RO(addr_offset), + __ATTR_NULL +}; + +static struct class astream_class = { + .name = "astream", + .class_attrs = astream_class_attrs, + }; + +#if 1 +#define IO_CBUS_PHY_BASE 0xc1100000 +#define CBUS_REG_OFFSET(reg) ((reg) << 2) +#define IO_SECBUS_PHY_BASE 0xda000000 + +static struct uio_info astream_uio_info = { + .name = "astream_uio", + .version = "0.1", + .irq = UIO_IRQ_NONE, + + .mem = { + [0] = { + .name = "AIFIFO", + .memtype = UIO_MEM_PHYS, + .addr = + (IO_CBUS_PHY_BASE + CBUS_REG_OFFSET(AIU_AIFIFO_CTRL)) + &(PAGE_MASK), + .size = PAGE_SIZE, + }, + [1] = { + .memtype = UIO_MEM_PHYS, + .addr = + (IO_CBUS_PHY_BASE + CBUS_REG_OFFSET(VCOP_CTRL_REG)), + .size = PAGE_SIZE, + }, + [2] = { + .name = "SECBUS", + .memtype = UIO_MEM_PHYS, + .addr = (IO_SECBUS_PHY_BASE), + .size = PAGE_SIZE, + }, + [3] = { + .name = "CBUS", + .memtype = UIO_MEM_PHYS, + .addr = + (IO_CBUS_PHY_BASE + CBUS_REG_OFFSET(ASSIST_HW_REV)) + &(PAGE_MASK), + .size = PAGE_SIZE, + }, + [4] = { + .name = "CBUS-START", + .memtype = UIO_MEM_PHYS, + .addr = (IO_CBUS_PHY_BASE + CBUS_REG_OFFSET(0x1000)), + .size = PAGE_SIZE * 4, + }, + }, +}; +#endif + +static void astream_release(struct device *dev) +{ + kfree(astream_dev); + + astream_dev = NULL; +} + +s32 adec_init(struct stream_port_s *port) +{ + enum aformat_e af; + + if (!astream_dev) + return -ENODEV; + + af = port->aformat; + + astream_dev->channum = port->achanl; + astream_dev->samplerate = port->asamprate; + astream_dev->datawidth = port->adatawidth; + + /*wmb();don't need it...*/ + if (af <= ARRAY_SIZE(astream_format)) + astream_dev->format = astream_format[af]; + else + astream_dev->format = NULL; + return 0; +} + +s32 adec_release(enum aformat_e vf) +{ + pr_info("adec_release\n"); + + if (!astream_dev) + return -ENODEV; + + astream_dev->format = NULL; + + return 0; +} + +int amstream_adec_show_fun(const char *trigger, int id, char *sbuf, int size) +{ + int ret = -1; + void *buf, *getbuf = NULL; + if (size < PAGE_SIZE) { + void *getbuf = (void *)__get_free_page(GFP_KERNEL); + if (!getbuf) + return -ENOMEM; + buf = getbuf; + } else { + buf = sbuf; + } + switch (trigger[0]) { + case 'f': + ret = format_show(NULL, NULL, buf); + break; + case 's': + ret = samplerate_show(NULL, NULL, buf); + break; + case 'c': + ret = channum_show(NULL, NULL, buf); + break; + case 'd': + ret = datawidth_show(NULL, NULL, buf); + break; + case 'p': + ret = pts_show(NULL, NULL, buf); + break; + default: + ret = -1; + } + if (ret > 0 && getbuf != NULL) { + int ret = min_t(int, ret, size); + strncpy(sbuf, buf, ret); + } + if (getbuf != NULL) + free_page((unsigned long)getbuf); + return ret; +} + +static struct mconfig adec_configs[] = { + MC_FUN("format", &amstream_adec_show_fun, NULL), + MC_FUN("samplerate", &amstream_adec_show_fun, NULL), + MC_FUN("channum", &amstream_adec_show_fun, NULL), + MC_FUN("datawidth", &amstream_adec_show_fun, NULL), + MC_FUN("pts", &amstream_adec_show_fun, NULL), +}; +static struct mconfig_node adec_node; + + +s32 astream_dev_register(void) +{ + s32 r; + struct device_node *node; + unsigned int cbus_base = 0xffd00000; + + r = class_register(&astream_class); + if (r) { + pr_info("astream class create fail.\n"); + return r; + } + + astream_dev = kzalloc(sizeof(struct astream_device_s), GFP_KERNEL); + + if (!astream_dev) { + pr_info("astream device create fail.\n"); + r = -ENOMEM; + goto err_3; + } + + astream_dev->dev.class = &astream_class; + astream_dev->dev.release = astream_release; + astream_dev->offset = 0; + dev_set_name(&astream_dev->dev, "astream-dev"); + + dev_set_drvdata(&astream_dev->dev, astream_dev); + + r = device_register(&astream_dev->dev); + if (r) { + pr_info("astream device register fail.\n"); + goto err_2; + } + + if (MESON_CPU_MAJOR_ID_TXL < get_cpu_type()) { + node = of_find_node_by_path("/codec_io/io_cbus_base"); + if (!node) { + pr_info("No io_cbus_base node found."); + goto err_1; + } + + r = of_property_read_u32_index(node, "reg", 1, &cbus_base); + if (r) { + pr_info("No find node.\n"); + goto err_1; + } + + /*need to offset -0x100 in txlx.*/ + astream_dev->offset = -0x100; + + /*need to offset -0x180 in g12a.*/ + if (MESON_CPU_MAJOR_ID_G12A <= get_cpu_type()) + astream_dev->offset = -0x180; + + astream_uio_info.mem[0].addr = + (cbus_base + CBUS_REG_OFFSET(AIU_AIFIFO_CTRL + + astream_dev->offset)) & (PAGE_MASK); + + astream_uio_info.mem[3].addr = + (cbus_base + CBUS_REG_OFFSET(ASSIST_HW_REV + + 0x100)) & (PAGE_MASK); + } + +#if 1 + if (uio_register_device(&astream_dev->dev, &astream_uio_info)) { + pr_info("astream UIO device register fail.\n"); + r = -ENODEV; + goto err_1; + } +#endif + INIT_REG_NODE_CONFIGS("media", &adec_node, + "adec", adec_configs, CONFIG_FOR_R); + return 0; + +err_1: + device_unregister(&astream_dev->dev); + +err_2: + kfree(astream_dev); + astream_dev = NULL; + +err_3: + class_unregister(&astream_class); + + return r; +} + +void astream_dev_unregister(void) +{ + if (astream_dev) { +#if 1 + uio_unregister_device(&astream_uio_info); +#endif + + device_unregister(&astream_dev->dev); + + class_unregister(&astream_class); + } +} diff --git a/drivers/amlogic/media_modules/stream_input/amports/adec.h b/drivers/amlogic/media_modules/stream_input/amports/adec.h new file mode 100644 index 000000000000..f06f73ad39b0 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/amports/adec.h @@ -0,0 +1,32 @@ +/* + * drivers/amlogic/media/stream_input/amports/adec.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef ADEC_H +#define ADEC_H + +#include "../parser/streambuf.h" +#include + +extern s32 adec_init(struct stream_port_s *port); + +extern s32 adec_release(enum aformat_e af); + +extern s32 astream_dev_register(void); + +extern s32 astream_dev_unregister(void); + +#endif /* ADEC_H */ diff --git a/drivers/amlogic/media_modules/stream_input/amports/amports_priv.h b/drivers/amlogic/media_modules/stream_input/amports/amports_priv.h new file mode 100644 index 000000000000..53669a5951a9 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/amports/amports_priv.h @@ -0,0 +1,52 @@ +/* + * drivers/amlogic/media/stream_input/amports/amports_priv.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef AMPORTS_PRIV_HEAD_HH +#define AMPORTS_PRIV_HEAD_HH +#include "../parser/streambuf.h" +#include "../../common/media_clock/switch/amports_gate.h" +#include +#include +#include + +struct port_priv_s { + struct vdec_s *vdec; + struct stream_port_s *port; +}; + +struct stream_buf_s *get_buf_by_type(u32 type); + +/*video.c provide*/ +extern u32 trickmode_i; +struct amvideocap_req; +extern u32 set_blackout_policy(int policy); +extern u32 get_blackout_policy(void); +int calculation_stream_ext_delayed_ms(u8 type); +int ext_get_cur_video_frame(struct vframe_s **vf, int *canvas_index); +int ext_put_video_frame(struct vframe_s *vf); +int ext_register_end_frame_callback(struct amvideocap_req *req); +int amstream_request_firmware_from_sys(const char *file_name, + char *buf, int size); +void set_vsync_pts_inc_mode(int inc); + +void set_real_audio_info(void *arg); +#define dbg() pr_info("on %s,line %d\n", __func__, __LINE__); + +struct device *amports_get_dma_device(void); +struct device *get_codec_cma_device(void); + +#endif diff --git a/drivers/amlogic/media_modules/stream_input/amports/amstream.c b/drivers/amlogic/media_modules/stream_input/amports/amstream.c new file mode 100644 index 000000000000..6546633df359 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/amports/amstream.c @@ -0,0 +1,3927 @@ +/* + * drivers/amlogic/media/stream_input/amports/amstream.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#define DEBUG +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +/* #include */ + +#include +#include +#include +#include +#include +#include +#include +#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ +/* #include */ +/* #include */ +#endif +#include "../parser/streambuf.h" +#include "../parser/streambuf_reg.h" +#include "../parser/tsdemux.h" +#include "../parser/psparser.h" +#include "../parser/esparser.h" +#include "../../frame_provider/decoder/utils/vdec.h" +#include "adec.h" +#include "../parser/rmparser.h" +#include "amports_priv.h" +#include +#include +#include "../parser/thread_rw.h" +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_COMPAT +#include +#endif +#include +#include +#include "../../frame_provider/decoder/utils/firmware.h" +#include "../../common/chips/chips.h" + +//#define G12A_BRINGUP_DEBUG + +#define CONFIG_AM_VDEC_REAL //DEBUG_TMP + +#define DEVICE_NAME "amstream-dev" +#define DRIVER_NAME "amstream" +#define MODULE_NAME "amstream" + +#define MAX_AMSTREAM_PORT_NUM ARRAY_SIZE(ports) +u32 amstream_port_num; +u32 amstream_buf_num; + +u32 amstream_audio_reset = 0; + +#if 0 +#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESONG9TV +#define NO_VDEC2_INIT 1 +#elif MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6TVD +#define NO_VDEC2_INIT IS_MESON_M8M2_CPU +#endif +#endif +#define NO_VDEC2_INIT 1 + +#define DEFAULT_VIDEO_BUFFER_SIZE (1024 * 1024 * 3) +#define DEFAULT_VIDEO_BUFFER_SIZE_4K (1024 * 1024 * 6) +#define DEFAULT_VIDEO_BUFFER_SIZE_TVP (1024 * 1024 * 10) +#define DEFAULT_VIDEO_BUFFER_SIZE_4K_TVP (1024 * 1024 * 15) + + +#define DEFAULT_AUDIO_BUFFER_SIZE (1024*768*2) +#define DEFAULT_SUBTITLE_BUFFER_SIZE (1024*256) + +static int def_4k_vstreambuf_sizeM = + (DEFAULT_VIDEO_BUFFER_SIZE_4K >> 20); +static int def_vstreambuf_sizeM = + (DEFAULT_VIDEO_BUFFER_SIZE >> 20); +static int slow_input; + + + + +/* #define DATA_DEBUG */ +static int use_bufferlevelx10000 = 10000; +static int reset_canuse_buferlevel(int level); +static struct platform_device *amstream_pdev; +struct device *amports_get_dma_device(void) +{ + return &amstream_pdev->dev; +} +EXPORT_SYMBOL(amports_get_dma_device); + +#ifdef DATA_DEBUG +#include + +#define DEBUG_FILE_NAME "/sdcard/debug.tmp" +static struct file *debug_filp; +static loff_t debug_file_pos; + +void debug_file_write(const char __user *buf, size_t count) +{ + mm_segment_t old_fs; + + if (!debug_filp) + return; + + old_fs = get_fs(); + set_fs(KERNEL_DS); + + if (count != vfs_write(debug_filp, buf, count, &debug_file_pos)) + pr_err("Failed to write debug file\n"); + + set_fs(old_fs); +} +#endif + + + +static int amstream_open(struct inode *inode, struct file *file); +static int amstream_release(struct inode *inode, struct file *file); +static long amstream_ioctl(struct file *file, unsigned int cmd, ulong arg); +#ifdef CONFIG_COMPAT +static long amstream_compat_ioctl + (struct file *file, unsigned int cmd, ulong arg); +#endif +static ssize_t amstream_vbuf_write +(struct file *file, const char *buf, size_t count, loff_t *ppos); +static ssize_t amstream_vframe_write +(struct file *file, const char *buf, size_t count, loff_t *ppos); +static ssize_t amstream_abuf_write +(struct file *file, const char *buf, size_t count, loff_t *ppos); +static ssize_t amstream_mpts_write +(struct file *file, const char *buf, size_t count, loff_t *ppos); +static ssize_t amstream_mpps_write +(struct file *file, const char *buf, size_t count, loff_t *ppos); +static ssize_t amstream_sub_read +(struct file *file, char *buf, size_t count, loff_t *ppos); +static ssize_t amstream_sub_write +(struct file *file, const char *buf, size_t count, loff_t *ppos); +static unsigned int amstream_sub_poll +(struct file *file, poll_table *wait_table); +static unsigned int amstream_userdata_poll +(struct file *file, poll_table *wait_table); +static ssize_t amstream_userdata_read +(struct file *file, char *buf, size_t count, loff_t *ppos); +static int (*amstream_adec_status) +(struct adec_status *astatus); +#ifdef CONFIG_AM_VDEC_REAL +static ssize_t amstream_mprm_write +(struct file *file, const char *buf, size_t count, loff_t *ppos); +#endif + +static const struct file_operations vbuf_fops = { + .owner = THIS_MODULE, + .open = amstream_open, + .release = amstream_release, + .write = amstream_vbuf_write, + .unlocked_ioctl = amstream_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = amstream_compat_ioctl, +#endif +}; + +static const struct file_operations vframe_fops = { + .owner = THIS_MODULE, + .open = amstream_open, + .release = amstream_release, + .write = amstream_vframe_write, + .unlocked_ioctl = amstream_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = amstream_compat_ioctl, +#endif +}; + +static const struct file_operations abuf_fops = { + .owner = THIS_MODULE, + .open = amstream_open, + .release = amstream_release, + .write = amstream_abuf_write, + .unlocked_ioctl = amstream_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = amstream_compat_ioctl, +#endif +}; + +static const struct file_operations mpts_fops = { + .owner = THIS_MODULE, + .open = amstream_open, + .release = amstream_release, + .write = amstream_mpts_write, + .unlocked_ioctl = amstream_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = amstream_compat_ioctl, +#endif +}; + +static const struct file_operations mpps_fops = { + .owner = THIS_MODULE, + .open = amstream_open, + .release = amstream_release, + .write = amstream_mpps_write, + .unlocked_ioctl = amstream_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = amstream_compat_ioctl, +#endif +}; + +static const struct file_operations mprm_fops = { + .owner = THIS_MODULE, + .open = amstream_open, + .release = amstream_release, +#ifdef CONFIG_AM_VDEC_REAL + .write = amstream_mprm_write, +#endif + .unlocked_ioctl = amstream_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = amstream_compat_ioctl, +#endif +}; + +static const struct file_operations sub_fops = { + .owner = THIS_MODULE, + .open = amstream_open, + .release = amstream_release, + .write = amstream_sub_write, + .unlocked_ioctl = amstream_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = amstream_compat_ioctl, +#endif +}; + +static const struct file_operations sub_read_fops = { + .owner = THIS_MODULE, + .open = amstream_open, + .release = amstream_release, + .read = amstream_sub_read, + .poll = amstream_sub_poll, + .unlocked_ioctl = amstream_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = amstream_compat_ioctl, +#endif +}; + +static const struct file_operations userdata_fops = { + .owner = THIS_MODULE, + .open = amstream_open, + .release = amstream_release, + .read = amstream_userdata_read, + .poll = amstream_userdata_poll, + .unlocked_ioctl = amstream_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = amstream_compat_ioctl, +#endif +}; + +static const struct file_operations amstream_fops = { + .owner = THIS_MODULE, + .open = amstream_open, + .release = amstream_release, + .unlocked_ioctl = amstream_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = amstream_compat_ioctl, +#endif +}; + +/**************************************************/ +static struct audio_info audio_dec_info; +static struct class *amstream_dev_class; +static DEFINE_MUTEX(amstream_mutex); + +atomic_t subdata_ready = ATOMIC_INIT(0); +static int sub_type; +static int sub_port_inited; +/* wait queue for poll */ +static wait_queue_head_t amstream_sub_wait; +atomic_t userdata_ready = ATOMIC_INIT(0); +static int userdata_length; +static wait_queue_head_t amstream_userdata_wait; +#define USERDATA_FIFO_NUM 1024 +static struct userdata_poc_info_t userdata_poc_info[USERDATA_FIFO_NUM]; +static int userdata_poc_ri, userdata_poc_wi; +static int last_read_wi; + + +static DEFINE_MUTEX(userdata_mutex); + +static struct stream_port_s ports[] = { + { + .name = "amstream_vbuf", + .type = PORT_TYPE_ES | PORT_TYPE_VIDEO, + .fops = &vbuf_fops, + }, +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + { + .name = "amstream_vbuf_sched", + .type = PORT_TYPE_ES | PORT_TYPE_VIDEO | + PORT_TYPE_DECODER_SCHED, + .fops = &vbuf_fops, + }, + { + .name = "amstream_vframe", + .type = PORT_TYPE_ES | PORT_TYPE_VIDEO | + PORT_TYPE_FRAME | PORT_TYPE_DECODER_SCHED, + .fops = &vframe_fops, + }, +#endif + { + .name = "amstream_abuf", + .type = PORT_TYPE_ES | PORT_TYPE_AUDIO, + .fops = &abuf_fops, + }, + { + .name = "amstream_mpts", + .type = PORT_TYPE_MPTS | PORT_TYPE_VIDEO | + PORT_TYPE_AUDIO | PORT_TYPE_SUB, + .fops = &mpts_fops, + }, +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + { + .name = "amstream_mpts_sched", + .type = PORT_TYPE_MPTS | PORT_TYPE_VIDEO | + PORT_TYPE_AUDIO | PORT_TYPE_SUB | + PORT_TYPE_DECODER_SCHED, + .fops = &mpts_fops, + }, +#endif + { + .name = "amstream_mpps", + .type = PORT_TYPE_MPPS | PORT_TYPE_VIDEO | + PORT_TYPE_AUDIO | PORT_TYPE_SUB, + .fops = &mpps_fops, + }, + { + .name = "amstream_rm", + .type = PORT_TYPE_RM | PORT_TYPE_VIDEO | PORT_TYPE_AUDIO, + .fops = &mprm_fops, + }, + { + .name = "amstream_sub", + .type = PORT_TYPE_SUB, + .fops = &sub_fops, + }, + { + .name = "amstream_sub_read", + .type = PORT_TYPE_SUB_RD, + .fops = &sub_read_fops, + }, + { + .name = "amstream_userdata", + .type = PORT_TYPE_USERDATA, + .fops = &userdata_fops, + }, + { + .name = "amstream_hevc", + .type = PORT_TYPE_ES | PORT_TYPE_VIDEO | PORT_TYPE_HEVC, + .fops = &vbuf_fops, + .vformat = VFORMAT_HEVC, + }, +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + { + .name = "amstream_hevc_frame", + .type = PORT_TYPE_ES | PORT_TYPE_VIDEO | PORT_TYPE_HEVC | + PORT_TYPE_FRAME | PORT_TYPE_DECODER_SCHED, + .fops = &vframe_fops, + .vformat = VFORMAT_HEVC, + }, + { + .name = "amstream_hevc_sched", + .type = PORT_TYPE_ES | PORT_TYPE_VIDEO | PORT_TYPE_HEVC | + PORT_TYPE_DECODER_SCHED, + .fops = &vbuf_fops, + .vformat = VFORMAT_HEVC, + }, +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + { + .name = "amstream_dves_avc", + .type = PORT_TYPE_ES | PORT_TYPE_VIDEO | + PORT_TYPE_DECODER_SCHED | PORT_TYPE_DUALDEC, + .fops = &vbuf_fops, + }, + { + .name = "amstream_dves_hevc", + .type = PORT_TYPE_ES | PORT_TYPE_VIDEO | PORT_TYPE_HEVC | + PORT_TYPE_DECODER_SCHED | PORT_TYPE_DUALDEC, + .fops = &vbuf_fops, + .vformat = VFORMAT_HEVC, + }, +#endif +#endif +}; + +static struct stream_buf_s bufs[BUF_MAX_NUM] = { + { + .reg_base = VLD_MEM_VIFIFO_REG_BASE, + .type = BUF_TYPE_VIDEO, + .buf_start = 0, + .buf_size = DEFAULT_VIDEO_BUFFER_SIZE, + .default_buf_size = DEFAULT_VIDEO_BUFFER_SIZE, + .first_tstamp = INVALID_PTS + }, + { + .reg_base = AIU_MEM_AIFIFO_REG_BASE, + .type = BUF_TYPE_AUDIO, + .buf_start = 0, + .buf_size = DEFAULT_AUDIO_BUFFER_SIZE, + .default_buf_size = DEFAULT_AUDIO_BUFFER_SIZE, + .first_tstamp = INVALID_PTS + }, + { + .reg_base = 0, + .type = BUF_TYPE_SUBTITLE, + .buf_start = 0, + .buf_size = DEFAULT_SUBTITLE_BUFFER_SIZE, + .default_buf_size = DEFAULT_SUBTITLE_BUFFER_SIZE, + .first_tstamp = INVALID_PTS + }, + { + .reg_base = 0, + .type = BUF_TYPE_USERDATA, + .buf_start = 0, + .buf_size = 0, + .first_tstamp = INVALID_PTS + }, + { + .reg_base = HEVC_STREAM_REG_BASE, + .type = BUF_TYPE_HEVC, + .buf_start = 0, + .buf_size = DEFAULT_VIDEO_BUFFER_SIZE_4K, + .default_buf_size = DEFAULT_VIDEO_BUFFER_SIZE_4K, + .first_tstamp = INVALID_PTS + }, +}; + +struct stream_buf_s *get_buf_by_type(u32 type) +{ + if (PTS_TYPE_VIDEO == type) + return &bufs[BUF_TYPE_VIDEO]; + if (PTS_TYPE_AUDIO == type) + return &bufs[BUF_TYPE_AUDIO]; + if (has_hevc_vdec()) { + if (PTS_TYPE_HEVC == type) + return &bufs[BUF_TYPE_HEVC]; + } + + return NULL; +} + +void set_sample_rate_info(int arg) +{ + audio_dec_info.sample_rate = arg; + audio_dec_info.valid = 1; +} + +void set_ch_num_info(int arg) +{ + audio_dec_info.channels = arg; +} + +struct audio_info *get_audio_info(void) +{ + return &audio_dec_info; +} +EXPORT_SYMBOL(get_audio_info); + +static void amstream_change_vbufsize(struct port_priv_s *priv, + struct stream_buf_s *pvbuf) +{ + if (pvbuf->buf_start != 0) { + pr_info("streambuf is alloced before\n"); + return; + } + if (pvbuf->for_4k) { + pvbuf->buf_size = def_4k_vstreambuf_sizeM * SZ_1M; + if (priv->vdec->port_flag & PORT_FLAG_DRM) + pvbuf->buf_size = DEFAULT_VIDEO_BUFFER_SIZE_4K_TVP; + if ((pvbuf->buf_size > 30 * SZ_1M) && + (codec_mm_get_total_size() < 220 * SZ_1M)) { + /*if less than 250M, used 20M for 4K & 265*/ + pvbuf->buf_size = pvbuf->buf_size >> 1; + } + } else if (pvbuf->buf_size > def_vstreambuf_sizeM * SZ_1M) { + if (priv->vdec->port_flag & PORT_FLAG_DRM) + pvbuf->buf_size = DEFAULT_VIDEO_BUFFER_SIZE_TVP; + } else { + pvbuf->buf_size = def_vstreambuf_sizeM * SZ_1M; + if (priv->vdec->port_flag & PORT_FLAG_DRM) + pvbuf->buf_size = DEFAULT_VIDEO_BUFFER_SIZE_TVP; + } + reset_canuse_buferlevel(10000); +} + +static bool port_get_inited(struct port_priv_s *priv) +{ + struct stream_port_s *port = priv->port; + + if (port->type & PORT_TYPE_VIDEO) { + struct vdec_s *vdec = priv->vdec; + + return vdec->port_flag & PORT_FLAG_INITED; + } + + return port->flag & PORT_FLAG_INITED; +} + +static void port_set_inited(struct port_priv_s *priv) +{ + struct stream_port_s *port = priv->port; + + if (port->type & PORT_TYPE_VIDEO) { + struct vdec_s *vdec = priv->vdec; + + vdec->port_flag |= PORT_FLAG_INITED; + } else + port->flag |= PORT_FLAG_INITED; +} + +static void video_port_release(struct port_priv_s *priv, + struct stream_buf_s *pbuf, int release_num) +{ + struct stream_port_s *port = priv->port; + struct vdec_s *vdec = priv->vdec; + struct vdec_s *slave = NULL; + bool is_multidec = !vdec_single(vdec); + + switch (release_num) { + default: + /*fallthrough*/ + case 0: /*release all */ + /*fallthrough*/ + case 4: + if ((port->type & PORT_TYPE_FRAME) == 0) + esparser_release(pbuf); + /*fallthrough*/ + case 3: + if (vdec->slave) + slave = vdec->slave; + vdec_release(vdec); + if (slave) + vdec_release(slave); + priv->vdec = NULL; + /*fallthrough*/ + case 2: + if ((port->type & PORT_TYPE_FRAME) == 0) + stbuf_release(pbuf, is_multidec); + /*fallthrough*/ + case 1: + ; + } +} + +static int video_port_init(struct port_priv_s *priv, + struct stream_buf_s *pbuf) +{ + int r; + struct stream_port_s *port = priv->port; + struct vdec_s *vdec = priv->vdec; + + if ((vdec->port_flag & PORT_FLAG_VFORMAT) == 0) { + pr_err("vformat not set\n"); + return -EPERM; + } + + if (port->vformat == VFORMAT_H264_4K2K || + (priv->vdec->sys_info->height * + priv->vdec->sys_info->width) > 1920*1088) { + pbuf->for_4k = 1; + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXLX + && port->vformat == VFORMAT_H264) { + amports_switch_gate("clk_hevc_mux", 1); + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) + amports_switch_gate("clk_hevcb_mux", 1); + + vdec_poweron(VDEC_HEVC); + } + } else { + pbuf->for_4k = 0; + } + + if (port->type & PORT_TYPE_FRAME) { + r = vdec_init(vdec, + (priv->vdec->sys_info->height * + priv->vdec->sys_info->width) > 1920*1088); + if (r < 0) { + pr_err("video_port_init %d, vdec_init failed\n", + __LINE__); + video_port_release(priv, pbuf, 2); + return r; + } + + return 0; + } + + amstream_change_vbufsize(priv, pbuf); + + if (has_hevc_vdec()) { + if (port->type & PORT_TYPE_MPTS) { + if (pbuf->type == BUF_TYPE_HEVC) + vdec_poweroff(VDEC_1); + else + vdec_poweroff(VDEC_HEVC); + } + } + + r = stbuf_init(pbuf, vdec, false); + if (r < 0) { + pr_err("video_port_init %d, stbuf_init failed\n", __LINE__); + return r; + } + + /* todo: set path based on port flag */ + r = vdec_init(vdec, + (priv->vdec->sys_info->height * + priv->vdec->sys_info->width) > 1920*1088); + + if (r < 0) { + pr_err("video_port_init %d, vdec_init failed\n", __LINE__); + video_port_release(priv, pbuf, 2); + return r; + } + + if (vdec_dual(vdec)) { + r = vdec_init(vdec->slave, + (priv->vdec->sys_info->height * + priv->vdec->sys_info->width) > 1920*1088); + if (r < 0) { + pr_err("video_port_init %d, vdec_init failed\n", + __LINE__); + video_port_release(priv, pbuf, 2); + return r; + } + } + + if (port->type & PORT_TYPE_ES) { + r = esparser_init(pbuf, vdec); + if (r < 0) { + video_port_release(priv, pbuf, 3); + pr_err("esparser_init() failed\n"); + return r; + } + } + + pbuf->flag |= BUF_FLAG_IN_USE; + + vdec_connect(priv->vdec); + + return 0; +} + +static void audio_port_release(struct stream_port_s *port, + struct stream_buf_s *pbuf, int release_num) +{ + switch (release_num) { + default: + /*fallthrough*/ + case 0: /*release all */ + /*fallthrough*/ + case 4: + esparser_release(pbuf); + /*fallthrough*/ + case 3: + adec_release(port->vformat); + /*fallthrough*/ + case 2: + stbuf_release(pbuf, false); + /*fallthrough*/ + case 1: + ; + } + amstream_audio_reset = 0; + return; +} + +static int audio_port_reset(struct stream_port_s *port, + struct stream_buf_s *pbuf) +{ + int r; + + if ((port->flag & PORT_FLAG_AFORMAT) == 0) { + pr_err("aformat not set\n"); + return 0; + } + + pts_stop(PTS_TYPE_AUDIO); + + stbuf_release(pbuf, false); + + r = stbuf_init(pbuf, NULL, false); + if (r < 0) + return r; + + r = adec_init(port); + if (r < 0) { + audio_port_release(port, pbuf, 2); + return r; + } + + if (port->type & PORT_TYPE_ES) + esparser_audio_reset_s(pbuf); + + if (port->type & PORT_TYPE_MPTS) + tsdemux_audio_reset(); + + if (port->type & PORT_TYPE_MPPS) + psparser_audio_reset(); + +#ifdef CONFIG_AM_VDEC_REAL + if (port->type & PORT_TYPE_RM) + rm_audio_reset(); +#endif + + pbuf->flag |= BUF_FLAG_IN_USE; + amstream_audio_reset = 1; + + r = pts_start(PTS_TYPE_AUDIO); + + return r; +} + +static int sub_port_reset(struct stream_port_s *port, + struct stream_buf_s *pbuf) +{ + int r; + + port->flag &= (~PORT_FLAG_INITED); + + stbuf_release(pbuf, false); + + r = stbuf_init(pbuf, NULL, false); + if (r < 0) + return r; + + if (port->type & PORT_TYPE_MPTS) + tsdemux_sub_reset(); + + if (port->type & PORT_TYPE_MPPS) + psparser_sub_reset(); + + if (port->sid == 0xffff) { /* es sub */ + esparser_sub_reset(); + pbuf->flag |= BUF_FLAG_PARSER; + } + + pbuf->flag |= BUF_FLAG_IN_USE; + + port->flag |= PORT_FLAG_INITED; + + return 0; +} + +static int audio_port_init(struct stream_port_s *port, + struct stream_buf_s *pbuf) +{ + int r; + + if ((port->flag & PORT_FLAG_AFORMAT) == 0) { + pr_err("aformat not set\n"); + return 0; + } + + r = stbuf_init(pbuf, NULL, false); + if (r < 0) + return r; + r = adec_init(port); + if (r < 0) { + audio_port_release(port, pbuf, 2); + return r; + } + if (port->type & PORT_TYPE_ES) { + r = esparser_init(pbuf, NULL); + if (r < 0) { + audio_port_release(port, pbuf, 3); + return r; + } + } + pbuf->flag |= BUF_FLAG_IN_USE; + return 0; +} + +static void sub_port_release(struct stream_port_s *port, + struct stream_buf_s *pbuf) +{ + if ((port->sid == 0xffff) && + ((port->type & (PORT_TYPE_MPPS | PORT_TYPE_MPTS)) == 0)) { + /* this is es sub */ + esparser_release(pbuf); + } + stbuf_release(pbuf, false); + sub_port_inited = 0; +} + +static int sub_port_init(struct stream_port_s *port, struct stream_buf_s *pbuf) +{ + int r; + r = stbuf_init(pbuf, NULL, false); + if (r < 0) + return r; + if ((port->flag & PORT_FLAG_SID) == 0) { + pr_err("subtitle id not set\n"); + return 0; + } + + if ((port->sid == 0xffff) && + ((port->type & (PORT_TYPE_MPPS | PORT_TYPE_MPTS)) == 0)) { + /* es sub */ + r = esparser_init(pbuf, NULL); + if (r < 0) { + sub_port_release(port, pbuf); + return r; + } + } + + sub_port_inited = 1; + return 0; +} + +static void amstream_user_buffer_init(void) +{ + struct stream_buf_s *pubuf = &bufs[BUF_TYPE_USERDATA]; + + pubuf->buf_size = 0; + pubuf->buf_start = 0; + pubuf->buf_wp = 0; + pubuf->buf_rp = 0; +} + +static int amstream_port_init(struct port_priv_s *priv) +{ + int r = 0; + struct stream_buf_s *pvbuf = &bufs[BUF_TYPE_VIDEO]; + struct stream_buf_s *pabuf = &bufs[BUF_TYPE_AUDIO]; + struct stream_buf_s *psbuf = &bufs[BUF_TYPE_SUBTITLE]; + struct stream_port_s *port = priv->port; + struct vdec_s *vdec = priv->vdec; + + mutex_lock(&amstream_mutex); + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) { + r = check_efuse_chip(port->vformat); + if (r) { + pr_info("No support video format %d.\n", port->vformat); + mutex_unlock(&amstream_mutex); + return 0; + } + } + + /* try to reload the fw.*/ + r = video_fw_reload(FW_LOAD_TRY); + if (r) + pr_err("the firmware reload fail.\n"); + + stbuf_fetch_init(); + + amstream_user_buffer_init(); + + if (port_get_inited(priv)) { + mutex_unlock(&amstream_mutex); + return 0; + } + + if ((port->type & PORT_TYPE_AUDIO) && + (port->flag & PORT_FLAG_AFORMAT)) { + r = audio_port_init(port, pabuf); + if (r < 0) { + pr_err("audio_port_init failed\n"); + goto error1; + } + } + + if ((port->type & PORT_TYPE_VIDEO) && + (vdec->port_flag & PORT_FLAG_VFORMAT)) { + pvbuf->for_4k = 0; + if (has_hevc_vdec()) { + if (port->vformat == VFORMAT_HEVC || + port->vformat == VFORMAT_AVS2 || + port->vformat == VFORMAT_VP9) + pvbuf = &bufs[BUF_TYPE_HEVC]; + } + r = video_port_init(priv, pvbuf); + if (r < 0) { + pr_err("video_port_init failed\n"); + goto error2; + } + } + + if ((port->type & PORT_TYPE_SUB) && (port->flag & PORT_FLAG_SID)) { + r = sub_port_init(port, psbuf); + if (r < 0) { + pr_err("sub_port_init failed\n"); + goto error3; + } + } + + if (port->type & PORT_TYPE_MPTS) { + if (has_hevc_vdec()) { + r = tsdemux_init( + (port->flag & PORT_FLAG_VID) ? port->vid : 0xffff, + (port->flag & PORT_FLAG_AID) ? port->aid : 0xffff, + (port->flag & PORT_FLAG_SID) ? port->sid : 0xffff, + (port->pcr_inited == 1) ? port->pcrid : 0xffff, + (port->vformat == VFORMAT_HEVC) || + (port->vformat == VFORMAT_AVS2) || + (port->vformat == VFORMAT_VP9), + vdec); + } else { + r = tsdemux_init( + (port->flag & PORT_FLAG_VID) ? port->vid : 0xffff, + (port->flag & PORT_FLAG_AID) ? port->aid : 0xffff, + (port->flag & PORT_FLAG_SID) ? port->sid : 0xffff, + (port->pcr_inited == 1) ? port->pcrid : 0xffff, + 0, + vdec); + } + + if (r < 0) { + pr_err("tsdemux_init failed\n"); + goto error4; + } + tsync_pcr_start(); + } + if (port->type & PORT_TYPE_MPPS) { + r = psparser_init( + (port->flag & PORT_FLAG_VID) ? port->vid : 0xffff, + (port->flag & PORT_FLAG_AID) ? port->aid : 0xffff, + (port->flag & PORT_FLAG_SID) ? port->sid : 0xffff, + priv->vdec); + if (r < 0) { + pr_err("psparser_init failed\n"); + goto error5; + } + } +#ifdef CONFIG_AM_VDEC_REAL + if (port->type & PORT_TYPE_RM) { + rm_set_vasid( + (port->flag & PORT_FLAG_VID) ? port->vid : 0xffff, + (port->flag & PORT_FLAG_AID) ? port->aid : 0xffff); + } +#endif +#if 1 /* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6TVD */ + if (!NO_VDEC2_INIT) { + if ((port->type & PORT_TYPE_VIDEO) + && (port->vformat == VFORMAT_H264_4K2K)) + stbuf_vdec2_init(pvbuf); + } +#endif + + if ((port->type & PORT_TYPE_VIDEO) && + (vdec->port_flag & PORT_FLAG_VFORMAT)) + /* connect vdec at the end after all HW initialization */ + vdec_connect(vdec); + + tsync_audio_break(0); /* clear audio break */ + set_vsync_pts_inc_mode(0); /* clear video inc */ + + port_set_inited(priv); + + mutex_unlock(&amstream_mutex); + return 0; + /*errors follow here */ +error5: + tsdemux_release(); +error4: + sub_port_release(port, psbuf); +error3: + video_port_release(priv, pvbuf, 0); +error2: + audio_port_release(port, pabuf, 0); +error1: + mutex_unlock(&amstream_mutex); + return r; +} + +static int amstream_port_release(struct port_priv_s *priv) +{ + struct stream_port_s *port = priv->port; + struct stream_buf_s *pvbuf = &bufs[BUF_TYPE_VIDEO]; + struct stream_buf_s *pabuf = &bufs[BUF_TYPE_AUDIO]; + struct stream_buf_s *psbuf = &bufs[BUF_TYPE_SUBTITLE]; + + if (has_hevc_vdec()) { + if (port->vformat == VFORMAT_HEVC + || port->vformat == VFORMAT_AVS2 + || port->vformat == VFORMAT_VP9) + pvbuf = &bufs[BUF_TYPE_HEVC]; + } + + if (port->type & PORT_TYPE_MPTS) { + tsync_pcr_stop(); + tsdemux_release(); + } + + if (port->type & PORT_TYPE_MPPS) + psparser_release(); + + if (port->type & PORT_TYPE_VIDEO) + video_port_release(priv, pvbuf, 0); + + if (port->type & PORT_TYPE_AUDIO) + audio_port_release(port, pabuf, 0); + + if (port->type & PORT_TYPE_SUB) + sub_port_release(port, psbuf); + + port->pcr_inited = 0; + port->flag = 0; + return 0; +} + +static void amstream_change_avid(struct stream_port_s *port) +{ + if (port->type & PORT_TYPE_MPTS) { + tsdemux_change_avid( + (port->flag & PORT_FLAG_VID) ? port->vid : 0xffff, + (port->flag & PORT_FLAG_AID) ? port->aid : 0xffff); + } + + if (port->type & PORT_TYPE_MPPS) { + psparser_change_avid( + (port->flag & PORT_FLAG_VID) ? port->vid : 0xffff, + (port->flag & PORT_FLAG_AID) ? port->aid : 0xffff); + } + +#ifdef CONFIG_AM_VDEC_REAL + if (port->type & PORT_TYPE_RM) { + rm_set_vasid( + (port->flag & PORT_FLAG_VID) ? port->vid : 0xffff, + (port->flag & PORT_FLAG_AID) ? port->aid : 0xffff); + } +#endif +} + +static void amstream_change_sid(struct stream_port_s *port) +{ + if (port->type & PORT_TYPE_MPTS) { + tsdemux_change_sid( + (port->flag & PORT_FLAG_SID) ? port->sid : 0xffff); + } + + if (port->type & PORT_TYPE_MPPS) { + psparser_change_sid( + (port->flag & PORT_FLAG_SID) ? port->sid : 0xffff); + } +} + +/**************************************************/ +static ssize_t amstream_vbuf_write(struct file *file, const char *buf, + size_t count, loff_t *ppos) +{ + struct port_priv_s *priv = (struct port_priv_s *)file->private_data; + struct stream_port_s *port = priv->port; + struct stream_buf_s *pbuf = NULL; + int r; + if (has_hevc_vdec()) { + pbuf = (port->type & PORT_TYPE_HEVC) ? &bufs[BUF_TYPE_HEVC] : + &bufs[BUF_TYPE_VIDEO]; + } else + pbuf = &bufs[BUF_TYPE_VIDEO]; + + if (!(port_get_inited(priv))) { + r = amstream_port_init(priv); + if (r < 0) + return r; + } + + if (priv->vdec->port_flag & PORT_FLAG_DRM) + r = drm_write(file, pbuf, buf, count); + else + r = esparser_write(file, pbuf, buf, count); + if (slow_input) { + pr_info("slow_input: es codec write size %x\n", r); + msleep(3000); + } +#ifdef DATA_DEBUG + debug_file_write(buf, r); +#endif + + return r; +} + +static ssize_t amstream_vframe_write(struct file *file, const char *buf, + size_t count, loff_t *ppos) +{ + struct port_priv_s *priv = (struct port_priv_s *)file->private_data; + ssize_t ret; + int wait_max_cnt = 5; +#ifdef DATA_DEBUG + debug_file_write(buf, count); +#endif + do { + ret = vdec_write_vframe(priv->vdec, buf, count); + if (file->f_flags & O_NONBLOCK) { + break;/*alway return for no block mode.*/ + } else if (ret == -EAGAIN) { + int level; + level = vdec_input_level(&priv->vdec->input); + if (wait_max_cnt-- < 0) + break; + msleep(20); + } + } while (ret == -EAGAIN); + return ret; +} + +static ssize_t amstream_abuf_write(struct file *file, const char *buf, + size_t count, loff_t *ppos) +{ + struct port_priv_s *priv = (struct port_priv_s *)file->private_data; + struct stream_port_s *port = priv->port; + struct stream_buf_s *pbuf = &bufs[BUF_TYPE_AUDIO]; + int r; + + if (!(port_get_inited(priv))) { + r = amstream_port_init(priv); + if (r < 0) + return r; + } + + if (port->flag & PORT_FLAG_DRM) + r = drm_write(file, pbuf, buf, count); + else + r = esparser_write(file, pbuf, buf, count); + + return r; +} + +static ssize_t amstream_mpts_write(struct file *file, const char *buf, + size_t count, loff_t *ppos) +{ + struct port_priv_s *priv = (struct port_priv_s *)file->private_data; + struct stream_port_s *port = priv->port; + struct stream_buf_s *pabuf = &bufs[BUF_TYPE_AUDIO]; + struct stream_buf_s *pvbuf = NULL; + int r = 0; + + if (has_hevc_vdec()) { + pvbuf = (port->vformat == VFORMAT_HEVC || + port->vformat == VFORMAT_AVS2 || + port->vformat == VFORMAT_VP9) ? + &bufs[BUF_TYPE_HEVC] : &bufs[BUF_TYPE_VIDEO]; + } else + pvbuf = &bufs[BUF_TYPE_VIDEO]; + + if (!(port_get_inited(priv))) { + r = amstream_port_init(priv); + if (r < 0) + return r; + } +#ifdef DATA_DEBUG + debug_file_write(buf, count); +#endif + if (port->flag & PORT_FLAG_DRM) + r = drm_tswrite(file, pvbuf, pabuf, buf, count); + else + r = tsdemux_write(file, pvbuf, pabuf, buf, count); + if (slow_input) { + pr_info("slow_input: ts codec write size %x\n", r); + msleep(3000); + } + return r; +} + +static ssize_t amstream_mpps_write(struct file *file, const char *buf, + size_t count, loff_t *ppos) +{ + struct port_priv_s *priv = (struct port_priv_s *)file->private_data; + struct stream_buf_s *pvbuf = &bufs[BUF_TYPE_VIDEO]; + struct stream_buf_s *pabuf = &bufs[BUF_TYPE_AUDIO]; + int r; + + if (!(port_get_inited(priv))) { + r = amstream_port_init(priv); + if (r < 0) + return r; + } + return psparser_write(file, pvbuf, pabuf, buf, count); +} + +#ifdef CONFIG_AM_VDEC_REAL +static ssize_t amstream_mprm_write(struct file *file, const char *buf, + size_t count, loff_t *ppos) +{ + struct port_priv_s *priv = (struct port_priv_s *)file->private_data; + struct stream_buf_s *pvbuf = &bufs[BUF_TYPE_VIDEO]; + struct stream_buf_s *pabuf = &bufs[BUF_TYPE_AUDIO]; + int r; + + if (!(port_get_inited(priv))) { + r = amstream_port_init(priv); + if (r < 0) + return r; + } + return rmparser_write(file, pvbuf, pabuf, buf, count); +} +#endif + +static ssize_t amstream_sub_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + u32 sub_rp, sub_wp, sub_start, data_size, res; + struct stream_buf_s *s_buf = &bufs[BUF_TYPE_SUBTITLE]; + + if (sub_port_inited == 0) + return 0; + + sub_rp = stbuf_sub_rp_get(); + sub_wp = stbuf_sub_wp_get(); + sub_start = stbuf_sub_start_get(); + + if (sub_wp == sub_rp || sub_rp == 0) + return 0; + + if (sub_wp > sub_rp) + data_size = sub_wp - sub_rp; + else + data_size = s_buf->buf_size - sub_rp + sub_wp; + + if (data_size > count) + data_size = count; + + if (sub_wp < sub_rp) { + int first_num = s_buf->buf_size - (sub_rp - sub_start); + + if (data_size <= first_num) { + res = copy_to_user((void *)buf, + (void *)(codec_mm_phys_to_virt(sub_rp)), + data_size); + if (res >= 0) + stbuf_sub_rp_set(sub_rp + data_size - res); + + return data_size - res; + } else { + if (first_num > 0) { + res = copy_to_user((void *)buf, + (void *)(codec_mm_phys_to_virt(sub_rp)), + first_num); + if (res >= 0) { + stbuf_sub_rp_set(sub_rp + first_num - + res); + } + + return first_num - res; + } + + res = copy_to_user((void *)buf, + (void *)(codec_mm_phys_to_virt(sub_start)), + data_size - first_num); + + if (res >= 0) { + stbuf_sub_rp_set(sub_start + data_size - + first_num - res); + } + + return data_size - first_num - res; + } + } else { + res = + copy_to_user((void *)buf, + (void *)(codec_mm_phys_to_virt(sub_rp)), + data_size); + + if (res >= 0) + stbuf_sub_rp_set(sub_rp + data_size - res); + + return data_size - res; + } +} + +static ssize_t amstream_sub_write(struct file *file, const char *buf, + size_t count, loff_t *ppos) +{ + struct port_priv_s *priv = (struct port_priv_s *)file->private_data; + struct stream_buf_s *pbuf = &bufs[BUF_TYPE_SUBTITLE]; + int r; + + if (!(port_get_inited(priv))) { + r = amstream_port_init(priv); + if (r < 0) + return r; + } + r = esparser_write(file, pbuf, buf, count); + if (r < 0) + return r; + + wakeup_sub_poll(); + + return r; +} + +static unsigned int amstream_sub_poll(struct file *file, + poll_table *wait_table) +{ + poll_wait(file, &amstream_sub_wait, wait_table); + + if (atomic_read(&subdata_ready)) { + atomic_dec(&subdata_ready); + return POLLOUT | POLLWRNORM; + } + + return 0; +} + +static void set_userdata_poc(struct userdata_poc_info_t poc) +{ + userdata_poc_info[userdata_poc_wi] = poc; + userdata_poc_wi++; + if (userdata_poc_wi == USERDATA_FIFO_NUM) + userdata_poc_wi = 0; +} +EXPORT_SYMBOL(set_userdata_poc); + +void init_userdata_fifo(void) +{ + userdata_poc_ri = 0; + userdata_poc_wi = 0; + userdata_length = 0; +} +EXPORT_SYMBOL(init_userdata_fifo); + +void reset_userdata_fifo(int bInit) +{ + struct stream_buf_s *userdata_buf; + int wi, ri; + u32 rp, wp; + + mutex_lock(&userdata_mutex); + + wi = userdata_poc_wi; + ri = userdata_poc_ri; + + userdata_buf = &bufs[BUF_TYPE_USERDATA]; + rp = userdata_buf->buf_rp; + wp = userdata_buf->buf_wp; + if (bInit) { + /* decoder reset */ + userdata_buf->buf_rp = 0; + userdata_buf->buf_wp = 0; + userdata_poc_ri = 0; + userdata_poc_wi = 0; + } else { + /* just clean fifo buffer */ + userdata_buf->buf_rp = userdata_buf->buf_wp; + userdata_poc_ri = userdata_poc_wi; + } + userdata_length = 0; + last_read_wi = userdata_poc_wi; + + mutex_unlock(&userdata_mutex); + pr_debug("reset_userdata_fifo, bInit=%d, wi=%d, ri=%d, rp=%d, wp=%d\n", + bInit, wi, ri, rp, wp); +} +EXPORT_SYMBOL(reset_userdata_fifo); + +int wakeup_userdata_poll(struct userdata_poc_info_t poc, + int wp, + unsigned long start_phyaddr, + int buf_size, + int data_length) +{ + struct stream_buf_s *userdata_buf = &bufs[BUF_TYPE_USERDATA]; + mutex_lock(&userdata_mutex); + + if (data_length & 0x7) + data_length = (((data_length + 8) >> 3) << 3); + set_userdata_poc(poc); + userdata_buf->buf_start = start_phyaddr; + userdata_buf->buf_wp = wp; + userdata_buf->buf_size = buf_size; + atomic_set(&userdata_ready, 1); + userdata_length += data_length; + mutex_unlock(&userdata_mutex); + + wake_up_interruptible(&amstream_userdata_wait); + return userdata_buf->buf_rp; +} +EXPORT_SYMBOL(wakeup_userdata_poll); + +static unsigned int amstream_userdata_poll(struct file *file, + poll_table *wait_table) +{ + poll_wait(file, &amstream_userdata_wait, wait_table); + if (atomic_read(&userdata_ready)) { + atomic_set(&userdata_ready, 0); + return POLLIN | POLLRDNORM; + } + return 0; +} + +static ssize_t amstream_userdata_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + u32 data_size, res, retVal = 0; + u32 buf_wp, buf_rp, buf_size; + unsigned long buf_start; + struct stream_buf_s *userdata_buf = &bufs[BUF_TYPE_USERDATA]; +#ifdef DEBUG_USER_DATA + int old_wi; +#endif + + mutex_lock(&userdata_mutex); + + if (userdata_poc_ri != last_read_wi) { + /*********************************************** + app picks up poc counter wrong from last read user data + for H264. So, we need to recalculate userdata_poc_ri + to the userdata_poc_wi from the last read. + ***********************************************/ +#if 0 + pr_info("app pick up poc error: ri = %d, last_wi = %d\n", + userdata_poc_ri, last_read_wi); +#endif + userdata_poc_ri = last_read_wi; + } + + buf_wp = userdata_buf->buf_wp; + buf_rp = userdata_buf->buf_rp; + buf_size = userdata_buf->buf_size; + buf_start = userdata_buf->buf_start; +#ifdef DEBUG_USER_DATA + old_wi = last_read_wi; +#endif + last_read_wi = userdata_poc_wi; + mutex_unlock(&userdata_mutex); + + if (buf_start == 0 || buf_size == 0) + return 0; + if (buf_wp == buf_rp) + return 0; + if (buf_wp > buf_rp) + data_size = buf_wp - buf_rp; + else + data_size = buf_size - buf_rp + buf_wp; + + if (data_size > count) + data_size = count; +#ifdef DEBUG_USER_DATA + pr_info("wi:%d ri:%d wp:%d rp:%d size:%d, last_read_wi=%d\n", + userdata_poc_wi, userdata_poc_ri, + buf_wp, buf_rp, data_size, old_wi); +#endif + if (buf_wp < buf_rp) { + int first_num = buf_size - buf_rp; + if (data_size <= first_num) { + res = copy_to_user((void *)buf, + (void *)((buf_rp + + buf_start)), data_size); + if (res) + pr_info("p1 read not end res=%d, request=%d\n", + res, data_size); + + mutex_lock(&userdata_mutex); + userdata_buf->buf_rp += data_size - res; + mutex_unlock(&userdata_mutex); + retVal = data_size - res; + } else { + if (first_num > 0) { + res = copy_to_user((void *)buf, + (void *)((buf_rp + + buf_start)), first_num); + if (res) + pr_info("p2 read not end res=%d, request=%d\n", + res, first_num); + + res = copy_to_user((void *)buf+first_num, + (void *)(buf_start), + data_size - first_num); + + if (res) + pr_info("p3 read not end res=%d, request=%d\n", + res, data_size - first_num); + + mutex_lock(&userdata_mutex); + userdata_buf->buf_rp += data_size; + if (userdata_buf->buf_rp >= buf_size) + userdata_buf->buf_rp = + userdata_buf->buf_rp - buf_size; + mutex_unlock(&userdata_mutex); + + retVal = data_size; + } else { + /* first_num == 0*/ + res = copy_to_user((void *)buf, + (void *)((buf_start)), + data_size - first_num); + mutex_lock(&userdata_mutex); + userdata_buf->buf_rp = + data_size - first_num - res; + mutex_unlock(&userdata_mutex); + retVal = data_size - first_num - res; + } + } + } else { + res = copy_to_user((void *)buf, + (void *)((buf_rp + buf_start)), + data_size); + if (res) + pr_info("p4 read not end res=%d, request=%d\n", + res, data_size); + + mutex_lock(&userdata_mutex); + userdata_buf->buf_rp += data_size - res; + mutex_unlock(&userdata_mutex); + retVal = data_size - res; + } + return retVal; +} + +static int amstream_open(struct inode *inode, struct file *file) +{ + s32 i; + struct stream_port_s *s; + struct stream_port_s *port = &ports[iminor(inode)]; + struct port_priv_s *priv; +#ifdef G12A_BRINGUP_DEBUG + if (vdec_get_debug_flags() & 0xff0000) { + pr_info("%s force open port %d\n", + __func__, + ((vdec_get_debug_flags() >> 16) & 0xff) - 1); + port = &ports[((vdec_get_debug_flags() >> 16) & 0xff) - 1]; + } + pr_info("%s, port name %s\n", __func__, port->name); +#endif + if (iminor(inode) >= amstream_port_num) + return -ENODEV; + + mutex_lock(&amstream_mutex); + + if (port->type & PORT_TYPE_VIDEO) { + for (s = &ports[0], i = 0; i < amstream_port_num; i++, s++) { + if ((!is_mult_inc(s->type)) && + (s->type & PORT_TYPE_VIDEO) && + (s->flag & PORT_FLAG_IN_USE)) { + mutex_unlock(&amstream_mutex); + return -EBUSY; + } + } + } + + if ((port->flag & PORT_FLAG_IN_USE) && + ((port->type & PORT_TYPE_FRAME) == 0)) { + mutex_unlock(&amstream_mutex); + return -EBUSY; + } + + /* check other ports conflicts for audio */ + for (s = &ports[0], i = 0; i < amstream_port_num; i++, s++) { + if ((s->flag & PORT_FLAG_IN_USE) && + ((port->type) & (s->type) & PORT_TYPE_AUDIO)) { + mutex_unlock(&amstream_mutex); + return -EBUSY; + } + } + + priv = kzalloc(sizeof(struct port_priv_s), GFP_KERNEL); + if (priv == NULL) { + mutex_unlock(&amstream_mutex); + return -ENOMEM; + } + + priv->port = port; + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M6) { + /* TODO: mod gate */ + /* switch_mod_gate_by_name("demux", 1); */ + amports_switch_gate("demux", 1); + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) { + /* TODO: clc gate */ + /* CLK_GATE_ON(HIU_PARSER_TOP); */ + amports_switch_gate("parser_top", 1); + } + + if (port->type & PORT_TYPE_VIDEO) { + /* TODO: mod gate */ + /* switch_mod_gate_by_name("vdec", 1); */ + amports_switch_gate("vdec", 1); + + if (has_hevc_vdec()) { + if (port->type & + (PORT_TYPE_MPTS | PORT_TYPE_HEVC)) { + amports_switch_gate("clk_hevc_mux", 1); + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) + amports_switch_gate("clk_hevcb_mux", 1); + vdec_poweron(VDEC_HEVC); + } + + if ((port->type & PORT_TYPE_HEVC) == 0) { + amports_switch_gate("clk_vdec_mux", 1); + vdec_poweron(VDEC_1); + } + } else { + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) { + amports_switch_gate("clk_vdec_mux", 1); + vdec_poweron(VDEC_1); + } + } + } + + if (port->type & PORT_TYPE_AUDIO) { + /* TODO: mod gate */ + /* switch_mod_gate_by_name("audio", 1); */ + amports_switch_gate("audio", 1); + } + } + + port->vid = 0; + port->aid = 0; + port->sid = 0; + port->pcrid = 0xffff; + file->f_op = port->fops; + file->private_data = priv; + + port->flag = PORT_FLAG_IN_USE; + port->pcr_inited = 0; +#ifdef DATA_DEBUG + debug_filp = filp_open(DEBUG_FILE_NAME, O_WRONLY, 0); + if (IS_ERR(debug_filp)) { + pr_err("amstream: open debug file failed\n"); + debug_filp = NULL; + } +#endif + mutex_unlock(&amstream_mutex); + + if (port->type & PORT_TYPE_VIDEO) { + priv->vdec = vdec_create(port, NULL); + + if (priv->vdec == NULL) { + port->flag = 0; + kfree(priv); + pr_err("amstream: vdec creation failed\n"); + return -ENOMEM; + } + + if ((port->type & PORT_TYPE_DUALDEC) || + (vdec_get_debug_flags() & 0x100)) { + priv->vdec->slave = vdec_create(port, priv->vdec); + + if (priv->vdec->slave == NULL) { + vdec_release(priv->vdec); + port->flag = 0; + kfree(priv); + pr_err("amstream: sub vdec creation failed\n"); + return -ENOMEM; + } + } + } + return 0; +} + +static int amstream_release(struct inode *inode, struct file *file) +{ + struct port_priv_s *priv = file->private_data; + struct stream_port_s *port = priv->port; + struct vdec_s *slave = NULL; +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + u32 port_flag = 0; +#endif + + if (iminor(inode) >= amstream_port_num) + return -ENODEV; + + mutex_lock(&amstream_mutex); + + if (port_get_inited(priv)) + amstream_port_release(priv); + + if (priv->vdec) { +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + port_flag = priv->vdec->port_flag; +#endif + if (priv->vdec->slave) + slave = priv->vdec->slave; + vdec_release(priv->vdec); + if (slave) + vdec_release(slave); + priv->vdec = NULL; + } + + if ((port->type & (PORT_TYPE_AUDIO | PORT_TYPE_VIDEO)) == + PORT_TYPE_AUDIO) { + s32 i; + struct stream_port_s *s; + + for (s = &ports[0], i = 0; i < amstream_port_num; i++, s++) { + if ((s->flag & PORT_FLAG_IN_USE) + && (s->type & PORT_TYPE_VIDEO)) + break; + } + if (i == amstream_port_num) + timestamp_firstvpts_set(0); + } + port->flag = 0; + + /* timestamp_pcrscr_set(0); */ + +#ifdef DATA_DEBUG + if (debug_filp) { + filp_close(debug_filp, current->files); + debug_filp = NULL; + debug_file_pos = 0; + } +#endif + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M6) { + if (port->type & PORT_TYPE_VIDEO) { + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) { +#ifndef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + if (has_hevc_vdec()) + vdec_poweroff(VDEC_HEVC); + + vdec_poweroff(VDEC_1); +#else + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXLX + && port->vformat == VFORMAT_H264 + && bufs[BUF_TYPE_VIDEO].for_4k) + vdec_poweroff(VDEC_HEVC); + + if ((port->vformat == VFORMAT_HEVC + || port->vformat == VFORMAT_AVS2 + || port->vformat == VFORMAT_VP9)) { + vdec_poweroff(VDEC_HEVC); + } else { + vdec_poweroff(VDEC_1); + } +#endif + } + /* TODO: mod gate */ + /* switch_mod_gate_by_name("vdec", 0); */ + amports_switch_gate("vdec", 0); + } + + if (port->type & PORT_TYPE_AUDIO) { + /* TODO: mod gate */ + /* switch_mod_gate_by_name("audio", 0); */ + /* amports_switch_gate("audio", 0); */ + } + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M8) { + /* TODO: clc gate */ + /* CLK_GATE_OFF(HIU_PARSER_TOP); */ + amports_switch_gate("parser_top", 0); + } + /* TODO: mod gate */ + /* switch_mod_gate_by_name("demux", 0); */ + amports_switch_gate("demux", 0); + } + + kfree(priv); + + mutex_unlock(&amstream_mutex); + return 0; +} + +static long amstream_ioctl_get_version(struct port_priv_s *priv, + ulong arg) +{ + int version = (AMSTREAM_IOC_VERSION_FIRST & 0xffff) << 16 + | (AMSTREAM_IOC_VERSION_SECOND & 0xffff); + put_user(version, (u32 __user *)arg); + + return 0; +} +static long amstream_ioctl_get(struct port_priv_s *priv, ulong arg) +{ + struct stream_port_s *this = priv->port; + long r = 0; + + struct am_ioctl_parm parm; + + if (copy_from_user + ((void *)&parm, (void *)arg, + sizeof(parm))) + r = -EFAULT; + + switch (parm.cmd) { + case AMSTREAM_GET_SUB_LENGTH: + if ((this->type & PORT_TYPE_SUB) || + (this->type & PORT_TYPE_SUB_RD)) { + u32 sub_wp, sub_rp; + struct stream_buf_s *psbuf = &bufs[BUF_TYPE_SUBTITLE]; + int val; + + sub_wp = stbuf_sub_wp_get(); + sub_rp = stbuf_sub_rp_get(); + + if (sub_wp == sub_rp) + val = 0; + else if (sub_wp > sub_rp) + val = sub_wp - sub_rp; + else + val = psbuf->buf_size - (sub_rp - sub_wp); + parm.data_32 = val; + } else + r = -EINVAL; + break; + case AMSTREAM_GET_UD_LENGTH: + if (this->type & PORT_TYPE_USERDATA) { + parm.data_32 = userdata_length; + userdata_length = 0; + } else + r = -EINVAL; + break; + case AMSTREAM_GET_APTS_LOOKUP: + if (this->type & PORT_TYPE_AUDIO) { + u32 pts = 0, offset; + + offset = parm.data_32; + pts_lookup_offset(PTS_TYPE_AUDIO, offset, &pts, 300); + parm.data_32 = pts; + } + break; + case AMSTREAM_GET_FIRST_APTS_FLAG: + if (this->type & PORT_TYPE_AUDIO) { + parm.data_32 = first_pts_checkin_complete( + PTS_TYPE_AUDIO); + } + break; + case AMSTREAM_GET_APTS: + parm.data_32 = timestamp_apts_get(); + break; + case AMSTREAM_GET_VPTS: + parm.data_32 = timestamp_vpts_get(); + break; + case AMSTREAM_GET_PCRSCR: + parm.data_32 = timestamp_pcrscr_get(); + break; + case AMSTREAM_GET_LAST_CHECKIN_APTS: + parm.data_32 = get_last_checkin_pts(PTS_TYPE_AUDIO); + break; + case AMSTREAM_GET_LAST_CHECKIN_VPTS: + parm.data_32 = get_last_checkin_pts(PTS_TYPE_VIDEO); + break; + case AMSTREAM_GET_LAST_CHECKOUT_APTS: + parm.data_32 = get_last_checkout_pts(PTS_TYPE_AUDIO); + break; + case AMSTREAM_GET_LAST_CHECKOUT_VPTS: + parm.data_32 = get_last_checkout_pts(PTS_TYPE_VIDEO); + break; + case AMSTREAM_GET_SUB_NUM: + parm.data_32 = psparser_get_sub_found_num(); + break; + case AMSTREAM_GET_VIDEO_DELAY_LIMIT_MS: + parm.data_32 = bufs[BUF_TYPE_VIDEO].max_buffer_delay_ms; + break; + case AMSTREAM_GET_AUDIO_DELAY_LIMIT_MS: + parm.data_32 = bufs[BUF_TYPE_AUDIO].max_buffer_delay_ms; + break; + case AMSTREAM_GET_VIDEO_CUR_DELAY_MS: { + int delay; + + delay = calculation_stream_delayed_ms( + PTS_TYPE_VIDEO, NULL, NULL); + if (delay >= 0) + parm.data_32 = delay; + else + parm.data_32 = 0; + } + break; + + case AMSTREAM_GET_AUDIO_CUR_DELAY_MS: { + int delay; + + delay = calculation_stream_delayed_ms( + PTS_TYPE_AUDIO, NULL, NULL); + if (delay >= 0) + parm.data_32 = delay; + else + parm.data_32 = 0; + } + break; + case AMSTREAM_GET_AUDIO_AVG_BITRATE_BPS: { + int delay; + u32 avgbps; + + delay = calculation_stream_delayed_ms( + PTS_TYPE_AUDIO, NULL, &avgbps); + if (delay >= 0) + parm.data_32 = avgbps; + else + parm.data_32 = 0; + } + break; + case AMSTREAM_GET_VIDEO_AVG_BITRATE_BPS: { + int delay; + u32 avgbps; + + delay = calculation_stream_delayed_ms( + PTS_TYPE_VIDEO, NULL, &avgbps); + if (delay >= 0) + parm.data_32 = avgbps; + else + parm.data_32 = 0; + } + break; + case AMSTREAM_GET_ION_ID: + parm.data_32 = priv->vdec->vf_receiver_inst; + break; + case AMSTREAM_GET_NEED_MORE_DATA: + parm.data_32 = vdec_need_more_data(priv->vdec); + break; + default: + r = -ENOIOCTLCMD; + break; + } + /* pr_info("parm size:%d\n", sizeof(parm)); */ + if (r == 0) { + if (copy_to_user((void *)arg, &parm, sizeof(parm))) + r = -EFAULT; + } + + return r; + +} +static long amstream_ioctl_set(struct port_priv_s *priv, ulong arg) +{ + struct stream_port_s *this = priv->port; + struct am_ioctl_parm parm; + long r = 0; + + if (copy_from_user + ((void *)&parm, (void *)arg, + sizeof(parm))) + r = -EFAULT; + + switch (parm.cmd) { + case AMSTREAM_SET_VB_START: + if ((this->type & PORT_TYPE_VIDEO) && + ((bufs[BUF_TYPE_VIDEO].flag & BUF_FLAG_IN_USE) == 0)) { + if (has_hevc_vdec()) + bufs[BUF_TYPE_HEVC].buf_start = parm.data_32; + bufs[BUF_TYPE_VIDEO].buf_start = parm.data_32; + } else + r = -EINVAL; + break; + case AMSTREAM_SET_VB_SIZE: + if ((this->type & PORT_TYPE_VIDEO) && + ((bufs[BUF_TYPE_VIDEO].flag & BUF_FLAG_IN_USE) == 0)) { + if (bufs[BUF_TYPE_VIDEO].flag & BUF_FLAG_ALLOC) { + if (has_hevc_vdec()) { + r = stbuf_change_size( + &bufs[BUF_TYPE_HEVC], + parm.data_32, + false); + } + r = stbuf_change_size( + &bufs[BUF_TYPE_VIDEO], + parm.data_32, + false); + } + } else if (this->type & PORT_TYPE_FRAME) { + /* todo: frame based set max buffer size */ + r = 0; + } else + r = -EINVAL; + break; + case AMSTREAM_SET_AB_START: + if ((this->type & PORT_TYPE_AUDIO) && + ((bufs[BUF_TYPE_AUDIO].flag & BUF_FLAG_IN_USE) == 0)) + bufs[BUF_TYPE_AUDIO].buf_start = parm.data_32; + else + r = -EINVAL; + break; + case AMSTREAM_SET_AB_SIZE: + if ((this->type & PORT_TYPE_AUDIO) && + ((bufs[BUF_TYPE_AUDIO].flag & BUF_FLAG_IN_USE) == 0)) { + if (bufs[BUF_TYPE_AUDIO].flag & BUF_FLAG_ALLOC) { + r = stbuf_change_size( + &bufs[BUF_TYPE_AUDIO], + parm.data_32, + false); + } + } else + r = -EINVAL; + break; + case AMSTREAM_SET_VFORMAT: + if ((this->type & PORT_TYPE_VIDEO) && + (parm.data_vformat < VFORMAT_MAX)) { + this->vformat = parm.data_vformat; + this->flag |= PORT_FLAG_VFORMAT; + + vdec_set_format(priv->vdec, this->vformat); + } else + r = -EINVAL; + break; + case AMSTREAM_SET_AFORMAT: + if ((this->type & PORT_TYPE_AUDIO) && + (parm.data_aformat < AFORMAT_MAX)) { + memset(&audio_dec_info, 0, + sizeof(struct audio_info)); + /* for new format,reset the audio info. */ + this->aformat = parm.data_aformat; + this->flag |= PORT_FLAG_AFORMAT; + } else + r = -EINVAL; + break; + case AMSTREAM_SET_VID: + if (this->type & PORT_TYPE_VIDEO) { + this->vid = parm.data_32; + this->flag |= PORT_FLAG_VID; + } else + r = -EINVAL; + + break; + case AMSTREAM_SET_AID: + if (this->type & PORT_TYPE_AUDIO) { + this->aid = parm.data_32; + this->flag |= PORT_FLAG_AID; + + if (port_get_inited(priv)) { + tsync_audio_break(1); + amstream_change_avid(this); + } + } else + r = -EINVAL; + break; + case AMSTREAM_SET_SID: + if (this->type & PORT_TYPE_SUB) { + this->sid = parm.data_32; + this->flag |= PORT_FLAG_SID; + + if (port_get_inited(priv)) + amstream_change_sid(this); + } else + r = -EINVAL; + + break; + case AMSTREAM_IOC_PCRID: + this->pcrid = parm.data_32; + this->pcr_inited = 1; + pr_err("set pcrid = 0x%x\n", this->pcrid); + break; + case AMSTREAM_SET_ACHANNEL: + if (this->type & PORT_TYPE_AUDIO) { + this->achanl = parm.data_32; + set_ch_num_info(parm.data_32); + } else + r = -EINVAL; + break; + case AMSTREAM_SET_SAMPLERATE: + if (this->type & PORT_TYPE_AUDIO) { + this->asamprate = parm.data_32; + set_sample_rate_info(parm.data_32); + } else + r = -EINVAL; + break; + case AMSTREAM_SET_DATAWIDTH: + if (this->type & PORT_TYPE_AUDIO) + this->adatawidth = parm.data_32; + else + r = -EINVAL; + break; + case AMSTREAM_SET_TSTAMP: + if ((this->type & (PORT_TYPE_AUDIO | PORT_TYPE_VIDEO)) == + ((PORT_TYPE_AUDIO | PORT_TYPE_VIDEO))) + r = -EINVAL; + else if (this->type & PORT_TYPE_FRAME) + r = vdec_set_pts(priv->vdec, parm.data_32); + else if (has_hevc_vdec() && this->type & PORT_TYPE_HEVC) + r = es_vpts_checkin(&bufs[BUF_TYPE_HEVC], + parm.data_32); + else if (this->type & PORT_TYPE_VIDEO) + r = es_vpts_checkin(&bufs[BUF_TYPE_VIDEO], + parm.data_32); + else if (this->type & PORT_TYPE_AUDIO) + r = es_apts_checkin(&bufs[BUF_TYPE_AUDIO], + parm.data_32); + break; + case AMSTREAM_SET_TSTAMP_US64: + if ((this->type & (PORT_TYPE_AUDIO | PORT_TYPE_VIDEO)) == + ((PORT_TYPE_AUDIO | PORT_TYPE_VIDEO))) + r = -EINVAL; + else { + u64 pts = parm.data_64; + + if (this->type & PORT_TYPE_FRAME) { + /* + *todo: check upper layer for decoder handler + * life sequence or multi-tasking management + */ + r = vdec_set_pts64(priv->vdec, pts); + } else if (has_hevc_vdec()) { + if (this->type & PORT_TYPE_HEVC) { + r = es_vpts_checkin_us64( + &bufs[BUF_TYPE_HEVC], pts); + } else if (this->type & PORT_TYPE_VIDEO) { + r = es_vpts_checkin_us64( + &bufs[BUF_TYPE_VIDEO], pts); + } else if (this->type & PORT_TYPE_AUDIO) { + r = es_vpts_checkin_us64( + &bufs[BUF_TYPE_AUDIO], pts); + } + } else { + if (this->type & PORT_TYPE_VIDEO) { + r = es_vpts_checkin_us64( + &bufs[BUF_TYPE_VIDEO], pts); + } else if (this->type & PORT_TYPE_AUDIO) { + r = es_vpts_checkin_us64( + &bufs[BUF_TYPE_AUDIO], pts); + } + } + } + break; + case AMSTREAM_PORT_INIT: + r = amstream_port_init(priv); + break; + case AMSTREAM_SET_TRICKMODE: + if ((this->type & PORT_TYPE_VIDEO) == 0) + return -EINVAL; + r = vdec_set_trickmode(priv->vdec, parm.data_32); + if (r == -1) + return -ENODEV; + break; + + case AMSTREAM_AUDIO_RESET: + if (this->type & PORT_TYPE_AUDIO) { + struct stream_buf_s *pabuf = &bufs[BUF_TYPE_AUDIO]; + + r = audio_port_reset(this, pabuf); + } else + r = -EINVAL; + + break; + case AMSTREAM_SUB_RESET: + if (this->type & PORT_TYPE_SUB) { + struct stream_buf_s *psbuf = &bufs[BUF_TYPE_SUBTITLE]; + + r = sub_port_reset(this, psbuf); + } else + r = -EINVAL; + break; + case AMSTREAM_DEC_RESET: + tsync_set_dec_reset(); + break; + case AMSTREAM_SET_TS_SKIPBYTE: + if (parm.data_32 >= 0) + tsdemux_set_skipbyte(parm.data_32); + else + r = -EINVAL; + break; + case AMSTREAM_SET_SUB_TYPE: + sub_type = parm.data_32; + break; + case AMSTREAM_SET_PCRSCR: + timestamp_pcrscr_set(parm.data_32); + break; + case AMSTREAM_SET_DEMUX: + tsdemux_set_demux(parm.data_32); + break; + case AMSTREAM_SET_VIDEO_DELAY_LIMIT_MS: + if (has_hevc_vdec()) + bufs[BUF_TYPE_HEVC].max_buffer_delay_ms = parm.data_32; + bufs[BUF_TYPE_VIDEO].max_buffer_delay_ms = parm.data_32; + break; + case AMSTREAM_SET_AUDIO_DELAY_LIMIT_MS: + bufs[BUF_TYPE_AUDIO].max_buffer_delay_ms = parm.data_32; + break; + case AMSTREAM_SET_DRMMODE: + if (parm.data_32 == 1) { + pr_debug("set drmmode\n"); + this->flag |= PORT_FLAG_DRM; + if ((this->type & PORT_TYPE_VIDEO) && + (priv->vdec)) + priv->vdec->port_flag |= PORT_FLAG_DRM; + } else { + this->flag &= (~PORT_FLAG_DRM); + pr_debug("no drmmode\n"); + } + break; + case AMSTREAM_SET_APTS: { + unsigned int pts; + + pts = parm.data_32; + if (tsync_get_mode() == TSYNC_MODE_PCRMASTER) + tsync_pcr_set_apts(pts); + else + tsync_set_apts(pts); + break; + } + case AMSTREAM_SET_FRAME_BASE_PATH: + if (is_mult_inc(this->type) && + (parm.frame_base_video_path < FRAME_BASE_PATH_MAX)) { + vdec_set_video_path(priv->vdec, parm.data_32); + } else + r = -EINVAL; + break; + case AMSTREAM_SET_EOS: + if (priv->vdec) + vdec_set_eos(priv->vdec, parm.data_32); + break; + case AMSTREAM_SET_RECEIVE_ID: + if (is_mult_inc(this->type)) + vdec_set_receive_id(priv->vdec, parm.data_32); + else + r = -EINVAL; + break; + case AMSTREAM_SET_IS_RESET: + if (priv->vdec) + vdec_set_isreset(priv->vdec, parm.data_32); + break; + case AMSTREAM_SET_DV_META_WITH_EL: + if (priv->vdec) { + vdec_set_dv_metawithel(priv->vdec, parm.data_32); + if (vdec_dual(priv->vdec) && priv->vdec->slave) + vdec_set_dv_metawithel(priv->vdec->slave, + parm.data_32); + } + break; + case AMSTREAM_SET_NO_POWERDOWN: + vdec_set_no_powerdown(parm.data_32); + break; + default: + r = -ENOIOCTLCMD; + break; + } + return r; +} +static long amstream_ioctl_get_ex(struct port_priv_s *priv, ulong arg) +{ + struct stream_port_s *this = priv->port; + long r = 0; + struct am_ioctl_parm_ex parm; + + if (copy_from_user + ((void *)&parm, (void *)arg, + sizeof(parm))) + r = -EFAULT; + + switch (parm.cmd) { + case AMSTREAM_GET_EX_VB_STATUS: + if (this->type & PORT_TYPE_VIDEO) { + struct am_ioctl_parm_ex *p = &parm; + struct stream_buf_s *buf = NULL; + + buf = (this->vformat == VFORMAT_HEVC || + this->vformat == VFORMAT_AVS2 || + this->vformat == VFORMAT_VP9) ? + &bufs[BUF_TYPE_HEVC] : + &bufs[BUF_TYPE_VIDEO]; + + if (p == NULL) { + r = -EINVAL; + break; + } + + if (this->type & PORT_TYPE_FRAME) { + struct vdec_input_status_s status; + + /* + *todo: check upper layer for decoder + * handler lifecycle + */ + if (priv->vdec == NULL) { + r = -EINVAL; + break; + } + + r = vdec_input_get_status(&priv->vdec->input, + &status); + if (r == 0) { + p->status.size = status.size; + p->status.data_len = status.data_len; + p->status.free_len = status.free_len; + p->status.read_pointer = + status.read_pointer; + } + break; + } + + p->status.size = stbuf_canusesize(buf); + p->status.data_len = stbuf_level(buf); + p->status.free_len = stbuf_space(buf); + p->status.read_pointer = stbuf_rp(buf); + } else + r = -EINVAL; + break; + case AMSTREAM_GET_EX_AB_STATUS: + if (this->type & PORT_TYPE_AUDIO) { + struct am_ioctl_parm_ex *p = &parm; + struct stream_buf_s *buf = &bufs[BUF_TYPE_AUDIO]; + + if (p == NULL) + r = -EINVAL; + + p->status.size = stbuf_canusesize(buf); + p->status.data_len = stbuf_level(buf); + p->status.free_len = stbuf_space(buf); + p->status.read_pointer = stbuf_rp(buf); + + } else + r = -EINVAL; + break; + case AMSTREAM_GET_EX_VDECSTAT: + if ((this->type & PORT_TYPE_VIDEO) == 0) { + pr_err("no video\n"); + return -EINVAL; + } else { + struct vdec_info vstatus; + struct am_ioctl_parm_ex *p = &parm; + + if (p == NULL) + return -EINVAL; + if (vdec_status(priv->vdec, &vstatus) == -1) + return -ENODEV; + p->vstatus.width = vstatus.frame_width; + p->vstatus.height = vstatus.frame_height; + p->vstatus.fps = vstatus.frame_rate; + p->vstatus.error_count = vstatus.error_count; + p->vstatus.status = vstatus.status; + } + break; + case AMSTREAM_GET_EX_ADECSTAT: + if ((this->type & PORT_TYPE_AUDIO) == 0) { + pr_err("no audio\n"); + return -EINVAL; + } + if (amstream_adec_status == NULL) { + /* + *pr_err("no amstream_adec_status\n"); + *return -ENODEV; + */ + memset(&parm.astatus, 0, sizeof(parm.astatus)); + } else { + struct adec_status astatus; + struct am_ioctl_parm_ex *p = &parm; + + if (p == NULL) + return -EINVAL; + amstream_adec_status(&astatus); + p->astatus.channels = astatus.channels; + p->astatus.sample_rate = astatus.sample_rate; + p->astatus.resolution = astatus.resolution; + p->astatus.error_count = astatus.error_count; + p->astatus.status = astatus.status; + } + break; + + case AMSTREAM_GET_EX_UD_POC: + if (this->type & PORT_TYPE_USERDATA) { + struct userdata_poc_info_t userdata_poc = + userdata_poc_info[userdata_poc_ri]; + memcpy(&parm.data_userdata_info, + &userdata_poc, + sizeof(struct userdata_poc_info_t)); + + userdata_poc_ri++; + if (userdata_poc_ri == USERDATA_FIFO_NUM) + userdata_poc_ri = 0; + } else + r = -EINVAL; + break; + default: + r = -ENOIOCTLCMD; + break; + } + /* pr_info("parm size:%zx\n", sizeof(parm)); */ + if (r == 0) { + if (copy_to_user((void *)arg, &parm, sizeof(parm))) + r = -EFAULT; + } + return r; + +} +static long amstream_ioctl_set_ex(struct port_priv_s *priv, ulong arg) +{ + long r = 0; + return r; +} +static long amstream_ioctl_get_ptr(struct port_priv_s *priv, ulong arg) +{ + long r = 0; + + struct am_ioctl_parm_ptr parm; + + if (copy_from_user + ((void *)&parm, (void *)arg, + sizeof(parm))) + r = -EFAULT; + + switch (parm.cmd) { + case AMSTREAM_GET_PTR_SUB_INFO: + { + struct subtitle_info msub_info[MAX_SUB_NUM]; + struct subtitle_info *psub_info[MAX_SUB_NUM]; + int i; + + for (i = 0; i < MAX_SUB_NUM; i++) + psub_info[i] = &msub_info[i]; + + r = psparser_get_sub_info(psub_info); + + if (r == 0) { + memcpy(parm.pdata_sub_info, msub_info, + sizeof(struct subtitle_info) + * MAX_SUB_NUM); + } + } + break; + default: + r = -ENOIOCTLCMD; + break; + } + /* pr_info("parm size:%d\n", sizeof(parm)); */ + if (r == 0) { + if (copy_to_user((void *)arg, &parm, sizeof(parm))) + r = -EFAULT; + } + + return r; + +} +static long amstream_ioctl_set_ptr(struct port_priv_s *priv, ulong arg) +{ + struct stream_port_s *this = priv->port; + struct am_ioctl_parm_ptr parm; + long r = 0; + + if (copy_from_user + ((void *)&parm, (void *)arg, + sizeof(parm))) { + pr_err("[%s]%d, arg err\n", __func__, __LINE__); + r = -EFAULT; + } + switch (parm.cmd) { + case AMSTREAM_SET_PTR_AUDIO_INFO: + if ((this->type & PORT_TYPE_VIDEO) + || (this->type & PORT_TYPE_AUDIO)) { + if (parm.pdata_audio_info != NULL) + memcpy((void *)&audio_dec_info, + (void *)parm.pdata_audio_info, + sizeof(audio_dec_info)); + } else + r = -EINVAL; + break; + case AMSTREAM_SET_PTR_CONFIGS: + if (this->type & PORT_TYPE_VIDEO) { + if (!parm.pointer || (parm.len <= 0) || + (parm.len > PAGE_SIZE)) { + r = -EINVAL; + } else { + r = copy_from_user(priv->vdec->config, + parm.pointer, parm.len); + if (r) + r = -EINVAL; + else + priv->vdec->config_len = parm.len; + } + } else + r = -EINVAL; + break; + default: + r = -ENOIOCTLCMD; + break; + } + return r; +} + +static long amstream_do_ioctl_new(struct port_priv_s *priv, + unsigned int cmd, ulong arg) +{ + long r = 0; + struct stream_port_s *this = priv->port; + + switch (cmd) { + case AMSTREAM_IOC_GET_VERSION: + r = amstream_ioctl_get_version(priv, arg); + break; + case AMSTREAM_IOC_GET: + r = amstream_ioctl_get(priv, arg); + break; + case AMSTREAM_IOC_SET: + r = amstream_ioctl_set(priv, arg); + break; + case AMSTREAM_IOC_GET_EX: + r = amstream_ioctl_get_ex(priv, arg); + break; + case AMSTREAM_IOC_SET_EX: + r = amstream_ioctl_set_ex(priv, arg); + break; + case AMSTREAM_IOC_GET_PTR: + r = amstream_ioctl_get_ptr(priv, arg); + break; + case AMSTREAM_IOC_SET_PTR: + r = amstream_ioctl_set_ptr(priv, arg); + break; + case AMSTREAM_IOC_SYSINFO: + if (this->type & PORT_TYPE_VIDEO) + r = vdec_set_decinfo(priv->vdec, (void *)arg); + else + r = -EINVAL; + break; + default: + r = -ENOIOCTLCMD; + break; + } + + return r; +} + +static long amstream_do_ioctl_old(struct port_priv_s *priv, + unsigned int cmd, ulong arg) +{ + struct stream_port_s *this = priv->port; + long r = 0; + + switch (cmd) { + + case AMSTREAM_IOC_VB_START: + if ((this->type & PORT_TYPE_VIDEO) && + ((bufs[BUF_TYPE_VIDEO].flag & BUF_FLAG_IN_USE) == 0)) { + if (has_hevc_vdec()) + bufs[BUF_TYPE_HEVC].buf_start = arg; + bufs[BUF_TYPE_VIDEO].buf_start = arg; + } else + r = -EINVAL; + break; + + case AMSTREAM_IOC_VB_SIZE: + if ((this->type & PORT_TYPE_VIDEO) && + ((bufs[BUF_TYPE_VIDEO].flag & BUF_FLAG_IN_USE) == 0)) { + if (bufs[BUF_TYPE_VIDEO].flag & BUF_FLAG_ALLOC) { + if (has_hevc_vdec()) { + r = stbuf_change_size( + &bufs[BUF_TYPE_HEVC], + arg, false); + } + r = stbuf_change_size( + &bufs[BUF_TYPE_VIDEO], + arg, false); + } + } else + r = -EINVAL; + break; + + case AMSTREAM_IOC_AB_START: + if ((this->type & PORT_TYPE_AUDIO) && + ((bufs[BUF_TYPE_AUDIO].flag & BUF_FLAG_IN_USE) == 0)) + bufs[BUF_TYPE_AUDIO].buf_start = arg; + else + r = -EINVAL; + break; + + case AMSTREAM_IOC_AB_SIZE: + if ((this->type & PORT_TYPE_AUDIO) && + ((bufs[BUF_TYPE_AUDIO].flag & BUF_FLAG_IN_USE) == 0)) { + if (bufs[BUF_TYPE_AUDIO].flag & BUF_FLAG_ALLOC) { + r = stbuf_change_size( + &bufs[BUF_TYPE_AUDIO], arg, false); + } + } else + r = -EINVAL; + break; + + case AMSTREAM_IOC_VFORMAT: + if ((this->type & PORT_TYPE_VIDEO) && (arg < VFORMAT_MAX)) { + this->vformat = (enum vformat_e)arg; + this->flag |= PORT_FLAG_VFORMAT; + + vdec_set_format(priv->vdec, this->vformat); + } else + r = -EINVAL; + break; + + case AMSTREAM_IOC_AFORMAT: + if ((this->type & PORT_TYPE_AUDIO) && (arg < AFORMAT_MAX)) { + memset(&audio_dec_info, 0, + sizeof(struct audio_info)); + /* for new format,reset the audio info. */ + this->aformat = (enum aformat_e)arg; + this->flag |= PORT_FLAG_AFORMAT; + } else + r = -EINVAL; + break; + + case AMSTREAM_IOC_VID: + if (this->type & PORT_TYPE_VIDEO) { + this->vid = (u32) arg; + this->flag |= PORT_FLAG_VID; + } else + r = -EINVAL; + + break; + + case AMSTREAM_IOC_AID: + if (this->type & PORT_TYPE_AUDIO) { + this->aid = (u32) arg; + this->flag |= PORT_FLAG_AID; + + if (port_get_inited(priv)) { + tsync_audio_break(1); + amstream_change_avid(this); + } + } else + r = -EINVAL; + break; + + case AMSTREAM_IOC_SID: + if (this->type & PORT_TYPE_SUB) { + this->sid = (u32) arg; + this->flag |= PORT_FLAG_SID; + + if (port_get_inited(priv)) + amstream_change_sid(this); + } else + r = -EINVAL; + + break; + + case AMSTREAM_IOC_PCRID: + this->pcrid = (u32) arg; + this->pcr_inited = 1; + pr_err("set pcrid = 0x%x\n", this->pcrid); + break; + + case AMSTREAM_IOC_VB_STATUS: + if (this->type & PORT_TYPE_VIDEO) { + struct am_io_param para; + struct am_io_param *p = ¶ + struct stream_buf_s *buf = NULL; + + buf = (this->vformat == VFORMAT_HEVC || + this->vformat == VFORMAT_AVS2 || + this->vformat == VFORMAT_VP9) ? + &bufs[BUF_TYPE_HEVC] : + &bufs[BUF_TYPE_VIDEO]; + + if (p == NULL) { + r = -EINVAL; + break; + } + + if (this->type & PORT_TYPE_FRAME) { + struct vdec_input_status_s status; + + /* + *todo: check upper layer for decoder + * handler lifecycle + */ + if (priv->vdec == NULL) { + r = -EINVAL; + break; + } + + r = vdec_input_get_status(&priv->vdec->input, + &status); + if (r == 0) { + p->status.size = status.size; + p->status.data_len = status.data_len; + p->status.free_len = status.free_len; + p->status.read_pointer = + status.read_pointer; + if (copy_to_user((void *)arg, p, + sizeof(para))) + r = -EFAULT; + } + break; + } + + p->status.size = stbuf_canusesize(buf); + p->status.data_len = stbuf_level(buf); + p->status.free_len = stbuf_space(buf); + p->status.read_pointer = stbuf_rp(buf); + if (copy_to_user((void *)arg, p, sizeof(para))) + r = -EFAULT; + return r; + } + r = -EINVAL; + break; + + case AMSTREAM_IOC_AB_STATUS: + if (this->type & PORT_TYPE_AUDIO) { + struct am_io_param para; + struct am_io_param *p = ¶ + struct stream_buf_s *buf = &bufs[BUF_TYPE_AUDIO]; + + if (p == NULL) + r = -EINVAL; + + p->status.size = stbuf_canusesize(buf); + p->status.data_len = stbuf_level(buf); + p->status.free_len = stbuf_space(buf); + p->status.read_pointer = stbuf_rp(buf); + if (copy_to_user((void *)arg, p, sizeof(para))) + r = -EFAULT; + return r; + } + r = -EINVAL; + break; + + case AMSTREAM_IOC_SYSINFO: + if (this->type & PORT_TYPE_VIDEO) + r = vdec_set_decinfo(priv->vdec, (void *)arg); + else + r = -EINVAL; + break; + + case AMSTREAM_IOC_ACHANNEL: + if (this->type & PORT_TYPE_AUDIO) { + this->achanl = (u32) arg; + set_ch_num_info((u32) arg); + } else + r = -EINVAL; + break; + + case AMSTREAM_IOC_SAMPLERATE: + if (this->type & PORT_TYPE_AUDIO) { + this->asamprate = (u32) arg; + set_sample_rate_info((u32) arg); + } else + r = -EINVAL; + break; + + case AMSTREAM_IOC_DATAWIDTH: + if (this->type & PORT_TYPE_AUDIO) + this->adatawidth = (u32) arg; + else + r = -EINVAL; + break; + + case AMSTREAM_IOC_TSTAMP: + if ((this->type & (PORT_TYPE_AUDIO | PORT_TYPE_VIDEO)) == + ((PORT_TYPE_AUDIO | PORT_TYPE_VIDEO))) + r = -EINVAL; + else if (this->type & PORT_TYPE_FRAME) + r = vdec_set_pts(priv->vdec, arg); + else if (has_hevc_vdec() && this->type & PORT_TYPE_HEVC) + r = es_vpts_checkin(&bufs[BUF_TYPE_HEVC], arg); + else if (this->type & PORT_TYPE_VIDEO) + r = es_vpts_checkin(&bufs[BUF_TYPE_VIDEO], arg); + else if (this->type & PORT_TYPE_AUDIO) + r = es_apts_checkin(&bufs[BUF_TYPE_AUDIO], arg); + break; + + case AMSTREAM_IOC_TSTAMP_uS64: + if ((this->type & (PORT_TYPE_AUDIO | PORT_TYPE_VIDEO)) == + ((PORT_TYPE_AUDIO | PORT_TYPE_VIDEO))) + r = -EINVAL; + else { + u64 pts; + + if (copy_from_user + ((void *)&pts, (void *)arg, sizeof(u64))) + return -EFAULT; + if (this->type & PORT_TYPE_FRAME) { + /* + *todo: check upper layer for decoder handler + * life sequence or multi-tasking management + */ + if (priv->vdec) + r = vdec_set_pts64(priv->vdec, pts); + } else if (has_hevc_vdec()) { + if (this->type & PORT_TYPE_HEVC) { + r = es_vpts_checkin_us64( + &bufs[BUF_TYPE_HEVC], pts); + } else if (this->type & PORT_TYPE_VIDEO) { + r = es_vpts_checkin_us64( + &bufs[BUF_TYPE_VIDEO], pts); + } else if (this->type & PORT_TYPE_AUDIO) { + r = es_vpts_checkin_us64( + &bufs[BUF_TYPE_AUDIO], pts); + } + } else { + if (this->type & PORT_TYPE_VIDEO) { + r = es_vpts_checkin_us64( + &bufs[BUF_TYPE_VIDEO], pts); + } else if (this->type & PORT_TYPE_AUDIO) { + r = es_vpts_checkin_us64( + &bufs[BUF_TYPE_AUDIO], pts); + } + } + } + break; + + case AMSTREAM_IOC_VDECSTAT: + if ((this->type & PORT_TYPE_VIDEO) == 0) + return -EINVAL; + { + struct vdec_info vstatus; + struct am_io_param para; + struct am_io_param *p = ¶ + + if (p == NULL) + return -EINVAL; + if (vdec_status(priv->vdec, &vstatus) == -1) + return -ENODEV; + p->vstatus.width = vstatus.frame_width; + p->vstatus.height = vstatus.frame_height; + p->vstatus.fps = vstatus.frame_rate; + p->vstatus.error_count = vstatus.error_count; + p->vstatus.status = vstatus.status; + if (copy_to_user((void *)arg, p, sizeof(para))) + r = -EFAULT; + return r; + } + + case AMSTREAM_IOC_VDECINFO: + if ((this->type & PORT_TYPE_VIDEO) == 0) + return -EINVAL; + { + struct vdec_info vinfo; + struct am_io_info para; + + if (vdec_status(priv->vdec, &vinfo) == -1) + return -ENODEV; + memcpy(¶.vinfo, &vinfo, sizeof(struct vdec_info)); + if (copy_to_user((void *)arg, ¶, sizeof(para))) + r = -EFAULT; + return r; + } + + case AMSTREAM_IOC_ADECSTAT: + if ((this->type & PORT_TYPE_AUDIO) == 0) + return -EINVAL; + if (amstream_adec_status == NULL) + return -ENODEV; + else { + struct adec_status astatus; + struct am_io_param para; + struct am_io_param *p = ¶ + + if (p == NULL) + return -EINVAL; + amstream_adec_status(&astatus); + p->astatus.channels = astatus.channels; + p->astatus.sample_rate = astatus.sample_rate; + p->astatus.resolution = astatus.resolution; + p->astatus.error_count = astatus.error_count; + p->astatus.status = astatus.status; + if (copy_to_user((void *)arg, p, sizeof(para))) + r = -EFAULT; + return r; + } + case AMSTREAM_IOC_PORT_INIT: + r = amstream_port_init(priv); + break; + + case AMSTREAM_IOC_VDEC_RESET: + if ((this->type & PORT_TYPE_VIDEO) == 0) + return -EINVAL; + + if (priv->vdec == NULL) + return -ENODEV; + + r = vdec_reset(priv->vdec); + break; + + case AMSTREAM_IOC_TRICKMODE: + if ((this->type & PORT_TYPE_VIDEO) == 0) + return -EINVAL; + r = vdec_set_trickmode(priv->vdec, arg); + if (r == -1) + return -ENODEV; + break; + + case AMSTREAM_IOC_AUDIO_INFO: + if ((this->type & PORT_TYPE_VIDEO) + || (this->type & PORT_TYPE_AUDIO)) { + if (copy_from_user + (&audio_dec_info, (void __user *)arg, + sizeof(audio_dec_info))) + r = -EFAULT; + } else + r = -EINVAL; + break; + + case AMSTREAM_IOC_AUDIO_RESET: + if (this->type & PORT_TYPE_AUDIO) { + struct stream_buf_s *pabuf = &bufs[BUF_TYPE_AUDIO]; + + r = audio_port_reset(this, pabuf); + } else + r = -EINVAL; + + break; + + case AMSTREAM_IOC_SUB_RESET: + if (this->type & PORT_TYPE_SUB) { + struct stream_buf_s *psbuf = &bufs[BUF_TYPE_SUBTITLE]; + + r = sub_port_reset(this, psbuf); + } else + r = -EINVAL; + break; + + case AMSTREAM_IOC_SUB_LENGTH: + if ((this->type & PORT_TYPE_SUB) || + (this->type & PORT_TYPE_SUB_RD)) { + u32 sub_wp, sub_rp; + struct stream_buf_s *psbuf = &bufs[BUF_TYPE_SUBTITLE]; + int val; + + sub_wp = stbuf_sub_wp_get(); + sub_rp = stbuf_sub_rp_get(); + + if (sub_wp == sub_rp) + val = 0; + else if (sub_wp > sub_rp) + val = sub_wp - sub_rp; + else + val = psbuf->buf_size - (sub_rp - sub_wp); + put_user(val, (int __user *)arg); + } else + r = -EINVAL; + break; + + case AMSTREAM_IOC_UD_LENGTH: + if (this->type & PORT_TYPE_USERDATA) { + /* *((u32 *)arg) = userdata_length; */ + put_user(userdata_length, (unsigned long __user *)arg); + userdata_length = 0; + } else + r = -EINVAL; + break; + + case AMSTREAM_IOC_UD_POC: + if (this->type & PORT_TYPE_USERDATA) { + /* *((u32 *)arg) = userdata_length; */ + int ri; +#ifdef DEBUG_USER_DATA + int wi; +#endif + int bDataAvail = 0; + + mutex_lock(&userdata_mutex); + if (userdata_poc_wi != userdata_poc_ri) { + bDataAvail = 1; + ri = userdata_poc_ri; +#ifdef DEBUG_USER_DATA + wi = userdata_poc_wi; +#endif + userdata_poc_ri++; + if (userdata_poc_ri >= USERDATA_FIFO_NUM) + userdata_poc_ri = 0; + } + mutex_unlock(&userdata_mutex); + if (bDataAvail) { + int res; + struct userdata_poc_info_t userdata_poc = + userdata_poc_info[ri]; +#ifdef DEBUG_USER_DATA + pr_info("read poc: ri=%d, wi=%d, poc=%d, last_wi=%d\n", + ri, wi, + userdata_poc.poc_number, + last_read_wi); +#endif + res = + copy_to_user((unsigned long __user *)arg, + &userdata_poc, + sizeof(struct userdata_poc_info_t)); + if (res < 0) + r = -EFAULT; + } else { + r = -EFAULT; + } + } else { + r = -EINVAL; + } + break; + + case AMSTREAM_IOC_UD_FLUSH_USERDATA: + if (this->type & PORT_TYPE_USERDATA) { + reset_userdata_fifo(0); + pr_info("reset_userdata_fifo\n"); + } else + r = -EINVAL; + break; + + case AMSTREAM_IOC_SET_DEC_RESET: + tsync_set_dec_reset(); + break; + + case AMSTREAM_IOC_TS_SKIPBYTE: + if ((int)arg >= 0) + tsdemux_set_skipbyte(arg); + else + r = -EINVAL; + break; + + case AMSTREAM_IOC_SUB_TYPE: + sub_type = (int)arg; + break; + + case AMSTREAM_IOC_APTS_LOOKUP: + if (this->type & PORT_TYPE_AUDIO) { + u32 pts = 0, offset; + + get_user(offset, (unsigned long __user *)arg); + pts_lookup_offset(PTS_TYPE_AUDIO, offset, &pts, 300); + put_user(pts, (int __user *)arg); + } + return 0; + case GET_FIRST_APTS_FLAG: + if (this->type & PORT_TYPE_AUDIO) { + put_user(first_pts_checkin_complete(PTS_TYPE_AUDIO), + (int __user *)arg); + } + break; + + case AMSTREAM_IOC_APTS: + put_user(timestamp_apts_get(), (int __user *)arg); + break; + + case AMSTREAM_IOC_VPTS: + put_user(timestamp_vpts_get(), (int __user *)arg); + break; + + case AMSTREAM_IOC_PCRSCR: + put_user(timestamp_pcrscr_get(), (int __user *)arg); + break; + + case AMSTREAM_IOC_SET_PCRSCR: + timestamp_pcrscr_set(arg); + break; + case AMSTREAM_IOC_GET_LAST_CHECKIN_APTS: + put_user(get_last_checkin_pts(PTS_TYPE_AUDIO), (int *)arg); + break; + case AMSTREAM_IOC_GET_LAST_CHECKIN_VPTS: + put_user(get_last_checkin_pts(PTS_TYPE_VIDEO), (int *)arg); + break; + case AMSTREAM_IOC_GET_LAST_CHECKOUT_APTS: + put_user(get_last_checkout_pts(PTS_TYPE_AUDIO), (int *)arg); + break; + case AMSTREAM_IOC_GET_LAST_CHECKOUT_VPTS: + put_user(get_last_checkout_pts(PTS_TYPE_VIDEO), (int *)arg); + break; + case AMSTREAM_IOC_SUB_NUM: + put_user(psparser_get_sub_found_num(), (int *)arg); + break; + + case AMSTREAM_IOC_SUB_INFO: + if (arg > 0) { + struct subtitle_info msub_info[MAX_SUB_NUM]; + struct subtitle_info *psub_info[MAX_SUB_NUM]; + int i; + + for (i = 0; i < MAX_SUB_NUM; i++) + psub_info[i] = &msub_info[i]; + + r = psparser_get_sub_info(psub_info); + + if (r == 0) { + if (copy_to_user((void __user *)arg, msub_info, + sizeof(struct subtitle_info) * MAX_SUB_NUM)) + r = -EFAULT; + } + } + break; + case AMSTREAM_IOC_SET_DEMUX: + tsdemux_set_demux((int)arg); + break; + case AMSTREAM_IOC_SET_VIDEO_DELAY_LIMIT_MS: + if (has_hevc_vdec()) + bufs[BUF_TYPE_HEVC].max_buffer_delay_ms = (int)arg; + bufs[BUF_TYPE_VIDEO].max_buffer_delay_ms = (int)arg; + break; + case AMSTREAM_IOC_SET_AUDIO_DELAY_LIMIT_MS: + bufs[BUF_TYPE_AUDIO].max_buffer_delay_ms = (int)arg; + break; + case AMSTREAM_IOC_GET_VIDEO_DELAY_LIMIT_MS: + put_user(bufs[BUF_TYPE_VIDEO].max_buffer_delay_ms, (int *)arg); + break; + case AMSTREAM_IOC_GET_AUDIO_DELAY_LIMIT_MS: + put_user(bufs[BUF_TYPE_AUDIO].max_buffer_delay_ms, (int *)arg); + break; + case AMSTREAM_IOC_GET_VIDEO_CUR_DELAY_MS: { + int delay; + + delay = calculation_stream_delayed_ms( + PTS_TYPE_VIDEO, NULL, NULL); + if (delay >= 0) + put_user(delay, (int *)arg); + else + put_user(0, (int *)arg); + } + break; + + case AMSTREAM_IOC_GET_AUDIO_CUR_DELAY_MS: { + int delay; + + delay = calculation_stream_delayed_ms(PTS_TYPE_AUDIO, NULL, + NULL); + if (delay >= 0) + put_user(delay, (int *)arg); + else + put_user(0, (int *)arg); + } + break; + case AMSTREAM_IOC_GET_AUDIO_AVG_BITRATE_BPS: { + int delay; + u32 avgbps; + + delay = calculation_stream_delayed_ms(PTS_TYPE_AUDIO, NULL, + &avgbps); + if (delay >= 0) + put_user(avgbps, (int *)arg); + else + put_user(0, (int *)arg); + break; + } + case AMSTREAM_IOC_GET_VIDEO_AVG_BITRATE_BPS: { + int delay; + u32 avgbps; + + delay = calculation_stream_delayed_ms(PTS_TYPE_VIDEO, NULL, + &avgbps); + if (delay >= 0) + put_user(avgbps, (int *)arg); + else + put_user(0, (int *)arg); + break; + } + case AMSTREAM_IOC_SET_DRMMODE: + if ((u32) arg == 1) { + pr_err("set drmmode\n"); + this->flag |= PORT_FLAG_DRM; + if ((this->type & PORT_TYPE_VIDEO) && + (priv->vdec)) + priv->vdec->port_flag |= PORT_FLAG_DRM; + } else { + this->flag &= (~PORT_FLAG_DRM); + pr_err("no drmmode\n"); + } + break; + case AMSTREAM_IOC_SET_APTS: { + unsigned long pts; + + if (get_user(pts, (unsigned long __user *)arg)) { + pr_err + ("Get audio pts from user space fault!\n"); + return -EFAULT; + } + if (tsync_get_mode() == TSYNC_MODE_PCRMASTER) + tsync_pcr_set_apts(pts); + else + tsync_set_apts(pts); + break; + } + default: + r = -ENOIOCTLCMD; + break; + } + + return r; +} + +static long amstream_do_ioctl(struct port_priv_s *priv, + unsigned int cmd, ulong arg) +{ + long r = 0; + + switch (cmd) { + case AMSTREAM_IOC_GET_VERSION: + case AMSTREAM_IOC_GET: + case AMSTREAM_IOC_SET: + case AMSTREAM_IOC_GET_EX: + case AMSTREAM_IOC_SET_EX: + case AMSTREAM_IOC_GET_PTR: + case AMSTREAM_IOC_SET_PTR: + case AMSTREAM_IOC_SYSINFO: + r = amstream_do_ioctl_new(priv, cmd, arg); + break; + default: + r = amstream_do_ioctl_old(priv, cmd, arg); + break; + } + if (r != 0) + pr_err("amstream_do_ioctl error :%lx, %x\n", r, cmd); + + return r; +} +static long amstream_ioctl(struct file *file, unsigned int cmd, ulong arg) +{ + struct port_priv_s *priv = (struct port_priv_s *)file->private_data; + struct stream_port_s *this = priv->port; + + if (!this) + return -ENODEV; + + return amstream_do_ioctl(priv, cmd, arg); +} + +#ifdef CONFIG_COMPAT +struct dec_sysinfo32 { + + u32 format; + + u32 width; + + u32 height; + + u32 rate; + + u32 extra; + + u32 status; + + u32 ratio; + + compat_uptr_t param; + + u64 ratio64; +}; + +struct am_ioctl_parm_ptr32 { + union { + compat_uptr_t pdata_audio_info; + compat_uptr_t pdata_sub_info; + compat_uptr_t pointer; + char data[8]; + }; + u32 cmd; + u32 len; +}; + +static long amstream_ioc_setget_ptr(struct port_priv_s *priv, + unsigned int cmd, struct am_ioctl_parm_ptr32 __user *arg) +{ + struct am_ioctl_parm_ptr __user *data; + struct am_ioctl_parm_ptr32 __user *data32 = arg; + int ret; + + data = compat_alloc_user_space(sizeof(*data)); + if (!access_ok(VERIFY_WRITE, data, sizeof(*data))) + return -EFAULT; + + if (put_user(data32->cmd, &data->cmd) || + put_user(compat_ptr(data32->pointer), &data->pointer) || + put_user(data32->len, &data->len)) + return -EFAULT; + + + ret = amstream_do_ioctl(priv, cmd, (unsigned long)data); + if (ret < 0) + return ret; + return 0; + +} + +static long amstream_set_sysinfo(struct port_priv_s *priv, + struct dec_sysinfo32 __user *arg) +{ + struct dec_sysinfo __user *data; + struct dec_sysinfo32 __user *data32 = arg; + int ret; + + data = compat_alloc_user_space(sizeof(*data)); + if (!access_ok(VERIFY_WRITE, data, sizeof(*data))) + return -EFAULT; + if (copy_in_user(data, data32, 7 * sizeof(u32))) + return -EFAULT; + if (put_user(compat_ptr(data32->param), &data->param)) + return -EFAULT; + if (copy_in_user(&data->ratio64, &data32->ratio64, + sizeof(data->ratio64))) + return -EFAULT; + + ret = amstream_do_ioctl(priv, AMSTREAM_IOC_SYSINFO, + (unsigned long)data); + if (ret < 0) + return ret; + + if (copy_in_user(&arg->format, &data->format, 7 * sizeof(u32)) || + copy_in_user(&arg->ratio64, &data->ratio64, + sizeof(arg->ratio64))) + return -EFAULT; + + return 0; +} +static long amstream_compat_ioctl(struct file *file, + unsigned int cmd, ulong arg) +{ + s32 r = 0; + struct port_priv_s *priv = (struct port_priv_s *)file->private_data; + + switch (cmd) { + case AMSTREAM_IOC_GET_VERSION: + case AMSTREAM_IOC_GET: + case AMSTREAM_IOC_SET: + case AMSTREAM_IOC_GET_EX: + case AMSTREAM_IOC_SET_EX: + return amstream_do_ioctl(priv, cmd, (ulong)compat_ptr(arg)); + case AMSTREAM_IOC_GET_PTR: + case AMSTREAM_IOC_SET_PTR: + return amstream_ioc_setget_ptr(priv, cmd, compat_ptr(arg)); + case AMSTREAM_IOC_SYSINFO: + return amstream_set_sysinfo(priv, compat_ptr(arg)); + default: + return amstream_do_ioctl(priv, cmd, (ulong)compat_ptr(arg)); + } + + return r; +} +#endif + +static ssize_t ports_show(struct class *class, struct class_attribute *attr, + char *buf) +{ + int i; + char *pbuf = buf; + struct stream_port_s *p = NULL; + + for (i = 0; i < amstream_port_num; i++) { + p = &ports[i]; + /*name */ + pbuf += sprintf(pbuf, "%s\t:\n", p->name); + /*type */ + pbuf += sprintf(pbuf, "\ttype:%d( ", p->type); + if (p->type & PORT_TYPE_VIDEO) + pbuf += sprintf(pbuf, "%s ", "Video"); + if (p->type & PORT_TYPE_AUDIO) + pbuf += sprintf(pbuf, "%s ", "Audio"); + if (p->type & PORT_TYPE_MPTS) + pbuf += sprintf(pbuf, "%s ", "TS"); + if (p->type & PORT_TYPE_MPPS) + pbuf += sprintf(pbuf, "%s ", "PS"); + if (p->type & PORT_TYPE_ES) + pbuf += sprintf(pbuf, "%s ", "ES"); + if (p->type & PORT_TYPE_RM) + pbuf += sprintf(pbuf, "%s ", "RM"); + if (p->type & PORT_TYPE_SUB) + pbuf += sprintf(pbuf, "%s ", "Subtitle"); + if (p->type & PORT_TYPE_SUB_RD) + pbuf += sprintf(pbuf, "%s ", "Subtitle_Read"); + if (p->type & PORT_TYPE_USERDATA) + pbuf += sprintf(pbuf, "%s ", "userdata"); + pbuf += sprintf(pbuf, ")\n"); + /*flag */ + pbuf += sprintf(pbuf, "\tflag:%d( ", p->flag); + if (p->flag & PORT_FLAG_IN_USE) + pbuf += sprintf(pbuf, "%s ", "Used"); + else + pbuf += sprintf(pbuf, "%s ", "Unused"); + if ((p->type & PORT_TYPE_VIDEO) == 0) { + if (p->flag & PORT_FLAG_INITED) + pbuf += sprintf(pbuf, "%s ", "inited"); + else + pbuf += sprintf(pbuf, "%s ", "uninited"); + } + pbuf += sprintf(pbuf, ")\n"); + /*others */ + pbuf += sprintf(pbuf, "\tVformat:%d\n", + (p->flag & PORT_FLAG_VFORMAT) ? p->vformat : -1); + pbuf += sprintf(pbuf, "\tAformat:%d\n", + (p->flag & PORT_FLAG_AFORMAT) ? p->aformat : -1); + pbuf += sprintf(pbuf, "\tVid:%d\n", + (p->flag & PORT_FLAG_VID) ? p->vid : -1); + pbuf += sprintf(pbuf, "\tAid:%d\n", + (p->flag & PORT_FLAG_AID) ? p->aid : -1); + pbuf += sprintf(pbuf, "\tSid:%d\n", + (p->flag & PORT_FLAG_SID) ? p->sid : -1); + pbuf += sprintf(pbuf, "\tPCRid:%d\n", + (p->pcr_inited == 1) ? p->pcrid : -1); + pbuf += sprintf(pbuf, "\tachannel:%d\n", p->achanl); + pbuf += sprintf(pbuf, "\tasamprate:%d\n", p->asamprate); + pbuf += sprintf(pbuf, "\tadatawidth:%d\n\n", p->adatawidth); + } + return pbuf - buf; +} + +static ssize_t bufs_show(struct class *class, struct class_attribute *attr, + char *buf) +{ + int i; + char *pbuf = buf; + struct stream_buf_s *p = NULL; + char buf_type[][12] = { "Video", "Audio", "Subtitle", + "UserData", "HEVC" }; + + for (i = 0; i < amstream_buf_num; i++) { + p = &bufs[i]; + /*type */ + pbuf += sprintf(pbuf, "%s buffer:", buf_type[p->type]); + /*flag */ + pbuf += sprintf(pbuf, "\tflag:%d( ", p->flag); + if (p->flag & BUF_FLAG_ALLOC) + pbuf += sprintf(pbuf, "%s ", "Alloc"); + else + pbuf += sprintf(pbuf, "%s ", "Unalloc"); + if (p->flag & BUF_FLAG_IN_USE) + pbuf += sprintf(pbuf, "%s ", "Used"); + else + pbuf += sprintf(pbuf, "%s ", "Noused"); + if (p->flag & BUF_FLAG_PARSER) + pbuf += sprintf(pbuf, "%s ", "Parser"); + else + pbuf += sprintf(pbuf, "%s ", "noParser"); + if (p->flag & BUF_FLAG_FIRST_TSTAMP) + pbuf += sprintf(pbuf, "%s ", "firststamp"); + else + pbuf += sprintf(pbuf, "%s ", "nofirststamp"); + pbuf += sprintf(pbuf, ")\n"); + /*buf stats */ + + pbuf += sprintf(pbuf, "\tbuf addr:%p\n", (void *)p->buf_start); + + if (p->type != BUF_TYPE_SUBTITLE) { + pbuf += sprintf(pbuf, "\tbuf size:%#x\n", p->buf_size); + pbuf += sprintf(pbuf, + "\tbuf canusesize:%#x\n", + p->canusebuf_size); + pbuf += sprintf(pbuf, + "\tbuf regbase:%#lx\n", p->reg_base); + + if (p->reg_base && p->flag & BUF_FLAG_IN_USE) { + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M6) { + /* TODO: mod gate */ + /* switch_mod_gate_by_name("vdec", 1);*/ + amports_switch_gate("vdec", 1); + } + pbuf += sprintf(pbuf, "\tbuf level:%#x\n", + stbuf_level(p)); + pbuf += sprintf(pbuf, "\tbuf space:%#x\n", + stbuf_space(p)); + pbuf += sprintf(pbuf, + "\tbuf read pointer:%#x\n", + stbuf_rp(p)); + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_M6) { + /* TODO: mod gate */ + /* switch_mod_gate_by_name("vdec", 0);*/ + amports_switch_gate("vdec", 0); + } + } else + pbuf += sprintf(pbuf, "\tbuf no used.\n"); + + if (p->type == BUF_TYPE_USERDATA) { + pbuf += sprintf(pbuf, + "\tbuf write pointer:%#x\n", + p->buf_wp); + pbuf += sprintf(pbuf, + "\tbuf read pointer:%#x\n", + p->buf_rp); + } + } else { + u32 sub_wp, sub_rp, data_size; + + sub_wp = stbuf_sub_wp_get(); + sub_rp = stbuf_sub_rp_get(); + if (sub_wp >= sub_rp) + data_size = sub_wp - sub_rp; + else + data_size = p->buf_size - sub_rp + sub_wp; + pbuf += sprintf(pbuf, "\tbuf size:%#x\n", p->buf_size); + pbuf += + sprintf(pbuf, "\tbuf canusesize:%#x\n", + p->canusebuf_size); + pbuf += + sprintf(pbuf, "\tbuf start:%#x\n", + stbuf_sub_start_get()); + pbuf += sprintf(pbuf, + "\tbuf write pointer:%#x\n", sub_wp); + pbuf += sprintf(pbuf, + "\tbuf read pointer:%#x\n", sub_rp); + pbuf += sprintf(pbuf, "\tbuf level:%#x\n", data_size); + } + + pbuf += sprintf(pbuf, "\tbuf first_stamp:%#x\n", + p->first_tstamp); + pbuf += sprintf(pbuf, "\tbuf wcnt:%#x\n\n", p->wcnt); + pbuf += sprintf(pbuf, "\tbuf max_buffer_delay_ms:%dms\n", + p->max_buffer_delay_ms); + + if (p->reg_base && p->flag & BUF_FLAG_IN_USE) { + int calc_delayms = 0; + u32 bitrate = 0, avg_bitrate = 0; + + calc_delayms = calculation_stream_delayed_ms( + (p->type == BUF_TYPE_AUDIO) ? PTS_TYPE_AUDIO : + PTS_TYPE_VIDEO, + &bitrate, + &avg_bitrate); + + if (calc_delayms >= 0) { + pbuf += sprintf(pbuf, + "\tbuf current delay:%dms\n", + calc_delayms); + pbuf += sprintf(pbuf, + "\tbuf bitrate latest:%dbps,avg:%dbps\n", + bitrate, avg_bitrate); + pbuf += sprintf(pbuf, + "\tbuf time after last pts:%d ms\n", + calculation_stream_ext_delayed_ms + ((p->type == BUF_TYPE_AUDIO) ? PTS_TYPE_AUDIO : + PTS_TYPE_VIDEO)); + + pbuf += sprintf(pbuf, + "\tbuf time after last write data :%d ms\n", + (int)(jiffies_64 - + p->last_write_jiffies64) * 1000 / HZ); + } + } + if (p->write_thread) { + pbuf += sprintf(pbuf, + "\twrite thread:%d/%d,fifo %d:%d,passed:%d\n", + threadrw_buffer_level(p), + threadrw_buffer_size(p), + threadrw_datafifo_len(p), + threadrw_freefifo_len(p), + threadrw_passed_len(p) + ); + } + } + + return pbuf - buf; +} + +static ssize_t videobufused_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + char *pbuf = buf; + struct stream_buf_s *p = NULL; + struct stream_buf_s *p_hevc = NULL; + + p = &bufs[0]; + if (has_hevc_vdec()) + p_hevc = &bufs[BUF_TYPE_HEVC]; + + if (p->flag & BUF_FLAG_IN_USE) + pbuf += sprintf(pbuf, "%d ", 1); + else if (has_hevc_vdec() && (p_hevc->flag & BUF_FLAG_IN_USE)) + pbuf += sprintf(pbuf, "%d ", 1); + else + pbuf += sprintf(pbuf, "%d ", 0); + return 1; +} + +static ssize_t vcodec_profile_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + return vcodec_profile_read(buf); +} + +static int reset_canuse_buferlevel(int levelx10000) +{ + int i; + struct stream_buf_s *p = NULL; + + if (levelx10000 >= 0 && levelx10000 <= 10000) + use_bufferlevelx10000 = levelx10000; + else + use_bufferlevelx10000 = 10000; + for (i = 0; i < amstream_buf_num; i++) { + p = &bufs[i]; + p->canusebuf_size = ((p->buf_size / 1024) * + use_bufferlevelx10000 / 10000) * 1024; + p->canusebuf_size += 1023; + p->canusebuf_size &= ~1023; + if (p->canusebuf_size > p->buf_size) + p->canusebuf_size = p->buf_size; + } + return 0; +} + +static ssize_t show_canuse_buferlevel(struct class *class, + struct class_attribute *attr, char *buf) +{ + ssize_t size = sprintf(buf, + "use_bufferlevel=%d/10000[=(set range[ 0~10000])=\n", + use_bufferlevelx10000); + return size; +} + +static ssize_t store_canuse_buferlevel(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size) +{ + unsigned int val; + ssize_t ret; + + /*ret = sscanf(buf, "%d", &val);*/ + ret = kstrtoint(buf, 0, &val); + + if (ret != 0) + return -EINVAL; + val = val; + reset_canuse_buferlevel(val); + return size; +} + +static ssize_t store_maxdelay(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size) +{ + unsigned int val; + ssize_t ret; + int i; + + /*ret = sscanf(buf, "%d", &val);*/ + ret = kstrtoint(buf, 0, &val); + if (ret != 0) + return -EINVAL; + for (i = 0; i < amstream_buf_num; i++) + bufs[i].max_buffer_delay_ms = val; + return size; +} + +static ssize_t show_maxdelay(struct class *class, + struct class_attribute *attr, + char *buf) +{ + ssize_t size = 0; + + size += sprintf(buf, "%dms video max buffered data delay ms\n", + bufs[0].max_buffer_delay_ms); + size += sprintf(buf, "%dms audio max buffered data delay ms\n", + bufs[1].max_buffer_delay_ms); + return size; +} + +static struct class_attribute amstream_class_attrs[] = { + __ATTR_RO(ports), + __ATTR_RO(bufs), + __ATTR_RO(vcodec_profile), + __ATTR_RO(videobufused), + __ATTR(canuse_buferlevel, S_IRUGO | S_IWUSR | S_IWGRP, + show_canuse_buferlevel, store_canuse_buferlevel), + __ATTR(max_buffer_delay_ms, S_IRUGO | S_IWUSR | S_IWGRP, show_maxdelay, + store_maxdelay), + __ATTR_NULL +}; + +static struct class amstream_class = { + .name = "amstream", + .class_attrs = amstream_class_attrs, +}; + +int amstream_request_firmware_from_sys(const char *file_name, + char *buf, int size) +{ + const struct firmware *firmware; + int err = 0; + struct device *micro_dev; + + pr_info("try load %s ...", file_name); + micro_dev = device_create(&amstream_class, + NULL, MKDEV(AMSTREAM_MAJOR, 100), + NULL, "videodec"); + if (micro_dev == NULL) { + pr_err("device_create failed =%d\n", err); + return -1; + } + err = request_firmware(&firmware, file_name, micro_dev); + if (err < 0) { + pr_err("can't load the %s,err=%d\n", file_name, err); + goto error1; + } + if (firmware->size > size) { + pr_err("not enough memory size for audiodsp code\n"); + err = -ENOMEM; + goto release; + } + + memcpy(buf, (char *)firmware->data, firmware->size); + /*mb(); don't need it*/ + pr_err("load mcode size=%zd\n mcode name %s\n", firmware->size, + file_name); + err = firmware->size; +release: + release_firmware(firmware); +error1: + device_destroy(&amstream_class, MKDEV(AMSTREAM_MAJOR, 100)); + return err; +} + +int videobufused_show_fun(const char *trigger, int id, char *sbuf, int size) +{ + int ret = -1; + void *buf, *getbuf = NULL; + if (size < PAGE_SIZE) { + getbuf = (void *)__get_free_page(GFP_KERNEL); + if (!getbuf) + return -ENOMEM; + buf = getbuf; + } else { + buf = sbuf; + } + + switch (id) { + case 0: + ret = videobufused_show(NULL, NULL , buf); + break; + default: + ret = -1; + } + if (ret > 0 && getbuf != NULL) { + ret = min_t(int, ret, size); + strncpy(sbuf, buf, ret); + } + if (getbuf != NULL) + free_page((unsigned long)getbuf); + return ret; +} + +static struct mconfig amports_configs[] = { + MC_PI32("def_4k_vstreambuf_sizeM", &def_4k_vstreambuf_sizeM), + MC_PI32("def_vstreambuf_sizeM", &def_vstreambuf_sizeM), + MC_PI32("slow_input", &slow_input), + MC_FUN_ID("videobufused", videobufused_show_fun, NULL, 0), +}; + + + +/*static struct resource memobj;*/ +static int amstream_probe(struct platform_device *pdev) +{ + int i; + int r; + struct stream_port_s *st; + + pr_err("Amlogic A/V streaming port init\n"); + + amstream_port_num = MAX_AMSTREAM_PORT_NUM; + amstream_buf_num = BUF_MAX_NUM; +/* + * r = of_reserved_mem_device_init(&pdev->dev); + * if (r == 0) + * pr_info("of probe done"); + * else { + * r = -ENOMEM; + * return r; + * } + */ + r = class_register(&amstream_class); + if (r) { + pr_err("amstream class create fail.\n"); + return r; + } + + r = astream_dev_register(); + if (r) + return r; + + r = register_chrdev(AMSTREAM_MAJOR, "amstream", &amstream_fops); + if (r < 0) { + pr_err("Can't allocate major for amstreaming device\n"); + + goto error2; + } + + amstream_dev_class = class_create(THIS_MODULE, DEVICE_NAME); + + for (st = &ports[0], i = 0; i < amstream_port_num; i++, st++) { + st->class_dev = device_create(amstream_dev_class, NULL, + MKDEV(AMSTREAM_MAJOR, i), NULL, + ports[i].name); + } + + amstream_adec_status = NULL; + if (tsdemux_class_register() != 0) { + r = (-EIO); + goto error3; + } + tsdemux_tsync_func_init(); + init_waitqueue_head(&amstream_sub_wait); + init_waitqueue_head(&amstream_userdata_wait); + reset_canuse_buferlevel(10000); + amstream_pdev = pdev; + amports_clock_gate_init(&amstream_pdev->dev); + + /*prealloc fetch buf to avoid no continue buffer later...*/ + stbuf_fetch_init(); + REG_PATH_CONFIGS("media.amports", amports_configs); + + /* poweroff the decode core because dos can not be reset when reboot */ + if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A) + vdec_power_reset(); + + return 0; + + /* + * error4: + * tsdemux_class_unregister(); + */ +error3: + for (st = &ports[0], i = 0; i < amstream_port_num; i++, st++) + device_destroy(amstream_dev_class, MKDEV(AMSTREAM_MAJOR, i)); + class_destroy(amstream_dev_class); +error2: + unregister_chrdev(AMSTREAM_MAJOR, "amstream"); + /* error1: */ + astream_dev_unregister(); + return r; +} + +static int amstream_remove(struct platform_device *pdev) +{ + int i; + struct stream_port_s *st; + + if (bufs[BUF_TYPE_VIDEO].flag & BUF_FLAG_ALLOC) + stbuf_change_size(&bufs[BUF_TYPE_VIDEO], 0, false); + if (bufs[BUF_TYPE_AUDIO].flag & BUF_FLAG_ALLOC) + stbuf_change_size(&bufs[BUF_TYPE_AUDIO], 0, false); + stbuf_fetch_release(); + tsdemux_class_unregister(); + for (st = &ports[0], i = 0; i < amstream_port_num; i++, st++) + device_destroy(amstream_dev_class, MKDEV(AMSTREAM_MAJOR, i)); + + class_destroy(amstream_dev_class); + + unregister_chrdev(AMSTREAM_MAJOR, "amstream"); + + class_unregister(&amstream_class); + + astream_dev_unregister(); + + amstream_adec_status = NULL; + + pr_err("Amlogic A/V streaming port release\n"); + + return 0; +} + +void set_adec_func(int (*adec_func)(struct adec_status *)) +{ + amstream_adec_status = adec_func; +} + +void wakeup_sub_poll(void) +{ + atomic_inc(&subdata_ready); + wake_up_interruptible(&amstream_sub_wait); +} + +int get_sub_type(void) +{ + return sub_type; +} + +u32 get_audio_reset(void) +{ + return amstream_audio_reset; +} + +/*get pes buffers */ + +struct stream_buf_s *get_stream_buffer(int id) +{ + if (id >= BUF_MAX_NUM) + return 0; + return &bufs[id]; +} +EXPORT_SYMBOL(get_stream_buffer); +static const struct of_device_id amlogic_mesonstream_dt_match[] = { + { + .compatible = "amlogic, codec, streambuf", + }, + {}, +}; + +static struct platform_driver amstream_driver = { + .probe = amstream_probe, + .remove = amstream_remove, + .driver = { + .owner = THIS_MODULE, + .name = "mesonstream", + .of_match_table = amlogic_mesonstream_dt_match, + } +}; + +static int __init amstream_module_init(void) +{ + if (platform_driver_register(&amstream_driver)) { + pr_err("failed to register amstream module\n"); + return -ENODEV; + } + return 0; +} + +static void __exit amstream_module_exit(void) +{ + platform_driver_unregister(&amstream_driver); +} + +module_init(amstream_module_init); +module_exit(amstream_module_exit); + +module_param(def_4k_vstreambuf_sizeM, uint, 0664); +MODULE_PARM_DESC(def_4k_vstreambuf_sizeM, + "\nDefault video Stream buf size for 4K MByptes\n"); + +module_param(def_vstreambuf_sizeM, uint, 0664); +MODULE_PARM_DESC(def_vstreambuf_sizeM, + "\nDefault video Stream buf size for < 1080p MByptes\n"); + +module_param(slow_input, uint, 0664); +MODULE_PARM_DESC(slow_input, "\n amstream slow_input\n"); + + +MODULE_DESCRIPTION("AMLOGIC streaming port driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Tim Yao "); diff --git a/drivers/amlogic/media_modules/stream_input/amports/amstream_profile.c b/drivers/amlogic/media_modules/stream_input/amports/amstream_profile.c new file mode 100644 index 000000000000..a2bc5564209f --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/amports/amstream_profile.c @@ -0,0 +1,54 @@ +/* + * drivers/amlogic/media/stream_input/amports/amstream_profile.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include "amports_priv.h" + +static const struct codec_profile_t *vcodec_profile[SUPPORT_VDEC_NUM] = { 0 }; + +static int vcodec_profile_idx; + +ssize_t vcodec_profile_read(char *buf) +{ + char *pbuf = buf; + int i = 0; + + for (i = 0; i < vcodec_profile_idx; i++) { + pbuf += sprintf(pbuf, "%s:%s;\n", vcodec_profile[i]->name, + vcodec_profile[i]->profile); + } + + return pbuf - buf; +} + +int vcodec_profile_register(const struct codec_profile_t *vdec_profile) +{ + if (vcodec_profile_idx < SUPPORT_VDEC_NUM) { + vcodec_profile[vcodec_profile_idx] = vdec_profile; + vcodec_profile_idx++; + pr_debug("regist %s codec profile\n", vdec_profile->name); + + } + + return 0; +} +EXPORT_SYMBOL(vcodec_profile_register); + diff --git a/drivers/amlogic/media_modules/stream_input/parser/esparser.c b/drivers/amlogic/media_modules/stream_input/parser/esparser.c new file mode 100644 index 000000000000..f04b9decb969 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/esparser.c @@ -0,0 +1,939 @@ +/* + * drivers/amlogic/media/stream_input/parser/esparser.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* #include */ +#include + +#include "../../frame_provider/decoder/utils/vdec.h" +#include +#include "streambuf_reg.h" +#include "streambuf.h" +#include "esparser.h" +#include "../amports/amports_priv.h" +#include "thread_rw.h" + +#include + + + +#define SAVE_SCR 0 + +#define ES_START_CODE_PATTERN 0x00000100 +#define ES_START_CODE_MASK 0xffffff00 +#define SEARCH_PATTERN_LEN 512 +#define ES_PARSER_POP READ_PARSER_REG(PFIFO_DATA) + +#define PARSER_WRITE (ES_WRITE | ES_PARSER_START) +#define PARSER_VIDEO (ES_TYPE_VIDEO) +#define PARSER_AUDIO (ES_TYPE_AUDIO) +#define PARSER_SUBPIC (ES_TYPE_SUBTITLE) +#define PARSER_PASSTHROUGH (ES_PASSTHROUGH | ES_PARSER_START) +#define PARSER_AUTOSEARCH (ES_SEARCH | ES_PARSER_START) +#define PARSER_DISCARD (ES_DISCARD | ES_PARSER_START) +#define PARSER_BUSY (ES_PARSER_BUSY) + +static unsigned char *search_pattern; +static dma_addr_t search_pattern_map; +static u32 audio_real_wp; +static u32 audio_buf_start; +static u32 audio_buf_end; + +static const char esparser_id[] = "esparser-id"; + +static DECLARE_WAIT_QUEUE_HEAD(wq); + + +static u32 search_done; +static u32 video_data_parsed; +static u32 audio_data_parsed; +static atomic_t esparser_use_count = ATOMIC_INIT(0); +static DEFINE_MUTEX(esparser_mutex); + +static inline u32 get_buf_wp(u32 type) +{ + if (type == BUF_TYPE_AUDIO) + return audio_real_wp; + else + return 0; +} +static inline u32 get_buf_start(u32 type) +{ + if (type == BUF_TYPE_AUDIO) + return audio_buf_start; + else + return 0; +} +static inline u32 get_buf_end(u32 type) +{ + if (type == BUF_TYPE_AUDIO) + return audio_buf_end; + else + return 0; +} +static void set_buf_wp(u32 type, u32 wp) +{ + if (type == BUF_TYPE_AUDIO) { + audio_real_wp = wp; + WRITE_AIU_REG(AIU_MEM_AIFIFO_MAN_WP, wp/* & 0xffffff00*/); + } + return; +} + +static irqreturn_t esparser_isr(int irq, void *dev_id) +{ + u32 int_status = READ_PARSER_REG(PARSER_INT_STATUS); + + WRITE_PARSER_REG(PARSER_INT_STATUS, int_status); + + if (int_status & PARSER_INTSTAT_SC_FOUND) { + WRITE_PARSER_REG(PFIFO_RD_PTR, 0); + WRITE_PARSER_REG(PFIFO_WR_PTR, 0); + search_done = 1; + wake_up_interruptible(&wq); + } + return IRQ_HANDLED; +} + +static inline u32 buf_wp(u32 type) +{ + u32 wp; + + if ((READ_PARSER_REG(PARSER_ES_CONTROL) & ES_VID_MAN_RD_PTR) == 0) { + wp = +#if 1/* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ + (type == BUF_TYPE_HEVC) ? READ_VREG(HEVC_STREAM_WR_PTR) : +#endif + (type == BUF_TYPE_VIDEO) ? READ_VREG(VLD_MEM_VIFIFO_WP) : + (type == BUF_TYPE_AUDIO) ? + READ_AIU_REG(AIU_MEM_AIFIFO_MAN_WP) : + READ_PARSER_REG(PARSER_SUB_START_PTR); + } else { + wp = +#if 1/* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ + (type == BUF_TYPE_HEVC) ? READ_PARSER_REG(PARSER_VIDEO_WP) : +#endif + (type == BUF_TYPE_VIDEO) ? READ_PARSER_REG(PARSER_VIDEO_WP) : + (type == BUF_TYPE_AUDIO) ? + READ_AIU_REG(AIU_MEM_AIFIFO_MAN_WP) : + READ_PARSER_REG(PARSER_SUB_START_PTR); + } + + return wp; +} + +static ssize_t _esparser_write(const char __user *buf, + size_t count, u32 type, int isphybuf) +{ + size_t r = count; + const char __user *p = buf; + + u32 len = 0; + u32 parser_type; + int ret; + u32 wp; + dma_addr_t dma_addr = 0; + + if (type == BUF_TYPE_HEVC) + parser_type = PARSER_VIDEO; + else if (type == BUF_TYPE_VIDEO) + parser_type = PARSER_VIDEO; + else if (type == BUF_TYPE_AUDIO) + parser_type = PARSER_AUDIO; + else + parser_type = PARSER_SUBPIC; + + wp = buf_wp(type); + + if (r > 0) { + if (isphybuf) + len = count; + else { + len = min_t(size_t, r, (size_t) FETCHBUF_SIZE); + + if (copy_from_user(fetchbuf, p, len)) + return -EFAULT; + dma_addr = dma_map_single( + amports_get_dma_device(), fetchbuf, + FETCHBUF_SIZE, DMA_TO_DEVICE); + if (dma_mapping_error(amports_get_dma_device(), + (dma_addr_t) dma_addr)) + return -EFAULT; + + } + + /* wmb(); don't need */ + /* reset the Write and read pointer to zero again */ + WRITE_PARSER_REG(PFIFO_RD_PTR, 0); + WRITE_PARSER_REG(PFIFO_WR_PTR, 0); + + WRITE_PARSER_REG_BITS(PARSER_CONTROL, len, ES_PACK_SIZE_BIT, + ES_PACK_SIZE_WID); + WRITE_PARSER_REG_BITS(PARSER_CONTROL, + parser_type | PARSER_WRITE | + PARSER_AUTOSEARCH, ES_CTRL_BIT, + ES_CTRL_WID); + + if (isphybuf) { + u32 buf_32 = (unsigned long)buf & 0xffffffff; + WRITE_PARSER_REG(PARSER_FETCH_ADDR, buf_32); + } else { + WRITE_PARSER_REG(PARSER_FETCH_ADDR, dma_addr); + dma_unmap_single(amports_get_dma_device(), dma_addr, + FETCHBUF_SIZE, DMA_TO_DEVICE); + } + + search_done = 0; + if (!(isphybuf & TYPE_PATTERN)) { + WRITE_PARSER_REG(PARSER_FETCH_CMD, + (7 << FETCH_ENDIAN) | len); + WRITE_PARSER_REG(PARSER_FETCH_ADDR, search_pattern_map); + WRITE_PARSER_REG(PARSER_FETCH_CMD, + (7 << FETCH_ENDIAN) | SEARCH_PATTERN_LEN); + } else { + WRITE_PARSER_REG(PARSER_FETCH_CMD, + (7 << FETCH_ENDIAN) | (len + 512)); + } + ret = wait_event_interruptible_timeout(wq, search_done != 0, + HZ / 5); + if (ret == 0) { + WRITE_PARSER_REG(PARSER_FETCH_CMD, 0); + + if (wp == buf_wp(type)) { + /*no data fetched */ + return -EAGAIN; + } else { + pr_info("W Timeout, but fetch ok,"); + pr_info("type %d len=%d,wpdiff=%d, isphy %x\n", + type, len, wp - buf_wp(type), isphybuf); + } + } else if (ret < 0) + return -ERESTARTSYS; + } + + if ((type == BUF_TYPE_VIDEO) + || (has_hevc_vdec() && (type == BUF_TYPE_HEVC))) + video_data_parsed += len; + else if (type == BUF_TYPE_AUDIO) + audio_data_parsed += len; + + return len; +} + +static ssize_t _esparser_write_s(const char __user *buf, + size_t count, u32 type) +{ + size_t r = count; + const char __user *p = buf; + u32 len = 0; + int ret; + u32 wp, buf_start, buf_end; + dma_addr_t buf_wp_map; + + if (type != BUF_TYPE_AUDIO) + BUG(); + wp = get_buf_wp(type); + buf_end = get_buf_end(type) + 8; + buf_start = get_buf_start(type); + /*pr_info("write wp 0x%x, count %d, start 0x%x, end 0x%x\n", + * wp, (u32)count, buf_start, buf_end);*/ + if (wp + count > buf_end) { + ret = copy_from_user(codec_mm_phys_to_virt(wp), + p, buf_end - wp); + if (ret > 0) { + len += buf_end - wp - ret; + buf_wp_map = dma_map_single(amports_get_dma_device(), + codec_mm_phys_to_virt(wp), len, DMA_TO_DEVICE); + wp += len; + pr_info("copy from user not finished\n"); + dma_unmap_single(NULL, buf_wp_map, len, DMA_TO_DEVICE); + set_buf_wp(type, wp); + goto end_write; + } else if (ret == 0) { + len += buf_end - wp; + buf_wp_map = dma_map_single(amports_get_dma_device(), + codec_mm_phys_to_virt(wp), len, DMA_TO_DEVICE); + wp = buf_start; + r = count - len; + dma_unmap_single(NULL, buf_wp_map, len, DMA_TO_DEVICE); + set_buf_wp(type, wp); + } else { + pr_info("copy from user failed 1\n"); + pr_info("w wp 0x%x, count %d, start 0x%x end 0x%x\n", + wp, (u32)count, buf_start, buf_end); + return -EAGAIN; + } + } + ret = copy_from_user(codec_mm_phys_to_virt(wp), p + len, r); + if (ret >= 0) { + len += r - ret; + buf_wp_map = dma_map_single(amports_get_dma_device(), + codec_mm_phys_to_virt(wp), r - ret, DMA_TO_DEVICE); + + if (ret > 0) + pr_info("copy from user not finished 2\n"); + wp += r - ret; + dma_unmap_single(NULL, buf_wp_map, r - ret, DMA_TO_DEVICE); + set_buf_wp(type, wp); + } else { + pr_info("copy from user failed 2\n"); + return -EAGAIN; + } + +end_write: + if (type == BUF_TYPE_AUDIO) + audio_data_parsed += len; + + return len; +} + +s32 es_vpts_checkin_us64(struct stream_buf_s *buf, u64 us64) +{ + u32 passed; + + if (buf->write_thread) + passed = threadrw_dataoffset(buf); + else + passed = video_data_parsed; + return pts_checkin_offset_us64(PTS_TYPE_VIDEO, passed, us64); + +} + +s32 es_apts_checkin_us64(struct stream_buf_s *buf, u64 us64) +{ + u32 passed; + + if (buf->write_thread) + passed = threadrw_dataoffset(buf); + else + passed = audio_data_parsed; + return pts_checkin_offset_us64(PTS_TYPE_AUDIO, passed, us64); +} + +s32 es_vpts_checkin(struct stream_buf_s *buf, u32 pts) +{ +#if 0 + if (buf->first_tstamp == INVALID_PTS) { + buf->flag |= BUF_FLAG_FIRST_TSTAMP; + buf->first_tstamp = pts; + return 0; + } +#endif + u32 passed = video_data_parsed + threadrw_buffer_level(buf); + + return pts_checkin_offset(PTS_TYPE_VIDEO, passed, pts); + +} + +s32 es_apts_checkin(struct stream_buf_s *buf, u32 pts) +{ +#if 0 + if (buf->first_tstamp == INVALID_PTS) { + buf->flag |= BUF_FLAG_FIRST_TSTAMP; + buf->first_tstamp = pts; + + return 0; + } +#endif + u32 passed = audio_data_parsed + threadrw_buffer_level(buf); + + return pts_checkin_offset(PTS_TYPE_AUDIO, passed, pts); +} + +s32 esparser_init(struct stream_buf_s *buf, struct vdec_s *vdec) +{ + s32 r = 0; + u32 pts_type; + u32 parser_sub_start_ptr; + u32 parser_sub_end_ptr; + u32 parser_sub_rp; + bool first_use = false; + /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ + if (has_hevc_vdec() && (buf->type == BUF_TYPE_HEVC)) + pts_type = PTS_TYPE_HEVC; + else + /* #endif */ + if (buf->type == BUF_TYPE_VIDEO) + pts_type = PTS_TYPE_VIDEO; + else if (buf->type == BUF_TYPE_AUDIO) + pts_type = PTS_TYPE_AUDIO; + else if (buf->type == BUF_TYPE_SUBTITLE) + pts_type = PTS_TYPE_MAX; + else + return -EINVAL; + mutex_lock(&esparser_mutex); + parser_sub_start_ptr = READ_PARSER_REG(PARSER_SUB_START_PTR); + parser_sub_end_ptr = READ_PARSER_REG(PARSER_SUB_END_PTR); + parser_sub_rp = READ_PARSER_REG(PARSER_SUB_RP); + + buf->flag |= BUF_FLAG_PARSER; + + if (atomic_add_return(1, &esparser_use_count) == 1) { + first_use = true; + + if (fetchbuf == 0) { + pr_info("%s: no fetchbuf\n", __func__); + r = -ENOMEM; + goto Err_1; + } + + if (search_pattern == NULL) { + search_pattern = kcalloc(1, + SEARCH_PATTERN_LEN, + GFP_KERNEL); + + if (search_pattern == NULL) { + pr_err("%s: no search_pattern\n", __func__); + r = -ENOMEM; + goto Err_1; + } + + /* build a fake start code to get parser interrupt */ + search_pattern[0] = 0x00; + search_pattern[1] = 0x00; + search_pattern[2] = 0x01; + search_pattern[3] = 0xff; + + search_pattern_map = dma_map_single( + amports_get_dma_device(), + search_pattern, + SEARCH_PATTERN_LEN, + DMA_TO_DEVICE); + } + + /* reset PARSER with first esparser_init() call */ + WRITE_RESET_REG(RESET1_REGISTER, RESET_PARSER); + + /* TS data path */ +#ifndef CONFIG_AM_DVB + WRITE_DEMUX_REG(FEC_INPUT_CONTROL, 0); +#else + tsdemux_set_reset_flag(); +#endif + CLEAR_DEMUX_REG_MASK(TS_HIU_CTL, 1 << USE_HI_BSF_INTERFACE); + CLEAR_DEMUX_REG_MASK(TS_HIU_CTL_2, 1 << USE_HI_BSF_INTERFACE); + CLEAR_DEMUX_REG_MASK(TS_HIU_CTL_3, 1 << USE_HI_BSF_INTERFACE); + + CLEAR_DEMUX_REG_MASK(TS_FILE_CONFIG, (1 << TS_HIU_ENABLE)); + + WRITE_PARSER_REG(PARSER_CONFIG, + (10 << PS_CFG_PFIFO_EMPTY_CNT_BIT) | + (1 << PS_CFG_MAX_ES_WR_CYCLE_BIT) | + (16 << PS_CFG_MAX_FETCH_CYCLE_BIT)); + + WRITE_PARSER_REG(PFIFO_RD_PTR, 0); + WRITE_PARSER_REG(PFIFO_WR_PTR, 0); + + WRITE_PARSER_REG(PARSER_SEARCH_PATTERN, ES_START_CODE_PATTERN); + WRITE_PARSER_REG(PARSER_SEARCH_MASK, ES_START_CODE_MASK); + + WRITE_PARSER_REG(PARSER_CONFIG, + (10 << PS_CFG_PFIFO_EMPTY_CNT_BIT) | + (1 << PS_CFG_MAX_ES_WR_CYCLE_BIT) | + PS_CFG_STARTCODE_WID_24 | + PS_CFG_PFIFO_ACCESS_WID_8 | + /* single byte pop */ + (16 << PS_CFG_MAX_FETCH_CYCLE_BIT)); + + WRITE_PARSER_REG(PARSER_CONTROL, PARSER_AUTOSEARCH); + + } + + /* hook stream buffer with PARSER */ + if (has_hevc_vdec() && (pts_type == PTS_TYPE_HEVC)) { + WRITE_PARSER_REG(PARSER_VIDEO_START_PTR, vdec->input.start); + WRITE_PARSER_REG(PARSER_VIDEO_END_PTR, vdec->input.start + + vdec->input.size - 8); + + if (vdec_single(vdec)) { + CLEAR_PARSER_REG_MASK(PARSER_ES_CONTROL, + ES_VID_MAN_RD_PTR); + + /* set vififo_vbuf_rp_sel=>hevc */ + WRITE_VREG(DOS_GEN_CTRL0, 3 << 1); + + /* set use_parser_vbuf_wp */ + SET_VREG_MASK(HEVC_STREAM_CONTROL, + (1 << 3) | (0 << 4)); + /* set stream_fetch_enable */ + SET_VREG_MASK(HEVC_STREAM_CONTROL, 1); + + /* set stream_buffer_hole with 256 bytes */ + SET_VREG_MASK(HEVC_STREAM_FIFO_CTL, (1 << 29)); + } else { + SET_PARSER_REG_MASK(PARSER_ES_CONTROL, + ES_VID_MAN_RD_PTR); + WRITE_PARSER_REG(PARSER_VIDEO_WP, vdec->input.start); + WRITE_PARSER_REG(PARSER_VIDEO_RP, vdec->input.start); + } + video_data_parsed = 0; + } else if (pts_type == PTS_TYPE_VIDEO) { + WRITE_PARSER_REG(PARSER_VIDEO_START_PTR, + vdec->input.start); + WRITE_PARSER_REG(PARSER_VIDEO_END_PTR, + vdec->input.start + vdec->input.size - 8); + if (vdec_single(vdec)) { + CLEAR_PARSER_REG_MASK(PARSER_ES_CONTROL, + ES_VID_MAN_RD_PTR); + + WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + CLEAR_VREG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, + MEM_BUFCTRL_INIT); + + if (has_hevc_vdec()) { + /* set vififo_vbuf_rp_sel=>vdec */ + WRITE_VREG(DOS_GEN_CTRL0, 0); + } + } else { + SET_PARSER_REG_MASK(PARSER_ES_CONTROL, + ES_VID_MAN_RD_PTR); + WRITE_PARSER_REG(PARSER_VIDEO_WP, + vdec->input.start); + WRITE_PARSER_REG(PARSER_VIDEO_RP, + vdec->input.start); + } + video_data_parsed = 0; + } else if (pts_type == PTS_TYPE_AUDIO) { + /* set wp as buffer start */ + SET_AIU_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, + MEM_BUFCTRL_MANUAL); + WRITE_AIU_REG(AIU_MEM_AIFIFO_MAN_RP, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + WRITE_AIU_REG_BITS(AIU_MEM_AIFIFO_CONTROL, 7, 3, 3); + SET_AIU_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, + MEM_BUFCTRL_INIT); + CLEAR_AIU_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, + MEM_BUFCTRL_INIT); + WRITE_AIU_REG(AIU_MEM_AIFIFO_MAN_WP, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + audio_data_parsed = 0; + audio_buf_start = + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR); + audio_real_wp = audio_buf_start; + audio_buf_end = READ_AIU_REG(AIU_MEM_AIFIFO_END_PTR); + } else if (buf->type == BUF_TYPE_SUBTITLE) { + WRITE_PARSER_REG(PARSER_SUB_START_PTR, + parser_sub_start_ptr); + WRITE_PARSER_REG(PARSER_SUB_END_PTR, + parser_sub_end_ptr); + WRITE_PARSER_REG(PARSER_SUB_RP, parser_sub_rp); + SET_PARSER_REG_MASK(PARSER_ES_CONTROL, + (7 << ES_SUB_WR_ENDIAN_BIT) | + ES_SUB_MAN_RD_PTR); + } + + if (pts_type < PTS_TYPE_MAX) { + r = pts_start(pts_type); + + if (r < 0) { + pr_info("esparser_init: pts_start failed\n"); + goto Err_1; + } + } +#if 0 + if (buf->flag & BUF_FLAG_FIRST_TSTAMP) { + if (buf->type == BUF_TYPE_VIDEO) + es_vpts_checkin(buf, buf->first_tstamp); + else if (buf->type == BUF_TYPE_AUDIO) + es_apts_checkin(buf, buf->first_tstamp); + + buf->flag &= ~BUF_FLAG_FIRST_TSTAMP; + } +#endif + + if (first_use) { + /*TODO irq */ + r = vdec_request_irq(PARSER_IRQ, esparser_isr, + "parser", (void *)esparser_id); + + if (r) { + pr_info("esparser_init: irq register failed.\n"); + goto Err_2; + } + + WRITE_PARSER_REG(PARSER_INT_STATUS, 0xffff); + WRITE_PARSER_REG(PARSER_INT_ENABLE, + PARSER_INTSTAT_SC_FOUND << + PARSER_INT_HOST_EN_BIT); + } + mutex_unlock(&esparser_mutex); + if (!(vdec_get_debug_flags() & 1) && + !codec_mm_video_tvp_enabled()) { + int block_size = (buf->type == BUF_TYPE_AUDIO) ? + PAGE_SIZE : PAGE_SIZE << 4; + int buf_num = (buf->type == BUF_TYPE_AUDIO) ? + 20 : (2 * SZ_1M)/(PAGE_SIZE << 4); + if (!(buf->type == BUF_TYPE_SUBTITLE)) + buf->write_thread = threadrw_alloc(buf_num, + block_size, + esparser_write_ex, + (buf->type == BUF_TYPE_AUDIO) ? 1 : 0); + /*manul mode for audio*/ + } + return 0; + +Err_2: + pts_stop(pts_type); + +Err_1: + atomic_dec(&esparser_use_count); + buf->flag &= ~BUF_FLAG_PARSER; + mutex_unlock(&esparser_mutex); + return r; +} + +void esparser_audio_reset_s(struct stream_buf_s *buf) +{ + ulong flags; + DEFINE_SPINLOCK(lock); + + spin_lock_irqsave(&lock, flags); + + SET_AIU_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_MANUAL); + WRITE_AIU_REG(AIU_MEM_AIFIFO_MAN_RP, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + WRITE_AIU_REG_BITS(AIU_MEM_AIFIFO_CONTROL, 7, 3, 3); + SET_AIU_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + CLEAR_AIU_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + WRITE_AIU_REG(AIU_MEM_AIFIFO_MAN_WP, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + + buf->flag |= BUF_FLAG_PARSER; + + audio_data_parsed = 0; + audio_real_wp = READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR); + audio_buf_start = READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR); + audio_buf_end = READ_AIU_REG(AIU_MEM_AIFIFO_END_PTR); + spin_unlock_irqrestore(&lock, flags); + + return; +} + +void esparser_audio_reset(struct stream_buf_s *buf) +{ + ulong flags; + DEFINE_SPINLOCK(lock); + + spin_lock_irqsave(&lock, flags); + + WRITE_PARSER_REG(PARSER_AUDIO_WP, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + WRITE_PARSER_REG(PARSER_AUDIO_RP, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + + WRITE_PARSER_REG(PARSER_AUDIO_START_PTR, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + WRITE_PARSER_REG(PARSER_AUDIO_END_PTR, + READ_AIU_REG(AIU_MEM_AIFIFO_END_PTR)); + CLEAR_PARSER_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR); + + WRITE_AIU_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + CLEAR_AIU_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + + buf->flag |= BUF_FLAG_PARSER; + + audio_data_parsed = 0; + audio_real_wp = 0; + audio_buf_start = 0; + audio_buf_end = 0; + spin_unlock_irqrestore(&lock, flags); + +} + +void esparser_release(struct stream_buf_s *buf) +{ + u32 pts_type; + + /* check if esparser_init() is ever called */ + if ((buf->flag & BUF_FLAG_PARSER) == 0) + return; + + if (atomic_read(&esparser_use_count) == 0) { + pr_info + ("[%s:%d]###warning, esparser has been released already\n", + __func__, __LINE__); + return; + } + if (buf->write_thread) + threadrw_release(buf); + if (atomic_dec_and_test(&esparser_use_count)) { + WRITE_PARSER_REG(PARSER_INT_ENABLE, 0); + /*TODO irq */ + + vdec_free_irq(PARSER_IRQ, (void *)esparser_id); + + if (search_pattern) { + dma_unmap_single(amports_get_dma_device(), + search_pattern_map, + SEARCH_PATTERN_LEN, DMA_TO_DEVICE); + kfree(search_pattern); + search_pattern = NULL; + } + } + + if (has_hevc_vdec() && (buf->type == BUF_TYPE_HEVC)) + pts_type = PTS_TYPE_VIDEO; + else if (buf->type == BUF_TYPE_VIDEO) + pts_type = PTS_TYPE_VIDEO; + else if (buf->type == BUF_TYPE_AUDIO) + pts_type = PTS_TYPE_AUDIO; + else if (buf->type == BUF_TYPE_SUBTITLE) { + buf->flag &= ~BUF_FLAG_PARSER; + return; + } else + return; + + buf->flag &= ~BUF_FLAG_PARSER; + pts_stop(pts_type); +} + +ssize_t drm_write(struct file *file, struct stream_buf_s *stbuf, + const char __user *buf, size_t count) +{ + s32 r; + u32 len; + u32 realcount, totalcount; + u32 re_count = count; + u32 havewritebytes = 0; + u32 leftcount = 0; + + struct drm_info tmpmm; + struct drm_info *drm = &tmpmm; + u32 res = 0; + int isphybuf = 0; + unsigned long realbuf; + + if (buf == NULL || count == 0) + return -EINVAL; + if (stbuf->write_thread) { + r = threadrw_flush_buffers(stbuf); + if (r < 0) + pr_info("Warning. drm flush threadrw failed[%d]\n", r); + } + res = copy_from_user(drm, buf, sizeof(struct drm_info)); + if (res) { + pr_info("drm kmalloc failed res[%d]\n", res); + return -EFAULT; + } + + if ((drm->drm_flag & TYPE_DRMINFO) && (drm->drm_hasesdata == 0)) { + /* buf only has drminfo not have esdata; */ + realbuf = drm->drm_phy; + realcount = drm->drm_pktsize; + isphybuf = drm->drm_flag; + /* DRM_PRNT("drm_get_rawdata + *onlydrminfo drm->drm_hasesdata[0x%x] + * stbuf->type %d buf[0x%x]\n", + *drm->drm_hasesdata,stbuf->type,buf); + */ + } else if (drm->drm_hasesdata == 1) { /* buf is drminfo+es; */ + realcount = drm->drm_pktsize; + realbuf = (unsigned long)buf + sizeof(struct drm_info); + isphybuf = 0; + /* DRM_PRNT("drm_get_rawdata + * drminfo+es drm->drm_hasesdata[0x%x] + * stbuf->type %d\n",drm->drm_hasesdata,stbuf->type); + */ + } else { /* buf is hwhead; */ + realcount = count; + isphybuf = 0; + realbuf = (unsigned long)buf; + /* DRM_PRNT("drm_get_rawdata + * drm->drm_hasesdata[0x%x] + * len[%d] count[%d] realcout[%d]\n", + * drm->drm_hasesdata,len,count,realcount); + */ + } + + len = realcount; + count = realcount; + totalcount = realcount; + + while (len > 0) { + if (stbuf->type != BUF_TYPE_SUBTITLE + && stbuf_space(stbuf) < count) { + /*should not write partial data in drm mode*/ + stbuf_wait_space(stbuf, count); + if (stbuf_space(stbuf) < count) + return -EAGAIN; + } + len = min_t(u32, len, count); + + mutex_lock(&esparser_mutex); + + if (stbuf->type != BUF_TYPE_AUDIO) + r = _esparser_write((const char __user *)realbuf, len, + stbuf->type, isphybuf); + else + r = _esparser_write_s((const char __user *)realbuf, len, + stbuf->type); + if (r < 0) { + pr_info("drm_write _esparser_write failed [%d]\n", r); + return r; + } + havewritebytes += r; + leftcount = totalcount - havewritebytes; + if (havewritebytes == totalcount) { + + mutex_unlock(&esparser_mutex); + break; /* write ok; */ + } else if ((len > 0) && (havewritebytes < totalcount)) { + DRM_PRNT + ("d writebytes[%d] want[%d] total[%d] real[%d]\n", + havewritebytes, len, totalcount, realcount); + len = len - r; /* write again; */ + realbuf = realbuf + r; + } else { + pr_info + ("e writebytes[%d] want[%d] total[%d] real[%d]\n", + havewritebytes, len, totalcount, realcount); + } + mutex_unlock(&esparser_mutex); + } + + return re_count; +} +/* + *flags: + *1:phy + *2:noblock + */ +ssize_t esparser_write_ex(struct file *file, + struct stream_buf_s *stbuf, + const char __user *buf, size_t count, + int flags) +{ + + s32 r; + u32 len = count; + + if (buf == NULL || count == 0) + return -EINVAL; + + /*subtitle have no level to check, */ + if (stbuf->type != BUF_TYPE_SUBTITLE && stbuf_space(stbuf) < count) { + if ((flags & 2) || ((file != NULL) && + (file->f_flags & O_NONBLOCK))) { + len = stbuf_space(stbuf); + + if (len < 256) /* <1k.do eagain, */ + return -EAGAIN; + } else { + len = min(stbuf_canusesize(stbuf) / 8, len); + + if (stbuf_space(stbuf) < len) { + r = stbuf_wait_space(stbuf, len); + if (r < 0) + return r; + } + } + } + + stbuf->last_write_jiffies64 = jiffies_64; + + len = min_t(u32, len, count); + + mutex_lock(&esparser_mutex); + + if (stbuf->type == BUF_TYPE_AUDIO) + r = _esparser_write_s(buf, len, stbuf->type); + else + r = _esparser_write(buf, len, stbuf->type, flags & 1); + + mutex_unlock(&esparser_mutex); + + return r; +} +ssize_t esparser_write(struct file *file, + struct stream_buf_s *stbuf, + const char __user *buf, size_t count) +{ + if (stbuf->write_thread) { + ssize_t ret; + + ret = threadrw_write(file, stbuf, buf, count); + if (ret == -EAGAIN) { + u32 a, b; + int vdelay, adelay; + + if ((stbuf->type != BUF_TYPE_VIDEO) && + (stbuf->type != BUF_TYPE_HEVC)) + return ret; + if (stbuf->buf_size > (SZ_1M * 30) || + (threadrw_buffer_size(stbuf) > SZ_1M * 10) || + !threadrw_support_more_buffers(stbuf)) + return ret; + /*only chang buffer for video.*/ + vdelay = calculation_stream_delayed_ms( + PTS_TYPE_VIDEO, &a, &b); + adelay = calculation_stream_delayed_ms( + PTS_TYPE_AUDIO, &a, &b); + if ((vdelay > 100 && vdelay < 2000) && /*vdelay valid.*/ + ((vdelay < 500) ||/*video delay is short!*/ + (adelay > 0 && adelay < 1000))/*audio is low.*/ + ) { + /*on buffer fulled. + *if delay is less than 100ms we think errors, + *And we add more buffer on delay < 2s. + */ + int new_size = 2 * 1024 * 1024; + + threadrw_alloc_more_buffer_size( + stbuf, new_size); + } + } + return ret; + } + return esparser_write_ex(file, stbuf, buf, count, 0); +} + + +void esparser_sub_reset(void) +{ + ulong flags; + DEFINE_SPINLOCK(lock); + u32 parser_sub_start_ptr; + u32 parser_sub_end_ptr; + + spin_lock_irqsave(&lock, flags); + + parser_sub_start_ptr = READ_PARSER_REG(PARSER_SUB_START_PTR); + parser_sub_end_ptr = READ_PARSER_REG(PARSER_SUB_END_PTR); + + WRITE_PARSER_REG(PARSER_SUB_START_PTR, parser_sub_start_ptr); + WRITE_PARSER_REG(PARSER_SUB_END_PTR, parser_sub_end_ptr); + WRITE_PARSER_REG(PARSER_SUB_RP, parser_sub_start_ptr); + WRITE_PARSER_REG(PARSER_SUB_WP, parser_sub_start_ptr); + SET_PARSER_REG_MASK(PARSER_ES_CONTROL, + (7 << ES_SUB_WR_ENDIAN_BIT) | ES_SUB_MAN_RD_PTR); + + spin_unlock_irqrestore(&lock, flags); +} diff --git a/drivers/amlogic/media_modules/stream_input/parser/esparser.h b/drivers/amlogic/media_modules/stream_input/parser/esparser.h new file mode 100644 index 000000000000..24e6926e91ed --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/esparser.h @@ -0,0 +1,152 @@ +/* + * drivers/amlogic/media/stream_input/parser/esparser.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef ESPARSER_H +#define ESPARSER_H + +#include "../../frame_provider/decoder/utils/vdec.h" + +extern ssize_t drm_write(struct file *file, + struct stream_buf_s *stbuf, + const char __user *buf, size_t count); + +extern s32 esparser_init(struct stream_buf_s *buf, struct vdec_s *vdec); +extern s32 esparser_init_s(struct stream_buf_s *buf); +extern void esparser_release(struct stream_buf_s *buf); +extern ssize_t esparser_write(struct file *file, + struct stream_buf_s *stbuf, + const char __user *buf, size_t count); +extern ssize_t esparser_write_ex(struct file *file, + struct stream_buf_s *stbuf, + const char __user *buf, size_t count, + int is_phy); + +extern s32 es_vpts_checkin_us64(struct stream_buf_s *buf, u64 us64); + +extern s32 es_apts_checkin_us64(struct stream_buf_s *buf, u64 us64); + +extern int es_vpts_checkin(struct stream_buf_s *buf, u32 pts); + +extern int es_apts_checkin(struct stream_buf_s *buf, u32 pts); + +extern void esparser_audio_reset(struct stream_buf_s *buf); +extern void esparser_audio_reset_s(struct stream_buf_s *buf); + +extern void esparser_sub_reset(void); + +#ifdef CONFIG_AM_DVB +extern int tsdemux_set_reset_flag(void); +#endif + +/* TODO: move to register headers */ +#define ES_PACK_SIZE_BIT 8 +#define ES_PACK_SIZE_WID 24 + +#define ES_CTRL_WID 8 +#define ES_CTRL_BIT 0 +#define ES_TYPE_MASK (3 << 6) +#define ES_TYPE_VIDEO (0 << 6) +#define ES_TYPE_AUDIO (1 << 6) +#define ES_TYPE_SUBTITLE (2 << 6) + +#define ES_WRITE (1<<5) +#define ES_PASSTHROUGH (1<<4) +#define ES_INSERT_BEFORE_ES_WRITE (1<<3) +#define ES_DISCARD (1<<2) +#define ES_SEARCH (1<<1) +#define ES_PARSER_START (1<<0) +#define ES_PARSER_BUSY (1<<0) + +#define PARSER_INTSTAT_FETCH_CMD (1<<7) +#define PARSER_INTSTAT_PARSE (1<<4) +#define PARSER_INTSTAT_DISCARD (1<<3) +#define PARSER_INTSTAT_INSZERO (1<<2) +#define PARSER_INTSTAT_ACT_NOSSC (1<<1) +#define PARSER_INTSTAT_SC_FOUND (1<<0) + +#define FETCH_CIR_BUF (1<<31) +#define FETCH_CHK_BUF_STOP (1<<30) +#define FETCH_PASSTHROUGH (1<<29) +#define FETCH_ENDIAN 27 +#define FETCH_PASSTHROUGH_TYPE_MASK (0x3<<27) +#define FETCH_ENDIAN_MASK (0x7<<27) +#define FETCH_BUF_SIZE_MASK (0x7ffffff) +#define FETCH_CMD_PTR_MASK 3 +#define FETCH_CMD_RD_PTR_BIT 5 +#define FETCH_CMD_WR_PTR_BIT 3 +#define FETCH_CMD_NUM_MASK 3 +#define FETCH_CMD_NUM_BIT 0 + +#define ES_COUNT_MASK 0xfff +#define ES_COUNT_BIT 20 +#define ES_REQ_PENDING (1<<19) +#define ES_PASSTHROUGH_EN (1<<18) +#define ES_PASSTHROUGH_TYPE_MASK (3<<16) +#define ES_PASSTHROUGH_TYPE_VIDEO (0<<16) +#define ES_PASSTHROUGH_TYPE_AUDIO (1<<16) +#define ES_PASSTHROUGH_TYPE_SUBTITLE (2<<16) +#define ES_WR_ENDIAN_MASK (0x7) +#define ES_SUB_WR_ENDIAN_BIT 9 +#define ES_SUB_MAN_RD_PTR (1<<8) +#define ES_AUD_WR_ENDIAN_BIT 5 +#define ES_AUD_MAN_RD_PTR (1<<4) +#define ES_VID_WR_ENDIAN_BIT 1 +#define ES_VID_MAN_RD_PTR (1<<0) + +#define PS_CFG_FETCH_DMA_URGENT (1<<31) +#define PS_CFG_STREAM_DMA_URGENT (1<<30) +#define PS_CFG_FORCE_PFIFO_REN (1<<29) +#define PS_CFG_PFIFO_PEAK_EN (1<<28) +#define PS_CFG_SRC_SEL_BIT 24 +#define PS_CFG_SRC_SEL_MASK (3< +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../streambuf.h" +#include "c_stb_define.h" +#include "c_stb_regs_define.h" +#include "aml_dvb.h" +#include "aml_dvb_reg.h" + + +#define ENABLE_SEC_BUFF_WATCHDOG +#define USE_AHB_MODE +#define PR_ERROR_SPEED_LIMIT + +#define pr_dbg_flag(_f, _args...)\ + do {\ + if (debug_dmx&(_f))\ + printk(_args);\ + } while (0) +#define pr_dbg_irq_flag(_f, _args...)\ + do {\ + if (debug_irq&(_f))\ + printk(_args);\ + } while (0) +#define pr_dbg(args...) pr_dbg_flag(0x1, args) +#define pr_dbg_irq(args...)pr_dbg_irq_flag(0x1, args) +#define pr_dbg_irq_dvr(args...)pr_dbg_irq_flag(0x2, args) +#define pr_dbg_sf(args...) pr_dbg_flag(0x4, args) +#define pr_dbg_irq_sf(args...) pr_dbg_irq_flag(0x4, args) +#define pr_dbg_ss(args...) pr_dbg_flag(0x8, args) +#define pr_dbg_irq_ss(args...) pr_dbg_irq_flag(0x8, args) +#define pr_dbg_irq_pes(args...) pr_dbg_irq_flag(0x10, args) + +#ifdef PR_ERROR_SPEED_LIMIT +static u32 last_pr_error_time; +#define pr_error(fmt, _args...)\ + do {\ + u32 diff = jiffies_to_msecs(jiffies - last_pr_error_time);\ + if (!last_pr_error_time || diff > 50) {\ + pr_err("DVB:" fmt, ## _args);\ + last_pr_error_time = jiffies;\ + } \ + } while (0) +#else +#define pr_error(fmt, args...) pr_err("DVB: " fmt, ## args) +#endif + +#define pr_inf(fmt, args...) printk("DVB: " fmt, ## args) + +#define dump(b, l) \ + do { \ + int i; \ + printk("dump: "); \ + for (i = 0; i < (l); i++) {\ + if (!(i&0xf)) \ + printk("\n\t"); \ + printk("%02x ", *(((unsigned char *)(b))+i)); \ + } \ + printk("\n"); \ + } while (0) + +MODULE_PARM_DESC(debug_dmx, "\n\t\t Enable demux debug information"); +static int debug_dmx; +module_param(debug_dmx, int, 0644); + +MODULE_PARM_DESC(debug_irq, "\n\t\t Enable demux IRQ debug information"); +static int debug_irq; +module_param(debug_irq, int, 0644); + +MODULE_PARM_DESC(disable_dsc, "\n\t\t Disable discrambler"); +static int disable_dsc; +module_param(disable_dsc, int, 0644); + +/*For old version kernel */ +#ifndef MESON_CPU_MAJOR_ID_GXL +#define MESON_CPU_MAJOR_ID_GXL 0x21 +#endif + +static int npids = CHANNEL_COUNT; +#define MOD_PARAM_DECLARE_CHANPIDS(_dmx) \ +MODULE_PARM_DESC(debug_dmx##_dmx##_chanpids, "\n\t\t pids of dmx channels"); \ +static short debug_dmx##_dmx##_chanpids[CHANNEL_COUNT] = \ + {[0 ... (CHANNEL_COUNT - 1)] = -1}; \ +module_param_array(debug_dmx##_dmx##_chanpids, short, &npids, 0444) + +#define CIPLUS_OUTPUT_AUTO 8 +static int ciplus_out_sel = CIPLUS_OUTPUT_AUTO; +static int ciplus_out_auto_mode = 1; + +MOD_PARAM_DECLARE_CHANPIDS(0); +MOD_PARAM_DECLARE_CHANPIDS(1); +MOD_PARAM_DECLARE_CHANPIDS(2); + +#define set_debug_dmx_chanpids(_dmx, _idx, _pid)\ + do { \ + if ((_dmx) == 0) \ + debug_dmx0_chanpids[(_idx)] = (_pid); \ + else if ((_dmx) == 1) \ + debug_dmx1_chanpids[(_idx)] = (_pid); \ + else if ((_dmx) == 2) \ + debug_dmx2_chanpids[(_idx)] = (_pid); \ + } while (0) + +MODULE_PARM_DESC(debug_sf_user, "\n\t\t only for sf mode check"); +static int debug_sf_user; +module_param(debug_sf_user, int, 0444); + +MODULE_PARM_DESC(force_sec_sf, "\n\t\t force sf mode for sec filter"); +static int force_sec_sf; +module_param(force_sec_sf, int, 0644); + +MODULE_PARM_DESC(force_pes_sf, "\n\t\t force sf mode for pes filter"); +static int force_pes_sf; +module_param(force_pes_sf, int, 0644); + +MODULE_PARM_DESC(use_of_sop, "\n\t\t Enable use of sop input"); +static int use_of_sop; +module_param(use_of_sop, int, 0644); + +/*#define CIPLUS_KEY0 0x16f8 +#define CIPLUS_KEY1 0x16f9 +#define CIPLUS_KEY2 0x16fa +#define CIPLUS_KEY3 0x16fb +#define CIPLUS_KEY_WR 0x16fc +#define CIPLUS_CONFIG 0x16fd +#define CIPLUS_ENDIAN 0x16fe*/ + +static u32 old_stb_top_config; +static u32 old_fec_input_control; +static int have_old_stb_top_config = 1; +static int have_old_fec_input_control = 1; + +static void +dmx_write_reg(int r, u32 v) +{ + u32 oldv, mask; + + if (disable_dsc) { + if (r == STB_TOP_CONFIG) { + if (have_old_stb_top_config) { + oldv = old_stb_top_config; + have_old_stb_top_config = 0; + } else { + oldv = READ_MPEG_REG(STB_TOP_CONFIG); + } + + mask = (1<<7)|(1<<15)|(3<<26)|(7<<28); + v &= ~mask; + v |= (oldv & mask); + } else if (r == FEC_INPUT_CONTROL) { + if (have_old_fec_input_control) { + oldv = old_fec_input_control; + have_old_fec_input_control = 0; + } else { + oldv = READ_MPEG_REG(FEC_INPUT_CONTROL); + } + + mask = (1<<15); + v &= ~mask; + v |= (oldv & mask); + } else if ((r == RESET1_REGISTER) || (r == RESET3_REGISTER)) { + if (!have_old_stb_top_config) { + have_old_stb_top_config = 1; + old_stb_top_config = + READ_MPEG_REG(STB_TOP_CONFIG); + } + if (!have_old_fec_input_control) { + have_old_fec_input_control = 1; + old_fec_input_control = + READ_MPEG_REG(FEC_INPUT_CONTROL); + } + } else if ((r == TS_PL_PID_INDEX) || (r == TS_PL_PID_DATA) + || (r == COMM_DESC_KEY0) + || (r == COMM_DESC_KEY1) + || (r == COMM_DESC_KEY_RW) + || (r == CIPLUS_KEY0) + || (r == CIPLUS_KEY1) + || (r == CIPLUS_KEY2) + || (r == CIPLUS_KEY3) + || (r == CIPLUS_KEY_WR) + || (r == CIPLUS_CONFIG) + || (r == CIPLUS_ENDIAN)) { + return; + } + } + + WRITE_MPEG_REG(r, v); +} + +#undef WRITE_MPEG_REG +#define WRITE_MPEG_REG(r, v) dmx_write_reg(r, v) + +#define DMX_READ_REG(i, r)\ + ((i)?((i == 1)?READ_MPEG_REG(r##_2) :\ + READ_MPEG_REG(r##_3)) : READ_MPEG_REG(r)) + +#define DMX_WRITE_REG(i, r, d)\ + do {\ + if (i == 1) {\ + WRITE_MPEG_REG(r##_2, d);\ + } else if (i == 2) {\ + WRITE_MPEG_REG(r##_3, d);\ + } \ + else {\ + WRITE_MPEG_REG(r, d);\ + } \ + } while (0) + +#define READ_PERI_REG READ_CBUS_REG +#define WRITE_PERI_REG WRITE_CBUS_REG + +#define READ_ASYNC_FIFO_REG(i, r)\ + ((i) ? READ_PERI_REG(ASYNC_FIFO2_##r) : READ_PERI_REG(ASYNC_FIFO_##r)) + +#define WRITE_ASYNC_FIFO_REG(i, r, d)\ + do {\ + if (i == 1) {\ + WRITE_PERI_REG(ASYNC_FIFO2_##r, d);\ + } else {\ + WRITE_PERI_REG(ASYNC_FIFO_##r, d);\ + } \ + } while (0) + +#define CLEAR_ASYNC_FIFO_REG_MASK(i, reg, mask) \ + WRITE_ASYNC_FIFO_REG(i, reg, \ + (READ_ASYNC_FIFO_REG(i, reg)&(~(mask)))) + +#define DVR_FEED(f) \ + ((f) && ((f)->type == DMX_TYPE_TS) && \ + (((f)->ts_type & (TS_PACKET | TS_DEMUX)) == TS_PACKET)) + +#define MOD_PARAM_DECLARE_CHANREC(_dmx) \ +MODULE_PARM_DESC(dmx##_dmx##_chanrec_enable, \ + "\n\t\t record by channel, one time use in the beginning"); \ +static int dmx##_dmx##_chanrec_enable; \ +module_param(dmx##_dmx##_chanrec_enable, int, 0644); \ +MODULE_PARM_DESC(dmx##_dmx##_chanrec, "\n\t\t record channels bits"); \ +static int dmx##_dmx##_chanrec; \ +module_param(dmx##_dmx##_chanrec, int, 0644) + +MOD_PARAM_DECLARE_CHANREC(0); +MOD_PARAM_DECLARE_CHANREC(1); +MOD_PARAM_DECLARE_CHANREC(2); + +#define MOD_PARAM_DECLARE_CHANPROC(_dmx) \ +MODULE_PARM_DESC(dmx##_dmx##_chanproc_enable, "channel further processing"); \ +static int dmx##_dmx##_chanproc_enable; \ +module_param(dmx##_dmx##_chanproc_enable, int, 0644); \ +MODULE_PARM_DESC(dmx##_dmx##_chanproc, "further process channels bits"); \ +static int dmx##_dmx##_chanproc; \ +module_param(dmx##_dmx##_chanproc, int, 0644) + +MOD_PARAM_DECLARE_CHANPROC(0); +MOD_PARAM_DECLARE_CHANPROC(1); +MOD_PARAM_DECLARE_CHANPROC(2); + +#define DMX_CH_OP_CHANREC 0 +#define DMX_CH_OP_CHANPROC 1 + +static inline int _setbit(int v, int b) { return v|(1<id == SF_DMX_ID) \ + && ((struct aml_dvb *)(_dmx)->demux.priv)->swfilter.user) +#define sf_afifo_sf(_afifo) \ + (((_afifo)->id == SF_AFIFO_ID) && (_afifo)->dvb->swfilter.user) +#define dmx_get_dev(dmx) (((struct aml_dvb *)((dmx)->demux.priv))->dev) +#define asyncfifo_get_dev(afifo) ((afifo)->dvb->dev) + + +/*Section buffer watchdog*/ +static void section_buffer_watchdog_func(unsigned long arg) +{ + struct aml_dvb *dvb = (struct aml_dvb *)arg; + struct aml_dmx *dmx; + u32 section_busy32 = 0, om_cmd_status32 = 0, + demux_channel_activity32 = 0; + u16 demux_int_status1 = 0; + u32 device_no = 0; + u32 filter_number = 0; + u32 i = 0; + unsigned long flags; + + spin_lock_irqsave(&dvb->slock, flags); + + for (device_no = 0; device_no < DMX_DEV_COUNT; device_no++) { + + dmx = &dvb->dmx[device_no]; + + if (dvb->dmx_watchdog_disable[device_no]) + continue; + + if (!dmx->init) + continue; + + om_cmd_status32 = + DMX_READ_REG(device_no, OM_CMD_STATUS); + demux_channel_activity32 = + DMX_READ_REG(device_no, DEMUX_CHANNEL_ACTIVITY); + section_busy32 = + DMX_READ_REG(device_no, SEC_BUFF_BUSY); +#if 1 + if (om_cmd_status32 & 0x8fc2) { + /* bit 15:12 -- om_cmd_count */ + /* bit 11:9 -- overflow_count */ + /* bit 8:6 -- om_overwrite_count */ + /* bit 1 -- om_cmd_overflow */ + /*BUG: If the recoder is running, return */ + if (dmx->record) + goto end; + /*Reset the demux */ + pr_dbg("reset the demux\n" + "%04x\t%03x\t%03x\t%03x\t%01x\t%01x\t" + "%x\t%x\tdmx%d:status:0x%x\n", + (om_cmd_status32 >> 12) & 0xf, + (om_cmd_status32 >> 9) & 0x7, + (om_cmd_status32 >> 6) & 0x7, + (om_cmd_status32 >> 3) & 0x7, + (om_cmd_status32 >> 2) & 0x1, + (om_cmd_status32 >> 1) & 0x1, + demux_channel_activity32, section_busy32, + dmx->id, om_cmd_status32); + + dmx_reset_dmx_hw_ex_unlock(dvb, dmx, 0); + goto end; + } +#else + /* bit 15:12 -- om_cmd_count (read only) */ + /* bit 11:9 -- overflow_count */ + /* bit 11:9 -- om_cmd_wr_ptr(read only) */ + /* bit 8:6 -- om_overwrite_count */ + /* bit 8:6 -- om_cmd_rd_ptr(read only) */ + /* bit 5:3 -- type_stb_om_w_rd(read only) */ + /* bit 2 -- unit_start_stb_om_w_rd(read only) */ + /* bit 1 -- om_cmd_overflow(read only) */ + /* bit 0 -- om_cmd_pending(read) */ + /* bit 0 -- om_cmd_read_finished(write) */ + if (om_cmd_status32 & 0x0002) { + pr_error("reset the demux\n"); + dmx_reset_hw_ex(dvb, 0); + goto end; + } +#endif + section_busy32 = + DMX_READ_REG(device_no, SEC_BUFF_BUSY); + if (LARGE_SEC_BUFF_MASK == + (section_busy32 & LARGE_SEC_BUFF_MASK)) { + /*All the largest section buffers occupied, + * clear buffers + */ + DMX_WRITE_REG(device_no, + SEC_BUFF_READY, section_busy32); + } else { + for (i = 0; i < SEC_BUF_COUNT; i++) { + if (!(section_busy32 & (1 << i))) + continue; + DMX_WRITE_REG(device_no, SEC_BUFF_NUMBER, i); + filter_number = DMX_READ_REG(device_no, + SEC_BUFF_NUMBER); + filter_number >>= 8; + if ((filter_number >= FILTER_COUNT) + /* >=31, do not handle this case */ + || ((filter_number < FILTER_COUNT) + && dmx->filter[filter_number].used)) + section_busy32 &= ~(1 << i); + } + if (section_busy32 & (dmx->smallsec.enable ? + 0x7FFFFFFF : + LARGE_SEC_BUFF_MASK)) { + /*Clear invalid buffers */ + DMX_WRITE_REG(device_no, + SEC_BUFF_READY, + section_busy32); + pr_error("clear invalid buffer 0x%x\n", + section_busy32); + } +#if 0 + section_busy32 = 0x7fffffff; + for (i = 0; i < SEC_BUF_BUSY_SIZE; i++) { + dmx->section_busy[i] = ( + (i == SEC_BUF_BUSY_SIZE - 1) ? + DMX_READ_REG(device_no, SEC_BUFF_BUSY) : + dmx->section_busy[i + 1]); + section_busy32 &= dmx->section_busy[i]; + } + + /*count the number of '1' bits */ + i = section_busy32; + i = (i & 0x55555555) + ((i & 0xaaaaaaaa) >> 1); + i = (i & 0x33333333) + ((i & 0xcccccccc) >> 2); + i = (i & 0x0f0f0f0f) + ((i & 0xf0f0f0f0) >> 4); + i = (i & 0x00ff00ff) + ((i & 0xff00ff00) >> 8); + i = (i & 0x0000ffff) + ((i & 0xffff0000) >> 16); + if (i > LARGE_SEC_BUFF_COUNT) { + /*too long some of the section + * buffers are being processed + */ + DMX_WRITE_REG(device_no, SEC_BUFF_READY, + section_busy32); + } +#endif + } + demux_int_status1 = + DMX_READ_REG(device_no, STB_INT_STATUS) & 0xfff7; + if (demux_int_status1 & (1 << TS_ERROR_PIN)) { + DMX_WRITE_REG(device_no, + STB_INT_STATUS, + (1 << TS_ERROR_PIN)); + } + } + +end: + spin_unlock_irqrestore(&dvb->slock, flags); +#ifdef ENABLE_SEC_BUFF_WATCHDOG + mod_timer(&dvb->watchdog_timer, + jiffies + msecs_to_jiffies(WATCHDOG_TIMER)); +#endif +} + +static inline int sec_filter_match(struct aml_dmx *dmx, struct aml_filter *f, + u8 *p) +{ + int b; + u8 neq = 0; + + if (!f->used || !dmx->channel[f->chan_id].used) + return 0; + + for (b = 0; b < FILTER_LEN; b++) { + u8 xor = p[b] ^ f->value[b]; + + if (xor & f->maskandmode[b]) + return 0; + + if (xor & f->maskandnotmode[b]) + neq = 1; + } + + if (f->neq && !neq) + return 0; + + return 1; +} + +static void trigger_crc_monitor(struct aml_dmx *dmx) +{ + if (!dmx->crc_check_time) { + dmx->crc_check_time = jiffies; + dmx->crc_check_count = 0; + } + + if (dmx->crc_check_count > 100) { + if (jiffies_to_msecs(jiffies - dmx->crc_check_time) <= 1000) { + struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv; + + pr_error("Too many crc fail (%d crc fail in %d ms)!\n", + dmx->crc_check_count, + jiffies_to_msecs(jiffies - dmx->crc_check_time) + ); + dmx_reset_dmx_hw_ex_unlock(dvb, dmx, 0); + } + dmx->crc_check_time = 0; + } + + dmx->crc_check_count++; +} +static int section_crc(struct aml_dmx *dmx, struct aml_filter *f, u8 *p) +{ + int sec_len = (((p[1] & 0xF) << 8) | p[2]) + 3; + struct dvb_demux_feed *feed = dmx->channel[f->chan_id].feed; + + if (feed->feed.sec.check_crc) { + struct dvb_demux *demux = feed->demux; + struct dmx_section_feed *sec = &feed->feed.sec; + int section_syntax_indicator; + + section_syntax_indicator = ((p[1] & 0x80) != 0); + sec->seclen = sec_len; + sec->crc_val = ~0; + if (demux->check_crc32(feed, p, sec_len)) { + pr_error("section CRC check failed!\n"); + +#if 0 +{ + int i; + + pr_error("sec:[%#lx:%#lx:%#lx-%#lx:%#lx:%#lx-%#lx:%#lx:%#lx]\n", + dmx->sec_cnt[0], dmx->sec_cnt_match[0], dmx->sec_cnt_crc_fail[0], + dmx->sec_cnt[1], dmx->sec_cnt_match[1], dmx->sec_cnt_crc_fail[1], + dmx->sec_cnt[2], dmx->sec_cnt_match[2], dmx->sec_cnt_crc_fail[2]); + pr_error("bad sec[%d]:\n", sec_len); + /* + * if (sec_len > 256) + * sec_len = 256; + * for (i = 0; i < sec_len; i++) { + * pr_err("%02x ", p[i]); + * if (!((i + 1) % 16)) + * pr_err("\n"); + * } + */ +} +#endif + trigger_crc_monitor(dmx); + return 0; + } +#if 0 + int i; + + for (i = 0; i < sec_len; i++) { + pr_dbg("%02x ", p[i]); + if (!((i + 1) % 16)) + pr_dbg("\n"); + } + pr_dbg("\nsection data\n"); +#endif + } + + return 1; +} + +static void section_notify(struct aml_dmx *dmx, struct aml_filter *f, u8 *p) +{ + int sec_len = (((p[1] & 0xF) << 8) | p[2]) + 3; + struct dvb_demux_feed *feed = dmx->channel[f->chan_id].feed; + + if (feed && feed->cb.sec) + feed->cb.sec(p, sec_len, NULL, 0, f->filter); +} + +static void hardware_match_section(struct aml_dmx *dmx, + u16 sec_num, u16 buf_num) +{ + u8 *p = (u8 *) dmx->sec_buf[buf_num].addr; + struct aml_filter *f; + int chid, i; + int need_crc = 1; + + if (sec_num >= FILTER_COUNT) { + pr_dbg("sec_num invalid: %d\n", sec_num); + return; + } + + dma_sync_single_for_cpu(dmx_get_dev(dmx), + dmx->sec_pages_map + (buf_num << 0x0c), + (1 << 0x0c), DMA_FROM_DEVICE); + + f = &dmx->filter[sec_num]; + chid = f->chan_id; + + dmx->sec_cnt[SEC_CNT_HW]++; + + for (i = 0; i < FILTER_COUNT; i++) { + f = &dmx->filter[i]; + if (f->chan_id != chid) + continue; + if (sec_filter_match(dmx, f, p)) { + if (need_crc) { + dmx->sec_cnt_match[SEC_CNT_HW]++; + if (!section_crc(dmx, f, p)) { + dmx->sec_cnt_crc_fail[SEC_CNT_HW]++; + return; + } + need_crc = 0; + } + section_notify(dmx, f, p); + } + } +} + +static void software_match_section(struct aml_dmx *dmx, u16 buf_num) +{ + u8 *p = (u8 *) dmx->sec_buf[buf_num].addr; + struct aml_filter *f, *fmatch = NULL; + int i, fid = -1; + + dma_sync_single_for_cpu(dmx_get_dev(dmx), + dmx->sec_pages_map + (buf_num << 0x0c), + (1 << 0x0c), DMA_FROM_DEVICE); + + dmx->sec_cnt[SEC_CNT_SW]++; + + for (i = 0; i < FILTER_COUNT; i++) { + f = &dmx->filter[i]; + + if (sec_filter_match(dmx, f, p)) { + pr_dbg("[software match]filter %d match, pid %d\n", + i, dmx->channel[f->chan_id].pid); + if (!fmatch) { + fmatch = f; + fid = i; + } else { + pr_error("[sw match]Muli-filter match this\n" + "section, will skip this section\n"); + return; + } + } + } + + if (fmatch) { + pr_dbg("[software match]dispatch\n" + "section to filter %d pid %d\n", + fid, dmx->channel[fmatch->chan_id].pid); + dmx->sec_cnt_match[SEC_CNT_SW]++; + if (section_crc(dmx, fmatch, p)) + section_notify(dmx, fmatch, p); + else + dmx->sec_cnt_crc_fail[SEC_CNT_SW]++; + } else { + pr_dbg("[software match]this section do not\n" + "match any filter!!!\n"); + } +} + + +static int _rbuf_write(struct dvb_ringbuffer *buf, const u8 *src, size_t len) +{ + ssize_t free; + + if (!len) + return 0; + if (!buf->data) + return 0; + + free = dvb_ringbuffer_free(buf); + if (len > free) { + pr_error("sf: buffer overflow\n"); + return -EOVERFLOW; + } + + return dvb_ringbuffer_write(buf, src, len); +} + +static int _rbuf_filter_pkts(struct dvb_ringbuffer *rb, + u8 *wrapbuf, + void (*swfilter_packets)(struct dvb_demux *demux, + const u8 *buf, + size_t count), + struct dvb_demux *demux) +{ + ssize_t len1 = 0; + ssize_t len2 = 0; + size_t off; + size_t count; + size_t size; + + if (debug_irq & 0x4) + dump(&rb->data[rb->pread], (debug_irq & 0xFFF00) >> 8); + + /* + * rb|====--------===[0x47]====| + * ^ ^ + * wr rd + */ + + len1 = rb->pwrite - rb->pread; + if (len1 < 0) { + len1 = rb->size - rb->pread; + len2 = rb->pwrite; + } + + for (off = 0; off < len1; off++) { + if (rb->data[rb->pread + off] == 0x47) + break; + } + + if (off) + pr_dbg_irq_sf("off ->|%zd\n", off); + + len1 -= off; + rb->pread = (rb->pread + off) % rb->size; + + count = len1 / 188; + if (count) { + pr_dbg_irq_sf("pkt >> 1[%zd<->%zd]\n", rb->pread, rb->pwrite); + swfilter_packets(demux, rb->data + rb->pread, count); + + size = count * 188; + len1 -= size; + rb->pread += size; + } + + if (len2 && len1 && ((len1 + len2) > 188)) { + pr_dbg_irq_sf("pkt >> 2[%zd<->%zd]\n", rb->pread, rb->pwrite); + size = 188 - len1; + memcpy(wrapbuf, rb->data + rb->pread, len1); + memcpy(wrapbuf + len1, rb->data, size); + swfilter_packets(demux, wrapbuf, 1); + rb->pread = size; + len2 -= size; + } + + if (len2) { + pr_dbg_irq_sf("pkt >> 3[%zd<->%zd]\n", rb->pread, rb->pwrite); + count = len2 / 188; + if (count) { + swfilter_packets(demux, rb->data + rb->pread, count); + rb->pread += count * 188; + } + } + return 0; +} + +static void smallsection_match_section(struct aml_dmx *dmx, u8 *p, u16 sec_num) +{ + struct aml_filter *f; + int chid, i; + int need_crc = 1; + + if (sec_num >= FILTER_COUNT) { + pr_dbg("sec_num invalid: %d\n", sec_num); + return; + } + + f = &dmx->filter[sec_num]; + chid = f->chan_id; + + dmx->sec_cnt[SEC_CNT_SS]++; + + for (i = 0; i < FILTER_COUNT; i++) { + f = &dmx->filter[i]; + if (f->chan_id != chid) + continue; + if (sec_filter_match(dmx, f, p)) { + if (need_crc) { + dmx->sec_cnt_match[SEC_CNT_SS]++; + if (!section_crc(dmx, f, p)) { + dmx->sec_cnt_crc_fail[SEC_CNT_SS]++; + return; + } + need_crc = 0; + } + section_notify(dmx, f, p); + } + } + +} +static void process_smallsection(struct aml_dmx *dmx) +{ + + u32 v, wr, rd; + u32 data32; + struct aml_smallsec *ss = &dmx->smallsec; + + v = DMX_READ_REG(dmx->id, DEMUX_SMALL_SEC_CTL); + wr = (v >> 8) & 0xff; + rd = (v >> 16) & 0xff; + + if (rd != wr) { + int n1 = wr - rd, + n2 = 0, + max = (ss->bufsize>>8); + int i; + u8 *p; + int sec_len; + + pr_dbg_irq_ss("secbuf[31] ctrl:0x%x\n", v); + + if (n1 < 0) { + n1 = max - rd; + n2 = wr; + } + if (n1) { + pr_dbg_irq_ss("n1:%d\n", n1); + dma_sync_single_for_cpu(dmx_get_dev(dmx), + ss->buf_map+(rd<<8), + n1<<8, + DMA_FROM_DEVICE); + for (i = 0; i < n1; i++) { + p = (u8 *)ss->buf+((rd+i)<<8); + sec_len = (((p[1] & 0xF) << 8) | p[2]) + 3; + smallsection_match_section(dmx, p, + *(p+sec_len+1)); + } + } + if (n2) { + pr_dbg_irq_ss("n2:%d\n", n2); + dma_sync_single_for_cpu(dmx_get_dev(dmx), + ss->buf_map, + n2<<8, + DMA_FROM_DEVICE); + for (i = 0; i < n2; i++) { + p = (u8 *)ss->buf+(i<<8); + sec_len = (((p[1] & 0xF) << 8) | p[2]) + 3; + smallsection_match_section(dmx, p, + *(p+sec_len+1)); + } + } + + rd = wr; + data32 = (DMX_READ_REG(dmx->id, DEMUX_SMALL_SEC_CTL) + & 0xff00ffff) + | (rd << 16); + DMX_WRITE_REG(dmx->id, DEMUX_SMALL_SEC_CTL, data32); + } +} + + +static void process_section(struct aml_dmx *dmx) +{ + u32 ready, i, sec_busy; + u16 sec_num; + + /*pr_dbg("section\n"); */ + ready = DMX_READ_REG(dmx->id, SEC_BUFF_READY); + if (ready) { +#ifdef USE_AHB_MODE + /* WRITE_ISA_REG(AHB_BRIDGE_CTRL1, + * READ_ISA_REG (AHB_BRIDGE_CTRL1) | (1 << 31)); + */ + /* WRITE_ISA_REG(AHB_BRIDGE_CTRL1, + * READ_ISA_REG (AHB_BRIDGE_CTRL1) & (~ (1 << 31))); + */ +#endif + + if ((ready & (1<<31)) && dmx->smallsec.enable) { + u32 v, wr, rd; + + v = DMX_READ_REG(dmx->id, DEMUX_SMALL_SEC_CTL); + wr = (v >> 8) & 0xff; + rd = (v >> 16) & 0xff; + if ((wr < rd) && (5 > (rd - wr))) + pr_error("warning: small ss buf [w%dr%d]\n", + wr, rd); + pr_dbg_irq_ss("ss>%x\n", + DMX_READ_REG(dmx->id, DEMUX_SMALL_SEC_CTL)); + process_smallsection(dmx); + /*tasklet_hi_schedule(&dmx->dmx_tasklet);*/ + /*tasklet_schedule(&dmx->dmx_tasklet);*/ + DMX_WRITE_REG(dmx->id, SEC_BUFF_READY, (1<<31)); + return; + } + + for (i = 0; i < SEC_BUF_COUNT; i++) { + + if (!(ready & (1 << i))) + continue; + + /* get section busy */ + sec_busy = DMX_READ_REG(dmx->id, SEC_BUFF_BUSY); + /* get filter number */ + DMX_WRITE_REG(dmx->id, SEC_BUFF_NUMBER, i); + sec_num = (DMX_READ_REG(dmx->id, SEC_BUFF_NUMBER) >> 8); + + /* + * sec_buf_watchdog_count dispatch: + * byte0 -- always busy=0 's watchdog count + * byte1 -- always busy=1 & filter_num=31 's + * watchdog count + */ + + /* sec_busy is not set, check busy=0 watchdog count */ + if (!(sec_busy & (1 << i))) { + /* clear other wd count of this buffer */ + dmx->sec_buf_watchdog_count[i] &= 0x000000ff; + dmx->sec_buf_watchdog_count[i] += 0x1; + pr_dbg("bit%d ready=1, busy=0,\n" + "sec_num=%d for %d times\n", + i, sec_num, + dmx->sec_buf_watchdog_count[i]); + if (dmx->sec_buf_watchdog_count[i] >= 5) { + pr_dbg("busy=0 reach the max count,\n" + "try software match.\n"); + software_match_section(dmx, i); + dmx->sec_buf_watchdog_count[i] = 0; + DMX_WRITE_REG(dmx->id, SEC_BUFF_READY, + (1 << i)); + } + continue; + } + + /* filter_num == 31 && busy == 1,check watchdog count */ + if (sec_num >= FILTER_COUNT) { + /* clear other wd count of this buffer */ + dmx->sec_buf_watchdog_count[i] &= 0x0000ff00; + dmx->sec_buf_watchdog_count[i] += 0x100; + pr_dbg("bit%d ready=1,busy=1,\n" + "sec_num=%d for %d times\n", + i, sec_num, + dmx->sec_buf_watchdog_count[i] >> 8); + if (dmx->sec_buf_watchdog_count[i] >= 0x500) { + pr_dbg("busy=1&filter_num=31\n" + " reach the max count, clear\n" + " the buf ready & busy!\n"); + software_match_section(dmx, i); + dmx->sec_buf_watchdog_count[i] = 0; + DMX_WRITE_REG(dmx->id, + SEC_BUFF_READY, + (1 << i)); + DMX_WRITE_REG(dmx->id, + SEC_BUFF_BUSY, + (1 << i)); + } + continue; + } + + /* now, ready & busy are both set and + * filter number is valid + */ + if (dmx->sec_buf_watchdog_count[i] != 0) + dmx->sec_buf_watchdog_count[i] = 0; + + /* process this section */ + hardware_match_section(dmx, sec_num, i); + + /* clear the ready & busy bit */ + DMX_WRITE_REG(dmx->id, SEC_BUFF_READY, (1 << i)); + DMX_WRITE_REG(dmx->id, SEC_BUFF_BUSY, (1 << i)); + } + } +} + +#ifdef NO_SUB +static void process_sub(struct aml_dmx *dmx) +{ + + u32 rd_ptr = 0; + + u32 wr_ptr = READ_MPEG_REG(PARSER_SUB_WP); + u32 start_ptr = READ_MPEG_REG(PARSER_SUB_START_PTR); + u32 end_ptr = READ_MPEG_REG(PARSER_SUB_END_PTR); + + u32 buffer1 = 0, buffer2 = 0; + unsigned char *buffer1_virt = 0, *buffer2_virt = 0; + u32 len1 = 0, len2 = 0; + + rd_ptr = READ_MPEG_REG(PARSER_SUB_RP); + if (!rd_ptr) + return; + if (rd_ptr > wr_ptr) { + len1 = end_ptr - rd_ptr + 8; + buffer1 = rd_ptr; + + len2 = wr_ptr - start_ptr; + buffer2 = start_ptr; + + rd_ptr = start_ptr + len2; + } else if (rd_ptr < wr_ptr) { + len1 = wr_ptr - rd_ptr; + buffer1 = rd_ptr; + rd_ptr += len1; + len2 = 0; + } else if (rd_ptr == wr_ptr) { + pr_dbg("sub no data\n"); + } + + if (buffer1) + buffer1_virt = phys_to_virt(buffer1); + if (buffer2) + buffer2_virt = phys_to_virt(buffer2); + + if (len1) + dma_sync_single_for_cpu(dmx_get_dev(dmx), + (dma_addr_t) buffer1, len1, + DMA_FROM_DEVICE); + if (len2) + dma_sync_single_for_cpu(dmx_get_dev(dmx), + (dma_addr_t) buffer2, len2, + DMA_FROM_DEVICE); + + if (dmx->channel[2].used) { + if (dmx->channel[2].feed && dmx->channel[2].feed->cb.ts) { + dmx->channel[2].feed->cb.ts(buffer1_virt, len1, + buffer2_virt, len2, + &dmx->channel[2].feed->feed.ts); + } + } + WRITE_MPEG_REG(PARSER_SUB_RP, rd_ptr); +} +#endif + +static void process_pes(struct aml_dmx *dmx) +{ + static long off, off_pre; + u8 *buffer1 = 0, *buffer2 = 0; + u8 *buffer1_phys = 0, *buffer2_phys = 0; + u32 len1 = 0, len2 = 0; + int i = 1; + + off = (DMX_READ_REG(dmx->id, OB_PES_WR_PTR) << 3); + + pr_dbg_irq_pes("[%d]WR:0x%x PES WR:0x%x\n", dmx->id, + DMX_READ_REG(dmx->id, OTHER_WR_PTR), + DMX_READ_REG(dmx->id, OB_PES_WR_PTR)); + buffer1 = (u8 *)(dmx->pes_pages + off_pre); + pr_dbg_irq_pes("[%d]PES WR[%02x %02x %02x %02x %02x %02x %02x %02x", + dmx->id, + buffer1[0], buffer1[1], buffer1[2], buffer1[3], + buffer1[4], buffer1[5], buffer1[6], buffer1[7]); + pr_dbg_irq_pes(" %02x %02x %02x %02x %02x %02x %02x %02x]\n", + buffer1[8], buffer1[9], buffer1[10], buffer1[11], + buffer1[12], buffer1[13], buffer1[14], buffer1[15]); + + if (off > off_pre) { + len1 = off-off_pre; + buffer1 = (unsigned char *)(dmx->pes_pages + off_pre); + } else if (off < off_pre) { + len1 = dmx->pes_buf_len-off_pre; + buffer1 = (unsigned char *)(dmx->pes_pages + off_pre); + len2 = off; + buffer2 = (unsigned char *)dmx->pes_pages; + } else if (off == off_pre) { + pr_dbg("pes no data\n"); + } + off_pre = off; + if (len1) { + buffer1_phys = (unsigned char *)virt_to_phys(buffer1); + dma_sync_single_for_cpu(dmx_get_dev(dmx), + (dma_addr_t)buffer1_phys, len1, DMA_FROM_DEVICE); + } + if (len2) { + buffer2_phys = (unsigned char *)virt_to_phys(buffer2); + dma_sync_single_for_cpu(dmx_get_dev(dmx), + (dma_addr_t)buffer2_phys, len2, DMA_FROM_DEVICE); + } + if (len1 || len2) { + struct aml_channel *ch; + + for (i = 0; i < CHANNEL_COUNT; i++) { + ch = &dmx->channel[i]; + if (ch->used && ch->feed + && (ch->feed->type == DMX_TYPE_TS)) { + if (ch->feed->ts_type & TS_PAYLOAD_ONLY) { + ch->feed->cb.ts(buffer1, + len1, buffer2, len2, + &ch->feed->feed.ts); + } + } + } + } +} + +static void process_om_read(struct aml_dmx *dmx) +{ + unsigned int i; + unsigned short om_cmd_status_data_0 = 0; + unsigned short om_cmd_status_data_1 = 0; +/* unsigned short om_cmd_status_data_2 = 0;*/ + unsigned short om_cmd_data_out = 0; + + om_cmd_status_data_0 = DMX_READ_REG(dmx->id, OM_CMD_STATUS); + om_cmd_status_data_1 = DMX_READ_REG(dmx->id, OM_CMD_DATA); +/* om_cmd_status_data_2 = DMX_READ_REG(dmx->id, OM_CMD_DATA2);*/ + + if (om_cmd_status_data_0 & 1) { + DMX_WRITE_REG(dmx->id, OM_DATA_RD_ADDR, + (1 << 15) | ((om_cmd_status_data_1 & 0xff) << 2)); + for (i = 0; i < (((om_cmd_status_data_1 >> 7) & 0x1fc) >> 1); + i++) { + om_cmd_data_out = DMX_READ_REG(dmx->id, OM_DATA_RD); + } + + om_cmd_data_out = DMX_READ_REG(dmx->id, OM_DATA_RD_ADDR); + DMX_WRITE_REG(dmx->id, OM_DATA_RD_ADDR, 0); + DMX_WRITE_REG(dmx->id, OM_CMD_STATUS, 1); + } +} + +static void dmx_irq_bh_handler(unsigned long arg) +{ + struct aml_dmx *dmx = (struct aml_dmx *)arg; +#if 0 + u32 status; + + status = DMX_READ_REG(dmx->id, STB_INT_STATUS); + + if (status) + DMX_WRITE_REG(dmx->id, STB_INT_STATUS, status); +#endif + process_smallsection(dmx); +} + +static irqreturn_t dmx_irq_handler(int irq_number, void *para) +{ + struct aml_dmx *dmx = (struct aml_dmx *)para; + struct aml_dvb *dvb = aml_get_dvb_device(); + u32 status; + unsigned long flags; + + spin_lock_irqsave(&dvb->slock, flags); + status = DMX_READ_REG(dmx->id, STB_INT_STATUS); + if (!status) + goto irq_handled; + + pr_dbg_irq("demux %d irq status: 0x%08x\n", dmx->id, status); + + if (status & (1 << SECTION_BUFFER_READY)) + process_section(dmx); +#ifdef NO_SUB + if (status & (1 << SUB_PES_READY)) { + /*If the subtitle is set by tsdemux, + *do not parser in demux driver. + */ + if (dmx->sub_chan == -1) + process_sub(dmx); + } +#endif + if (status & (1 << OTHER_PES_READY)) + process_pes(dmx); + if (status & (1 << OM_CMD_READ_PENDING)) + process_om_read(dmx); + /* + *if (status & (1 << DUPLICATED_PACKET)) { + *} + *if (status & (1 << DIS_CONTINUITY_PACKET)) { + *} + *if (status & (1 << VIDEO_SPLICING_POINT)) { + *} + *if (status & (1 << AUDIO_SPLICING_POINT)) { + *} + */ + if (status & (1 << TS_ERROR_PIN)) + pr_error("TS_ERROR_PIN\n"); + + if (status & (1 << NEW_PDTS_READY)) { + u32 pdts_status = DMX_READ_REG(dmx->id, STB_PTS_DTS_STATUS); + + if (pdts_status & (1 << VIDEO_PTS_READY)) { + video_pts = DMX_READ_REG(dmx->id, VIDEO_PTS_DEMUX); + if (!first_video_pts + || 0 > (int)(video_pts - first_video_pts)) + first_video_pts = video_pts; + } + + if (pdts_status & (1 << AUDIO_PTS_READY)) { + audio_pts = DMX_READ_REG(dmx->id, AUDIO_PTS_DEMUX); + if (!first_audio_pts + || 0 > (int)(audio_pts - first_audio_pts)) + first_audio_pts = audio_pts; + } + } + + if (dmx->irq_handler) + dmx->irq_handler(dmx->dmx_irq, (void *)(long)dmx->id); + + DMX_WRITE_REG(dmx->id, STB_INT_STATUS, status); + + /*tasklet_schedule(&dmx->dmx_tasklet);*/ + + { + if (!dmx->int_check_time) { + dmx->int_check_time = jiffies; + dmx->int_check_count = 0; + } + + if (jiffies_to_msecs(jiffies - dmx->int_check_time) >= 100 + || dmx->int_check_count > 1000) { + if (dmx->int_check_count > 1000) { + struct aml_dvb *dvb = + (struct aml_dvb *)dmx->demux.priv; + pr_error("Too many irq (%d irq in %d ms)!\n", + dmx->int_check_count, + jiffies_to_msecs(jiffies - + dmx->int_check_time)); + if (dmx->fe && !dmx->in_tune) + DMX_WRITE_REG(dmx->id, STB_INT_MASK, 0); + dmx_reset_hw_ex(dvb, 0); + } + dmx->int_check_time = 0; + } + + dmx->int_check_count++; + + if (dmx->in_tune) { + dmx->error_check++; + if (dmx->error_check > 200) + DMX_WRITE_REG(dmx->id, STB_INT_MASK, 0); + } + } + +irq_handled: + spin_unlock_irqrestore(&dvb->slock, flags); + return IRQ_HANDLED; +} + +static inline int dmx_get_order(unsigned long size) +{ + int order; + + order = -1; + do { + size >>= 1; + order++; + } while (size); + + return order; +} + +static void dvr_process_channel(struct aml_asyncfifo *afifo, + struct aml_channel *channel, + u32 total, u32 size, + struct aml_swfilter *sf) +{ + int cnt; + int ret = 0; + + if (afifo->buf_read > afifo->buf_toggle) { + cnt = total - afifo->buf_read; + dma_sync_single_for_cpu(asyncfifo_get_dev(afifo), + afifo->pages_map+afifo->buf_read*size, + cnt*size, + DMA_FROM_DEVICE); + if (sf) + ret = _rbuf_write(&sf->rbuf, + (u8 *)afifo->pages+afifo->buf_read*size, + cnt*size); + else + channel->dvr_feed->cb.ts( + (u8 *)afifo->pages+afifo->buf_read*size, + cnt*size, NULL, 0, + &channel->dvr_feed->feed.ts); + afifo->buf_read = 0; + } + + if (afifo->buf_toggle > afifo->buf_read) { + cnt = afifo->buf_toggle - afifo->buf_read; + dma_sync_single_for_cpu(asyncfifo_get_dev(afifo), + afifo->pages_map+afifo->buf_read*size, + cnt*size, + DMA_FROM_DEVICE); + if (sf) { + if (ret >= 0) + ret = _rbuf_write(&sf->rbuf, + (u8 *)afifo->pages+afifo->buf_read*size, + cnt*size); + } else + channel->dvr_feed->cb.ts( + (u8 *)afifo->pages+afifo->buf_read*size, + cnt*size, NULL, 0, + &channel->dvr_feed->feed.ts); + afifo->buf_read = afifo->buf_toggle; + } + + if (sf && ret > 0) { + _rbuf_filter_pkts(&sf->rbuf, sf->wrapbuf, + dvb_dmx_swfilter_packets, + channel->dvr_feed->demux); + } else if (sf && ret <= 0) + pr_error("sf rbuf write error[%d]\n", ret); + else + pr_dbg_irq_dvr("write data to dvr\n"); +} + +static void dvr_irq_bh_handler(unsigned long arg) +{ + struct aml_asyncfifo *afifo = (struct aml_asyncfifo *)arg; + struct aml_dvb *dvb = afifo->dvb; + struct aml_dmx *dmx; + u32 size, total; + int i, factor; + unsigned long flags; + + pr_dbg_irq_dvr("async fifo %d irq\n", afifo->id); + + spin_lock_irqsave(&dvb->slock, flags); + + if (dvb && afifo->source >= AM_DMX_0 && afifo->source < AM_DMX_MAX) { + dmx = &dvb->dmx[afifo->source]; + if (dmx->init && dmx->record) { + struct aml_swfilter *sf = &dvb->swfilter; + int issf = 0; + + total = afifo->buf_len / afifo->flush_size; + factor = dmx_get_order(total); + size = afifo->buf_len >> factor; + + if (sf->user && (sf->afifo == afifo)) + issf = 1; + + for (i = 0; i < CHANNEL_COUNT; i++) { + if (dmx->channel[i].used + && dmx->channel[i].dvr_feed) { + dvr_process_channel(afifo, + &dmx->channel[i], + total, + size, + issf?sf:NULL); + break; + } + } + + } + } + spin_unlock_irqrestore(&dvb->slock, flags); +} + +static irqreturn_t dvr_irq_handler(int irq_number, void *para) +{ + struct aml_asyncfifo *afifo = (struct aml_asyncfifo *)para; + int factor = dmx_get_order(afifo->buf_len / afifo->flush_size); + + afifo->buf_toggle++; + afifo->buf_toggle %= (1 << factor); + tasklet_schedule(&afifo->asyncfifo_tasklet); + return IRQ_HANDLED; +} + +/*Enable the STB*/ +static void stb_enable(struct aml_dvb *dvb) +{ + int out_src, des_in, en_des, fec_clk, hiu, dec_clk_en; + int src, tso_src, i; + u32 fec_s0, fec_s1; + u32 invert0, invert1; + u32 data; + + switch (dvb->stb_source) { + case AM_TS_SRC_DMX0: + src = dvb->dmx[0].source; + break; + case AM_TS_SRC_DMX1: + src = dvb->dmx[1].source; + break; + case AM_TS_SRC_DMX2: + src = dvb->dmx[2].source; + break; + default: + src = dvb->stb_source; + break; + } + + switch (src) { + case AM_TS_SRC_TS0: + fec_clk = tsfile_clkdiv; + hiu = 0; + break; + case AM_TS_SRC_TS1: + fec_clk = tsfile_clkdiv; + hiu = 0; + break; + case AM_TS_SRC_TS2: + fec_clk = tsfile_clkdiv; + hiu = 0; + break; + case AM_TS_SRC_S_TS0: + fec_clk = tsfile_clkdiv; + hiu = 0; + break; + case AM_TS_SRC_S_TS1: + fec_clk = tsfile_clkdiv; + hiu = 0; + break; + case AM_TS_SRC_S_TS2: + fec_clk = tsfile_clkdiv; + hiu = 0; + break; + case AM_TS_SRC_HIU: + fec_clk = tsfile_clkdiv; + hiu = 1; + break; + default: + fec_clk = 0; + hiu = 0; + break; + } + + switch (dvb->dsc[0].source) { + case AM_TS_SRC_DMX0: + des_in = 0; + en_des = 1; + dec_clk_en = 1; + break; + case AM_TS_SRC_DMX1: + des_in = 1; + en_des = 1; + dec_clk_en = 1; + break; + case AM_TS_SRC_DMX2: + des_in = 2; + en_des = 1; + dec_clk_en = 1; + break; + default: + des_in = 0; + en_des = 0; + dec_clk_en = 0; + break; + } + + switch (dvb->tso_source) { + case AM_TS_SRC_DMX0: + tso_src = dvb->dmx[0].source; + break; + case AM_TS_SRC_DMX1: + tso_src = dvb->dmx[1].source; + break; + case AM_TS_SRC_DMX2: + tso_src = dvb->dmx[2].source; + break; + default: + tso_src = dvb->tso_source; + break; + } + + switch (tso_src) { + case AM_TS_SRC_TS0: + out_src = 0; + break; + case AM_TS_SRC_TS1: + out_src = 1; + break; + case AM_TS_SRC_TS2: + out_src = 2; + break; + case AM_TS_SRC_S_TS0: + case AM_TS_SRC_S_TS1: + case AM_TS_SRC_S_TS2: + out_src = 6; + break; + case AM_TS_SRC_HIU: + out_src = 7; + break; + default: + out_src = 0; + break; + } + + pr_dbg("[stb]src: %d, dsc1in: %d, tso: %d\n", src, des_in, out_src); + + fec_s0 = 0; + fec_s1 = 0; + invert0 = 0; + invert1 = 0; + + for (i = 0; i < TS_IN_COUNT; i++) { + if (dvb->ts[i].s2p_id == 0) + fec_s0 = i; + else if (dvb->ts[i].s2p_id == 1) + fec_s1 = i; + } + + invert0 = dvb->s2p[0].invert; + invert1 = dvb->s2p[1].invert; + + WRITE_MPEG_REG(STB_TOP_CONFIG, + (invert1 << INVERT_S2P1_FEC_CLK) | + (fec_s1 << S2P1_FEC_SERIAL_SEL) | + (out_src << TS_OUTPUT_SOURCE) | + (des_in << DES_INPUT_SEL) | + (en_des << ENABLE_DES_PL) | + (dec_clk_en << ENABLE_DES_PL_CLK) | + (invert0 << INVERT_S2P0_FEC_CLK) | + (fec_s0 << S2P0_FEC_SERIAL_SEL)); + + if (dvb->reset_flag) + hiu = 0; + /* invert ts out clk,add ci model need add this*/ + if (dvb->ts_out_invert) { + /*printk("ts out invert ---\r\n");*/ + data = READ_MPEG_REG(TS_TOP_CONFIG); + data |= 1 << TS_OUT_CLK_INVERT; + WRITE_MPEG_REG(TS_TOP_CONFIG, data); + } + /* invert ts out clk end */ + WRITE_MPEG_REG(TS_FILE_CONFIG, + (demux_skipbyte << 16) | + (6 << DES_OUT_DLY) | + (3 << TRANSPORT_SCRAMBLING_CONTROL_ODD) | + (3 << TRANSPORT_SCRAMBLING_CONTROL_ODD_2) | + (hiu << TS_HIU_ENABLE) | (fec_clk << FEC_FILE_CLK_DIV)); +} + +int dsc_set_pid(struct aml_dsc_channel *ch, int pid) +{ + struct aml_dsc *dsc = ch->dsc; + int is_dsc2 = (dsc->id == 1) ? 1 : 0; + u32 data; + + WRITE_MPEG_REG(TS_PL_PID_INDEX, + ((ch->id & 0x0f) >> 1)+(is_dsc2 ? 4 : 0)); + data = READ_MPEG_REG(TS_PL_PID_DATA); + if (ch->id & 1) { + data &= 0xFFFF0000; + data |= pid & 0x1fff; + if (!ch->used) + data |= 1 << PID_MATCH_DISABLE_LOW; + } else { + data &= 0xFFFF; + data |= (pid & 0x1fff) << 16; + if (!ch->used) + data |= 1 << PID_MATCH_DISABLE_HIGH; + } + WRITE_MPEG_REG(TS_PL_PID_INDEX, + ((ch->id & 0x0f) >> 1)+(is_dsc2 ? 4 : 0)); + WRITE_MPEG_REG(TS_PL_PID_DATA, data); + WRITE_MPEG_REG(TS_PL_PID_INDEX, 0); + + if (ch->used) + pr_dbg("set DSC %d ch %d PID %d\n", dsc->id, ch->id, pid); + else + pr_dbg("disable DSC %d ch %d\n", dsc->id, ch->id); + return 0; +} + +int dsc_set_key(struct aml_dsc_channel *ch, int flags, enum ca_cw_type type, + u8 *key) +{ + /*struct aml_dsc *dsc = ch->dsc;*/ + int ret = -1; + + if (type == CA_CW_DVB_CSA_EVEN || type == CA_CW_DVB_CSA_ODD) { + ret = dsc_set_csa_key(ch, flags, type, key); + if (ret != 0) + goto END; + /* Different with old mode, do change */ + if (ch->work_mode == CIPLUS_MODE || ch->work_mode == -1) { + if (ch->work_mode == -1) + pr_error("Dsc set output and enable\n"); + else + pr_error("Dsc set output change from ciplus\n"); + aml_ci_plus_disable_output(); + ch->aes_mode = AES_ECB_MODE; + /*aml_ci_plus_disable();*/ + ch->work_mode = DVBCSA_MODE; + } + } else if (type == CA_CW_AES_EVEN || + type == CA_CW_AES_ODD || + type == CA_CW_AES_EVEN_IV || + type == CA_CW_AES_ODD_IV) { + ret = dsc_set_aes_key(ch, flags, type, key); + if (ret != 0) + goto END; + /* Different with old mode, do change */ + if (ch->work_mode == DVBCSA_MODE || ch->work_mode == -1) { + if (ch->work_mode == -1) + pr_error("Ciplus set output and enable\n"); + else + pr_error("Ciplus set output change from dsc\n"); + am_ci_plus_set_output(ch); + aml_ci_plus_enable(); + ch->work_mode = CIPLUS_MODE; + } + } +END: + return ret; +} + +static int dsc_set_csa_key(struct aml_dsc_channel *ch, int flags, + enum ca_cw_type type, u8 *key) +{ + struct aml_dsc *dsc = ch->dsc; + int is_dsc2 = (dsc->id == 1) ? 1 : 0; + u16 k0, k1, k2, k3; + u32 key0, key1; + int reg; /*not sure if reg readable*/ +/* u32 data; + * u32 pid = 0x1fff; + */ + int from_kl = flags & CA_CW_FROM_KL; +/* int pid = ch->pid; */ + + if (from_kl) { + k0 = k1 = k2 = k3 = 0; +/* ch->used = 1; + * dsc_set_pid(ch, pid); + */ + /*dummy write to check if kl not working*/ + key0 = key1 = 0; + WRITE_MPEG_REG(COMM_DESC_KEY0, key0); + WRITE_MPEG_REG(COMM_DESC_KEY1, key1); + + /*tdes? :*/ + if (get_cpu_type() == MESON_CPU_MAJOR_ID_GXBB) { + WRITE_MPEG_REG(COMM_DESC_KEY_RW, +/* (type ? (1 << 6) : (1 << 5)) | */ + ((1 << 5)) | + ((ch->id + type * DSC_COUNT)+ + (is_dsc2 ? 16 : 0))); + } + if (get_cpu_type() == MESON_CPU_MAJOR_ID_GXL) { + WRITE_MPEG_REG(COMM_DESC_KEY_RW, + (type ? (1 << 6) : (1 << 5)) | (1<<7) | + ((ch->id + type * DSC_COUNT)+ + (is_dsc2 ? 16 : 0))); + } + reg = (type ? (1 << 6) : (1 << 5)) | + ((ch->id + type * DSC_COUNT)+ + (is_dsc2 ? 16 : 0)); + } else { + k0 = (key[0] << 8) | key[1]; + k1 = (key[2] << 8) | key[3]; + k2 = (key[4] << 8) | key[5]; + k3 = (key[6] << 8) | key[7]; + + key0 = (k0 << 16) | k1; + key1 = (k2 << 16) | k3; + WRITE_MPEG_REG(COMM_DESC_KEY0, key0); + WRITE_MPEG_REG(COMM_DESC_KEY1, key1); + WRITE_MPEG_REG(COMM_DESC_KEY_RW, + (ch->id + type * DSC_COUNT)+(is_dsc2 ? 16 : 0)); + reg = (ch->id + type * DSC_COUNT)+(is_dsc2 ? 16 : 0); + } + + return 0; +} + +/************************* AES DESC************************************/ +/*#define STB_TOP_CONFIG 0x16f0 +#define CIPLUS_KEY0 0x16f8 +#define CIPLUS_KEY1 0x16f9 +#define CIPLUS_KEY2 0x16fa +#define CIPLUS_KEY3 0x16fb +#define CIPLUS_KEY_WR 0x16fc +#define CIPLUS_CONFIG 0x16fd +#define CIPLUS_ENDIAN 0x16fe*/ + +#define ENABLE_DEC_PL 7 +#define ENABLE_DES_PL_CLK 15 +#define CIPLUS_OUT_SEL 28 +#define CIPLUS_IN_SEL 26 + +#define KEY_WR_AES_IV_B 5 +#define KEY_WR_AES_IV_A 4 +#define KEY_WR_AES_B 3 +#define KEY_WR_AES_A 2 + +#define CNTL_ENABLE 3 +#define AES_CBC_DISABLE 2 +#define AES_EN 1 +#define DES_EN 0 + +#define AES_MSG_OUT_ENDIAN 24 +#define AES_MSG_IN_ENDIAN 20 +#define AES_KEY_ENDIAN 16 + + +#if 0 +static void aml_ci_plus_set_stb(void) +{ + unsigned int data; + /* data = READ_MPEG_REG(FEC_INPUT_CONTROL); */ + /* data |= (0<id << 9) | (1<id << 9) | (1<dsc; + u32 data; + + if (dsc->id != 0) { + pr_error("Ciplus set output can only work at dsc0 device\n"); + return; + } + + if (ciplus_out_auto_mode == 1) { + data = READ_MPEG_REG(STB_TOP_CONFIG); + switch (dsc->source) { + case AM_TS_SRC_DMX0: + data |= 1 << CIPLUS_OUT_SEL; + ciplus_out_sel = 1; + break; + case AM_TS_SRC_DMX1: + data |= 2 << CIPLUS_OUT_SEL; + ciplus_out_sel = 2; + break; + case AM_TS_SRC_DMX2: + data |= 4 << CIPLUS_OUT_SEL; + ciplus_out_sel = 4; + break; + default: + pr_error("ciplus auto set source failed\n"); + return; + } + WRITE_MPEG_REG(STB_TOP_CONFIG, data); + } else if (ciplus_out_sel >= 0 && ciplus_out_sel <= 7) { + pr_error("Set output selection %d\n", ciplus_out_sel); + data = READ_MPEG_REG(STB_TOP_CONFIG); + data &= ~(7<aes_mode == -1) + ch->aes_mode = AES_ECB_MODE; + } else if (type == CA_CW_AES_ODD) { + aes_a = 1; + aes_b = 0; + if (ch->aes_mode == -1) + ch->aes_mode = AES_ECB_MODE; + } else if ((type == CA_CW_AES_EVEN_IV) + || (type == CA_CW_AES_ODD_IV)) { + aml_ci_plus_set_iv(ch, type, key); + ch->aes_mode = AES_CBC_MODE; + return 0; + } + + /* Set endian and cbc/ecb mode */ + if (from_kl) + aml_ci_plus_config(7, ch->aes_mode); + else + aml_ci_plus_config(0, ch->aes_mode); + + /* Write keys to work */ + if (from_kl) { + k0 = k1 = k2 = k3 = 0; + +/* dummy write to + * check if kl not working + */ + WRITE_MPEG_REG(CIPLUS_KEY0, k0); + WRITE_MPEG_REG(CIPLUS_KEY1, k1); + WRITE_MPEG_REG(CIPLUS_KEY2, k2); + WRITE_MPEG_REG(CIPLUS_KEY3, k3); + WRITE_MPEG_REG(CIPLUS_KEY_WR, + (ch->id << 9) | + +/* bit[11:9] the key of index, + * need match PID index + */ + (0 << 8) | /* bit[8] des key use cw[127:64]*/ + (0 << 7) | /* bit[7] aes iv use cw*/ + (1 << 6) | /* bit[6] aes/des key use cw*/ + (0 << 5) | /* bit[5] write AES IV B value*/ + (0 << 4) | /* bit[4] write AES IV A value*/ + (aes_b << 3) | /* bit[3] write AES B key*/ + (aes_a << 2) | /* bit[2] write AES A key*/ + (0 << 1) | /* bit[1] write DES B key*/ + (0)); /* bit[0] write DES A key*/ + } else { + + k3 = (key[0] << 24) | (key[1] << 16) | (key[2] << 8) | key[3]; + k2 = (key[4] << 24) | (key[5] << 16) | (key[6] << 8) | key[7]; + k1 = (key[8] << 24) | (key[9] << 16) | + (key[10] << 8) | key[11]; + k0 = (key[12] << 24) | (key[13] << 16) | + (key[14] << 8) | key[15]; + + WRITE_MPEG_REG(CIPLUS_KEY0, k0); + WRITE_MPEG_REG(CIPLUS_KEY1, k1); + WRITE_MPEG_REG(CIPLUS_KEY2, k2); + WRITE_MPEG_REG(CIPLUS_KEY3, k3); + index_flag = (ch->id << 9); + if (type == 2) { /* even */ + WRITE_MPEG_REG(CIPLUS_KEY_WR, + index_flag | (1<id == 0) { + WRITE_MPEG_REG(STB_TOP_CONFIG, + READ_MPEG_REG(STB_TOP_CONFIG) & + ~((0x11 << DES_INPUT_SEL)| + (1 << ENABLE_DES_PL)| + (1 << ENABLE_DES_PL_CLK))); + } else if (dsc->id == 1) { + WRITE_MPEG_REG(COMM_DESC_2_CTL, 0); + } + return 0; +} + +/*Set section buffer*/ +static int dmx_alloc_sec_buffer(struct aml_dmx *dmx) +{ + unsigned long base; + unsigned long grp_addr[SEC_BUF_GRP_COUNT]; + int grp_len[SEC_BUF_GRP_COUNT]; + int i; + + if (dmx->sec_pages) + return 0; + + grp_len[0] = (1 << SEC_GRP_LEN_0) * 8; + grp_len[1] = (1 << SEC_GRP_LEN_1) * 8; + grp_len[2] = (1 << SEC_GRP_LEN_2) * 8; + grp_len[3] = (1 << SEC_GRP_LEN_3) * 8; + + dmx->sec_total_len = grp_len[0] + grp_len[1] + grp_len[2] + grp_len[3]; + dmx->sec_pages = + __get_free_pages(GFP_KERNEL, get_order(dmx->sec_total_len)); + if (!dmx->sec_pages) { + pr_error("cannot allocate section buffer %d bytes %d order\n", + dmx->sec_total_len, get_order(dmx->sec_total_len)); + return -1; + } + dmx->sec_pages_map = + dma_map_single(dmx_get_dev(dmx), (void *)dmx->sec_pages, + dmx->sec_total_len, DMA_FROM_DEVICE); + + grp_addr[0] = dmx->sec_pages_map; + + grp_addr[1] = grp_addr[0] + grp_len[0]; + grp_addr[2] = grp_addr[1] + grp_len[1]; + grp_addr[3] = grp_addr[2] + grp_len[2]; + + dmx->sec_buf[0].addr = dmx->sec_pages; + dmx->sec_buf[0].len = grp_len[0] / 8; + + for (i = 1; i < SEC_BUF_COUNT; i++) { + dmx->sec_buf[i].addr = + dmx->sec_buf[i - 1].addr + dmx->sec_buf[i - 1].len; + dmx->sec_buf[i].len = grp_len[i / 8] / 8; + } + + base = grp_addr[0] & 0xFFFF0000; + DMX_WRITE_REG(dmx->id, SEC_BUFF_BASE, base >> 16); + DMX_WRITE_REG(dmx->id, SEC_BUFF_01_START, + (((grp_addr[0] - base) >> 8) << 16) | + ((grp_addr[1] - base) >> 8)); + DMX_WRITE_REG(dmx->id, SEC_BUFF_23_START, + (((grp_addr[2] - base) >> 8) << 16) | + ((grp_addr[3] - base) >> 8)); + DMX_WRITE_REG(dmx->id, SEC_BUFF_SIZE, + SEC_GRP_LEN_0 | + (SEC_GRP_LEN_1 << 4) | + (SEC_GRP_LEN_2 << 8) | + (SEC_GRP_LEN_3 << 12)); + + return 0; +} + +#ifdef NO_SUB +/*Set subtitle buffer*/ +static int dmx_alloc_sub_buffer(struct aml_dmx *dmx) +{ + unsigned long addr; + + if (dmx->sub_pages) + return 0; + + dmx->sub_buf_len = 64 * 1024; + dmx->sub_pages = + __get_free_pages(GFP_KERNEL, get_order(dmx->sub_buf_len)); + if (!dmx->sub_pages) { + pr_error("cannot allocate subtitle buffer\n"); + return -1; + } + dmx->sub_pages_map = + dma_map_single(dmx_get_dev(dmx), (void *)dmx->sub_pages, + dmx->sub_buf_len, DMA_FROM_DEVICE); + + addr = virt_to_phys((void *)dmx->sub_pages); + DMX_WRITE_REG(dmx->id, SB_START, addr >> 12); + DMX_WRITE_REG(dmx->id, SB_LAST_ADDR, (dmx->sub_buf_len >> 3) - 1); + return 0; +} +#endif /*NO_SUB */ + +/*Set PES buffer*/ +static int dmx_alloc_pes_buffer(struct aml_dmx *dmx) +{ + unsigned long addr; + + if (dmx->pes_pages) + return 0; + + dmx->pes_buf_len = 64 * 1024; + dmx->pes_pages = + __get_free_pages(GFP_KERNEL, get_order(dmx->pes_buf_len)); + if (!dmx->pes_pages) { + pr_error("cannot allocate pes buffer\n"); + return -1; + } + dmx->pes_pages_map = + dma_map_single(dmx_get_dev(dmx), (void *)dmx->pes_pages, + dmx->pes_buf_len, DMA_FROM_DEVICE); + + addr = virt_to_phys((void *)dmx->pes_pages); + DMX_WRITE_REG(dmx->id, OB_START, addr >> 12); + DMX_WRITE_REG(dmx->id, OB_LAST_ADDR, (dmx->pes_buf_len >> 3) - 1); + return 0; +} + +/*Allocate ASYNC FIFO Buffer*/ +static unsigned long asyncfifo_alloc_buffer(int len) +{ + unsigned long pages = __get_free_pages(GFP_KERNEL, get_order(len)); + + if (!pages) { + pr_error("cannot allocate async fifo buffer\n"); + return 0; + } + return pages; +} +static void asyncfifo_free_buffer(unsigned long buf, int len) +{ + free_pages(buf, get_order(len)); +} + +static int asyncfifo_set_buffer(struct aml_asyncfifo *afifo, + int len, unsigned long buf) +{ + if (afifo->pages) + return -1; + + afifo->buf_toggle = 0; + afifo->buf_read = 0; + afifo->buf_len = len; + pr_error("async fifo %d buf size %d, flush size %d\n", + afifo->id, afifo->buf_len, afifo->flush_size); + + if ((afifo->flush_size <= 0) + || (afifo->flush_size > (afifo->buf_len>>1))) { + afifo->flush_size = afifo->buf_len>>1; + } else if (afifo->flush_size < 128) { + afifo->flush_size = 128; + } else { + int fsize; + + for (fsize = 128; fsize < (afifo->buf_len>>1); fsize <<= 1) { + if (fsize >= afifo->flush_size) + break; + } + + afifo->flush_size = fsize; + } + + afifo->pages = buf; + if (!afifo->pages) + return -1; + + afifo->pages_map = dma_map_single(asyncfifo_get_dev(afifo), + (void *)afifo->pages, afifo->buf_len, DMA_FROM_DEVICE); + + return 0; +} +static void asyncfifo_put_buffer(struct aml_asyncfifo *afifo) +{ + if (afifo->pages) { + dma_unmap_single(asyncfifo_get_dev(afifo), + afifo->pages_map, afifo->buf_len, DMA_FROM_DEVICE); + asyncfifo_free_buffer(afifo->pages, afifo->buf_len); + afifo->pages_map = 0; + afifo->pages = 0; + } +} + +int async_fifo_init(struct aml_asyncfifo *afifo, int initirq, + int buf_len, unsigned long buf) +{ + int ret = 0; + int irq; + + if (afifo->init) + return -1; + + afifo->source = AM_DMX_MAX; + afifo->pages = 0; + afifo->buf_toggle = 0; + afifo->buf_read = 0; + afifo->buf_len = 0; + + if (afifo->asyncfifo_irq == -1) { + pr_error("no irq for ASYNC_FIFO%d\n", afifo->id); + /*Do not return error*/ + return -1; + } + + tasklet_init(&afifo->asyncfifo_tasklet, + dvr_irq_bh_handler, (unsigned long)afifo); + if (initirq) + irq = request_irq(afifo->asyncfifo_irq, dvr_irq_handler, + IRQF_SHARED|IRQF_TRIGGER_RISING, + "dvr irq", afifo); + else + enable_irq(afifo->asyncfifo_irq); + + /*alloc buffer*/ + ret = asyncfifo_set_buffer(afifo, buf_len, buf); + + afifo->init = 1; + + return ret; +} + +int async_fifo_deinit(struct aml_asyncfifo *afifo, int freeirq) +{ + if (!afifo->init) + return 0; + + CLEAR_ASYNC_FIFO_REG_MASK(afifo->id, REG1, 1 << ASYNC_FIFO_FLUSH_EN); + CLEAR_ASYNC_FIFO_REG_MASK(afifo->id, REG2, 1 << ASYNC_FIFO_FILL_EN); + + asyncfifo_put_buffer(afifo); + + afifo->source = AM_DMX_MAX; + afifo->buf_toggle = 0; + afifo->buf_read = 0; + afifo->buf_len = 0; + + if (afifo->asyncfifo_irq != -1) { + if (freeirq) + free_irq(afifo->asyncfifo_irq, afifo); + else + disable_irq(afifo->asyncfifo_irq); + } + tasklet_kill(&afifo->asyncfifo_tasklet); + + afifo->init = 0; + + return 0; +} + +static int _dmx_smallsec_enable(struct aml_smallsec *ss, int bufsize) +{ + if (!ss->buf) { + + ss->buf = __get_free_pages(GFP_KERNEL, + get_order(bufsize)); + if (!ss->buf) { + pr_error("cannot allocate smallsec buffer\n" + "%d bytes %d order\n", + bufsize, get_order(bufsize)); + return -1; + } + ss->buf_map = dma_map_single(dmx_get_dev(ss->dmx), + (void *)ss->buf, + bufsize, DMA_FROM_DEVICE); + } + + DMX_WRITE_REG(ss->dmx->id, DEMUX_SMALL_SEC_ADDR, + ss->buf_map); + DMX_WRITE_REG(ss->dmx->id, DEMUX_SMALL_SEC_CTL, + ((((bufsize>>8)-1)&0xff)<<24) | + (1<<1) |/*enable reset the wr ptr*/ + (1<<0)); + + ss->bufsize = bufsize; + ss->enable = 1; + + pr_inf("demux%d smallsec buf start: %lx, size: %d\n", + ss->dmx->id, ss->buf, ss->bufsize); + return 0; +} + +static int _dmx_smallsec_disable(struct aml_smallsec *ss) +{ + DMX_WRITE_REG(ss->dmx->id, DEMUX_SMALL_SEC_CTL, 0); + if (ss->buf) { + dma_unmap_single(dmx_get_dev(ss->dmx), ss->buf_map, + ss->bufsize, DMA_FROM_DEVICE); + free_pages(ss->buf, get_order(ss->bufsize)); + ss->buf = 0; + ss->buf_map = 0; + } + ss->enable = 0; + pr_inf("demux%d smallsec buf disable\n", ss->dmx->id); + return 0; +} + +static int dmx_smallsec_set(struct aml_smallsec *ss, int enable, int bufsize, + int force) +{ + if (!enable) {/*disable*/ + + if (ss->enable || force) + _dmx_smallsec_disable(ss); + + } else {/*enable*/ + + if (bufsize < 0) + bufsize = SS_BUFSIZE_DEF; + else if (!bufsize) + bufsize = ss->bufsize; + else { + /*unit:FF max:FF00*/ + bufsize &= ~0xFF; + bufsize &= 0x1FF00; + } + + if ((ss->enable && (bufsize != ss->bufsize)) || force) + _dmx_smallsec_disable(ss); + + if (!ss->enable) + _dmx_smallsec_enable(ss, bufsize); + } + + return 0; +} + +static int _dmx_timeout_enable(struct aml_dmxtimeout *dto, int timeout, + int ch_dis, int match) +{ + + DMX_WRITE_REG(dto->dmx->id, DEMUX_INPUT_TIMEOUT_C, ch_dis); + DMX_WRITE_REG(dto->dmx->id, DEMUX_INPUT_TIMEOUT, + ((!!match)<<31) | + (timeout&0x7fffffff)); + + dto->ch_disable = ch_dis; + dto->match = match; + dto->timeout = timeout; + dto->trigger = 0; + dto->enable = 1; + + pr_inf("demux%d timeout enable:timeout(%d),ch(0x%x),match(%d)\n", + dto->dmx->id, dto->timeout, dto->ch_disable, dto->match); + + return 0; +} +static int _dmx_timeout_disable(struct aml_dmxtimeout *dto) +{ + + DMX_WRITE_REG(dto->dmx->id, DEMUX_INPUT_TIMEOUT, 0); + dto->enable = 0; + dto->trigger = 0; + pr_inf("demux%d timeout disable\n", dto->dmx->id); + + return 0; +} + +static int dmx_timeout_set(struct aml_dmxtimeout *dto, int enable, + int timeout, int ch_dis, int match, + int force) +{ + + if (!enable) {/*disable*/ + + if (dto->enable || force) + _dmx_timeout_disable(dto); + + } else {/*enable*/ + + if (timeout < 0) { + timeout = DTO_TIMEOUT_DEF; + ch_dis = DTO_CHDIS_VAS; + match = dto->match; + } else if (!timeout) { + timeout = dto->timeout; + ch_dis = dto->ch_disable; + match = dto->match; + } + + if ((dto->enable && (timeout != dto->timeout)) + || force) + _dmx_timeout_disable(dto); + + if (!dto->enable) + _dmx_timeout_enable(dto, timeout, ch_dis, match); + } + + return 0; +} + +/*Initialize the registers*/ +static int dmx_init(struct aml_dmx *dmx) +{ + struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv; + int irq; + + if (dmx->init) + return 0; + + pr_inf("demux init\n"); + + /*Register irq handlers */ + if (dmx->dmx_irq != -1) { + pr_dbg("request irq\n"); + tasklet_init(&dmx->dmx_tasklet, + dmx_irq_bh_handler, + (unsigned long)dmx); + irq = request_irq(dmx->dmx_irq, dmx_irq_handler, + IRQF_SHARED|IRQF_TRIGGER_RISING, + "dmx irq", dmx); + } + + /*Allocate buffer */ + if (dmx_alloc_sec_buffer(dmx) < 0) + return -1; +#ifdef NO_SUB + if (dmx_alloc_sub_buffer(dmx) < 0) + return -1; +#endif + if (dmx_alloc_pes_buffer(dmx) < 0) + return -1; + + /*Reset the hardware */ + if (!dvb->dmx_init) { + init_timer(&dvb->watchdog_timer); + dvb->watchdog_timer.function = section_buffer_watchdog_func; + dvb->watchdog_timer.expires = + jiffies + msecs_to_jiffies(WATCHDOG_TIMER); + dvb->watchdog_timer.data = (unsigned long)dvb; +#ifdef ENABLE_SEC_BUFF_WATCHDOG + add_timer(&dvb->watchdog_timer); +#endif + dmx_reset_hw(dvb); + } + + dvb->dmx_init++; + + memset(dmx->sec_buf_watchdog_count, 0, + sizeof(dmx->sec_buf_watchdog_count)); + + dmx->init = 1; + + return 0; +} + +/*Release the resource*/ +static int dmx_deinit(struct aml_dmx *dmx) +{ + struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv; + + if (!dmx->init) + return 0; + + DMX_WRITE_REG(dmx->id, DEMUX_CONTROL, 0); + + dvb->dmx_init--; + + /*Reset the hardware */ + if (!dvb->dmx_init) { + dmx_reset_hw(dvb); +#ifdef ENABLE_SEC_BUFF_WATCHDOG + del_timer_sync(&dvb->watchdog_timer); +#endif + } + + if (dmx->sec_pages) { + dma_unmap_single(dmx_get_dev(dmx), dmx->sec_pages_map, + dmx->sec_total_len, DMA_FROM_DEVICE); + free_pages(dmx->sec_pages, get_order(dmx->sec_total_len)); + dmx->sec_pages = 0; + dmx->sec_pages_map = 0; + } +#ifdef NO_SUB + if (dmx->sub_pages) { + dma_unmap_single(dmx_get_dev(dmx), dmx->sub_pages_map, + dmx->sub_buf_len, DMA_FROM_DEVICE); + free_pages(dmx->sub_pages, get_order(dmx->sub_buf_len)); + dmx->sub_pages = 0; + } +#endif + if (dmx->pes_pages) { + dma_unmap_single(dmx_get_dev(dmx), dmx->pes_pages_map, + dmx->pes_buf_len, DMA_FROM_DEVICE); + free_pages(dmx->pes_pages, get_order(dmx->pes_buf_len)); + dmx->pes_pages = 0; + } + + if (dmx->dmx_irq != -1) { + free_irq(dmx->dmx_irq, dmx); + tasklet_kill(&dmx->dmx_tasklet); + } + + dmx->init = 0; + + return 0; +} + +/*Check the record flag*/ +static int dmx_get_record_flag(struct aml_dmx *dmx) +{ + int i, linked = 0, record_flag = 0; + struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv; + + /*Check whether a async fifo connected to this dmx */ + for (i = 0; i < ASYNCFIFO_COUNT; i++) { + if (!dvb->asyncfifo[i].init) + continue; + if ((dvb->asyncfifo[i].source == dmx->id) + /*&& !(dvb->swfilter.user && (i==SF_AFIFO_ID)) */ + /*sf mode reserved */ + ) { + linked = 1; + break; + } + } + + for (i = 0; i < CHANNEL_COUNT; i++) { + if (dmx->channel[i].used && dmx->channel[i].dvr_feed) { + if (!dmx->record) { + dmx->record = 1; + + if (linked) { + /*A new record will start, + * must reset the async fifos for + * linking the right demux + */ + reset_async_fifos(dvb); + } + } + if (linked) + record_flag = 1; + goto find_done; + } + } + + if (dmx->record) { + dmx->record = 0; + if (linked) { + /*A record will stop, reset the async fifos + *for linking the right demux + */ + reset_async_fifos(dvb); + } + } + +find_done: + return record_flag; +} + +/*Enable the demux device*/ +static int dmx_enable(struct aml_dmx *dmx) +{ + struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv; + int fec_sel, hi_bsf, fec_ctrl, record; + int fec_core_sel = 0; + int set_stb = 0, fec_s = 0; + int s2p_id; + u32 invert0 = 0, invert1 = 0, fec_s0 = 0, fec_s1 = 0; + u32 use_sop = 0; + + record = dmx_get_record_flag(dmx); + if (use_of_sop == 1) { + use_sop = 1; + pr_inf("dmx use of sop input\r\n"); + } + switch (dmx->source) { + case AM_TS_SRC_TS0: + fec_sel = 0; + fec_ctrl = dvb->ts[0].control; + record = record ? 1 : 0; + break; + case AM_TS_SRC_TS1: + fec_sel = 1; + fec_ctrl = dvb->ts[1].control; + record = record ? 1 : 0; + break; + case AM_TS_SRC_TS2: + fec_sel = 2; + fec_ctrl = dvb->ts[2].control; + record = record ? 1 : 0; + break; + case AM_TS_SRC_S_TS0: + case AM_TS_SRC_S_TS1: + case AM_TS_SRC_S_TS2: + s2p_id = 0; + fec_ctrl = 0; + if (dmx->source == AM_TS_SRC_S_TS0) { + s2p_id = dvb->ts[0].s2p_id; + fec_ctrl = dvb->ts[0].control; + } else if (dmx->source == AM_TS_SRC_S_TS1) { + s2p_id = dvb->ts[1].s2p_id; + fec_ctrl = dvb->ts[1].control; + } else if (dmx->source == AM_TS_SRC_S_TS2) { + s2p_id = dvb->ts[2].s2p_id; + fec_ctrl = dvb->ts[2].control; + } + fec_sel = (s2p_id == 1) ? 5 : 6; + record = record ? 1 : 0; + set_stb = 1; + fec_s = dmx->source - AM_TS_SRC_S_TS0; + break; + case AM_TS_SRC_HIU: + fec_sel = 7; + fec_ctrl = 0; + record = 0; + break; + default: + fec_sel = 0; + fec_ctrl = 0; + record = 0; + break; + } + + if (dmx->channel[0].used || dmx->channel[1].used) + hi_bsf = 1; + else + hi_bsf = 0; + + if ((dvb->dsc[0].dst != -1) + && ((dvb->dsc[0].dst - AM_TS_SRC_DMX0) == dmx->id)) + fec_core_sel = 1; + + if ((dvb->dsc[1].dst != -1) + && ((dvb->dsc[1].dst - AM_TS_SRC_DMX0) == dmx->id)) { + int des_in, des_out, en_des = 0; + + switch (dvb->dsc[1].source) { + case AM_TS_SRC_DMX0: + des_in = 0; + en_des = 1; + break; + case AM_TS_SRC_DMX1: + des_in = 1; + en_des = 1; + break; + case AM_TS_SRC_DMX2: + des_in = 2; + en_des = 1; + break; + default: + des_in = 0; + en_des = 0; + break; + } + + switch (dvb->dsc[1].dst) { + case AM_TS_SRC_DMX0: + des_out = 1; + break; + case AM_TS_SRC_DMX1: + des_out = 2; + break; + case AM_TS_SRC_DMX2: + des_out = 4; + break; + default: + des_out = 0; + break; + } + + if (!des_out) + en_des = 0; + + WRITE_MPEG_REG(COMM_DESC_2_CTL, + (6 << 8) |/*des_out_dly_2*/ + ((!!en_des) << 6) |/* des_pl_clk_2*/ + ((!!en_des) << 5) |/* des_pl_2*/ + (des_out << 2) |/*use_des_2*/ + (des_in)/*des_i_sel_2*/ + ); + fec_core_sel = 1; + pr_dbg("dsc2 ctrl: 0x%x\n", READ_MPEG_REG(COMM_DESC_2_CTL)); + } + + pr_dbg("[dmx-%d]src: %d, rec: %d, hi_bsf: %d, dsc: %d\n", + dmx->id, dmx->source, record, hi_bsf, fec_core_sel); + + if (dmx->chan_count) { + if (set_stb) { + u32 v = READ_MPEG_REG(STB_TOP_CONFIG); + int i; + + for (i = 0; i < TS_IN_COUNT; i++) { + if (dvb->ts[i].s2p_id == 0) + fec_s0 = i; + else if (dvb->ts[i].s2p_id == 1) + fec_s1 = i; + } + + invert0 = dvb->s2p[0].invert; + invert1 = dvb->s2p[1].invert; + + v &= ~((0x3 << S2P0_FEC_SERIAL_SEL) | + (0x1f << INVERT_S2P0_FEC_CLK) | + (0x3 << S2P1_FEC_SERIAL_SEL) | + (0x1f << INVERT_S2P1_FEC_CLK)); + + v |= (fec_s0 << S2P0_FEC_SERIAL_SEL) | + (invert0 << INVERT_S2P0_FEC_CLK) | + (fec_s1 << S2P1_FEC_SERIAL_SEL) | + (invert1 << INVERT_S2P1_FEC_CLK); + WRITE_MPEG_REG(STB_TOP_CONFIG, v); + } + + /*Initialize the registers */ + DMX_WRITE_REG(dmx->id, STB_INT_MASK, DEMUX_INT_MASK); + DMX_WRITE_REG(dmx->id, DEMUX_MEM_REQ_EN, +#ifdef USE_AHB_MODE + (1 << SECTION_AHB_DMA_EN) | + (0 << SUB_AHB_DMA_EN) | + (1 << OTHER_PES_AHB_DMA_EN) | +#endif + (1 << SECTION_PACKET) | + (1 << VIDEO_PACKET) | + (1 << AUDIO_PACKET) | + (1 << SUB_PACKET) | + (1 << SCR_ONLY_PACKET) | + (1 << OTHER_PES_PACKET)); + DMX_WRITE_REG(dmx->id, PES_STRONG_SYNC, 0x1234); + DMX_WRITE_REG(dmx->id, DEMUX_ENDIAN, + (1<id, TS_HIU_CTL, + (0 << LAST_BURST_THRESHOLD) | + (hi_bsf << USE_HI_BSF_INTERFACE)); + + DMX_WRITE_REG(dmx->id, FEC_INPUT_CONTROL, + (fec_core_sel << FEC_CORE_SEL) | + (fec_sel << FEC_SEL) | (fec_ctrl << 0)); + DMX_WRITE_REG(dmx->id, STB_OM_CTL, + (0x40 << MAX_OM_DMA_COUNT) | + (0x7f << LAST_OM_ADDR)); + DMX_WRITE_REG(dmx->id, DEMUX_CONTROL, + (0 << BYPASS_USE_RECODER_PATH) | + (0 << INSERT_AUDIO_PES_STRONG_SYNC) | + (0 << INSERT_VIDEO_PES_STRONG_SYNC) | + (0 << OTHER_INT_AT_PES_BEGINING) | + (0 << DISCARD_AV_PACKAGE) | + ((!!dmx->dump_ts_select) << TS_RECORDER_SELECT) | + (record << TS_RECORDER_ENABLE) | + (1 << KEEP_DUPLICATE_PACKAGE) | + (1 << SECTION_END_WITH_TABLE_ID) | + (1 << ENABLE_FREE_CLK_FEC_DATA_VALID) | + (1 << ENABLE_FREE_CLK_STB_REG) | + (1 << STB_DEMUX_ENABLE) | + (use_sop << NOT_USE_OF_SOP_INPUT)); + } else { + DMX_WRITE_REG(dmx->id, STB_INT_MASK, 0); + DMX_WRITE_REG(dmx->id, FEC_INPUT_CONTROL, 0); + DMX_WRITE_REG(dmx->id, DEMUX_CONTROL, 0); + } + + return 0; +} + +static int dmx_set_misc(struct aml_dmx *dmx, int hi_bsf, int en_dsc) +{ + if (hi_bsf >= 0) { + DMX_WRITE_REG(dmx->id, TS_HIU_CTL, + hi_bsf ? + (DMX_READ_REG(dmx->id, TS_HIU_CTL) | + (1 << USE_HI_BSF_INTERFACE)) + : + (DMX_READ_REG(dmx->id, TS_HIU_CTL) & + (~(1 << USE_HI_BSF_INTERFACE)))); + } + + if (en_dsc >= 0) { + DMX_WRITE_REG(dmx->id, FEC_INPUT_CONTROL, + en_dsc ? + (DMX_READ_REG(dmx->id, FEC_INPUT_CONTROL) | + (1 << FEC_CORE_SEL)) + : + (DMX_READ_REG(dmx->id, FEC_INPUT_CONTROL) & + (~(1 << FEC_CORE_SEL)))); + } + + return 0; +} + +static int dmx_set_misc_id(struct aml_dvb *dvb, int id, int hi_bsf, int en_dsc) +{ + return dmx_set_misc(&dvb->dmx[id], hi_bsf, en_dsc); +} + +/*Get the channel's ID by its PID*/ +static int dmx_get_chan(struct aml_dmx *dmx, int pid) +{ + int id; + + for (id = 0; id < CHANNEL_COUNT; id++) { + if (dmx->channel[id].used && dmx->channel[id].pid == pid) + return id; + } + + return -1; +} + +/*Get the channel's target*/ +static u32 dmx_get_chan_target(struct aml_dmx *dmx, int cid) +{ + u32 type; + + if (!dmx->channel[cid].used) + return 0xFFFF; + + if (dmx->channel[cid].type == DMX_TYPE_SEC) { + type = SECTION_PACKET; + } else { + switch (dmx->channel[cid].pes_type) { + case DMX_PES_AUDIO: + type = AUDIO_PACKET; + break; + case DMX_PES_VIDEO: + type = VIDEO_PACKET; + break; + case DMX_PES_SUBTITLE: + case DMX_PES_TELETEXT: + type = SUB_PACKET; + break; + case DMX_PES_PCR: + type = SCR_ONLY_PACKET; + break; + default: + type = OTHER_PES_PACKET; + break; + } + } + + pr_dbg("chan target: %x %x\n", type, dmx->channel[cid].pid); + return (type << PID_TYPE) | dmx->channel[cid].pid; +} + +/*Get the advance value of the channel*/ +static inline u32 dmx_get_chan_advance(struct aml_dmx *dmx, int cid) +{ + return 0; +} + +/*Set the channel registers*/ +static int dmx_set_chan_regs(struct aml_dmx *dmx, int cid) +{ + u32 data, addr, advance, max; + + pr_dbg("set channel (id:%d PID:0x%x) registers\n", cid, + dmx->channel[cid].pid); + + while (DMX_READ_REG(dmx->id, FM_WR_ADDR) & 0x8000) + udelay(1); + + if (cid & 1) { + data = + (dmx_get_chan_target(dmx, cid - 1) << 16) | + dmx_get_chan_target(dmx, cid); + advance = + (dmx_get_chan_advance(dmx, cid) << 8) | + dmx_get_chan_advance(dmx, cid - 1); + } else { + data = + (dmx_get_chan_target(dmx, cid) << 16) | + dmx_get_chan_target(dmx, cid + 1); + advance = + (dmx_get_chan_advance(dmx, cid + 1) << 8) | + dmx_get_chan_advance(dmx, cid); + } + addr = cid >> 1; + DMX_WRITE_REG(dmx->id, FM_WR_DATA, data); + DMX_WRITE_REG(dmx->id, FM_WR_ADDR, (advance << 16) | 0x8000 | addr); + + pr_dbg("write fm %x:%x\n", (advance << 16) | 0x8000 | addr, data); + + for (max = CHANNEL_COUNT - 1; max > 0; max--) { + if (dmx->channel[max].used) + break; + } + + data = DMX_READ_REG(dmx->id, MAX_FM_COMP_ADDR) & 0xF0; + DMX_WRITE_REG(dmx->id, MAX_FM_COMP_ADDR, data | (max >> 1)); + + pr_dbg("write fm comp %x\n", data | (max >> 1)); + + if (DMX_READ_REG(dmx->id, OM_CMD_STATUS) & 0x8e00) { + pr_error("error send cmd %x\n", + DMX_READ_REG(dmx->id, OM_CMD_STATUS)); + } + + if (cid == 0) + first_video_pts = 0; + else if (cid == 1) + first_audio_pts = 0; + + return 0; +} + +/*Get the filter target*/ +static int dmx_get_filter_target(struct aml_dmx *dmx, int fid, u32 *target, + u8 *advance) +{ + struct dmx_section_filter *filter; + struct aml_filter *f; + int i, cid, neq_bytes; + + fid = fid & 0xFFFF; + f = &dmx->filter[fid]; + + if (!f->used) { + target[0] = 0x1fff; + advance[0] = 0; + for (i = 1; i < FILTER_LEN; i++) { + target[i] = 0x9fff; + advance[i] = 0; + } + return 0; + } + + cid = f->chan_id; + filter = f->filter; + + neq_bytes = 0; + if (filter->filter_mode[0] != 0xFF) { + neq_bytes = 2; + } else { + for (i = 3; i < FILTER_LEN; i++) { + if (filter->filter_mode[i] != 0xFF) + neq_bytes++; + } + } + + f->neq = 0; + + for (i = 0; i < FILTER_LEN; i++) { + u8 value = filter->filter_value[i]; + u8 mask = filter->filter_mask[i]; + u8 mode = filter->filter_mode[i]; + u8 mb, mb1, nb, v, t, adv = 0; + + if (!i) { + mb = 1; + mb1 = 1; + v = 0; + if ((mode == 0xFF) && mask) { + t = mask & 0xF0; + if (t) { + mb1 = 0; + adv |= t^0xF0; + } + v |= (value & 0xF0) | adv; + + t = mask & 0x0F; + if (t) { + mb = 0; + adv |= t^0x0F; + } + v |= (value & 0x0F) | adv; + } + + target[i] = (mb << SECTION_FIRSTBYTE_MASKLOW) | + (mb1 << SECTION_FIRSTBYTE_MASKHIGH) | + (0 << SECTION_FIRSTBYTE_DISABLE_PID_CHECK) | + (cid << SECTION_FIRSTBYTE_PID_INDEX) | v; + advance[i] = adv; + } else { + if (i < 3) { + value = 0; + mask = 0; + mode = 0xff; + } + mb = 1; + nb = 0; + v = 0; + + if ((i >= 3) && mask) { + if (mode == 0xFF) { + mb = 0; + nb = 0; + adv = mask ^ 0xFF; + v = value | adv; + } else { + if (neq_bytes == 1) { + mb = 0; + nb = 1; + adv = mask ^ 0xFF; + v = value & ~adv; + } + } + } + target[i] = (mb << SECTION_RESTBYTE_MASK) | + (nb << SECTION_RESTBYTE_MASK_EQ) | + (0 << SECTION_RESTBYTE_DISABLE_PID_CHECK) | + (cid << SECTION_RESTBYTE_PID_INDEX) | v; + advance[i] = adv; + } + + f->value[i] = value; + f->maskandmode[i] = mask & mode; + f->maskandnotmode[i] = mask & ~mode; + + if (f->maskandnotmode[i]) + f->neq = 1; + } + + return 0; +} + +/*Set the filter registers*/ +static int dmx_set_filter_regs(struct aml_dmx *dmx, int fid) +{ + u32 t1[FILTER_LEN], t2[FILTER_LEN]; + u8 advance1[FILTER_LEN], advance2[FILTER_LEN]; + u32 addr, data, max, adv; + int i; + + pr_dbg("set filter (id:%d) registers\n", fid); + + if (fid & 1) { + dmx_get_filter_target(dmx, fid - 1, t1, advance1); + dmx_get_filter_target(dmx, fid, t2, advance2); + } else { + dmx_get_filter_target(dmx, fid, t1, advance1); + dmx_get_filter_target(dmx, fid + 1, t2, advance2); + } + + for (i = 0; i < FILTER_LEN; i++) { + while (DMX_READ_REG(dmx->id, FM_WR_ADDR) & 0x8000) + udelay(1); + + data = (t1[i] << 16) | t2[i]; + addr = (fid >> 1) | ((i + 1) << 4); + adv = (advance1[i] << 8) | advance2[i]; + + DMX_WRITE_REG(dmx->id, FM_WR_DATA, data); + DMX_WRITE_REG(dmx->id, FM_WR_ADDR, (adv << 16) | 0x8000 | addr); + + pr_dbg("write fm %x:%x\n", (adv << 16) | 0x8000 | addr, data); + } + + for (max = FILTER_COUNT - 1; max > 0; max--) { + if (dmx->filter[max].used) + break; + } + + data = DMX_READ_REG(dmx->id, MAX_FM_COMP_ADDR) & 0xF; + DMX_WRITE_REG(dmx->id, MAX_FM_COMP_ADDR, data | ((max >> 1) << 4)); + + pr_dbg("write fm comp %x\n", data | ((max >> 1) << 4)); + + if (DMX_READ_REG(dmx->id, OM_CMD_STATUS) & 0x8e00) { + pr_error("error send cmd %x\n", + DMX_READ_REG(dmx->id, OM_CMD_STATUS)); + } + + return 0; +} + +/*Clear the filter's buffer*/ +static void dmx_clear_filter_buffer(struct aml_dmx *dmx, int fid) +{ + u32 section_busy32 = DMX_READ_REG(dmx->id, SEC_BUFF_READY); + u32 filter_number; + int i; + + if (!section_busy32) + return; + + for (i = 0; i < SEC_BUF_COUNT; i++) { + if (section_busy32 & (1 << i)) { + DMX_WRITE_REG(dmx->id, SEC_BUFF_NUMBER, i); + filter_number = + (DMX_READ_REG(dmx->id, SEC_BUFF_NUMBER) >> 8); + if (filter_number != fid) + section_busy32 &= ~(1 << i); + } + } + + if (section_busy32) + DMX_WRITE_REG(dmx->id, SEC_BUFF_READY, section_busy32); +} + +static void async_fifo_set_regs(struct aml_asyncfifo *afifo, int source_val) +{ + u32 start_addr = virt_to_phys((void *)afifo->pages); + u32 size = afifo->buf_len; + u32 flush_size = afifo->flush_size; + int factor = dmx_get_order(size / flush_size); + + pr_dbg("ASYNC FIFO id=%d, link to DMX%d, start_addr %x, buf_size %d,source value 0x%x, factor %d\n", + afifo->id, afifo->source, start_addr, size, source_val, factor); + /* Destination address */ + WRITE_ASYNC_FIFO_REG(afifo->id, REG0, start_addr); + + /* Setup flush parameters */ + WRITE_ASYNC_FIFO_REG(afifo->id, REG1, + (0 << ASYNC_FIFO_TO_HIU) | + (0 << ASYNC_FIFO_FLUSH) | + /* don't flush the path */ + (1 << ASYNC_FIFO_RESET) | + /* reset the path */ + (1 << ASYNC_FIFO_WRAP_EN) | + /* wrap enable */ + (0 << ASYNC_FIFO_FLUSH_EN) | + /* disable the flush path */ + /*(0x3 << ASYNC_FIFO_FLUSH_CNT_LSB); + * flush 3 x 32 32-bit words + */ + /*(0x7fff << ASYNC_FIFO_FLUSH_CNT_LSB); + * flush 4MBytes of data + */ + (((size >> 7) & 0x7fff) << ASYNC_FIFO_FLUSH_CNT_LSB)); + /* number of 128-byte blocks to flush */ + + /* clear the reset signal */ + WRITE_ASYNC_FIFO_REG(afifo->id, REG1, + READ_ASYNC_FIFO_REG(afifo->id, + REG1) & ~(1 << ASYNC_FIFO_RESET)); + /* Enable flush */ + WRITE_ASYNC_FIFO_REG(afifo->id, REG1, + READ_ASYNC_FIFO_REG(afifo->id, + REG1) | (1 << ASYNC_FIFO_FLUSH_EN)); + + /*Setup Fill parameters */ + WRITE_ASYNC_FIFO_REG(afifo->id, REG2, + (1 << ASYNC_FIFO_ENDIAN_LSB) | + (0 << ASYNC_FIFO_FILL_EN) | + /* disable fill path to reset fill path */ + /*(96 << ASYNC_FIFO_FILL_CNT_LSB); + *3 x 32 32-bit words + */ + (0 << ASYNC_FIFO_FILL_CNT_LSB)); + /* forever FILL; */ + WRITE_ASYNC_FIFO_REG(afifo->id, REG2, + READ_ASYNC_FIFO_REG(afifo->id, REG2) | + (1 << ASYNC_FIFO_FILL_EN));/*Enable fill path*/ + + /* generate flush interrupt */ + WRITE_ASYNC_FIFO_REG(afifo->id, REG3, + (READ_ASYNC_FIFO_REG(afifo->id, REG3) & 0xffff0000) | + ((((size >> (factor + 7)) - 1) & 0x7fff) << + ASYNC_FLUSH_SIZE_IRQ_LSB)); + + /* Connect the STB DEMUX to ASYNC_FIFO */ + WRITE_ASYNC_FIFO_REG(afifo->id, REG2, + READ_ASYNC_FIFO_REG(afifo->id, REG2) | + (source_val << ASYNC_FIFO_SOURCE_LSB)); +} + +/*Reset the ASYNC FIFOS when a ASYNC FIFO connect to a different DMX*/ +static void reset_async_fifos(struct aml_dvb *dvb) +{ + struct aml_asyncfifo *low_dmx_fifo = NULL; + struct aml_asyncfifo *high_dmx_fifo = NULL; + int i, j; + int record_enable; + + pr_dbg("reset ASYNC FIFOs\n"); + for (i = 0; i < ASYNCFIFO_COUNT; i++) { + if (!dvb->asyncfifo[i].init) + continue; + pr_dbg("Disable ASYNC FIFO id=%d\n", dvb->asyncfifo[i].id); + CLEAR_ASYNC_FIFO_REG_MASK(dvb->asyncfifo[i].id, REG1, + 1 << ASYNC_FIFO_FLUSH_EN); + CLEAR_ASYNC_FIFO_REG_MASK(dvb->asyncfifo[i].id, REG2, + 1 << ASYNC_FIFO_FILL_EN); + if (READ_ASYNC_FIFO_REG(dvb->asyncfifo[i].id, REG2) & + (1 << ASYNC_FIFO_FILL_EN) || + READ_ASYNC_FIFO_REG(dvb->asyncfifo[i].id, REG1) & + (1 << ASYNC_FIFO_FLUSH_EN)) { + pr_dbg("Set reg failed\n"); + } else + pr_dbg("Set reg ok\n"); + dvb->asyncfifo[i].buf_toggle = 0; + dvb->asyncfifo[i].buf_read = 0; + } + + for (j = 0; j < DMX_DEV_COUNT; j++) { + if (!dvb->dmx[j].init) + continue; + record_enable = 0; + for (i = 0; i < ASYNCFIFO_COUNT; i++) { + if (!dvb->asyncfifo[i].init) + continue; + + if (dvb->dmx[j].record + && dvb->dmx[j].id == dvb->asyncfifo[i].source) { + /*This dmx is linked to the async fifo, + *Enable the TS_RECORDER_ENABLE + */ + record_enable = 1; + if (!low_dmx_fifo) { + low_dmx_fifo = &dvb->asyncfifo[i]; + } else if (low_dmx_fifo->source > + dvb->asyncfifo[i].source) { + high_dmx_fifo = low_dmx_fifo; + low_dmx_fifo = &dvb->asyncfifo[i]; + } else if (low_dmx_fifo->source < + dvb->asyncfifo[i].source) { + high_dmx_fifo = &dvb->asyncfifo[i]; + } + + break; + } + } + pr_dbg("Set DMX%d TS_RECORDER_ENABLE to %d\n", dvb->dmx[j].id, + record_enable ? 1 : 0); + if (record_enable) { + /*DMX_SET_REG_MASK(dvb->dmx[j].id, + *DEMUX_CONTROL, 1<dmx[j].id, DEMUX_CONTROL, + DMX_READ_REG(dvb->dmx[j].id, DEMUX_CONTROL) | + (1 << TS_RECORDER_ENABLE)); + } else { + /*DMX_CLEAR_REG_MASK(dvb->dmx[j].id, + *DEMUX_CONTROL, 1<dmx[j].id, DEMUX_CONTROL, + DMX_READ_REG(dvb->dmx[j].id, DEMUX_CONTROL) & + (~(1 << TS_RECORDER_ENABLE))); + } + } + + /*Set the async fifo regs */ + if (low_dmx_fifo) { + async_fifo_set_regs(low_dmx_fifo, 0x3); + + if (high_dmx_fifo) + async_fifo_set_regs(high_dmx_fifo, 0x2); + } +} + +/*Reset the demux device*/ +void dmx_reset_hw(struct aml_dvb *dvb) +{ + dmx_reset_hw_ex(dvb, 1); +} + +/*Reset the demux device*/ +void dmx_reset_hw_ex(struct aml_dvb *dvb, int reset_irq) +{ + int id, times; + + pr_dbg("demux reset begin\n"); + + for (id = 0; id < DMX_DEV_COUNT; id++) { + if (!dvb->dmx[id].init) + continue; + if (reset_irq) { + if (dvb->dmx[id].dmx_irq != -1) + disable_irq(dvb->dmx[id].dmx_irq); + if (dvb->dmx[id].dvr_irq != -1) + disable_irq(dvb->dmx[id].dvr_irq); + } + } +#ifdef ENABLE_SEC_BUFF_WATCHDOG + if (reset_irq) + del_timer_sync(&dvb->watchdog_timer); +#endif + + WRITE_MPEG_REG(RESET1_REGISTER, RESET_DEMUXSTB); + + for (id = 0; id < DMX_DEV_COUNT; id++) { + times = 0; + while (times++ < 1000000) { + if (!(DMX_READ_REG(id, OM_CMD_STATUS) & 0x01)) + break; + } + } + + WRITE_MPEG_REG(STB_TOP_CONFIG, 0); + + for (id = 0; id < DMX_DEV_COUNT; id++) { + u32 version, data; + + if (!dvb->dmx[id].init) + continue; + + if (reset_irq) { + if (dvb->dmx[id].dmx_irq != -1) + enable_irq(dvb->dmx[id].dmx_irq); + if (dvb->dmx[id].dvr_irq != -1) + enable_irq(dvb->dmx[id].dvr_irq); + } + DMX_WRITE_REG(id, DEMUX_CONTROL, 0x0000); + version = DMX_READ_REG(id, STB_VERSION); + DMX_WRITE_REG(id, STB_TEST_REG, version); + pr_dbg("STB %d hardware version : %d\n", id, version); + DMX_WRITE_REG(id, STB_TEST_REG, 0x5550); + data = DMX_READ_REG(id, STB_TEST_REG); + if (data != 0x5550) + pr_error("STB %d register access failed\n", id); + DMX_WRITE_REG(id, STB_TEST_REG, 0xaaa0); + data = DMX_READ_REG(id, STB_TEST_REG); + if (data != 0xaaa0) + pr_error("STB %d register access failed\n", id); + DMX_WRITE_REG(id, MAX_FM_COMP_ADDR, 0x0000); + DMX_WRITE_REG(id, STB_INT_MASK, 0); + DMX_WRITE_REG(id, STB_INT_STATUS, 0xffff); + DMX_WRITE_REG(id, FEC_INPUT_CONTROL, 0); + } + + stb_enable(dvb); + + for (id = 0; id < DMX_DEV_COUNT; id++) { + struct aml_dmx *dmx = &dvb->dmx[id]; + int n; + unsigned long addr; + unsigned long base; + unsigned long grp_addr[SEC_BUF_GRP_COUNT]; + int grp_len[SEC_BUF_GRP_COUNT]; + + if (!dvb->dmx[id].init) + continue; + + if (dmx->sec_pages) { + grp_len[0] = (1 << SEC_GRP_LEN_0) * 8; + grp_len[1] = (1 << SEC_GRP_LEN_1) * 8; + grp_len[2] = (1 << SEC_GRP_LEN_2) * 8; + grp_len[3] = (1 << SEC_GRP_LEN_3) * 8; + + grp_addr[0] = virt_to_phys((void *)dmx->sec_pages); + grp_addr[1] = grp_addr[0] + grp_len[0]; + grp_addr[2] = grp_addr[1] + grp_len[1]; + grp_addr[3] = grp_addr[2] + grp_len[2]; + + base = grp_addr[0] & 0xFFFF0000; + DMX_WRITE_REG(dmx->id, SEC_BUFF_BASE, base >> 16); + DMX_WRITE_REG(dmx->id, SEC_BUFF_01_START, + (((grp_addr[0] - base) >> 8) << 16) | + ((grp_addr[1] - base) >> 8)); + DMX_WRITE_REG(dmx->id, SEC_BUFF_23_START, + (((grp_addr[2] - base) >> 8) << 16) | + ((grp_addr[3] - base) >> 8)); + DMX_WRITE_REG(dmx->id, SEC_BUFF_SIZE, + SEC_GRP_LEN_0 | + (SEC_GRP_LEN_1 << 4) | + (SEC_GRP_LEN_2 << 8) | + (SEC_GRP_LEN_3 << 12)); + } + + if (dmx->sub_pages) { + addr = virt_to_phys((void *)dmx->sub_pages); + DMX_WRITE_REG(dmx->id, SB_START, addr >> 12); + DMX_WRITE_REG(dmx->id, SB_LAST_ADDR, + (dmx->sub_buf_len >> 3) - 1); + } + + if (dmx->pes_pages) { + addr = virt_to_phys((void *)dmx->pes_pages); + DMX_WRITE_REG(dmx->id, OB_START, addr >> 12); + DMX_WRITE_REG(dmx->id, OB_LAST_ADDR, + (dmx->pes_buf_len >> 3) - 1); + } + + for (n = 0; n < CHANNEL_COUNT; n++) { + /*struct aml_channel *chan = &dmx->channel[n];*/ + + /*if (chan->used)*/ + { + dmx_set_chan_regs(dmx, n); + } + } + + for (n = 0; n < FILTER_COUNT; n++) { + struct aml_filter *filter = &dmx->filter[n]; + + if (filter->used) + dmx_set_filter_regs(dmx, n); + } + + dmx_enable(&dvb->dmx[id]); + + dmx_smallsec_set(&dmx->smallsec, + dmx->smallsec.enable, + dmx->smallsec.bufsize, + 1); + + dmx_timeout_set(&dmx->timeout, + dmx->timeout.enable, + dmx->timeout.timeout, + dmx->timeout.ch_disable, + dmx->timeout.match, + 1); + } + + for (id = 0; id < DSC_DEV_COUNT; id++) { + struct aml_dsc *dsc = &dvb->dsc[id]; + int n; + + for (n = 0; n < DSC_COUNT; n++) { + struct aml_dsc_channel *ch = &dsc->channel[n]; + /*if(ch->used) */ + { + ch->id = n; + dsc_set_pid(ch, ch->pid); + + if (ch->flags & DSC_SET_EVEN) { + dsc_set_key(ch, 0, + CA_CW_DVB_CSA_EVEN, + ch->even); + } + if (ch->flags & DSC_SET_ODD) { + dsc_set_key(ch, 0, + CA_CW_DVB_CSA_ODD, + ch->odd); + } + if (ch->flags & DSC_SET_AES_EVEN) { + dsc_set_key(ch, 0, + CA_CW_AES_EVEN, + ch->aes_even); + } + if (ch->flags & DSC_SET_AES_ODD) { + dsc_set_key(ch, 0, + CA_CW_AES_ODD, + ch->aes_odd); + } + } + } + } +#ifdef ENABLE_SEC_BUFF_WATCHDOG + if (reset_irq) { + mod_timer(&dvb->watchdog_timer, + jiffies + msecs_to_jiffies(WATCHDOG_TIMER)); + } +#endif + + pr_dbg("demux reset end\n"); +} + +/*Reset the individual demux*/ +void dmx_reset_dmx_hw_ex_unlock(struct aml_dvb *dvb, struct aml_dmx *dmx, + int reset_irq) +{ + { + if (!dmx->init) + return; + if (reset_irq) { + if (dmx->dmx_irq != -1) + disable_irq(dmx->dmx_irq); + if (dmx->dvr_irq != -1) + disable_irq(dmx->dvr_irq); + } + } +#ifdef ENABLE_SEC_BUFF_WATCHDOG + if (reset_irq) { + /*del_timer_sync(&dvb->watchdog_timer); */ + dvb->dmx_watchdog_disable[dmx->id] = 1; + } +#endif + + WRITE_MPEG_REG(RESET3_REGISTER, + (dmx->id) ? ((dmx->id == + 1) ? RESET_DEMUX1 : RESET_DEMUX2) : + RESET_DEMUX0); + WRITE_MPEG_REG(RESET3_REGISTER, RESET_DES); + + { + int times; + + times = 0; + while (times++ < 1000000) { + if (!(DMX_READ_REG(dmx->id, OM_CMD_STATUS) & 0x01)) + break; + } + } + + /*WRITE_MPEG_REG(STB_TOP_CONFIG, 0); */ + + { + u32 version, data; + + if (!dmx->init) + return; + + if (reset_irq) { + if (dmx->dmx_irq != -1) + enable_irq(dmx->dmx_irq); + if (dmx->dvr_irq != -1) + enable_irq(dmx->dvr_irq); + } + DMX_WRITE_REG(dmx->id, DEMUX_CONTROL, 0x0000); + version = DMX_READ_REG(dmx->id, STB_VERSION); + DMX_WRITE_REG(dmx->id, STB_TEST_REG, version); + pr_dbg("STB %d hardware version : %d\n", dmx->id, version); + DMX_WRITE_REG(dmx->id, STB_TEST_REG, 0x5550); + data = DMX_READ_REG(dmx->id, STB_TEST_REG); + if (data != 0x5550) + pr_error("STB %d register access failed\n", dmx->id); + DMX_WRITE_REG(dmx->id, STB_TEST_REG, 0xaaa0); + data = DMX_READ_REG(dmx->id, STB_TEST_REG); + if (data != 0xaaa0) + pr_error("STB %d register access failed\n", dmx->id); + DMX_WRITE_REG(dmx->id, MAX_FM_COMP_ADDR, 0x0000); + DMX_WRITE_REG(dmx->id, STB_INT_MASK, 0); + DMX_WRITE_REG(dmx->id, STB_INT_STATUS, 0xffff); + DMX_WRITE_REG(dmx->id, FEC_INPUT_CONTROL, 0); + } + + stb_enable(dvb); + + { + int n; + unsigned long addr; + unsigned long base; + unsigned long grp_addr[SEC_BUF_GRP_COUNT]; + int grp_len[SEC_BUF_GRP_COUNT]; + + if (!dmx->init) + return; + + if (dmx->sec_pages) { + grp_len[0] = (1 << SEC_GRP_LEN_0) * 8; + grp_len[1] = (1 << SEC_GRP_LEN_1) * 8; + grp_len[2] = (1 << SEC_GRP_LEN_2) * 8; + grp_len[3] = (1 << SEC_GRP_LEN_3) * 8; + + grp_addr[0] = virt_to_phys((void *)dmx->sec_pages); + grp_addr[1] = grp_addr[0] + grp_len[0]; + grp_addr[2] = grp_addr[1] + grp_len[1]; + grp_addr[3] = grp_addr[2] + grp_len[2]; + + base = grp_addr[0] & 0xFFFF0000; + DMX_WRITE_REG(dmx->id, SEC_BUFF_BASE, base >> 16); + DMX_WRITE_REG(dmx->id, SEC_BUFF_01_START, + (((grp_addr[0] - base) >> 8) << 16) | + ((grp_addr[1] - base) >> 8)); + DMX_WRITE_REG(dmx->id, SEC_BUFF_23_START, + (((grp_addr[2] - base) >> 8) << 16) | + ((grp_addr[3] - base) >> 8)); + DMX_WRITE_REG(dmx->id, SEC_BUFF_SIZE, + SEC_GRP_LEN_0 | + (SEC_GRP_LEN_1 << 4) | + (SEC_GRP_LEN_2 << 8) | + (SEC_GRP_LEN_3 << 12)); + } + + if (dmx->sub_pages) { + addr = virt_to_phys((void *)dmx->sub_pages); + DMX_WRITE_REG(dmx->id, SB_START, addr >> 12); + DMX_WRITE_REG(dmx->id, SB_LAST_ADDR, + (dmx->sub_buf_len >> 3) - 1); + } + + if (dmx->pes_pages) { + addr = virt_to_phys((void *)dmx->pes_pages); + DMX_WRITE_REG(dmx->id, OB_START, addr >> 12); + DMX_WRITE_REG(dmx->id, OB_LAST_ADDR, + (dmx->pes_buf_len >> 3) - 1); + } + + for (n = 0; n < CHANNEL_COUNT; n++) { + /*struct aml_channel *chan = &dmx->channel[n];*/ + + /*if (chan->used)*/ + { + dmx_set_chan_regs(dmx, n); + } + } + + for (n = 0; n < FILTER_COUNT; n++) { + struct aml_filter *filter = &dmx->filter[n]; + + if (filter->used) + dmx_set_filter_regs(dmx, n); + } + + for (n = 0; n < SEC_CNT_MAX; n++) { + dmx->sec_cnt[n] = 0; + dmx->sec_cnt_match[n] = 0; + dmx->sec_cnt_crc_fail[n] = 0; + } + + dmx_enable(dmx); + + dmx_smallsec_set(&dmx->smallsec, + dmx->smallsec.enable, + dmx->smallsec.bufsize, + 1); + + dmx_timeout_set(&dmx->timeout, + dmx->timeout.enable, + dmx->timeout.timeout, + dmx->timeout.ch_disable, + dmx->timeout.match, + 1); + } + + { + int id; + + for (id = 0; id < DSC_DEV_COUNT; id++) { + struct aml_dsc *dsc = &dvb->dsc[id]; + int n; + + for (n = 0; n < DSC_COUNT; n++) { + struct aml_dsc_channel *ch = &dsc->channel[n]; + /*if(ch->used) */ + dsc_set_pid(ch, ch->pid); + + if (ch->flags & DSC_SET_EVEN) { + dsc_set_key(ch, 0, + CA_CW_DVB_CSA_EVEN, + ch->even); + } + if (ch->flags & DSC_SET_ODD) { + dsc_set_key(ch, 0, + CA_CW_DVB_CSA_ODD, + ch->odd); + } + if (ch->flags & DSC_SET_AES_EVEN) { + dsc_set_key(ch, 0, + CA_CW_AES_EVEN, + ch->aes_even); + } + if (ch->flags & DSC_SET_AES_ODD) { + dsc_set_key(ch, 0, + CA_CW_AES_ODD, + ch->aes_odd); + } + } + } + } +#ifdef ENABLE_SEC_BUFF_WATCHDOG + if (reset_irq) { + /*mod_timer(&dvb->watchdog_timer, + *jiffies+msecs_to_jiffies(WATCHDOG_TIMER)); + */ + dvb->dmx_watchdog_disable[dmx->id] = 0; + } +#endif +} + +void dmx_reset_dmx_id_hw_ex_unlock(struct aml_dvb *dvb, int id, int reset_irq) +{ + dmx_reset_dmx_hw_ex_unlock(dvb, &dvb->dmx[id], reset_irq); +} + +void dmx_reset_dmx_hw_ex(struct aml_dvb *dvb, struct aml_dmx *dmx, + int reset_irq) +{ + unsigned long flags; + + spin_lock_irqsave(&dvb->slock, flags); + dmx_reset_dmx_hw_ex_unlock(dvb, dmx, reset_irq); + spin_unlock_irqrestore(&dvb->slock, flags); +} + +void dmx_reset_dmx_id_hw_ex(struct aml_dvb *dvb, int id, int reset_irq) +{ + unsigned long flags; + + spin_lock_irqsave(&dvb->slock, flags); + dmx_reset_dmx_id_hw_ex_unlock(dvb, id, reset_irq); + spin_unlock_irqrestore(&dvb->slock, flags); +} + +void dmx_reset_dmx_hw(struct aml_dvb *dvb, int id) +{ + dmx_reset_dmx_id_hw_ex(dvb, id, 1); +} + +/*Allocate subtitle pes buffer*/ +static int alloc_subtitle_pes_buffer(struct aml_dmx *dmx) +{ + int start_ptr = 0; + struct stream_buf_s *sbuff = 0; + u32 phy_addr; + + start_ptr = READ_MPEG_REG(PARSER_SUB_START_PTR); + if (start_ptr) { + WRITE_MPEG_REG(PARSER_SUB_RP, start_ptr); + goto exit; + } + sbuff = get_stream_buffer(BUF_TYPE_SUBTITLE); + if (sbuff) { + if (sbuff->flag & BUF_FLAG_IOMEM) + phy_addr = sbuff->buf_start; + else + phy_addr = virt_to_phys((void *)sbuff->buf_start); + + WRITE_MPEG_REG(PARSER_SUB_RP, phy_addr); + WRITE_MPEG_REG(PARSER_SUB_START_PTR, phy_addr); + WRITE_MPEG_REG(PARSER_SUB_END_PTR, + phy_addr + sbuff->buf_size - 8); + + pr_dbg("pes buff=:%x %x\n", phy_addr, sbuff->buf_size); + } else + pr_dbg("Error stream buffer\n"); +exit: + return 0; +} + +/*Allocate a new channel*/ +int dmx_alloc_chan(struct aml_dmx *dmx, int type, int pes_type, int pid) +{ + int id = -1; + int ret; + + if (type == DMX_TYPE_TS) { + switch (pes_type) { + case DMX_PES_VIDEO: + if (!dmx->channel[0].used) + id = 0; + break; + case DMX_PES_AUDIO: + if (!dmx->channel[1].used) + id = 1; + break; + case DMX_PES_SUBTITLE: + case DMX_PES_TELETEXT: + if (!dmx->channel[2].used) + id = 2; + alloc_subtitle_pes_buffer(dmx); + break; + case DMX_PES_PCR: + if (!dmx->channel[3].used) + id = 3; + break; + case DMX_PES_OTHER: + { + int i; + + for (i = SYS_CHAN_COUNT; + i < CHANNEL_COUNT; i++) { + if (!dmx->channel[i].used) { + id = i; + break; + } + } + } + break; + default: + break; + } + } else { + int i; + + for (i = SYS_CHAN_COUNT; i < CHANNEL_COUNT; i++) { + if (!dmx->channel[i].used) { + id = i; + break; + } + } + } + + if (id == -1) { + pr_error("too many channels\n"); + return -1; + } + + pr_dbg("allocate channel(id:%d PID:0x%x)\n", id, pid); + + if (id <= 3) { + ret = dmx_get_chan(dmx, pid); + if (ret >= 0 && DVR_FEED(dmx->channel[ret].feed)) { + dmx_remove_feed(dmx, dmx->channel[ret].feed); + dmx->channel[id].dvr_feed = dmx->channel[ret].feed; + dmx->channel[id].dvr_feed->priv = (void *)(long)id; + } else { + dmx->channel[id].dvr_feed = NULL; + } + } + + dmx->channel[id].type = type; + dmx->channel[id].pes_type = pes_type; + dmx->channel[id].pid = pid; + dmx->channel[id].used = 1; + dmx->channel[id].filter_count = 0; + + dmx_set_chan_regs(dmx, id); + + set_debug_dmx_chanpids(dmx->id, id, pid); + + dmx->chan_count++; + + dmx_enable(dmx); + + return id; +} + +/*Free a channel*/ +void dmx_free_chan(struct aml_dmx *dmx, int cid) +{ + pr_dbg("free channel(id:%d PID:0x%x)\n", cid, dmx->channel[cid].pid); + + dmx->channel[cid].used = 0; + dmx->channel[cid].pid = 0x1fff; + dmx_set_chan_regs(dmx, cid); + + if (cid == 2) { + u32 parser_sub_start_ptr; + + parser_sub_start_ptr = READ_MPEG_REG(PARSER_SUB_START_PTR); + WRITE_MPEG_REG(PARSER_SUB_RP, parser_sub_start_ptr); + WRITE_MPEG_REG(PARSER_SUB_WP, parser_sub_start_ptr); + } + + set_debug_dmx_chanpids(dmx->id, cid, -1); + dmx->chan_count--; + + dmx_enable(dmx); + + /*Special pes type channel, check its dvr feed */ + if (cid <= 3 && dmx->channel[cid].dvr_feed) { + /*start the dvr feed */ + dmx_add_feed(dmx, dmx->channel[cid].dvr_feed); + } +} + +/*Add a section*/ +static int dmx_chan_add_filter(struct aml_dmx *dmx, int cid, + struct dvb_demux_filter *filter) +{ + int id = -1; + int i; + + for (i = 0; i < FILTER_COUNT; i++) { + if (!dmx->filter[i].used) { + id = i; + break; + } + } + + if (id == -1) { + pr_error("too many filters\n"); + return -1; + } + + pr_dbg("channel(id:%d PID:0x%x) add filter(id:%d)\n", cid, + filter->feed->pid, id); + + dmx->filter[id].chan_id = cid; + dmx->filter[id].used = 1; + dmx->filter[id].filter = (struct dmx_section_filter *)filter; + dmx->channel[cid].filter_count++; + + dmx_set_filter_regs(dmx, id); + + return id; +} + +static void dmx_remove_filter(struct aml_dmx *dmx, int cid, int fid) +{ + pr_dbg("channel(id:%d PID:0x%x) remove filter(id:%d)\n", cid, + dmx->channel[cid].pid, fid); + + dmx->filter[fid].used = 0; + dmx->channel[cid].filter_count--; + + dmx_set_filter_regs(dmx, fid); + dmx_clear_filter_buffer(dmx, fid); +} + +static int sf_add_feed(struct aml_dmx *src_dmx, struct dvb_demux_feed *feed) +{ + int ret = 0; + + struct aml_dvb *dvb = (struct aml_dvb *)src_dmx->demux.priv; + struct aml_swfilter *sf = &dvb->swfilter; + + pr_dbg_sf("sf add pid[%d]\n", feed->pid); + + /*init sf */ + if (!sf->user) { + void *mem; + + mem = vmalloc(SF_BUFFER_SIZE); + if (!mem) { + ret = -ENOMEM; + goto fail; + } + dvb_ringbuffer_init(&sf->rbuf, mem, SF_BUFFER_SIZE); + + sf->dmx = &dvb->dmx[SF_DMX_ID]; + sf->afifo = &dvb->asyncfifo[SF_AFIFO_ID]; + + sf->dmx->source = src_dmx->source; + sf->afifo->source = sf->dmx->id; + sf->track_dmx = src_dmx->id; + /*sf->afifo->flush_size = 188*10; */ + + pr_dbg_sf("init sf mode.\n"); + + } else if (sf->dmx->source != src_dmx->source) { + pr_error(" pid=%d[src:%d] already used with sfdmx%d[src:%d]\n", + feed->pid, src_dmx->source, sf->dmx->id, + sf->dmx->source); + ret = -EBUSY; + goto fail; + } + + /*setup feed */ + ret = dmx_get_chan(sf->dmx, feed->pid); + if (ret >= 0) { + pr_error(" pid=%d[dmx:%d] already used [dmx:%d].\n", + feed->pid, src_dmx->id, + ((struct aml_dmx *)sf->dmx->channel[ret].feed-> + demux)->id); + ret = -EBUSY; + goto fail; + } + ret = + dmx_alloc_chan(sf->dmx, DMX_TYPE_TS, DMX_PES_OTHER, + feed->pid); + if (ret < 0) { + pr_error(" %s: alloc chan error, ret=%d\n", __func__, ret); + ret = -EBUSY; + goto fail; + } + sf->dmx->channel[ret].feed = feed; + feed->priv = (void *)(long)ret; + + sf->dmx->channel[ret].dvr_feed = feed; + + sf->user++; + debug_sf_user = sf->user; + + dmx_enable(sf->dmx); + + return 0; + +fail: + feed->priv = (void *)-1; + return ret; +} + +static int sf_remove_feed(struct aml_dmx *src_dmx, struct dvb_demux_feed *feed) +{ + int ret; + + struct aml_dvb *dvb = (struct aml_dvb *)src_dmx->demux.priv; + struct aml_swfilter *sf = &dvb->swfilter; + + if (!sf->user || (sf->dmx->source != src_dmx->source)) + return 0; + + /*add fail, no need to remove*/ + if (((long)feed->priv) < 0) + return 0; + + ret = dmx_get_chan(sf->dmx, feed->pid); + if (ret < 0) + return 0; + + pr_dbg_sf("sf remove pid[%d]\n", feed->pid); + + dmx_free_chan(sf->dmx, (long)feed->priv); + + sf->dmx->channel[ret].feed = NULL; + sf->dmx->channel[ret].dvr_feed = NULL; + + sf->user--; + debug_sf_user = sf->user; + + if (!sf->user) { + sf->dmx->source = -1; + sf->afifo->source = AM_DMX_MAX; + sf->track_dmx = -1; + /*sf->afifo->flush_size = sf->afifo->buf_len>>1; */ + + if (sf->rbuf.data) { + void *mem = sf->rbuf.data; + + sf->rbuf.data = NULL; + vfree(mem); + } + pr_dbg_sf("exit sf mode.\n"); + } + + return 0; +} + +static int sf_feed_sf(struct aml_dmx *dmx, struct dvb_demux_feed *feed, + int add_not_remove) +{ + int sf = 0; + + if (sf_dmx_sf(dmx)) { + pr_error("%s: demux %d is in sf mode\n", __func__, dmx->id); + return -EINVAL; + } + + switch (feed->type) { + case DMX_TYPE_TS:{ + struct dmxdev_filter *dmxdevfilter = + feed->feed.ts.priv; + if (!DVR_FEED(feed)) { + if (dmxdevfilter->params.pes. + flags & DMX_USE_SWFILTER) + sf = 1; + if (force_pes_sf) + sf = 1; + } + } + break; + + case DMX_TYPE_SEC:{ + struct dvb_demux_filter *filter; + + for (filter = feed->filter; filter; + filter = filter->next) { + struct dmxdev_filter *dmxdevfilter = + filter->filter.priv; + if (dmxdevfilter->params.sec. + flags & DMX_USE_SWFILTER) + sf = 1; + if (add_not_remove) + filter->hw_handle = (u16)-1; + } + if (force_sec_sf) + sf = 1; + } + break; + } + + return sf ? 0 : 1; +} + +static int sf_check_feed(struct aml_dmx *dmx, struct dvb_demux_feed *feed, + int add_not_remove) +{ + int ret = 0; + + ret = sf_feed_sf(dmx, feed, add_not_remove); + if (ret) + return ret; + + pr_dbg_sf("%s [pid:%d] %s\n", + (feed->type == DMX_TYPE_TS) ? "DMX_TYPE_TS" : "DMX_TYPE_SEC", + feed->pid, add_not_remove ? "-> sf mode" : "sf mode ->"); + + if (add_not_remove) + ret = sf_add_feed(dmx, feed); + else + ret = sf_remove_feed(dmx, feed); + + if (ret < 0) { + pr_error("sf %s feed fail[%d]\n", + add_not_remove ? "add" : "remove", ret); + } + return ret; +} + +static int dmx_add_feed(struct aml_dmx *dmx, struct dvb_demux_feed *feed) +{ + int id, ret = 0; + struct dvb_demux_filter *filter; + struct dvb_demux_feed *dfeed = NULL; + int sf_ret = 0; /*<0:error, =0:sf_on, >0:sf_off */ + + sf_ret = sf_check_feed(dmx, feed, 1/*SF_FEED_OP_ADD */); + if (sf_ret < 0) + return sf_ret; + + switch (feed->type) { + case DMX_TYPE_TS: + pr_dbg("%s: DMX_TYPE_TS\n", __func__); + ret = dmx_get_chan(dmx, feed->pid); + if (ret >= 0) { + if (DVR_FEED(dmx->channel[ret].feed)) { + if (DVR_FEED(feed)) { + /*dvr feed already work */ + pr_error("PID %d already used(DVR)\n", + feed->pid); + ret = -EBUSY; + goto fail; + } + if (sf_ret) { + /*if sf_on, we do not reset the + *previous dvr feed, just load the pes + *feed on the sf, a diffrent data path. + */ + dfeed = dmx->channel[ret].feed; + dmx_remove_feed(dmx, dfeed); + } + } else { + if (DVR_FEED(feed) + && (!dmx->channel[ret].dvr_feed)) { + /*just store the dvr_feed */ + dmx->channel[ret].dvr_feed = feed; + feed->priv = (void *)(long)ret; + if (!dmx->record) + dmx_enable(dmx); + dmx_add_recchan(dmx->id, ret); + return 0; + } + { + pr_error("PID %d already used\n", + feed->pid); + ret = -EBUSY; + goto fail; + } + } + } + + if (sf_ret) { /*not sf feed. */ + ret = + dmx_alloc_chan(dmx, feed->type, + feed->pes_type, feed->pid); + if (ret < 0) { + pr_dbg("%s: alloc chan error, ret=%d\n", + __func__, ret); + ret = -EBUSY; + goto fail; + } + dmx->channel[ret].feed = feed; + feed->priv = (void *)(long)ret; + dmx->channel[ret].dvr_feed = NULL; + } + /*dvr */ + if (DVR_FEED(feed)) { + dmx->channel[ret].dvr_feed = feed; + feed->priv = (void *)(long)ret; + if (!dmx->record) + dmx_enable(dmx); + dmx_add_recchan(dmx->id, ret); + } else if (dfeed && sf_ret) { + dmx->channel[ret].dvr_feed = dfeed; + dfeed->priv = (void *)(long)ret; + if (!dmx->record) + dmx_enable(dmx); + dmx_add_recchan(dmx->id, ret); + } + + break; + case DMX_TYPE_SEC: + pr_dbg("%s: DMX_TYPE_SEC\n", __func__); + ret = dmx_get_chan(dmx, feed->pid); + if (ret >= 0) { + if (DVR_FEED(dmx->channel[ret].feed)) { + if (sf_ret) { + /*if sf_on, we do not reset the + *previous dvr feed, just load the pes + *feed on the sf,a diffrent data path. + */ + dfeed = dmx->channel[ret].feed; + dmx_remove_feed(dmx, dfeed); + } + } else { + pr_error("PID %d already used\n", feed->pid); + ret = -EBUSY; + goto fail; + } + } + if (sf_ret) { /*not sf feed. */ + id = dmx_alloc_chan(dmx, feed->type, + feed->pes_type, feed->pid); + if (id < 0) { + pr_dbg("%s: alloc chan error, ret=%d\n", + __func__, id); + ret = -EBUSY; + goto fail; + } + for (filter = feed->filter; filter; + filter = filter->next) { + ret = dmx_chan_add_filter(dmx, id, filter); + if (ret >= 0) + filter->hw_handle = ret; + else + filter->hw_handle = (u16)-1; + } + dmx->channel[id].feed = feed; + feed->priv = (void *)(long)id; + dmx->channel[id].dvr_feed = NULL; + + if (dfeed) { + dmx->channel[id].dvr_feed = dfeed; + dfeed->priv = (void *)(long)id; + if (!dmx->record) + dmx_enable(dmx); + dmx_add_recchan(dmx->id, id); + } + } + break; + default: + return -EINVAL; + } + + dmx->feed_count++; + + return 0; + +fail: + feed->priv = (void *)-1; + return ret; +} + +static int dmx_remove_feed(struct aml_dmx *dmx, struct dvb_demux_feed *feed) +{ + struct dvb_demux_filter *filter; + struct dvb_demux_feed *dfeed = NULL; + + int sf_ret = 0; /*<0:error, =0:sf_on, >0:sf_off */ + + /*add fail, no need to remove*/ + if (((long)feed->priv) < 0) + return 0; + + sf_ret = sf_check_feed(dmx, feed, 0/*SF_FEED_OP_RM */); + if (sf_ret <= 0) + return sf_ret; + + switch (feed->type) { + case DMX_TYPE_TS: + if (dmx->channel[(long)feed->priv].feed == + dmx->channel[(long)feed->priv].dvr_feed) { + dmx_rm_recchan(dmx->id, (long)feed->priv); + dmx_free_chan(dmx, (long)feed->priv); + } else { + if (feed == dmx->channel[(long)feed->priv].feed) { + dfeed = dmx->channel[(long)feed->priv].dvr_feed; + dmx_rm_recchan(dmx->id, (long)feed->priv); + dmx_free_chan(dmx, (long)feed->priv); + if (dfeed) { + /*start the dvr feed */ + dmx_add_feed(dmx, dfeed); + } + } else if (feed == + dmx->channel[(long)feed->priv].dvr_feed) { + /*just remove the dvr_feed */ + dmx->channel[(long)feed->priv].dvr_feed = NULL; + dmx_rm_recchan(dmx->id, (long)feed->priv); + if (dmx->record) + dmx_enable(dmx); + } else { + /*This must never happen */ + pr_error("%s: unknown feed\n", __func__); + return -EINVAL; + } + } + + break; + case DMX_TYPE_SEC: + for (filter = feed->filter; filter; filter = filter->next) { + if (filter->hw_handle != (u16)-1) + dmx_remove_filter(dmx, (long)feed->priv, + (int)filter->hw_handle); + } + + dfeed = dmx->channel[(long)feed->priv].dvr_feed; + dmx_rm_recchan(dmx->id, (long)feed->priv); + dmx_free_chan(dmx, (long)feed->priv); + if (dfeed) { + /*start the dvr feed */ + dmx_add_feed(dmx, dfeed); + } + break; + default: + return -EINVAL; + } + + dmx->feed_count--; + return 0; +} + +int aml_dmx_hw_init(struct aml_dmx *dmx) +{ + /* + *struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv; + *unsigned long flags; + */ + int ret; + + /*Demux initialize */ + /*spin_lock_irqsave(&dvb->slock, flags);*/ + ret = dmx_init(dmx); + /*spin_unlock_irqrestore(&dvb->slock, flags);*/ + + return ret; +} + +int aml_dmx_hw_deinit(struct aml_dmx *dmx) +{ + struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv; + unsigned long flags; + int ret; + + spin_lock_irqsave(&dvb->slock, flags); + ret = dmx_deinit(dmx); + spin_unlock_irqrestore(&dvb->slock, flags); + + return ret; +} + +/*extern void afifo_reset(int v);*/ + +int aml_asyncfifo_hw_init(struct aml_asyncfifo *afifo) +{ + +/* + * struct aml_dvb *dvb = afifo->dvb; + * unsigned long flags; + */ + int ret; + + int len = ASYNCFIFO_BUFFER_SIZE_DEFAULT; + unsigned long buf = asyncfifo_alloc_buffer(len); + + if (!buf) + return -1; + + /*Async FIFO initialize*/ +/* + * spin_lock_irqsave(&dvb->slock, flags); + */ +/* + *#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 + * CLK_GATE_ON(ASYNC_FIFO); + *#endif + */ + /*afifo_reset(0);*/ + + WRITE_MPEG_REG(RESET6_REGISTER, (1<<11)|(1<<12)); + + ret = async_fifo_init(afifo, 1, len, buf); +/* + * spin_unlock_irqrestore(&dvb->slock, flags); + */ + if (ret < 0) + asyncfifo_free_buffer(buf, len); + + return ret; +} + +int aml_asyncfifo_hw_deinit(struct aml_asyncfifo *afifo) +{ + int ret; + + ret = async_fifo_deinit(afifo, 1); +/* + *#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 + * CLK_GATE_OFF(ASYNC_FIFO); + *#endif + */ + /*afifo_reset(1);*/ + + return ret; +} + +int aml_asyncfifo_hw_reset(struct aml_asyncfifo *afifo) +{ + struct aml_dvb *dvb = afifo->dvb; + unsigned long flags; + int ret, src = -1; + + int len = ASYNCFIFO_BUFFER_SIZE_DEFAULT; + unsigned long buf = asyncfifo_alloc_buffer(len); + + if (!buf) + return -1; + + spin_lock_irqsave(&dvb->slock, flags); + if (afifo->init) { + src = afifo->source; + async_fifo_deinit(afifo, 0); + } + ret = async_fifo_init(afifo, 0, len, buf); + /* restore the source */ + if (src != -1) + afifo->source = src; + + if ((ret == 0) && afifo->dvb) + reset_async_fifos(afifo->dvb); + + spin_unlock_irqrestore(&dvb->slock, flags); + + if (ret < 0) + asyncfifo_free_buffer(buf, len); + + return ret; +} + +int aml_dmx_hw_start_feed(struct dvb_demux_feed *dvbdmxfeed) +{ + struct aml_dmx *dmx = (struct aml_dmx *)dvbdmxfeed->demux; + struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv; + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&dvb->slock, flags); + ret = dmx_add_feed(dmx, dvbdmxfeed); + spin_unlock_irqrestore(&dvb->slock, flags); + + /*handle errors silently*/ + if (ret != 0) + ret = 0; + + return ret; +} + +int aml_dmx_hw_stop_feed(struct dvb_demux_feed *dvbdmxfeed) +{ + struct aml_dmx *dmx = (struct aml_dmx *)dvbdmxfeed->demux; + struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv; + unsigned long flags; + + spin_lock_irqsave(&dvb->slock, flags); + dmx_remove_feed(dmx, dvbdmxfeed); + spin_unlock_irqrestore(&dvb->slock, flags); + + return 0; +} + +int sf_dmx_track_source(struct aml_dmx *dmx) +{ + struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv; + struct aml_swfilter *sf = &dvb->swfilter; + + if (sf->user && (dmx->id == sf->track_dmx)) { + pr_dbg_sf("tracking dmx src [%d -> %d]\n", + sf->dmx->source, dmx->source); + sf->dmx->source = dmx->source; + dmx_reset_dmx_hw_ex_unlock(dvb, sf->dmx, 0); + } + return 0; +} + +int aml_dmx_hw_set_source(struct dmx_demux *demux, dmx_source_t src) +{ + struct aml_dmx *dmx = (struct aml_dmx *)demux; + struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv; + int ret = 0; + int hw_src; + unsigned long flags; + + if (sf_dmx_sf(dmx)) { + pr_error("%s: demux %d is in sf mode\n", __func__, dmx->id); + return -EINVAL; + } + + spin_lock_irqsave(&dvb->slock, flags); + + hw_src = dmx->source; + + switch (src) { + case DMX_SOURCE_FRONT0: + hw_src = + (dvb->ts[0].mode == + AM_TS_SERIAL) ? AM_TS_SRC_S_TS0 : AM_TS_SRC_TS0; + break; + case DMX_SOURCE_FRONT1: + hw_src = + (dvb->ts[1].mode == + AM_TS_SERIAL) ? AM_TS_SRC_S_TS1 : AM_TS_SRC_TS1; + break; + case DMX_SOURCE_FRONT2: + hw_src = + (dvb->ts[2].mode == + AM_TS_SERIAL) ? AM_TS_SRC_S_TS2 : AM_TS_SRC_TS2; + break; + case DMX_SOURCE_DVR0: + hw_src = AM_TS_SRC_HIU; + break; + default: + pr_error("illegal demux source %d\n", src); + ret = -EINVAL; + break; + } + + if (hw_src != dmx->source) { + dmx->source = hw_src; + dmx_reset_dmx_hw_ex_unlock(dvb, dmx, 0); + sf_dmx_track_source(dmx); + } + + spin_unlock_irqrestore(&dvb->slock, flags); + + return ret; +} + +#define IS_SRC_DMX(_src) ((_src) >= AM_TS_SRC_DMX0 && (_src) <= AM_TS_SRC_DMX2) + +int aml_stb_hw_set_source(struct aml_dvb *dvb, dmx_source_t src) +{ + unsigned long flags; + int hw_src; + int ret; + + ret = 0; + spin_lock_irqsave(&dvb->slock, flags); + + hw_src = dvb->stb_source; + + switch (src) { + case DMX_SOURCE_FRONT0: + hw_src = + (dvb->ts[0].mode == + AM_TS_SERIAL) ? AM_TS_SRC_S_TS0 : AM_TS_SRC_TS0; + break; + case DMX_SOURCE_FRONT1: + hw_src = + (dvb->ts[1].mode == + AM_TS_SERIAL) ? AM_TS_SRC_S_TS1 : AM_TS_SRC_TS1; + break; + case DMX_SOURCE_FRONT2: + hw_src = + (dvb->ts[2].mode == + AM_TS_SERIAL) ? AM_TS_SRC_S_TS2 : AM_TS_SRC_TS2; + break; + case DMX_SOURCE_DVR0: + hw_src = AM_TS_SRC_HIU; + break; + case DMX_SOURCE_FRONT0_OFFSET: + hw_src = AM_TS_SRC_DMX0; + break; + case DMX_SOURCE_FRONT1_OFFSET: + hw_src = AM_TS_SRC_DMX1; + break; + case DMX_SOURCE_FRONT2_OFFSET: + hw_src = AM_TS_SRC_DMX2; + break; + default: + pr_error("illegal demux source %d\n", src); + ret = -EINVAL; + break; + } + + if (dvb->stb_source != hw_src) { + int old_source = dvb->stb_source; + + dvb->stb_source = hw_src; + + if (IS_SRC_DMX(old_source)) { + dmx_set_misc_id(dvb, + (old_source - AM_TS_SRC_DMX0), 0, -1); + } else { + /*which dmx for av-play is unknown, + *can't avoid reset-all + */ + dmx_reset_hw_ex(dvb, 0); + } + + if (IS_SRC_DMX(dvb->stb_source)) { + dmx_set_misc_id(dvb, + (dvb->stb_source - AM_TS_SRC_DMX0), 1, -1); + /*dmx_reset_dmx_id_hw_ex_unlock + * (dvb, (dvb->stb_source-AM_TS_SRC_DMX0), 0); + */ + } else { + /*which dmx for av-play is unknown, + *can't avoid reset-all + */ + dmx_reset_hw_ex(dvb, 0); + } + } + + spin_unlock_irqrestore(&dvb->slock, flags); + + return ret; +} + + + +int aml_dsc_hw_set_source(struct aml_dsc *dsc, + dmx_source_t src, dmx_source_t dst) +{ + struct aml_dvb *dvb = dsc->dvb; + int ret = 0; + unsigned long flags; + int hw_src = -1, hw_dst = -1, org_src = -1, org_dst = -1; + int src_reset = 0, dst_reset = 0; + + spin_lock_irqsave(&dvb->slock, flags); + + hw_src = dsc->source; + hw_dst = dsc->dst; + + switch (src) { + case DMX_SOURCE_FRONT0_OFFSET: + hw_src = AM_TS_SRC_DMX0; + break; + case DMX_SOURCE_FRONT1_OFFSET: + hw_src = AM_TS_SRC_DMX1; + break; + case DMX_SOURCE_FRONT2_OFFSET: + hw_src = AM_TS_SRC_DMX2; + break; + default: + hw_src = -1; + break; + } + switch (dst) { + case DMX_SOURCE_FRONT0_OFFSET: + hw_dst = AM_TS_SRC_DMX0; + break; + case DMX_SOURCE_FRONT1_OFFSET: + hw_dst = AM_TS_SRC_DMX1; + break; + case DMX_SOURCE_FRONT2_OFFSET: + hw_dst = AM_TS_SRC_DMX2; + break; + default: + hw_dst = -1; + break; + } + + if (hw_src != dsc->source) { + org_src = dsc->source; + dsc->source = hw_src; + src_reset = 1; + } + if (hw_dst != dsc->dst) { + org_dst = dsc->dst; + dsc->dst = hw_dst; + dst_reset = 1; + } + + if (src_reset) { + pr_dbg("dsc%d source changed: %d -> %d\n", + dsc->id, org_src, hw_src); + if (org_src != -1) { + pr_dbg("reset dmx%d\n", (org_src - AM_TS_SRC_DMX0)); + dmx_reset_dmx_id_hw_ex_unlock(dvb, + (org_src - AM_TS_SRC_DMX0), 0); + } + if (hw_src != -1) { + pr_dbg("reset dmx%d\n", (hw_src - AM_TS_SRC_DMX0)); + dmx_reset_dmx_id_hw_ex_unlock(dvb, + (hw_src - AM_TS_SRC_DMX0), 0); + } else + dsc_enable(dsc, 0); + } + if (dst_reset) { + pr_dbg("dsc%d dest changed: %d -> %d\n", + dsc->id, org_dst, hw_dst); + if (((!src_reset) && (org_dst != -1)) || + (src_reset && (org_dst != -1) && + (org_dst != org_src) && (org_dst != hw_src))) { + pr_dbg("reset dmx%d\n", (org_dst - AM_TS_SRC_DMX0)); + dmx_reset_dmx_id_hw_ex_unlock(dvb, + (org_dst - AM_TS_SRC_DMX0), 0); + } + if (((!src_reset) && (hw_dst != -1)) || + (src_reset && (hw_dst != -1) + && (hw_dst != org_src) && (hw_dst != hw_src))) { + pr_dbg("reset dmx%d\n", (hw_dst - AM_TS_SRC_DMX0)); + dmx_reset_dmx_id_hw_ex_unlock(dvb, + (hw_dst - AM_TS_SRC_DMX0), 0); + } + if (hw_dst == -1) + dsc_enable(dsc, 0); + } + + spin_unlock_irqrestore(&dvb->slock, flags); + + return ret; +} + +int aml_ciplus_hw_set_source(int src) +{ + int hw_src = 0; + int hw_dst = 0; + u32 data; + + switch (src) { + case DMX_SOURCE_FRONT0_OFFSET: + hw_src = 0; + hw_dst = 1; + break; + case DMX_SOURCE_FRONT1_OFFSET: + hw_src = 1; + hw_dst = 2; + break; + case DMX_SOURCE_FRONT2_OFFSET: + hw_src = 2; + hw_dst = 4; + break; + default: + return -1; + } + + data = READ_MPEG_REG(STB_TOP_CONFIG); + + /* Set ciplus input source , + * output set 0 means no output. ---> need confirm. + * if output set 0 still affects dsc output, we need to disable + * ciplus module. + */ + data &= ~(3<slock, flags); + + hw_src = dvb->tso_source; + + switch (src) { + case DMX_SOURCE_FRONT0: + hw_src = (dvb->ts[0].mode == AM_TS_SERIAL) + ? AM_TS_SRC_S_TS0 : AM_TS_SRC_TS0; + break; + case DMX_SOURCE_FRONT1: + hw_src = (dvb->ts[1].mode == AM_TS_SERIAL) + ? AM_TS_SRC_S_TS1 : AM_TS_SRC_TS1; + break; + case DMX_SOURCE_FRONT2: + hw_src = (dvb->ts[2].mode == AM_TS_SERIAL) + ? AM_TS_SRC_S_TS2 : AM_TS_SRC_TS2; + break; + case DMX_SOURCE_DVR0: + hw_src = AM_TS_SRC_HIU; + break; + case DMX_SOURCE_FRONT0 + 100: + hw_src = AM_TS_SRC_DMX0; + break; + case DMX_SOURCE_FRONT1 + 100: + hw_src = AM_TS_SRC_DMX1; + break; + case DMX_SOURCE_FRONT2 + 100: + hw_src = AM_TS_SRC_DMX2; + break; + default: + hw_src = -1; + ret = -EINVAL; + break; + } + + if (hw_src != dvb->tso_source) { + dvb->tso_source = hw_src; + stb_enable(dvb); + } + + spin_unlock_irqrestore(&dvb->slock, flags); + + return ret; +} + +int aml_asyncfifo_hw_set_source(struct aml_asyncfifo *afifo, + enum aml_dmx_id_t src) +{ + struct aml_dvb *dvb = afifo->dvb; + int ret = -1; + unsigned long flags; + + if (sf_afifo_sf(afifo)) { + pr_error("%s: afifo %d is in sf mode\n", __func__, afifo->id); + return -EINVAL; + } + + spin_lock_irqsave(&dvb->slock, flags); + + pr_dbg("asyncfifo %d set source %d->%d", + afifo->id, afifo->source, src); + switch (src) { + case AM_DMX_0: + case AM_DMX_1: + case AM_DMX_2: + if (afifo->source != src) { + afifo->source = src; + ret = 0; + } + break; + default: + pr_error("illegal async fifo source %d\n", src); + ret = -EINVAL; + break; + } + + if (ret == 0 && afifo->dvb) + reset_async_fifos(afifo->dvb); + + spin_unlock_irqrestore(&dvb->slock, flags); + + return ret; +} + +int aml_dmx_hw_set_dump_ts_select(struct dmx_demux *demux, int dump_ts_select) +{ + struct aml_dmx *dmx = (struct aml_dmx *)demux; + struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv; + int ret = 0; + unsigned long flags; + + spin_lock_irqsave(&dvb->slock, flags); + dump_ts_select = !!dump_ts_select; + if (dmx->dump_ts_select != dump_ts_select) { + dmx->dump_ts_select = dump_ts_select; + dmx_reset_dmx_hw_ex_unlock(dvb, dmx, 0); + } + spin_unlock_irqrestore(&dvb->slock, flags); + + return ret; +} + +u32 aml_dmx_get_video_pts(struct aml_dvb *dvb) +{ + unsigned long flags; + u32 pts; + + spin_lock_irqsave(&dvb->slock, flags); + pts = video_pts; + spin_unlock_irqrestore(&dvb->slock, flags); + + return pts; +} + +u32 aml_dmx_get_audio_pts(struct aml_dvb *dvb) +{ + unsigned long flags; + u32 pts; + + spin_lock_irqsave(&dvb->slock, flags); + pts = audio_pts; + spin_unlock_irqrestore(&dvb->slock, flags); + + return pts; +} + +u32 aml_dmx_get_first_video_pts(struct aml_dvb *dvb) +{ + unsigned long flags; + u32 pts; + + spin_lock_irqsave(&dvb->slock, flags); + pts = first_video_pts; + spin_unlock_irqrestore(&dvb->slock, flags); + + return pts; +} + +u32 aml_dmx_get_first_audio_pts(struct aml_dvb *dvb) +{ + unsigned long flags; + u32 pts; + + spin_lock_irqsave(&dvb->slock, flags); + pts = first_audio_pts; + spin_unlock_irqrestore(&dvb->slock, flags); + + return pts; +} + +int aml_dmx_set_skipbyte(struct aml_dvb *dvb, int skipbyte) +{ + if (demux_skipbyte != skipbyte) { + pr_dbg("set skip byte %d\n", skipbyte); + demux_skipbyte = skipbyte; + dmx_reset_hw_ex(dvb, 0); + } + + return 0; +} + +int aml_dmx_set_demux(struct aml_dvb *dvb, int id) +{ + aml_stb_hw_set_source(dvb, DMX_SOURCE_DVR0); + if (id < DMX_DEV_COUNT) { + struct aml_dmx *dmx = &dvb->dmx[id]; + + aml_dmx_hw_set_source((struct dmx_demux *)dmx, + DMX_SOURCE_DVR0); + } + + return 0; +} + +int _set_tsfile_clkdiv(struct aml_dvb *dvb, int clkdiv) +{ + if (tsfile_clkdiv != clkdiv) { + pr_dbg("set ts file clock div %d\n", clkdiv); + tsfile_clkdiv = clkdiv; + dmx_reset_hw(dvb); + } + + return 0; +} + +static ssize_t stb_set_tsfile_clkdiv(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size) +{ + /*int div = (int)simple_strtol(buf, NULL, 10);*/ + long div; + + if (kstrtol(buf, 0, &div) == 0) + _set_tsfile_clkdiv(aml_get_dvb_device(), (int)div); + return size; +} + +static ssize_t stb_get_tsfile_clkdiv(struct class *class, + struct class_attribute *attr, char *buf) +{ + ssize_t ret; + + ret = sprintf(buf, "%d\n", tsfile_clkdiv); + return ret; +} + + +static int dmx_id; + +static ssize_t dmx_smallsec_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + ssize_t ret; + struct aml_dvb *dvb = aml_get_dvb_device(); + + ret = sprintf(buf, "%d:%d\n", dvb->dmx[dmx_id].smallsec.enable, + dvb->dmx[dmx_id].smallsec.bufsize); + return ret; +} +static ssize_t dmx_smallsec_store(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size) +{ + int i, e, s = 0, f = 0; + struct aml_dvb *dvb = aml_get_dvb_device(); + + i = sscanf(buf, "%d:%i:%d", &e, &s, &f); + if (i <= 0) + return size; + + dmx_smallsec_set(&dvb->dmx[dmx_id].smallsec, e, s, f); + return size; +} + +static ssize_t dmx_timeout_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + ssize_t ret; + struct aml_dvb *dvb = aml_get_dvb_device(); + + ret = sprintf(buf, "%d:%d:0x%x:%d:%d\n", + dvb->dmx[dmx_id].timeout.enable, + dvb->dmx[dmx_id].timeout.timeout, + dvb->dmx[dmx_id].timeout.ch_disable, + dvb->dmx[dmx_id].timeout.match, + (DMX_READ_REG(dmx_id, STB_INT_STATUS)&(1<dmx[dmx_id].timeout, e, t, c, m, f); + return size; +} + + +#define DEMUX_SCAMBLE_FUNC_DECL(i) \ +static ssize_t dmx_reg_value_show_demux##i##_scramble(struct class *class, \ +struct class_attribute *attr, char *buf)\ +{\ + int data = 0;\ + int aflag = 0;\ + int vflag = 0;\ + ssize_t ret = 0;\ + data = DMX_READ_REG(i, DEMUX_SCRAMBLING_STATE);\ + if ((data & 0x01) == 0x01) \ + vflag = 1;\ + if ((data & 0x02) == 0x02) \ + aflag = 1;\ + ret = sprintf(buf, "%d %d\n", vflag, aflag);\ + return ret;\ +} + +#if DMX_DEV_COUNT > 0 +DEMUX_SCAMBLE_FUNC_DECL(0) +#endif +#if DMX_DEV_COUNT > 1 +DEMUX_SCAMBLE_FUNC_DECL(1) +#endif +#if DMX_DEV_COUNT > 2 +DEMUX_SCAMBLE_FUNC_DECL(2) +#endif +static ssize_t ciplus_output_ctrl_show(struct class *class, + struct class_attribute *attr, + char *buf) +{ + int ret; + + pr_error("output demux use 3 bit to indicate. "); + pr_error("1bit:demux0 2bit:demux1 3bit:demux2\n"); + if (ciplus_out_auto_mode == 1) + ret = sprintf(buf, "Using auto mode, value: %x\n", + ciplus_out_sel); + else + ret = sprintf(buf, "%d\n", ciplus_out_sel); + pr_error("ciplus output path:\n"); + if (ciplus_out_sel&1) + pr_error("demux0 "); + if (ciplus_out_sel&1<<1) + pr_error("demux1 "); + if (ciplus_out_sel&1<<2) + pr_error("demux2 "); + pr_error("\n"); + return ret; +} + +static ssize_t ciplus_output_ctrl_store(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size) +{ + int i, tmp; + + pr_error("output demux use 3 bit to indicate. "); + pr_error("1bit:demux0 2bit:demux1 3bit:demux2, 8 for auto\n"); + /*i = sscanf(buf, "%d", &tmp); */ + i = kstrtoint(buf, -1, &tmp); + if (tmp > 8 || tmp < 0) + pr_error("Invalid output set\n"); + else if (tmp == 8) { + ciplus_out_auto_mode = 1; + ciplus_out_sel = -1; + pr_error("Auto set output mode enable\n"); + } else { + ciplus_out_auto_mode = 0; + ciplus_out_sel = tmp; + pr_error("Auto set output mode disable\n"); + } + return size; +} +static ssize_t reset_fec_input_ctrl_show(struct class *class, + struct class_attribute *attr, + char *buf) +{ + return 0; +} + +static ssize_t reset_fec_input_ctrl_store(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size) +{ + u32 v; + + v = READ_MPEG_REG(FEC_INPUT_CONTROL); + v &= ~(1<<11); + WRITE_MPEG_REG(FEC_INPUT_CONTROL, v); + + pr_dbg("reset FEC_INPUT_CONTROL to %x\n", v); + + return size; +} +static ssize_t dmx_reg_addr_show_source(struct class *class, + struct class_attribute *attr, + char *buf); +static ssize_t dmx_reg_addr_store_source(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size); +static ssize_t dmx_id_show_source(struct class *class, + struct class_attribute *attr, char *buf); +static ssize_t dmx_id_store_source(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size); +static ssize_t dmx_reg_value_show_source(struct class *class, + struct class_attribute *attr, + char *buf); +static ssize_t dmx_reg_value_store_source(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size); +static ssize_t dmx_sec_statistics_show(struct class *class, + struct class_attribute *attr, + char *buf); +static int reg_addr; + +static struct class_attribute aml_dmx_class_attrs[] = { + __ATTR(dmx_id, 0644, dmx_id_show_source, + dmx_id_store_source), + __ATTR(register_addr, 0644, dmx_reg_addr_show_source, + dmx_reg_addr_store_source), + __ATTR(register_value, 0644, dmx_reg_value_show_source, + dmx_reg_value_store_source), + __ATTR(tsfile_clkdiv, 0644, stb_get_tsfile_clkdiv, + stb_set_tsfile_clkdiv), + +#define DEMUX_SCAMBLE_ATTR_DECL(i)\ + __ATTR(demux##i##_scramble, 0644, \ + dmx_reg_value_show_demux##i##_scramble, NULL) +#if DMX_DEV_COUNT > 0 + DEMUX_SCAMBLE_ATTR_DECL(0), +#endif +#if DMX_DEV_COUNT > 1 + DEMUX_SCAMBLE_ATTR_DECL(1), +#endif +#if DMX_DEV_COUNT > 2 + DEMUX_SCAMBLE_ATTR_DECL(2), +#endif + + __ATTR(dmx_smallsec, 0644, + dmx_smallsec_show, + dmx_smallsec_store), + __ATTR(dmx_timeout, 0644, + dmx_timeout_show, + dmx_timeout_store), + __ATTR(reset_fec_input_ctrl, 0644, + reset_fec_input_ctrl_show, + reset_fec_input_ctrl_store), + __ATTR(ciplus_output_ctrl, 0644, + ciplus_output_ctrl_show, + ciplus_output_ctrl_store), + __ATTR_RO(dmx_sec_statistics), + __ATTR_NULL +}; + +static struct class aml_dmx_class = { + .name = "dmx", + .class_attrs = aml_dmx_class_attrs, +}; + +static ssize_t dmx_id_show_source(struct class *class, + struct class_attribute *attr, char *buf) +{ + int ret; + + ret = sprintf(buf, "%d\n", dmx_id); + return ret; +} + +static ssize_t dmx_id_store_source(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size) +{ + int id = 0; + long value = 0; + + if (kstrtol(buf, 0, &value) == 0) + id = (int)value; + /*id = simple_strtol(buf, 0, 16);*/ + + if (id < 0 || id > 2) + pr_dbg("dmx id must 0 ~2\n"); + else + dmx_id = id; + + return size; +} + +static ssize_t dmx_reg_addr_show_source(struct class *class, + struct class_attribute *attr, + char *buf) +{ + int ret; + + ret = sprintf(buf, "%x\n", reg_addr); + return ret; +} + +static ssize_t dmx_reg_addr_store_source(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size) +{ + int addr = 0; + /*addr = simple_strtol(buf, 0, 16);*/ + long value = 0; + + if (kstrtol(buf, 0, &value) == 0) + addr = (int)value; + reg_addr = addr; + return size; +} + +static ssize_t dmx_reg_value_show_source(struct class *class, + struct class_attribute *attr, + char *buf) +{ + int ret, value; + + value = READ_MPEG_REG(reg_addr); + ret = sprintf(buf, "%x\n", value); + return ret; +} + +static ssize_t dmx_reg_value_store_source(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size) +{ + int value = 0; + /*value = simple_strtol(buf, 0, 16);*/ + long val = 0; + + if (kstrtol(buf, 0, &val) == 0) + value = (int)val; + WRITE_MPEG_REG(reg_addr, value); + return size; +} + +static ssize_t dmx_sec_statistics_show(struct class *class, + struct class_attribute *attr, + char *buf) +{ + ssize_t ret; + char tmp[128]; + struct aml_dvb *dvb = aml_get_dvb_device(); + + ret = sprintf(tmp, "[hw]%#lx:%#lx:%#lx\n[sw]%#lx:%#lx:%#lx\n", + dvb->dmx[dmx_id].sec_cnt[SEC_CNT_HW], + dvb->dmx[dmx_id].sec_cnt_match[SEC_CNT_HW], + dvb->dmx[dmx_id].sec_cnt_crc_fail[SEC_CNT_HW], + dvb->dmx[dmx_id].sec_cnt[SEC_CNT_SW], + dvb->dmx[dmx_id].sec_cnt_match[SEC_CNT_SW], + dvb->dmx[dmx_id].sec_cnt_crc_fail[SEC_CNT_SW]); + ret = sprintf(buf, "%s[ss]%#lx:%#lx:%#lx\n", + tmp, + dvb->dmx[dmx_id].sec_cnt[SEC_CNT_SS], + dvb->dmx[dmx_id].sec_cnt_match[SEC_CNT_SS], + dvb->dmx[dmx_id].sec_cnt_crc_fail[SEC_CNT_SS]); + return ret; +} + +int aml_regist_dmx_class(void) +{ + + if (class_register(&aml_dmx_class) < 0) + pr_error("register class error\n"); + + return 0; +} + +int aml_unregist_dmx_class(void) +{ + + class_unregister(&aml_dmx_class); + return 0; +} + diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb.c b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb.c new file mode 100644 index 000000000000..1c882ff1e6cc --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb.c @@ -0,0 +1,2410 @@ + /* + * AMLOGIC DVB driver. + */ + +//move to define in Makefile +//#define ENABLE_DEMUX_DRIVER + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "c_stb_define.h" +#include "c_stb_regs_define.h" +#include "aml_dvb.h" +#include "aml_dvb_reg.h" + +#include "../../tv_frontend/aml_fe.h" +#include "aml_demod_gt.h" +#include "../../../common/media_clock/switch/amports_gate.h" + +typedef enum __demod_type +{ + DEMOD_INVALID, + DEMOD_INTERNAL, + DEMOD_ATBM8881, + DEMOD_MAX_NUM +}demod_type; + +typedef enum __tuner_type +{ + TUNER_INVALID, + TUNER_SI2151, + TUNER_MXL661, + TUNER_SI2159, + TUNER_MAX_NUM +}tuner_type; + +#define pr_dbg(args...)\ + do {\ + if (debug_dvb)\ + printk(args);\ + } while (0) +#define pr_error(fmt, args...) printk("DVB: " fmt, ## args) +#define pr_inf(fmt, args...) printk("DVB: " fmt, ## args) + +MODULE_PARM_DESC(debug_dvb, "\n\t\t Enable dvb debug information"); +static int debug_dvb = 1; +module_param(debug_dvb, int, 0644); + +#define CARD_NAME "amlogic-dvb" + +DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); + +MODULE_PARM_DESC(dsc_max, "max number of dsc"); +static int dsc_max = DSC_DEV_COUNT; +module_param(dsc_max, int, 0644); + +static struct aml_dvb aml_dvb_device; +static struct class aml_stb_class; + +static struct dvb_frontend *frontend[FE_DEV_COUNT] = {NULL, NULL}; +static demod_type s_demod_type[FE_DEV_COUNT] = {DEMOD_INVALID, DEMOD_INVALID}; +static tuner_type s_tuner_type[FE_DEV_COUNT] = {TUNER_INVALID, TUNER_INVALID}; + +#if 0 +static struct reset_control *aml_dvb_demux_reset_ctl; +static struct reset_control *aml_dvb_afifo_reset_ctl; +static struct reset_control *aml_dvb_ahbarb0_reset_ctl; +static struct reset_control *aml_dvb_uparsertop_reset_ctl; +#else +/*no used reset ctl,need use clk in 4.9 kernel*/ +static struct clk *aml_dvb_demux_clk; +static struct clk *aml_dvb_afifo_clk; +static struct clk *aml_dvb_ahbarb0_clk; +static struct clk *aml_dvb_uparsertop_clk; +#endif + +static int aml_tsdemux_reset(void); +static int aml_tsdemux_set_reset_flag(void); +static int aml_tsdemux_request_irq(irq_handler_t handler, void *data); +static int aml_tsdemux_free_irq(void); +static int aml_tsdemux_set_vid(int vpid); +static int aml_tsdemux_set_aid(int apid); +static int aml_tsdemux_set_sid(int spid); +static int aml_tsdemux_set_pcrid(int pcrpid); +static int aml_tsdemux_set_skipbyte(int skipbyte); +static int aml_tsdemux_set_demux(int id); + +static struct tsdemux_ops aml_tsdemux_ops = { + .reset = aml_tsdemux_reset, + .set_reset_flag = aml_tsdemux_set_reset_flag, + .request_irq = aml_tsdemux_request_irq, + .free_irq = aml_tsdemux_free_irq, + .set_vid = aml_tsdemux_set_vid, + .set_aid = aml_tsdemux_set_aid, + .set_sid = aml_tsdemux_set_sid, + .set_pcrid = aml_tsdemux_set_pcrid, + .set_skipbyte = aml_tsdemux_set_skipbyte, + .set_demux = aml_tsdemux_set_demux +}; + +long aml_stb_get_base(int id) +{ + int newbase = 0; + if (MESON_CPU_MAJOR_ID_TXL < get_cpu_type() + && MESON_CPU_MAJOR_ID_GXLX != get_cpu_type()) { + newbase = 1; + } + + switch (id) { + case ID_STB_CBUS_BASE: + return (newbase) ? 0x1800 : 0x1600; + case ID_SMARTCARD_REG_BASE: + return (newbase) ? 0x9400 : 0x2110; + case ID_ASYNC_FIFO_REG_BASE: + return (newbase) ? 0x2800 : 0x2310; + case ID_ASYNC_FIFO2_REG_BASE: + return (newbase) ? 0x2400 : 0x2314; + case ID_RESET_BASE: + return (newbase) ? 0x0400 : 0x1100; + case ID_PARSER_SUB_START_PTR_BASE: + return (newbase) ? 0x3800 : 0x2900; + default: + return 0; + } + return 0; +} +static void aml_dvb_dmx_release(struct aml_dvb *advb, struct aml_dmx *dmx) +{ + int i; + + dvb_net_release(&dmx->dvb_net); + aml_dmx_hw_deinit(dmx); + dmx->demux.dmx.close(&dmx->demux.dmx); + dmx->demux.dmx.remove_frontend(&dmx->demux.dmx, &dmx->mem_fe); + + for (i = 0; i < DMX_DEV_COUNT; i++) + dmx->demux.dmx.remove_frontend(&dmx->demux.dmx, &dmx->hw_fe[i]); + + dvb_dmxdev_release(&dmx->dmxdev); + dvb_dmx_release(&dmx->demux); +} + +static int aml_dvb_dmx_init(struct aml_dvb *advb, struct aml_dmx *dmx, int id) +{ + int i, ret; + + struct resource *res; + char buf[32]; + + switch (id) { + case 0: + dmx->dmx_irq = INT_DEMUX; + break; + case 1: + dmx->dmx_irq = INT_DEMUX_1; + break; + case 2: + dmx->dmx_irq = INT_DEMUX_2; + break; + } + + snprintf(buf, sizeof(buf), "demux%d_irq", id); + res = platform_get_resource_byname(advb->pdev, IORESOURCE_IRQ, buf); + if (res) + dmx->dmx_irq = res->start; + + printk("%s irq num:%d \r\n", buf, dmx->dmx_irq); + + dmx->source = -1; + dmx->dump_ts_select = 0; + dmx->dvr_irq = -1; + + dmx->demux.dmx.capabilities = + (DMX_TS_FILTERING | DMX_SECTION_FILTERING | + DMX_MEMORY_BASED_FILTERING); + dmx->demux.filternum = dmx->demux.feednum = FILTER_COUNT; + dmx->demux.priv = advb; + dmx->demux.start_feed = aml_dmx_hw_start_feed; + dmx->demux.stop_feed = aml_dmx_hw_stop_feed; + dmx->demux.write_to_decoder = NULL; + ret = dvb_dmx_init(&dmx->demux); + if (ret < 0) { + pr_error("dvb_dmx failed: error %d\n", ret); + goto error_dmx_init; + } + + dmx->dmxdev.filternum = dmx->demux.feednum; + dmx->dmxdev.demux = &dmx->demux.dmx; + dmx->dmxdev.capabilities = 0; + ret = dvb_dmxdev_init(&dmx->dmxdev, &advb->dvb_adapter); + if (ret < 0) { + pr_error("dvb_dmxdev_init failed: error %d\n", ret); + goto error_dmxdev_init; + } + + for (i = 0; i < DMX_DEV_COUNT; i++) { + int source = i + DMX_FRONTEND_0; + + dmx->hw_fe[i].source = source; + ret = + dmx->demux.dmx.add_frontend(&dmx->demux.dmx, + &dmx->hw_fe[i]); + if (ret < 0) { + pr_error("adding hw_frontend to dmx failed: error %d", + ret); + dmx->hw_fe[i].source = 0; + goto error_add_hw_fe; + } + } + + dmx->mem_fe.source = DMX_MEMORY_FE; + ret = dmx->demux.dmx.add_frontend(&dmx->demux.dmx, &dmx->mem_fe); + if (ret < 0) { + pr_error("adding mem_frontend to dmx failed: error %d", ret); + goto error_add_mem_fe; + } + ret = dmx->demux.dmx.connect_frontend(&dmx->demux.dmx, &dmx->hw_fe[1]); + if (ret < 0) { + pr_error("connect frontend failed: error %d", ret); + goto error_connect_fe; + } + + dmx->id = id; + dmx->aud_chan = -1; + dmx->vid_chan = -1; + dmx->sub_chan = -1; + dmx->pcr_chan = -1; + + /*smallsec*/ + dmx->smallsec.enable = 0; + dmx->smallsec.bufsize = SS_BUFSIZE_DEF; + dmx->smallsec.dmx = dmx; + + /*input timeout*/ + dmx->timeout.enable = 1; + dmx->timeout.timeout = DTO_TIMEOUT_DEF; + dmx->timeout.ch_disable = DTO_CHDIS_VAS; + dmx->timeout.match = 1; + dmx->timeout.trigger = 0; + dmx->timeout.dmx = dmx; + + /*CRC monitor*/ + dmx->crc_check_count = 0; + dmx->crc_check_time = 0; + + ret = aml_dmx_hw_init(dmx); + if (ret < 0) { + pr_error("demux hw init error %d", ret); + dmx->id = -1; + goto error_dmx_hw_init; + } + + dvb_net_init(&advb->dvb_adapter, &dmx->dvb_net, &dmx->demux.dmx); + + return 0; +error_dmx_hw_init: +error_connect_fe: + dmx->demux.dmx.remove_frontend(&dmx->demux.dmx, &dmx->mem_fe); +error_add_mem_fe: +error_add_hw_fe: + for (i = 0; i < DMX_DEV_COUNT; i++) { + if (dmx->hw_fe[i].source) + dmx->demux.dmx.remove_frontend(&dmx->demux.dmx, + &dmx->hw_fe[i]); + } + dvb_dmxdev_release(&dmx->dmxdev); +error_dmxdev_init: + dvb_dmx_release(&dmx->demux); +error_dmx_init: + return ret; +} + +struct aml_dvb *aml_get_dvb_device(void) +{ + return &aml_dvb_device; +} +EXPORT_SYMBOL(aml_get_dvb_device); + +static int dvb_dsc_open(struct inode *inode, struct file *file) +{ + int err; + + err = dvb_generic_open(inode, file); + if (err < 0) + return err; + + return 0; +} + +static void dsc_channel_alloc(struct aml_dsc *dsc, int id, unsigned int pid) +{ + struct aml_dsc_channel *ch = &dsc->channel[id]; + + ch->used = 1; + ch->work_mode = -1; + ch->id = id; + ch->pid = pid; + ch->flags = 0; + ch->dsc = dsc; + ch->aes_mode = -1; + + dsc_set_pid(ch, ch->pid); +} + +static void dsc_channel_free(struct aml_dsc_channel *ch) +{ + if (!ch->used) + return; + + ch->used = 0; + dsc_set_pid(ch, 0x1fff); + dsc_release(); + + ch->pid = 0x1fff; + ch->flags = 0; + ch->work_mode = -1; + ch->aes_mode = -1; +} + +static void dsc_reset(struct aml_dsc *dsc) +{ + int i; + + for (i = 0; i < DSC_COUNT; i++) + dsc_channel_free(&dsc->channel[i]); +} + +static int get_dsc_key_work_mode(enum ca_cw_type cw_type) +{ + int work_mode = 0; + + if (cw_type == CA_CW_DVB_CSA_EVEN || cw_type == CA_CW_DVB_CSA_ODD) + work_mode = DVBCSA_MODE; + else if (cw_type == CA_CW_AES_EVEN || + cw_type == CA_CW_AES_ODD || + cw_type == CA_CW_AES_EVEN_IV || + cw_type == CA_CW_AES_ODD_IV) { + work_mode = CIPLUS_MODE; + } + return work_mode; +} + +/* Check if there are channels run in previous mode(aes/dvbcsa) + * in dsc0/ciplus + */ +static void dsc_ciplus_switch_check(struct aml_dsc_channel *ch, + enum ca_cw_type cw_type) +{ + struct aml_dsc *dsc = ch->dsc; + int work_mode = 0; + struct aml_dsc_channel *pch = NULL; + int i; + + work_mode = get_dsc_key_work_mode(cw_type); + if (dsc->work_mode == work_mode) + return; + + dsc->work_mode = work_mode; + + for (i = 0; i < DSC_COUNT; i++) { + pch = &dsc->channel[i]; + if (pch->work_mode != work_mode && pch->work_mode != -1) { + pr_error("Dsc work mode changed,"); + pr_error("but there are still some channels"); + pr_error("run in different mode\n"); + } + } +} + +static int dsc_set_cw(struct aml_dsc *dsc, struct ca_descr_ex *d) +{ + struct aml_dsc_channel *ch; + + if (d->index >= DSC_COUNT) + return -EINVAL; + + ch = &dsc->channel[d->index]; + + switch (d->type) { + case CA_CW_DVB_CSA_EVEN: + memcpy(ch->even, d->cw, 8); + ch->flags &= ~(DSC_SET_AES_EVEN|DSC_SET_AES_ODD); + ch->flags |= DSC_SET_EVEN; + break; + case CA_CW_DVB_CSA_ODD: + memcpy(ch->odd, d->cw, 8); + ch->flags &= ~(DSC_SET_AES_EVEN|DSC_SET_AES_ODD); + ch->flags |= DSC_SET_ODD; + break; + case CA_CW_AES_EVEN: + memcpy(ch->aes_even, d->cw, 16); + ch->flags &= ~(DSC_SET_EVEN|DSC_SET_ODD); + ch->flags |= DSC_SET_AES_EVEN; + break; + case CA_CW_AES_ODD: + memcpy(ch->aes_odd, d->cw, 16); + ch->flags &= ~(DSC_SET_EVEN|DSC_SET_ODD); + ch->flags |= DSC_SET_AES_ODD; + break; + default: + break; + } + + if (d->flags & CA_CW_FROM_KL) + ch->flags = DSC_FROM_KL; + + dsc_set_key(ch, d->flags, d->type, d->cw); + dsc_ciplus_switch_check(ch, d->type); + + return 0; +} + +static int dvb_dsc_do_ioctl(struct file *file, unsigned int cmd, + void *parg) +{ + struct dvb_device *dvbdev = file->private_data; + struct aml_dsc *dsc = dvbdev->priv; + struct aml_dvb *dvb = dsc->dvb; + struct aml_dsc_channel *ch; + int ret = 0; + unsigned long flags; + + spin_lock_irqsave(&dvb->slock, flags); + + switch (cmd) { + case CA_RESET: + dsc_reset(dsc); + break; + case CA_GET_CAP: { + ca_caps_t *cap = parg; + + cap->slot_num = 1; + cap->slot_type = CA_DESCR; + cap->descr_num = DSC_COUNT; + cap->descr_type = 0; + break; + } + case CA_GET_SLOT_INFO: { + ca_slot_info_t *slot = parg; + + slot->num = 1; + slot->type = CA_DESCR; + slot->flags = 0; + break; + } + case CA_GET_DESCR_INFO: { + ca_descr_info_t *descr = parg; + + descr->num = DSC_COUNT; + descr->type = 0; + break; + } + case CA_SET_DESCR: { + ca_descr_t *d = parg; + struct ca_descr_ex dex; + + dex.index = d->index; + dex.type = d->parity ? CA_CW_DVB_CSA_ODD : CA_CW_DVB_CSA_EVEN; + dex.flags = 0; + memcpy(dex.cw, d->cw, sizeof(d->cw)); + + ret = dsc_set_cw(dsc, &dex); + break; + } + case CA_SET_PID: { + ca_pid_t *pi = parg; + int i; + + if (pi->index == -1) { + for (i = 0; i < DSC_COUNT; i++) { + ch = &dsc->channel[i]; + + if (ch->used && (ch->pid == pi->pid)) { + dsc_channel_free(ch); + break; + } + } + } else if ((pi->index >= 0) && (pi->index < DSC_COUNT)) { + ch = &dsc->channel[pi->index]; + + if (pi->pid < 0x1fff) { + if (!ch->used) { + dsc_channel_alloc(dsc, + pi->index, pi->pid); + } + } else { + if (ch->used) + dsc_channel_free(ch); + } + } else { + ret = -EINVAL; + } + break; + } + case CA_SET_DESCR_EX: { + struct ca_descr_ex *d = parg; + + ret = dsc_set_cw(dsc, d); + break; + } + default: + ret = -EINVAL; + break; + } + + spin_unlock_irqrestore(&dvb->slock, flags); + + return ret; +} + +static int dvb_dsc_usercopy(struct file *file, + unsigned int cmd, unsigned long arg, + int (*func)(struct file *file, + unsigned int cmd, void *arg)) +{ + char sbuf[128]; + void *mbuf = NULL; + void *parg = NULL; + int err = -EINVAL; + + /* Copy arguments into temp kernel buffer */ + switch (_IOC_DIR(cmd)) { + case _IOC_NONE: + /* + * For this command, the pointer is actually an integer + * argument. + */ + parg = (void *) arg; + break; + case _IOC_READ: /* some v4l ioctls are marked wrong ... */ + case _IOC_WRITE: + case (_IOC_WRITE | _IOC_READ): + if (_IOC_SIZE(cmd) <= sizeof(sbuf)) { + parg = sbuf; + } else { + /* too big to allocate from stack */ + mbuf = kmalloc(_IOC_SIZE(cmd), GFP_KERNEL); + if (mbuf == NULL) + return -ENOMEM; + parg = mbuf; + } + + err = -EFAULT; + if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd))) + goto out; + break; + } + + /* call driver */ + err = func(file, cmd, parg); + if (err == -ENOIOCTLCMD) + err = -ENOTTY; + + if (err < 0) + goto out; + + /* Copy results into user buffer */ + switch (_IOC_DIR(cmd)) { + case _IOC_READ: + case (_IOC_WRITE | _IOC_READ): + if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd))) + err = -EFAULT; + break; + } + +out: + kfree(mbuf); + return err; +} + +static long dvb_dsc_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + return dvb_dsc_usercopy(file, cmd, arg, dvb_dsc_do_ioctl); +} + +static int dvb_dsc_release(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct aml_dsc *dsc = dvbdev->priv; + struct aml_dvb *dvb = dsc->dvb; + unsigned long flags; + + spin_lock_irqsave(&dvb->slock, flags); + + dsc_reset(dsc); + + spin_unlock_irqrestore(&dvb->slock, flags); + + dvb_generic_release(inode, file); + + return 0; +} + +#ifdef CONFIG_COMPAT +static long dvb_dsc_compat_ioctl(struct file *filp, + unsigned int cmd, unsigned long args) +{ + unsigned long ret; + + args = (unsigned long)compat_ptr(args); + ret = dvb_dsc_ioctl(filp, cmd, args); + return ret; +} +#endif + + +static const struct file_operations dvb_dsc_fops = { + .owner = THIS_MODULE, + .read = NULL, + .write = NULL, + .unlocked_ioctl = dvb_dsc_ioctl, + .open = dvb_dsc_open, + .release = dvb_dsc_release, + .poll = NULL, +#ifdef CONFIG_COMPAT + .compat_ioctl = dvb_dsc_compat_ioctl, +#endif +}; + +static struct dvb_device dvbdev_dsc = { + .priv = NULL, + .users = 1, + .readers = 1, + .writers = 1, + .fops = &dvb_dsc_fops, +}; + +static int aml_dvb_asyncfifo_init(struct aml_dvb *advb, + struct aml_asyncfifo *asyncfifo, int id) +{ + struct resource *res; + char buf[32]; + + if (id == 0) + asyncfifo->asyncfifo_irq = INT_ASYNC_FIFO_FLUSH; + else + asyncfifo->asyncfifo_irq = INT_ASYNC_FIFO2_FLUSH; + + snprintf(buf, sizeof(buf), "dvr%d_irq", id); + res = platform_get_resource_byname(advb->pdev, IORESOURCE_IRQ, buf); + if (res) + asyncfifo->asyncfifo_irq = res->start; + pr_info("%s irq num:%d ", buf, asyncfifo->asyncfifo_irq); + asyncfifo->dvb = advb; + asyncfifo->id = id; + asyncfifo->init = 0; + asyncfifo->flush_size = 256 * 1024; + + return aml_asyncfifo_hw_init(asyncfifo); +} +static void aml_dvb_asyncfifo_release(struct aml_dvb *advb, + struct aml_asyncfifo *asyncfifo) +{ + aml_asyncfifo_hw_deinit(asyncfifo); +} + +static int aml_dvb_dsc_init(struct aml_dvb *advb, + struct aml_dsc *dsc, int id) +{ + int i; + + for (i = 0; i < DSC_COUNT; i++) { + dsc->channel[i].id = i; + dsc->channel[i].used = 0; + dsc->channel[i].flags = 0; + dsc->channel[i].pid = 0x1fff; + dsc->channel[i].dsc = dsc; + } + dsc->dvb = advb; + dsc->id = id; + dsc->source = -1; + dsc->dst = -1; + + /*Register descrambler device */ + return dvb_register_device(&advb->dvb_adapter, &dsc->dev, + &dvbdev_dsc, dsc, DVB_DEVICE_CA, 0); +} +static void aml_dvb_dsc_release(struct aml_dvb *advb, + struct aml_dsc *dsc) +{ + if (dsc->dev) + dvb_unregister_device(dsc->dev); + dsc->dev = NULL; +} + + +/*Show the STB input source*/ +static ssize_t stb_show_source(struct class *class, + struct class_attribute *attr, char *buf) +{ + struct aml_dvb *dvb = &aml_dvb_device; + ssize_t ret = 0; + char *src; + + switch (dvb->stb_source) { + case AM_TS_SRC_TS0: + case AM_TS_SRC_S_TS0: + src = "ts0"; + break; + case AM_TS_SRC_TS1: + case AM_TS_SRC_S_TS1: + src = "ts1"; + break; + case AM_TS_SRC_TS2: + case AM_TS_SRC_S_TS2: + src = "ts2"; + break; + case AM_TS_SRC_HIU: + src = "hiu"; + break; + case AM_TS_SRC_DMX0: + src = "dmx0"; + break; + case AM_TS_SRC_DMX1: + src = "dmx1"; + break; + case AM_TS_SRC_DMX2: + src = "dmx2"; + break; + default: + src = "disable"; + break; + } + + ret = sprintf(buf, "%s\n", src); + return ret; +} + +/*Set the STB input source*/ +static ssize_t stb_store_source(struct class *class, + struct class_attribute *attr, const char *buf, + size_t size) +{ + dmx_source_t src = -1; + + if (!strncmp("ts0", buf, 3)) + src = DMX_SOURCE_FRONT0; + else if (!strncmp("ts1", buf, 3)) + src = DMX_SOURCE_FRONT1; + else if (!strncmp("ts2", buf, 3)) + src = DMX_SOURCE_FRONT2; + else if (!strncmp("hiu", buf, 3)) + src = DMX_SOURCE_DVR0; + else if (!strncmp("dmx0", buf, 4)) + src = DMX_SOURCE_FRONT0 + 100; + else if (!strncmp("dmx1", buf, 4)) + src = DMX_SOURCE_FRONT1 + 100; + else if (!strncmp("dmx2", buf, 4)) + src = DMX_SOURCE_FRONT2 + 100; + if (src != -1) + aml_stb_hw_set_source(&aml_dvb_device, src); + + return size; +} + +#define CASE_PREFIX + +/*Show the descrambler's input source*/ +#define DSC_SOURCE_FUNC_DECL(i) \ +static ssize_t dsc##i##_show_source(struct class *class, \ + struct class_attribute *attr, char *buf)\ +{\ + struct aml_dvb *dvb = &aml_dvb_device;\ + struct aml_dsc *dsc = &dvb->dsc[i];\ + ssize_t ret = 0;\ + char *src, *dst;\ + switch (dsc->source) {\ + CASE_PREFIX case AM_TS_SRC_DMX0:\ + src = "dmx0";\ + break;\ + CASE_PREFIX case AM_TS_SRC_DMX1:\ + src = "dmx1";\ + break;\ + CASE_PREFIX case AM_TS_SRC_DMX2:\ + src = "dmx2";\ + break;\ + CASE_PREFIX default :\ + src = "bypass";\ + break;\ + } \ + switch (dsc->dst) {\ + CASE_PREFIX case AM_TS_SRC_DMX0:\ + dst = "dmx0";\ + break;\ + CASE_PREFIX case AM_TS_SRC_DMX1:\ + dst = "dmx1";\ + break;\ + CASE_PREFIX case AM_TS_SRC_DMX2:\ + dst = "dmx2";\ + break;\ + CASE_PREFIX default :\ + dst = "bypass";\ + break;\ + } \ + ret = sprintf(buf, "%s-%s\n", src, dst);\ + return ret;\ +} \ +static ssize_t dsc##i##_store_source(struct class *class, \ + struct class_attribute *attr, const char *buf, size_t size)\ +{\ + dmx_source_t src = -1, dst = -1;\ + \ + if (!strncmp("dmx0", buf, 4)) {\ + src = DMX_SOURCE_FRONT0 + 100;\ + } else if (!strncmp("dmx1", buf, 4)) {\ + src = DMX_SOURCE_FRONT1 + 100;\ + } else if (!strncmp("dmx2", buf, 4)) {\ + src = DMX_SOURCE_FRONT2 + 100;\ + } \ + if (buf[4] == '-') {\ + if (!strncmp("dmx0", buf+5, 4)) {\ + dst = DMX_SOURCE_FRONT0 + 100;\ + } else if (!strncmp("dmx1", buf+5, 4)) {\ + dst = DMX_SOURCE_FRONT1 + 100;\ + } else if (!strncmp("dmx2", buf+5, 4)) {\ + dst = DMX_SOURCE_FRONT2 + 100;\ + } \ + } \ + else \ + dst = src; \ + aml_dsc_hw_set_source(&aml_dvb_device.dsc[i], src, dst);\ + if (i == 0) \ + aml_ciplus_hw_set_source(src); \ + return size;\ +} + +/*Show free descramblers count*/ +#define DSC_FREE_FUNC_DECL(i) \ +static ssize_t dsc##i##_show_free_dscs(struct class *class, \ + struct class_attribute *attr, char *buf) \ +{ \ + struct aml_dvb *dvb = &aml_dvb_device; \ + int fid, count; \ + ssize_t ret = 0; \ + unsigned long flags;\ +\ + spin_lock_irqsave(&dvb->slock, flags); \ + count = 0; \ + for (fid = 0; fid < DSC_COUNT; fid++) { \ + if (!dvb->dsc[i].channel[fid].used) \ + count++; \ + } \ + spin_unlock_irqrestore(&dvb->slock, flags); \ +\ + ret = sprintf(buf, "%d\n", count); \ + return ret; \ +} + +#if DSC_DEV_COUNT > 0 + DSC_SOURCE_FUNC_DECL(0) + DSC_FREE_FUNC_DECL(0) +#endif +#if DSC_DEV_COUNT > 1 + DSC_SOURCE_FUNC_DECL(1) + DSC_FREE_FUNC_DECL(1) +#endif + +/*Show the TS output source*/ +static ssize_t tso_show_source(struct class *class, + struct class_attribute *attr, char *buf) +{ + struct aml_dvb *dvb = &aml_dvb_device; + ssize_t ret = 0; + char *src; + + switch (dvb->tso_source) { + case AM_TS_SRC_TS0: + case AM_TS_SRC_S_TS0: + src = "ts0"; + break; + case AM_TS_SRC_TS1: + case AM_TS_SRC_S_TS1: + src = "ts1"; + break; + case AM_TS_SRC_TS2: + case AM_TS_SRC_S_TS2: + src = "ts2"; + break; + case AM_TS_SRC_HIU: + src = "hiu"; + break; + case AM_TS_SRC_DMX0: + src = "dmx0"; + break; + case AM_TS_SRC_DMX1: + src = "dmx1"; + break; + case AM_TS_SRC_DMX2: + src = "dmx2"; + break; + default: + src = "default"; + break; + } + + ret = sprintf(buf, "%s\n", src); + return ret; +} + +/*Set the TS output source*/ +static ssize_t tso_store_source(struct class *class, + struct class_attribute *attr, const char *buf, + size_t size) +{ + dmx_source_t src = -1; + + if (!strncmp("ts0", buf, 3)) + src = DMX_SOURCE_FRONT0; + else if (!strncmp("ts1", buf, 3)) + src = DMX_SOURCE_FRONT1; + else if (!strncmp("ts2", buf, 3)) + src = DMX_SOURCE_FRONT2; + else if (!strncmp("hiu", buf, 3)) + src = DMX_SOURCE_DVR0; + else if (!strncmp("dmx0", buf, 4)) + src = DMX_SOURCE_FRONT0 + 100; + else if (!strncmp("dmx1", buf, 4)) + src = DMX_SOURCE_FRONT1 + 100; + else if (!strncmp("dmx2", buf, 4)) + src = DMX_SOURCE_FRONT2 + 100; + + aml_tso_hw_set_source(&aml_dvb_device, src); + + return size; +} + +/*Show PCR*/ +#define DEMUX_PCR_FUNC_DECL(i) \ +static ssize_t demux##i##_show_pcr(struct class *class, \ + struct class_attribute *attr, char *buf)\ +{\ + int f = 0;\ + if (i == 0)\ + f = READ_MPEG_REG(PCR_DEMUX);\ + else if (i == 1)\ + f = READ_MPEG_REG(PCR_DEMUX_2);\ + else if (i == 2)\ + f = READ_MPEG_REG(PCR_DEMUX_3);\ + return sprintf(buf, "%08x\n", f);\ +} + +/*Show the STB input source*/ +#define DEMUX_SOURCE_FUNC_DECL(i) \ +static ssize_t demux##i##_show_source(struct class *class, \ + struct class_attribute *attr, char *buf)\ +{\ + struct aml_dvb *dvb = &aml_dvb_device;\ + struct aml_dmx *dmx = &dvb->dmx[i];\ + ssize_t ret = 0;\ + char *src;\ + switch (dmx->source) {\ + CASE_PREFIX case AM_TS_SRC_TS0:\ + CASE_PREFIX case AM_TS_SRC_S_TS0:\ + src = "ts0";\ + break;\ + CASE_PREFIX case AM_TS_SRC_TS1:\ + CASE_PREFIX case AM_TS_SRC_S_TS1:\ + src = "ts1";\ + break;\ + CASE_PREFIX case AM_TS_SRC_TS2:\ + CASE_PREFIX case AM_TS_SRC_S_TS2:\ + src = "ts2";\ + break;\ + CASE_PREFIX case AM_TS_SRC_HIU:\ + src = "hiu";\ + break;\ + CASE_PREFIX default :\ + src = "";\ + break;\ + } \ + ret = sprintf(buf, "%s\n", src);\ + return ret;\ +} \ +static ssize_t demux##i##_store_source(struct class *class, \ + struct class_attribute *attr, const char *buf, size_t size)\ +{\ + dmx_source_t src = -1;\ + \ + if (!strncmp("ts0", buf, 3)) {\ + src = DMX_SOURCE_FRONT0;\ + } else if (!strncmp("ts1", buf, 3)) {\ + src = DMX_SOURCE_FRONT1;\ + } else if (!strncmp("ts2", buf, 3)) {\ + src = DMX_SOURCE_FRONT2;\ + } else if (!strncmp("hiu", buf, 3)) {\ + src = DMX_SOURCE_DVR0;\ + } \ + if (src != -1) {\ + aml_dmx_hw_set_source(aml_dvb_device.dmx[i].dmxdev.demux, src);\ + } \ + return size;\ +} + +/*Show free filters count*/ +#define DEMUX_FREE_FILTERS_FUNC_DECL(i) \ +static ssize_t demux##i##_show_free_filters(struct class *class, \ + struct class_attribute *attr, char *buf)\ +{\ + struct aml_dvb *dvb = &aml_dvb_device;\ + struct dvb_demux *dmx = &dvb->dmx[i].demux;\ + int fid, count;\ + ssize_t ret = 0;\ + if (mutex_lock_interruptible(&dmx->mutex)) \ + return -ERESTARTSYS; \ + count = 0;\ + for (fid = 0; fid < dmx->filternum; fid++) {\ + if (!dmx->filter[fid].state != DMX_STATE_FREE)\ + count++;\ + } \ + mutex_unlock(&dmx->mutex);\ + ret = sprintf(buf, "%d\n", count);\ + return ret;\ +} + +/*Show filter users count*/ +#define DEMUX_FILTER_USERS_FUNC_DECL(i) \ +static ssize_t demux##i##_show_filter_users(struct class *class, \ + struct class_attribute *attr, char *buf)\ +{\ + struct aml_dvb *dvb = &aml_dvb_device;\ + struct aml_dmx *dmx = &dvb->dmx[i];\ + int dmxdevfid, count;\ + ssize_t ret = 0;\ + unsigned long flags;\ + spin_lock_irqsave(&dvb->slock, flags);\ + count = 0;\ + for (dmxdevfid = 0; dmxdevfid < dmx->dmxdev.filternum; dmxdevfid++) {\ + if (dmx->dmxdev.filter[dmxdevfid].state >= \ + DMXDEV_STATE_ALLOCATED)\ + count++;\ + } \ + if (count > dmx->demux_filter_user) {\ + count = dmx->demux_filter_user;\ + } else{\ + dmx->demux_filter_user = count;\ + } \ + spin_unlock_irqrestore(&dvb->slock, flags);\ + ret = sprintf(buf, "%d\n", count);\ + return ret;\ +} \ +static ssize_t demux##i##_store_filter_used(struct class *class, \ + struct class_attribute *attr, const char *buf, size_t size)\ +{\ + struct aml_dvb *dvb = &aml_dvb_device;\ + struct aml_dmx *dmx = &dvb->dmx[i];\ + unsigned long filter_used;\ + unsigned long flags;/*char *endp;*/\ + /*filter_used = simple_strtol(buf, &endp, 0);*/\ + int ret = kstrtol(buf, 0, &filter_used);\ + spin_lock_irqsave(&dvb->slock, flags);\ + if (ret == 0 && filter_used) {\ + if (dmx->demux_filter_user < FILTER_COUNT)\ + dmx->demux_filter_user++;\ + } else {\ + if (dmx->demux_filter_user > 0)\ + dmx->demux_filter_user--;\ + } \ + spin_unlock_irqrestore(&dvb->slock, flags);\ + return size;\ +} + +/*Show ts header*/ +#define DEMUX_TS_HEADER_FUNC_DECL(i) \ +static ssize_t demux##i##_show_ts_header(struct class *class, \ + struct class_attribute *attr, char *buf)\ +{\ + int hdr = 0;\ + if (i == 0)\ + hdr = READ_MPEG_REG(TS_HEAD_1);\ + else if (i == 1)\ + hdr = READ_MPEG_REG(TS_HEAD_1_2);\ + else if (i == 2)\ + hdr = READ_MPEG_REG(TS_HEAD_1_3);\ + return sprintf(buf, "%08x\n", hdr);\ +} + +/*Show channel activity*/ +#define DEMUX_CHANNEL_ACTIVITY_FUNC_DECL(i) \ +static ssize_t demux##i##_show_channel_activity(struct class *class, \ + struct class_attribute *attr, char *buf)\ +{\ + int f = 0;\ + if (i == 0)\ + f = READ_MPEG_REG(DEMUX_CHANNEL_ACTIVITY);\ + else if (i == 1)\ + f = READ_MPEG_REG(DEMUX_CHANNEL_ACTIVITY_2);\ + else if (i == 2)\ + f = READ_MPEG_REG(DEMUX_CHANNEL_ACTIVITY_3);\ + return sprintf(buf, "%08x\n", f);\ +} + +#define DEMUX_RESET_FUNC_DECL(i) \ +static ssize_t demux##i##_reset_store(struct class *class, \ + struct class_attribute *attr, \ + const char *buf, size_t size)\ +{\ + if (!strncmp("1", buf, 1)) { \ + struct aml_dvb *dvb = &aml_dvb_device; \ + pr_info("Reset demux["#i"], call dmx_reset_dmx_hw\n"); \ + dmx_reset_dmx_id_hw_ex(dvb, i, 0); \ + } \ + return size; \ +} + +/*DVR record mode*/ +#define DVR_MODE_FUNC_DECL(i) \ +static ssize_t dvr##i##_show_mode(struct class *class, \ + struct class_attribute *attr, char *buf)\ +{\ + struct aml_dvb *dvb = &aml_dvb_device;\ + struct aml_dmx *dmx = &dvb->dmx[i];\ + ssize_t ret = 0;\ + char *mode;\ + if (dmx->dump_ts_select) {\ + mode = "ts";\ + } else {\ + mode = "pid";\ + } \ + ret = sprintf(buf, "%s\n", mode);\ + return ret;\ +} \ +static ssize_t dvr##i##_store_mode(struct class *class, \ + struct class_attribute *attr, const char *buf, size_t size)\ +{\ + struct aml_dvb *dvb = &aml_dvb_device;\ + struct aml_dmx *dmx = &dvb->dmx[i];\ + int dump_ts_select = -1;\ + \ + if (!strncmp("pid", buf, 3) && dmx->dump_ts_select) {\ + dump_ts_select = 0;\ + } else if (!strncmp("ts", buf, 2) && !dmx->dump_ts_select) {\ + dump_ts_select = 1;\ + } \ + if (dump_ts_select != -1) {\ + aml_dmx_hw_set_dump_ts_select(\ + aml_dvb_device.dmx[i].dmxdev.demux, dump_ts_select);\ + } \ + return size;\ +} + +#if DMX_DEV_COUNT > 0 + DEMUX_PCR_FUNC_DECL(0) + DEMUX_SOURCE_FUNC_DECL(0) + DEMUX_FREE_FILTERS_FUNC_DECL(0) + DEMUX_FILTER_USERS_FUNC_DECL(0) + DVR_MODE_FUNC_DECL(0) + DEMUX_TS_HEADER_FUNC_DECL(0) + DEMUX_CHANNEL_ACTIVITY_FUNC_DECL(0) + DEMUX_RESET_FUNC_DECL(0) +#endif +#if DMX_DEV_COUNT > 1 + DEMUX_PCR_FUNC_DECL(1) + DEMUX_SOURCE_FUNC_DECL(1) + DEMUX_FREE_FILTERS_FUNC_DECL(1) + DEMUX_FILTER_USERS_FUNC_DECL(1) + DVR_MODE_FUNC_DECL(1) + DEMUX_TS_HEADER_FUNC_DECL(1) + DEMUX_CHANNEL_ACTIVITY_FUNC_DECL(1) + DEMUX_RESET_FUNC_DECL(1) +#endif +#if DMX_DEV_COUNT > 2 + DEMUX_PCR_FUNC_DECL(2) + DEMUX_SOURCE_FUNC_DECL(2) + DEMUX_FREE_FILTERS_FUNC_DECL(2) + DEMUX_FILTER_USERS_FUNC_DECL(2) + DVR_MODE_FUNC_DECL(2) + DEMUX_TS_HEADER_FUNC_DECL(2) + DEMUX_CHANNEL_ACTIVITY_FUNC_DECL(2) + DEMUX_RESET_FUNC_DECL(2) +#endif + +/*Show the async fifo source*/ +#define ASYNCFIFO_SOURCE_FUNC_DECL(i) \ +static ssize_t asyncfifo##i##_show_source(struct class *class, \ + struct class_attribute *attr, char *buf)\ +{\ + struct aml_dvb *dvb = &aml_dvb_device;\ + struct aml_asyncfifo *afifo = &dvb->asyncfifo[i];\ + ssize_t ret = 0;\ + char *src;\ + switch (afifo->source) {\ + CASE_PREFIX case AM_DMX_0:\ + src = "dmx0";\ + break;\ + CASE_PREFIX case AM_DMX_1:\ + src = "dmx1";\ + break; \ + CASE_PREFIX case AM_DMX_2:\ + src = "dmx2";\ + break;\ + CASE_PREFIX default :\ + src = "";\ + break;\ + } \ + ret = sprintf(buf, "%s\n", src);\ + return ret;\ +} \ +static ssize_t asyncfifo##i##_store_source(struct class *class, \ + struct class_attribute *attr, const char *buf, size_t size)\ +{\ + enum aml_dmx_id_t src = -1;\ + \ + if (!strncmp("dmx0", buf, 4)) {\ + src = AM_DMX_0;\ + } else if (!strncmp("dmx1", buf, 4)) {\ + src = AM_DMX_1;\ + } else if (!strncmp("dmx2", buf, 4)) {\ + src = AM_DMX_2;\ + } \ + if (src != -1) {\ + aml_asyncfifo_hw_set_source(&aml_dvb_device.asyncfifo[i], src);\ + } \ + return size;\ +} + +#if ASYNCFIFO_COUNT > 0 +ASYNCFIFO_SOURCE_FUNC_DECL(0) +#endif +#if ASYNCFIFO_COUNT > 1 + ASYNCFIFO_SOURCE_FUNC_DECL(1) +#endif +/*Show the async fifo flush size*/ +#define ASYNCFIFO_FLUSHSIZE_FUNC_DECL(i) \ +static ssize_t asyncfifo##i##_show_flush_size(struct class *class, \ + struct class_attribute *attr, char *buf)\ +{\ + struct aml_dvb *dvb = &aml_dvb_device;\ + struct aml_asyncfifo *afifo = &dvb->asyncfifo[i];\ + ssize_t ret = 0;\ + ret = sprintf(buf, "%d\n", afifo->flush_size);\ + return ret;\ +} \ +static ssize_t asyncfifo##i##_store_flush_size(struct class *class, \ + struct class_attribute *attr, \ + const char *buf, size_t size)\ +{\ + struct aml_dvb *dvb = &aml_dvb_device;\ + struct aml_asyncfifo *afifo = &dvb->asyncfifo[i];\ + /*int fsize = simple_strtol(buf, NULL, 10);*/\ + int fsize = 0;\ + long value;\ + int ret = kstrtol(buf, 0, &value);\ + if (ret == 0)\ + fsize = value;\ + if (fsize != afifo->flush_size) {\ + afifo->flush_size = fsize;\ + aml_asyncfifo_hw_reset(&aml_dvb_device.asyncfifo[i]);\ + } \ + return size;\ +} + +#if ASYNCFIFO_COUNT > 0 +ASYNCFIFO_FLUSHSIZE_FUNC_DECL(0) +#endif + +#if ASYNCFIFO_COUNT > 1 + ASYNCFIFO_FLUSHSIZE_FUNC_DECL(1) +#endif +/*Reset the Demux*/ +static ssize_t demux_do_reset(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size) +{ + if (!strncmp("1", buf, 1)) { + struct aml_dvb *dvb = &aml_dvb_device; + unsigned long flags; + + spin_lock_irqsave(&dvb->slock, flags); + pr_dbg("Reset demux, call dmx_reset_hw\n"); + dmx_reset_hw_ex(dvb, 0); + spin_unlock_irqrestore(&dvb->slock, flags); + } + + return size; +} + +/*Show the Video PTS value*/ +static ssize_t demux_show_video_pts(struct class *class, + struct class_attribute *attr, char *buf) +{ + struct aml_dvb *dvb = &aml_dvb_device; + ssize_t ret = 0; + + ret = sprintf(buf, "%u\n", aml_dmx_get_video_pts(dvb)); + + return ret; +} + +/*Show the Audio PTS value*/ +static ssize_t demux_show_audio_pts(struct class *class, + struct class_attribute *attr, char *buf) +{ + struct aml_dvb *dvb = &aml_dvb_device; + ssize_t ret = 0; + + ret = sprintf(buf, "%u\n", aml_dmx_get_audio_pts(dvb)); + + return ret; +} + +/*Show the First Video PTS value*/ +static ssize_t demux_show_first_video_pts(struct class *class, + struct class_attribute *attr, + char *buf) +{ + struct aml_dvb *dvb = &aml_dvb_device; + ssize_t ret = 0; + + ret = sprintf(buf, "%u\n", aml_dmx_get_first_video_pts(dvb)); + + return ret; +} + +/*Show the First Audio PTS value*/ +static ssize_t demux_show_first_audio_pts(struct class *class, + struct class_attribute *attr, + char *buf) +{ + struct aml_dvb *dvb = &aml_dvb_device; + ssize_t ret = 0; + + ret = sprintf(buf, "%u\n", aml_dmx_get_first_audio_pts(dvb)); + + return ret; +} + +static ssize_t stb_show_hw_setting(struct class *class, + struct class_attribute *attr, char *buf) +{ + int r, total = 0; + int i; + struct aml_dvb *dvb = &aml_dvb_device; + int invert, ctrl; + + for (i = 0; i < TS_IN_COUNT; i++) { + struct aml_ts_input *ts = &dvb->ts[i]; + + if (ts->s2p_id != -1) + invert = dvb->s2p[ts->s2p_id].invert; + else + invert = 0; + + ctrl = ts->control; + + r = sprintf(buf, "ts%d %s control: 0x%x invert: 0x%x\n", i, + ts->mode == AM_TS_DISABLE ? "disable" : + (ts->mode == AM_TS_SERIAL ? "serial" : + "parallel"), ctrl, invert); + buf += r; + total += r; + } + + return total; +} + +static ssize_t stb_store_hw_setting(struct class *class, + struct class_attribute *attr, + const char *buf, size_t count) +{ + int id, ctrl, invert, r, mode; + char mname[32]; + char pname[32]; + unsigned long flags; + struct aml_ts_input *ts; + struct aml_dvb *dvb = &aml_dvb_device; + + r = sscanf(buf, "%d %s %x %x", &id, mname, &ctrl, &invert); + if (r != 4) + return -EINVAL; + + if (id < 0 || id >= TS_IN_COUNT) + return -EINVAL; + + if ((mname[0] == 's') || (mname[0] == 'S')) { + sprintf(pname, "s_ts%d", id); + mode = AM_TS_SERIAL; + } else if ((mname[0] == 'p') || (mname[0] == 'P')) { + sprintf(pname, "p_ts%d", id); + mode = AM_TS_PARALLEL; + } else + mode = AM_TS_DISABLE; + + spin_lock_irqsave(&dvb->slock, flags); + + ts = &dvb->ts[id]; + + if ((mode == AM_TS_SERIAL) && (ts->mode != AM_TS_SERIAL)) { + int i; + int scnt = 0; + + for (i = 0; i < TS_IN_COUNT; i++) { + if (dvb->ts[i].s2p_id != -1) + scnt++; + } + + if (scnt >= S2P_COUNT) + pr_error("no free s2p\n"); + else + ts->s2p_id = scnt; + } + + if ((mode != AM_TS_SERIAL) || (ts->s2p_id != -1)) { + if (ts->pinctrl) { + devm_pinctrl_put(ts->pinctrl); + ts->pinctrl = NULL; + } + + ts->pinctrl = devm_pinctrl_get_select(&dvb->pdev->dev, pname); +/* if(IS_ERR_VALUE(ts->pinctrl))*/ +/* ts->pinctrl = NULL;*/ + ts->mode = mode; + ts->control = ctrl; + + if (mode == AM_TS_SERIAL) + dvb->s2p[ts->s2p_id].invert = invert; + else + ts->s2p_id = -1; + } + + spin_unlock_irqrestore(&dvb->slock, flags); + + return count; +} + +static struct class_attribute aml_stb_class_attrs[] = { + __ATTR(hw_setting, 0664, stb_show_hw_setting, + stb_store_hw_setting), + __ATTR(source, 0664, stb_show_source, + stb_store_source), + __ATTR(tso_source, 0644, tso_show_source, + tso_store_source), +#define DEMUX_SOURCE_ATTR_PCR(i)\ + __ATTR(demux##i##_pcr, 0644, demux##i##_show_pcr, NULL) +#define DEMUX_SOURCE_ATTR_DECL(i)\ + __ATTR(demux##i##_source, 0664,\ + demux##i##_show_source, demux##i##_store_source) +#define DEMUX_FREE_FILTERS_ATTR_DECL(i)\ + __ATTR(demux##i##_free_filters, 0644, \ + demux##i##_show_free_filters, NULL) +#define DEMUX_FILTER_USERS_ATTR_DECL(i)\ + __ATTR(demux##i##_filter_users, 0644, \ + demux##i##_show_filter_users, demux##i##_store_filter_used) +#define DVR_MODE_ATTR_DECL(i)\ + __ATTR(dvr##i##_mode, 0644, dvr##i##_show_mode, \ + dvr##i##_store_mode) +#define DEMUX_TS_HEADER_ATTR_DECL(i)\ + __ATTR(demux##i##_ts_header, 0644, \ + demux##i##_show_ts_header, NULL) +#define DEMUX_CHANNEL_ACTIVITY_ATTR_DECL(i)\ + __ATTR(demux##i##_channel_activity, 0644, \ + demux##i##_show_channel_activity, NULL) +#define DMX_RESET_ATTR_DECL(i)\ + __ATTR(demux##i##_reset, 0644, NULL, \ + demux##i##_reset_store) + +#if DMX_DEV_COUNT > 0 + DEMUX_SOURCE_ATTR_PCR(0), + DEMUX_SOURCE_ATTR_DECL(0), + DEMUX_FREE_FILTERS_ATTR_DECL(0), + DEMUX_FILTER_USERS_ATTR_DECL(0), + DVR_MODE_ATTR_DECL(0), + DEMUX_TS_HEADER_ATTR_DECL(0), + DEMUX_CHANNEL_ACTIVITY_ATTR_DECL(0), + DMX_RESET_ATTR_DECL(0), +#endif +#if DMX_DEV_COUNT > 1 + DEMUX_SOURCE_ATTR_PCR(1), + DEMUX_SOURCE_ATTR_DECL(1), + DEMUX_FREE_FILTERS_ATTR_DECL(1), + DEMUX_FILTER_USERS_ATTR_DECL(1), + DVR_MODE_ATTR_DECL(1), + DEMUX_TS_HEADER_ATTR_DECL(1), + DEMUX_CHANNEL_ACTIVITY_ATTR_DECL(1), + DMX_RESET_ATTR_DECL(1), +#endif +#if DMX_DEV_COUNT > 2 + DEMUX_SOURCE_ATTR_PCR(2), + DEMUX_SOURCE_ATTR_DECL(2), + DEMUX_FREE_FILTERS_ATTR_DECL(2), + DEMUX_FILTER_USERS_ATTR_DECL(2), + DVR_MODE_ATTR_DECL(2), + DEMUX_TS_HEADER_ATTR_DECL(2), + DEMUX_CHANNEL_ACTIVITY_ATTR_DECL(2), + DMX_RESET_ATTR_DECL(2), +#endif + +#define ASYNCFIFO_SOURCE_ATTR_DECL(i)\ + __ATTR(asyncfifo##i##_source, 0664, \ + asyncfifo##i##_show_source, asyncfifo##i##_store_source) +#define ASYNCFIFO_FLUSHSIZE_ATTR_DECL(i)\ + __ATTR(asyncfifo##i##_flush_size, 0664,\ + asyncfifo##i##_show_flush_size, \ + asyncfifo##i##_store_flush_size) +#if ASYNCFIFO_COUNT > 0 + ASYNCFIFO_SOURCE_ATTR_DECL(0), + ASYNCFIFO_FLUSHSIZE_ATTR_DECL(0), +#endif +#if ASYNCFIFO_COUNT > 1 + ASYNCFIFO_SOURCE_ATTR_DECL(1), + ASYNCFIFO_FLUSHSIZE_ATTR_DECL(1), +#endif + + __ATTR(demux_reset, 0644, NULL, demux_do_reset), + __ATTR(video_pts, 0664, demux_show_video_pts, + NULL), + __ATTR(audio_pts, 0664, demux_show_audio_pts, + NULL), + __ATTR(first_video_pts, 0644, demux_show_first_video_pts, + NULL), + __ATTR(first_audio_pts, 0644, demux_show_first_audio_pts, + NULL), + +#define DSC_SOURCE_ATTR_DECL(i)\ + __ATTR(dsc##i##_source, 0664,\ + dsc##i##_show_source, dsc##i##_store_source) +#define DSC_FREE_ATTR_DECL(i) \ + __ATTR(dsc##i##_free_dscs, 0644, \ + dsc##i##_show_free_dscs, NULL) + +#if DSC_DEV_COUNT > 0 + DSC_SOURCE_ATTR_DECL(0), + DSC_FREE_ATTR_DECL(0), +#endif +#if DSC_DEV_COUNT > 1 + DSC_SOURCE_ATTR_DECL(1), + DSC_FREE_ATTR_DECL(1), +#endif + + __ATTR_NULL +}; + +static struct class aml_stb_class = { + .name = "stb", + .class_attrs = aml_stb_class_attrs, +}; + +/* + *extern int aml_regist_dmx_class(void); + *extern int aml_unregist_dmx_class(void); + */ +/* + *void afifo_reset(int v) + *{ + * if (v) + * reset_control_assert(aml_dvb_afifo_reset_ctl); + * else + * reset_control_deassert(aml_dvb_afifo_reset_ctl); + *} + */ + +static int aml_dvb_probe(struct platform_device *pdev) +{ + struct aml_dvb *advb; + int i, ret = 0; + struct devio_aml_platform_data *pd_dvb; + + pr_inf("probe amlogic dvb driver\n"); + + /*switch_mod_gate_by_name("demux", 1); */ +#if 0 + /*no used reset ctl to set clk*/ + aml_dvb_demux_reset_ctl = + devm_reset_control_get(&pdev->dev, "demux"); + pr_inf("dmx rst ctl = %p\n", aml_dvb_demux_reset_ctl); + reset_control_deassert(aml_dvb_demux_reset_ctl); + + aml_dvb_afifo_reset_ctl = + devm_reset_control_get(&pdev->dev, "asyncfifo"); + pr_inf("asyncfifo rst ctl = %p\n", aml_dvb_afifo_reset_ctl); + reset_control_deassert(aml_dvb_afifo_reset_ctl); + + aml_dvb_ahbarb0_reset_ctl = + devm_reset_control_get(&pdev->dev, "ahbarb0"); + pr_inf("ahbarb0 rst ctl = %p\n", aml_dvb_ahbarb0_reset_ctl); + reset_control_deassert(aml_dvb_ahbarb0_reset_ctl); + + aml_dvb_uparsertop_reset_ctl = + devm_reset_control_get(&pdev->dev, "uparsertop"); + pr_inf("uparsertop rst ctl = %p\n", aml_dvb_uparsertop_reset_ctl); + reset_control_deassert(aml_dvb_uparsertop_reset_ctl); +#else + + if (get_cpu_type() < MESON_CPU_MAJOR_ID_G12A) + { + aml_dvb_demux_clk = + devm_clk_get(&pdev->dev, "demux"); + if (IS_ERR_OR_NULL(aml_dvb_demux_clk)) { + dev_err(&pdev->dev, "get demux clk fail\n"); + return -1; + } + clk_prepare_enable(aml_dvb_demux_clk); + + aml_dvb_afifo_clk = + devm_clk_get(&pdev->dev, "asyncfifo"); + if (IS_ERR_OR_NULL(aml_dvb_afifo_clk)) { + dev_err(&pdev->dev, "get asyncfifo clk fail\n"); + return -1; + } + clk_prepare_enable(aml_dvb_afifo_clk); + + aml_dvb_ahbarb0_clk = + devm_clk_get(&pdev->dev, "ahbarb0"); + if (IS_ERR_OR_NULL(aml_dvb_ahbarb0_clk)) { + dev_err(&pdev->dev, "get ahbarb0 clk fail\n"); + return -1; + } + clk_prepare_enable(aml_dvb_ahbarb0_clk); + + aml_dvb_uparsertop_clk = + devm_clk_get(&pdev->dev, "uparsertop"); + if (IS_ERR_OR_NULL(aml_dvb_uparsertop_clk)) { + dev_err(&pdev->dev, "get uparsertop clk fail\n"); + return -1; + } + clk_prepare_enable(aml_dvb_uparsertop_clk); + } + else + { + amports_switch_gate("demux", 1); + amports_switch_gate("ahbarb0", 1); + amports_switch_gate("parser_top", 1); + } +#endif + advb = &aml_dvb_device; + memset(advb, 0, sizeof(aml_dvb_device)); + + spin_lock_init(&advb->slock); + + advb->dev = &pdev->dev; + advb->pdev = pdev; + advb->stb_source = -1; + advb->tso_source = -1; + + for (i = 0; i < DMX_DEV_COUNT; i++) { + advb->dmx[i].dmx_irq = -1; + advb->dmx[i].dvr_irq = -1; + } + +#ifdef CONFIG_OF + if (pdev->dev.of_node) { + int s2p_id = 0; + char buf[32]; + const char *str; + u32 value; + + for (i = 0; i < TS_IN_COUNT; i++) { + + advb->ts[i].mode = AM_TS_DISABLE; + advb->ts[i].s2p_id = -1; + advb->ts[i].pinctrl = NULL; + memset(buf, 0, 32); + snprintf(buf, sizeof(buf), "ts%d", i); + ret = + of_property_read_string(pdev->dev.of_node, buf, + &str); + if (!ret) { + if (!strcmp(str, "serial")) { + pr_inf("%s: serial\n", buf); + + if (s2p_id >= S2P_COUNT) + pr_error("no free s2p\n"); + else { + snprintf(buf, sizeof(buf), + "s_ts%d", i); + advb->ts[i].mode = AM_TS_SERIAL; + advb->ts[i].pinctrl = + devm_pinctrl_get_select + (&pdev->dev, buf); + advb->ts[i].s2p_id = s2p_id; + + s2p_id++; + } + } else if (!strcmp(str, "parallel")) { + pr_inf("%s: parallel\n", buf); + memset(buf, 0, 32); + snprintf(buf, sizeof(buf), "p_ts%d", i); + advb->ts[i].mode = AM_TS_PARALLEL; + advb->ts[i].pinctrl = + devm_pinctrl_get_select(&pdev->dev, + buf); + } else { + advb->ts[i].mode = AM_TS_DISABLE; + advb->ts[i].pinctrl = NULL; + } + + /* if(IS_ERR_VALUE(advb->ts[i].pinctrl)) */ + /* advb->ts[i].pinctrl = NULL; */ + } + memset(buf, 0, 32); + snprintf(buf, sizeof(buf), "ts%d_control", i); + ret = + of_property_read_u32(pdev->dev.of_node, buf, + &value); + if (!ret) { + pr_inf("%s: 0x%x\n", buf, value); + advb->ts[i].control = value; + } else { + pr_inf("read error:%s: 0x%x\n", buf, value); + } + + if (advb->ts[i].s2p_id != -1) { + memset(buf, 0, 32); + snprintf(buf, sizeof(buf), "ts%d_invert", i); + ret = + of_property_read_u32(pdev->dev.of_node, buf, + &value); + if (!ret) { + pr_inf("%s: 0x%x\n", buf, value); + advb->s2p[advb->ts[i].s2p_id].invert = + value; + } + } + } + memset(buf, 0, 32); + snprintf(buf, sizeof(buf), "ts_out_invert"); + ret = + of_property_read_u32(pdev->dev.of_node, buf, + &value); + if (!ret) { + pr_inf("%s: 0x%x\n", buf, value); + advb->ts_out_invert = value; + } + } +#endif + + pd_dvb = (struct devio_aml_platform_data *)advb->dev->platform_data; + + ret = + dvb_register_adapter(&advb->dvb_adapter, CARD_NAME, THIS_MODULE, + advb->dev, adapter_nr); + if (ret < 0) + return ret; + + for (i = 0; i < DMX_DEV_COUNT; i++) + advb->dmx[i].id = -1; + + for (i = 0; idsc[i].id = -1; + + if (get_cpu_type() < MESON_CPU_MAJOR_ID_G12A) { + for (i = 0; i < ASYNCFIFO_COUNT; i++) + advb->asyncfifo[i].id = -1; + } + advb->dvb_adapter.priv = advb; + dev_set_drvdata(advb->dev, advb); + + for (i = 0; i < DSC_DEV_COUNT; i++) { + ret = aml_dvb_dsc_init(advb, &advb->dsc[i], i); + if (ret < 0) + goto error; + } + + for (i = 0; i < DMX_DEV_COUNT; i++) { + ret = aml_dvb_dmx_init(advb, &advb->dmx[i], i); + if (ret < 0) + goto error; + } + if (get_cpu_type() < MESON_CPU_MAJOR_ID_G12A) + { + /*Init the async fifos */ + for (i = 0; i < ASYNCFIFO_COUNT; i++) { + ret = aml_dvb_asyncfifo_init(advb, &advb->asyncfifo[i], i); + if (ret < 0) + goto error; + } + } + aml_regist_dmx_class(); + + if (class_register(&aml_stb_class) < 0) { + pr_error("register class error\n"); + goto error; + } + +#ifdef ENABLE_DEMUX_DRIVER + tsdemux_set_ops(&aml_tsdemux_ops); +#else + tsdemux_set_ops(NULL); +#endif + + //pengcc add for dvb using linux TV frontend api init + { + struct amlfe_exp_config config; + struct i2c_adapter *i2c_adapter = NULL; + char buf[32]; + const char *str = NULL; + struct device_node *node_i2c = NULL; + u32 i2c_addr = 0xFFFFFFFF; + + for (i=0; idev.of_node, buf, &str); + if (ret) { + continue; + } + if (!strcmp(str,"internal")) + { + config.set_mode = 0; + frontend[i] = dvb_attach(aml_dtvdm_attach,&config); + if (frontend[i] == NULL) { + pr_error("dvb attach demod error\n"); + goto error_fe; + } else { + pr_inf("dtvdemod attatch sucess\n"); + s_demod_type[i] = DEMOD_INTERNAL; + } + + memset(buf, 0, 32); + snprintf(buf, sizeof(buf), "fe%d_tuner",i); + ret = of_property_read_string(pdev->dev.of_node, buf, &str); + if (ret) { + // pr_error("tuner%d type error\n",i); + ret = 0; + continue; + } + memset(buf, 0, 32); + snprintf(buf, sizeof(buf), "fe%d_i2c_adap_id",i); + node_i2c = of_parse_phandle(pdev->dev.of_node,buf,0); + if (!node_i2c) { + pr_error("tuner_i2c_adap_id error\n"); + } else { + i2c_adapter = of_find_i2c_adapter_by_node(node_i2c); + of_node_put(node_i2c); + if (i2c_adapter == NULL) { + pr_error("i2c_get_adapter error\n"); + goto error_fe; + } + } + + memset(buf, 0, 32); + snprintf(buf, sizeof(buf), "fe%d_tuner_i2c_addr",i); + ret = of_property_read_u32(pdev->dev.of_node, buf,&i2c_addr); + if (ret) { + pr_error("i2c_addr error\n"); + } + /* define general-purpose callback pointer */ + frontend[i]->callback = NULL; + + if (!strcmp(str,"si2151_tuner")) { + if (!dvb_attach(si2151_attach, frontend[i],i2c_adapter,i2c_addr)) { + pr_error("dvb attach tuner error\n"); + goto error_fe; + } else { + pr_inf("si2151 attach sucess\n"); + s_tuner_type[i] = TUNER_SI2151; + } + }else if(!strcmp(str,"mxl661_tuner")) { + if (!dvb_attach(mxl661_attach, frontend[i],i2c_adapter,i2c_addr)) { + pr_error("dvb attach mxl661_attach tuner error\n"); + goto error_fe; + } else { + pr_inf("mxl661_attach attach sucess\n"); + s_tuner_type[i] = TUNER_MXL661; + } + }else if(!strcmp(str,"si2159_tuner")) { + if (!dvb_attach(si2159_attach, frontend[i],i2c_adapter,i2c_addr)) { + pr_error("dvb attach si2159_attach tuner error\n"); + goto error_fe; + } else { + pr_inf("si2159_attach attach sucess\n"); + s_tuner_type[i] = TUNER_SI2159; + } + }else { + pr_error("can't support tuner type: %s\n",str); + } + ret = dvb_register_frontend(&advb->dvb_adapter, frontend[i]); + if (ret) { + pr_error("register dvb frontend failed\n"); + goto error_fe; + } + } else if(!strcmp(str,"external")) { + const char *name = NULL; + struct amlfe_demod_config config; + + config.dev_id = i; + memset(buf, 0, 32); + snprintf(buf, sizeof(buf), "fe%d_demod",i); + ret = of_property_read_string(pdev->dev.of_node, buf, &name); + if (ret) { + ret = 0; + continue; + } + + memset(buf, 0, 32); + snprintf(buf, sizeof(buf), "fe%d_i2c_adap_id",i); + node_i2c = of_parse_phandle(pdev->dev.of_node,buf,0); + if (!node_i2c) { + pr_error("demod%d_i2c_adap_id error\n", i); + } else { + config.i2c_adap = of_find_i2c_adapter_by_node(node_i2c); + of_node_put(node_i2c); + if (config.i2c_adap == NULL) { + pr_error("i2c_get_adapter error\n"); + goto error_fe; + } + } + + memset(buf, 0, 32); + snprintf(buf, sizeof(buf), "fe%d_demod_i2c_addr",i); + ret = of_property_read_u32(pdev->dev.of_node, buf,&config.i2c_addr); + if (ret) { + pr_error("i2c_addr error\n"); + goto error_fe; + } + + memset(buf, 0, 32); + snprintf(buf, sizeof(buf), "fe%d_ts",i); + ret = of_property_read_u32(pdev->dev.of_node, buf,&config.ts); + if (ret) { + pr_error("ts error\n"); + goto error_fe; + } + + memset(buf, 0, 32); + snprintf(buf, sizeof(buf), "fe%d_reset_gpio",i); + ret = of_property_read_string(pdev->dev.of_node, buf, &str); + if (!ret) { + config.reset_gpio = + of_get_named_gpio_flags(pdev->dev.of_node, + buf, 0, NULL); + pr_inf("%s: %d\n", buf, config.reset_gpio); + } else { + config.reset_gpio = -1; + pr_error("cannot find resource \"%s\"\n", buf); + goto error_fe; + } + + memset(buf, 0, 32); + snprintf(buf, sizeof(buf), "fe%d_reset_value",i); + ret = of_property_read_u32(pdev->dev.of_node, buf,&config.reset_value); + if (ret) { + pr_error("reset_value error\n"); + goto error_fe; + } + + if (!strcmp(name,"Atbm8881")) { + frontend[i] = dvb_attach(atbm8881_attach,&config); + if (frontend[i] == NULL) { + pr_error("dvb attach demod error\n"); + goto error_fe; + } else { + pr_inf("dtvdemod attatch sucess\n"); + s_demod_type[i] = DEMOD_ATBM8881; + } + } + if (frontend[i]) { + ret = dvb_register_frontend(&advb->dvb_adapter, frontend[i]); + if (ret) { + pr_error("register dvb frontend failed\n"); + goto error_fe; + } + } + } + } + return 0; +error_fe: + for (i=0; iasyncfifo[i].id != -1) + aml_dvb_asyncfifo_release(advb, &advb->asyncfifo[i]); + } + } + for (i = 0; i < DMX_DEV_COUNT; i++) { + if (advb->dmx[i].id != -1) + aml_dvb_dmx_release(advb, &advb->dmx[i]); + } + + for (i = 0; i < DSC_DEV_COUNT; i++) { + if (advb->dsc[i].id != -1) + aml_dvb_dsc_release(advb, &advb->dsc[i]); + } + + dvb_unregister_adapter(&advb->dvb_adapter); + + return ret; +} +static int aml_dvb_remove(struct platform_device *pdev) +{ + struct aml_dvb *advb = (struct aml_dvb *)dev_get_drvdata(&pdev->dev); + int i; + + for (i=0; iasyncfifo[i].id != -1) + aml_dvb_asyncfifo_release(advb, &advb->asyncfifo[i]); + } + } + + for (i = 0; i < DMX_DEV_COUNT; i++) { + pr_error("remove demx %d, id is %d\n",i,advb->dmx[i].id); + if (advb->dmx[i].id != -1) + aml_dvb_dmx_release(advb, &advb->dmx[i]); + } + + for (i = 0; i < DSC_DEV_COUNT; i++) { + if (advb->dsc[i].id != -1) + aml_dvb_dsc_release(advb, &advb->dsc[i]); + } + dvb_unregister_adapter(&advb->dvb_adapter); + + for (i = 0; i < TS_IN_COUNT; i++) { + if (advb->ts[i].pinctrl && !IS_ERR_VALUE(advb->ts[i].pinctrl)) + devm_pinctrl_put(advb->ts[i].pinctrl); + } + + /*switch_mod_gate_by_name("demux", 0); */ +#if 0 + reset_control_assert(aml_dvb_uparsertop_reset_ctl); + reset_control_assert(aml_dvb_ahbarb0_reset_ctl); + reset_control_assert(aml_dvb_afifo_reset_ctl); + reset_control_assert(aml_dvb_demux_reset_ctl); +#else +#if 1 + if (get_cpu_type() < MESON_CPU_MAJOR_ID_G12A) + { + clk_disable_unprepare(aml_dvb_uparsertop_clk); + clk_disable_unprepare(aml_dvb_ahbarb0_clk); + clk_disable_unprepare(aml_dvb_afifo_clk); + clk_disable_unprepare(aml_dvb_demux_clk); + } + else + { + amports_switch_gate("demux", 0); + amports_switch_gate("ahbarb0", 0); + amports_switch_gate("parser_top", 0); + } +#endif +#endif + return 0; +} + +static int aml_dvb_suspend(struct platform_device *dev, pm_message_t state) +{ + return 0; +} + +static int aml_dvb_resume(struct platform_device *dev) +{ + struct aml_dvb *dvb = &aml_dvb_device; + int i; + + for (i = 0; i < DMX_DEV_COUNT; i++) + dmx_reset_dmx_id_hw_ex(dvb, i, 0); + + pr_inf("dvb resume\n"); + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id aml_dvb_dt_match[] = { + { + .compatible = "amlogic, dvb", + }, + {}, +}; +#endif /*CONFIG_OF */ + +static struct platform_driver aml_dvb_driver = { + .probe = aml_dvb_probe, + .remove = aml_dvb_remove, + .suspend = aml_dvb_suspend, + .resume = aml_dvb_resume, + .driver = { + .name = "amlogic-dvb", + .owner = THIS_MODULE, +#ifdef CONFIG_OF + .of_match_table = aml_dvb_dt_match, +#endif + } +}; + +static int __init aml_dvb_init(void) +{ + pr_dbg("aml dvb init\n"); + return platform_driver_register(&aml_dvb_driver); +} + +static void __exit aml_dvb_exit(void) +{ + pr_dbg("aml dvb exit\n"); + platform_driver_unregister(&aml_dvb_driver); +} + +/*Get the STB source demux*/ +static struct aml_dmx *get_stb_dmx(void) +{ + struct aml_dvb *dvb = &aml_dvb_device; + struct aml_dmx *dmx = NULL; + int i; + + switch (dvb->stb_source) { + case AM_TS_SRC_DMX0: + dmx = &dvb->dmx[0]; + break; + case AM_TS_SRC_DMX1: + dmx = &dvb->dmx[1]; + break; + case AM_TS_SRC_DMX2: + dmx = &dvb->dmx[2]; + break; + default: + for (i = 0; i < DMX_DEV_COUNT; i++) { + dmx = &dvb->dmx[i]; + if (dmx->source == dvb->stb_source) + return dmx; + } + break; + } + + return dmx; +} + +static int aml_tsdemux_reset(void) +{ + struct aml_dvb *dvb = &aml_dvb_device; + unsigned long flags; + + spin_lock_irqsave(&dvb->slock, flags); + if (dvb->reset_flag) { + struct aml_dmx *dmx = get_stb_dmx(); + + dvb->reset_flag = 0; + if (dmx) + dmx_reset_dmx_hw_ex_unlock(dvb, dmx, 0); + } + spin_unlock_irqrestore(&dvb->slock, flags); + + return 0; +} + +static int aml_tsdemux_set_reset_flag(void) +{ + struct aml_dvb *dvb = &aml_dvb_device; + unsigned long flags; + + spin_lock_irqsave(&dvb->slock, flags); + dvb->reset_flag = 1; + spin_unlock_irqrestore(&dvb->slock, flags); + + return 0; + +} + +/*Add the amstream irq handler*/ +static int aml_tsdemux_request_irq(irq_handler_t handler, void *data) +{ + struct aml_dvb *dvb = &aml_dvb_device; + struct aml_dmx *dmx; + unsigned long flags; + + spin_lock_irqsave(&dvb->slock, flags); + + dmx = get_stb_dmx(); + if (dmx) { + dmx->irq_handler = handler; + dmx->irq_data = data; + } + + spin_unlock_irqrestore(&dvb->slock, flags); + + return 0; +} + +/*Free the amstream irq handler*/ +static int aml_tsdemux_free_irq(void) +{ + struct aml_dvb *dvb = &aml_dvb_device; + struct aml_dmx *dmx; + unsigned long flags; + + spin_lock_irqsave(&dvb->slock, flags); + + dmx = get_stb_dmx(); + if (dmx) { + dmx->irq_handler = NULL; + dmx->irq_data = NULL; + } + + spin_unlock_irqrestore(&dvb->slock, flags); + + return 0; +} + +/*Reset the video PID*/ +static int aml_tsdemux_set_vid(int vpid) +{ + struct aml_dvb *dvb = &aml_dvb_device; + struct aml_dmx *dmx; + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&dvb->slock, flags); + dmx = get_stb_dmx(); + if (dmx) { + if (dmx->vid_chan != -1) { + dmx_free_chan(dmx, dmx->vid_chan); + dmx->vid_chan = -1; + } + + if ((vpid >= 0) && (vpid < 0x1FFF)) { + dmx->vid_chan = + dmx_alloc_chan(dmx, DMX_TYPE_TS, + DMX_PES_VIDEO, vpid); + if (dmx->vid_chan == -1) + ret = -1; + } + } + + spin_unlock_irqrestore(&dvb->slock, flags); + + return ret; +} + +/*Reset the audio PID*/ +static int aml_tsdemux_set_aid(int apid) +{ + struct aml_dvb *dvb = &aml_dvb_device; + struct aml_dmx *dmx; + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&dvb->slock, flags); + dmx = get_stb_dmx(); + if (dmx) { + if (dmx->aud_chan != -1) { + dmx_free_chan(dmx, dmx->aud_chan); + dmx->aud_chan = -1; + } + + if ((apid >= 0) && (apid < 0x1FFF)) { + dmx->aud_chan = + dmx_alloc_chan(dmx, DMX_TYPE_TS, + DMX_PES_AUDIO, apid); + if (dmx->aud_chan == -1) + ret = -1; + } + } + + spin_unlock_irqrestore(&dvb->slock, flags); + + return ret; +} + +/*Reset the subtitle PID*/ +static int aml_tsdemux_set_sid(int spid) +{ + struct aml_dvb *dvb = &aml_dvb_device; + struct aml_dmx *dmx; + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&dvb->slock, flags); + + dmx = get_stb_dmx(); + if (dmx) { + if (dmx->sub_chan != -1) { + dmx_free_chan(dmx, dmx->sub_chan); + dmx->sub_chan = -1; + } + + if ((spid >= 0) && (spid < 0x1FFF)) { + dmx->sub_chan = + dmx_alloc_chan(dmx, DMX_TYPE_TS, + DMX_PES_SUBTITLE, spid); + if (dmx->sub_chan == -1) + ret = -1; + } + } + + spin_unlock_irqrestore(&dvb->slock, flags); + + return ret; +} + +static int aml_tsdemux_set_pcrid(int pcrpid) +{ + struct aml_dvb *dvb = &aml_dvb_device; + struct aml_dmx *dmx; + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&dvb->slock, flags); + + dmx = get_stb_dmx(); + if (dmx) { + if (dmx->pcr_chan != -1) { + dmx_free_chan(dmx, dmx->pcr_chan); + dmx->pcr_chan = -1; + } + + if ((pcrpid >= 0) && (pcrpid < 0x1FFF)) { + dmx->pcr_chan = + dmx_alloc_chan(dmx, DMX_TYPE_TS, + DMX_PES_PCR, pcrpid); + if (dmx->pcr_chan == -1) + ret = -1; + } + } + + spin_unlock_irqrestore(&dvb->slock, flags); + + return ret; +} + +static int aml_tsdemux_set_skipbyte(int skipbyte) +{ + struct aml_dvb *dvb = &aml_dvb_device; + unsigned long flags; + + spin_lock_irqsave(&dvb->slock, flags); + aml_dmx_set_skipbyte(dvb, skipbyte); + spin_unlock_irqrestore(&dvb->slock, flags); + + return 0; +} + +static int aml_tsdemux_set_demux(int id) +{ + struct aml_dvb *dvb = &aml_dvb_device; + + aml_dmx_set_demux(dvb, id); + return 0; +} + +module_init(aml_dvb_init); +module_exit(aml_dvb_exit); + +MODULE_DESCRIPTION("driver for the AMLogic DVB card"); +MODULE_AUTHOR("AMLOGIC"); +MODULE_LICENSE("GPL"); diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb.h b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb.h new file mode 100644 index 000000000000..f04c5c915a47 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb.h @@ -0,0 +1,357 @@ +#ifndef _AML_DVB_H_ +#define _AML_DVB_H_ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_HAS_EARLYSUSPEND +#include +#endif + + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define TS_IN_COUNT 3 +#define S2P_COUNT 2 + +#define DMX_DEV_COUNT 3 +#define FE_DEV_COUNT 2 +#define CHANNEL_COUNT 31 +#define FILTER_COUNT 31 +#define FILTER_LEN 15 +#define DSC_DEV_COUNT 2 +#define DSC_COUNT 8 +#define SEC_BUF_GRP_COUNT 4 +#define SEC_BUF_BUSY_SIZE 4 +#define SEC_BUF_COUNT (SEC_BUF_GRP_COUNT*8) +#define ASYNCFIFO_COUNT 2 + +enum aml_dmx_id_t { + AM_DMX_0 = 0, + AM_DMX_1, + AM_DMX_2, + AM_DMX_MAX, +}; + +enum aml_ts_source_t { + AM_TS_SRC_TS0, + AM_TS_SRC_TS1, + AM_TS_SRC_TS2, + AM_TS_SRC_S_TS0, + AM_TS_SRC_S_TS1, + AM_TS_SRC_S_TS2, + AM_TS_SRC_HIU, + AM_TS_SRC_DMX0, + AM_TS_SRC_DMX1, + AM_TS_SRC_DMX2 +}; + +struct aml_sec_buf { + unsigned long addr; + int len; +}; + +struct aml_channel { + int type; + enum dmx_ts_pes pes_type; + int pid; + int used; + int filter_count; + struct dvb_demux_feed *feed; + struct dvb_demux_feed *dvr_feed; +}; + +struct aml_filter { + int chan_id; + int used; + struct dmx_section_filter *filter; + u8 value[FILTER_LEN]; + u8 maskandmode[FILTER_LEN]; + u8 maskandnotmode[FILTER_LEN]; + u8 neq; +}; + +#define DVBCSA_MODE 0 +#define CIPLUS_MODE 1 +#define AES_CBC_MODE 0 +#define AES_ECB_MODE 1 + +#define DSC_SET_EVEN 1 +#define DSC_SET_ODD 2 +#define DSC_SET_AES_EVEN 4 +#define DSC_SET_AES_ODD 8 +#define DSC_FROM_KL 16 + +struct aml_dsc_channel { + int pid; + u8 even[8]; + u8 odd[8]; + u8 aes_even[16]; + u8 aes_odd[16]; + int used; + int flags; + int id; + struct aml_dsc *dsc; + int work_mode; + int aes_mode; +}; + +struct aml_dsc { + struct dvb_device *dev; + struct aml_dsc_channel channel[DSC_COUNT]; + enum aml_ts_source_t source; + enum aml_ts_source_t dst; + struct aml_dvb *dvb; + int id; + int work_mode; +}; + +struct aml_smallsec { + struct aml_dmx *dmx; + + int enable; + int bufsize; +#define SS_BUFSIZE_DEF (16*4*256) /*16KB*/ + long buf; + long buf_map; +}; + +struct aml_dmxtimeout { + struct aml_dmx *dmx; + + int enable; + + int timeout; +#define DTO_TIMEOUT_DEF (9000) /*0.5s*/ + u32 ch_disable; +#define DTO_CHDIS_VAS (0xfffffff8) /*v/a/s only*/ + int match; + + int trigger; +}; + +struct aml_dmx { + struct dvb_demux demux; + struct dmxdev dmxdev; + int id; + int feed_count; + int chan_count; + enum aml_ts_source_t source; + int init; + int record; + struct dmx_frontend hw_fe[DMX_DEV_COUNT]; + struct dmx_frontend mem_fe; + struct dvb_net dvb_net; + int dmx_irq; + int dvr_irq; + struct tasklet_struct dmx_tasklet; + struct tasklet_struct dvr_tasklet; + unsigned long sec_pages; + unsigned long sec_pages_map; + int sec_total_len; + struct aml_sec_buf sec_buf[SEC_BUF_COUNT]; + unsigned long pes_pages; + unsigned long pes_pages_map; + int pes_buf_len; + unsigned long sub_pages; + unsigned long sub_pages_map; + int sub_buf_len; + struct aml_channel channel[CHANNEL_COUNT+1]; + struct aml_filter filter[FILTER_COUNT+1]; + irq_handler_t irq_handler; + void *irq_data; + int aud_chan; + int vid_chan; + int sub_chan; + int pcr_chan; + u32 section_busy[SEC_BUF_BUSY_SIZE]; + struct dvb_frontend *fe; + int int_check_count; + u32 int_check_time; + int in_tune; + int error_check; + int dump_ts_select; + int sec_buf_watchdog_count[SEC_BUF_COUNT]; + + struct aml_smallsec smallsec; + struct aml_dmxtimeout timeout; + + int demux_filter_user; + + unsigned long sec_cnt[3]; + unsigned long sec_cnt_match[3]; + unsigned long sec_cnt_crc_fail[3]; + #define SEC_CNT_HW (0) + #define SEC_CNT_SW (1) + #define SEC_CNT_SS (2) + #define SEC_CNT_MAX (3) + + int crc_check_count; + u32 crc_check_time; +}; + +struct aml_asyncfifo { + int id; + int init; + int asyncfifo_irq; + enum aml_dmx_id_t source; + unsigned long pages; + unsigned long pages_map; + int buf_len; + int buf_toggle; + int buf_read; + int flush_size; + struct tasklet_struct asyncfifo_tasklet; + struct aml_dvb *dvb; +}; + +enum{ + AM_TS_DISABLE, + AM_TS_PARALLEL, + AM_TS_SERIAL +}; + +struct aml_ts_input { + int mode; + struct pinctrl *pinctrl; + int control; + int s2p_id; +}; + +struct aml_s2p { + int invert; +}; + +struct aml_swfilter { + int user; + struct aml_dmx *dmx; + struct aml_asyncfifo *afifo; + + struct dvb_ringbuffer rbuf; +#define SF_BUFFER_SIZE (10*188*1024) + + u8 wrapbuf[188]; + int track_dmx; +}; + +struct aml_dvb { + struct dvb_device dvb_dev; + + struct aml_ts_input ts[TS_IN_COUNT]; + struct aml_s2p s2p[S2P_COUNT]; + struct aml_dmx dmx[DMX_DEV_COUNT]; + struct aml_dsc dsc[DSC_DEV_COUNT]; + struct aml_asyncfifo asyncfifo[ASYNCFIFO_COUNT]; + struct dvb_adapter dvb_adapter; + struct device *dev; + struct platform_device *pdev; + enum aml_ts_source_t stb_source; + enum aml_ts_source_t tso_source; + int dmx_init; + int reset_flag; + spinlock_t slock; + struct timer_list watchdog_timer; + int dmx_watchdog_disable[DMX_DEV_COUNT]; + struct aml_swfilter swfilter; + int ts_out_invert; +}; + + +/*AMLogic demux interface*/ +extern int aml_dmx_hw_init(struct aml_dmx *dmx); +extern int aml_dmx_hw_deinit(struct aml_dmx *dmx); +extern int aml_dmx_hw_start_feed(struct dvb_demux_feed *dvbdmxfeed); +extern int aml_dmx_hw_stop_feed(struct dvb_demux_feed *dvbdmxfeed); +extern int aml_dmx_hw_set_source(struct dmx_demux *demux, + dmx_source_t src); +extern int aml_stb_hw_set_source(struct aml_dvb *dvb, dmx_source_t src); +extern int aml_dsc_hw_set_source(struct aml_dsc *dsc, + dmx_source_t src, dmx_source_t dst); +extern int aml_tso_hw_set_source(struct aml_dvb *dvb, dmx_source_t src); +extern int aml_dmx_set_skipbyte(struct aml_dvb *dvb, int skipbyte); +extern int aml_dmx_set_demux(struct aml_dvb *dvb, int id); +extern int aml_dmx_hw_set_dump_ts_select + (struct dmx_demux *demux, int dump_ts_select); + +extern int dmx_alloc_chan(struct aml_dmx *dmx, int type, + int pes_type, int pid); +extern void dmx_free_chan(struct aml_dmx *dmx, int cid); + +extern int dmx_get_ts_serial(enum aml_ts_source_t src); + +/*AMLogic dsc interface*/ +extern int dsc_set_pid(struct aml_dsc_channel *ch, int pid); +extern int dsc_set_key(struct aml_dsc_channel *ch, int flags, + enum ca_cw_type type, u8 *key); +extern void dsc_release(void); +extern int aml_ciplus_hw_set_source(int src); + +/*AMLogic ASYNC FIFO interface*/ +extern int aml_asyncfifo_hw_init(struct aml_asyncfifo *afifo); +extern int aml_asyncfifo_hw_deinit(struct aml_asyncfifo *afifo); +extern int aml_asyncfifo_hw_set_source(struct aml_asyncfifo *afifo, + enum aml_dmx_id_t src); +extern int aml_asyncfifo_hw_reset(struct aml_asyncfifo *afifo); + +/*Get the Audio & Video PTS*/ +extern u32 aml_dmx_get_video_pts(struct aml_dvb *dvb); +extern u32 aml_dmx_get_audio_pts(struct aml_dvb *dvb); +extern u32 aml_dmx_get_first_video_pts(struct aml_dvb *dvb); +extern u32 aml_dmx_get_first_audio_pts(struct aml_dvb *dvb); + +/*Get the DVB device*/ +extern struct aml_dvb *aml_get_dvb_device(void); + +extern int aml_regist_dmx_class(void); +extern int aml_unregist_dmx_class(void); + +struct devio_aml_platform_data { + int (*io_setup)(void *); + int (*io_cleanup)(void *); + int (*io_power)(void *, int enable); + int (*io_reset)(void *, int enable); +}; + +void get_aml_dvb(struct aml_dvb *dvb_device); + +/*Reset the demux device*/ +void dmx_reset_hw(struct aml_dvb *dvb); +void dmx_reset_hw_ex(struct aml_dvb *dvb, int reset_irq); + +/*Reset the individual demux*/ +void dmx_reset_dmx_hw(struct aml_dvb *dvb, int id); +void dmx_reset_dmx_id_hw_ex(struct aml_dvb *dvb, int id, int reset_irq); +void dmx_reset_dmx_id_hw_ex_unlock(struct aml_dvb *dvb, int id, int reset_irq); +void dmx_reset_dmx_hw_ex(struct aml_dvb *dvb, + struct aml_dmx *dmx, + int reset_irq); +void dmx_reset_dmx_hw_ex_unlock(struct aml_dvb *dvb, + struct aml_dmx *dmx, + int reset_irq); + +#endif + diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb_reg.h b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb_reg.h new file mode 100644 index 000000000000..180b3d897e96 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb_reg.h @@ -0,0 +1,56 @@ +/* + * drivers/amlogic/dvb_tv/dvb_reg.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef _DVB_REG_H_ +#define _DVB_REG_H_ + +#include + +#include + +#define ID_STB_CBUS_BASE 0 +#define ID_SMARTCARD_REG_BASE 1 +#define ID_ASYNC_FIFO_REG_BASE 2 +#define ID_ASYNC_FIFO2_REG_BASE 3 +#define ID_RESET_BASE 4 +#define ID_PARSER_SUB_START_PTR_BASE 5 + +long aml_stb_get_base(int id); +#include "c_stb_define.h" +#include "c_stb_regs_define.h" + +#define WRITE_MPEG_REG(_r, _v) aml_write_cbus(_r, _v) +#define READ_MPEG_REG(_r) aml_read_cbus(_r) + +#define WRITE_CBUS_REG(_r, _v) aml_write_cbus(_r, _v) +#define READ_CBUS_REG(_r) aml_read_cbus(_r) + +#define WRITE_VCBUS_REG(_r, _v) aml_write_vcbus(_r, _v) +#define READ_VCBUS_REG(_r) aml_read_vcbus(_r) + +#define BASE_IRQ 32 +#define AM_IRQ(reg) (reg + BASE_IRQ) +#define INT_DEMUX AM_IRQ(23) +#define INT_DEMUX_1 AM_IRQ(5) +#define INT_DEMUX_2 AM_IRQ(21) //AM_IRQ(53) +#define INT_ASYNC_FIFO_FILL AM_IRQ(18) +#define INT_ASYNC_FIFO_FLUSH AM_IRQ(19) +#define INT_ASYNC_FIFO2_FILL AM_IRQ(24) +#define INT_ASYNC_FIFO2_FLUSH AM_IRQ(25) + +#endif + diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_define.h b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_define.h new file mode 100644 index 000000000000..a5309d52753c --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_define.h @@ -0,0 +1,1163 @@ +/* ----------------------------------------------------------------------*/ +/* This file is automatically generated from the script:*/ +/**/ +/* ./create_stb_define_for_C_code.pl*/ +/**/ +/* and was applied to the file*/ +/**/ +/* ./stb_define.h*/ +/**/ +/* DO NOT EDIT!!!!!*/ +/* ----------------------------------------------------------------------*/ +/**/ +#ifdef C_STB_DEFINE_H +#else +#define C_STB_DEFINE_H + +/*=================================================*/ +/* STB Registers Start*/ +/*=================================================*/ +/* -----------------------------------------------*/ +/*#define STB_CBUS_BASE 0x1600*/ +/* -----------------------------------------------*/ +/* There are two instantiations under one CBUS slave. + * Each CBUS slave can support*/ +/* 256 registers. + * Each demux is allocated 128 registers so set the offset in*/ +/* the middle*/ +/* Copy this define but don't add a base address*/ +/*#define DEMUX_1_OFFSET 0x00*/ +/*#define DEMUX_2_OFFSET 0x50*/ +/*#define DEMUX_3_OFFSET 0xa0*/ +/*======================================================*/ +/* STB TOP Registers (8'hf0 - 8'hf7)*/ +/*======================================================*/ +/* bit 30:28 -- ciplus_o_sel*/ +/* bit 27:26 -- ciplus_i_sel*/ +/* bit 25 -- use FAIL fro TS2*/ +/* bit 24 -- use FAIL fro TS1*/ +/* bit 23 -- use FAIL fro TS0*/ +/* bit 22 -- invert fec_error for S2P1*/ +/* bit 21 -- invert fec_data for S2P1*/ +/* bit 20 -- invert fec_sync for S2P1*/ +/* bit 19 -- invert fec_valid for S2P1*/ +/* bit 18 -- invert fec_clk for S2P1*/ +/* bit 17:16 -- fec_s_sel for S2P1 + * 00 - select TS0, 01 -- select TS1, 10 -- select TS2, 11 - reserved*/ +/* Bit 15 -- enable_des_pl_clk*/ +/* Bit 14:13 -- reserved*/ +/* Bit 12:10 -- ts_out_select, + * 0-TS0, 1-TS1, 2-TS2, 3,4-Reserved, 5-S2P1, 6-S2P0, 7-File*/ +/* bit 9:8 -- des_i_sel 00 -- select demux0 as des input, +* 01 -- select_demux1, 10 -- select_demux2, 11 - reserved*/ +/* bit 7 -- enable_des_pl*/ +/* bit 6 -- invert fec_error for S2P0*/ +/* bit 5 -- invert fec_data for S2P0*/ +/* bit 4 -- invert fec_sync for S2P0*/ +/* bit 3 -- invert fec_valid for S2P0*/ +/* bit 2 -- invert fec_clk for S2P0*/ +/* bit 1:0 -- fec_s_sel for S2P0 + * 00 - select TS0, 01 -- select TS1, 10 -- select TS2, 11 - reserved*/ +/*#define STB_TOP_CONFIG (STB_CBUS_BASE + 0xf0) // 0x16f0*/ +/*----------- bit define -----------*/ +#define INVERT_S2P1_FEC_ERROR 22 +#define INVERT_S2P1_FEC_DATA 21 +#define INVERT_S2P1_FEC_SYNC 20 +#define INVERT_S2P1_FEC_VALID 19 +#define INVERT_S2P1_FEC_CLK 18 +#define S2P1_FEC_SERIAL_SEL 16 +#define ENABLE_DES_PL_CLK 15 +#define TS_OUTPUT_SOURCE 10 +#define DES_INPUT_SEL 8 +#define ENABLE_DES_PL 7 +#define INVERT_S2P0_FEC_ERROR 6 +#define INVERT_S2P0_FEC_DATA 5 +#define INVERT_S2P0_FEC_SYNC 4 +#define INVERT_S2P0_FEC_VALID 3 +#define INVERT_S2P0_FEC_CLK 2 +#define S2P0_FEC_SERIAL_SEL 0 + +/* 31:28 - s2p1_clk_div*/ +/* 27:24 - s2p0_clk_div*/ +/* 23 - s2p1_disable*/ +/* 22 - s2p0_disable*/ +/* 21 - Reserved*/ +/* 20 -- TS_OUT_error_INVERT*/ +/* 19 -- TS_OUT_data_INVERT*/ +/* 18 -- TS_OUT_sync_INVERT*/ +/* 17 -- TS_OUT_valid_INVERT*/ +/* 16 -- TS_OUT_clk_INVERT*/ +/* 15:8 -- TS_package_length_sub_1 (default : 187)*/ +/* 7:0 -- fec_sync_byte (default : 0x47)*/ +/*#define TS_TOP_CONFIG (STB_CBUS_BASE + 0xf1) // 0x16f1*/ +/*----------- bit define -----------*/ +#define TS_OUT_CLK_INVERT 16 +#define TS_PACKAGE_LENGTH_SUB_1 8 +#define FEC_DEFAULT_SYNC_BYTE 0 + +/* Bit 25:24 -- transport_scrambling_control_odd_2 // should be 3*/ +/* Bit 23:16 -- file_m2ts_skip_bytes*/ +/* Bit 15:8 -- des_out_dly*/ +/* Bit 7:6 -- transport_scrambling_control_odd // should be 3*/ +/* Bit 5 -- ts_hiu_enable*/ +/* Bit 4:0 -- fec_clk_div*/ +/*#define TS_FILE_CONFIG (STB_CBUS_BASE + 0xf2) // 0x16f2*/ +/*----------- bit define -----------*/ +#define TRANSPORT_SCRAMBLING_CONTROL_ODD_2 24 +#define FILE_M2TS_SKIP_BYTES 16 +#define DES_OUT_DLY 8 +#define TRANSPORT_SCRAMBLING_CONTROL_ODD 6 +#define TS_HIU_ENABLE 5 +#define FEC_FILE_CLK_DIV 0 + +/* Bit 19:14 -- des_2 ts pl state -- Read Only*/ +/* Bit 13:8 -- des ts pl state -- Read Only*/ +/* Bit 3:0 PID index to 8 PID to get key-set*/ +/* auto increse after TS_PL_PID_DATA read/write*/ +/*#define TS_PL_PID_INDEX (STB_CBUS_BASE + 0xf3) // 0x16f3*/ +/*----------- bit define -----------*/ +#define DES_TS_PL_STATE 8 +#define DES_2_TS_PL_STATE 14 + +/* Bit 13 -- PID match disble*/ +/* Bit 12:0 -- PID*/ +/*#define TS_PL_PID_DATA (STB_CBUS_BASE + 0xf4) // 0x16f4*/ +/*----------- bit define -----------*/ +#define PID_MATCH_DISABLE_HIGH 29 +#define PID_MATCH_HIGH 16 +#define PID_MATCH_DISABLE_LOW 13 +#define PID_MATCH_LOW 0 + +/*#define COMM_DESC_KEY0 + * (STB_CBUS_BASE + 0xf5) // 0x16f5 + Common descrambler key (key bits[63:32])*/ +/*#define COMM_DESC_KEY1 + * (STB_CBUS_BASE + 0xf6) // 0x16f6 + Common descrambler key (key bits[31:0])*/ +/*#define COMM_DESC_KEY_RW + * (STB_CBUS_BASE + 0xf7) // 0x16f7 // bits[3:0] + * point to the address to write the key + * {COMM_DESC_KEY3,...,COMM_DESC_KEY0}*/ +/* Writing this register writes the key to RAM*/ + +/* bit 15:8 - des_out_dly_2*/ +/* bit 7 - reserved*/ +/* Bit 6-- enable_des_pl_clk_2*/ +/* bit 5 - enable_des_pl_2*/ +/* bit 4:2 -- use_des_2 bit[2] -- demux0, bit[3] -- demux1, bit[4] -- demux2*/ +/* bit 1:0 -- des_i_sel_2 00 -- select_fec_0, 01 -- select_fec_1, + * 10 -- select_fec_2, 11 - reserved*/ +/*#define COMM_DESC_2_CTL (STB_CBUS_BASE + 0xff) *//*0x16ff*/ + +/*=======================================================*/ +/* Multiple STB Registers (8'h00 - 8'h45)*/ +/*=======================================================*/ +/* STB registers are 8'h0x*/ +/* Bit 15:0 -- version number : 0x0002 (v0.01)*/ +/*#define STB_VERSION + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x00) // 0x1600 // read only*/ +/*#define STB_VERSION_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x00) // 0x1650 // read only*/ +/*#define STB_VERSION_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x00) // 0x16a0 // read only*/ + +/*#define STB_TEST_REG + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x01) // 0x1601*/ +/*#define STB_TEST_REG_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x01) // 0x1651*/ +/*#define STB_TEST_REG_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x01) // 0x16a1*/ + +/* Bit 15 -- fec_core_select 1 - select descramble output*/ +/* Bit 14:12 - fec_select + * 0-TS0, 1-TS1, 2-TS2, 3,4-Reserved, 5-S2P1, 6-S2P0, 7-File*/ +/* Bit 11 -- FEC_CLK*/ +/* Bit 10 -- SOP*/ +/* Bit 9 -- D_VALID*/ +/* Bit 8 -- D_FAIL*/ +/* Bit 7:0 -- D_DATA 7:0*/ +/*#define FEC_INPUT_CONTROL + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x02) // 0x1602*/ +/*#define FEC_INPUT_CONTROL_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x02) // 0x1652*/ +/*#define FEC_INPUT_CONTROL_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x02) // 0x16a2*/ +/*----------- bit define -----------*/ +#define FEC_CORE_SEL 15 +#define FEC_SEL 12 +#define FEC_INPUT_FEC_CLK 11 +#define FEC_INPUT_SOP 10 +#define FEC_INPUT_D_VALID 9 +#define FEC_INPUT_D_FAIL 8 + +/*#define FEC_INPUT_DATA + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x03) // 0x1603 // read only*/ +/*#define FEC_INPUT_DATA_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x03) // 0x1653 // read only*/ +/*#define FEC_INPUT_DATA_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x03) // 0x16a3 // read only*/ + +/* bit 31 -- enable_free_clk_fec_data_valid*/ +/* bit 30 -- enable_free_clk_stb_reg*/ +/* bit 29 -- always_use_pes_package_length*/ +/* bit 28 -- disable_pre_incomplete_section_fix*/ +/* bit 27 -- pointer_field_multi_pre_en*/ +/* bit 26 -- ignore_pre_incomplete_section*/ +/* bit 25 -- video2_enable*/ +/* bit 24:22 -- video2_type*/ +/* bit 21 -- do_not_trust_pes_package_length*/ +/* bit 20 (bit 4) -- Bypass use recoder path*/ +/* bit 19 (bit 3) -- clear_PID_continuity_counter_valid*/ +/* bit 18 (bit 2) -- Disable Splicing*/ +/* bit 17 (bit 1) -- Insert PES_STRONG_SYNC in Audio PES*/ +/* bit 16 (bit 0) -- Insert PES_STRONG_SYNC in Video PES*/ +/* Bit 15 - do not trust section length*/ +/* Bit 14 - om cmd push even zero*/ +/* Bit 13 - reserved*/ +/* Bit 12 - SUB, OTHER PES interrupt at beginning of PES*/ +/* Bit 11 - discard_av_package -- for ts_recorder use only*/ +/* Bit 10 - ts_recorder_select 0:after PID filter 1:before PID filter*/ +/* Bit 9 - ts_recorder_enable*/ +/* Bit 8 - (table_id == 0xff) means section_end*/ +/* Bit 7 - do not send uncomplete section*/ +/* Bit 6 - do not discard duplicate package*/ +/* Bit 5 - search SOP when trasport_error_indicator*/ +/* Bit 4 - stb demux enable*/ +/* Bit 3 - do not reset state machine on SOP*/ +/* Bit 2 - search SOP when error happened + * ( when ignore_fail_n_sop, will have this case)*/ +/* Bit 1 - do not use SOP input ( check FEC sync byte instead )*/ +/* Bit 0 - ignore fec_error bit when non sop ( check error on SOP only)*/ +/*#define DEMUX_CONTROL + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x04) // 0x1604*/ +/*#define DEMUX_CONTROL_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x04) // 0x1654*/ +/*#define DEMUX_CONTROL_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x04) // 0x16a4*/ +/*----------- bit define -----------*/ +#define ENABLE_FREE_CLK_FEC_DATA_VALID 31 +#define ENABLE_FREE_CLK_STB_REG 30 +#define BYPASS_USE_RECODER_PATH 20 +#define CLEAR_PID_CONTINUITY_COUNTER_VALID 19 +#define DISABLE_SPLICING 18 +#define INSERT_AUDIO_PES_STRONG_SYNC 17 +#define INSERT_VIDEO_PES_STRONG_SYNC 16 +#define SECTION_LENGTH_UNTRUSTY 15 +#define OM_CMD_PUSH_EVEN_ZERO 14 +#define OTHER_INT_AT_PES_BEGINING 12 +#define DISCARD_AV_PACKAGE 11 +#define TS_RECORDER_SELECT 10 +#define TS_RECORDER_ENABLE 9 +#define SECTION_END_WITH_TABLE_ID 8 +#define SEND_COMPLETE_SECTION_ONLY 7 +#define KEEP_DUPLICATE_PACKAGE 6 +#define SEACH_SOP_ON_TRANSPORT_ERROR 5 +#define STB_DEMUX_ENABLE 4 +#define NO_RESET_ON_SOP 3 +#define SEARCH_SOP_ON_ERROR 2 +#define NOT_USE_OF_SOP_INPUT 1 +#define IGNORE_NONSOP_FEC_ERROR 0 + +/* bit 15:8 demux package length - 1 ( default : 187 )*/ +/* bit 7:0 default is 0x47*/ +/*#define FEC_SYNC_BYTE + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x05) // 0x1605*/ +/*#define FEC_SYNC_BYTE_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x05) // 0x1655*/ +/*#define FEC_SYNC_BYTE_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x05) // 0x16a5*/ + +/**************************************** + * FM Memory Usage : + * 0-15 (32 PID filter target) ---- 15:13-PID type 12:0-PID target or force data + * (force data : 1 will mask corespoding bit, + * 0 will disable this PID filter channel) + * advanced setting -- bit 7:0 + * bit 7 -- PID bit 12:11 compare result force + * bit 6 -- PID bit 10:9 compare result force + * bit 5 -- PID bit 8:7 compare result force + * bit 4 -- PID bit 6:5 compare result force + * bit 3 -- PID bit 4:3 compare result force + * bit 2 -- PID bit 2 compare result force + * bit 1 -- PID bit 1 compare result force + * bit 0 -- PID bit 0 compare result force + * 16-255(15x32 Section filter target) + * For first byte : Table_ID + * ---- 15-Mask High 4-bits + * 14-Mask Low 4-bits + * 13-disable_PID_check + * 12:8-PIDindex + * 7:0-section target (always EQ) + * For rest of bytes : + * ---- 15-Mask 14-EQ/NE 13-disable_PID_check + * ----12:8-PIDindex 7:0-section target (or force data) + * advanced setting -- bit 7:0 force compare result + **************************************************/ +/*----------- bit define -----------*/ +#define PID_TYPE 13 +#define PID_TARGET 0 + +#define SECTION_FIRSTBYTE_MASKHIGH 15 +#define SECTION_FIRSTBYTE_MASKLOW 14 +#define SECTION_FIRSTBYTE_DISABLE_PID_CHECK 13 +#define SECTION_FIRSTBYTE_PID_INDEX 8 +#define SECTION_TARGET 0 + +#define SECTION_RESTBYTE_MASK 15 +#define SECTION_RESTBYTE_MASK_EQ 14 +#define SECTION_RESTBYTE_DISABLE_PID_CHECK 13 +#define SECTION_RESTBYTE_PID_INDEX 8 + +/* bit 31:16 -- filter memory write data hi[31:16]*/ +/* bit 15:0 -- filter memory write data low [15:0]*/ +/*#define FM_WR_DATA + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x06) // 0x1606*/ +/*#define FM_WR_DATA_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x06) // 0x1656*/ +/*#define FM_WR_DATA_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x06) // 0x16a6*/ +/*----------- bit define -----------*/ +#define FM_WR_DATA_HI 16 + +/* bit 31:24 -- advanced setting hi*/ +/* bit 23:16 -- advanced setting low*/ +/* bit 15 -- filter memory write data request*/ +/* bit 7:0 -- filter memory write addr*/ +/*#define FM_WR_ADDR + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x07) // 0x1607*/ +/*#define FM_WR_ADDR_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x07) // 0x1657*/ +/*#define FM_WR_ADDR_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x07) // 0x16a7*/ +/*----------- bit define -----------*/ +#define FM_ADVANCED_SETTING_HI 24 +#define FM_ADVANCED_SETTING_LO 16 +#define FM_WR_DATA_REQUEST 15 + +/* bit 13:8 demux state -- read only*/ +/* bit 7:4 -- maxnum section filter compare address*/ +/* bit 3:0 -- maxnum PID filter compare address*/ +/*#define MAX_FM_COMP_ADDR + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x08) // 0x1608*/ +/*#define MAX_FM_COMP_ADDR_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x08) // 0x1658*/ +/*#define MAX_FM_COMP_ADDR_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x08) // 0x16a8*/ +/*----------- bit define -----------*/ +#define DEMUX_STATE 8 +#define MAX_FM_SECTION_FILTER_COMP_ADDR 4 + +/* bit 15 - transport_error_indicator*/ +/* bit 14 - payload_unit_start_indicator*/ +/* bit 13 - transport_priority*/ +/* bit 12:0 - PID*/ +/*#define TS_HEAD_0 + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x09) // 0x1609*/ +/*#define TS_HEAD_0_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x09) // 0x1659*/ +/*#define TS_HEAD_0_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x09) // 0x16a9*/ +/*----------- bit define -----------*/ +#define TRANSPORT_ERROR_INDICATOR 15 +#define PAYLOAD_UNIT_START_INDICATOR 14 +#define TRANSPORT_PRIORITY 13 + +/* bit 7:6 transport_scrambling_control*/ +/* bit 5:4 adaptation_field_control*/ +/* bit 3:0 continuity_counter*/ +/*#define TS_HEAD_1 + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x0a) // 0x160a*/ +/*#define TS_HEAD_1_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x0a) // 0x165a*/ +/*#define TS_HEAD_1_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x0a) // 0x16aa*/ +/*----------- bit define -----------*/ +#define TRANSPORT_SCRAMBLING_CONTROL 6 +#define ADAPTATION_FIELD_CONTROL 4 + +/* bit 15:12 -- om_cmd_count (read only)*/ +/* bit 11:9 -- overflow_count // bit 11:9 -- om_cmd_wr_ptr (read only)*/ +/* bit 8:6 -- om_overwrite_count // bit 8:6 -- om_cmd_rd_ptr (read only)*/ +/* bit 5:3 -- type_stb_om_w_rd (read only)*/ +/* bit 2 -- unit_start_stb_om_w_rd (read only)*/ +/* bit 1 -- om_cmd_overflow (read only)*/ +/* bit 0 -- om_cmd_pending (read)*/ +/* bit 0 -- om_cmd_read_finished (write)*/ +/*#define OM_CMD_STATUS + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x0b) // 0x160b*/ +/*#define OM_CMD_STATUS_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x0b) // 0x165b*/ +/*#define OM_CMD_STATUS_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x0b) // 0x16ab*/ +/*----------- bit define -----------*/ +#define OM_CMD_COUNT 12 +#define OM_OVERFLOW_COUNT 9 +#define OM_OVERWRITE_COUNT 6 +#define TYPE_STB_OM_W_RD 3 +#define UNIT_START_STB_OM_W_RD 2 +#define OM_CMD_OVERFLOW 1 + +/* bit 15:9 -- count_stb_om_w_rd (read only)*/ +/* bit 8:0 -- start_stb_om_wa_rd (read only)*/ +/*#define OM_CMD_DATA + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x0c) // 0x160c*/ +/*#define OM_CMD_DATA_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x0c) // 0x165c*/ +/*#define OM_CMD_DATA_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x0c) // 0x16ac*/ +/*----------- bit define -----------*/ +#define COUNT_STB_OM_W_RD 9 + +/* bit 11:0 -- offset for section data*/ +/*#define OM_CMD_DATA2 + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x0d) // 0x160d*/ +/*#define OM_CMD_DATA2_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x0d) // 0x165d*/ +/*#define OM_CMD_DATA2_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x0d) // 0x16ad*/ + +/* bit 31:16 -- base address for section buffer group 0 + * (*0x400 to get real address)*/ +/* bit 15:0 -- base address for section buffer group 1 + * (*0x400 to get real address)*/ +/*#define SEC_BUFF_01_START + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x0e) // 0x160e*/ +/*#define SEC_BUFF_01_START_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x0e) // 0x165e*/ +/*#define SEC_BUFF_01_START_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x0e) // 0x16ae*/ +/*----------- bit define -----------*/ +#define SEC_BUFF_0_BASE_ADDR 16 + +/* bit 31:16 -- base address for section buffer group 2 + * (*0x400 to get real address)*/ +/* bit 15:0 -- base address for section buffer group 3 + * (*0x400 to get real address)*/ +/*#define SEC_BUFF_23_START + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x0f) // 0x160f*/ +/*#define SEC_BUFF_23_START_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x0f) // 0x165f*/ +/*#define SEC_BUFF_23_START_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x0f) // 0x16af*/ +/*----------- bit define -----------*/ +#define SEC_BUFF_2_BASE_ADDR 16 + +/* bit 15:12 -- section buffer size for group 3*/ +/* bit 11:8 -- section buffer size for group 2*/ +/* bit 7:4 -- section buffer size for group 1*/ +/* bit 3:0 -- section buffer size for group 0 + * (bit used, for example, 10 means 1K)*/ +/*#define SEC_BUFF_SIZE + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x10) // 0x1610*/ +/*#define SEC_BUFF_SIZE_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x10) // 0x1660*/ +/*#define SEC_BUFF_SIZE_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x10) // 0x16b0*/ +/*----------- bit define -----------*/ +#define SEC_BUFF_3_SIZE 12 +#define SEC_BUFF_2_SIZE 8 +#define SEC_BUFF_1_SIZE 4 + +/* section buffer busy status for buff 31:0 ( Read Only )*/ +/*#define SEC_BUFF_BUSY + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x11) // 0x1611*/ +/*#define SEC_BUFF_BUSY_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x11) // 0x1661*/ +/*#define SEC_BUFF_BUSY_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x11) // 0x16b1*/ + +/* section buffer write status for buff 31:0 -- Read*/ +/* clear buffer status ( buff READY and BUSY ) -- write*/ +/*#define SEC_BUFF_READY + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x12) // 0x1612*/ +/*#define SEC_BUFF_READY_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x12) // 0x1662*/ +/*#define SEC_BUFF_READY_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x12) // 0x16b2*/ + +/* bit 15 -- section_reset_busy (Read Only)*/ +/* bit 14 -- output_section_buffer_valid*/ +/* bit 12:8 -- SEC_BUFFER_NUMBER for the INDEX buffer Read_Only*/ +/* bit 4:0 -- SEC_BUFFER_INDEX RW*/ +/*#define SEC_BUFF_NUMBER + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x13) // 0x1613*/ +/*#define SEC_BUFF_NUMBER_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x13) // 0x1663*/ +/*#define SEC_BUFF_NUMBER_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x13) // 0x16b3*/ +/*----------- bit define -----------*/ +#define SECTION_RESET_BUSY 15 +#define OUTPUT_SECTION_BUFFER_VALID 14 +#define INDEXED_SEC_BUFF_NUMBER 8 + +/* bit 9:5 -- BYPASS PID number*/ +/* bit 4:0 -- PCR PID number*/ +/*#define ASSIGN_PID_NUMBER + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x14) // 0x1614*/ +/*#define ASSIGN_PID_NUMBER_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x14) // 0x1664*/ +/*#define ASSIGN_PID_NUMBER_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x14) // 0x16b4*/ +/*----------- bit define -----------*/ +#define BYPASS_PID_NUMBER 5 + +/* bit 15:0 -- stream_id filter bit enable*/ +/* bit 7:0 -- stream_id filter target*/ +/*#define VIDEO_STREAM_ID + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x15) // 0x1615*/ +/*#define VIDEO_STREAM_ID_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x15) // 0x1665*/ +/*#define VIDEO_STREAM_ID_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x15) // 0x16b5*/ + +/*#define AUDIO_STREAM_ID + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x16) // 0x1616*/ +/*#define AUDIO_STREAM_ID_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x16) // 0x1666*/ +/*#define AUDIO_STREAM_ID_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x16) // 0x16b6*/ + +/*#define SUB_STREAM_ID + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x17) // 0x1617*/ +/*#define SUB_STREAM_ID_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x17) // 0x1667*/ +/*#define SUB_STREAM_ID_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x17) // 0x16b7*/ + +/*#define OTHER_STREAM_ID + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x18) // 0x1618*/ +/*#define OTHER_STREAM_ID_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x18) // 0x1668*/ +/*#define OTHER_STREAM_ID_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x18) // 0x16b8*/ + +/* bit 12 -- PCR_EN*/ +/* bit 11:0 -- PCR90K_DIV*/ +/*#define PCR90K_CTL + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x19) // 0x1619*/ +/*#define PCR90K_CTL_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x19) // 0x1669*/ +/*#define PCR90K_CTL_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x19) // 0x16b9*/ +/*----------- bit define -----------*/ +#define PCR_EN 12 + +/* bit 15:0 -- PCR[31:0] R/W*/ +/*#define PCR_DEMUX + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x1a) // 0x161a*/ +/*#define PCR_DEMUX_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x1a) // 0x166a*/ +/*#define PCR_DEMUX_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x1a) // 0x16ba*/ + +/* bit 15:0 -- VPTS[31:0] R/W*/ +/*#define VIDEO_PTS_DEMUX + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x1b) // 0x161b*/ +/*#define VIDEO_PTS_DEMUX_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x1b) // 0x166b*/ +/*#define VIDEO_PTS_DEMUX_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x1b) // 0x16bb*/ + +/* bit 15:0 -- VDTS[31:0] R/W*/ +/*#define VIDEO_DTS_DEMUX + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x1c) // 0x161c*/ +/*#define VIDEO_DTS_DEMUX_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x1c) // 0x166c*/ +/*#define VIDEO_DTS_DEMUX_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x1c) // 0x16bc*/ + +/* bit 15:0 -- APTS[31:0] R/W*/ +/*#define AUDIO_PTS_DEMUX + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x1d) // 0x161d*/ +/*#define AUDIO_PTS_DEMUX_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x1d) // 0x166d*/ +/*#define AUDIO_PTS_DEMUX_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x1d) // 0x16bd*/ + +/* bit 15:0 -- SPTS[31:0] R/W*/ +/*#define SUB_PTS_DEMUX + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x1e) // 0x161e*/ +/*#define SUB_PTS_DEMUX_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x1e) // 0x166e*/ +/*#define SUB_PTS_DEMUX_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x1e) // 0x16be*/ + +/* read -- status, write 1 clear status*/ +/* bit 15 -- SUB_PTS[32]*/ +/* bit 14 -- AUDIO_PTS[32]*/ +/* bit 13 -- VIDEO_DTS[32]*/ +/* bit 12 -- VIDEO_PTS[32]*/ +/* bit 3 -- sub_pts_ready*/ +/* bit 2 -- audio_pts_ready*/ +/* bit 1 -- video_dts_ready*/ +/* bit 0 -- video_pts_ready*/ +/*#define STB_PTS_DTS_STATUS + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x1f) // 0x161f*/ +/*#define STB_PTS_DTS_STATUS_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x1f) // 0x166f*/ +/*#define STB_PTS_DTS_STATUS_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x1f) // 0x16bf*/ +/*----------- bit define -----------*/ +#define SUB_PTS_BIT32 15 +#define AUDIO_PTS_BIT32 14 +#define VIDEO_DTS_BIT32 13 +#define VIDEO_PTS_BIT32 12 +#define SUB_PTS_READY 3 +#define AUDIO_PTS_READY 2 +#define VIDEO_DTS_READY 1 +#define VIDEO_PTS_READY 0 + +/* bit 3:0 --*/ +/* 0 -- adaptation_field_length[7:0], adaption_field_byte_1[7:0]*/ +/* 1 -- stream_id[7:0], pes_header_bytes_left[7:0]*/ +/* 2 -- pes_package_bytes_left[15:0]*/ +/* 3 -- pes_ctr_byte[7:0], pes_flag_byte[7:0]*/ +/*#define STB_DEBUG_INDEX + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x20) // 0x1620*/ +/*#define STB_DEBUG_INDEX_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x20) // 0x1670*/ +/*#define STB_DEBUG_INDEX_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x20) // 0x16c0*/ + +/* read only*/ +/*#define STB_DEBUG_DATA_OUT + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x21) // 0x1621*/ +/*#define STB_DEBUG_DATA_OUT_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x21) // 0x1671*/ +/*#define STB_DEBUG_DATA_OUT_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x21) // 0x16c1*/ + +/* bit[31] -- no_match_record_en*/ +/* bit[30:16] - reserved*/ +/* default : 0x807f*/ +/* bit 15:9 -- MAX OM DMA COUNT (default: 0x40)*/ +/* bit 8:0 -- LAST ADDR OF OM ADDR (default: 127)*/ +/*#define STB_OM_CTL \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x22) // 0x1622*/ +/*#define STB_OM_CTL_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x22) // 0x1672*/ +/*#define STB_OM_CTL_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x22) // 0x16c2*/ +/*----------- bit define -----------*/ +#define MAX_OM_DMA_COUNT 9 +#define LAST_OM_ADDR 0 + +/* 15:0 WRITE 1 CLEAR to clear interrupt source*/ +/*12 -- INPUT_TIME_OUT*/ +/*11 -- PCR_ready*/ +/*10 -- audio_splicing_point*/ +/* 9 -- video_splicing_point*/ +/* 8 -- other_PES_int*/ +/* 7 -- sub_PES_int*/ +/* 6 -- discontinuity*/ +/* 5 -- duplicated_pack_found*/ +/* 4 -- New PDTS ready*/ +/* 3 -- om_cmd_buffer ready for access*/ +/* 2 -- section buffer ready*/ +/* 1 -- transport_error_indicator*/ +/* 0 -- TS ERROR PIN*/ +/*#define STB_INT_STATUS + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x23) // 0x1623*/ +/*#define STB_INT_STATUS_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x23) // 0x1673*/ +/*#define STB_INT_STATUS_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x23) // 0x16c3*/ +/*----------- bit define -----------*/ +#define INPUT_TIME_OUT 12 +#define PCR_READY 11 +#define AUDIO_SPLICING_POINT 10 +#define VIDEO_SPLICING_POINT 9 +#define OTHER_PES_READY 8 +#define SUB_PES_READY 7 +#define DIS_CONTINUITY_PACKET 6 +#define DUPLICATED_PACKET 5 +#define NEW_PDTS_READY 4 +#define OM_CMD_READ_PENDING 3 +#define SECTION_BUFFER_READY 2 +#define TS_ERROR_PACKAGE 1 +#define TS_ERROR_PIN 0 + +/* When Bit 31 - 1 write will indicate all type use sepertate endian + * (Write Only)*/ +/* When Bit 31 - 0 write will indicate all type else use Bit 8:6*/ +/* Bit 23:21 - demux om write endian control for OTHER_PES_PACKET*/ +/* Bit 20:18 - demux om write endian control for SCR_ONLY_PACKET*/ +/* Bit 17:15 - demux om write endian control for SUB_PACKET*/ +/* Bit 14:12 - demux om write endian control for AUDIO_PACKET*/ +/* Bit 11:9 - demux om write endian control for VIDEO_PACKET*/ +/* Bit 8:6 - demux om write endian control for else*/ +/* Bit 5:3 - demux om write endian control for bypass*/ +/* Bit 2:0 - demux om write endian control for section*/ +/*#define DEMUX_ENDIAN + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x24) // 0x1624*/ +/*#define DEMUX_ENDIAN_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x24) // 0x1674*/ +/*#define DEMUX_ENDIAN_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x24) // 0x16c4*/ +/*----------- bit define -----------*/ +#define SEPERATE_ENDIAN 31 +#define OTHER_PES_ENDIAN 21 +#define SCR_ENDIAN 18 +#define SUB_ENDIAN 15 +#define AUDIO_ENDIAN 12 +#define VIDEO_ENDIAN 9 +#define OTHER_ENDIAN 6 +#define BYPASS_ENDIAN 3 +#define SECTION_ENDIAN 0 + +/* Bit 15:8 -- last_burst_threshold*/ +/* Bit 7 -- use hi_bsf interface*/ +/* Bit 6:2 - fec_clk_div*/ +/* Bit 1 ts_source_sel */ +/* Bit 0 - Hiu TS generate enable */ +/*#define TS_HIU_CTL + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x25) // 0x1625*/ +/*#define TS_HIU_CTL_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x25) // 0x1675*/ +/*#define TS_HIU_CTL_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x25) // 0x16c5*/ +/*----------- bit define -----------*/ +#define LAST_BURST_THRESHOLD 8 +#define USE_HI_BSF_INTERFACE 7 + +/* bit 15:0 -- base address for section buffer start + * (*0x10000 to get real base)*/ +/*#define SEC_BUFF_BASE + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x26) // 0x1626*/ +/*#define SEC_BUFF_BASE_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x26) // 0x1676*/ +/*#define SEC_BUFF_BASE_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x26) // 0x16c6*/ + +/* bit 11 -- mask bit for OTHER_PES_AHB_DMA_EN*/ +/* bit 10 -- mask bit for SUB_AHB_DMA_EN*/ +/* bit 9 -- mask bit for BYPASS_AHB_DMA_EN*/ +/* bit 8 -- mask bit for SECTION_AHB_DMA_EN*/ +/* bit 7 -- mask bit for recoder stream*/ +/* bit 6:0 -- mask bit for each type*/ +/*#define DEMUX_MEM_REQ_EN + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x27) // 0x1627*/ +/*#define DEMUX_MEM_REQ_EN_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x27) // 0x1677*/ +/*#define DEMUX_MEM_REQ_EN_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x27) // 0x16c7*/ +/*----------- bit define -----------*/ +#define VIDEO2_DMA_EN_BIT 12 +#define OTHER_PES_AHB_DMA_EN 11 +#define SUB_AHB_DMA_EN 10 +#define BYPASS_AHB_DMA_EN 9 +#define SECTION_AHB_DMA_EN 8 +#define RECORDER_STREAM 7 +#define OTHER_PES_PACKET 6 +#define SCR_ONLY_PACKET 5 /*will never be used*/ +#define BYPASS_PACKET 4 +#define SECTION_PACKET 3 +#define SUB_PACKET 2 +#define AUDIO_PACKET 1 +#define VIDEO_PACKET 0 + +/* bit 31:0 -- vb_wr_ptr for video PDTS*/ +/*#define VIDEO_PDTS_WR_PTR + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x28) // 0x1628*/ +/*#define VIDEO_PDTS_WR_PTR_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x28) // 0x1678*/ +/*#define VIDEO_PDTS_WR_PTR_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x28) // 0x16c8*/ + +/* bit 31:0 -- ab_wr_ptr for audio PDTS*/ +/*#define AUDIO_PDTS_WR_PTR + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x29) // 0x1629*/ +/*#define AUDIO_PDTS_WR_PTR_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x29) // 0x1679*/ +/*#define AUDIO_PDTS_WR_PTR_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x29) // 0x16c9*/ + +/* bit 20:0 -- SB_WRITE_PTR (sb_wr_ptr << 3 == byte write position)*/ +/*#define SUB_WR_PTR + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x2a) // 0x162a*/ +/*#define SUB_WR_PTR_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x2a) // 0x167a*/ +/*#define SUB_WR_PTR_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x2a) // 0x16ca*/ + +/* bit 19:0 -- SB_START (sb_start << 12 == byte address);*/ +/*#define SB_START + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x2b) // 0x162b*/ +/*#define SB_START_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x2b) // 0x167b*/ +/*#define SB_START_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x2b) // 0x16cb*/ + +/* bit 20:0 -- SB_SIZE (sb_size << 3 == byte size, 16M maximun)*/ +/*#define SB_LAST_ADDR + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x2c) // 0x162c*/ +/*#define SB_LAST_ADDR_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x2c) // 0x167c*/ +/*#define SB_LAST_ADDR_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x2c) // 0x16cc*/ + +/* bit 31:0 -- sb_wr_ptr for sub PES*/ +/*#define SB_PES_WRITE_PTR + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x2d) // 0x162d*/ +/*#define SB_PES_WRITE_PTR_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x2d) // 0x167d*/ +/*#define SB_PES_WRITE_PTR_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x2d) // 0x16cd*/ + +/* bit 31:16 -- ob_wr_ptr for other PES*/ +/* bit 20:0 -- OB_WRITE_PTR (ob_wr_ptr << 3 == byte write position)*/ +/*#define OTHER_WR_PTR + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x2e) // 0x162e*/ +/*#define OTHER_WR_PTR_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x2e) // 0x167e*/ +/*#define OTHER_WR_PTR_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x2e) // 0x16ce*/ + +/* bit 19:0 -- OB_START (ob_start << 12 == byte address);*/ +/*#define OB_START + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x2f) // 0x162f*/ +/*#define OB_START_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x2f) // 0x167f*/ +/*#define OB_START_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x2f) // 0x16cf*/ + +/* bit 20:0 -- OB_SIZE (ob_size << 3 == byte size, 16M maximun)*/ +/*#define OB_LAST_ADDR + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x30) // 0x1630*/ +/*#define OB_LAST_ADDR_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x30) // 0x1680*/ +/*#define OB_LAST_ADDR_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x30) // 0x16d0*/ + +/* bit 31:0 -- ob_wr_ptr for sub PES*/ +/*#define OB_PES_WRITE_PTR + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x31) // 0x1631*/ +/*#define OB_PES_WRITE_PTR_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x31) // 0x1681*/ +/*#define OB_PES_WRITE_PTR_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x31) // 0x16d1*/ + +/* 15:0 DEMUX interrupt MASK*/ +/* 11 -- PCR_READY*/ +/* 10 -- audio_splicing_point*/ +/* 9 -- video_splicing_point*/ +/* 8 -- other_PES_int*/ +/* 7 -- sub_PES_int*/ +/* 6 -- discontinuity*/ +/* 5 -- duplicated_pack_found*/ +/* 4 -- New PDTS ready*/ +/* 3 -- om_cmd_buffer ready for access*/ +/* 2 -- section buffer ready*/ +/* 1 -- transport_error_indicator*/ +/* 0 -- TS ERROR PIN*/ +/*#define STB_INT_MASK + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x32) // 0x1632*/ +/*#define STB_INT_MASK_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x32) // 0x1682*/ +/*#define STB_INT_MASK_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x32) // 0x16d2*/ + +/* 31:16 VIDEO PID filter data*/ +/*15 -- splicing VIDEO PID change enable*/ +/*14:10 -- VIDEO PID FILTER ADDRESS*/ +/* 9 -- PES splicing active (Read Only)*/ +/* 8 -- splicing active (Read Only)*/ +/* 7:0 splicing countdown (Read Only)*/ +/*#define VIDEO_SPLICING_CTL + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x33) // 0x1633*/ +/*#define VIDEO_SPLICING_CTL_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x33) // 0x1683*/ +/*#define VIDEO_SPLICING_CTL_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x33) // 0x16d3*/ +/*----------- bit define -----------*/ +#define VIDEO_PID_FILTER_DATA 16 +#define VIDEO_SPLICING_PID_CHANGE_ENABLE 15 +#define VIDEO_PID_FILTER_ADDRESS 10 +#define VIDEO_PES_SPLICING_ACTIVE 9 +#define VIDEO_SPLICING_ACTIVE 8 + + +/* 31:16 AUDIO PID filter data*/ +/*15 -- splicing AUDIO PID change enable*/ +/*14:10 -- AUDIO PID FILTER ADDRESS*/ +/* 9 -- PES splicing active (Read Only)*/ +/* 8 -- splicing active (Read Only)*/ +/* 7:0 splicing countdown (Read Only)*/ +/*#define AUDIO_SPLICING_CTL + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x34) // 0x1634*/ +/*#define AUDIO_SPLICING_CTL_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x34) // 0x1684*/ +/*#define AUDIO_SPLICING_CTL_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x34) // 0x16d4*/ +/*----------- bit define -----------*/ +#define AUDIO_PID_FILTER_DATA 16 +#define AUDIO_SPLICING_PID_CHANGE_ENABLE 15 +#define AUDIO_PID_FILTER_ADDRESS 10 +#define AUDIO_PES_SPLICING_ACTIVE 9 +#define AUDIO_SPLICING_ACTIVE 8 + +/* 23:16 M2TS_SKIP_BYTES*/ +/* 15:8 LAST TS PACKAGE BYTE COUNT (Read Only)*/ +/* 7:0 PACKAGE BYTE COUNT (Read Only)*/ +/*#define TS_PACKAGE_BYTE_COUNT + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x35) // 0x1635*/ +/*#define TS_PACKAGE_BYTE_COUNT_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x35) // 0x1685*/ +/*#define TS_PACKAGE_BYTE_COUNT_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x35) // 0x16d5*/ +/*----------- bit define -----------*/ +#define M2TS_SKIP_BYTES 16 +#define LAST_TS_PACKAGE_BYTE_COUNT 8 + +/* 15:0 2 bytes strong sync add to PES*/ +/*#define PES_STRONG_SYNC + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x36) // 0x1636*/ +/*#define PES_STRONG_SYNC_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x36) // 0x1686*/ +/*#define PES_STRONG_SYNC_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x36) // 0x16d6*/ + +/* bit 15 -- stb_om_ren*/ +/* bit 14:11 -- reserved*/ +/* bit 10:0 -- OM_DATA_RD_ADDR*/ +/*#define OM_DATA_RD_ADDR + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x37) // 0x1637*/ +/*#define OM_DATA_RD_ADDR_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x37) // 0x1687*/ +/*#define OM_DATA_RD_ADDR_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x37) // 0x16d7*/ +/*----------- bit define -----------*/ +#define STB_OM_REN 15 + +/* bit 15:0 -- OM_DATA_RD*/ +/*#define OM_DATA_RD + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x38) // 0x1638*/ +/*#define OM_DATA_RD_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x38) // 0x1688*/ +/*#define OM_DATA_RD_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x38) // 0x16d8*/ + +/* AUTO STOP SETTING for 32 channels*/ +/* 4-bits per channel*/ +/* when write*/ +/* bit 3 -- set section active*/ +/* bit 2:0 -- auto stop after count (0 means never stop)*/ +/* when read*/ +/* bit 3 -- current active status (1 - active, 0 - stopped )*/ +/* bit 2:0 -- count down to auto stop*/ +/* section 31:24*/ +/*#define SECTION_AUTO_STOP_3 + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x39) // 0x1639*/ +/*#define SECTION_AUTO_STOP_3_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x39) // 0x1689*/ +/*#define SECTION_AUTO_STOP_3_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x39) // 0x16d9*/ +/* section 23:16*/ +/*#define SECTION_AUTO_STOP_2 + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x3a) // 0x163a*/ +/*#define SECTION_AUTO_STOP_2_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x3a) // 0x168a*/ +/*#define SECTION_AUTO_STOP_2_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x3a) // 0x16da*/ +/* section 15:8*/ +/*#define SECTION_AUTO_STOP_1 + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x3b) // 0x163b*/ +/*#define SECTION_AUTO_STOP_1_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x3b) // 0x168b*/ +/*#define SECTION_AUTO_STOP_1_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x3b) // 0x16db*/ +/* section 7:0*/ +/*#define SECTION_AUTO_STOP_0 + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x3c) // 0x163c*/ +/*#define SECTION_AUTO_STOP_0_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x3c) // 0x168c*/ +/*#define SECTION_AUTO_STOP_0_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x3c) // 0x16dc*/ + +/* bit 31:0 reset channel status - each bit reset each channel*/ +/* read -- 32 channel status*/ +/*#define DEMUX_CHANNEL_RESET + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x3d) // 0x163d*/ +/*#define DEMUX_CHANNEL_RESET_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x3d) // 0x168d*/ +/*#define DEMUX_CHANNEL_RESET_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x3d) // 0x16dd*/ + +/*#define DEMUX_SCRAMBLING_STATE + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x3e) // 0x163e*/ +/*#define DEMUX_SCRAMBLING_STATE_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x3e) // 0x168e*/ +/*#define DEMUX_SCRAMBLING_STATE_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x3e) // 0x16de*/ + +/*#define DEMUX_CHANNEL_ACTIVITY + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x3f) // 0x163f*/ +/*#define DEMUX_CHANNEL_ACTIVITY_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x3f) // 0x168f*/ +/*#define DEMUX_CHANNEL_ACTIVITY_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x3f) // 0x16df*/ + +/* bit 4 -- video_stamp_use_dts*/ +/* bit 3 -- audio_stamp_sync_1_en*/ +/* bit 2 -- audio_stamp_insert_en*/ +/* bit 1 -- video_stamp_sync_1_en*/ +/* bit 0 -- video_stamp_insert_en*/ +/*#define DEMUX_STAMP_CTL + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x40) // 0x1640*/ +/*#define DEMUX_STAMP_CTL_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x40) // 0x1690*/ +/*#define DEMUX_STAMP_CTL_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x40) // 0x16e0*/ + +/*#define DEMUX_VIDEO_STAMP_SYNC_0 + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x41) // 0x1641*/ +/*#define DEMUX_VIDEO_STAMP_SYNC_0_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x41) // 0x1691*/ +/*#define DEMUX_VIDEO_STAMP_SYNC_0_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x41) // 0x16e1*/ + +/*#define DEMUX_VIDEO_STAMP_SYNC_1 + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x42) // 0x1642*/ +/*#define DEMUX_VIDEO_STAMP_SYNC_1_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x42) // 0x1692*/ +/*#define DEMUX_VIDEO_STAMP_SYNC_1_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x42) // 0x16e2*/ + +/*#define DEMUX_AUDIO_STAMP_SYNC_0 + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x43) // 0x1643*/ +/*#define DEMUX_AUDIO_STAMP_SYNC_0_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x43) // 0x1693*/ +/*#define DEMUX_AUDIO_STAMP_SYNC_0_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x43) // 0x16e3*/ + +/*#define DEMUX_AUDIO_STAMP_SYNC_1 + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x44) // 0x1644*/ +/*#define DEMUX_AUDIO_STAMP_SYNC_1_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x44) // 0x1694*/ +/*#define DEMUX_AUDIO_STAMP_SYNC_1_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x44) // 0x16e4*/ + +/* Write : Bit[4:0] secter filter number for reset*/ +/* Read : select according to output_section_buffer_valid :*/ +/* per bit per section buffer valid status*/ +/* or section_buffer_ignore*/ +/*#define DEMUX_SECTION_RESET + * (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x45) // 0x1645*/ +/*#define DEMUX_SECTION_RESET_2 + * (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x45) // 0x1695*/ +/*#define DEMUX_SECTION_RESET_3 + * (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x45) // 0x16e5*/ + + +/* bit[31:0] - channel_reset_timeout_disable*/ +/*#define DEMUX_INPUT_TIMEOUT_C \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x46) // 0x1646*/ +/*#define DEMUX_INPUT_TIMEOUT_C_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x46) // 0x1696*/ +/*#define DEMUX_INPUT_TIMEOUT_C_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x46) // 0x16e6*/ +/* bit[31] - no_match_reset_timeout_disable*/ +/* bit[30:0] input_time_out_int_cnt (0 -- means disable) Wr-setting, Rd-count*/ +/*#define DEMUX_INPUT_TIMEOUT \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x47) // 0x1647*/ +/*#define DEMUX_INPUT_TIMEOUT_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x47) // 0x1697*/ +/*#define DEMUX_INPUT_TIMEOUT_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x47) // 0x16e7*/ + +/* bit[31:0] - channel_packet_count_disable*/ +/*#define DEMUX_PACKET_COUNT_C \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x48) // 0x1648*/ +/*#define DEMUX_PACKET_COUNT_C_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x48) // 0x1698*/ +/*#define DEMUX_PACKET_COUNT_C_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x48)*/ /* 0x16e8*/ +/* bit[31] - no_match_packet_count_disable*/ +/* bit[30:0] input_packet_count*/ +/*#define DEMUX_PACKET_COUNT \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x49) // 0x1649*/ +/*#define DEMUX_PACKET_COUNT_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x49) // 0x1699*/ +/*#define DEMUX_PACKET_COUNT_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x49) // 0x16e9*/ + +/* bit[31:0] channel_record_enable*/ +/*#define DEMUX_CHAN_RECORD_EN \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4a) // 0x164a*/ +/*#define DEMUX_CHAN_RECORD_EN_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4a) // 0x169a*/ +/*#define DEMUX_CHAN_RECORD_EN_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4a) // 0x16ea*/ + +/* bit[31:0] channel_process_enable*/ +/*#define DEMUX_CHAN_PROCESS_EN \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4b) // 0x164b*/ +/*#define DEMUX_CHAN_PROCESS_EN_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4b) */ /* 0x169b*/ +/*#define DEMUX_CHAN_PROCESS_EN_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4b) // 0x16eb*/ + +/* bit[31:24] small_sec_size ((n+1) * 256 Bytes)*/ +/* bit[23:16] small_sec_rd_ptr */ +/* bit[15:8] small_sec_wr_ptr */ +/* bit[7:2] reserved*/ +/* bit[1] small_sec_wr_ptr_wr_enable*/ +/* bit[0] small_section_enable*/ +/*#define DEMUX_SMALL_SEC_CTL \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4c)*/ /* 0x164c*/ +/*#define DEMUX_SMALL_SEC_CTL_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4c) // 0x169c*/ +/*#define DEMUX_SMALL_SEC_CTL_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4c) // 0x16ec*/ +/* bit[31:0] small_sec_start_addr*/ +/*#define DEMUX_SMALL_SEC_ADDR \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4d) // 0x164d*/ +/*#define DEMUX_SMALL_SEC_ADDR_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4d) // 0x169d*/ +/*#define DEMUX_SMALL_SEC_ADDR_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4d) // 0x16ed*/ + + +/*======================================================*/ +/* STB Registers End*/ +/*====================================================*/ +/* ----------------------------*/ +/* ASYNC FIFO (4)*/ +/* ----------------------------*/ +/*#define ASYNC_FIFO_REG0 0x2310*/ +/*#define ASYNC_FIFO_REG1 0x2311*/ +#define ASYNC_FIFO_FLUSH_STATUS 31 +#define ASYNC_FIFO_ERR 30 +#define ASYNC_FIFO_FIFO_EMPTY 29 +#define ASYNC_FIFO_TO_HIU 24 +#define ASYNC_FIFO_FLUSH 23 +#define ASYNC_FIFO_RESET 22 +#define ASYNC_FIFO_WRAP_EN 21 +#define ASYNC_FIFO_FLUSH_EN 20 +#define ASYNC_FIFO_RESIDUAL_MSB 19 +#define ASYNC_FIFO_RESIDUAL_LSB 15 +#define ASYNC_FIFO_FLUSH_CNT_MSB 14 +#define ASYNC_FIFO_FLUSH_CNT_LSB 0 +/*#define ASYNC_FIFO_REG2 0x2312*/ +#define ASYNC_FIFO_FIFO_FULL 26 +#define ASYNC_FIFO_FILL_STATUS 25 +#define ASYNC_FIFO_SOURCE_MSB 24 +#define ASYNC_FIFO_SOURCE_LSB 23 +#define ASYNC_FIFO_ENDIAN_MSB 22 +#define ASYNC_FIFO_ENDIAN_LSB 21 +#define ASYNC_FIFO_FILL_EN 20 +#define ASYNC_FIFO_FILL_CNT_MSB 19 +#define ASYNC_FIFO_FILL_CNT_LSB 0 +/*#define ASYNC_FIFO_REG3 0x2313*/ +#define ASYNC_FLUSH_SIZE_IRQ_MSB 15 +#define ASYNC_FLUSH_SIZE_IRQ_LSB 0 +/* ----------------------------*/ +/* ASYNC FIFO (4)*/ +/* ----------------------------*/ +/*#define ASYNC_FIFO2_REG0 0x2314*/ +/*#define ASYNC_FIFO2_REG1 0x2315*/ +/*#define ASYNC_FIFO2_REG2 0x2316*/ +/*#define ASYNC_FIFO2_REG3 0x2317*/ + +#define RESET_DEMUXSTB (1 << 1) +#endif /* C_STB_DEFINE_H*/ diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_regs_define.h b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_regs_define.h new file mode 100644 index 000000000000..5651ba7f5aa8 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_regs_define.h @@ -0,0 +1,769 @@ +/* + * This file is automaticly generated by genregs.awk. Please do not edit it + * Base files are .. + * .. + * .. + * Tue Oct 22 15:28:48 CST 2013 + **/ + +#ifndef __MACH_MESON8_REG_ADDR_H_ +#define __MACH_MESON8_REG_ADDR_H_ +#include +#define CBUS_REG_ADDR(_r) aml_read_cbus(_r) + + +#define STB_CBUS_BASE aml_stb_get_base(ID_STB_CBUS_BASE) +#define SMARTCARD_REG_BASE aml_stb_get_base(ID_SMARTCARD_REG_BASE) +#define ASYNC_FIFO_REG_BASE aml_stb_get_base(ID_ASYNC_FIFO_REG_BASE) +#define ASYNC_FIFO2_REG_BASE aml_stb_get_base(ID_ASYNC_FIFO2_REG_BASE) +#define RESET_BASE aml_stb_get_base(ID_RESET_BASE) +#define PARSER_SUB_START_PTR_BASE \ + aml_stb_get_base(ID_PARSER_SUB_START_PTR_BASE) + +#define HHI_CSI_PHY_CNTL_BASE 0x1000 + +#define DEMUX_1_OFFSET 0x00 +#define DEMUX_2_OFFSET 0x50 +#define DEMUX_3_OFFSET 0xa0 + + +#define STB_TOP_CONFIG (STB_CBUS_BASE + 0xf0) +#define P_STB_TOP_CONFIG CBUS_REG_ADDR(STB_TOP_CONFIG) +#define TS_TOP_CONFIG (STB_CBUS_BASE + 0xf1) +#define P_TS_TOP_CONFIG CBUS_REG_ADDR(TS_TOP_CONFIG) +#define TS_FILE_CONFIG (STB_CBUS_BASE + 0xf2) +#define P_TS_FILE_CONFIG CBUS_REG_ADDR(TS_FILE_CONFIG) +#define TS_PL_PID_INDEX (STB_CBUS_BASE + 0xf3) +#define P_TS_PL_PID_INDEX CBUS_REG_ADDR(TS_PL_PID_INDEX) +#define TS_PL_PID_DATA (STB_CBUS_BASE + 0xf4) +#define P_TS_PL_PID_DATA CBUS_REG_ADDR(TS_PL_PID_DATA) +#define COMM_DESC_KEY0 (STB_CBUS_BASE + 0xf5) +#define P_COMM_DESC_KEY0 CBUS_REG_ADDR(COMM_DESC_KEY0) +#define COMM_DESC_KEY1 (STB_CBUS_BASE + 0xf6) +#define P_COMM_DESC_KEY1 CBUS_REG_ADDR(COMM_DESC_KEY1) +#define COMM_DESC_KEY_RW (STB_CBUS_BASE + 0xf7) +#define P_COMM_DESC_KEY_RW CBUS_REG_ADDR(COMM_DESC_KEY_RW) +#define CIPLUS_KEY0 (STB_CBUS_BASE + 0xf8) +#define P_CIPLUS_KEY0 CBUS_REG_ADDR(CIPLUS_KEY0) +#define CIPLUS_KEY1 (STB_CBUS_BASE + 0xf9) +#define P_CIPLUS_KEY1 CBUS_REG_ADDR(CIPLUS_KEY1) +#define CIPLUS_KEY2 (STB_CBUS_BASE + 0xfa) +#define P_CIPLUS_KEY2 CBUS_REG_ADDR(CIPLUS_KEY2) +#define CIPLUS_KEY3 (STB_CBUS_BASE + 0xfb) +#define P_CIPLUS_KEY3 CBUS_REG_ADDR(CIPLUS_KEY3) +#define CIPLUS_KEY_WR (STB_CBUS_BASE + 0xfc) +#define P_CIPLUS_KEY_WR CBUS_REG_ADDR(CIPLUS_KEY_WR) +#define CIPLUS_CONFIG (STB_CBUS_BASE + 0xfd) +#define P_CIPLUS_CONFIG CBUS_REG_ADDR(CIPLUS_CONFIG) +#define CIPLUS_ENDIAN (STB_CBUS_BASE + 0xfe) +#define P_CIPLUS_ENDIAN CBUS_REG_ADDR(CIPLUS_ENDIAN) + +#define SMARTCARD_REG0 (SMARTCARD_REG_BASE + 0x0) +#define P_SMARTCARD_REG0 CBUS_REG_ADDR(SMARTCARD_REG0) +#define SMARTCARD_REG1 (SMARTCARD_REG_BASE + 0x1) +#define P_SMARTCARD_REG1 CBUS_REG_ADDR(SMARTCARD_REG1) +#define SMARTCARD_REG2 (SMARTCARD_REG_BASE + 0x2) +#define P_SMARTCARD_REG2 CBUS_REG_ADDR(SMARTCARD_REG2) +#define SMARTCARD_STATUS (SMARTCARD_REG_BASE + 0x3) +#define P_SMARTCARD_STATUS CBUS_REG_ADDR(SMARTCARD_STATUS) +#define SMARTCARD_INTR (SMARTCARD_REG_BASE + 0x4) +#define P_SMARTCARD_INTR CBUS_REG_ADDR(SMARTCARD_INTR) +#define SMARTCARD_REG5 (SMARTCARD_REG_BASE + 0x5) +#define P_SMARTCARD_REG5 CBUS_REG_ADDR(SMARTCARD_REG5) +#define SMARTCARD_REG6 (SMARTCARD_REG_BASE + 0x6) +#define P_SMARTCARD_REG6 CBUS_REG_ADDR(SMARTCARD_REG6) +#define SMARTCARD_FIFO (SMARTCARD_REG_BASE + 0x7) +#define P_SMARTCARD_FIFO CBUS_REG_ADDR(SMARTCARD_FIFO) +#define SMARTCARD_REG8 (SMARTCARD_REG_BASE + 0x8) +#define P_SMARTCARD_REG8 CBUS_REG_ADDR(SMARTCARD_REG8) + +#define ASYNC_FIFO_REG0 (ASYNC_FIFO_REG_BASE + 0x0) +#define P_ASYNC_FIFO_REG0 CBUS_REG_ADDR(ASYNC_FIFO_REG0) +#define ASYNC_FIFO_REG1 (ASYNC_FIFO_REG_BASE + 0x1) +#define P_ASYNC_FIFO_REG1 CBUS_REG_ADDR(ASYNC_FIFO_REG1) +#define ASYNC_FIFO_REG2 (ASYNC_FIFO_REG_BASE + 0x2) +#define P_ASYNC_FIFO_REG2 CBUS_REG_ADDR(ASYNC_FIFO_REG2) +#define ASYNC_FIFO_REG3 (ASYNC_FIFO_REG_BASE + 0x3) +#define P_ASYNC_FIFO_REG3 CBUS_REG_ADDR(ASYNC_FIFO_REG3) +#define ASYNC_FIFO_REG4 (ASYNC_FIFO_REG_BASE + 0x4) +#define P_ASYNC_FIFO_REG4 CBUS_REG_ADDR(ASYNC_FIFO_REG4) +#define ASYNC_FIFO_REG5 (ASYNC_FIFO_REG_BASE + 0x5) +#define P_ASYNC_FIFO_REG5 CBUS_REG_ADDR(ASYNC_FIFO_REG5) + + +#define ASYNC_FIFO2_REG0 (ASYNC_FIFO2_REG_BASE + 0x0) +#define P_ASYNC_FIFO2_REG0 CBUS_REG_ADDR(ASYNC_FIFO2_REG0) +#define ASYNC_FIFO2_REG1 (ASYNC_FIFO2_REG_BASE + 0x1) +#define P_ASYNC_FIFO2_REG1 CBUS_REG_ADDR(ASYNC_FIFO2_REG1) +#define ASYNC_FIFO2_REG2 (ASYNC_FIFO2_REG_BASE + 0x2) +#define P_ASYNC_FIFO2_REG2 CBUS_REG_ADDR(ASYNC_FIFO2_REG2) +#define ASYNC_FIFO2_REG3 (ASYNC_FIFO2_REG_BASE + 0x3) +#define P_ASYNC_FIFO2_REG3 CBUS_REG_ADDR(ASYNC_FIFO2_REG3) +#define ASYNC_FIFO2_REG4 (ASYNC_FIFO2_REG_BASE + 0x4) +#define P_ASYNC_FIFO2_REG4 CBUS_REG_ADDR(ASYNC_FIFO2_REG4) +#define ASYNC_FIFO2_REG5 (ASYNC_FIFO2_REG_BASE + 0x5) +#define P_ASYNC_FIFO2_REG5 CBUS_REG_ADDR(ASYNC_FIFO2_REG5) + + +#define RESET0_REGISTER (RESET_BASE + 0x1) +#define P_RESET0_REGISTER CBUS_REG_ADDR(RESET0_REGISTER) +#define RESET1_REGISTER (RESET_BASE + 0x2) +#define P_RESET1_REGISTER CBUS_REG_ADDR(RESET1_REGISTER) +#define RESET2_REGISTER (RESET_BASE + 0x3) +#define P_RESET2_REGISTER CBUS_REG_ADDR(RESET2_REGISTER) +#define RESET3_REGISTER (RESET_BASE + 0x4) +#define P_RESET3_REGISTER CBUS_REG_ADDR(RESET3_REGISTER) +#define RESET4_REGISTER (RESET_BASE + 0x5) +#define P_RESET4_REGISTER CBUS_REG_ADDR(RESET4_REGISTER) +#define RESET5_REGISTER (RESET_BASE + 0x6) +#define P_RESET5_REGISTER CBUS_REG_ADDR(RESET5_REGISTER) +#define RESET6_REGISTER (RESET_BASE + 0x7) +#define P_RESET6_REGISTER CBUS_REG_ADDR(RESET6_REGISTER) +#define RESET7_REGISTER (RESET_BASE + 0x8) +#define P_RESET7_REGISTER CBUS_REG_ADDR(RESET7_REGISTER) +#define RESET0_MASK (RESET_BASE + 0x10) +#define P_RESET0_MASK CBUS_REG_ADDR(RESET0_MASK) +#define RESET1_MASK (RESET_BASE + 0x11) +#define P_RESET1_MASK CBUS_REG_ADDR(RESET1_MASK) +#define RESET2_MASK (RESET_BASE + 0x12) +#define P_RESET2_MASK CBUS_REG_ADDR(RESET2_MASK) +#define RESET3_MASK (RESET_BASE + 0x13) +#define P_RESET3_MASK CBUS_REG_ADDR(RESET3_MASK) +#define RESET4_MASK (RESET_BASE + 0x14) +#define P_RESET4_MASK CBUS_REG_ADDR(RESET4_MASK) +#define RESET5_MASK (RESET_BASE + 0x15) +#define P_RESET5_MASK CBUS_REG_ADDR(RESET5_MASK) +#define RESET6_MASK (RESET_BASE + 0x16) +#define P_RESET6_MASK CBUS_REG_ADDR(RESET6_MASK) +#define CRT_MASK (RESET_BASE + 0x17) +#define P_CRT_MASK CBUS_REG_ADDR(CRT_MASK) +#define RESET7_MASK (RESET_BASE + 0x18) +#define P_RESET7_MASK CBUS_REG_ADDR(RESET7_MASK) +/*add from M8M2*/ +#define P_RESET0_LEVEL CBUS_REG_ADDR(RESET0_LEVEL) +#define RESET1_LEVEL (RESET_BASE + 0x21) +#define P_RESET1_LEVEL CBUS_REG_ADDR(RESET1_LEVEL) +#define RESET2_LEVEL (RESET_BASE + 0x22) +#define P_RESET2_LEVEL CBUS_REG_ADDR(RESET2_LEVEL) +#define RESET3_LEVEL (RESET_BASE + 0x23) +#define P_RESET3_LEVEL CBUS_REG_ADDR(RESET3_LEVEL) +#define RESET4_LEVEL (RESET_BASE + 0x24) +#define P_RESET4_LEVEL CBUS_REG_ADDR(RESET4_LEVEL) +#define RESET5_LEVEL (RESET_BASE + 0x25) +#define P_RESET5_LEVEL CBUS_REG_ADDR(RESET5_LEVEL) +#define RESET6_LEVEL (RESET_BASE + 0x26) +#define P_RESET6_LEVEL CBUS_REG_ADDR(RESET6_LEVEL) +#define RESET7_LEVEL (RESET_BASE + 0x27) +#define P_RESET7_LEVEL CBUS_REG_ADDR(RESET7_LEVEL) + +/*no set*/ +#ifdef MESON_M8_CPU +#define HHI_CSI_PHY_CNTL0 (HHI_CSI_PHY_CNTL_BASE + 0xd3) +#define P_HHI_CSI_PHY_CNTL0 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL0) +#define HHI_CSI_PHY_CNTL1 (HHI_CSI_PHY_CNTL_BASE + 0xd4) +#define P_HHI_CSI_PHY_CNTL1 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL1) +#define HHI_CSI_PHY_CNTL2 (HHI_CSI_PHY_CNTL_BASE + 0xd5) +#define P_HHI_CSI_PHY_CNTL2 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL2) +#define HHI_CSI_PHY_CNTL3 (HHI_CSI_PHY_CNTL_BASE + 0xd6) +#define P_HHI_CSI_PHY_CNTL3 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL3) +#define HHI_CSI_PHY_CNTL4 (HHI_CSI_PHY_CNTL_BASE + 0xd7) +#define P_HHI_CSI_PHY_CNTL4 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL4) +#endif + +#define PARSER_SUB_START_PTR (PARSER_SUB_START_PTR_BASE + 0x8a) +#define P_PARSER_SUB_START_PTR CBUS_REG_ADDR(PARSER_SUB_START_PTR) +#define PARSER_SUB_END_PTR (PARSER_SUB_START_PTR_BASE + 0x8b) +#define P_PARSER_SUB_END_PTR CBUS_REG_ADDR(PARSER_SUB_END_PTR) +#define PARSER_SUB_WP (PARSER_SUB_START_PTR_BASE + 0x8c) +#define P_PARSER_SUB_WP CBUS_REG_ADDR(PARSER_SUB_WP) +#define PARSER_SUB_RP (PARSER_SUB_START_PTR_BASE + 0x8d) +#define P_PARSER_SUB_RP CBUS_REG_ADDR(PARSER_SUB_RP) +#define PARSER_SUB_HOLE (PARSER_SUB_START_PTR_BASE + 0x8e) +#define P_PARSER_SUB_HOLE CBUS_REG_ADDR(PARSER_SUB_HOLE) + +/*no set*/ +#define AO_RTI_GEN_PWR_SLEEP0 ((0x00 << 10) | (0x3a << 2)) +#define P_AO_RTI_GEN_PWR_SLEEP0 \ + AOBUS_REG_ADDR(AO_RTI_GEN_PWR_SLEEP0) +#define AO_RTI_GEN_PWR_ISO0 ((0x00 << 10) | (0x3b << 2)) +#define P_AO_RTI_GEN_PWR_ISO0 AOBUS_REG_ADDR(AO_RTI_GEN_PWR_ISO0) + +/**/ +#define STB_VERSION (STB_CBUS_BASE + 0x00) +#define P_STB_VERSION CBUS_REG_ADDR(STB_VERSION) +#define STB_VERSION_2 (STB_CBUS_BASE + 0x50) +#define P_STB_VERSION_2 CBUS_REG_ADDR(STB_VERSION_2) +#define STB_VERSION_3 (STB_CBUS_BASE + 0xa0) +#define P_STB_VERSION_3 CBUS_REG_ADDR(STB_VERSION_3) +#define STB_TEST_REG (STB_CBUS_BASE + 0x01) +#define P_STB_TEST_REG CBUS_REG_ADDR(STB_TEST_REG) +#define STB_TEST_REG_2 (STB_CBUS_BASE + 0x51) +#define P_STB_TEST_REG_2 CBUS_REG_ADDR(STB_TEST_REG_2) +#define STB_TEST_REG_3 (STB_CBUS_BASE + 0xa1) +#define P_STB_TEST_REG_3 CBUS_REG_ADDR(STB_TEST_REG_3) + +#define FEC_INPUT_CONTROL (STB_CBUS_BASE + 0x2) +#define P_FEC_INPUT_CONTROL CBUS_REG_ADDR(FEC_INPUT_CONTROL) +#define FEC_INPUT_CONTROL_2 (STB_CBUS_BASE + 0x52) +#define P_FEC_INPUT_CONTROL_2 CBUS_REG_ADDR(FEC_INPUT_CONTROL_2) +#define FEC_INPUT_CONTROL_3 (STB_CBUS_BASE + 0xa2) +#define P_FEC_INPUT_CONTROL_3 CBUS_REG_ADDR(FEC_INPUT_CONTROL_3) +/*no used*/ +#define FEC_INPUT_DATA (STB_CBUS_BASE + 0x03) +#define P_FEC_INPUT_DATA CBUS_REG_ADDR(FEC_INPUT_DATA) +#define FEC_INPUT_DATA_2 (STB_CBUS_BASE + 0x53) +#define P_FEC_INPUT_DATA_2 CBUS_REG_ADDR(FEC_INPUT_DATA_2) +#define FEC_INPUT_DATA_3 (STB_CBUS_BASE + 0xa3) +#define P_FEC_INPUT_DATA_3 CBUS_REG_ADDR(FEC_INPUT_DATA_3) +/*no used end*/ +#define DEMUX_CONTROL (STB_CBUS_BASE + 0x04) +#define P_DEMUX_CONTROL CBUS_REG_ADDR(DEMUX_CONTROL) +#define DEMUX_CONTROL_2 (STB_CBUS_BASE + 0x54) +#define P_DEMUX_CONTROL_2 CBUS_REG_ADDR(DEMUX_CONTROL_2) +#define DEMUX_CONTROL_3 (STB_CBUS_BASE + 0xa4) +#define P_DEMUX_CONTROL_3 CBUS_REG_ADDR(DEMUX_CONTROL_3) +/*no used*/ +#define FEC_SYNC_BYTE (STB_CBUS_BASE + 0x05) +#define P_FEC_SYNC_BYTE CBUS_REG_ADDR(FEC_SYNC_BYTE) +#define FEC_SYNC_BYTE_2 (STB_CBUS_BASE + 0x55) +#define P_FEC_SYNC_BYTE_2 CBUS_REG_ADDR(FEC_SYNC_BYTE_2) +#define FEC_SYNC_BYTE_3 (STB_CBUS_BASE + 0xa5) +#define P_FEC_SYNC_BYTE_3 CBUS_REG_ADDR(FEC_SYNC_BYTE_3) +/*no used end*/ + +#define FM_WR_DATA (STB_CBUS_BASE + 0x06) +#define P_FM_WR_DATA CBUS_REG_ADDR(FM_WR_DATA) +#define FM_WR_DATA_2 (STB_CBUS_BASE + 0x56) +#define P_FM_WR_DATA_2 CBUS_REG_ADDR(FM_WR_DATA_2) +#define FM_WR_DATA_3 (STB_CBUS_BASE + 0xa6) +#define P_FM_WR_DATA_3 CBUS_REG_ADDR(FM_WR_DATA_3) +#define FM_WR_ADDR (STB_CBUS_BASE + 0x07) +#define P_FM_WR_ADDR CBUS_REG_ADDR(FM_WR_ADDR) +#define FM_WR_ADDR_2 (STB_CBUS_BASE + 0x57) +#define P_FM_WR_ADDR_2 CBUS_REG_ADDR(FM_WR_ADDR_2) +#define FM_WR_ADDR_3 (STB_CBUS_BASE + 0xa7) +#define P_FM_WR_ADDR_3 CBUS_REG_ADDR(FM_WR_ADDR_3) +#define MAX_FM_COMP_ADDR (STB_CBUS_BASE + 0x08) +#define P_MAX_FM_COMP_ADDR CBUS_REG_ADDR(MAX_FM_COMP_ADDR) +#define MAX_FM_COMP_ADDR_2 (STB_CBUS_BASE + 0x58) +#define P_MAX_FM_COMP_ADDR_2 CBUS_REG_ADDR(MAX_FM_COMP_ADDR_2) +#define MAX_FM_COMP_ADDR_3 (STB_CBUS_BASE + 0xa8) +#define P_MAX_FM_COMP_ADDR_3 CBUS_REG_ADDR(MAX_FM_COMP_ADDR_3) + +#define TS_HEAD_0 (STB_CBUS_BASE + 0x09) +#define P_TS_HEAD_0 CBUS_REG_ADDR(TS_HEAD_0) +#define TS_HEAD_0_2 (STB_CBUS_BASE + 0x59) +#define P_TS_HEAD_0_2 CBUS_REG_ADDR(TS_HEAD_0_2) +#define TS_HEAD_0_3 (STB_CBUS_BASE + 0xa9) +#define P_TS_HEAD_0_3 CBUS_REG_ADDR(TS_HEAD_0_3) +#define TS_HEAD_1 (STB_CBUS_BASE + 0x0a) +#define P_TS_HEAD_1 CBUS_REG_ADDR(TS_HEAD_1) +#define TS_HEAD_1_2 (STB_CBUS_BASE + 0x5a) +#define P_TS_HEAD_1_2 CBUS_REG_ADDR(TS_HEAD_1_2) +#define TS_HEAD_1_3 (STB_CBUS_BASE + 0xaa) +#define P_TS_HEAD_1_3 CBUS_REG_ADDR(TS_HEAD_1_3) + +#define OM_CMD_STATUS (STB_CBUS_BASE + 0x0b) +#define P_OM_CMD_STATUS CBUS_REG_ADDR(OM_CMD_STATUS) +#define OM_CMD_STATUS_2 (STB_CBUS_BASE + 0x5b) +#define P_OM_CMD_STATUS_2 CBUS_REG_ADDR(OM_CMD_STATUS_2) +#define OM_CMD_STATUS_3 (STB_CBUS_BASE + 0xab) +#define P_OM_CMD_STATUS_3 CBUS_REG_ADDR(OM_CMD_STATUS_3) + +#define OM_CMD_DATA (STB_CBUS_BASE + 0x0c) +#define P_OM_CMD_DATA CBUS_REG_ADDR(OM_CMD_DATA) +#define OM_CMD_DATA_2 (STB_CBUS_BASE + 0x5c) +#define P_OM_CMD_DATA_2 CBUS_REG_ADDR(OM_CMD_DATA_2) +#define OM_CMD_DATA_3 (STB_CBUS_BASE + 0xac) +#define P_OM_CMD_DATA_3 CBUS_REG_ADDR(OM_CMD_DATA_3) +#define OM_CMD_DATA2 (STB_CBUS_BASE + 0x0d) +#define P_OM_CMD_DATA2 CBUS_REG_ADDR(OM_CMD_DATA2) +#define OM_CMD_DATA2_2 (STB_CBUS_BASE + 0x5d) +#define P_OM_CMD_DATA2_2 CBUS_REG_ADDR(OM_CMD_DATA2_2) +#define OM_CMD_DATA2_3 (STB_CBUS_BASE + 0xad) +#define P_OM_CMD_DATA2_3 CBUS_REG_ADDR(OM_CMD_DATA2_3) + +#define SEC_BUFF_01_START (STB_CBUS_BASE + 0x0e) +#define P_SEC_BUFF_01_START CBUS_REG_ADDR(SEC_BUFF_01_START) +#define SEC_BUFF_01_START_2 (STB_CBUS_BASE + 0x5e) +#define P_SEC_BUFF_01_START_2 CBUS_REG_ADDR(SEC_BUFF_01_START_2) +#define SEC_BUFF_01_START_3 (STB_CBUS_BASE + 0xae) +#define P_SEC_BUFF_01_START_3 CBUS_REG_ADDR(SEC_BUFF_01_START_3) +#define SEC_BUFF_23_START (STB_CBUS_BASE + 0x0f) +#define P_SEC_BUFF_23_START CBUS_REG_ADDR(SEC_BUFF_23_START) +#define SEC_BUFF_23_START_2 (STB_CBUS_BASE + 0x5f) +#define P_SEC_BUFF_23_START_2 CBUS_REG_ADDR(SEC_BUFF_23_START_2) +#define SEC_BUFF_23_START_3 (STB_CBUS_BASE + 0xaf) +#define P_SEC_BUFF_23_START_3 CBUS_REG_ADDR(SEC_BUFF_23_START_3) +#define SEC_BUFF_SIZE (STB_CBUS_BASE + 0x10) +#define P_SEC_BUFF_SIZE CBUS_REG_ADDR(SEC_BUFF_SIZE) +#define SEC_BUFF_SIZE_2 (STB_CBUS_BASE + 0x60) +#define P_SEC_BUFF_SIZE_2 CBUS_REG_ADDR(SEC_BUFF_SIZE_2) +#define SEC_BUFF_SIZE_3 (STB_CBUS_BASE + 0xb0) +#define P_SEC_BUFF_SIZE_3 CBUS_REG_ADDR(SEC_BUFF_SIZE_3) +#define SEC_BUFF_BUSY (STB_CBUS_BASE + 0x11) +#define P_SEC_BUFF_BUSY CBUS_REG_ADDR(SEC_BUFF_BUSY) +#define SEC_BUFF_BUSY_2 (STB_CBUS_BASE + 0x61) +#define P_SEC_BUFF_BUSY_2 CBUS_REG_ADDR(SEC_BUFF_BUSY_2) +#define SEC_BUFF_BUSY_3 (STB_CBUS_BASE + 0xb1) +#define P_SEC_BUFF_BUSY_3 CBUS_REG_ADDR(SEC_BUFF_BUSY_3) +#define SEC_BUFF_READY (STB_CBUS_BASE + 0x12) +#define P_SEC_BUFF_READY CBUS_REG_ADDR(SEC_BUFF_READY) +#define SEC_BUFF_READY_2 (STB_CBUS_BASE + 0x62) +#define P_SEC_BUFF_READY_2 CBUS_REG_ADDR(SEC_BUFF_READY_2) +#define SEC_BUFF_READY_3 (STB_CBUS_BASE + 0xb2) +#define P_SEC_BUFF_READY_3 CBUS_REG_ADDR(SEC_BUFF_READY_3) +#define SEC_BUFF_NUMBER (STB_CBUS_BASE + 0x13) +#define P_SEC_BUFF_NUMBER CBUS_REG_ADDR(SEC_BUFF_NUMBER) +#define SEC_BUFF_NUMBER_2 (STB_CBUS_BASE + 0x63) +#define P_SEC_BUFF_NUMBER_2 CBUS_REG_ADDR(SEC_BUFF_NUMBER_2) +#define SEC_BUFF_NUMBER_3 (STB_CBUS_BASE + 0xb3) +#define P_SEC_BUFF_NUMBER_3 CBUS_REG_ADDR(SEC_BUFF_NUMBER_3) + + +/**no used*/ +#define ASSIGN_PID_NUMBER (STB_CBUS_BASE + 0x14) +#define P_ASSIGN_PID_NUMBER CBUS_REG_ADDR(ASSIGN_PID_NUMBER) +#define ASSIGN_PID_NUMBER_2 (STB_CBUS_BASE + 0x64) +#define P_ASSIGN_PID_NUMBER_2 CBUS_REG_ADDR(ASSIGN_PID_NUMBER_2) +#define ASSIGN_PID_NUMBER_3 (STB_CBUS_BASE + 0xb4) +#define P_ASSIGN_PID_NUMBER_3 CBUS_REG_ADDR(ASSIGN_PID_NUMBER_3) +#define VIDEO_STREAM_ID (STB_CBUS_BASE + 0x15) +#define P_VIDEO_STREAM_ID CBUS_REG_ADDR(VIDEO_STREAM_ID) +#define VIDEO_STREAM_ID_2 (STB_CBUS_BASE + 0x65) +#define P_VIDEO_STREAM_ID_2 CBUS_REG_ADDR(VIDEO_STREAM_ID_2) +#define VIDEO_STREAM_ID_3 (STB_CBUS_BASE + 0xb5) +#define P_VIDEO_STREAM_ID_3 CBUS_REG_ADDR(VIDEO_STREAM_ID_3) +#define AUDIO_STREAM_ID (STB_CBUS_BASE + 0x16) +#define P_AUDIO_STREAM_ID CBUS_REG_ADDR(AUDIO_STREAM_ID) +#define AUDIO_STREAM_ID_2 (STB_CBUS_BASE + 0x66) +#define P_AUDIO_STREAM_ID_2 CBUS_REG_ADDR(AUDIO_STREAM_ID_2) +#define AUDIO_STREAM_ID_3 (STB_CBUS_BASE + 0xb6) +#define P_AUDIO_STREAM_ID_3 CBUS_REG_ADDR(AUDIO_STREAM_ID_3) +#define SUB_STREAM_ID (STB_CBUS_BASE + 0x17) +#define P_SUB_STREAM_ID CBUS_REG_ADDR(SUB_STREAM_ID) +#define SUB_STREAM_ID_2 (STB_CBUS_BASE + 0x67) +#define P_SUB_STREAM_ID_2 CBUS_REG_ADDR(SUB_STREAM_ID_2) +#define SUB_STREAM_ID_3 (STB_CBUS_BASE + 0xb7) +#define P_SUB_STREAM_ID_3 CBUS_REG_ADDR(SUB_STREAM_ID_3) +#define OTHER_STREAM_ID (STB_CBUS_BASE + 0x18) +#define P_OTHER_STREAM_ID CBUS_REG_ADDR(OTHER_STREAM_ID) +#define OTHER_STREAM_ID_2 (STB_CBUS_BASE + 0x68) +#define P_OTHER_STREAM_ID_2 CBUS_REG_ADDR(OTHER_STREAM_ID_2) +#define OTHER_STREAM_ID_3 (STB_CBUS_BASE + 0xb8) +#define P_OTHER_STREAM_ID_3 CBUS_REG_ADDR(OTHER_STREAM_ID_3) +#define PCR90K_CTL (STB_CBUS_BASE + 0x19) +#define P_PCR90K_CTL CBUS_REG_ADDR(PCR90K_CTL) +#define PCR90K_CTL_2 (STB_CBUS_BASE + 0x69) +#define P_PCR90K_CTL_2 CBUS_REG_ADDR(PCR90K_CTL_2) +#define PCR90K_CTL_3 (STB_CBUS_BASE + 0xb9) +#define P_PCR90K_CTL_3 CBUS_REG_ADDR(PCR90K_CTL_3) +/*no used end*/ +#define PCR_DEMUX (STB_CBUS_BASE + 0x1a) +#define P_PCR_DEMUX CBUS_REG_ADDR(PCR_DEMUX) +#define PCR_DEMUX_2 (STB_CBUS_BASE + 0x6a) +#define P_PCR_DEMUX_2 CBUS_REG_ADDR(PCR_DEMUX_2) +#define PCR_DEMUX_3 (STB_CBUS_BASE + 0xba) +#define P_PCR_DEMUX_3 CBUS_REG_ADDR(PCR_DEMUX_3) + +#define VIDEO_PTS_DEMUX (STB_CBUS_BASE + 0x1b) +#define P_VIDEO_PTS_DEMUX CBUS_REG_ADDR(VIDEO_PTS_DEMUX) +#define VIDEO_PTS_DEMUX_2 (STB_CBUS_BASE + 0x6b) +#define P_VIDEO_PTS_DEMUX_2 CBUS_REG_ADDR(VIDEO_PTS_DEMUX_2) +#define VIDEO_PTS_DEMUX_3 (STB_CBUS_BASE + 0xbb) +#define P_VIDEO_PTS_DEMUX_3 CBUS_REG_ADDR(VIDEO_PTS_DEMUX_3) +/*no used*/ +#define VIDEO_DTS_DEMUX (STB_CBUS_BASE + 0x1c) +#define P_VIDEO_DTS_DEMUX CBUS_REG_ADDR(VIDEO_DTS_DEMUX) +#define VIDEO_DTS_DEMUX_2 (STB_CBUS_BASE + 0x6c) +#define P_VIDEO_DTS_DEMUX_2 CBUS_REG_ADDR(VIDEO_DTS_DEMUX_2) +#define VIDEO_DTS_DEMUX_3 (STB_CBUS_BASE + 0xbc) +#define P_VIDEO_DTS_DEMUX_3 CBUS_REG_ADDR(VIDEO_DTS_DEMUX_3) +/*no used end*/ +#define AUDIO_PTS_DEMUX (STB_CBUS_BASE + 0x1d) +#define P_AUDIO_PTS_DEMUX CBUS_REG_ADDR(AUDIO_PTS_DEMUX) +#define AUDIO_PTS_DEMUX_2 (STB_CBUS_BASE + 0x6d) +#define P_AUDIO_PTS_DEMUX_2 CBUS_REG_ADDR(AUDIO_PTS_DEMUX_2) +#define AUDIO_PTS_DEMUX_3 (STB_CBUS_BASE + 0xbd) +#define P_AUDIO_PTS_DEMUX_3 CBUS_REG_ADDR(AUDIO_PTS_DEMUX_3) +/*no used */ +#define SUB_PTS_DEMUX (STB_CBUS_BASE + 0x1e) +#define P_SUB_PTS_DEMUX CBUS_REG_ADDR(SUB_PTS_DEMUX) +#define SUB_PTS_DEMUX_2 (STB_CBUS_BASE + 0x6e) +#define P_SUB_PTS_DEMUX_2 CBUS_REG_ADDR(SUB_PTS_DEMUX_2) +#define SUB_PTS_DEMUX_3 (STB_CBUS_BASE + 0xbe) +#define P_SUB_PTS_DEMUX_3 CBUS_REG_ADDR(SUB_PTS_DEMUX_3) +/*no used end*/ +#define STB_PTS_DTS_STATUS (STB_CBUS_BASE + 0x1f) +#define P_STB_PTS_DTS_STATUS CBUS_REG_ADDR(STB_PTS_DTS_STATUS) +#define STB_PTS_DTS_STATUS_2 (STB_CBUS_BASE + 0x6f) +#define P_STB_PTS_DTS_STATUS_2 CBUS_REG_ADDR(STB_PTS_DTS_STATUS_2) +#define STB_PTS_DTS_STATUS_3 (STB_CBUS_BASE + 0xbf) +#define P_STB_PTS_DTS_STATUS_3 CBUS_REG_ADDR(STB_PTS_DTS_STATUS_3) + +/*no use*/ +#define STB_DEBUG_INDEX (STB_CBUS_BASE + 0x20) +#define P_STB_DEBUG_INDEX CBUS_REG_ADDR(STB_DEBUG_INDEX) +#define STB_DEBUG_INDEX_2 (STB_CBUS_BASE + 0x70) +#define P_STB_DEBUG_INDEX_2 CBUS_REG_ADDR(STB_DEBUG_INDEX_2) +#define STB_DEBUG_INDEX_3 (STB_CBUS_BASE + 0xc0) +#define P_STB_DEBUG_INDEX_3 CBUS_REG_ADDR(STB_DEBUG_INDEX_3) +#define STB_DEBUG_DATAUT_O (STB_CBUS_BASE + 0x21) +#define P_STB_DEBUG_DATAUT_O CBUS_REG_ADDR(STB_DEBUG_DATAUT_O) +#define STB_DEBUG_DATAUT_O_2 (STB_CBUS_BASE + 0x71) +#define P_STB_DEBUG_DATAUT_O_2 CBUS_REG_ADDR(STB_DEBUG_DATAUT_O_2) +#define STB_DEBUG_DATAUT_O_3 (STB_CBUS_BASE + 0xc1) +#define P_STB_DEBUG_DATAUT_O_3 CBUS_REG_ADDR(STB_DEBUG_DATAUT_O_3) +/*no use end*/ + +#define STBM_CTL_O (STB_CBUS_BASE + 0x22) +#define P_STBM_CTL_O CBUS_REG_ADDR(STBM_CTL_O) +#define STBM_CTL_O_2 (STB_CBUS_BASE + 0x72) +#define P_STBM_CTL_O_2 CBUS_REG_ADDR(STBM_CTL_O_2) +#define STBM_CTL_O_3 (STB_CBUS_BASE + 0xc2) +#define P_STBM_CTL_O_3 CBUS_REG_ADDR(STBM_CTL_O_3) +#define STB_INT_STATUS (STB_CBUS_BASE + 0x23) +#define P_STB_INT_STATUS CBUS_REG_ADDR(STB_INT_STATUS) +#define STB_INT_STATUS_2 (STB_CBUS_BASE + 0x73) +#define P_STB_INT_STATUS_2 CBUS_REG_ADDR(STB_INT_STATUS_2) +#define STB_INT_STATUS_3 (STB_CBUS_BASE + 0xc3) +#define P_STB_INT_STATUS_3 CBUS_REG_ADDR(STB_INT_STATUS_3) +#define DEMUX_ENDIAN (STB_CBUS_BASE + 0x24) +#define P_DEMUX_ENDIAN CBUS_REG_ADDR(DEMUX_ENDIAN) +#define DEMUX_ENDIAN_2 (STB_CBUS_BASE + 0x74) +#define P_DEMUX_ENDIAN_2 CBUS_REG_ADDR(DEMUX_ENDIAN_2) +#define DEMUX_ENDIAN_3 (STB_CBUS_BASE + 0xc4) +#define P_DEMUX_ENDIAN_3 CBUS_REG_ADDR(DEMUX_ENDIAN_3) +#define TS_HIU_CTL (STB_CBUS_BASE + 0x25) +#define P_TS_HIU_CTL CBUS_REG_ADDR(TS_HIU_CTL) +#define TS_HIU_CTL_2 (STB_CBUS_BASE + 0x75) +#define P_TS_HIU_CTL_2 CBUS_REG_ADDR(TS_HIU_CTL_2) +#define TS_HIU_CTL_3 (STB_CBUS_BASE + 0xc5) +#define P_TS_HIU_CTL_3 CBUS_REG_ADDR(TS_HIU_CTL_3) + +#define SEC_BUFF_BASE (STB_CBUS_BASE + 0x26) +#define P_SEC_BUFF_BASE CBUS_REG_ADDR(SEC_BUFF_BASE) +#define SEC_BUFF_BASE_2 (STB_CBUS_BASE + 0x76) +#define P_SEC_BUFF_BASE_2 CBUS_REG_ADDR(SEC_BUFF_BASE_2) +#define SEC_BUFF_BASE_3 (STB_CBUS_BASE + 0xc6) +#define P_SEC_BUFF_BASE_3 CBUS_REG_ADDR(SEC_BUFF_BASE_3) +#define DEMUX_MEM_REQ_EN (STB_CBUS_BASE + 0x27) +#define P_DEMUX_MEM_REQ_EN CBUS_REG_ADDR(DEMUX_MEM_REQ_EN) +#define DEMUX_MEM_REQ_EN_2 (STB_CBUS_BASE + 0x77) +#define P_DEMUX_MEM_REQ_EN_2 CBUS_REG_ADDR(DEMUX_MEM_REQ_EN_2) +#define DEMUX_MEM_REQ_EN_3 (STB_CBUS_BASE + 0xc7) +#define P_DEMUX_MEM_REQ_EN_3 CBUS_REG_ADDR(DEMUX_MEM_REQ_EN_3) + + +/*no use*/ +#define VIDEO_PDTS_WR_PTR (STB_CBUS_BASE + 0x28) +#define P_VIDEO_PDTS_WR_PTR CBUS_REG_ADDR(VIDEO_PDTS_WR_PTR) +#define VIDEO_PDTS_WR_PTR_2 (STB_CBUS_BASE + 0x78) +#define P_VIDEO_PDTS_WR_PTR_2 CBUS_REG_ADDR(VIDEO_PDTS_WR_PTR_2) +#define VIDEO_PDTS_WR_PTR_3 (STB_CBUS_BASE + 0xc8) +#define P_VIDEO_PDTS_WR_PTR_3 CBUS_REG_ADDR(VIDEO_PDTS_WR_PTR_3) +#define AUDIO_PDTS_WR_PTR (STB_CBUS_BASE + 0x29) +#define P_AUDIO_PDTS_WR_PTR CBUS_REG_ADDR(AUDIO_PDTS_WR_PTR) +#define AUDIO_PDTS_WR_PTR_2 (STB_CBUS_BASE + 0x79) +#define P_AUDIO_PDTS_WR_PTR_2 CBUS_REG_ADDR(AUDIO_PDTS_WR_PTR_2) +#define AUDIO_PDTS_WR_PTR_3 (STB_CBUS_BASE + 0xc9) +#define P_AUDIO_PDTS_WR_PTR_3 CBUS_REG_ADDR(AUDIO_PDTS_WR_PTR_3) +#define SUB_WR_PTR (STB_CBUS_BASE + 0x2a) +#define P_SUB_WR_PTR CBUS_REG_ADDR(SUB_WR_PTR) +#define SUB_WR_PTR_2 (STB_CBUS_BASE + 0x7a) +#define P_SUB_WR_PTR_2 CBUS_REG_ADDR(SUB_WR_PTR_2) +#define SUB_WR_PTR_3 (STB_CBUS_BASE + 0xca) +#define P_SUB_WR_PTR_3 CBUS_REG_ADDR(SUB_WR_PTR_3) +/*no use*/ + +#define SB_START (STB_CBUS_BASE + 0x2b) +#define P_SB_START CBUS_REG_ADDR(SB_START) +#define SB_START_2 (STB_CBUS_BASE + 0x7b) +#define P_SB_START_2 CBUS_REG_ADDR(SB_START_2) +#define SB_START_3 (STB_CBUS_BASE + 0xcb) +#define P_SB_START_3 CBUS_REG_ADDR(SB_START_3) +#define SB_LAST_ADDR (STB_CBUS_BASE + 0x2c) +#define P_SB_LAST_ADDR CBUS_REG_ADDR(SB_LAST_ADDR) +#define SB_LAST_ADDR_2 (STB_CBUS_BASE + 0x7c) +#define P_SB_LAST_ADDR_2 CBUS_REG_ADDR(SB_LAST_ADDR_2) +#define SB_LAST_ADDR_3 (STB_CBUS_BASE + 0xcc) +#define P_SB_LAST_ADDR_3 CBUS_REG_ADDR(SB_LAST_ADDR_3) +#define SB_PES_WR_PTR (STB_CBUS_BASE + 0x2d) +#define P_SB_PES_WR_PTR CBUS_REG_ADDR(SB_PES_WR_PTR) +#define SB_PES_WR_PTR_2 (STB_CBUS_BASE + 0x7d) +#define P_SB_PES_WR_PTR_2 CBUS_REG_ADDR(SB_PES_WR_PTR_2) +#define SB_PES_WR_PTR_3 (STB_CBUS_BASE + 0xcd) +#define P_SB_PES_WR_PTR_3 CBUS_REG_ADDR(SB_PES_WR_PTR_3) +#define OTHER_WR_PTR (STB_CBUS_BASE + 0x2e) +#define P_OTHER_WR_PTR CBUS_REG_ADDR(OTHER_WR_PTR) +#define OTHER_WR_PTR_2 (STB_CBUS_BASE + 0x7e) +#define P_OTHER_WR_PTR_2 CBUS_REG_ADDR(OTHER_WR_PTR_2) +#define OTHER_WR_PTR_3 (STB_CBUS_BASE + 0xce) +#define P_OTHER_WR_PTR_3 CBUS_REG_ADDR(OTHER_WR_PTR_3) + +#define OB_START (STB_CBUS_BASE + 0x2f) +#define P_OB_START CBUS_REG_ADDR(OB_START) +#define OB_START_2 (STB_CBUS_BASE + 0x7f) +#define P_OB_START_2 CBUS_REG_ADDR(OB_START_2) +#define OB_START_3 (STB_CBUS_BASE + 0xcf) +#define P_OB_START_3 CBUS_REG_ADDR(OB_START_3) +#define OB_LAST_ADDR (STB_CBUS_BASE + 0x30) +#define P_OB_LAST_ADDR CBUS_REG_ADDR(OB_LAST_ADDR) +#define OB_LAST_ADDR_2 (STB_CBUS_BASE + 0x80) +#define P_OB_LAST_ADDR_2 CBUS_REG_ADDR(OB_LAST_ADDR_2) +#define OB_LAST_ADDR_3 (STB_CBUS_BASE + 0xd0) +#define P_OB_LAST_ADDR_3 CBUS_REG_ADDR(OB_LAST_ADDR_3) +#define OB_PES_WR_PTR (STB_CBUS_BASE + 0x31) +#define P_OB_PES_WR_PTR CBUS_REG_ADDR(OB_PES_WR_PTR) +#define OB_PES_WR_PTR_2 (STB_CBUS_BASE + 0x81) +#define P_OB_PES_WR_PTR_2 CBUS_REG_ADDR(OB_PES_WR_PTR_2) +#define OB_PES_WR_PTR_3 (STB_CBUS_BASE + 0xd1) +#define P_OB_PES_WR_PTR_3 CBUS_REG_ADDR(OB_PES_WR_PTR_3) +#define STB_INT_MASK (STB_CBUS_BASE + 0x32) +#define P_STB_INT_MASK CBUS_REG_ADDR(STB_INT_MASK) +#define STB_INT_MASK_2 (STB_CBUS_BASE + 0x82) +#define P_STB_INT_MASK_2 CBUS_REG_ADDR(STB_INT_MASK_2) +#define STB_INT_MASK_3 (STB_CBUS_BASE + 0xd2) +#define P_STB_INT_MASK_3 CBUS_REG_ADDR(STB_INT_MASK_3) +/*no used */ +#define VIDEO_SPLICING_CTL (STB_CBUS_BASE + 0x33) +#define P_VIDEO_SPLICING_CTL CBUS_REG_ADDR(VIDEO_SPLICING_CTL) +#define VIDEO_SPLICING_CTL_2 (STB_CBUS_BASE + 0x83) +#define P_VIDEO_SPLICING_CTL_2 CBUS_REG_ADDR(VIDEO_SPLICING_CTL_2) +#define VIDEO_SPLICING_CTL_3 (STB_CBUS_BASE + 0xd3) +#define P_VIDEO_SPLICING_CTL_3 CBUS_REG_ADDR(VIDEO_SPLICING_CTL_3) +#define AUDIO_SPLICING_CTL (STB_CBUS_BASE + 0x34) +#define P_AUDIO_SPLICING_CTL CBUS_REG_ADDR(AUDIO_SPLICING_CTL) +#define AUDIO_SPLICING_CTL_2 (STB_CBUS_BASE + 0x84) +#define P_AUDIO_SPLICING_CTL_2 CBUS_REG_ADDR(AUDIO_SPLICING_CTL_2) +#define AUDIO_SPLICING_CTL_3 (STB_CBUS_BASE + 0xd4) +#define P_AUDIO_SPLICING_CTL_3 CBUS_REG_ADDR(AUDIO_SPLICING_CTL_3) +#define TS_PACKAGE_BYTE_COUNT (STB_CBUS_BASE + 0x35) +#define P_TS_PACKAGE_BYTE_COUNT \ + CBUS_REG_ADDR(TS_PACKAGE_BYTE_COUNT) +#define TS_PACKAGE_BYTE_COUNT_2 (STB_CBUS_BASE + 0x85) +#define P_TS_PACKAGE_BYTE_COUNT_2 \ + CBUS_REG_ADDR(TS_PACKAGE_BYTE_COUNT_2) +#define TS_PACKAGE_BYTE_COUNT_3 (STB_CBUS_BASE + 0xd5) +#define P_TS_PACKAGE_BYTE_COUNT_3 \ + CBUS_REG_ADDR(TS_PACKAGE_BYTE_COUNT_3) +/*no used end*/ + +#define PES_STRONG_SYNC (STB_CBUS_BASE + 0x36) +#define P_PES_STRONG_SYNC CBUS_REG_ADDR(PES_STRONG_SYNC) +#define PES_STRONG_SYNC_2 (STB_CBUS_BASE + 0x86) +#define P_PES_STRONG_SYNC_2 CBUS_REG_ADDR(PES_STRONG_SYNC_2) +#define PES_STRONG_SYNC_3 (STB_CBUS_BASE + 0xd6) +#define P_PES_STRONG_SYNC_3 CBUS_REG_ADDR(PES_STRONG_SYNC_3) + +#define OM_DATA_RD_ADDR (STB_CBUS_BASE + 0x37) +#define P_OM_DATA_RD_ADDR CBUS_REG_ADDR(OM_DATA_RD_ADDR) +#define OM_DATA_RD_ADDR_2 (STB_CBUS_BASE + 0x87) +#define P_OM_DATA_RD_ADDR_2 CBUS_REG_ADDR(OM_DATA_RD_ADDR_2) +#define OM_DATA_RD_ADDR_3 (STB_CBUS_BASE + 0xd7) +#define P_OM_DATA_RD_ADDR_3 CBUS_REG_ADDR(OM_DATA_RD_ADDR_3) +#define OM_DATA_RD (STB_CBUS_BASE + 0x38) +#define P_OM_DATA_RD CBUS_REG_ADDR(OM_DATA_RD) +#define OM_DATA_RD_2 (STB_CBUS_BASE + 0x88) +#define P_OM_DATA_RD_2 CBUS_REG_ADDR(OM_DATA_RD_2) +#define OM_DATA_RD_3 (STB_CBUS_BASE + 0xd8) +#define P_OM_DATA_RD_3 CBUS_REG_ADDR(OM_DATA_RD_3) + +/*no used*/ + +#define SECTION_AUTO_STOP_3 (STB_CBUS_BASE + 0x39) +#define P_SECTION_AUTO_STOP_3 CBUS_REG_ADDR(SECTION_AUTO_STOP_3) +#define SECTION_AUTO_STOP_3_2 (STB_CBUS_BASE + 0x89) +#define P_SECTION_AUTO_STOP_3_2 \ + CBUS_REG_ADDR(SECTION_AUTO_STOP_3_2) +#define SECTION_AUTO_STOP_3_3 (STB_CBUS_BASE + 0xd9) +#define P_SECTION_AUTO_STOP_3_3 \ + CBUS_REG_ADDR(SECTION_AUTO_STOP_3_3) +#define SECTION_AUTO_STOP_2 (STB_CBUS_BASE + 0x3a) +#define P_SECTION_AUTO_STOP_2 \ + CBUS_REG_ADDR(SECTION_AUTO_STOP_2) +#define SECTION_AUTO_STOP_2_2 (STB_CBUS_BASE + 0x8a) +#define P_SECTION_AUTO_STOP_2_2 \ + CBUS_REG_ADDR(SECTION_AUTO_STOP_2_2) +#define SECTION_AUTO_STOP_2_3 (STB_CBUS_BASE + 0xda) +#define P_SECTION_AUTO_STOP_2_3 \ + CBUS_REG_ADDR(SECTION_AUTO_STOP_2_3) +#define SECTION_AUTO_STOP_1 (STB_CBUS_BASE + 0x3b) +#define P_SECTION_AUTO_STOP_1 CBUS_REG_ADDR(SECTION_AUTO_STOP_1) +#define SECTION_AUTO_STOP_1_2 (STB_CBUS_BASE + 0x8b) +#define P_SECTION_AUTO_STOP_1_2 \ + CBUS_REG_ADDR(SECTION_AUTO_STOP_1_2) +#define SECTION_AUTO_STOP_1_3 (STB_CBUS_BASE + 0xdb) +#define P_SECTION_AUTO_STOP_1_3 \ + CBUS_REG_ADDR(SECTION_AUTO_STOP_1_3) +#define SECTION_AUTO_STOP_0 (STB_CBUS_BASE + 0x3c) +#define P_SECTION_AUTO_STOP_0 \ + CBUS_REG_ADDR(SECTION_AUTO_STOP_0) +#define SECTION_AUTO_STOP_0_2 (STB_CBUS_BASE + 0x8c) +#define P_SECTION_AUTO_STOP_0_2 \ + CBUS_REG_ADDR(SECTION_AUTO_STOP_0_2) +#define SECTION_AUTO_STOP_0_3 (STB_CBUS_BASE + 0xdc) +#define P_SECTION_AUTO_STOP_0_3 \ + CBUS_REG_ADDR(SECTION_AUTO_STOP_0_3) + +#define DEMUX_CHANNEL_RESET (STB_CBUS_BASE + 0x3d) +#define P_DEMUX_CHANNEL_RESET \ + CBUS_REG_ADDR(DEMUX_CHANNEL_RESET) +#define DEMUX_CHANNEL_RESET_2 (STB_CBUS_BASE + 0x8d) +#define P_DEMUX_CHANNEL_RESET_2 \ + CBUS_REG_ADDR(DEMUX_CHANNEL_RESET_2) +#define DEMUX_CHANNEL_RESET_3 (STB_CBUS_BASE + 0xdd) +#define P_DEMUX_CHANNEL_RESET_3 \ + CBUS_REG_ADDR(DEMUX_CHANNEL_RESET_3) +/*no use end*/ +#define DEMUX_SCRAMBLING_STATE (STB_CBUS_BASE + 0x3e) +#define DEMUX_SCRAMBLING_STATE_2 (STB_CBUS_BASE + 0x8e) +#define P_DEMUX_SCRAMBLING_STATE_2 \ + CBUS_REG_ADDR(DEMUX_SCRAMBLING_STATE_2) +#define DEMUX_SCRAMBLING_STATE_3 (STB_CBUS_BASE + 0xde) +#define P_DEMUX_SCRAMBLING_STATE_3 \ + CBUS_REG_ADDR(DEMUX_SCRAMBLING_STATE_3) +#define DEMUX_CHANNEL_ACTIVITY (STB_CBUS_BASE + 0x3f) +#define P_DEMUX_CHANNEL_ACTIVITY \ + CBUS_REG_ADDR(DEMUX_CHANNEL_ACTIVITY) +#define DEMUX_CHANNEL_ACTIVITY_2 (STB_CBUS_BASE + 0x8f) +#define P_DEMUX_CHANNEL_ACTIVITY_2 \ + CBUS_REG_ADDR(DEMUX_CHANNEL_ACTIVITY_2) +#define DEMUX_CHANNEL_ACTIVITY_3 (STB_CBUS_BASE + 0xdf) +#define P_DEMUX_CHANNEL_ACTIVITY_3 \ + CBUS_REG_ADDR(DEMUX_CHANNEL_ACTIVITY_3) + +/*no use*/ + +#define DEMUX_STAMP_CTL (STB_CBUS_BASE + 0x40) +#define P_DEMUX_STAMP_CTL CBUS_REG_ADDR(DEMUX_STAMP_CTL) +#define DEMUX_STAMP_CTL_2 (STB_CBUS_BASE + 0x90) +#define P_DEMUX_STAMP_CTL_2 \ + CBUS_REG_ADDR(DEMUX_STAMP_CTL_2) +#define DEMUX_STAMP_CTL_3 (STB_CBUS_BASE + 0xe0) +#define P_DEMUX_STAMP_CTL_3 \ + CBUS_REG_ADDR(DEMUX_STAMP_CTL_3) +#define DEMUX_VIDEO_STAMP_SYNC_0 (STB_CBUS_BASE + 0x41) +#define P_DEMUX_VIDEO_STAMP_SYNC_0 \ + CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_0) +#define DEMUX_VIDEO_STAMP_SYNC_0_2 (STB_CBUS_BASE + 0x91) +#define P_DEMUX_VIDEO_STAMP_SYNC_0_2 \ + CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_0_2) +#define DEMUX_VIDEO_STAMP_SYNC_0_3 (STB_CBUS_BASE + 0xe1) +#define P_DEMUX_VIDEO_STAMP_SYNC_0_3 \ + CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_0_3) +#define DEMUX_VIDEO_STAMP_SYNC_1 (STB_CBUS_BASE + 0x42) +#define P_DEMUX_VIDEO_STAMP_SYNC_1 \ + CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_1) +#define DEMUX_VIDEO_STAMP_SYNC_1_2 (STB_CBUS_BASE + 0x92) +#define P_DEMUX_VIDEO_STAMP_SYNC_1_2 \ + CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_1_2) +#define DEMUX_VIDEO_STAMP_SYNC_1_3 (STB_CBUS_BASE + 0xe2) +#define P_DEMUX_VIDEO_STAMP_SYNC_1_3 \ + CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_1_3) +#define DEMUX_AUDIO_STAMP_SYNC_0 (STB_CBUS_BASE + 0x43) +#define P_DEMUX_AUDIO_STAMP_SYNC_0 \ + CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_0) +#define DEMUX_AUDIO_STAMP_SYNC_0_2 (STB_CBUS_BASE + 0x93) +#define P_DEMUX_AUDIO_STAMP_SYNC_0_2 \ + CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_0_2) +#define DEMUX_AUDIO_STAMP_SYNC_0_3 (STB_CBUS_BASE + 0xe3) +#define P_DEMUX_AUDIO_STAMP_SYNC_0_3 \ + CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_0_3) +#define DEMUX_AUDIO_STAMP_SYNC_1 (STB_CBUS_BASE + 0x44) +#define P_DEMUX_AUDIO_STAMP_SYNC_1 \ + CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_1) +#define DEMUX_AUDIO_STAMP_SYNC_1_2 (STB_CBUS_BASE + 0x94) +#define P_DEMUX_AUDIO_STAMP_SYNC_1_2 \ + CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_1_2) +#define DEMUX_AUDIO_STAMP_SYNC_1_3 (STB_CBUS_BASE + 0xe4) +#define P_DEMUX_AUDIO_STAMP_SYNC_1_3 \ + CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_1_3) +#define DEMUX_SECTION_RESET (STB_CBUS_BASE + 0x45) +#define P_DEMUX_SECTION_RESET CBUS_REG_ADDR(DEMUX_SECTION_RESET) +#define DEMUX_SECTION_RESET_2 (STB_CBUS_BASE + 0x95) +#define P_DEMUX_SECTION_RESET_2 \ + CBUS_REG_ADDR(DEMUX_SECTION_RESET_2) +#define DEMUX_SECTION_RESET_3 (STB_CBUS_BASE + 0xe5) +#define P_DEMUX_SECTION_RESET_3 \ + CBUS_REG_ADDR(DEMUX_SECTION_RESET_3) +/*no use end*/ + +/*from c_stb_define.h*/ +#define COMM_DESC_2_CTL (STB_CBUS_BASE + 0xff) /*0x16ff*/ + +#define STB_OM_CTL \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x22) /* 0x1622*/ +#define STB_OM_CTL_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x22) /* 0x1672*/ +#define STB_OM_CTL_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x22) /* 0x16c2*/ + +#define DEMUX_INPUT_TIMEOUT_C \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x46) /* 0x1646*/ +#define DEMUX_INPUT_TIMEOUT_C_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x46) /* 0x1696*/ +#define DEMUX_INPUT_TIMEOUT_C_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x46) /* 0x16e6*/ +/* bit[31] - no_match_reset_timeout_disable*/ +/* bit[30:0] input_time_out_int_cnt (0 -- means disable) Wr-setting, Rd-count*/ +#define DEMUX_INPUT_TIMEOUT \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x47) /* 0x1647*/ +#define DEMUX_INPUT_TIMEOUT_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x47) /* 0x1697*/ +#define DEMUX_INPUT_TIMEOUT_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x47) /* 0x16e7*/ + +/* bit[31:0] - channel_packet_count_disable*/ +#define DEMUX_PACKET_COUNT_C \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x48) /* 0x1648*/ +#define DEMUX_PACKET_COUNT_C_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x48) /* 0x1698*/ +#define DEMUX_PACKET_COUNT_C_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x48) /* 0x16e8*/ +/* bit[31] - no_match_packet_count_disable*/ +/* bit[30:0] input_packet_count*/ +#define DEMUX_PACKET_COUNT \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x49) /* 0x1649*/ +#define DEMUX_PACKET_COUNT_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x49) /* 0x1699*/ +#define DEMUX_PACKET_COUNT_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x49) /* 0x16e9*/ + +/* bit[31:0] channel_record_enable*/ +#define DEMUX_CHAN_RECORD_EN \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4a) /* 0x164a*/ +#define DEMUX_CHAN_RECORD_EN_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4a) /* 0x169a*/ +#define DEMUX_CHAN_RECORD_EN_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4a) /* 0x16ea*/ + +/* bit[31:0] channel_process_enable*/ +#define DEMUX_CHAN_PROCESS_EN \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4b) /* 0x164b*/ +#define DEMUX_CHAN_PROCESS_EN_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4b) /* 0x169b*/ +#define DEMUX_CHAN_PROCESS_EN_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4b) /* 0x16eb*/ + +/* bit[31:24] small_sec_size ((n+1) * 256 Bytes)*/ +/* bit[23:16] small_sec_rd_ptr */ +/* bit[15:8] small_sec_wr_ptr */ +/* bit[7:2] reserved*/ +/* bit[1] small_sec_wr_ptr_wr_enable*/ +/* bit[0] small_section_enable*/ +#define DEMUX_SMALL_SEC_CTL \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4c) /* 0x164c*/ +#define DEMUX_SMALL_SEC_CTL_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4c) /* 0x169c*/ +#define DEMUX_SMALL_SEC_CTL_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4c) /* 0x16ec*/ +/* bit[31:0] small_sec_start_addr*/ +#define DEMUX_SMALL_SEC_ADDR \ + (STB_CBUS_BASE + DEMUX_1_OFFSET + 0x4d) /* 0x164d*/ +#define DEMUX_SMALL_SEC_ADDR_2 \ + (STB_CBUS_BASE + DEMUX_2_OFFSET + 0x4d) /* 0x169d*/ +#define DEMUX_SMALL_SEC_ADDR_3 \ + (STB_CBUS_BASE + DEMUX_3_OFFSET + 0x4d) /* 0x16ed*/ + +#endif diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/Makefile b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/Makefile new file mode 100644 index 000000000000..e258f64ad7dd --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/Makefile @@ -0,0 +1,9 @@ +obj-m += aml_hardware_spi.o aml_hardware_pcmcia.o aml_hardware_ci.o + +ccflags-y += -I$(srctree)/drivers/media/dvb-core -I$(srctree)/drivers/gpio -I$(srctree)/include + +aml_hardware_spi-objs += aml_spi.o + +aml_hardware_pcmcia-objs += aml_pcmcia.o + +aml_hardware_ci-objs += aml_ci.o diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/aml_ci.c b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/aml_ci.c new file mode 100644 index 000000000000..bf72b4ec5a5b --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/aml_ci.c @@ -0,0 +1,448 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "aml_ci.h" +#include "aml_spi.h" + +MODULE_PARM_DESC(aml_ci_debug, "\n\t\t dvb ci debug"); +static int aml_ci_debug = 1; +module_param(aml_ci_debug, int, 0444); + +#define pr_dbg(args...)\ + do {\ + if (aml_ci_debug)\ + printk(args);\ + } while (0) +#define pr_error(fmt, args...) printk("DVBCI: " fmt, ## args) +/**\brief aml_ci_mem_read:mem read from cam + * \param en50221: en50221 obj,used this data to get dvb_ci obj + * \param slot: slot index + * \param addr: read addr + * \return + * - read value:ok + * - -EINVAL : error + */ +static int aml_ci_mem_read(struct dvb_ca_en50221 *en50221, int slot, int addr) +{ + struct aml_ci *ci = en50221->data; + + if (slot != 0) { + pr_error("slot !=0 %s :%d\r\n", __func__, slot); + return -EINVAL; + } + + if (ci->ci_mem_read != NULL) + return ci->ci_mem_read(ci, slot, addr); + + pr_error("ci_mem_read is null %s\r\n", __func__); + return -EINVAL; +} +/**\brief aml_ci_mem_write:mem write to cam + * \param en50221: en50221 obj,used this data to get dvb_ci obj + * \param slot: slot index + * \param addr: write addr + * \param addr: write value + * \return + * - 0:ok + * - -EINVAL : error + */ +static int aml_ci_mem_write(struct dvb_ca_en50221 *en50221, + int slot, int addr, u8 data) +{ + + struct aml_ci *ci = en50221->data; + + if (slot != 0) { + pr_error("slot not 0 %s :%d\r\n", __func__, slot); + return -EINVAL; + } + + if (ci->ci_mem_write != NULL) + return ci->ci_mem_write(ci, slot, addr, data); + pr_error("ci_mem_write is null %s\r\n", __func__); + return -EINVAL; +} +/**\brief aml_ci_io_read:io read from cam + * \param en50221: en50221 obj,used this data to get dvb_ci obj + * \param slot: slot index + * \param addr: read addr + * \return + * - read value:ok + * - -EINVAL : error + */ +static int aml_ci_io_read(struct dvb_ca_en50221 *en50221, int slot, u8 addr) +{ + struct aml_ci *ci = en50221->data; + + if (slot != 0) { + pr_error("slot !=0 %s :%d\r\n", __func__, slot); + return -EINVAL; + } + + if (ci->ci_io_read != NULL) + return ci->ci_io_read(ci, slot, addr); + + pr_error("ci_io_read is null %s\r\n", __func__); + return -EINVAL; +} +/**\brief aml_ci_io_write:io write to cam + * \param en50221: en50221 obj,used this data to get dvb_ci obj + * \param slot: slot index + * \param addr: write addr + * \param addr: write value + * \return + * - 0:ok + * - -EINVAL : error + */ +static int aml_ci_io_write( + struct dvb_ca_en50221 *en50221, int slot, u8 addr, u8 data) +{ + struct aml_ci *ci = en50221->data; + + if (slot != 0) { + pr_error("slot !=0 %s :%d\r\n", __func__, slot); + return -EINVAL; + } + + if (ci->ci_mem_write != NULL) + return ci->ci_io_write(ci, slot, addr, data); + + pr_error("ci_io_write is null %s\r\n", __func__); + return -EINVAL; +} +/**\brief aml_ci_slot_reset:reset slot + * \param en50221: en50221 obj,used this data to get dvb_ci obj + * \param slot: slot index + * \return + * - 0:ok + * - -EINVAL : error + */ +static int aml_ci_slot_reset(struct dvb_ca_en50221 *en50221, int slot) +{ + struct aml_ci *ci = en50221->data; + + pr_dbg("Slot(%d): Slot RESET\n", slot); + if (ci->ci_slot_reset != NULL) { + ci->ci_slot_reset(ci, slot); + } else { + pr_error("ci_slot_reset is null %s\r\n", __func__); + return -EINVAL; + } + return 0; +} +/**\brief aml_ci_slot_shutdown:show slot + * \param en50221: en50221 obj,used this data to get dvb_ci obj + * \param slot: slot index + * \return + * - 0:ok + * - -EINVAL : error + */ +static int aml_ci_slot_shutdown(struct dvb_ca_en50221 *en50221, int slot) +{ + struct aml_ci *ci = en50221->data; + + pr_dbg("Slot(%d): Slot shutdown\n", slot); + if (ci->ci_slot_shutdown != NULL) { + ci->ci_slot_shutdown(ci, slot); + } else { + pr_error("aml_ci_slot_shutdown is null %s\r\n", __func__); + return -EINVAL; + } + return 0; +} +/**\brief aml_ci_ts_control:control slot ts + * \param en50221: en50221 obj,used this data to get dvb_ci obj + * \param slot: slot index + * \return + * - 0:ok + * - -EINVAL : error + */ +static int aml_ci_ts_control(struct dvb_ca_en50221 *en50221, int slot) +{ + + struct aml_ci *ci = en50221->data; + + pr_dbg("Slot(%d): TS control\n", slot); + if (ci->ci_slot_ts_enable != NULL) { + ci->ci_slot_ts_enable(ci, slot); + } else { + pr_error("aml_ci_ts_control is null %s\r\n", __func__); + return -EINVAL; + } + return 0; +} +/**\brief aml_ci_slot_status:get slot status + * \param en50221: en50221 obj,used this data to get dvb_ci obj + * \param slot: slot index + * \param open: no used + * \return + * - cam status + * - -EINVAL : error + */ +static int aml_ci_slot_status( + struct dvb_ca_en50221 *en50221, int slot, int open) +{ + struct aml_ci *ci = en50221->data; + + pr_dbg("Slot(%d): Poll Slot status\n", slot); + + if (ci->ci_poll_slot_status != NULL) + return ci->ci_poll_slot_status(ci, slot, open); + pr_error("ci_poll_slot_status is null %s\r\n", __func__); + return -EINVAL; +} + +/**\brief get ci config from dts + * \param np: device node + * \return + * - 0 æˆåŠŸ + * - 其他值 : + */ +static int aml_ci_get_config_from_dts( + struct platform_device *pdev, struct aml_ci *ci) +{ + char buf[32]; + int ret = 0; + int value; + + snprintf(buf, sizeof(buf), "%s", "io_type"); + ret = of_property_read_u32(pdev->dev.of_node, buf, &value); + if (!ret) { + pr_dbg("%s: 0x%x\n", buf, value); + ci->io_type = value; + } + return 0; +} + +/**\brief aml_ci_init:ci dev init + * \param pdev: platform_device device node,used to get dts info + * \param dvb: aml_dvb obj,used to get dvb_adapter for en0211 to use + * \param cip: ci_dev pp + * \return + * - 0 æˆåŠŸ + * - 其他值 : + */ +int aml_ci_init(struct platform_device *pdev, + struct aml_dvb *dvb, struct aml_ci **cip) +{ + struct dvb_adapter *dvb_adapter = &dvb->dvb_adapter; + struct aml_ci *ci = NULL; + int ca_flags = 0, result; + + ci = kzalloc(sizeof(struct aml_ci), GFP_KERNEL); + if (!ci) { + pr_error("Out of memory!, exiting ..\n"); + result = -ENOMEM; + goto err; + } + ci->id = 0; + aml_ci_get_config_from_dts(pdev, ci); + + ci->priv = dvb; + ca_flags = DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE; + /* register CA interface */ + ci->en50221.owner = THIS_MODULE; + ci->en50221.read_attribute_mem = aml_ci_mem_read; + ci->en50221.write_attribute_mem = aml_ci_mem_write; + ci->en50221.read_cam_control = aml_ci_io_read; + ci->en50221.write_cam_control = aml_ci_io_write; + ci->en50221.slot_reset = aml_ci_slot_reset; + ci->en50221.slot_shutdown = aml_ci_slot_shutdown; + ci->en50221.slot_ts_enable = aml_ci_ts_control; + ci->en50221.poll_slot_status = aml_ci_slot_status; + ci->en50221.data = ci; + + + pr_dbg("Registering EN50221 device\n"); + result = dvb_ca_en50221_init(dvb_adapter, &ci->en50221, ca_flags, 1); + if (result != 0) { + pr_error("EN50221: Initialization failed <%d>\n", result); + goto err; + } + *cip = ci; + pr_dbg("Registered EN50221 device\n"); + if (ci->io_type == AML_DVB_IO_TYPE_SPI) { + /* spi init */ + aml_spi_init(pdev, ci); + } else { + /* no io dev init,is error */ + pr_dbg("io dev no init,we do not known use spi or iobus or other,please check io_type in dts file\r\n"); + } + return 0; +err: + /* for init spi */ + aml_spi_exit(); + kfree(ci); + return result; +} +EXPORT_SYMBOL_GPL(aml_ci_init); + +void aml_ci_exit(struct aml_ci *ci) +{ + pr_dbg("Unregistering EN50221 device\n"); + if (ci) { + dvb_ca_en50221_release(&ci->en50221); + kfree(ci); + } +} +EXPORT_SYMBOL_GPL(aml_ci_exit); + +static struct aml_ci *ci_dev; + +static ssize_t aml_ci_ts_show(struct class *class, +struct class_attribute *attr, char *buf) +{ + int ret; + + ret = sprintf(buf, "ts%d\n", 1); + return ret; +} + +static struct class_attribute amlci_class_attrs[] = { + __ATTR(ts, 0644, aml_ci_ts_show, NULL), + __ATTR_NULL +}; + +static int aml_ci_register_class(struct aml_ci *ci) +{ + #define CLASS_NAME_LEN 48 + int ret; + struct class *clp; + + clp = &(ci->class); + + clp->name = kzalloc(CLASS_NAME_LEN, GFP_KERNEL); + if (!clp->name) + return -ENOMEM; + + snprintf((char *)clp->name, CLASS_NAME_LEN, "amlci-%d", ci->id); + clp->owner = THIS_MODULE; + clp->class_attrs = amlci_class_attrs; + ret = class_register(clp); + if (ret) + kfree(clp->name); + + return 0; +} + +static int aml_ci_unregister_class(struct aml_ci *ci) +{ + class_unregister(&ci->class); + kzfree(ci->class.name); + return 0; +} + + +static int aml_ci_probe(struct platform_device *pdev) +{ + struct aml_dvb *dvb = aml_get_dvb_device(); + int err = 0; + + pr_dbg("---Amlogic CI Init---\n"); + err = aml_ci_init(pdev, dvb, &ci_dev); + if (err < 0) + return err; + platform_set_drvdata(pdev, ci_dev); + aml_ci_register_class(ci_dev); + return 0; +} + +static int aml_ci_remove(struct platform_device *pdev) +{ + aml_ci_unregister_class(ci_dev); + platform_set_drvdata(pdev, NULL); + if (ci_dev->io_type == AML_DVB_IO_TYPE_SPI) + aml_spi_exit(); + else + pr_dbg("---Amlogic CI remove unknown io type---\n"); + + aml_ci_exit(ci_dev); + return 0; +} + +static int aml_ci_suspend(struct platform_device *pdev, pm_message_t state) +{ + pr_dbg("Amlogic CI Suspend!\n"); + if (ci_dev->io_type == AML_DVB_IO_TYPE_SPI) + aml_spi_exit(); + else + pr_dbg("---Amlogic CI remove unknown io type---\n"); + + return 0; +} + +static int aml_ci_resume(struct platform_device *pdev) +{ + int err = 0; + + pr_dbg("Amlogic CI Resume!\n"); + if (ci_dev->io_type == AML_DVB_IO_TYPE_SPI) + aml_spi_init(pdev, ci_dev); + else + pr_dbg("---Amlogic CI remove unknown io type---\n"); + return err; +} + +static const struct of_device_id dvbci_dev_dt_match[] = { + { + .compatible = "amlogic, dvbci", + }, + {}, +}; + + + +static struct platform_driver aml_ci_driver = { + .probe = aml_ci_probe, + .remove = aml_ci_remove, + .suspend = aml_ci_suspend, + .resume = aml_ci_resume, + .driver = { + .name = "dvbci", + .of_match_table = dvbci_dev_dt_match, + .owner = THIS_MODULE, + } +}; + +static int __init aml_ci_mod_init(void) +{ + pr_dbg("Amlogic CI mode init\n"); + return platform_driver_register(&aml_ci_driver); +} + +static void __exit aml_ci_mod_exit(void) +{ + pr_dbg("Amlogic CI mode Exit\n"); + platform_driver_unregister(&aml_ci_driver); +} + +module_init(aml_ci_mod_init); +module_exit(aml_ci_mod_exit); + +MODULE_LICENSE("GPL"); + + diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/aml_ci.h b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/aml_ci.h new file mode 100644 index 000000000000..03f5e5e2c141 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/aml_ci.h @@ -0,0 +1,60 @@ +#ifndef __AML_CI_H_ +#define __AML_CI_H_ + +#include +#include "../aml_dvb.h" + +enum aml_dvb_io_type_e { + AML_DVB_IO_TYPE_IOBUS = 0, + AML_DVB_IO_TYPE_SPI, + AML_DVB_IO_TYPE_MAX, +}; + +struct aml_ci { + struct dvb_ca_en50221 en50221; + struct mutex ci_lock; + int io_type; + void *priv; + int id; + struct class class; + + /* NOTE: the read_*, write_* and poll_slot_status functions will be + * called for different slots concurrently and need to use locks where + * and if appropriate. There will be no concurrent access to one slot. + */ + + /* functions for accessing attribute memory on the CAM */ + int (*ci_mem_read)(struct aml_ci *ca, int slot, int address); + int (*ci_mem_write)(struct aml_ci *ca, int slot, int address, u8 value); + + /* functions for accessing the control interface on the CAM */ + int (*ci_io_read)(struct aml_ci *ca, int slot, int address); + int (*ci_io_write)(struct aml_ci *ca, int slot, int address, u8 value); + + /* Functions for controlling slots */ + int (*ci_slot_reset)(struct aml_ci *ca, int slot); + int (*ci_slot_shutdown)(struct aml_ci *ca, int slot); + int (*ci_slot_ts_enable)(struct aml_ci *ca, int slot); + + /* + * Poll slot status. + * Only necessary if DVB_CA_FLAG_EN50221_IRQ_CAMCHANGE is not set + */ + int (*ci_poll_slot_status)(struct aml_ci *ca, int slot, int open); + + /* private data, used by caller */ + void *data; +}; + +struct ci_dev_config_s { + char name[20]; + unsigned char type; + int cs_hold_delay; + int cs_clk_delay; +}; +extern int aml_ci_init(struct platform_device + *pdev, struct aml_dvb *dvb, struct aml_ci **cip); +extern void aml_ci_exit(struct aml_ci *ci); + +#endif /* __AML_CI_H_ */ + diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/aml_pcmcia.c b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/aml_pcmcia.c new file mode 100644 index 000000000000..b840db43918d --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/aml_pcmcia.c @@ -0,0 +1,200 @@ + +#include +#include +#include +#include +#include +#include + +#include "aml_pcmcia.h" + +static int aml_pcmcia_debug = 1; + +module_param_named(pcmcia_debug, aml_pcmcia_debug, int, 0644); +MODULE_PARM_DESC(pcmcia_debug, "enable verbose debug messages"); + +#define pr_dbg(args...)\ + do {\ + if (aml_pcmcia_debug)\ + printk(args);\ + } while (0) +#define pr_error(fmt, args...) printk("PCMCIA: " fmt, ## args) + + +static int pcmcia_plugin(struct aml_pcmcia *pc) +{ + if (pc->slot_state == MODULE_XTRACTED) { + pr_dbg(" CAM Plugged IN: Adapter(%d) Slot(0)\n", 0); + udelay(50); + aml_pcmcia_reset(pc); + /*wait unplug*/ + pc->init_irq(pc, IRQF_TRIGGER_RISING); + udelay(500); + pc->slot_state = MODULE_INSERTED; + } else { + pr_error("repeat into pcmcia insert \r\n"); + aml_pcmcia_reset(pc); + } + udelay(100); + pc->pcmcia_plugin(pc, 1); + + return 0; +} + +static int pcmcia_unplug(struct aml_pcmcia *pc) +{ + if (pc->slot_state == MODULE_INSERTED) { + pr_dbg(" CAM Unplugged: Adapter(%d) Slot(0)\n", 0); + /*udelay(50);*/ + /*aml_pcmcia_reset(pc);*/ + /*wait plugin*/ + pc->init_irq(pc, IRQF_TRIGGER_FALLING); + udelay(500); + pc->slot_state = MODULE_XTRACTED; + } + udelay(100); + pc->pcmcia_plugin(pc, 0); + + return 0; +} + +static irqreturn_t pcmcia_irq_handler(int irq, void *dev_id) +{ + struct aml_pcmcia *pc = (struct aml_pcmcia *)dev_id; + + pr_dbg("pcmcia_irq_handler--into--\r\n"); + disable_irq_nosync(pc->irq); + schedule_work(&pc->pcmcia_work); + enable_irq(pc->irq); + return IRQ_HANDLED; +} + +static void aml_pcmcia_work(struct work_struct *work) +{ + int cd1, cd2; + struct aml_pcmcia *pc = container_of( + work, struct aml_pcmcia, pcmcia_work); + + cd1 = pc->get_cd1(pc); + cd2 = pc->get_cd2(pc); + + if (cd1 != cd2) + pr_error("CAM card not inerted.\n"); + else { + if (!cd1) { + pr_error("Adapter(%d) Slot(0): CAM Plugin\n", 0); + pcmcia_plugin(pc); + } else { + pr_error("Adapter(%d) Slot(0): CAM Unplug\n", 0); + pcmcia_unplug(pc); + } + } +} + +static struct aml_pcmcia *pc_cur; + +int aml_pcmcia_init(struct aml_pcmcia *pc) +{ + int err = 0; + + pr_dbg("aml_pcmcia_init start pc->irq=%d\r\n", pc->irq); + pc->rst(pc, AML_L); + /*power on*/ + pc->pwr(pc, AML_PWR_OPEN);/*hi is open power*/ + /*assuming cam unpluged, config the INT to waiting-for-plugin mode*/ + pc->init_irq(pc, IRQF_TRIGGER_LOW); + + INIT_WORK(&pc->pcmcia_work, aml_pcmcia_work); + + err = request_irq(pc->irq, + pcmcia_irq_handler, + IRQF_ONESHOT, "aml-pcmcia", pc); + if (err != 0) { + pr_error("ERROR: IRQ registration failed ! <%d>", err); + return -ENODEV; + } + + pc_cur = pc; + pr_dbg("aml_pcmcia_init ok\r\n"); + return 0; +} +EXPORT_SYMBOL(aml_pcmcia_init); + +int aml_pcmcia_exit(struct aml_pcmcia *pc) +{ + free_irq(pc->irq, pc); + return 0; +} +EXPORT_SYMBOL(aml_pcmcia_exit); + +int aml_pcmcia_reset(struct aml_pcmcia *pc) +{ + pr_dbg("CAM RESET-->\n"); + /* viaccess neotion cam need delay 2000 and 3000 */ + /* smit cam need delay 1000 and 1500 */ + /* need change delay according cam vendor */ + pc->rst(pc, AML_H);/*HI is reset*/ + mdelay(1000); + pc->rst(pc, AML_L);/*defaule LOW*/ + pr_dbg("CAM RESET--\n"); + mdelay(1500); + pr_dbg("CAM RESET--end\n"); + return 0; +} +EXPORT_SYMBOL(aml_pcmcia_reset); + + + +static ssize_t aml_pcmcia_test_cmd(struct class *class, +struct class_attribute *attr, const char *buf, size_t size) +{ + pr_dbg("pcmcia cmd: %s\n", buf); + if (pc_cur) { + if (memcmp(buf, "reset", 5) == 0) + aml_pcmcia_reset(pc_cur); + else if (memcmp(buf, "on", 2) == 0) + pc_cur->pwr(pc_cur, AML_PWR_OPEN); + else if (memcmp(buf, "off", 3) == 0) + pc_cur->pwr(pc_cur, AML_PWR_CLOSE); + else if (memcmp(buf, "poll", 4) == 0) + schedule_work(&pc_cur->pcmcia_work); + else if (memcmp(buf, "intr", 4) == 0) + pc_cur->init_irq(pc_cur, IRQF_TRIGGER_RISING); + else if (memcmp(buf, "intf", 4) == 0) + pc_cur->init_irq(pc_cur, IRQF_TRIGGER_FALLING); + } + return size; +} + +static struct class_attribute aml_pcmcia_class_attrs[] = { + __ATTR(cmd, 0644, NULL, aml_pcmcia_test_cmd), + __ATTR_NULL +}; + +static struct class aml_pcmcia_class = { + .name = "aml_pcmcia_test", + .class_attrs = aml_pcmcia_class_attrs, +}; + +static int __init aml_pcmcia_mod_init(void) +{ + pr_dbg("Amlogic PCMCIA Init\n"); + + class_register(&aml_pcmcia_class); + + return 0; +} + +static void __exit aml_pcmcia_mod_exit(void) +{ + pr_dbg("Amlogic PCMCIA Exit\n"); + + class_unregister(&aml_pcmcia_class); +} + + + +module_init(aml_pcmcia_mod_init); +module_exit(aml_pcmcia_mod_exit); + +MODULE_LICENSE("GPL"); diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/aml_pcmcia.h b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/aml_pcmcia.h new file mode 100644 index 000000000000..2d8a3ad4b9fc --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/aml_pcmcia.h @@ -0,0 +1,40 @@ + +#ifndef _AML_PCMCIA_ +#define _AML_PCMCIA_ + +enum aml_slot_state { + MODULE_INSERTED = 3, + MODULE_XTRACTED = 4 +}; + +enum aml_pwr_cmd { + AML_PWR_OPEN = 0, + AML_PWR_CLOSE = 1 +}; +enum aml_reset_cmd { + AML_L = 0, + AML_H = 1 +}; +struct aml_pcmcia { + enum aml_slot_state slot_state; + struct work_struct pcmcia_work; + int run_type;/*0：irq;1:poll*/ + int irq; + int (*init_irq)(struct aml_pcmcia *pc, int flag); + int (*get_cd1)(struct aml_pcmcia *pc); + int (*get_cd2)(struct aml_pcmcia *pc); + int (*pwr)(struct aml_pcmcia *pc, int enable); + int (*rst)(struct aml_pcmcia *pc, int enable); + + int (*pcmcia_plugin)(struct aml_pcmcia *pc, int plugin); + + void *priv; +}; + +int aml_pcmcia_init(struct aml_pcmcia *pc); +int aml_pcmcia_exit(struct aml_pcmcia *pc); +int aml_pcmcia_reset(struct aml_pcmcia *pc); + + +#endif /*_AML_PCMCIA_*/ + diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/aml_spi.c b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/aml_spi.c new file mode 100644 index 000000000000..bbfe295b6977 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/aml_spi.c @@ -0,0 +1,1667 @@ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "aml_spi.h" +#include "aml_ci.h" + +#define AML_MODE_NAME "aml_dvbci_spi" +static int AML_CI_GPIO_IRQ_BASE = 251; +static struct aml_spi *g_spi_dev; +static int aml_spi_debug = 1; +static int G_rec_flag = AM_SPI_STEP_INIT; + + +module_param_named(spi_debug, aml_spi_debug, int, 0644); +MODULE_PARM_DESC(spi_debug, "enable verbose debug messages"); + + +#define pr_dbg(args...)\ + do {\ + if (aml_spi_debug)\ + printk(args);\ + } while (0) +#define pr_error(fmt, args...) printk("AML_CI_SPI: " fmt, ## args) + +struct spi_board_info aml_ci_spi_bdinfo = { + .modalias = "ci_spi_dev", + .mode = SPI_MODE_0, + .max_speed_hz = 1000000, /* 1MHz */ + .bus_num = 0, /* SPI bus No. */ + .chip_select = 0, /* the device index on the spi bus */ + .controller_data = NULL, +}; + +#define NORMAL_MSG (0<<7) +#define BROADCAST_MSG (1<<7) +#define BLOCK_DATA (0<<6) +#define SINGLE_DATA (1<<6) +#define CISPI_DEV_ADDR 1 + +#define INPUT 0 +#define OUTPUT 1 +#define OUTLEVEL_LOW 0 +#define OUTLEVEL_HIGH 1 +#define PULLLOW 1 +#define PULLHIGH 0 + +/* + *sendbuf data struct + *---------------------------------------------------- + *|start flag| cmd | data | addr |end flag | + *---------------------------------------------------- + *| 2 byte | 1byte | 1byte | 2 byte| 2 byte | + *---------------------------------------------------- + */ + +#define SENDBUFLEN 8 +static u8 sendbuf[SENDBUFLEN];/* send data */ +static u8 rbuf[SENDBUFLEN];/*save get data */ +/**\brief aml_init_send_buf:init spi send buf + * \param cmd: ci cmd + * \param data: write value + * \param addr: read or write addr + * \return + * - read value:ok + * - -EINVAL : error + */ +static int aml_init_send_buf(u8 cmd, u8 data, u16 addr) +{ + /* start flag */ + sendbuf[0] = DATASTART; + sendbuf[1] = DATASTART; + /* cmd */ + sendbuf[2] = cmd; + /* data */ + sendbuf[3] = data; + /* addr senf low 8 bit first,and then send hi 8bit */ + sendbuf[4] = addr & 0x00ff; + sendbuf[5] = (addr>>8) & 0xff; + /* end flag */ + sendbuf[6] = DATAEND; + sendbuf[7] = DATAEND; + return 0; +} +/**\brief aml_ci_spi_reciver + * \param[out] None + * \param[in] value,get from spi + * \return + * - 0:reciver end,-1:reciver + * - + */ +/* + *data strouct + *---------------------------------------------------- + *|start flag| cmd | data | addr |end flag | + *---------------------------------------------------- + *| 2 byte | 1byte | 1byte | 2 byte| 2 byte | + *---------------------------------------------------- + */ +int aml_ci_spi_paser_bit(uint8_t value) +{ + /* read spi data from slave */ + if (G_rec_flag == AM_SPI_STEP_INIT) { + /* start type first */ + if (value == DATASTART) { + rbuf[0] = value; + G_rec_flag = AM_SPI_STEP_START1; + } + } else if (G_rec_flag == AM_SPI_STEP_START1) { + /* start2 type seccond */ + if (value == DATASTART) { + rbuf[1] = value; + G_rec_flag = AM_SPI_STEP_START2; + } + } else if (G_rec_flag == AM_SPI_STEP_START2) { + /* cmd type */ + /* pr_dbg("spi value=%d\r\n",value); */ + rbuf[2] = value; + G_rec_flag = AM_SPI_STEP_CMD; + } else if (G_rec_flag == AM_SPI_STEP_CMD) { + /* data */ + rbuf[3] = value; + G_rec_flag = AM_SPI_STEP_DATA; + } else if (G_rec_flag == AM_SPI_STEP_DATA) { + /* ADDR1 */ + rbuf[4] = value; + G_rec_flag = AM_SPI_STEP_ADDR1; + } else if (G_rec_flag == AM_SPI_STEP_ADDR1) { + /* ADDR2 type */ + rbuf[5] = value; + G_rec_flag = AM_SPI_STEP_ADDR2; + } else if (G_rec_flag == AM_SPI_STEP_ADDR2) { + /* END1 type */ + if (value == DATAEND) { + rbuf[6] = value; + G_rec_flag = AM_SPI_STEP_END1; + } + } else if (G_rec_flag == AM_SPI_STEP_END1) { + /* END2 type */ + if (value == DATAEND) { + rbuf[7] = value; + G_rec_flag = AM_SPI_STEP_END2; + /* pr_dbg("spi read value ok end\r\n"); */ + return 0; + } + } + return -1; +} + +/**\brief aml_spi_io_api:spi read or write api with mcu + * \param spi_dev: aml_spi obj,used this data to get spi obj + * \param val: write value + * \param len: write value len + * \param mode: read or write + * \return + * - read value:ok + * - -EINVAL : error + */ +static int aml_spi_io_api(struct aml_spi *spi_dev, u8 *val, int len, int mode) +{ + u8 rb[32] = {0}; + int ret = 0; + int i = 0; + u8 rd = 0; + + if (spi_dev->spi == NULL) { + pr_error("%s spi is null\r\n", __func__); + return -EINVAL; + } + spin_lock(&spi_dev->spi_lock); + if (spi_dev->cs_hold_delay) + udelay(spi_dev->cs_hold_delay); + dirspi_start(spi_dev->spi); + if (spi_dev->cs_clk_delay) + udelay(spi_dev->cs_clk_delay); + + dirspi_xfer(spi_dev->spi, val, rb, len); + /* wait mcu io */ + udelay(1000); + /* init rec flag */ + G_rec_flag = AM_SPI_STEP_INIT; + memset(rbuf, 0, 8); + for (i = 0; i < 4*len; i++) { + udelay(50); + ret = dirspi_read(spi_dev->spi, &rd, 1); + if (ret != 0) + pr_dbg("spi read value timeout:%x\r\n", rd); + ret = aml_ci_spi_paser_bit(rd); + if (ret == 0) + break; + } + if (ret == 0) { + rd = rbuf[3];/* data */ + } else { + pr_dbg("spi read value error\r\n"); + rd = 0; + } + + if (spi_dev->cs_clk_delay) + udelay(spi_dev->cs_clk_delay); + + /* pr_error("ci spi is stop in %s rd=%d\r\n",__func__,rd);*/ + dirspi_stop(spi_dev->spi); + + spin_unlock(&spi_dev->spi_lock); + + return rd; +} + +/********************************************************/ +/********************************************************/ +/******* gpio api *************/ +/********************************************************/ +/********************************************************/ +/**\brief aml_set_gpio_out:set gio out and set val value + * \param gpio: gpio_desc obj, + * \param val: set val + * \return + * - 0:ok + * - -EINVAL : error + */ +static int aml_set_gpio_out(struct gpio_desc *gpio, int val) +{ + int ret = 0; + + if (val < 0) { + pr_dbg("gpio out val = -1.\n"); + return -1; + } + if (val != 0) + val = 1; + ret = gpiod_direction_output(gpio, val); + pr_dbg("dvb ci gpio out ret %d set val:%d\n", ret, val); + return ret; +} +/**\brief aml_set_gpio_in:set gio in + * \param gpio: gpio_desc obj, + * \return + * - 0:ok + * - -EINVAL : error + */ +static inline int aml_set_gpio_in(struct gpio_desc *gpio) +{ + gpiod_direction_input(gpio); + return 0; +} +/**\brief aml_get_gpio_value:get gio value + * \param gpio: gpio_desc obj, + * \return + * - gpio value:ok + * - -EINVAL : error + */ +static inline int aml_get_gpio_value(struct gpio_desc *gpio) +{ + int ret = 0; + + ret = gpiod_get_value(gpio); + return ret; +} +/**\brief aml_gpio_free:free gio + * \param gpio: gpio_desc obj, + * \return + * - 0:ok + * - -EINVAL : error + */ +static int aml_gpio_free(struct gpio_desc *gpio) +{ + gpiod_put(gpio); + return 0; +} +/**\brief spi_get_gpio_by_name:get gpio desc from dts file + * \param spi_dev: aml_spi obj + * \param gpiod: gpio_desc * obj + * \param str: gpio name at dts file + * \param input_output: gpio input or output type + * \param output_value: gpio out put value + * \return + * - 0:ok + * - -EINVAL : error + */ +static int spi_get_gpio_by_name(struct aml_spi *spi_dev, +struct gpio_desc **gpiod, int *pin_value, +char *str, int input_output, int output_level) +{ + int ret = 0; + struct device_node *child = NULL; + struct platform_device *pdev = spi_dev->pdev; + struct device_node *np = pdev->dev.of_node; + + /*get spi and gpio config from dts*/ + /* get device config for dvbci_io*/ + child = of_get_child_by_name(np, "dvbci_io"); + if (IS_ERR(*gpiod)) { + pr_dbg("dvb ci spi %s request failed\n", str); + return -1; + } + + *pin_value = of_get_named_gpio_flags(child, str, 0, NULL); + *gpiod = gpio_to_desc(*pin_value); + if (IS_ERR(*gpiod)) { + pr_dbg("spi %s request failed\n", str); + return -1; + } + pr_dbg("spi get_gpio %s %p %d\n", str, *gpiod, *pin_value); + gpio_request(*pin_value, AML_MODE_NAME); + + if (input_output == OUTPUT) { + ret = gpiod_direction_output(*gpiod, output_level); + } else if (input_output == INPUT) { + ret = gpiod_direction_input(*gpiod); + /*ret |= gpiod_set_pullup(*gpiod, 1);*/ + } else { + pr_error("spi Request gpio direction invalid\n"); + } + return ret; +} +/********************************************************/ +/********************************************************/ +/******* gpio api end *************/ +/********************************************************/ +/********************************************************/ +/**\brief aml_ci_cis_test_by_spi:test cis + * \param ci_dev: aml_ci obj,used this data to get spi_dev obj + * \param slot: slot index + * \param addr: read addr + * \return + * - test :ok + * - -EINVAL : error + */ +/**\brief aml_ci_full_test_by_spi:ci full test + * \param ci_dev: aml_ci obj,used this data to get spi_dev obj + * \param slot: slot index + * \param addr: read addr + * \return + * - read value:ok + * - -EINVAL : error + */ +static int aml_ci_full_test_by_spi( + struct aml_ci *ci_dev, int slot, int addr) +{ + u8 data = 0; + u16 address = addr; + int value = 0; + struct aml_spi *spi_dev = ci_dev->data; + + aml_init_send_buf(AM_CI_CMD_FULLTEST, data, address); + value = aml_spi_io_api(spi_dev, + sendbuf, SENDBUFLEN, AM_CI_CMD_FULLTEST); + pr_dbg("FULL : TEST END \r\n"); + return value; +} + +/**\brief aml_ci_mem_read_by_spi:io read from cam + * \param ci_dev: aml_ci obj,used this data to get spi_dev obj + * \param slot: slot index + * \param addr: read addr + * \return + * - read value:ok + * - -EINVAL : error + */ +static int aml_ci_mem_read_by_spi( + struct aml_ci *ci_dev, int slot, int addr) +{ + u8 data = 0; + u16 address = addr; + int value = 0; + struct aml_spi *spi_dev = ci_dev->data; + + aml_init_send_buf(AM_CI_CMD_MEMR, data, address); + value = aml_spi_io_api(spi_dev, sendbuf, SENDBUFLEN, AM_CI_CMD_MEMR); + /*pr_dbg("Read : mem[%d] = 0x%x\n", addr, value);*/ + return value; +} +/**\brief aml_ci_mem_write_by_spi:io write to cam by spi api + * \param ci_dev: aml_ci obj,used this data to get spi_dev obj + * \param slot: slot index + * \param addr: write addr + * \param addr: write value + * \return + * - 0:ok + * - -EINVAL : error + */ +static int aml_ci_mem_write_by_spi( + struct aml_ci *ci_dev, int slot, int addr, u8 val) +{ + u8 data = val; + u16 address = addr; + int value = 0; + struct aml_spi *spi_dev = ci_dev->data; + + aml_init_send_buf(AM_CI_CMD_MEMW, data, address); + value = aml_spi_io_api(spi_dev, sendbuf, SENDBUFLEN, AM_CI_CMD_MEMW); + /*pr_dbg("write : mem[%d] = 0x%x\n", addr, data);*/ + return value; +} +/**\brief aml_ci_io_read_by_spi:io read from cam by spi api + * \param ci_dev: aml_ci obj,used this data to get spi_dev obj + * \param slot: slot index + * \param addr: read addr + * \return + * - read value:ok + * - -EINVAL : error + */ +static int aml_ci_io_read_by_spi( + struct aml_ci *ci_dev, int slot, int addr) +{ + u8 data = 0; + u16 address = addr; + int value = 0; + struct aml_spi *spi_dev = ci_dev->data; + + aml_init_send_buf(AM_CI_CMD_IOR, data, address); + value = aml_spi_io_api(spi_dev, sendbuf, SENDBUFLEN, AM_CI_CMD_IOR); + /*pr_dbg("read : io[%d] = 0x%x\n", addr, value);*/ + return value; +} +/**\brief aml_ci_io_write_by_spi:io write to cam + * \param ci_dev: aml_ci obj,used this data to get spi_dev obj + * \param slot: slot index + * \param addr: write addr + * \param addr: write value + * \return + * - 0:ok + * - -EINVAL : error + */ +static int aml_ci_io_write_by_spi( + struct aml_ci *ci_dev, int slot, int addr, u8 val) +{ + u8 data = val; + u16 address = addr; + int value = 0; + struct aml_spi *spi_dev = ci_dev->data; + /*add by chl,need add time delay*/ + mdelay(10); + aml_init_send_buf(AM_CI_CMD_IOW, data, address); + value = aml_spi_io_api(spi_dev, sendbuf, SENDBUFLEN, AM_CI_CMD_IOW); + /*pr_dbg("write : ATTR[%d] = 0x%x\n", addr, data);*/ + return value; +} + + +/**\brief aml_ci_slot_reset:reset slot + * \param ci_dev: aml_ci obj,used this data to get spi_dev obj + * \param slot: slot index + * \return + * - 0:ok + * - -EINVAL : error + */ +static int aml_ci_slot_reset(struct aml_ci *ci_dev, int slot) +{ + struct aml_spi *spi_dev = ci_dev->data; + + pr_dbg("Slot(%d): Slot RESET\n", slot); + aml_pcmcia_reset(&spi_dev->pc); + dvb_ca_en50221_camready_irq(&ci_dev->en50221, 0); + return 0; +} +/**\brief aml_ci_slot_shutdown:show slot + * \param ci_dev: aml_ci obj,used this data to get spi_dev obj + * \param slot: slot index + * \return + * - 0:ok + * - -EINVAL : error + * readme:no use this api + */ +static int aml_ci_slot_shutdown(struct aml_ci *ci_dev, int slot) +{ + pr_dbg("Slot(%d): Slot shutdown\n", slot); + return 0; +} +/**\brief aml_ci_ts_control:control slot ts + * \param ci_dev: aml_ci obj,used this data to get spi_dev obj + * \param slot: slot index + * \return + * - 0:ok + * - -EINVAL : error + * readme:no use this api + */ +static int aml_ci_ts_control(struct aml_ci *ci_dev, int slot) +{ + pr_dbg("Slot(%d): TS control\n", slot); + return 0; +} +/**\brief aml_ci_slot_status:get slot status + * \param ci_dev: aml_ci obj,used this data to get spi_dev obj + * \param slot: slot index + * \param open: no used + * \return + * - cam status + * - -EINVAL : error + */ +static int aml_ci_slot_status(struct aml_ci *ci_dev, int slot, int open) +{ + struct aml_spi *spi_dev = ci_dev->data; + + pr_dbg("Slot(%d): Poll Slot status\n", slot); + + if (spi_dev->pc.slot_state == MODULE_INSERTED) { + pr_dbg("CA Module present and ready\n"); + return DVB_CA_EN50221_POLL_CAM_PRESENT | + DVB_CA_EN50221_POLL_CAM_READY; + } else { + pr_error("CA Module not present or not ready\n"); + } + return -EINVAL; +} + +/**\brief aml_ci_gio_get_irq:get gpio cam irq pin value + * \return + * - irq pin value + * - -EINVAL : error + */ +static int aml_ci_gio_get_irq(void) +{ + int ret = 0; + + ret = aml_get_gpio_value(g_spi_dev->irq_cam_pin); + return ret; +} +/********************************************************/ +/********************************************************/ +/******* for pcmcid api *************/ +/********************************************************/ +/********************************************************/ +/**\brief aml_gio_power:set power gpio hi or low + * \param pc: aml_pcmcia obj,used this priv to get spi_dev obj + * \param enable: power pin hi or low + * \return + * - 0 + * - -EINVAL : error + */ +static int aml_gio_power(struct aml_pcmcia *pc, int enable) +{ + int ret = 0; + struct aml_spi *spi_dev = pc->priv; + + if (spi_dev == NULL) { + pr_dbg("spi dev is null %s : %d\r\n", __func__, enable); + return -1; + } + pr_dbg("%s : %d\r\n", __func__, enable); + if (enable == AML_PWR_OPEN) { + /*hi level ,open power*/ + ret = aml_set_gpio_out(spi_dev->pwr_pin, AML_GPIO_HIGH); + } else { + /*low level ,close power*/ + ret = aml_set_gpio_out(spi_dev->pwr_pin, AML_GPIO_LOW); + } + return ret; +} +/**\brief aml_gio_reset:set reset gpio hi or low + * \param pc: aml_pcmcia obj,used this priv to get spi_dev obj + * \param enable: reset pin hi or low + * \return + * - 0 + * - -EINVAL : error + */ +static int aml_gio_reset(struct aml_pcmcia *pc, int enable) +{ + /*need set hi and sleep set low*/ + int ret = 0; + struct aml_spi *spi_dev = pc->priv; + + pr_dbg("%s : %d\r\n", __func__, enable); + if (enable == AML_L) + ret = aml_set_gpio_out(spi_dev->reset_pin, AML_GPIO_LOW); + else + ret = aml_set_gpio_out(spi_dev->reset_pin, AML_GPIO_HIGH); + return ret; +} + +/**\brief aml_gio_init_irq:set gpio irq + * \param pc: aml_pcmcia obj,used this priv to get spi_dev obj + * \param flag: rising or falling or hi or low + * \return + * - 0 + * - -EINVAL : error + */ +/*need change*/ +static int aml_gio_init_irq(struct aml_pcmcia *pc, int flag) +{ + struct aml_spi *spi_dev = (struct aml_spi *)pc->priv; + +#if 0 + int cd1_pin = desc_to_gpio(spi_dev->cd_pin1); + + int irq = pc->irq-AML_CI_GPIO_IRQ_BASE; + + printk("----cd1_pin=%d irq=%d\r\n", cd1_pin, irq); + aml_set_gpio_in(spi_dev->cd_pin1); + + if (flag == IRQF_TRIGGER_RISING) + gpio_for_irq(cd1_pin, + AML_GPIO_IRQ(irq, FILTER_NUM7, GPIO_IRQ_RISING)); + else if (flag == IRQF_TRIGGER_FALLING) + gpio_for_irq(cd1_pin, + AML_GPIO_IRQ(irq, FILTER_NUM7, GPIO_IRQ_FALLING)); + else if (flag == IRQF_TRIGGER_HIGH) + gpio_for_irq(cd1_pin, + AML_GPIO_IRQ(irq, FILTER_NUM7, GPIO_IRQ_HIGH)); + else if (flag == IRQF_TRIGGER_LOW) + gpio_for_irq(cd1_pin, + AML_GPIO_IRQ(irq, FILTER_NUM7, GPIO_IRQ_LOW)); + else + return -1; +#endif + gpiod_to_irq(spi_dev->cd_pin1); + + return 0; +} +/**\brief aml_gio_get_cd1:get gpio cd1 pin value + * \param pc: aml_pcmcia obj,used this priv to get spi_dev obj + * \return + * - cd1 pin value + * - -EINVAL : error + */ +static int aml_gio_get_cd1(struct aml_pcmcia *pc) +{ + int ret = 0; + struct aml_spi *spi_dev = pc->priv; + + ret = aml_get_gpio_value(spi_dev->cd_pin1); + return ret; +} +/**\brief aml_gio_get_cd2:get gpio cd2 pin value + * \param pc: aml_pcmcia obj,used this priv to get spi_dev obj + * \return + * - cd2 pin value + * - -EINVAL : error + */ +static int aml_gio_get_cd2(struct aml_pcmcia *pc) +{ + int ret = 0; + struct aml_spi *spi_dev = pc->priv; + + ret = aml_get_gpio_value(spi_dev->cd_pin2); + pr_dbg("%s : %d\r\n", __func__, ret); + return ret; +} +/**\brief aml_cam_plugin:notify en50221 cam card in or out + * \param pc: aml_pcmcia obj,used this priv to get spi_dev obj + * \plugin: 0:remove;1:in + * \return + * - 0 + * - -EINVAL : error + */ +static int aml_cam_plugin(struct aml_pcmcia *pc, int plugin) +{ + struct aml_ci *ci = (struct aml_ci *) + ((struct aml_spi *)(pc->priv))->priv; + pr_dbg("%s : %d\r\n", __func__, plugin); + if (plugin) { + dvb_ca_en50221_camchange_irq(&ci->en50221, + 0, DVB_CA_EN50221_CAMCHANGE_INSERTED); + } else { + dvb_ca_en50221_camchange_irq(&ci->en50221, + 0, DVB_CA_EN50221_CAMCHANGE_REMOVED); + } + return 0; +} +/**\brief aml_pcmcia_alloc:alloc nad init pcmcia obj + * \param spi_dev: aml_spi obj, + * \param pcmcia: aml_pcmcia * obj, + * \return + * - 0 + * - -EINVAL : error + */ +static void aml_pcmcia_alloc(struct aml_spi *spi_dev, + struct aml_pcmcia **pcmcia) +{ + pr_dbg("aml_pcmcia_alloc----\n"); + *pcmcia = &spi_dev->pc; + (*pcmcia)->irq = spi_dev->irq; + (*pcmcia)->init_irq = aml_gio_init_irq; + (*pcmcia)->get_cd1 = aml_gio_get_cd1; + (*pcmcia)->get_cd2 = aml_gio_get_cd2; + (*pcmcia)->pwr = aml_gio_power; + (*pcmcia)->rst = aml_gio_reset; + (*pcmcia)->pcmcia_plugin = aml_cam_plugin; + (*pcmcia)->slot_state = MODULE_XTRACTED; + (*pcmcia)->priv = spi_dev; + (*pcmcia)->run_type = 0;/*0:irq;1:poll*/ +} + +/**\brief aml_spi_get_config_from_dts:get spi config and gpio config from dts + * \param spi_dev: aml_spi obj, + * \return + * - 0 + * - -EINVAL : error + */ +static int aml_spi_get_config_from_dts(struct aml_spi *spi_dev) +{ + struct device_node *child = NULL; + struct platform_device *pdev = spi_dev->pdev; + struct device_node *np = pdev->dev.of_node; + unsigned int temp[5], val; + int ret = 0; + + pr_dbg("into get spi dts \r\n"); + + /*get spi and gpio config from dts*/ + /* get device config for dvbci_io*/ + child = of_get_child_by_name(np, "dvbci_io"); + if (child == NULL) { + pr_error("failed to get dvbci_io\n"); + return -1; + } + spi_dev->spi_bdinfo = &aml_ci_spi_bdinfo; + /* get spi config */ + ret = of_property_read_u32_array(child, "spi_bus_num", temp, 1); + if (ret) { + pr_error("failed to get spi_bus_num\n"); + } else { + aml_ci_spi_bdinfo.bus_num = temp[0]; + pr_dbg("bus_num: %d\n", aml_ci_spi_bdinfo.bus_num); + } + ret = of_property_read_u32_array(child, "spi_chip_select", + temp, 1); + if (ret) { + pr_error("failed to get spi_chip_select\n"); + } else { + aml_ci_spi_bdinfo.chip_select = temp[0]; + pr_dbg("chip_select: %d\n", aml_ci_spi_bdinfo.chip_select); + } + ret = of_property_read_u32_array(child, "spi_max_frequency", + temp, 1); + if (ret) { + pr_error("failed to get spi_chip_select\n"); + } else { + aml_ci_spi_bdinfo.max_speed_hz = temp[0]; + pr_dbg("max_speed_hz: %d\n", aml_ci_spi_bdinfo.max_speed_hz); + } + ret = of_property_read_u32_array(child, "spi_mode", temp, 1); + if (ret) { + pr_error("failed to get spi_mode\n"); + } else { + aml_ci_spi_bdinfo.mode = temp[0]; + pr_dbg("mode: %d\n", aml_ci_spi_bdinfo.mode); + } + ret = of_property_read_u32_array(child, "spi_cs_delay", + &temp[0], 2); + if (ret) { + spi_dev->cs_hold_delay = 0; + spi_dev->cs_clk_delay = 0; + } else { + spi_dev->cs_hold_delay = temp[0]; + spi_dev->cs_clk_delay = temp[1]; + } + ret = of_property_read_u32(child, "spi_write_check", &val); + if (ret) + spi_dev->write_check = 0; + else + spi_dev->write_check = (unsigned char)val; + /*get cd1 irq num*/ + ret = of_property_read_u32(child, "irq_cd1", &val); + if (ret) { + spi_dev->irq = 5; + } else { + /*set irq value need add + *AML_CI_GPIO_IRQ_BASE,but + *we need minus + *AML_CI_GPIO_IRQ_BASE + *when gpio request irq + */ + spi_dev->irq = val+AML_CI_GPIO_IRQ_BASE; + } + + spi_dev->irq = irq_of_parse_and_map( + pdev->dev.of_node, 0); + AML_CI_GPIO_IRQ_BASE = spi_dev->irq - val; + pr_dbg("get spi irq : %d 0:%d USEDBASE:%d val:%d\r\n", + spi_dev->irq, INT_GPIO_0, AML_CI_GPIO_IRQ_BASE, val); + /*get reset pwd cd1 cd2 gpio pin*/ + spi_dev->reset_pin = NULL; + ret = spi_get_gpio_by_name(spi_dev, &spi_dev->reset_pin, + &spi_dev->reset_pin_value, "reset_pin", + OUTPUT, OUTLEVEL_HIGH); + if (ret) { + pr_error("dvb ci reset pin request failed\n"); + return -1; + } + spi_dev->cd_pin1 = NULL; + ret = spi_get_gpio_by_name(spi_dev, + &spi_dev->cd_pin1, + &spi_dev->cd_pin1_value, "cd_pin1", + INPUT, OUTLEVEL_HIGH); + if (ret) { + pr_error("dvb ci cd_pin1 pin request failed\n"); + return -1; + } + spi_dev->cd_pin2 = spi_dev->cd_pin1; + spi_dev->cd_pin2_value = spi_dev->cd_pin1_value; + /*set irq*/ + spi_dev->irq = gpiod_to_irq(spi_dev->cd_pin1); + spi_dev->pwr_pin = NULL; + pr_dbg("spi_dev->cd_pin1_value==%d irq=%d\r\n", + spi_dev->cd_pin1_value, spi_dev->irq); + ret = spi_get_gpio_by_name(spi_dev, + &spi_dev->pwr_pin, &spi_dev->pwr_pin_value, + "pwr_pin", OUTPUT, OUTLEVEL_HIGH); + if (ret) { + pr_error("dvb ci pwr_pin pin request failed\n"); + return -1; + } + spi_dev->irq_cam_pin = NULL; + ret = spi_get_gpio_by_name(spi_dev, + &spi_dev->irq_cam_pin, &spi_dev->irq_cam_pin_value, + "irq_cam_pin", INPUT, OUTLEVEL_HIGH); + if (ret) { + pr_error("dvbci irq_cam_pin pin request failed\n"); + return -1; + } + + return 0; +} +/**\brief aml_ci_free_gpio:free ci gpio + * \param spi_dev: aml_spi obj, + * \return + * - 0 + * - -EINVAL : error + */ +static void aml_ci_free_gpio(struct aml_spi *spi_dev) +{ + if (spi_dev == NULL) { + pr_error("spi_dev is NULL,no need free gpio res\r\n"); + return; + } + + if (spi_dev->pwr_pin) { + aml_gpio_free(spi_dev->pwr_pin); + spi_dev->pwr_pin = NULL; + } + if (spi_dev->cd_pin1) { + aml_gpio_free(spi_dev->cd_pin1); + spi_dev->cd_pin1 = NULL; + spi_dev->cd_pin2 = NULL; + } + if (spi_dev->reset_pin) { + aml_gpio_free(spi_dev->reset_pin); + spi_dev->reset_pin = NULL; + } + if (spi_dev->irq_cam_pin) { + aml_gpio_free(spi_dev->irq_cam_pin); + spi_dev->irq_cam_pin = NULL; + } +} + + +/**\brief ci_spi_dev_remove:spi probe api + * \param spi: spi obj, + * \return + * - 0 + * - -EINVAL : error + */ +static int ci_spi_dev_probe(struct spi_device *spi) +{ + int ret; + + pr_dbg("spi Dev probe--\n"); + if (g_spi_dev) + g_spi_dev->spi = spi; + else + pr_dbg("spi Dev probe-error-\n"); + spi->bits_per_word = 8; + ret = spi_setup(spi); + if (ret) + pr_dbg("spi setup failed\n"); + return ret; +} +/**\brief ci_spi_dev_remove:spi remove api + * \param spi: spi obj, + * \return + * - 0 + * - -EINVAL : error + */ +static int ci_spi_dev_remove(struct spi_device *spi) +{ + pr_dbg("spi Dev remove--\n"); + if (g_spi_dev) + g_spi_dev->spi = NULL; + + return 0; +} + +static struct spi_driver ci_spi_dev_driver = { + .probe = ci_spi_dev_probe, + .remove = ci_spi_dev_remove, + .driver = { + .name = "ci_spi_dev",/*set same with board info modalias*/ + .owner = THIS_MODULE, + }, +}; +/**\brief aml_spi_init:spi_dev init + * \param ci_dev: aml_ci obj, + * \param pdev: platform_device obj,used to get dts info + * \return + * - 0 + * - -EINVAL : error + */ +int aml_spi_init(struct platform_device *pdev, struct aml_ci *ci_dev) +{ + struct aml_spi *spi_dev = NULL; + struct aml_pcmcia *pc; + int result; + + spi_dev = kmalloc(sizeof(struct aml_spi), GFP_KERNEL); + if (!spi_dev) { + pr_error("Out of memory!, exiting ..\n"); + result = -ENOMEM; + goto err; + } + g_spi_dev = spi_dev; + spi_dev->pdev = pdev; + spi_dev->priv = ci_dev; + /*get config from dts*/ + aml_spi_get_config_from_dts(spi_dev); + /*regist api dev*/ + spi_register_board_info(spi_dev->spi_bdinfo, 1); + result = spi_register_driver(&ci_spi_dev_driver); + if (result) { + pr_error("register amlspi_dev spi driver failed\n"); + goto fail1; + } + aml_pcmcia_alloc(spi_dev, &pc); + result = aml_pcmcia_init(pc); + if (result < 0) + pr_error("aml_pcmcia_init failed\n"); + + /*init ci_dev used api.*/ + ci_dev->ci_mem_read = aml_ci_mem_read_by_spi; + ci_dev->ci_mem_write = aml_ci_mem_write_by_spi; + ci_dev->ci_io_read = aml_ci_io_read_by_spi; + ci_dev->ci_io_write = aml_ci_io_write_by_spi; + ci_dev->ci_slot_reset = aml_ci_slot_reset; + ci_dev->ci_slot_shutdown = aml_ci_slot_shutdown; + ci_dev->ci_slot_ts_enable = aml_ci_ts_control; + ci_dev->ci_poll_slot_status = aml_ci_slot_status; + ci_dev->data = spi_dev; + /*init spi_lock*/ + spin_lock_init(&(spi_dev->spi_lock)); + return 0; + spi_unregister_driver(&ci_spi_dev_driver); +fail1: + kfree(spi_dev); + spi_dev = NULL; +err: + return -1; +} +EXPORT_SYMBOL(aml_spi_init); +/**\brief aml_spi_exit:spi exit + * \return + * - 0 + * - -EINVAL : error + */ +int aml_spi_exit(void) +{ + /*exit pc card*/ + aml_pcmcia_exit(&g_spi_dev->pc); + /*un regist spi driver*/ + spi_unregister_driver(&ci_spi_dev_driver); + /*free gpio*/ + aml_ci_free_gpio(g_spi_dev); + /*free spi dev*/ + kfree(g_spi_dev); + g_spi_dev = NULL; + + return 0; +} +EXPORT_SYMBOL(aml_spi_exit); + +/********************************************************/ +/********************************************************/ +/******* for spi test api *************/ +/********************************************************/ +/********************************************************/ + +/*cam difines*/ +#define DA 0x80 +#define FR 0x40 +#define WE 0x02 +#define RE 0x01 + +#define RS 0x08 +#define SR 0x04 +#define SW 0x02 +#define HC 0x01 +#define DATA_REG 0 +#define COM_STA_REG 1 +#define SIZE_REG_L 2 +#define SIZE_REG_M 3 +static void aml_spi_ca_full_test(struct aml_ci *ci_dev) +{ + unsigned int BUF_SIZE = 0; + unsigned int i = 0; + unsigned char cc = 0; + unsigned char reg; + unsigned int bsize = 0; + int cnt = 0; + unsigned char buf[10]; + int count = 1000; + + mdelay(1000); + pr_dbg("READ CIS START\r\n"); + for (i = 0; i < 267; i++) { + mdelay(100); + cc = aml_ci_mem_read_by_spi(ci_dev, 0, i); + pr_dbg("0x%x ", cc); + if ((i + 1) % 16 == 0) + pr_dbg(" \r\n"); + } + pr_dbg("READ CIS OVER\r\n"); + mdelay(1000); + pr_dbg("SW rst CAM...\r\n"); + aml_ci_io_write_by_spi(ci_dev, 0, COM_STA_REG, RS); + pr_dbg("SW rst over.\r\n"); + pr_dbg("-----------------------------------\r\n"); + pr_dbg("TO delay 2000ms\r\n"); + mdelay(2000); + pr_dbg("\r\n"); + pr_dbg("--------------clear rs--!!!-YOU MUST CLEAR RS BIT--no sleep--------\r\n"); + aml_ci_io_write_by_spi(ci_dev, 0, COM_STA_REG, 0); + pr_dbg("--------------sleep---------------------\r\n"); + mdelay(2000); + pr_dbg("TO check sw-rst is OK\r\n"); + pr_dbg("start read fr \r\n"); + if (1) { + unsigned char reg; + unsigned char reg1; + int count1 = 4000; + + while (1) { + mdelay(20); + count1--; + reg1 = aml_ci_io_read_by_spi( + ci_dev, 0, COM_STA_REG); + if (FR != (FR & reg1)) { + continue; + } else { + pr_dbg("CAM Reset Ok\r\n"); + break; + } + } + reg = aml_ci_io_read_by_spi(ci_dev, 0, COM_STA_REG); + pr_dbg("STA_REG = 0x%2.2x\r\n", reg); + if (FR & reg) { + pr_dbg("SW-RST is OK!\r\n"); + } else { + pr_dbg("SW-RST is ERR!\r\n"); + goto end; + } + } +end: + pr_dbg("TO check sw-rst over.\r\n"); + pr_dbg("\r\n"); + pr_dbg("-----------------------------------\r\n"); + pr_dbg("TO buffer size negotiation protocol...\r\n"); + pr_dbg("Get which buf size CAM can support\r\n"); + aml_ci_io_write_by_spi(ci_dev, 0, COM_STA_REG, SR); + mdelay(1000); + while (1) { + + reg = aml_ci_io_read_by_spi(ci_dev, 0, COM_STA_REG); + if ((reg & DA) == DA) { + pr_dbg("Buffer negotiate size date avalible.\r\n"); + break; + } + { + /*pr_dbg("Buffer negotiate + *size date NOT avalible\r\n"); + */ + continue; + } + mdelay(100); + } + cnt = (aml_ci_io_read_by_spi(ci_dev, 0, SIZE_REG_L)) + + ((aml_ci_io_read_by_spi(ci_dev, 0, SIZE_REG_M)) * 256); + pr_dbg("Moudle have <%d> Bytes send to host.\r\n", cnt); + if (cnt != 2) { + pr_dbg("The Bytes will be tx is ERR!\r\n"); + return; + } + for (i = 0; i < cnt; i++) + buf[i] = aml_ci_io_read_by_spi(ci_dev, 0, DATA_REG); + + reg = aml_ci_io_read_by_spi(ci_dev, 0, COM_STA_REG); + if (RE == (RE & reg)) { + pr_dbg("(1)Read CAM buf size ERR!\r\n"); + return; + } + aml_ci_io_write_by_spi(ci_dev, 0, (COM_STA_REG), 0); + + mdelay(1000); + + while (count--) { + reg = aml_ci_io_read_by_spi(ci_dev, 0, COM_STA_REG); + if (FR != (FR & reg)) { + pr_dbg("CAM is busy 2, waiting...\r\n"); + continue; + } else { + pr_dbg("CAM is OK 2.\r\n"); + break; + } + } + reg = aml_ci_io_read_by_spi(ci_dev, 0, COM_STA_REG); + if (FR != (FR & reg)) { + pr_dbg("(2)Read CAM buf size ERR!-\r\n"); + return; + } + bsize = (buf[0] * 256) + buf[1]; + + pr_dbg("CAM can support buf size is: <%d>B\r\n", bsize); + + pr_dbg("Tell CAM which size buf is be used\r\n"); + reg = aml_ci_io_read_by_spi(ci_dev, 0, COM_STA_REG); + if (FR != (FR & reg)) + pr_dbg("CAM is busy, waiting free\r\n"); + while (1) { + reg = aml_ci_io_read_by_spi(ci_dev, 0, COM_STA_REG); + if (FR != (FR & reg)) { + pr_dbg("CAM is busy 3, waiting\r\n"); + continue; + } else { + pr_dbg("CAM is OK 3\r\n"); + break; + } + } + + bsize = bsize - 0; + BUF_SIZE = bsize; + pr_dbg("We will use this buf size: <%d>B\r\n", bsize); + aml_ci_io_write_by_spi(ci_dev, 0, COM_STA_REG, SW); + reg = aml_ci_io_read_by_spi(ci_dev, 0, COM_STA_REG); + if (FR != (FR & reg)) + pr_dbg("CAM is busy, waiting\r\n"); + + while (1) { + reg = aml_ci_io_read_by_spi(ci_dev, 0, COM_STA_REG); + if (FR != (FR & reg)) { + pr_dbg("CAM is busy 4, waiting\r\n"); + continue; + } else { + pr_dbg("CAM is OK 4\r\n"); + break; + } + } + /*SHOULD CHECK DA!!!!!*/ + /*PLS ADD THIS CHECK CODE:*/ + pr_dbg("PRIOR to check CAM'S DA\r\n"); + reg = aml_ci_io_read_by_spi(ci_dev, 0, COM_STA_REG); + if ((reg & DA) == DA) { + pr_dbg("CAM have data send to HOST\r\n"); + return; + } + + + buf[0] = (unsigned char)((bsize >> 8) & 0xff); + buf[1] = (unsigned char)(bsize & 0xff); + + while (1) { + mdelay(10); + aml_ci_io_write_by_spi(ci_dev, + 0, COM_STA_REG, HC | SW); + mdelay(100); + reg = aml_ci_io_read_by_spi(ci_dev, + 0, COM_STA_REG); + if (FR != (FR & reg)) { + pr_dbg("CAM is busy 5, waiting\r\n"); + aml_ci_io_write_by_spi(ci_dev, + 0, COM_STA_REG, SW); + continue; + } else { + pr_dbg("CAM is OK 5\r\n"); + break; + } + } + pr_dbg("<2> Bytes send to CAM\r\n"); + aml_ci_io_write_by_spi(ci_dev, 0, SIZE_REG_M, 0); + aml_ci_io_write_by_spi(ci_dev, 0, SIZE_REG_L, 2); + for (i = 0; i < 2; i++) + aml_ci_io_write_by_spi(ci_dev, 0, DATA_REG, buf[i]); + + reg = aml_ci_io_read_by_spi(ci_dev, 0, COM_STA_REG); + if (WE == (WE & reg)) { + pr_dbg("Write CAM ERR!\r\n"); + return; + } + { + aml_ci_io_write_by_spi(ci_dev, 0, COM_STA_REG, SW); + mdelay(100); + aml_ci_io_write_by_spi(ci_dev, 0, COM_STA_REG, 0); + pr_dbg("Buffer size negotiation over!\r\n"); + pr_dbg("NOW, HOST can communicates with CAM\r\n"); + pr_dbg("NOW, TEST END\r\n"); + } +} + +/** + * Read a tuple from attribute memory. + * + * @param ca CA instance. + * @param slot Slot id. + * @param address Address to read from. Updated. + * @param tupleType Tuple id byte. Updated. + * @param tupleLength Tuple length. Updated. + * @param tuple Dest buffer for tuple (must be 256 bytes). Updated. + * + * @return 0 on success, nonzero on error. + */ +static int dvb_ca_en50221_read_tuple( +int *address, int *tupleType, int *tupleLength, u8 *tuple) +{ + int i; + int _tupleType; + int _tupleLength; + int _address = *address; + + /* grab the next tuple length and type */ + _tupleType = aml_ci_mem_read_by_spi((struct aml_ci *) + g_spi_dev->priv, 0, _address); + if (_tupleType < 0) + return _tupleType; + if (_tupleType == 0xff) { + pr_dbg("END OF CHAIN TUPLE type:0x%x\n", _tupleType); + *address += 2; + *tupleType = _tupleType; + *tupleLength = 0; + return 0; + } + _tupleLength = aml_ci_mem_read_by_spi((struct aml_ci *) + g_spi_dev->priv, 0, _address + 2); + if (_tupleLength < 0) + return _tupleLength; + _address += 4; + + pr_dbg("TUPLE type:0x%x length:%i\n", _tupleType, _tupleLength); + + /* read in the whole tuple */ + for (i = 0; i < _tupleLength; i++) { + tuple[i] = aml_ci_mem_read_by_spi((struct aml_ci *) + g_spi_dev->priv, 0, _address + (i * 2)); + pr_dbg(" 0x%02x: 0x%02x %c\n", + i, tuple[i] & 0xff, + ((tuple[i] > 31) && (tuple[i] < 127)) ? tuple[i] : '.'); + } + _address += (_tupleLength * 2); + + /* success */ + *tupleType = _tupleType; + *tupleLength = _tupleLength; + *address = _address; + return 0; +} +static char *findstr(char *haystack, int hlen, char *needle, int nlen) +{ + int i; + + if (hlen < nlen) + return NULL; + + for (i = 0; i <= hlen - nlen; i++) { + if (!strncmp(haystack + i, needle, nlen)) + return haystack + i; + } + + return NULL; +} + +/** + * Parse attribute memory of a CAM module, + * extracting Config register, and checking + * it is a DVB CAM module. + * + * @param ca CA instance. + * @param slot Slot id. + * + * @return 0 on success, <0 on failure. + */ +static int dvb_ca_en50221_parse_attributes(void) +{ + int address = 0; + int tupleLength; + int tupleType; + u8 tuple[257]; + char *dvb_str; + int rasz; + int status; + int got_cftableentry = 0; + int end_chain = 0; + int i; + u16 manfid = 0; + u16 devid = 0; + int config_base = 0; + int config_option; + + /* CISTPL_DEVICE_0A */ + status = dvb_ca_en50221_read_tuple(&address, + &tupleType, &tupleLength, tuple); + if (status < 0) { + pr_error("read status error\r\n"); + return status; + } + if (tupleType != 0x1D) { + pr_error("read tupleType error [0x%x]\r\n", tupleType); + return -EINVAL; + } + + + + /* CISTPL_DEVICE_0C */ + status = dvb_ca_en50221_read_tuple(&address, + &tupleType, &tupleLength, tuple); + if (status < 0) { + pr_error("read read cis error\r\n"); + return status; + } + if (tupleType != 0x1C) { + pr_error("read read cis type error\r\n"); + return -EINVAL; + } + + + + /* CISTPL_VERS_1 */ + status = dvb_ca_en50221_read_tuple(&address, + &tupleType, &tupleLength, tuple); + if (status < 0) { + pr_error("read read cis version error\r\n"); + return status; + } + if (tupleType != 0x15) { + pr_error("read read cis version type error\r\n"); + return -EINVAL; + } + + + + /* CISTPL_MANFID */ + status = dvb_ca_en50221_read_tuple(&address, &tupleType, + &tupleLength, tuple); + if (status < 0) { + pr_error("read read cis manfid error\r\n"); + return status; + } + if (tupleType != 0x20) { + pr_error("read read cis manfid type error\r\n"); + return -EINVAL; + } + if (tupleLength != 4) { + pr_error("read read cis manfid len error\r\n"); + return -EINVAL; + } + manfid = (tuple[1] << 8) | tuple[0]; + devid = (tuple[3] << 8) | tuple[2]; + + + + /* CISTPL_CONFIG */ + status = dvb_ca_en50221_read_tuple(&address, &tupleType, + &tupleLength, tuple); + if (status < 0) { + pr_error("read read cis config error\r\n"); + return status; + } + if (tupleType != 0x1A) { + pr_error("read read cis config type error\r\n"); + return -EINVAL; + } + if (tupleLength < 3) { + pr_error("read read cis config len error\r\n"); + return -EINVAL; + } + + /* extract the configbase */ + rasz = tuple[0] & 3; + if (tupleLength < (3 + rasz + 14)) { + pr_error("read extract the configbase error\r\n"); + return -EINVAL; + } + + for (i = 0; i < rasz + 1; i++) + config_base |= (tuple[2 + i] << (8 * i)); + + + /* check it contains the correct DVB string */ + dvb_str = findstr((char *)tuple, tupleLength, "DVB_CI_V", 8); + if (dvb_str == NULL) { + pr_error("find dvb str DVB_CI_V error\r\n"); + return -EINVAL; + } + if (tupleLength < ((dvb_str - (char *) tuple) + 12)) { + pr_error("find dvb str DVB_CI_V len error\r\n"); + return -EINVAL; + } + + /* is it a version we support? */ + if (strncmp(dvb_str + 8, "1.00", 4)) { + pr_error(" Unsupported DVB CAM module version %c%c%c%c\n", + dvb_str[8], dvb_str[9], dvb_str[10], dvb_str[11]); + return -EINVAL; + } + +/* process the CFTABLE_ENTRY tuples, and any after those */ + while ((!end_chain) && (address < 0x1000)) { + status = dvb_ca_en50221_read_tuple(&address, &tupleType, + &tupleLength, tuple); + if (status < 0) { + pr_error("process the CFTABLE_ENTRY tuples error\r\n"); + return status; + } + + switch (tupleType) { + case 0x1B: /* CISTPL_CFTABLE_ENTRY */ + if (tupleLength < (2 + 11 + 17)) + break; + + /* if we've already parsed one, just use it */ + if (got_cftableentry) + break; + + /* get the config option */ + config_option = tuple[0] & 0x3f; + + /* OK, check it contains the correct strings */ + if ((findstr((char *)tuple, + tupleLength, "DVB_HOST", 8) == NULL) || + (findstr((char *)tuple, + tupleLength, "DVB_CI_MODULE", 13) == NULL)) + break; + + + got_cftableentry = 1; + break; + + case 0x14: /* CISTPL_NO_LINK*/ + break; + + case 0xFF: /* CISTPL_END */ + end_chain = 1; + break; + + default: + /* Unknown tuple type - just skip + *this tuple and move to the next one + */ + pr_error("Skipping unknown tupletype:0x%x L:0x%x\n", + tupleType, tupleLength); + break; + } + } + + if ((address > 0x1000) || (!got_cftableentry)) { + pr_error("got_cftableentry :%d\r\n", got_cftableentry); + return -EINVAL; + } + + pr_error("----------ci cis ok-----\r\n"); + return 0; +} + +static ssize_t aml_spi_ci_reset_help(struct class *class, +struct class_attribute *attr, char *buf) +{ + int ret; + + ret = sprintf(buf, "echo 1 > %s\n\t", attr->attr.name); + return ret; +} + +static ssize_t aml_spi_ci_reset(struct class *class, +struct class_attribute *attr, const char *buf, size_t size) +{ + int ret; + struct aml_ci *ci = (struct aml_ci *)g_spi_dev->priv; + + ret = aml_ci_slot_reset(ci, 0); + return size; +} + +static ssize_t aml_spi_ci_pwr_help(struct class *class, +struct class_attribute *attr, char *buf) +{ + int ret; + + ret = sprintf(buf, "echo 1|0> %s\n\t", attr->attr.name); + return ret; +} + +static ssize_t aml_spi_ci_pwr(struct class *class, +struct class_attribute *attr, const char *buf, size_t size) +{ + int ret = 0; + int enable = 0; + long value; + + if (kstrtol(buf, 0, &value) == 0) + enable = (int)value; + ret = aml_gio_power(&g_spi_dev->pc, enable); + return size; +} +static ssize_t aml_spi_ci_state_show(struct class *class, +struct class_attribute *attr, char *buf) +{ + int ret; + struct aml_ci *ci = (struct aml_ci *)g_spi_dev->priv; + + ret = aml_ci_slot_status(ci, 0, 0); + ret = sprintf(buf, "%s: %d;\n\t", attr->attr.name, ret); + return ret; +} + +static ssize_t aml_spi_ci_irq_show(struct class *class, +struct class_attribute *attr, char *buf) +{ + int ret; + + ret = aml_ci_gio_get_irq(); + ret = sprintf(buf, "%s irq: %d\n\t", attr->attr.name, ret); + return ret; +} + +static ssize_t aml_spi_io_test_help(struct class *class, +struct class_attribute *attr, char *buf) +{ + int ret; + + ret = sprintf(buf, "echo (r|w|f|c)(i|a) addr data > %s\n", + attr->attr.name); + return ret; +} + +static ssize_t aml_spi_io_test(struct class *class, +struct class_attribute *attr, const char *buf, size_t size) +{ + int n = 0; + char *buf_orig, *ps, *token; + char *parm[3]; + unsigned int addr = 0, val = 0, retval = 0; + long value = 0; + struct aml_ci *ci = (struct aml_ci *)g_spi_dev->priv; + + buf_orig = kstrdup(buf, GFP_KERNEL); + ps = buf_orig; + while (1) { + /*need set '\n' to ' \n'*/ + token = strsep(&ps, "\n"); + if (token == NULL) + break; + if (*token == '\0') + continue; + parm[n++] = token; + } + + if ((n > 0) && (strlen(parm[0]) != 2)) { + pr_err("invalid command\n"); + kfree(buf_orig); + return size; + } + + if ((parm[0][0] == 'r')) { + if (n != 2) { + pr_err("read: invalid parameter\n"); + kfree(buf_orig); + return size; + } + if (kstrtol(parm[1], 0, &value) == 0) + addr = (int)value; + pr_err("%s 0x%x\n", parm[0], addr); + /* switch ((char)parm[0][1]) { + * case 'i': + * retval = aml_ci_io_read_by_spi(ci, 0, addr); + * break; + * case 'a': + * retval = aml_ci_mem_read_by_spi(ci, 0, addr); + * break; + * default: + * break; + * } + */ + pr_dbg("%s: 0x%x --> 0x%x\n", parm[0], addr, retval); + } else if ((parm[0][0] == 'w')) { + if (n != 3) { + pr_err("write: invalid parameter\n"); + kfree(buf_orig); + return size; + } + if (kstrtol(parm[1], 0, &value) == 0) + addr = (int)value; + if (kstrtol(parm[2], 0, &value) == 0) + val = (int)value; + + pr_err("%s 0x%x 0x%x", parm[0], addr, val); + /*switch ((char)parm[0][1]) { + * case 'i': +retval = aml_ci_io_write_by_spi(ci, 0, addr, val); + * break; + * case 'a': +retval = aml_ci_mem_write_by_spi(ci, 0, addr, val); + * break; + * default: + * break; + *} + */ + pr_dbg("%s: 0x%x <-- 0x%x\n", parm[0], addr, retval); + } else if ((parm[0][0] == 'f')) { + pr_dbg("full test----\r\n"); + aml_spi_ca_full_test(ci); + } else if ((parm[0][0] == 'c')) { + pr_dbg("cis test----\r\n"); + aml_ci_full_test_by_spi(ci, 0, addr); + } else if ((parm[0][0] == 'p')) { + pr_dbg("cis dvb_ca_en50221_parse_attributes----\r\n"); + dvb_ca_en50221_parse_attributes(); + } + + kfree(buf_orig); + return size; +} + +static struct class_attribute aml_spi_class_attrs[] = { + __ATTR(reset, 0644, + aml_spi_ci_reset_help, aml_spi_ci_reset), + __ATTR(pwr, 0644, + aml_spi_ci_pwr_help, aml_spi_ci_pwr), + __ATTR(irq, 0644, + aml_spi_ci_irq_show, NULL), + __ATTR(status, 0644, + aml_spi_ci_state_show, NULL), + __ATTR(iotest, 0644, + aml_spi_io_test_help, aml_spi_io_test), + __ATTR_NULL +}; + +static struct class aml_spi_class = { + .name = "aml_dvb_spi_test", + .class_attrs = aml_spi_class_attrs, +}; + +static int __init aml_spi_mod_init(void) +{ + pr_dbg("Amlogic DVB SPI Init\n"); + class_register(&aml_spi_class); +return 0; +} + +static void __exit aml_spi_mod_exit(void) +{ + pr_dbg("Amlogic DVB SPI Exit\n"); + class_unregister(&aml_spi_class); +} + +module_init(aml_spi_mod_init); +module_exit(aml_spi_mod_exit); + +MODULE_LICENSE("GPL"); diff --git a/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/aml_spi.h b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/aml_spi.h new file mode 100644 index 000000000000..2795dc9dae5d --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/hw_demux/dvb_ci/aml_spi.h @@ -0,0 +1,81 @@ +#ifndef __AML_SPI_H_ +#define __AML_SPI_H_ + +#include +#include +#include +#include "aml_pcmcia.h" +#include "aml_ci.h" + +/* + *aml spi dev + */ +struct aml_spi { + spinlock_t spi_lock; + + /* add SPI DEV */ + struct spi_board_info *spi_bdinfo; + struct spi_device *spi; + struct platform_device *pdev; + struct device *dev; + + /* spi otherconfig */ + int cs_hold_delay; + int cs_clk_delay; + int write_check; + + /* add gpio pin */ + struct gpio_desc *reset_pin; + int reset_pin_value; + struct gpio_desc *cd_pin1; + int cd_pin1_value; + struct gpio_desc *cd_pin2; + int cd_pin2_value; + struct gpio_desc *pwr_pin; + int pwr_pin_value; + + /* cam and mcu irq */ + struct gpio_desc *irq_cam_pin; + int irq_cam_pin_value; + int irq; + struct aml_pcmcia pc; + void *priv; +}; +enum aml_gpio_level_e { + AML_GPIO_LOW = 0, + AML_GPIO_HIGH +}; + +/* used to mcu */ +#define DATASTART 0xef +#define DATAEND 0xfe +enum AM_CI_CMD { + AM_CI_CMD_IOR = 0, + AM_CI_CMD_IOW, + AM_CI_CMD_MEMR, + AM_CI_CMD_MEMW, + AM_CI_CMD_FULLTEST, + AM_CI_CMD_CISTEST +}; +enum AM_SPI_RECIVERSTEP { + AM_SPI_STEP_INIT = 0, + AM_SPI_STEP_START1, + AM_SPI_STEP_START2, + AM_SPI_STEP_CMD, + AM_SPI_STEP_DATA, + AM_SPI_STEP_ADDR1, + AM_SPI_STEP_ADDR2, + AM_SPI_STEP_END1, + AM_SPI_STEP_END2 +}; +extern int dirspi_xfer(struct spi_device *spi, u8 *tx_buf, u8 *rx_buf, + int len); +extern int dirspi_write(struct spi_device *spi, u8 *buf, int len); +extern int dirspi_read(struct spi_device *spi, u8 *buf, int len); +extern void dirspi_start(struct spi_device *spi); +extern void dirspi_stop(struct spi_device *spi); +extern void dvb_ca_en50221_camready_irq(struct dvb_ca_en50221 *pubca, int slot); +extern int aml_spi_init(struct platform_device *pdev, struct aml_ci *ci_dev); +extern int aml_spi_exit(void); + +#endif /* __AML_SPI_H_ */ diff --git a/drivers/amlogic/media_modules/stream_input/parser/psparser.c b/drivers/amlogic/media_modules/stream_input/parser/psparser.c new file mode 100644 index 000000000000..c3b63c181a98 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/psparser.c @@ -0,0 +1,1160 @@ +/* + * drivers/amlogic/media/stream_input/parser/psparser.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +/* #include */ +#include +#include "streambuf_reg.h" +#include "streambuf.h" +#include "psparser.h" +#include "../amports/amports_priv.h" + + +#define TIMESTAMP_IONLY 1 +#define SAVE_SCR 0 + +#define MPEG_START_CODE_PATTERN (0x00000100L) +#define MPEG_START_CODE_MASK (0xffffff00L) +#define MAX_MPG_AUDIOPK_SIZE 0x1000 + +#define SUB_INSERT_START_CODE_HIGH 0x414d4c55 +#define SUB_INSERT_START_CODE_LOW 0xaa000000 + +#define PARSER_WRITE (ES_WRITE | ES_PARSER_START) +#define PARSER_VIDEO (ES_TYPE_VIDEO) +#define PARSER_AUDIO (ES_TYPE_AUDIO) +#define PARSER_SUBPIC (ES_TYPE_SUBTITLE) +#define PARSER_PASSTHROUGH (ES_PASSTHROUGH | ES_PARSER_START) +#define PARSER_AUTOSEARCH (ES_SEARCH | ES_PARSER_START) +#define PARSER_DISCARD (ES_DISCARD | ES_PARSER_START) +#define PARSER_BUSY (ES_PARSER_BUSY) + +#define PARSER_PARAMETER_LENGTH_BIT 16 +#define PARSER_PARAMETER_LOOP_BIT 24 + +#define PARSER_POP READ_PARSER_REG(PFIFO_DATA) +#define SET_BLOCK(size) \ +WRITE_PARSER_REG_BITS(PARSER_CONTROL, size, ES_PACK_SIZE_BIT, ES_PACK_SIZE_WID) +#define SET_DISCARD_SIZE(size) WRITE_PARSER_REG(PARSER_PARAMETER, size) + +#define VIDEO_AUTO_FLUSH +#ifdef VIDEO_AUTO_FLUSH +static u32 video_auto_flush_state; +#define VIDEO_AUTO_FLUSH_IDLE 0 +#define VIDEO_AUTO_FLUSH_MONITOR 1 +#define VIDEO_AUTO_FLUSH_TRIGGER 2 +#define VIDEO_AUTO_FLUSH_DONE 3 +#define VIDEO_AUTO_FLUSH_PTS_THRESHOLD 90000 +#define VIDEO_AUTO_FLUSH_BYTE_COUNT 1024 + +static s32 audio_last_pts; +static s32 audio_monitor_pts; +#endif + +enum { + SEARCH_START_CODE = 0, + SEND_VIDEO_SEARCH, + SEND_AUDIO_SEARCH, + SEND_SUBPIC_SEARCH, + DISCARD_SEARCH, + DISCARD_ONLY +#ifdef VIDEO_AUTO_FLUSH + , + SEARCH_START_CODE_VIDEO_FLUSH +#endif +}; + +enum { + AUDIO_FIRST_ACCESS_ARM = 0, + AUDIO_FIRST_ACCESS_POPING, + AUDIO_FIRST_ACCESS_DONE +}; + +static const char psparser_id[] = "psparser-id"; + +static DECLARE_WAIT_QUEUE_HEAD(wq); + +static struct tasklet_struct psparser_tasklet; +static u32 fetch_done; +static u8 audio_id, video_id, sub_id, sub_id_max; +static u32 audio_first_access; +static u32 packet_remaining; +static u32 video_data_parsed; +static u32 audio_data_parsed; +static u32 pts_equ_dts_flag; + +static unsigned int first_apts, first_vpts; +static unsigned int audio_got_first_pts, video_got_first_dts, sub_got_first_pts; +atomic_t sub_block_found = ATOMIC_INIT(0); + +#define DEBUG_VOB_SUB +#ifdef DEBUG_VOB_SUB +static u8 sub_found_num; +static struct subtitle_info *sub_info[MAX_SUB_NUM]; +#endif + +static bool ptsmgr_first_vpts_ready(void) +{ + return (video_got_first_dts != 0) ? true : false; +} + +static bool ptsmgr_first_apts_ready(void) +{ + return (audio_got_first_pts != 0) ? true : false; +} + +static void ptsmgr_vpts_checkin(u32 pts) +{ + if (video_got_first_dts == 0) { + video_got_first_dts = 1; + first_vpts = pts; + } + + pts_checkin_offset(PTS_TYPE_VIDEO, video_data_parsed, pts); +} + +static void ptsmgr_apts_checkin(u32 pts) +{ + if (audio_got_first_pts == 0) { + audio_got_first_pts = 1; + first_apts = pts; + } + /* apts_checkin(pts); */ + pts_checkin_offset(PTS_TYPE_AUDIO, audio_data_parsed, pts); + +#ifdef VIDEO_AUTO_FLUSH + audio_last_pts = pts; + + if ((video_auto_flush_state == VIDEO_AUTO_FLUSH_IDLE) + && ptsmgr_first_vpts_ready()) { + video_auto_flush_state = VIDEO_AUTO_FLUSH_MONITOR; + audio_monitor_pts = pts; + } + + if (video_auto_flush_state == VIDEO_AUTO_FLUSH_MONITOR) { + if ((audio_last_pts - audio_monitor_pts) > + VIDEO_AUTO_FLUSH_PTS_THRESHOLD) + video_auto_flush_state = VIDEO_AUTO_FLUSH_TRIGGER; + } +#endif +} + +static u32 parser_process(s32 type, s32 packet_len) +{ + s16 temp, header_len, misc_flags, i; + u32 pts = 0, dts = 0; + u32 pts_dts_flag = 0; + u16 invalid_pts = 0; + + temp = PARSER_POP; + packet_len--; + + if ((temp >> 6) == 0x02) { + /* mpeg-2 system */ + misc_flags = PARSER_POP; + header_len = PARSER_POP; + packet_len -= 2; + packet_len -= header_len; + + if ((misc_flags >> 6) > 1) { + /* PTS exist */ + pts = ((PARSER_POP >> 1) & 7) << 30; /* bit 32-30 */ + pts |= PARSER_POP << 22; /* bit 29-22 */ + pts |= (PARSER_POP >> 1) << 15; /* bit 21-15 */ + pts |= (PARSER_POP << 7); /* bit 14-07 */ + pts |= (PARSER_POP >> 1); /* bit 06-00 */ + header_len -= 5; + pts_dts_flag |= 2; + } + + if ((misc_flags >> 6) > 2) { + /* DTS exist */ + dts = ((PARSER_POP >> 1) & 7) << 30; /* bit 32-30 */ + dts |= PARSER_POP << 22; /* bit 29-22 */ + dts |= (PARSER_POP >> 1) << 15; /* bit 21-15 */ + dts |= (PARSER_POP << 7); /* bit 14-07 */ + dts |= (PARSER_POP >> 1); /* bit 06-00 */ + header_len -= 5; + pts_dts_flag |= 1; + } + + if (misc_flags & 0x20) { + /* ESCR_flag */ + PARSER_POP; + PARSER_POP; + PARSER_POP; + PARSER_POP; + PARSER_POP; + PARSER_POP; + header_len -= 5; + } + + if (misc_flags & 0x10) { + /* ES_rate_flag */ + PARSER_POP; + PARSER_POP; + PARSER_POP; + header_len -= 3; + } + + if (misc_flags & 0x08) { + /* DSM_trick_mode_flag */ + PARSER_POP; + header_len -= 1; + } + + if (misc_flags & 0x04) { + /* additional_copy_info_flag */ + PARSER_POP; + header_len -= 1; + } + + if (misc_flags & 0x02) { + /* PES_CRC_flag */ + PARSER_POP; + PARSER_POP; + header_len -= 2; + } + + if (misc_flags & 0x01) { + /* PES_extension_flag */ + misc_flags = PARSER_POP; + header_len--; + + if ((misc_flags & 0x80) && (header_len >= 128)) { + /* PES_private_data_flag */ + for (i = 0; i < 128; i++) + PARSER_POP; + + header_len -= 128; + } +#if 0 + if (misc_flags & 0x40) { + /* pack_header_field_flag */ + /* Invalid case */ + } +#endif + if (misc_flags & 0x20) { + /* program_packet_sequence_counter_flag */ + PARSER_POP; + PARSER_POP; + header_len -= 2; + } + + if (misc_flags & 0x10) { + /* PSTD_buffer_flag */ + PARSER_POP; + PARSER_POP; + header_len -= 2; + } + + if (misc_flags & 1) { + /* PES_extension_flag_2 */ + temp = PARSER_POP & 0x7f; + + while (temp) { + PARSER_POP; + temp--; + header_len--; + } + } + + while (header_len) { + PARSER_POP; + header_len--; + } + } + + while (header_len) { + PARSER_POP; + header_len--; + } + + } else { + /* mpeg-1 system */ + while (temp == 0xff) { + temp = PARSER_POP; + packet_len--; + } + + if ((temp >> 6) == 1) { + PARSER_POP; /* STD buffer size */ + temp = PARSER_POP; + packet_len -= 2; + } + + if (((temp >> 4) == 2) || ((temp >> 4) == 3)) { + pts = ((temp >> 1) & 7) << 30; /* bit 32-30 */ + pts |= PARSER_POP << 22; /* bit 29-22 */ + pts |= (PARSER_POP >> 1) << 15; /* bit 21-15 */ + pts |= (PARSER_POP << 7); /* bit 14-07 */ + pts |= (PARSER_POP >> 1); /* bit 06-00 */ + packet_len -= 4; + pts_dts_flag |= 2; + } + + if ((temp >> 4) == 3) { + dts = ((PARSER_POP >> 1) & 7) << 30; /* bit 32-30 */ + dts |= PARSER_POP << 22; /* bit 29-22 */ + dts |= (PARSER_POP >> 1) << 15; /* bit 21-15 */ + dts |= (PARSER_POP << 7); /* bit 14-07 */ + dts |= (PARSER_POP >> 1); /* bit 06-00 */ + packet_len -= 5; + pts_dts_flag |= 1; + } + } + + if ((pts == 0) && (dts == 0xffffffff)) { + invalid_pts = 1; + pr_info("invalid pts\n"); + } + + if (!packet_len) + return SEARCH_START_CODE; + + else if (type == 0) { +#ifdef VIDEO_AUTO_FLUSH + if (video_auto_flush_state == VIDEO_AUTO_FLUSH_MONITOR) + audio_monitor_pts = audio_last_pts; +#endif + + if ((pts_dts_flag) && (!invalid_pts)) { +#if TIMESTAMP_IONLY + if (!ptsmgr_first_vpts_ready()) { + if (pts_dts_flag & 2) + ptsmgr_vpts_checkin(pts); + else + ptsmgr_vpts_checkin(dts); + } else if ((pts_dts_flag & 3) == 3) { + if (pts_equ_dts_flag) { + if (dts == pts) + ptsmgr_vpts_checkin(pts); + } else { + if (dts == pts) + pts_equ_dts_flag = 1; + ptsmgr_vpts_checkin(pts); + } + } +#else + if (!ptsmgr_first_vpts_ready()) { + if (pts_dts_flag & 2) + ptsmgr_vpts_checkin(pts); + else + ptsmgr_vpts_checkin(dts); + } else if (pts_dts_flag & 2) + ptsmgr_vpts_checkin(pts); +#endif + } + + if (ptsmgr_first_vpts_ready() || invalid_pts) { + SET_BLOCK(packet_len); + video_data_parsed += packet_len; + return SEND_VIDEO_SEARCH; + + } else { + SET_DISCARD_SIZE(packet_len); + return DISCARD_SEARCH; + } + + } else if (type == 1) { + /* mpeg audio */ + if (pts_dts_flag & 2) + ptsmgr_apts_checkin(pts); + + if (ptsmgr_first_apts_ready()) { + SET_BLOCK(packet_len); + audio_data_parsed += packet_len; + return SEND_AUDIO_SEARCH; + + } else { + SET_DISCARD_SIZE(packet_len); + return DISCARD_SEARCH; + } + + } else if (type == 2) { + /* Private stream */ + temp = PARSER_POP; /* sub_stream_id */ + packet_len--; + + if (((temp & 0xf8) == 0xa0) && (temp == audio_id)) { + /* DVD_VIDEO Audio LPCM data */ + PARSER_POP; + temp = (PARSER_POP << 8) | PARSER_POP; + if (temp == 0) + temp = 4; + temp--; + packet_len -= 3; + + if (audio_first_access == AUDIO_FIRST_ACCESS_ARM) { + if (temp) { + packet_remaining = packet_len - temp; + SET_DISCARD_SIZE(temp); + audio_first_access = + AUDIO_FIRST_ACCESS_POPING; + return DISCARD_ONLY; + } + + audio_first_access = AUDIO_FIRST_ACCESS_DONE; + + if (packet_len) { + SET_BLOCK(packet_len); + audio_data_parsed += packet_len; + return SEND_AUDIO_SEARCH; + + } else + return SEARCH_START_CODE; + + } else { + PARSER_POP; + PARSER_POP; + PARSER_POP; + packet_len -= 3; + } + + if (pts_dts_flag & 2) + ptsmgr_apts_checkin(pts); + + if (ptsmgr_first_apts_ready()) { + SET_BLOCK(packet_len); + audio_data_parsed += packet_len; + return SEND_AUDIO_SEARCH; + + } else { + SET_DISCARD_SIZE(packet_len); + return DISCARD_SEARCH; + } + + } else if (((temp & 0xf8) == 0x80) && (temp == audio_id)) { + /* Audio AC3 data */ + PARSER_POP; + temp = (PARSER_POP << 8) | PARSER_POP; + packet_len -= 3; + + if (audio_first_access == AUDIO_FIRST_ACCESS_ARM) { + if (pts_dts_flag & 2) + ptsmgr_apts_checkin(pts); + + if ((temp > 2) && (packet_len > (temp - 2))) { + temp -= 2; + packet_remaining = packet_len - temp; + SET_DISCARD_SIZE(temp); + audio_first_access = + AUDIO_FIRST_ACCESS_POPING; + return DISCARD_ONLY; + } + + audio_first_access = AUDIO_FIRST_ACCESS_DONE; + + if (packet_len) { + SET_BLOCK(packet_len); + audio_data_parsed += packet_len; + return SEND_AUDIO_SEARCH; + + } else + return SEARCH_START_CODE; + } + + if (pts_dts_flag & 2) + ptsmgr_apts_checkin(pts); + + if (ptsmgr_first_apts_ready()) { + SET_BLOCK(packet_len); + audio_data_parsed += packet_len; + return SEND_AUDIO_SEARCH; + + } else { + SET_DISCARD_SIZE(packet_len); + return DISCARD_SEARCH; + } + + } else if (((temp & 0xf8) == 0x88) && (temp == audio_id)) { + /* Audio DTS data */ + PARSER_POP; + PARSER_POP; + PARSER_POP; + packet_len -= 3; + + if (audio_first_access == AUDIO_FIRST_ACCESS_ARM) + audio_first_access = AUDIO_FIRST_ACCESS_DONE; + + if (pts_dts_flag & 2) + ptsmgr_apts_checkin(pts); + + if (ptsmgr_first_apts_ready()) { + SET_BLOCK(packet_len); + audio_data_parsed += packet_len; + return SEND_AUDIO_SEARCH; + + } else { + SET_DISCARD_SIZE(packet_len); + return DISCARD_SEARCH; + } + } else if ((temp & 0xe0) == 0x20) { + if (temp > sub_id_max) + sub_id_max = temp; +#ifdef DEBUG_VOB_SUB + for (i = 0; i < sub_found_num; i++) { + if (!sub_info[i]) + break; + if (temp == sub_info[i]->id) + break; + } + if (i == sub_found_num && i < MAX_SUB_NUM) { + if (sub_info[sub_found_num]) { + sub_info[sub_found_num]->id = temp; + sub_found_num++; + pr_info + ("[%s]found new sub_id=0x%x (num %d)\n", + __func__, temp, sub_found_num); + } else { + pr_info + ("[%s]sub info NULL!\n", __func__); + } + } +#endif + + if (temp == sub_id) { + /* DVD sub-picture data */ + if (!packet_len) + return SEARCH_START_CODE; + + else { +#if 0 + if (pts_dts_flag & 2) + ptsmgr_spts_checkin(pts); + + if (ptsmgr_first_spts_ready()) { + SET_BLOCK(packet_len); + return SEND_SUBPIC_SEARCH; + + } else { + SET_DISCARD_SIZE(packet_len); + return DISCARD_SEARCH; + } +#else + if (pts_dts_flag & 2) + sub_got_first_pts = 1; + + if (sub_got_first_pts) { + pr_info + ("sub pts 0x%x, len %d\n", + pts, packet_len); + SET_BLOCK(packet_len); + WRITE_PARSER_REG + (PARSER_PARAMETER, + 16 << + PARSER_PARAMETER_LENGTH_BIT); + WRITE_PARSER_REG + (PARSER_INSERT_DATA, + SUB_INSERT_START_CODE_HIGH); + WRITE_PARSER_REG + (PARSER_INSERT_DATA, + SUB_INSERT_START_CODE_LOW | + get_sub_type()); + WRITE_PARSER_REG + (PARSER_INSERT_DATA, + packet_len); + WRITE_PARSER_REG + (PARSER_INSERT_DATA, pts); + atomic_set(&sub_block_found, 1); + return SEND_SUBPIC_SEARCH; + } + + SET_DISCARD_SIZE(packet_len); + return DISCARD_SEARCH; +#endif + } + } else { + SET_DISCARD_SIZE(packet_len); + return DISCARD_SEARCH; + } + } else { + SET_DISCARD_SIZE(packet_len); + return DISCARD_SEARCH; + } + + if (!packet_len) + return SEARCH_START_CODE; + + else { + SET_BLOCK(packet_len); + audio_data_parsed += packet_len; + return SEND_AUDIO_SEARCH; + } + } + + return SEARCH_START_CODE; +} + +static void on_start_code_found(int start_code) +{ + unsigned short packet_len; + unsigned short temp; + unsigned int next_action; +#if SAVE_SCR + unsigned int scr; +#endif + + if (atomic_read(&sub_block_found)) { + wakeup_sub_poll(); + atomic_set(&sub_block_found, 0); + } + + if (audio_first_access == AUDIO_FIRST_ACCESS_POPING) { + /* + *we are in the procedure of poping data for audio first + * access, continue with last packet + */ + audio_first_access = AUDIO_FIRST_ACCESS_DONE; + + if (packet_remaining) { + next_action = SEND_AUDIO_SEARCH; + SET_BLOCK(packet_remaining); + + } else + next_action = SEARCH_START_CODE; + + } else if (start_code == 0xba) { /* PACK_START_CODE */ + temp = PARSER_POP; + + if ((temp >> 6) == 0x01) { +#if SAVE_SCR + scr = ((temp >> 3) & 0x3) << 30; /* bit 31-30 */ + scr |= (temp & 0x3) << 28; /* bit 29-28 */ + scr |= (PARSER_POP) << 20; /* bit 27-20 */ + temp = PARSER_POP; + scr |= (temp >> 4) << 16; /* bit 19-16 */ + scr |= (temp & 7) << 13; /* bit 15-13 */ + scr |= (PARSER_POP) << 5; /* bit 12-05 */ + scr |= (PARSER_POP) >> 3; /* bit 04-00 */ +#else + PARSER_POP; + PARSER_POP; + PARSER_POP; + PARSER_POP; +#endif + PARSER_POP; + PARSER_POP; + PARSER_POP; + PARSER_POP; + temp = PARSER_POP & 7; + + while (temp) { /* stuff byte */ + PARSER_POP; + temp--; + } + + } else { + /* mpeg-1 Pack Header */ +#if SAVE_SCR + scr = ((temp >> 1) & 0x3) << 30; /* bit 31-30 */ + scr |= (PARSER_POP) << 22; /* bit 29-22 */ + scr |= (PARSER_POP >> 1) << 15; /* bit 21-15 */ + scr |= (PARSER_POP) << 7; /* bit 14-07 */ + scr |= (PARSER_POP >> 1); /* bit 06-00 */ +#else + PARSER_POP; + PARSER_POP; + PARSER_POP; + PARSER_POP; +#endif + } + +#ifdef VIDEO_AUTO_FLUSH + if (video_auto_flush_state == VIDEO_AUTO_FLUSH_TRIGGER) { + next_action = SEARCH_START_CODE_VIDEO_FLUSH; + video_auto_flush_state = VIDEO_AUTO_FLUSH_DONE; + } else +#endif + + next_action = SEARCH_START_CODE; + + } else { + packet_len = (PARSER_POP << 8) | PARSER_POP; + + if (start_code == video_id) + next_action = parser_process(0, packet_len); + + else if (start_code == audio_id) { + /* add mpeg audio packet length check */ + if (packet_len > MAX_MPG_AUDIOPK_SIZE) + next_action = SEARCH_START_CODE; + + else + next_action = parser_process(1, packet_len); + + } else if (start_code == 0xbb) { + SET_DISCARD_SIZE(packet_len); + next_action = DISCARD_SEARCH; + } else if (start_code == 0xbd) + next_action = parser_process(2, packet_len); + + else if (start_code == 0xbf) { + SET_DISCARD_SIZE(packet_len); + next_action = DISCARD_SEARCH; + } else if ((start_code < 0xc0) || (start_code > 0xc8)) + next_action = SEARCH_START_CODE; + + else if (packet_len) { + SET_DISCARD_SIZE(packet_len); + next_action = DISCARD_SEARCH; + + } else + next_action = SEARCH_START_CODE; + } + + switch (next_action) { + case SEARCH_START_CODE: + WRITE_PARSER_REG(PARSER_CONTROL, PARSER_AUTOSEARCH); + break; + + case SEND_VIDEO_SEARCH: + WRITE_PARSER_REG_BITS(PARSER_CONTROL, + PARSER_AUTOSEARCH | PARSER_VIDEO | + PARSER_WRITE, ES_CTRL_BIT, ES_CTRL_WID); + break; + + case SEND_AUDIO_SEARCH: + WRITE_PARSER_REG_BITS(PARSER_CONTROL, + PARSER_AUTOSEARCH | PARSER_AUDIO | + PARSER_WRITE, ES_CTRL_BIT, ES_CTRL_WID); + break; + + case SEND_SUBPIC_SEARCH: + WRITE_PARSER_REG_BITS(PARSER_CONTROL, + PARSER_AUTOSEARCH | PARSER_SUBPIC | + PARSER_WRITE | ES_INSERT_BEFORE_ES_WRITE, + ES_CTRL_BIT, ES_CTRL_WID); + break; + + case DISCARD_SEARCH: + WRITE_PARSER_REG_BITS(PARSER_CONTROL, + PARSER_AUTOSEARCH | PARSER_DISCARD, + ES_CTRL_BIT, ES_CTRL_WID); + break; + + case DISCARD_ONLY: + WRITE_PARSER_REG_BITS(PARSER_CONTROL, + PARSER_DISCARD, ES_CTRL_BIT, ES_CTRL_WID); + break; + +#ifdef VIDEO_AUTO_FLUSH + case SEARCH_START_CODE_VIDEO_FLUSH: + WRITE_PARSER_REG(PARSER_INSERT_DATA, 0xffffffff); + WRITE_PARSER_REG(PARSER_INSERT_DATA, 0xffffffff); + WRITE_PARSER_REG(PARSER_PARAMETER, + ((VIDEO_AUTO_FLUSH_BYTE_COUNT / + 8) << PARSER_PARAMETER_LOOP_BIT) | (8 << + PARSER_PARAMETER_LENGTH_BIT)); + WRITE_PARSER_REG(PARSER_CONTROL, + PARSER_AUTOSEARCH | PARSER_VIDEO | PARSER_WRITE | + ES_INSERT_BEFORE_ES_WRITE); + break; +#endif + } +} + +static void parser_tasklet(ulong data) +{ + s32 sc; + u32 int_status = READ_PARSER_REG(PARSER_INT_STATUS); + + WRITE_PARSER_REG(PARSER_INT_STATUS, int_status); + + if (int_status & PARSER_INTSTAT_FETCH_CMD) { + fetch_done = 1; + + wake_up_interruptible(&wq); + } + + if (int_status & PARSER_INTSTAT_SC_FOUND) { + sc = PARSER_POP; + + on_start_code_found(sc); + + } else if (int_status & PARSER_INTSTAT_DISCARD) + on_start_code_found(0); +} + +static irqreturn_t parser_isr(int irq, void *dev_id) +{ + tasklet_schedule(&psparser_tasklet); + + return IRQ_HANDLED; +} + +static ssize_t _psparser_write(const char __user *buf, size_t count) +{ + size_t r = count; + const char __user *p = buf; + u32 len; + int ret; + dma_addr_t dma_addr = 0; + + if (r > 0) { + len = min_t(size_t, r, FETCHBUF_SIZE); + if (copy_from_user(fetchbuf, p, len)) + return -EFAULT; + + dma_addr = + dma_map_single(amports_get_dma_device(), + fetchbuf, FETCHBUF_SIZE, DMA_TO_DEVICE); + if (dma_mapping_error(amports_get_dma_device(), dma_addr)) + return -EFAULT; + + + fetch_done = 0; + + wmb(); /* Ensure fetchbuf contents visible */ + + WRITE_PARSER_REG(PARSER_FETCH_ADDR, dma_addr); + + WRITE_PARSER_REG(PARSER_FETCH_CMD, (7 << FETCH_ENDIAN) | len); + dma_unmap_single(amports_get_dma_device(), dma_addr, + FETCHBUF_SIZE, DMA_TO_DEVICE); + ret = + wait_event_interruptible_timeout(wq, fetch_done != 0, + HZ / 10); + if (ret == 0) { + WRITE_PARSER_REG(PARSER_FETCH_CMD, 0); + pr_info("write timeout, retry\n"); + return -EAGAIN; + } else if (ret < 0) + return -ERESTARTSYS; + + p += len; + r -= len; + } + + return count - r; +} + +s32 psparser_init(u32 vid, u32 aid, u32 sid, struct vdec_s *vdec) +{ + s32 r; + u32 parser_sub_start_ptr; + u32 parser_sub_end_ptr; + u32 parser_sub_rp; + +#ifdef DEBUG_VOB_SUB + u8 i; + + for (i = 0; i < MAX_SUB_NUM; i++) { + sub_info[i] = kzalloc(sizeof(struct subtitle_info), GFP_KERNEL); + if (!sub_info[i]) { + pr_info + ("[psparser_init]alloc for subtitle info failed\n"); + } else + sub_info[i]->id = -1; + } + sub_found_num = 0; +#endif + parser_sub_start_ptr = READ_PARSER_REG(PARSER_SUB_START_PTR); + parser_sub_end_ptr = READ_PARSER_REG(PARSER_SUB_END_PTR); + parser_sub_rp = READ_PARSER_REG(PARSER_SUB_RP); + + video_id = vid; + audio_id = aid; + sub_id = sid; + audio_got_first_pts = 0; + video_got_first_dts = 0; + sub_got_first_pts = 0; + first_apts = 0; + first_vpts = 0; + pts_equ_dts_flag = 0; + +#ifdef VIDEO_AUTO_FLUSH + video_auto_flush_state = VIDEO_AUTO_FLUSH_IDLE; +#endif + + pr_info("video 0x%x, audio 0x%x, sub 0x%x\n", video_id, audio_id, + sub_id); + if (fetchbuf == 0) { + pr_info("%s: no fetchbuf\n", __func__); + return -ENOMEM; + } + + WRITE_RESET_REG(RESET1_REGISTER, RESET_PARSER); + + /* TS data path */ +#ifndef CONFIG_AM_DVB + WRITE_DEMUX_REG(FEC_INPUT_CONTROL, 0); +#else + tsdemux_set_reset_flag(); +#endif + CLEAR_DEMUX_REG_MASK(TS_HIU_CTL, 1 << USE_HI_BSF_INTERFACE); + CLEAR_DEMUX_REG_MASK(TS_HIU_CTL_2, 1 << USE_HI_BSF_INTERFACE); + CLEAR_DEMUX_REG_MASK(TS_HIU_CTL_3, 1 << USE_HI_BSF_INTERFACE); + CLEAR_DEMUX_REG_MASK(TS_FILE_CONFIG, (1 << TS_HIU_ENABLE)); + + /* hook stream buffer with PARSER */ + WRITE_PARSER_REG(PARSER_VIDEO_START_PTR, vdec->input.start); + WRITE_PARSER_REG(PARSER_VIDEO_END_PTR, + vdec->input.start + vdec->input.size - 8); + + if (vdec_single(vdec)) { + CLEAR_PARSER_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR); + WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + CLEAR_VREG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + } else { + SET_PARSER_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR); + WRITE_PARSER_REG(PARSER_VIDEO_WP, vdec->input.start); + WRITE_PARSER_REG(PARSER_VIDEO_RP, vdec->input.start); + } + + WRITE_PARSER_REG(PARSER_AUDIO_START_PTR, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + WRITE_PARSER_REG(PARSER_AUDIO_END_PTR, + READ_AIU_REG(AIU_MEM_AIFIFO_END_PTR)); + CLEAR_PARSER_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR); + + WRITE_PARSER_REG(PARSER_CONFIG, + (10 << PS_CFG_PFIFO_EMPTY_CNT_BIT) | + (1 << PS_CFG_MAX_ES_WR_CYCLE_BIT) | + (16 << PS_CFG_MAX_FETCH_CYCLE_BIT)); + + if (vdec_single(vdec)) { + WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + CLEAR_VREG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + } + + WRITE_AIU_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + CLEAR_AIU_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + + WRITE_PARSER_REG(PARSER_SUB_START_PTR, parser_sub_start_ptr); + WRITE_PARSER_REG(PARSER_SUB_END_PTR, parser_sub_end_ptr); + WRITE_PARSER_REG(PARSER_SUB_RP, parser_sub_start_ptr); + WRITE_PARSER_REG(PARSER_SUB_WP, parser_sub_start_ptr); + SET_PARSER_REG_MASK(PARSER_ES_CONTROL, + (7 << ES_SUB_WR_ENDIAN_BIT) | ES_SUB_MAN_RD_PTR); + + WRITE_PARSER_REG(PFIFO_RD_PTR, 0); + WRITE_PARSER_REG(PFIFO_WR_PTR, 0); + + WRITE_PARSER_REG(PARSER_SEARCH_PATTERN, MPEG_START_CODE_PATTERN); + WRITE_PARSER_REG(PARSER_SEARCH_MASK, MPEG_START_CODE_MASK); + + WRITE_PARSER_REG(PARSER_CONFIG, + (10 << PS_CFG_PFIFO_EMPTY_CNT_BIT) | + (1 << PS_CFG_MAX_ES_WR_CYCLE_BIT) | + PS_CFG_STARTCODE_WID_24 | + PS_CFG_PFIFO_ACCESS_WID_8 | /* single byte pop */ + (16 << PS_CFG_MAX_FETCH_CYCLE_BIT)); + WRITE_PARSER_REG(PARSER_CONTROL, PARSER_AUTOSEARCH); + + tasklet_init(&psparser_tasklet, parser_tasklet, 0); + r = pts_start(PTS_TYPE_VIDEO); + if (r < 0) + goto Err_1; + r = pts_start(PTS_TYPE_AUDIO); + if (r < 0) + goto Err_2; + + video_data_parsed = 0; + audio_data_parsed = 0; + /*TODO irq */ + + r = vdec_request_irq(PARSER_IRQ, parser_isr, + "psparser", (void *)psparser_id); + + if (r) { + pr_info("PS Demux irq register failed.\n"); + + r = -ENOENT; + goto Err_3; + } + + WRITE_PARSER_REG(PARSER_INT_STATUS, 0xffff); + WRITE_PARSER_REG(PARSER_INT_ENABLE, + PARSER_INT_ALL << PARSER_INT_HOST_EN_BIT); + + return 0; + +Err_3: + pts_stop(PTS_TYPE_AUDIO); + +Err_2: + pts_stop(PTS_TYPE_VIDEO); + +Err_1: + return r; +} + +void psparser_release(void) +{ + u8 i; + + pr_info("psparser_release\n"); + + WRITE_PARSER_REG(PARSER_INT_ENABLE, 0); + /*TODO irq */ + + vdec_free_irq(PARSER_IRQ, (void *)psparser_id); + + pts_stop(PTS_TYPE_VIDEO); + pts_stop(PTS_TYPE_AUDIO); +#ifdef DEBUG_VOB_SUB + for (i = 0; i < MAX_SUB_NUM; i++) + kfree(sub_info[i]); + pr_info("psparser release subtitle info\n"); +#endif +} + +ssize_t psparser_write(struct file *file, + struct stream_buf_s *vbuf, + struct stream_buf_s *abuf, + const char __user *buf, size_t count) +{ + s32 r; + + struct port_priv_s *priv = (struct port_priv_s *)file->private_data; + struct stream_port_s *port = priv->port; + + if ((stbuf_space(vbuf) < count) || (stbuf_space(abuf) < count)) { + if (file->f_flags & O_NONBLOCK) + return -EAGAIN; + + if ((port->flag & PORT_FLAG_VID) + && (stbuf_space(vbuf) < count)) { + r = stbuf_wait_space(vbuf, count); + if (r < 0) + return r; + } + if ((port->flag & PORT_FLAG_AID) + && (stbuf_space(abuf) < count)) { + r = stbuf_wait_space(abuf, count); + if (r < 0) + return r; + } + } + + return _psparser_write(buf, count); +} + +void psparser_change_avid(unsigned int vid, unsigned int aid) +{ + video_id = vid; + audio_id = aid; +} + +void psparser_change_sid(unsigned int sid) +{ + sub_id = sid; +} + +void psparser_audio_reset(void) +{ + ulong flags; + + DEFINE_SPINLOCK(lock); + + spin_lock_irqsave(&lock, flags); + + WRITE_PARSER_REG(PARSER_AUDIO_WP, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + WRITE_PARSER_REG(PARSER_AUDIO_RP, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + + WRITE_PARSER_REG(PARSER_AUDIO_START_PTR, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + WRITE_PARSER_REG(PARSER_AUDIO_END_PTR, + READ_AIU_REG(AIU_MEM_AIFIFO_END_PTR)); + CLEAR_PARSER_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR); + + WRITE_AIU_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + CLEAR_AIU_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + + audio_data_parsed = 0; + + spin_unlock_irqrestore(&lock, flags); + +} + +void psparser_sub_reset(void) +{ + ulong flags; + + DEFINE_SPINLOCK(lock); + u32 parser_sub_start_ptr; + u32 parser_sub_end_ptr; + + spin_lock_irqsave(&lock, flags); + + parser_sub_start_ptr = READ_PARSER_REG(PARSER_SUB_START_PTR); + parser_sub_end_ptr = READ_PARSER_REG(PARSER_SUB_END_PTR); + + WRITE_PARSER_REG(PARSER_SUB_START_PTR, parser_sub_start_ptr); + WRITE_PARSER_REG(PARSER_SUB_END_PTR, parser_sub_end_ptr); + WRITE_PARSER_REG(PARSER_SUB_RP, parser_sub_start_ptr); + WRITE_PARSER_REG(PARSER_SUB_WP, parser_sub_start_ptr); + SET_PARSER_REG_MASK(PARSER_ES_CONTROL, + (7 << ES_SUB_WR_ENDIAN_BIT) | ES_SUB_MAN_RD_PTR); + + spin_unlock_irqrestore(&lock, flags); + +} + +u8 psparser_get_sub_found_num(void) +{ +#ifdef DEBUG_VOB_SUB + return sub_found_num; +#else + return 0; +#endif +} + +u8 psparser_get_sub_info(struct subtitle_info **sub_infos) +{ +#ifdef DEBUG_VOB_SUB + u8 i = 0; + int ret = 0; + u8 size = sizeof(struct subtitle_info); + + for (i = 0; i < sub_found_num; i++) { + if (!sub_info[i]) { + pr_info + ("[psparser_get_sub_info:%d] sub_info[%d] NULL\n", + __LINE__, i); + ret = -1; + break; + } + if (!sub_infos[i]) { + pr_info + ("[psparser_get_sub_info:%d] sub_infos[%d] NULL\n", + __LINE__, i); + ret = -2; + break; + } + memcpy(sub_infos[i], sub_info[i], size); + } + return ret; +#else + return 0; +#endif +} diff --git a/drivers/amlogic/media_modules/stream_input/parser/psparser.h b/drivers/amlogic/media_modules/stream_input/parser/psparser.h new file mode 100644 index 000000000000..b83e342d024c --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/psparser.h @@ -0,0 +1,142 @@ +/* + * drivers/amlogic/media/stream_input/parser/psparser.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef PSPARSER_H +#define PSPARSER_H + +#include "../../frame_provider/decoder/utils/vdec.h" + +extern s32 psparser_init(u32 vid, u32 aid, u32 sid, struct vdec_s *vdec); + +extern void psparser_release(void); + +extern ssize_t psparser_write(struct file *file, + struct stream_buf_s *vbuf, + struct stream_buf_s *abuf, + const char __user *buf, size_t count); + +extern void psparser_change_avid(unsigned int vid, unsigned int aid); + +extern void psparser_change_sid(unsigned int sid); + +extern void psparser_audio_reset(void); + +extern void psparser_sub_reset(void); + +extern u8 psparser_get_sub_found_num(void); + +extern u8 psparser_get_sub_info(struct subtitle_info *sub_infos[]); + +#ifdef CONFIG_AM_DVB +extern int tsdemux_set_reset_flag(void); +#endif + +/* TODO: move to register headers */ +#define ES_PACK_SIZE_BIT 8 +#define ES_PACK_SIZE_WID 24 + +#define ES_CTRL_WID 8 +#define ES_CTRL_BIT 0 +#define ES_TYPE_MASK (3 << 6) +#define ES_TYPE_VIDEO (0 << 6) +#define ES_TYPE_AUDIO (1 << 6) +#define ES_TYPE_SUBTITLE (2 << 6) + +#define ES_WRITE (1<<5) +#define ES_PASSTHROUGH (1<<4) +#define ES_INSERT_BEFORE_ES_WRITE (1<<3) +#define ES_DISCARD (1<<2) +#define ES_SEARCH (1<<1) +#define ES_PARSER_START (1<<0) +#define ES_PARSER_BUSY (1<<0) + +#define PARSER_INTSTAT_FETCH_CMD (1<<7) +#define PARSER_INTSTAT_PARSE (1<<4) +#define PARSER_INTSTAT_DISCARD (1<<3) +#define PARSER_INTSTAT_INSZERO (1<<2) +#define PARSER_INTSTAT_ACT_NOSSC (1<<1) +#define PARSER_INTSTAT_SC_FOUND (1<<0) + +#define FETCH_CIR_BUF (1<<31) +#define FETCH_CHK_BUF_STOP (1<<30) +#define FETCH_PASSTHROUGH (1<<29) +#define FETCH_ENDIAN 27 +#define FETCH_PASSTHROUGH_TYPE_MASK (0x3<<27) +#define FETCH_ENDIAN_MASK (0x7<<27) +#define FETCH_BUF_SIZE_MASK (0x7ffffff) +#define FETCH_CMD_PTR_MASK 3 +#define FETCH_CMD_RD_PTR_BIT 5 +#define FETCH_CMD_WR_PTR_BIT 3 +#define FETCH_CMD_NUM_MASK 3 +#define FETCH_CMD_NUM_BIT 0 + +#define ES_COUNT_MASK 0xfff +#define ES_COUNT_BIT 20 +#define ES_REQ_PENDING (1<<19) +#define ES_PASSTHROUGH_EN (1<<18) +#define ES_PASSTHROUGH_TYPE_MASK (3<<16) +#define ES_PASSTHROUGH_TYPE_VIDEO (0<<16) +#define ES_PASSTHROUGH_TYPE_AUDIO (1<<16) +#define ES_PASSTHROUGH_TYPE_SUBTITLE (2<<16) +#define ES_WR_ENDIAN_MASK (0x7) +#define ES_SUB_WR_ENDIAN_BIT 9 +#define ES_SUB_MAN_RD_PTR (1<<8) +#define ES_AUD_WR_ENDIAN_BIT 5 +#define ES_AUD_MAN_RD_PTR (1<<4) +#define ES_VID_WR_ENDIAN_BIT 1 +#define ES_VID_MAN_RD_PTR (1<<0) + +#define PS_CFG_FETCH_DMA_URGENT (1<<31) +#define PS_CFG_STREAM_DMA_URGENT (1<<30) +#define PS_CFG_FORCE_PFIFO_REN (1<<29) +#define PS_CFG_PFIFO_PEAK_EN (1<<28) +#define PS_CFG_SRC_SEL_BIT 24 +#define PS_CFG_SRC_SEL_MASK (3< +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "../amports/amports_priv.h" +#include "streambuf.h" +#include "streambuf_reg.h" +#include +#include "rmparser.h" + +#define MANAGE_PTS + +static u32 fetch_done; +static u32 parse_halt; + +static DECLARE_WAIT_QUEUE_HEAD(rm_wq); +static const char rmparser_id[] = "rmparser-id"; + +static irqreturn_t rm_parser_isr(int irq, void *dev_id) +{ + u32 int_status = READ_PARSER_REG(PARSER_INT_STATUS); + + if (int_status & PARSER_INTSTAT_FETCH_CMD) { + WRITE_PARSER_REG(PARSER_INT_STATUS, PARSER_INTSTAT_FETCH_CMD); + fetch_done = 1; + + wake_up_interruptible(&rm_wq); + } + + return IRQ_HANDLED; +} + +s32 rmparser_init(struct vdec_s *vdec) +{ + s32 r; + + parse_halt = 0; + if (fetchbuf == 0) { + pr_info("%s: no fetchbuf\n", __func__); + return -ENOMEM; + } + + WRITE_RESET_REG(RESET1_REGISTER, RESET_PARSER); + + /* TS data path */ +#ifndef CONFIG_AM_DVB + WRITE_DEMUX_REG(FEC_INPUT_CONTROL, 0); +#else + tsdemux_set_reset_flag(); +#endif + CLEAR_DEMUX_REG_MASK(TS_HIU_CTL, 1 << USE_HI_BSF_INTERFACE); + CLEAR_DEMUX_REG_MASK(TS_HIU_CTL_2, 1 << USE_HI_BSF_INTERFACE); + CLEAR_DEMUX_REG_MASK(TS_HIU_CTL_3, 1 << USE_HI_BSF_INTERFACE); + + CLEAR_DEMUX_REG_MASK(TS_FILE_CONFIG, (1 << TS_HIU_ENABLE)); + + /* hook stream buffer with PARSER */ + WRITE_PARSER_REG(PARSER_VIDEO_START_PTR, vdec->input.start); + WRITE_PARSER_REG(PARSER_VIDEO_END_PTR, + vdec->input.start + vdec->input.size - 8); + + CLEAR_PARSER_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR); + + WRITE_PARSER_REG(PARSER_AUDIO_START_PTR, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + WRITE_PARSER_REG(PARSER_AUDIO_END_PTR, + READ_AIU_REG(AIU_MEM_AIFIFO_END_PTR)); + CLEAR_PARSER_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR); + + WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + CLEAR_VREG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + + WRITE_AIU_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + CLEAR_AIU_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + + WRITE_PARSER_REG(PFIFO_RD_PTR, 0); + WRITE_PARSER_REG(PFIFO_WR_PTR, 0); + + WRITE_PARSER_REG(PARSER_SEARCH_MASK, 0); + WRITE_PARSER_REG(PARSER_CONTROL, (ES_SEARCH | ES_PARSER_START)); + +#ifdef MANAGE_PTS + if (pts_start(PTS_TYPE_VIDEO) < 0) + goto Err_1; + + if (pts_start(PTS_TYPE_AUDIO) < 0) + goto Err_2; +#endif + /*TODO irq */ + + /* enable interrupt */ + + r = vdec_request_irq(PARSER_IRQ, rm_parser_isr, + "rmparser", (void *)rmparser_id); + + if (r) { + pr_info("RM parser irq register failed.\n"); + goto Err_3; + } + + WRITE_PARSER_REG(PARSER_INT_STATUS, 0xffff); + WRITE_PARSER_REG(PARSER_INT_ENABLE, + ((PARSER_INT_ALL & (~PARSER_INTSTAT_FETCH_CMD)) << + PARSER_INT_AMRISC_EN_BIT) + | (PARSER_INTSTAT_FETCH_CMD << PARSER_INT_HOST_EN_BIT)); + + return 0; + +Err_3: + pts_stop(PTS_TYPE_AUDIO); +Err_2: + pts_stop(PTS_TYPE_VIDEO); +Err_1: + return -ENOENT; +} +EXPORT_SYMBOL(rmparser_init); + +void rmparser_release(void) +{ + WRITE_PARSER_REG(PARSER_INT_ENABLE, 0); + /*TODO irq */ + + vdec_free_irq(PARSER_IRQ, (void *)rmparser_id); + +#ifdef MANAGE_PTS + pts_stop(PTS_TYPE_VIDEO); + pts_stop(PTS_TYPE_AUDIO); +#endif + +} +EXPORT_SYMBOL(rmparser_release); + +static inline u32 buf_wp(u32 type) +{ + return (type == BUF_TYPE_VIDEO) ? READ_VREG(VLD_MEM_VIFIFO_WP) : + (type == BUF_TYPE_AUDIO) ? + READ_AIU_REG(AIU_MEM_AIFIFO_MAN_WP) : + READ_PARSER_REG(PARSER_SUB_START_PTR); +} + +static ssize_t _rmparser_write(const char __user *buf, size_t count) +{ + size_t r = count; + const char __user *p = buf; + u32 len; + int ret; + static int halt_droped_len; + u32 vwp, awp; + dma_addr_t dma_addr = 0; + + if (r > 0) { + len = min_t(size_t, r, FETCHBUF_SIZE); + + if (copy_from_user(fetchbuf, p, len)) + return -EFAULT; + dma_addr = + dma_map_single(amports_get_dma_device(), + fetchbuf, FETCHBUF_SIZE, + DMA_TO_DEVICE); + if (dma_mapping_error(amports_get_dma_device(), dma_addr)) + return -EFAULT; + + fetch_done = 0; + + wmb(); /* Ensure fetchbuf contents visible */ + vwp = buf_wp(BUF_TYPE_VIDEO); + awp = buf_wp(BUF_TYPE_AUDIO); + WRITE_PARSER_REG(PARSER_FETCH_ADDR, dma_addr); + + WRITE_PARSER_REG(PARSER_FETCH_CMD, (7 << FETCH_ENDIAN) | len); + dma_unmap_single(amports_get_dma_device(), dma_addr, + FETCHBUF_SIZE, DMA_TO_DEVICE); + ret = + wait_event_interruptible_timeout(rm_wq, fetch_done != 0, + HZ / 10); + if (ret == 0) { + WRITE_PARSER_REG(PARSER_FETCH_CMD, 0); + parse_halt++; + pr_info + ("write timeout,retry,halt_count=%d parse_control=%x\n", + parse_halt, READ_PARSER_REG(PARSER_CONTROL)); + + //vreal_set_fatal_flag(1);//DEBUG_TMP + + if (parse_halt > 10) { + WRITE_PARSER_REG(PARSER_CONTROL, + (ES_SEARCH | ES_PARSER_START)); + pr_info("reset parse_control=%x\n", + READ_PARSER_REG(PARSER_CONTROL)); + } + return -EAGAIN; + } else if (ret < 0) + return -ERESTARTSYS; + + if (vwp == buf_wp(BUF_TYPE_VIDEO) + && awp == buf_wp(BUF_TYPE_AUDIO)) { + struct stream_buf_s *v_buf_t = + get_buf_by_type(BUF_TYPE_VIDEO); + struct stream_buf_s *a_buf_t = + get_buf_by_type(BUF_TYPE_AUDIO); + int v_st_lv = stbuf_level(v_buf_t); + int a_st_lv = stbuf_level(a_buf_t); + + if ((parse_halt + 1) % 10 == 1) { + pr_info("V&A WP not changed after write"); + pr_info(",video %x->%x", vwp, + buf_wp(BUF_TYPE_VIDEO)); + pr_info(",Audio:%x-->%x,parse_halt=%d\n", + awp, buf_wp(BUF_TYPE_AUDIO), + parse_halt); + } + parse_halt++; + +/* wp not changed , + * we think have bugs on parser now. + */ + if (parse_halt > 10 && + (v_st_lv < 1000 || a_st_lv < 100)) { + /*reset while at least one is underflow. */ + WRITE_PARSER_REG(PARSER_CONTROL, + (ES_SEARCH | ES_PARSER_START)); + pr_info("reset parse_control=%x\n", + READ_PARSER_REG(PARSER_CONTROL)); + } + if (parse_halt <= 10 || + halt_droped_len < 100 * 1024) { + /*drops first 10 pkt , + * some times maybe no av data + */ + pr_info("drop this pkt=%d,len=%d\n", parse_halt, + len); + p += len; + r -= len; + halt_droped_len += len; + } else + return -EAGAIN; + } else { + halt_droped_len = 0; + parse_halt = 0; + p += len; + r -= len; + } + } + return count - r; +} + +ssize_t rmparser_write(struct file *file, + struct stream_buf_s *vbuf, + struct stream_buf_s *abuf, + const char __user *buf, size_t count) +{ + s32 r; + struct port_priv_s *priv = (struct port_priv_s *)file->private_data; + struct stream_port_s *port = priv->port; + size_t towrite = count; + + if ((stbuf_space(vbuf) < count) || (stbuf_space(abuf) < count)) { + if (file->f_flags & O_NONBLOCK) { + towrite = min(stbuf_space(vbuf), stbuf_space(abuf)); + if (towrite < 1024) /*? can write small? */ + return -EAGAIN; + } else { + if ((port->flag & PORT_FLAG_VID) + && (stbuf_space(vbuf) < count)) { + r = stbuf_wait_space(vbuf, count); + if (r < 0) + return r; + } + if ((port->flag & PORT_FLAG_AID) + && (stbuf_space(abuf) < count)) { + r = stbuf_wait_space(abuf, count); + if (r < 0) + return r; + } + } + } + towrite = min(towrite, count); + return _rmparser_write(buf, towrite); +} + +void rm_set_vasid(u32 vid, u32 aid) +{ + pr_info("rm_set_vasid aid %d, vid %d\n", aid, vid); + WRITE_PARSER_REG(VAS_STREAM_ID, (aid << 8) | vid); +} + +void rm_audio_reset(void) +{ + ulong flags; + DEFINE_SPINLOCK(lock); + + spin_lock_irqsave(&lock, flags); + + WRITE_PARSER_REG(PARSER_AUDIO_WP, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + WRITE_PARSER_REG(PARSER_AUDIO_RP, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + + WRITE_PARSER_REG(PARSER_AUDIO_START_PTR, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + WRITE_PARSER_REG(PARSER_AUDIO_END_PTR, + READ_AIU_REG(AIU_MEM_AIFIFO_END_PTR)); + CLEAR_PARSER_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR); + + WRITE_AIU_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + CLEAR_AIU_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + + spin_unlock_irqrestore(&lock, flags); +} +EXPORT_SYMBOL(rm_audio_reset); diff --git a/drivers/amlogic/media_modules/stream_input/parser/rmparser.h b/drivers/amlogic/media_modules/stream_input/parser/rmparser.h new file mode 100644 index 000000000000..eb2023a972ba --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/rmparser.h @@ -0,0 +1,136 @@ +/* + * drivers/amlogic/amports/rmparser.h + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef RMPARSER_H +#define RMPARSER_H + +#include "../../frame_provider/decoder/utils/vdec.h" + +extern void rm_set_vasid(u32 vid, u32 aid); + +extern ssize_t rmparser_write(struct file *file, + struct stream_buf_s *vbuf, + struct stream_buf_s *abuf, + const char __user *buf, size_t count); + +s32 rmparser_init(struct vdec_s *vdec); + +extern void rmparser_release(void); + +extern void rm_audio_reset(void); + +extern void vreal_set_fatal_flag(int flag); + +#ifdef CONFIG_AM_DVB +extern int tsdemux_set_reset_flag(void); +#endif + +/* TODO: move to register headers */ +#define ES_PACK_SIZE_BIT 8 +#define ES_PACK_SIZE_WID 24 + +#define ES_CTRL_WID 8 +#define ES_CTRL_BIT 0 +#define ES_TYPE_MASK (3 << 6) +#define ES_TYPE_VIDEO (0 << 6) +#define ES_TYPE_AUDIO (1 << 6) +#define ES_TYPE_SUBTITLE (2 << 6) + +#define ES_WRITE (1<<5) +#define ES_PASSTHROUGH (1<<4) +#define ES_INSERT_BEFORE_ES_WRITE (1<<3) +#define ES_DISCARD (1<<2) +#define ES_SEARCH (1<<1) +#define ES_PARSER_START (1<<0) +#define ES_PARSER_BUSY (1<<0) + +#define PARSER_INTSTAT_FETCH_CMD (1<<7) +#define PARSER_INTSTAT_PARSE (1<<4) +#define PARSER_INTSTAT_DISCARD (1<<3) +#define PARSER_INTSTAT_INSZERO (1<<2) +#define PARSER_INTSTAT_ACT_NOSSC (1<<1) +#define PARSER_INTSTAT_SC_FOUND (1<<0) + +#define FETCH_CIR_BUF (1<<31) +#define FETCH_CHK_BUF_STOP (1<<30) +#define FETCH_PASSTHROUGH (1<<29) +#define FETCH_ENDIAN 27 +#define FETCH_PASSTHROUGH_TYPE_MASK (0x3<<27) +#define FETCH_ENDIAN_MASK (0x7<<27) +#define FETCH_BUF_SIZE_MASK (0x7ffffff) +#define FETCH_CMD_PTR_MASK 3 +#define FETCH_CMD_RD_PTR_BIT 5 +#define FETCH_CMD_WR_PTR_BIT 3 +#define FETCH_CMD_NUM_MASK 3 +#define FETCH_CMD_NUM_BIT 0 + +#define ES_COUNT_MASK 0xfff +#define ES_COUNT_BIT 20 +#define ES_REQ_PENDING (1<<19) +#define ES_PASSTHROUGH_EN (1<<18) +#define ES_PASSTHROUGH_TYPE_MASK (3<<16) +#define ES_PASSTHROUGH_TYPE_VIDEO (0<<16) +#define ES_PASSTHROUGH_TYPE_AUDIO (1<<16) +#define ES_PASSTHROUGH_TYPE_SUBTITLE (2<<16) +#define ES_WR_ENDIAN_MASK (0x7) +#define ES_SUB_WR_ENDIAN_BIT 9 +#define ES_SUB_MAN_RD_PTR (1<<8) +#define ES_AUD_WR_ENDIAN_BIT 5 +#define ES_AUD_MAN_RD_PTR (1<<4) +#define ES_VID_WR_ENDIAN_BIT 1 +#define ES_VID_MAN_RD_PTR (1<<0) + +#define PS_CFG_FETCH_DMA_URGENT (1<<31) +#define PS_CFG_STREAM_DMA_URGENT (1<<30) +#define PS_CFG_FORCE_PFIFO_REN (1<<29) +#define PS_CFG_PFIFO_PEAK_EN (1<<28) +#define PS_CFG_SRC_SEL_BIT 24 +#define PS_CFG_SRC_SEL_MASK (3< +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +/* #include */ + +#include +#include "../../frame_provider/decoder/utils/vdec.h" +#include "streambuf_reg.h" +#include "streambuf.h" +#include +#include "../amports/amports_priv.h" +#include +#include +#include + +#define STBUF_SIZE (64*1024) +#define STBUF_WAIT_INTERVAL (HZ/100) +#define MEM_NAME "streambuf" + +void *fetchbuf = 0; + +static s32 _stbuf_alloc(struct stream_buf_s *buf, bool is_secure) +{ + if (buf->buf_size == 0) + return -ENOBUFS; + + while (buf->buf_start == 0) { + int flags = CODEC_MM_FLAGS_DMA; + + buf->buf_page_num = PAGE_ALIGN(buf->buf_size) / PAGE_SIZE; + if (buf->type == BUF_TYPE_SUBTITLE) + flags = CODEC_MM_FLAGS_DMA_CPU; + + /* + *if 4k, + *used cma first,for less mem fragments. + */ + if (((buf->type == BUF_TYPE_HEVC) || + (buf->type == BUF_TYPE_VIDEO)) && + buf->for_4k) + flags |= CODEC_MM_FLAGS_CMA_FIRST; + if (buf->buf_size > 20 * 1024 * 1024) + flags |= CODEC_MM_FLAGS_CMA_FIRST; + + if ((buf->type == BUF_TYPE_HEVC) || + (buf->type == BUF_TYPE_VIDEO)) { + flags |= CODEC_MM_FLAGS_FOR_VDECODER; + } else if (buf->type == BUF_TYPE_AUDIO) { + flags |= CODEC_MM_FLAGS_FOR_ADECODER; + flags |= CODEC_MM_FLAGS_DMA_CPU; + } + + if (is_secure) + flags |= CODEC_MM_FLAGS_TVP; + + buf->buf_start = codec_mm_alloc_for_dma(MEM_NAME, + buf->buf_page_num, 4+PAGE_SHIFT, flags); + if (!buf->buf_start) { + int is_video = (buf->type == BUF_TYPE_HEVC) || + (buf->type == BUF_TYPE_VIDEO); + if (is_video && buf->buf_size >= 9 * SZ_1M) {/*min 6M*/ + int old_size = buf->buf_size; + + buf->buf_size = + PAGE_ALIGN(buf->buf_size * 2/3); + pr_info("%s stbuf alloced size = %d failed try small %d size\n", + (buf->type == BUF_TYPE_HEVC) ? "HEVC" : + (buf->type == BUF_TYPE_VIDEO) ? "Video" : + (buf->type == BUF_TYPE_AUDIO) ? "Audio" : + "Subtitle", old_size, buf->buf_size); + continue; + } + pr_info("%s stbuf alloced size = %d failed\n", + (buf->type == BUF_TYPE_HEVC) ? "HEVC" : + (buf->type == BUF_TYPE_VIDEO) ? "Video" : + (buf->type == BUF_TYPE_AUDIO) ? "Audio" : + "Subtitle", buf->buf_size); + return -ENOMEM; + } + + buf->is_secure = is_secure; + + pr_debug("%s stbuf alloced at %p, secure = %d, size = %d\n", + (buf->type == BUF_TYPE_HEVC) ? "HEVC" : + (buf->type == BUF_TYPE_VIDEO) ? "Video" : + (buf->type == BUF_TYPE_AUDIO) ? "Audio" : + "Subtitle", (void *)buf->buf_start, + buf->is_secure, + buf->buf_size); + } + if (buf->buf_size < buf->canusebuf_size) + buf->canusebuf_size = buf->buf_size; + buf->flag |= BUF_FLAG_ALLOC; + + return 0; +} + +int stbuf_change_size(struct stream_buf_s *buf, int size, bool is_secure) +{ + unsigned long old_buf; + int old_size, old_pagenum; + int ret; + + pr_info("buffersize=%d,%d,start=%p, secure=%d\n", size, buf->buf_size, + (void *)buf->buf_start, is_secure); + + if (buf->buf_size == size && buf->buf_start != 0) + return 0; + + old_buf = buf->buf_start; + old_size = buf->buf_size; + old_pagenum = buf->buf_page_num; + buf->buf_start = 0; + buf->buf_size = size; + ret = size; + + if (size == 0 || + _stbuf_alloc(buf, is_secure) == 0) { + /* + * size=0:We only free the old memory; + * alloc ok,changed to new buffer + */ + if (old_buf != 0) { + codec_mm_free_for_dma(MEM_NAME, old_buf); + } + + if (size == 0) + buf->is_secure = false; + + pr_info("changed the (%d) buffer size from %d to %d\n", + buf->type, old_size, size); + return 0; + } else { + /* alloc failed */ + buf->buf_start = old_buf; + buf->buf_size = old_size; + buf->buf_page_num = old_pagenum; + pr_info("changed the (%d) buffer size from %d to %d,failed\n", + buf->type, old_size, size); + } + + return ret; +} + +int stbuf_fetch_init(void) +{ + if (NULL != fetchbuf) + return 0; + + fetchbuf = (void *)__get_free_pages(GFP_KERNEL, + get_order(FETCHBUF_SIZE)); + + if (!fetchbuf) { + pr_info("%s: Can not allocate fetch working buffer\n", + __func__); + return -ENOMEM; + } + return 0; +} + +void stbuf_fetch_release(void) +{ + if (0 && fetchbuf) { + /* always don't free.for safe alloc/free*/ + free_pages((unsigned long)fetchbuf, get_order(FETCHBUF_SIZE)); + fetchbuf = 0; + } +} + +static void _stbuf_timer_func(unsigned long arg) +{ + struct stream_buf_s *p = (struct stream_buf_s *)arg; + + if (stbuf_space(p) < p->wcnt) { + p->timer.expires = jiffies + STBUF_WAIT_INTERVAL; + + add_timer(&p->timer); + } else + wake_up_interruptible(&p->wq); + +} + +u32 stbuf_level(struct stream_buf_s *buf) +{ + if ((buf->type == BUF_TYPE_HEVC) || (buf->type == BUF_TYPE_VIDEO)) { + if (READ_PARSER_REG(PARSER_ES_CONTROL) & 1) { + int level = READ_PARSER_REG(PARSER_VIDEO_WP) - + READ_PARSER_REG(PARSER_VIDEO_RP); + if (level < 0) + level += READ_PARSER_REG(PARSER_VIDEO_END_PTR) - + READ_PARSER_REG(PARSER_VIDEO_START_PTR) + 8; + return (u32)level; + } else + return (buf->type == BUF_TYPE_HEVC) ? + READ_VREG(HEVC_STREAM_LEVEL) : + _READ_ST_REG(LEVEL); + } + + return _READ_ST_REG(LEVEL); +} + +u32 stbuf_rp(struct stream_buf_s *buf) +{ + if ((buf->type == BUF_TYPE_HEVC) || (buf->type == BUF_TYPE_VIDEO)) { + if (READ_PARSER_REG(PARSER_ES_CONTROL) & 1) + return READ_PARSER_REG(PARSER_VIDEO_RP); + else + return (buf->type == BUF_TYPE_HEVC) ? + READ_VREG(HEVC_STREAM_RD_PTR) : + _READ_ST_REG(RP); + } + + return _READ_ST_REG(RP); +} + +u32 stbuf_space(struct stream_buf_s *buf) +{ + /* reserved space for safe write, + * the parser fifo size is 1024byts, so reserve it + */ + int size; + + size = buf->canusebuf_size - stbuf_level(buf); + + if (buf->canusebuf_size >= buf->buf_size / 2) { + /* old reversed value,tobe full, reversed only... */ + size = size - 6 * 1024; + } + + if ((buf->type == BUF_TYPE_VIDEO) + || (has_hevc_vdec() && buf->type == BUF_TYPE_HEVC)) + size -= READ_PARSER_REG(PARSER_VIDEO_HOLE); + + return size > 0 ? size : 0; +} + +u32 stbuf_size(struct stream_buf_s *buf) +{ + return buf->buf_size; +} + +u32 stbuf_canusesize(struct stream_buf_s *buf) +{ + return buf->canusebuf_size; +} + +s32 stbuf_init(struct stream_buf_s *buf, struct vdec_s *vdec, bool is_multi) +{ + s32 r; + u32 dummy; + u32 addr32; + + if (!buf->buf_start) { + r = _stbuf_alloc(buf, (vdec) ? + vdec->port_flag & PORT_FLAG_DRM : 0); + if (r < 0) + return r; + } + addr32 = buf->buf_start & 0xffffffff; + init_waitqueue_head(&buf->wq); + + /* + * For multidec, do not touch HW stream buffers during port + * init and release. + */ + if ((buf->type == BUF_TYPE_VIDEO) || (buf->type == BUF_TYPE_HEVC)) { + if (vdec) { + if (vdec_stream_based(vdec)) + vdec_set_input_buffer(vdec, addr32, + buf->buf_size); + else + return vdec_set_input_buffer(vdec, addr32, + buf->buf_size); + } + } + + buf->write_thread = 0; + + if ((vdec && !vdec_single(vdec)) || (is_multi)) + return 0; + + if (has_hevc_vdec() && buf->type == BUF_TYPE_HEVC) { + CLEAR_VREG_MASK(HEVC_STREAM_CONTROL, 1); + WRITE_VREG(HEVC_STREAM_START_ADDR, addr32); + WRITE_VREG(HEVC_STREAM_END_ADDR, addr32 + buf->buf_size); + WRITE_VREG(HEVC_STREAM_RD_PTR, addr32); + WRITE_VREG(HEVC_STREAM_WR_PTR, addr32); + + return 0; + } + + if (buf->type == BUF_TYPE_VIDEO) { + _WRITE_ST_REG(CONTROL, 0); + /* reset VLD before setting all pointers */ + WRITE_VREG(VLD_MEM_VIFIFO_WRAP_COUNT, 0); + /*TODO: only > m6*/ +#if 1/* MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ + WRITE_VREG(DOS_SW_RESET0, (1 << 4)); + WRITE_VREG(DOS_SW_RESET0, 0); +#else + WRITE_RESET_REG(RESET0_REGISTER, RESET_VLD); +#endif + + dummy = READ_RESET_REG(RESET0_REGISTER); + WRITE_VREG(POWER_CTL_VLD, 1 << 4); + } else if (buf->type == BUF_TYPE_AUDIO) { + _WRITE_ST_REG(CONTROL, 0); + + WRITE_AIU_REG(AIU_AIFIFO_GBIT, 0x80); + } + + if (buf->type == BUF_TYPE_SUBTITLE) { + WRITE_PARSER_REG(PARSER_SUB_RP, addr32); + WRITE_PARSER_REG(PARSER_SUB_START_PTR, addr32); + WRITE_PARSER_REG(PARSER_SUB_END_PTR, + addr32 + buf->buf_size - 8); + + return 0; + } + + _WRITE_ST_REG(START_PTR, addr32); + _WRITE_ST_REG(CURR_PTR, addr32); + _WRITE_ST_REG(END_PTR, addr32 + buf->buf_size - 8); + + _SET_ST_REG_MASK(CONTROL, MEM_BUFCTRL_INIT); + _CLR_ST_REG_MASK(CONTROL, MEM_BUFCTRL_INIT); + + _WRITE_ST_REG(BUF_CTRL, MEM_BUFCTRL_MANUAL); + _WRITE_ST_REG(WP, addr32); + + _SET_ST_REG_MASK(BUF_CTRL, MEM_BUFCTRL_INIT); + _CLR_ST_REG_MASK(BUF_CTRL, MEM_BUFCTRL_INIT); + + _SET_ST_REG_MASK(CONTROL, + (0x11 << 16) | MEM_FILL_ON_LEVEL | MEM_CTRL_FILL_EN | + MEM_CTRL_EMPTY_EN); + return 0; +} + +void stbuf_vdec2_init(struct stream_buf_s *buf) +{ + + _WRITE_VDEC2_ST_REG(CONTROL, 0); + + _WRITE_VDEC2_ST_REG(START_PTR, _READ_ST_REG(START_PTR)); + _WRITE_VDEC2_ST_REG(END_PTR, _READ_ST_REG(END_PTR)); + _WRITE_VDEC2_ST_REG(CURR_PTR, _READ_ST_REG(CURR_PTR)); + + _WRITE_VDEC2_ST_REG(CONTROL, MEM_FILL_ON_LEVEL | MEM_BUFCTRL_INIT); + _WRITE_VDEC2_ST_REG(CONTROL, MEM_FILL_ON_LEVEL); + + _WRITE_VDEC2_ST_REG(BUF_CTRL, MEM_BUFCTRL_INIT); + _WRITE_VDEC2_ST_REG(BUF_CTRL, 0); + + _WRITE_VDEC2_ST_REG(CONTROL, + (0x11 << 16) | MEM_FILL_ON_LEVEL | MEM_CTRL_FILL_EN + | MEM_CTRL_EMPTY_EN); +} + +s32 stbuf_wait_space(struct stream_buf_s *stream_buf, size_t count) +{ + struct stream_buf_s *p = stream_buf; + long time_out = 200; + + p->wcnt = count; + + setup_timer(&p->timer, _stbuf_timer_func, (ulong) p); + + mod_timer(&p->timer, jiffies + STBUF_WAIT_INTERVAL); + + if (wait_event_interruptible_timeout + (p->wq, stbuf_space(p) >= count, + msecs_to_jiffies(time_out)) == 0) { + del_timer_sync(&p->timer); + + return -EAGAIN; + } + + del_timer_sync(&p->timer); + + return 0; +} + +void stbuf_release(struct stream_buf_s *buf, bool is_multi) +{ + int r; + + buf->first_tstamp = INVALID_PTS; + + r = stbuf_init(buf, NULL, is_multi);/* reinit buffer */ + if (r < 0) + pr_err("stbuf_release %d, stbuf_init failed\n", __LINE__); + + if (buf->flag & BUF_FLAG_ALLOC && buf->buf_start) { + codec_mm_free_for_dma(MEM_NAME, buf->buf_start); + buf->flag &= ~BUF_FLAG_ALLOC; + buf->buf_start = 0; + buf->is_secure = false; + } + buf->flag &= ~BUF_FLAG_IN_USE; +} + +u32 stbuf_sub_rp_get(void) +{ + return READ_PARSER_REG(PARSER_SUB_RP); +} + +void stbuf_sub_rp_set(unsigned int sub_rp) +{ + WRITE_PARSER_REG(PARSER_SUB_RP, sub_rp); + return; +} + +u32 stbuf_sub_wp_get(void) +{ + return READ_PARSER_REG(PARSER_SUB_WP); +} + +u32 stbuf_sub_start_get(void) +{ + return READ_PARSER_REG(PARSER_SUB_START_PTR); +} diff --git a/drivers/amlogic/media_modules/stream_input/parser/streambuf.h b/drivers/amlogic/media_modules/stream_input/parser/streambuf.h new file mode 100644 index 000000000000..6ea2c75c32c2 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/streambuf.h @@ -0,0 +1,139 @@ +/* + * drivers/amlogic/media/stream_input/parser/streambuf.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef STREAMBUF_H +#define STREAMBUF_H +#include + +#define BUF_FLAG_ALLOC 0x01 +#define BUF_FLAG_IN_USE 0x02 +#define BUF_FLAG_PARSER 0x04 +#define BUF_FLAG_FIRST_TSTAMP 0x08 +#define BUF_FLAG_IOMEM 0x10 + +#define BUF_TYPE_VIDEO 0 +#define BUF_TYPE_AUDIO 1 +#define BUF_TYPE_SUBTITLE 2 +#define BUF_TYPE_USERDATA 3 +#define BUF_TYPE_HEVC 4 +#define BUF_MAX_NUM 5 + +#define INVALID_PTS 0xffffffff + +#define FETCHBUF_SIZE (64*1024) +#define USER_DATA_SIZE (8*1024) + +struct vdec_s; + +struct stream_buf_s { + s32 flag; + u32 type; + unsigned long buf_start; + struct page *buf_pages; + int buf_page_num; + u32 buf_size; + u32 default_buf_size; + u32 canusebuf_size; + u32 first_tstamp; + const ulong reg_base; + wait_queue_head_t wq; + struct timer_list timer; + u32 wcnt; + u32 buf_wp; + u32 buf_rp; + u32 max_buffer_delay_ms; + u64 last_write_jiffies64; + void *write_thread; + int for_4k; + bool is_secure; +} /*stream_buf_t */; + +struct stream_port_s { + /* driver info */ + const char *name; + struct device *class_dev; + const struct file_operations *fops; + + /* ports control */ + s32 type; + s32 flag; + s32 pcr_inited; + + /* decoder info */ + s32 vformat; + s32 aformat; + s32 achanl; + s32 asamprate; + s32 adatawidth; + + /* parser info */ + u32 vid; + u32 aid; + u32 sid; + u32 pcrid; +} /*stream_port_t */; +enum drm_level_e { + DRM_LEVEL1 = 1, + DRM_LEVEL2 = 2, + DRM_LEVEL3 = 3, + DRM_NONE = 4, +}; + +struct drm_info { + enum drm_level_e drm_level; + u32 drm_flag; + u32 drm_hasesdata; + u32 drm_priv; + u32 drm_pktsize; + u32 drm_pktpts; + u32 drm_phy; + u32 drm_vir; + u32 drm_remap; + u32 data_offset; + u32 extpad[8]; +} /*drminfo_t */; + +#define TYPE_DRMINFO 0x80 +#define TYPE_PATTERN 0x40 + +struct vdec_s; + +extern void *fetchbuf; + +extern u32 stbuf_level(struct stream_buf_s *buf); +extern u32 stbuf_rp(struct stream_buf_s *buf); +extern u32 stbuf_space(struct stream_buf_s *buf); +extern u32 stbuf_size(struct stream_buf_s *buf); +extern u32 stbuf_canusesize(struct stream_buf_s *buf); +extern s32 stbuf_init(struct stream_buf_s *buf, struct vdec_s *vdec, + bool is_multi); +extern s32 stbuf_wait_space(struct stream_buf_s *stream_buf, size_t count); +extern void stbuf_release(struct stream_buf_s *buf, bool is_multi); +extern int stbuf_change_size(struct stream_buf_s *buf, int size, + bool is_secure); +extern int stbuf_fetch_init(void); +extern void stbuf_fetch_release(void); +extern u32 stbuf_sub_rp_get(void); +extern void stbuf_sub_rp_set(unsigned int sub_rp); +extern u32 stbuf_sub_wp_get(void); +extern u32 stbuf_sub_start_get(void); +extern u32 stbuf_userdata_start_get(void); +extern struct stream_buf_s *get_stream_buffer(int id); + +extern void stbuf_vdec2_init(struct stream_buf_s *buf); + +#endif /* STREAMBUF_H */ diff --git a/drivers/amlogic/media_modules/stream_input/parser/streambuf_reg.h b/drivers/amlogic/media_modules/stream_input/parser/streambuf_reg.h new file mode 100644 index 000000000000..5f0c8ca81dc3 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/streambuf_reg.h @@ -0,0 +1,114 @@ +/* + * drivers/amlogic/media/stream_input/parser/streambuf_reg.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef STREAMBUF_REG_H +#define STREAMBUF_REG_H + +#define HEVC_STREAM_REG_BASE HEVC_STREAM_START_ADDR + +#define VLD_MEM_VIFIFO_REG_BASE VLD_MEM_VIFIFO_START_PTR +#define AIU_MEM_AIFIFO_REG_BASE AIU_MEM_AIFIFO_START_PTR + +#define START_PTR 0 +#define CURR_PTR 1 +#define END_PTR 2 +#define BYTES_AVAIL 3 +#define CONTROL 4 +#define WP 5 +#define RP 6 +#define LEVEL 7 +#define BUF_CTRL 8 + +/* + *#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 + *#define _WRITE_ST_REG(r, val) \ + * __raw_writel(val, (volatile void __iomem *)(buf->reg_base+(r<<2))) + *#define _WRITE_ST_REG_BITS(r, val, s, e) \ + * __raw_writel((((_READ_ST_REG(r) & \ + * (((1L<<(e)-1)<<(s))-1)<<(s)))|((unsigned)((val)&((1L<<(e))-1))<<(s))), \ + * (volatile void __iomem *)(buf->reg_base+(r<<2))) + *#define _SET_ST_REG_MASK(r, val) \ + * __raw_writel(_READ_ST_REG(r)| (val), \ + * (volatile void __iomem *)(buf->reg_base+(r<<2))) + *#define _CLR_ST_REG_MASK(r, val) \ + * __raw_writel(_READ_ST_REG(r)&~(val), \ + * (volatile void __iomem *)(buf->reg_base+(r<<2))) + *#define _READ_ST_REG(r) \ + * (__raw_readl((volatile void __iomem *)(buf->reg_base+(r<<2)))) + * + *#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6TVD + *#define _READ_VDEC2_ST_REG(r) \ + * (__raw_readl((volatile void __iomem *)(buf->reg_base + \ + * DOS_REG_ADDR(VDEC2_VLD_MEM_VIFIFO_START_PTR) - \ + * DOS_REG_ADDR(VLD_MEM_VIFIFO_START_PTR) + (r<<2)))) + *#define _WRITE_VDEC2_ST_REG(r, val) \ + * __raw_writel(val, (volatile void __iomem *)(buf->reg_base + \ + * DOS_REG_ADDR(VDEC2_VLD_MEM_VIFIFO_START_PTR) - \ + * DOS_REG_ADDR(VLD_MEM_VIFIFO_START_PTR) + (r<<2))) + *#endif + * + *#define MEM_BUFCTRL_MANUAL (1<<1) + *#define MEM_BUFCTRL_INIT (1<<0) + *#define MEM_LEVEL_CNT_BIT 18 + *#define MEM_FIFO_CNT_BIT 16 + *#define MEM_FILL_ON_LEVEL (1<<10) + *#define MEM_CTRL_EMPTY_EN (1<<2) + *#define MEM_CTRL_FILL_EN (1<<1) + *#define MEM_CTRL_INIT (1<<0) + * + *#else + *#define _WRITE_ST_REG(r, val) \ + *WRITE_MPEG_REG(buf->reg_base + (r), \ + * (val)) + *#define _WRITE_ST_REG_BITS(r, val, s, e)\ + * WRITE_MPEG_REG(buf->reg_base + (r), \ + * (val), (s), (e)) + *#define _SET_ST_REG_MASK(r, val) SET_MPEG_REG_MASK(buf->reg_base + \ + * (r), (val)) + *#define _CLR_ST_REG_MASK(r, val) CLEAR_MPEG_REG_MASK(buf->reg_base + \ + * (r), (val)) + *#define _READ_ST_REG(r) READ_MPEG_REG(buf->reg_base + (r)) + *#endif + */ + + /*TODO*/ +#define _WRITE_ST_REG(r, val) do { \ + if (buf->reg_base == VLD_MEM_VIFIFO_REG_BASE) \ + codec_dosbus_write((buf->reg_base+(r)), (val)); \ + else \ + codec_aiubus_write((buf->reg_base+(r)), (val)); \ + } while (0) +#define _READ_ST_REG(r) \ + ((buf->reg_base == VLD_MEM_VIFIFO_REG_BASE) ? \ + codec_dosbus_read(buf->reg_base+(r)) : \ + codec_aiubus_read(buf->reg_base+(r))) + +#define _SET_ST_REG_MASK(r, val) _WRITE_ST_REG(r, _READ_ST_REG(r) | (val)) +#define _CLR_ST_REG_MASK(r, val) _WRITE_ST_REG(r, _READ_ST_REG(r)&~(val)) +#define _READ_VDEC2_ST_REG(r) (codec_dosbus_read(\ + (VDEC2_VLD_MEM_VIFIFO_START_PTR+(r)))) +#define _WRITE_VDEC2_ST_REG(r, val) codec_dosbus_write(\ + (VDEC2_VLD_MEM_VIFIFO_START_PTR+r), val) +#define MEM_BUFCTRL_MANUAL (1<<1) +#define MEM_BUFCTRL_INIT (1<<0) +#define MEM_LEVEL_CNT_BIT 18 +#define MEM_FIFO_CNT_BIT 16 +#define MEM_FILL_ON_LEVEL (1<<10) +#define MEM_CTRL_EMPTY_EN (1<<2) +#define MEM_CTRL_FILL_EN (1<<1) +#define MEM_CTRL_INIT (1<<0) +#endif /* STREAMBUF_REG_H */ diff --git a/drivers/amlogic/media_modules/stream_input/parser/thread_rw.c b/drivers/amlogic/media_modules/stream_input/parser/thread_rw.c new file mode 100644 index 000000000000..04e5a2c4613d --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/thread_rw.c @@ -0,0 +1,611 @@ +/* + * drivers/amlogic/media/stream_input/parser/thread_rw.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* #include */ +#include + +#include "../../stream_input/parser/streambuf.h" +#include "../../stream_input/amports/amports_priv.h" +#include "thread_rw.h" + +#define BUF_NAME "fetchbuf" + +#define DEFAULT_BLOCK_SIZE (64*1024) + +struct threadrw_buf { + void *vbuffer; + dma_addr_t dma_handle; + int write_off; + int data_size; + int buffer_size; + int from_cma; +}; + +#define MAX_MM_BUFFER_NUM 16 +struct threadrw_write_task { + struct file *file; + struct delayed_work write_work; + DECLARE_KFIFO_PTR(datafifo, void *); + DECLARE_KFIFO_PTR(freefifo, void *); + int bufs_num; + int max_bufs; + int errors; + spinlock_t lock; + struct mutex mutex; + struct stream_buf_s *sbuf; + int buffered_data_size; + int passed_data_len; + int buffer_size; + int def_block_size; + int data_offset; + int writework_on; + unsigned long codec_mm_buffer[MAX_MM_BUFFER_NUM]; + int manual_write; + int failed_onmore; + wait_queue_head_t wq; + ssize_t (*write)(struct file *, + struct stream_buf_s *, + const char __user *, + size_t, int); + struct threadrw_buf buf[1]; + /*don't add any after buf[] define */ +}; + +static int free_task_buffers(struct threadrw_write_task *task); + +static struct workqueue_struct *threadrw_wq_get(void) +{ + static struct workqueue_struct *threadrw_wq; + + if (!threadrw_wq) + threadrw_wq = create_singlethread_workqueue("threadrw"); + return threadrw_wq; +} + +static int threadrw_schedule_delayed_work( + struct threadrw_write_task *task, + unsigned long delay) +{ + bool ret; + + if (threadrw_wq_get()) { + ret = queue_delayed_work(threadrw_wq_get(), + &task->write_work, delay); + } else + ret = schedule_delayed_work(&task->write_work, delay); + if (!ret) { + cancel_delayed_work(&task->write_work); + if (threadrw_wq_get()) + ret = queue_delayed_work(threadrw_wq_get(), + &task->write_work, 0); + else + ret = schedule_delayed_work(&task->write_work, 0); + } + return 0; +} + +static ssize_t threadrw_write_onece( + struct threadrw_write_task *task, + struct file *file, + struct stream_buf_s *stbuf, + const char __user *buf, size_t count) +{ + struct threadrw_buf *rwbuf = NULL; + int ret = 0; + int to_write; + + if (!kfifo_get(&task->freefifo, (void *)&rwbuf)) { + if (task->errors) + return task->errors; + return -EAGAIN; + } + + to_write = min_t(u32, rwbuf->buffer_size, count); + if (copy_from_user(rwbuf->vbuffer, buf, to_write)) { + kfifo_put(&task->freefifo, (const void *)buf); + ret = -EFAULT; + goto err; + } + rwbuf->data_size = to_write; + rwbuf->write_off = 0; + kfifo_put(&task->datafifo, (const void *)rwbuf); + threadrw_schedule_delayed_work(task, 0); + return to_write; +err: + return ret; +} + +static ssize_t threadrw_write_in( + struct threadrw_write_task *task, + struct stream_buf_s *stbuf, + const char __user *buf, size_t count) +{ + int ret = 0; + int off = 0; + int left = count; + int wait_num = 0; + unsigned long flags; + + while (left > 0) { + ret = threadrw_write_onece(task, + task->file, + stbuf, buf + off, left); + if (ret >= left) { + off = count; + left = 0; + } else if (ret > 0) { + off += ret; + left -= ret; + + } else if (ret < 0) { + if (off > 0) { + break; /*have write ok some data. */ + } else if (ret == -EAGAIN) { + if (!(task->file->f_flags & O_NONBLOCK) && + (++wait_num < 10)) { + wait_event_interruptible_timeout( + task->wq, + !kfifo_is_empty( + &task->freefifo), + HZ / 100); + continue; /* write again. */ + } + ret = -EAGAIN; + break; + } + break; /*to end */ + } + } + + /*end: */ + spin_lock_irqsave(&task->lock, flags); + if (off > 0) { + task->buffered_data_size += off; + task->data_offset += off; + } + spin_unlock_irqrestore(&task->lock, flags); + if (off > 0) + return off; + else + return ret; +} + +static int do_write_work_in(struct threadrw_write_task *task) +{ + struct threadrw_buf *rwbuf = NULL; + int ret; + int need_re_write = 0; + int write_len = 0; + unsigned long flags; + + if (kfifo_is_empty(&task->datafifo)) + return 0; + if (!kfifo_peek(&task->datafifo, (void *)&rwbuf)) + return 0; + if (!task->manual_write && + rwbuf->from_cma && + !rwbuf->write_off) + codec_mm_dma_flush(rwbuf->vbuffer, + rwbuf->buffer_size, + DMA_TO_DEVICE); + if (task->manual_write) { + ret = task->write(task->file, task->sbuf, + (const char __user *)rwbuf->vbuffer + rwbuf->write_off, + rwbuf->data_size, + 2); /* noblock,virtual addr */ + } else { + ret = task->write(task->file, task->sbuf, + (const char __user *)rwbuf->dma_handle + rwbuf->write_off, + rwbuf->data_size, + 3); /* noblock,phy addr */ + } + if (ret == -EAGAIN) { + need_re_write = 0; + /*do later retry. */ + } else if (ret >= rwbuf->data_size) { + write_len += rwbuf->data_size; + if (kfifo_get(&task->datafifo, (void *)&rwbuf)) { + rwbuf->data_size = 0; + kfifo_put(&task->freefifo, (const void *)rwbuf); + /*wakeup write thread. */ + wake_up_interruptible(&task->wq); + } else + pr_err("write ok,but kfifo_get data failed.!!!\n"); + need_re_write = 1; + } else if (ret > 0) { + rwbuf->data_size -= ret; /* half data write */ + rwbuf->write_off += ret; + write_len += ret; + need_re_write = 1; + } else { /*ret <=0 */ + pr_err("get errors ret=%d size=%d\n", ret, + rwbuf->data_size); + task->errors = ret; + } + if (write_len > 0) { + spin_lock_irqsave(&task->lock, flags); + task->passed_data_len += write_len; + task->buffered_data_size -= write_len; + spin_unlock_irqrestore(&task->lock, flags); + } + return need_re_write; + +} + +static void do_write_work(struct work_struct *work) +{ + struct threadrw_write_task *task = container_of(work, + struct threadrw_write_task, + write_work.work); + int need_retry = 1; + + task->writework_on = 1; + while (need_retry) { + mutex_lock(&task->mutex); + need_retry = do_write_work_in(task); + mutex_unlock(&task->mutex); + } + threadrw_schedule_delayed_work(task, HZ / 10); + task->writework_on = 0; +} + +static int alloc_task_buffers_inlock(struct threadrw_write_task *task, + int new_bubffers, + int block_size) +{ + struct threadrw_buf *rwbuf; + int i; + int used_codec_mm = task->manual_write ? 0 : 1; + int new_num = new_bubffers; + int mm_slot = -1; + int start_idx = task->bufs_num; + int total_mm = 0; + unsigned long addr; + + if (codec_mm_get_total_size() < 80 || + codec_mm_get_free_size() < 40) + used_codec_mm = 0; + if (task->bufs_num + new_num > task->max_bufs) + new_num = task->max_bufs - task->bufs_num; + for (i = 0; i < MAX_MM_BUFFER_NUM; i++) { + if (task->codec_mm_buffer[i] == 0) { + mm_slot = i; + break; + } + } + if (mm_slot < 0) + used_codec_mm = 0; + if (block_size <= 0) + block_size = DEFAULT_BLOCK_SIZE; + + if (used_codec_mm && (block_size * new_num) >= 128 * 1024) { + total_mm = ALIGN(block_size * new_num, (1 << 17)); + addr = + codec_mm_alloc_for_dma(BUF_NAME, + total_mm / PAGE_SIZE, 0, + CODEC_MM_FLAGS_DMA_CPU); + if (addr != 0) { + task->codec_mm_buffer[mm_slot] = addr; + task->buffer_size += total_mm; + } else { + used_codec_mm = 0; + } + } + for (i = 0; i < new_num; i++) { + int bufidx = start_idx + i; + + rwbuf = &task->buf[bufidx]; + rwbuf->buffer_size = block_size; + if (used_codec_mm) { + unsigned long start_addr = + task->codec_mm_buffer[mm_slot]; + if (i == new_num - 1) + rwbuf->buffer_size = total_mm - + block_size * i; + rwbuf->dma_handle = (dma_addr_t) start_addr + + block_size * i; + rwbuf->vbuffer = codec_mm_phys_to_virt( + rwbuf->dma_handle); + rwbuf->from_cma = 1; + + } else { + rwbuf->vbuffer = dma_alloc_coherent( + amports_get_dma_device(), + rwbuf->buffer_size, + &rwbuf->dma_handle, GFP_KERNEL); + if (!rwbuf->vbuffer) { + rwbuf->buffer_size = 0; + rwbuf->dma_handle = 0; + task->bufs_num = bufidx; + break; + } + rwbuf->from_cma = 0; + task->buffer_size += rwbuf->buffer_size; + } + + kfifo_put(&task->freefifo, (const void *)rwbuf); + task->bufs_num = bufidx + 1; + } + if (start_idx > 0 ||/*have buffers before*/ + task->bufs_num >= 3 || + task->bufs_num == new_num) { + if (!task->def_block_size) + task->def_block_size = task->buf[0].buffer_size; + return 0; /*must >=3 for swap buffers. */ + } + if (task->bufs_num > 0) + free_task_buffers(task); + return -1; +} + +static int free_task_buffers(struct threadrw_write_task *task) +{ + int i; + + for (i = 0; i < MAX_MM_BUFFER_NUM; i++) { + if (task->codec_mm_buffer[i]) + codec_mm_free_for_dma(BUF_NAME, + task->codec_mm_buffer[i]); + } + for (i = 0; i < task->bufs_num; i++) { + if (task->buf[i].vbuffer && task->buf[i].from_cma == 0) + dma_free_coherent(amports_get_dma_device(), + task->buf[i].buffer_size, + task->buf[i].vbuffer, + task->buf[i].dma_handle); + } + return 0; +} + +static struct threadrw_write_task *threadrw_alloc_in(int num, + int block_size, + ssize_t (*write)(struct file *, + struct stream_buf_s *, + const char __user *, size_t, int), + int flags) +{ + int max_bufs = num; + int task_buffer_size; + struct threadrw_write_task *task; + int ret; + + if (!(flags & 1)) /*not audio*/ + max_bufs = 300; /*can great for video bufs.*/ + task_buffer_size = sizeof(struct threadrw_write_task) + + sizeof(struct threadrw_buf) * max_bufs; + task = vmalloc(task_buffer_size); + + if (!task) + return NULL; + memset(task, 0, task_buffer_size); + + spin_lock_init(&task->lock); + mutex_init(&task->mutex); + INIT_DELAYED_WORK(&task->write_work, do_write_work); + init_waitqueue_head(&task->wq); + ret = kfifo_alloc(&task->datafifo, max_bufs, GFP_KERNEL); + if (ret) + goto err1; + ret = kfifo_alloc(&task->freefifo, max_bufs, GFP_KERNEL); + if (ret) + goto err2; + task->write = write; + task->file = NULL; + task->buffer_size = 0; + task->manual_write = flags & 1; + task->max_bufs = max_bufs; + mutex_lock(&task->mutex); + ret = alloc_task_buffers_inlock(task, num, block_size); + mutex_unlock(&task->mutex); + if (ret < 0) + goto err3; + threadrw_wq_get(); /*start thread. */ + return task; + +err3: + kfifo_free(&task->freefifo); +err2: + kfifo_free(&task->datafifo); +err1: + vfree(task); + pr_err("alloc threadrw failed num:%d,block:%d\n", num, block_size); + return NULL; +} + +/* + *fifo data size; + */ + +int threadrw_buffer_level(struct stream_buf_s *stbuf) +{ + struct threadrw_write_task *task = stbuf->write_thread; + + if (task) + return task->buffered_data_size; + return 0; +} + +int threadrw_buffer_size(struct stream_buf_s *stbuf) +{ + struct threadrw_write_task *task = stbuf->write_thread; + + if (task) + return task->buffer_size; + return 0; +} + +int threadrw_datafifo_len(struct stream_buf_s *stbuf) +{ + struct threadrw_write_task *task = stbuf->write_thread; + + if (task) + return kfifo_len(&task->datafifo); + return 0; +} + +int threadrw_freefifo_len(struct stream_buf_s *stbuf) +{ + struct threadrw_write_task *task = stbuf->write_thread; + + if (task) + return kfifo_len(&task->freefifo); + return 0; +} +int threadrw_support_more_buffers(struct stream_buf_s *stbuf) +{ + struct threadrw_write_task *task = stbuf->write_thread; + + if (!task) + return 0; + if (task->failed_onmore) + return 0; + return task->max_bufs - task->bufs_num; +} + +/* + *data len out fifo; + */ +int threadrw_passed_len(struct stream_buf_s *stbuf) +{ + struct threadrw_write_task *task = stbuf->write_thread; + + if (task) + return task->passed_data_len; + return 0; + +} +/* + *all data writed.; + */ +int threadrw_dataoffset(struct stream_buf_s *stbuf) +{ + struct threadrw_write_task *task = stbuf->write_thread; + int offset = 0; + + if (task) + return task->data_offset; + return offset; + +} + +ssize_t threadrw_write(struct file *file, struct stream_buf_s *stbuf, + const char __user *buf, size_t count) +{ + struct threadrw_write_task *task = stbuf->write_thread; + ssize_t size; + + if (!task->file) { + task->file = file; + task->sbuf = stbuf; + } + mutex_lock(&task->mutex); + size = threadrw_write_in(task, stbuf, buf, count); + mutex_unlock(&task->mutex); + return size; +} + +int threadrw_flush_buffers(struct stream_buf_s *stbuf) +{ + struct threadrw_write_task *task = stbuf->write_thread; + int max_retry = 20; + + if (!task) + return 0; + while (!kfifo_is_empty(&task->datafifo) && max_retry-- > 0) { + threadrw_schedule_delayed_work(task, 0); + msleep(20); + } + if (!kfifo_is_empty(&task->datafifo)) + return -1;/*data not flushed*/ + return 0; +} +int threadrw_alloc_more_buffer_size( + struct stream_buf_s *stbuf, + int size) +{ + struct threadrw_write_task *task = stbuf->write_thread; + int block_size; + int new_num; + int ret = -1; + int old_num; + + if (!task) + return -1; + mutex_lock(&task->mutex); + block_size = task->def_block_size; + if (block_size == 0) + block_size = 32 * 1024; + new_num = size / block_size; + old_num = task->bufs_num; + if (new_num == 0) + new_num = 1; + else if (new_num > task->max_bufs - task->bufs_num) + new_num = task->max_bufs - task->bufs_num; + if (new_num != 0) + ret = alloc_task_buffers_inlock(task, new_num, + block_size); + mutex_unlock(&task->mutex); + pr_info("threadrw add more buffer from %d -> %d for size %d\n", + old_num, task->bufs_num, + size); + if (ret < 0 || old_num == task->bufs_num) + task->failed_onmore = 1; + return ret; +} + +void *threadrw_alloc(int num, + int block_size, + ssize_t (*write)(struct file *, + struct stream_buf_s *, + const char __user *, + size_t, int), + int flags) +{ + return threadrw_alloc_in(num, block_size, write, flags); +} + +void threadrw_release(struct stream_buf_s *stbuf) +{ + struct threadrw_write_task *task = stbuf->write_thread; + + if (task) { + wake_up_interruptible(&task->wq); + cancel_delayed_work_sync(&task->write_work); + mutex_lock(&task->mutex); + free_task_buffers(task); + mutex_unlock(&task->mutex); + kfifo_free(&task->freefifo); + kfifo_free(&task->datafifo); + vfree(task); + } + stbuf->write_thread = NULL; +} diff --git a/drivers/amlogic/media_modules/stream_input/parser/thread_rw.h b/drivers/amlogic/media_modules/stream_input/parser/thread_rw.h new file mode 100644 index 000000000000..c6283f0963ab --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/thread_rw.h @@ -0,0 +1,52 @@ +/* + * drivers/amlogic/media/stream_input/parser/thread_rw.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef THREAD_RW_H +#define THREAD_RW_H +#include "../../stream_input/parser/streambuf_reg.h" +#include "../../stream_input/parser/streambuf.h" +#include "../../stream_input/parser/esparser.h" +#include "../../stream_input/amports/amports_priv.h" + +ssize_t threadrw_write(struct file *file, + struct stream_buf_s *stbuf, + const char __user *buf, + size_t count); + +void *threadrw_alloc(int num, + int block_size, + ssize_t (*write)(struct file *, + struct stream_buf_s *, + const char __user *, + size_t, int), + int flags);/*flags &1: manual mode*/ + +void threadrw_release(struct stream_buf_s *stbuf); + +int threadrw_buffer_level(struct stream_buf_s *stbuf); +int threadrw_buffer_size(struct stream_buf_s *stbuf); +int threadrw_datafifo_len(struct stream_buf_s *stbuf); +int threadrw_freefifo_len(struct stream_buf_s *stbuf); +int threadrw_passed_len(struct stream_buf_s *stbuf); +int threadrw_flush_buffers(struct stream_buf_s *stbuf); +int threadrw_dataoffset(struct stream_buf_s *stbuf); +int threadrw_alloc_more_buffer_size( + struct stream_buf_s *stbuf, + int size); +int threadrw_support_more_buffers(struct stream_buf_s *stbuf); + +#endif diff --git a/drivers/amlogic/media_modules/stream_input/parser/tsdemux.c b/drivers/amlogic/media_modules/stream_input/parser/tsdemux.c new file mode 100644 index 000000000000..a93396f350c0 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/tsdemux.c @@ -0,0 +1,1187 @@ +/* + * drivers/amlogic/media/stream_input/parser/tsdemux.c + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +/* #include */ +#include +/* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ +/* #include */ +/* #endif */ + +#include "../../frame_provider/decoder/utils/vdec.h" +#include +#include "streambuf_reg.h" +#include "streambuf.h" +#include + +#include "tsdemux.h" +#include +#include "../amports/amports_priv.h" + + +static const char tsdemux_fetch_id[] = "tsdemux-fetch-id"; +static const char tsdemux_irq_id[] = "tsdemux-irq-id"; + +static u32 curr_pcr_num = 0xffff; +static u32 curr_vid_id = 0xffff; +static u32 curr_aud_id = 0xffff; +static u32 curr_sub_id = 0xffff; +static u32 curr_pcr_id = 0xffff; + +static DECLARE_WAIT_QUEUE_HEAD(wq); +static u32 fetch_done; +static u32 discontinued_counter; +static u32 first_pcr; +static u8 pcrscr_valid; +static u8 pcraudio_valid; +static u8 pcrvideo_valid; +static u8 pcr_init_flag; + +static int demux_skipbyte; + +static struct tsdemux_ops *demux_ops; +static DEFINE_SPINLOCK(demux_ops_lock); + +static int enable_demux_driver(void) +{ + return demux_ops ? 1 : 0; +} + +void tsdemux_set_ops(struct tsdemux_ops *ops) +{ + unsigned long flags; + + spin_lock_irqsave(&demux_ops_lock, flags); + demux_ops = ops; + spin_unlock_irqrestore(&demux_ops_lock, flags); +} +EXPORT_SYMBOL(tsdemux_set_ops); + +int tsdemux_set_reset_flag_ext(void) +{ + int r = 0; + + if (demux_ops && demux_ops->set_reset_flag) + r = demux_ops->set_reset_flag(); + + return r; +} + +int tsdemux_set_reset_flag(void) +{ + unsigned long flags; + int r; + + spin_lock_irqsave(&demux_ops_lock, flags); + r = tsdemux_set_reset_flag_ext(); + spin_unlock_irqrestore(&demux_ops_lock, flags); + + return r; +} + +static int tsdemux_reset(void) +{ + unsigned long flags; + int r; + + spin_lock_irqsave(&demux_ops_lock, flags); + if (demux_ops && demux_ops->reset) { + tsdemux_set_reset_flag_ext(); + r = demux_ops->reset(); + } + spin_unlock_irqrestore(&demux_ops_lock, flags); + + return r; +} + +static int tsdemux_request_irq(irq_handler_t handler, void *data) +{ + unsigned long flags; + int r; + + spin_lock_irqsave(&demux_ops_lock, flags); + if (demux_ops && demux_ops->request_irq) + r = demux_ops->request_irq(handler, data); + spin_unlock_irqrestore(&demux_ops_lock, flags); + + return r; +} + +static int tsdemux_free_irq(void) +{ + unsigned long flags; + int r; + + spin_lock_irqsave(&demux_ops_lock, flags); + if (demux_ops && demux_ops->free_irq) + r = demux_ops->free_irq(); + spin_unlock_irqrestore(&demux_ops_lock, flags); + + return r; +} + +static int tsdemux_set_vid(int vpid) +{ + unsigned long flags; + int r = 0; + + spin_lock_irqsave(&demux_ops_lock, flags); + if (demux_ops && demux_ops->set_vid) + r = demux_ops->set_vid(vpid); + spin_unlock_irqrestore(&demux_ops_lock, flags); + + return r; +} + +static int tsdemux_set_aid(int apid) +{ + unsigned long flags; + int r = 0; + + spin_lock_irqsave(&demux_ops_lock, flags); + if (demux_ops && demux_ops->set_aid) + r = demux_ops->set_aid(apid); + spin_unlock_irqrestore(&demux_ops_lock, flags); + + return r; +} + +static int tsdemux_set_sid(int spid) +{ + unsigned long flags; + int r = 0; + + spin_lock_irqsave(&demux_ops_lock, flags); + if (demux_ops && demux_ops->set_sid) + r = demux_ops->set_sid(spid); + spin_unlock_irqrestore(&demux_ops_lock, flags); + + return r; +} + +static int tsdemux_set_pcrid(int pcrpid) +{ + unsigned long flags; + int r = 0; + + spin_lock_irqsave(&demux_ops_lock, flags); + if (demux_ops && demux_ops->set_pcrid) + r = demux_ops->set_pcrid(pcrpid); + spin_unlock_irqrestore(&demux_ops_lock, flags); + + return r; +} + +static int tsdemux_set_skip_byte(int skipbyte) +{ + unsigned long flags; + int r = 0; + + spin_lock_irqsave(&demux_ops_lock, flags); + if (demux_ops && demux_ops->set_skipbyte) + r = demux_ops->set_skipbyte(skipbyte); + spin_unlock_irqrestore(&demux_ops_lock, flags); + + return r; +} + +static int tsdemux_config(void) +{ + return 0; +} + +static void tsdemux_pcr_set(unsigned int pcr); +/*TODO irq*/ +static irqreturn_t tsdemux_isr(int irq, void *dev_id) +{ + u32 int_status = 0; + int id = (long)dev_id; + + if (!enable_demux_driver()) { + int_status = READ_DEMUX_REG(STB_INT_STATUS); + } else { + if (id == 0) + int_status = READ_DEMUX_REG(STB_INT_STATUS); + else if (id == 1) + int_status = READ_DEMUX_REG(STB_INT_STATUS_2); + else if (id == 2) + int_status = READ_DEMUX_REG(STB_INT_STATUS_3); + } + + if (int_status & (1 << NEW_PDTS_READY)) { + if (!enable_demux_driver()) { + u32 pdts_status = READ_DEMUX_REG(STB_PTS_DTS_STATUS); + + if (pdts_status & (1 << VIDEO_PTS_READY)) + pts_checkin_wrptr(PTS_TYPE_VIDEO, + READ_DEMUX_REG(VIDEO_PDTS_WR_PTR), + READ_DEMUX_REG(VIDEO_PTS_DEMUX)); + + if (pdts_status & (1 << AUDIO_PTS_READY)) + pts_checkin_wrptr(PTS_TYPE_AUDIO, + READ_DEMUX_REG(AUDIO_PDTS_WR_PTR), + READ_DEMUX_REG(AUDIO_PTS_DEMUX)); + + WRITE_DEMUX_REG(STB_PTS_DTS_STATUS, pdts_status); + } else { +#define DMX_READ_REG(i, r)\ + ((i) ? ((i == 1) ? READ_DEMUX_REG(r##_2) : \ + READ_DEMUX_REG(r##_3)) : READ_DEMUX_REG(r)) + + u32 pdts_status = DMX_READ_REG(id, STB_PTS_DTS_STATUS); + + if (pdts_status & (1 << VIDEO_PTS_READY)) + pts_checkin_wrptr(PTS_TYPE_VIDEO, + DMX_READ_REG(id, VIDEO_PDTS_WR_PTR), + DMX_READ_REG(id, VIDEO_PTS_DEMUX)); + + if (pdts_status & (1 << AUDIO_PTS_READY)) + pts_checkin_wrptr(PTS_TYPE_AUDIO, + DMX_READ_REG(id, AUDIO_PDTS_WR_PTR), + DMX_READ_REG(id, AUDIO_PTS_DEMUX)); + + if (id == 1) + WRITE_DEMUX_REG(STB_PTS_DTS_STATUS_2, + pdts_status); + else if (id == 2) + WRITE_DEMUX_REG(STB_PTS_DTS_STATUS_3, + pdts_status); + else + WRITE_DEMUX_REG(STB_PTS_DTS_STATUS, + pdts_status); + } + } + if (int_status & (1 << DIS_CONTINUITY_PACKET)) { + discontinued_counter++; + /* pr_info("discontinued counter=%d\n",discontinued_counter); */ + } + if (int_status & (1 << SUB_PES_READY)) { + /* TODO: put data to somewhere */ + /* pr_info("subtitle pes ready\n"); */ + wakeup_sub_poll(); + } + if (int_status & (1< 0) { + if (isphybuf) + len = count; + else { + len = min_t(size_t, r, FETCHBUF_SIZE); + if (copy_from_user(fetchbuf, p, len)) + return -EFAULT; + + dma_addr = + dma_map_single(amports_get_dma_device(), + fetchbuf, + FETCHBUF_SIZE, DMA_TO_DEVICE); + if (dma_mapping_error(amports_get_dma_device(), + dma_addr)) + return -EFAULT; + + + } + + fetch_done = 0; + + wmb(); /* Ensure fetchbuf contents visible */ + + if (isphybuf) { + u32 buf_32 = (unsigned long)buf & 0xffffffff; + WRITE_PARSER_REG(PARSER_FETCH_ADDR, buf_32); + } else { + WRITE_PARSER_REG(PARSER_FETCH_ADDR, dma_addr); + dma_unmap_single(amports_get_dma_device(), dma_addr, + FETCHBUF_SIZE, DMA_TO_DEVICE); + } + + WRITE_PARSER_REG(PARSER_FETCH_CMD, (7 << FETCH_ENDIAN) | len); + + + ret = + wait_event_interruptible_timeout(wq, fetch_done != 0, + HZ / 2); + if (ret == 0) { + WRITE_PARSER_REG(PARSER_FETCH_CMD, 0); + pr_info("write timeout, retry\n"); + return -EAGAIN; + } else if (ret < 0) + return -ERESTARTSYS; + + p += len; + r -= len; + } + + return count - r; +} + +#define PCR_EN 12 + +static int reset_pcr_regs(void) +{ + u32 pcr_num; + u32 pcr_regs = 0; + if (curr_pcr_id >= 0x1FFF) + return 0; + /* set paramater to fetch pcr */ + pcr_num = 0; + if (curr_pcr_id == curr_vid_id) + pcr_num = 0; + else if (curr_pcr_id == curr_aud_id) + pcr_num = 1; + else if (curr_pcr_id == curr_sub_id) + pcr_num = 2; + else + pcr_num = 3; + if (pcr_num != curr_pcr_num) { + u32 clk_unit = 0; + u32 clk_81 = 0; + struct clk *clk; + //clk = clk_get(NULL,"clk81"); + clk= devm_clk_get(amports_get_dma_device(),"clk_81"); + if (IS_ERR(clk) || clk == 0) { + pr_info("[%s:%d] error clock\n", __func__, __LINE__); + return 0; + } + clk_81 = clk_get_rate(clk); + clk_unit = clk_81 / 90000; + pr_info("[%s:%d] clk_81 = %x clk_unit =%x\n", __func__, + __LINE__, clk_81, clk_unit); + pcr_regs = 1 << PCR_EN | clk_unit; + pr_info("[tsdemux_init] the set pcr_regs =%x\n", pcr_regs); + if (READ_DEMUX_REG(TS_HIU_CTL_2) & 0x80) { + WRITE_DEMUX_REG(PCR90K_CTL_2, pcr_regs); + WRITE_DEMUX_REG(ASSIGN_PID_NUMBER_2, pcr_num); + pr_info("[tsdemux_init] To use device 2,pcr_num=%d\n", + pcr_num); + pr_info("tsdemux_init] the read pcr_regs= %x\n", + READ_DEMUX_REG(PCR90K_CTL_2)); + } else if (READ_DEMUX_REG(TS_HIU_CTL_3) & 0x80) { + WRITE_DEMUX_REG(PCR90K_CTL_3, pcr_regs); + WRITE_DEMUX_REG(ASSIGN_PID_NUMBER_3, pcr_num); + pr_info("[tsdemux_init] To use device 3,pcr_num=%d\n", + pcr_num); + pr_info("tsdemux_init] the read pcr_regs= %x\n", + READ_DEMUX_REG(PCR90K_CTL_3)); + } else { + WRITE_DEMUX_REG(PCR90K_CTL, pcr_regs); + WRITE_DEMUX_REG(ASSIGN_PID_NUMBER, pcr_num); + pr_info("[tsdemux_init] To use device 1,pcr_num=%d\n", + pcr_num); + pr_info("tsdemux_init] the read pcr_regs= %x\n", + READ_DEMUX_REG(PCR90K_CTL)); + } + curr_pcr_num = pcr_num; + } + return 1; +} + +s32 tsdemux_init(u32 vid, u32 aid, u32 sid, u32 pcrid, bool is_hevc, + struct vdec_s *vdec) +{ + s32 r; + u32 parser_sub_start_ptr; + u32 parser_sub_end_ptr; + u32 parser_sub_rp; + pcrvideo_valid = 0; + pcraudio_valid = 0; + pcr_init_flag = 0; + + /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ + /*TODO clk */ + /* + *switch_mod_gate_by_type(MOD_DEMUX, 1); + */ + /* #endif */ + + amports_switch_gate("demux", 1); + + parser_sub_start_ptr = READ_PARSER_REG(PARSER_SUB_START_PTR); + parser_sub_end_ptr = READ_PARSER_REG(PARSER_SUB_END_PTR); + parser_sub_rp = READ_PARSER_REG(PARSER_SUB_RP); + + WRITE_RESET_REG(RESET1_REGISTER, RESET_PARSER); + + if (enable_demux_driver()) { + tsdemux_reset(); + } else { + WRITE_RESET_REG(RESET1_REGISTER, RESET_PARSER | RESET_DEMUXSTB); + + WRITE_DEMUX_REG(STB_TOP_CONFIG, 0); + WRITE_DEMUX_REG(DEMUX_CONTROL, 0); + } + + /* set PID filter */ + pr_info + ("tsdemux video_pid = 0x%x, audio_pid = 0x%x,", + vid, aid); + pr_info + ("sub_pid = 0x%x, pcrid = 0x%x\n", + sid, pcrid); + + if (!enable_demux_driver()) { + WRITE_DEMUX_REG(FM_WR_DATA, + (((vid < 0x1fff) + ? (vid & 0x1fff) | (VIDEO_PACKET << 13) + : 0xffff) << 16) + | ((aid < 0x1fff) + ? (aid & 0x1fff) | (AUDIO_PACKET << 13) + : 0xffff)); + WRITE_DEMUX_REG(FM_WR_ADDR, 0x8000); + while (READ_DEMUX_REG(FM_WR_ADDR) & 0x8000) + ; + + WRITE_DEMUX_REG(FM_WR_DATA, + (((sid < 0x1fff) + ? (sid & 0x1fff) | (SUB_PACKET << 13) + : 0xffff) << 16) + | 0xffff); + WRITE_DEMUX_REG(FM_WR_ADDR, 0x8001); + while (READ_DEMUX_REG(FM_WR_ADDR) & 0x8000) + ; + + WRITE_DEMUX_REG(MAX_FM_COMP_ADDR, 1); + + WRITE_DEMUX_REG(STB_INT_MASK, 0); + WRITE_DEMUX_REG(STB_INT_STATUS, 0xffff); + + /* TS data path */ + WRITE_DEMUX_REG(FEC_INPUT_CONTROL, 0x7000); + WRITE_DEMUX_REG(DEMUX_MEM_REQ_EN, + (1 << VIDEO_PACKET) | + (1 << AUDIO_PACKET) | (1 << SUB_PACKET)); + WRITE_DEMUX_REG(DEMUX_ENDIAN, + (7 << OTHER_ENDIAN) | + (7 << BYPASS_ENDIAN) | (0 << SECTION_ENDIAN)); + WRITE_DEMUX_REG(TS_HIU_CTL, 1 << USE_HI_BSF_INTERFACE); + WRITE_DEMUX_REG(TS_FILE_CONFIG, + (demux_skipbyte << 16) | + (6 << DES_OUT_DLY) | + (3 << TRANSPORT_SCRAMBLING_CONTROL_ODD) | + (1 << TS_HIU_ENABLE) | (4 << FEC_FILE_CLK_DIV)); + + /* enable TS demux */ + WRITE_DEMUX_REG(DEMUX_CONTROL, + (1 << STB_DEMUX_ENABLE) | + (1 << KEEP_DUPLICATE_PACKAGE)); + } + + if (fetchbuf == 0) { + pr_info("%s: no fetchbuf\n", __func__); + return -ENOMEM; + } + + /* hook stream buffer with PARSER */ + if (has_hevc_vdec() && is_hevc) { + WRITE_PARSER_REG(PARSER_VIDEO_START_PTR, vdec->input.start); + WRITE_PARSER_REG(PARSER_VIDEO_END_PTR, vdec->input.start + + vdec->input.size - 8); + + if (vdec_single(vdec)) { + CLEAR_PARSER_REG_MASK(PARSER_ES_CONTROL, + ES_VID_MAN_RD_PTR); + /* set vififo_vbuf_rp_sel=>hevc */ + WRITE_VREG(DOS_GEN_CTRL0, 3 << 1); + /* set use_parser_vbuf_wp */ + SET_VREG_MASK(HEVC_STREAM_CONTROL, + (1 << 3) | (0 << 4)); + /* set stream_fetch_enable */ + SET_VREG_MASK(HEVC_STREAM_CONTROL, 1); + /* set stream_buffer_hole with 256 bytes */ + SET_VREG_MASK(HEVC_STREAM_FIFO_CTL, + (1 << 29)); + } else { + SET_PARSER_REG_MASK(PARSER_ES_CONTROL, + ES_VID_MAN_RD_PTR); + WRITE_PARSER_REG(PARSER_VIDEO_WP, vdec->input.start); + WRITE_PARSER_REG(PARSER_VIDEO_RP, vdec->input.start); + } + } else { + WRITE_PARSER_REG(PARSER_VIDEO_START_PTR, vdec->input.start); + WRITE_PARSER_REG(PARSER_VIDEO_END_PTR, vdec->input.start + + vdec->input.size - 8); + + if (vdec_single(vdec)) { + CLEAR_PARSER_REG_MASK(PARSER_ES_CONTROL, + ES_VID_MAN_RD_PTR); + + WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + CLEAR_VREG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, + MEM_BUFCTRL_INIT); + /* set vififo_vbuf_rp_sel=>vdec */ + if (has_hevc_vdec()) + WRITE_VREG(DOS_GEN_CTRL0, 0); + } else { + SET_PARSER_REG_MASK(PARSER_ES_CONTROL, + ES_VID_MAN_RD_PTR); + WRITE_PARSER_REG(PARSER_VIDEO_WP, vdec->input.start); + WRITE_PARSER_REG(PARSER_VIDEO_RP, vdec->input.start); + } + } + + WRITE_PARSER_REG(PARSER_AUDIO_START_PTR, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + WRITE_PARSER_REG(PARSER_AUDIO_END_PTR, + READ_AIU_REG(AIU_MEM_AIFIFO_END_PTR)); + CLEAR_PARSER_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR); + + WRITE_PARSER_REG(PARSER_CONFIG, + (10 << PS_CFG_PFIFO_EMPTY_CNT_BIT) | + (1 << PS_CFG_MAX_ES_WR_CYCLE_BIT) | + (16 << PS_CFG_MAX_FETCH_CYCLE_BIT)); + + WRITE_AIU_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + CLEAR_AIU_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + + WRITE_PARSER_REG(PARSER_SUB_START_PTR, parser_sub_start_ptr); + WRITE_PARSER_REG(PARSER_SUB_END_PTR, parser_sub_end_ptr); + WRITE_PARSER_REG(PARSER_SUB_RP, parser_sub_rp); + SET_PARSER_REG_MASK(PARSER_ES_CONTROL, + (7 << ES_SUB_WR_ENDIAN_BIT) | ES_SUB_MAN_RD_PTR); + + /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ + if (has_hevc_vdec()) + r = pts_start((is_hevc) ? PTS_TYPE_HEVC : PTS_TYPE_VIDEO); + else + /* #endif */ + r = pts_start(PTS_TYPE_VIDEO); + + if (r < 0) { + pr_info("Video pts start failed.(%d)\n", r); + goto err1; + } + r = pts_start(PTS_TYPE_AUDIO); + if (r < 0) { + pr_info("Audio pts start failed.(%d)\n", r); + goto err2; + } + /*TODO irq */ + + r = vdec_request_irq(PARSER_IRQ, parser_isr, + "tsdemux-fetch", (void *)tsdemux_fetch_id); + + if (r) + goto err3; + + WRITE_PARSER_REG(PARSER_INT_STATUS, 0xffff); + WRITE_PARSER_REG(PARSER_INT_ENABLE, + PARSER_INTSTAT_FETCH_CMD << PARSER_INT_HOST_EN_BIT); + + WRITE_PARSER_REG(PARSER_VIDEO_HOLE, 0x400); + WRITE_PARSER_REG(PARSER_AUDIO_HOLE, 0x400); + + discontinued_counter = 0; + + if (!enable_demux_driver()) { + /*TODO irq */ + + r = vdec_request_irq(DEMUX_IRQ, tsdemux_isr, + "tsdemux-irq", (void *)tsdemux_irq_id); + + WRITE_DEMUX_REG(STB_INT_MASK, (1 << SUB_PES_READY) + | (1 << NEW_PDTS_READY) + | (1 << DIS_CONTINUITY_PACKET)); + if (r) + goto err4; + } else { + tsdemux_config(); + tsdemux_request_irq(tsdemux_isr, (void *)tsdemux_irq_id); + if (vid < 0x1FFF) { + curr_vid_id = vid; + tsdemux_set_vid(vid); + pcrvideo_valid = 1; + } + if (aid < 0x1FFF) { + curr_aud_id = aid; + tsdemux_set_aid(aid); + pcraudio_valid = 1; + } + if (sid < 0x1FFF) { + curr_sub_id = sid; + tsdemux_set_sid(sid); + } + + curr_pcr_id = pcrid; + if ((pcrid < 0x1FFF) && (pcrid != vid) && (pcrid != aid) + && (pcrid != sid)) + tsdemux_set_pcrid(pcrid); + } + + pcrscr_valid = reset_pcr_regs(); + first_pcr = 0; + + return 0; + +err4: + /*TODO irq */ + + if (!enable_demux_driver()) + vdec_free_irq(PARSER_IRQ, (void *)tsdemux_fetch_id); + +err3: + pts_stop(PTS_TYPE_AUDIO); +err2: + /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 */ + if (has_hevc_vdec()) + pts_stop((is_hevc) ? PTS_TYPE_HEVC : PTS_TYPE_VIDEO); + else + /* #endif */ + pts_stop(PTS_TYPE_VIDEO); +err1: + pr_info("TS Demux init failed.\n"); + return -ENOENT; +} + +void tsdemux_release(void) +{ + pcrscr_valid = 0; + first_pcr = 0; + pcr_init_flag = 0; + + WRITE_PARSER_REG(PARSER_INT_ENABLE, 0); + WRITE_PARSER_REG(PARSER_VIDEO_HOLE, 0); + WRITE_PARSER_REG(PARSER_AUDIO_HOLE, 0); + + /*TODO irq */ + + vdec_free_irq(PARSER_IRQ, (void *)tsdemux_fetch_id); + + if (!enable_demux_driver()) { + WRITE_DEMUX_REG(STB_INT_MASK, 0); + /*TODO irq */ + + vdec_free_irq(DEMUX_IRQ, (void *)tsdemux_irq_id); + } else { + + tsdemux_set_aid(0xffff); + tsdemux_set_vid(0xffff); + tsdemux_set_sid(0xffff); + tsdemux_set_pcrid(0xffff); + tsdemux_free_irq(); + + curr_vid_id = 0xffff; + curr_aud_id = 0xffff; + curr_sub_id = 0xffff; + curr_pcr_id = 0xffff; + curr_pcr_num = 0xffff; + } + + pts_stop(PTS_TYPE_VIDEO); + pts_stop(PTS_TYPE_AUDIO); + + WRITE_RESET_REG(RESET1_REGISTER, RESET_PARSER); +#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC + SET_PARSER_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR); + WRITE_PARSER_REG(PARSER_VIDEO_WP, 0); + WRITE_PARSER_REG(PARSER_VIDEO_RP, 0); +#endif + + /* #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */ + /*TODO clk */ + /* + *switch_mod_gate_by_type(MOD_DEMUX, 0); + */ + /* #endif */ + amports_switch_gate("demux", 0); + +} + +static int limited_delay_check(struct file *file, + struct stream_buf_s *vbuf, + struct stream_buf_s *abuf, + const char __user *buf, size_t count) +{ + int write_size; + + if (vbuf->max_buffer_delay_ms > 0 && abuf->max_buffer_delay_ms > 0 && + stbuf_level(vbuf) > 1024 && stbuf_level(abuf) > 256) { + int vdelay = + calculation_stream_delayed_ms(PTS_TYPE_VIDEO, + NULL, NULL); + int adelay = + calculation_stream_delayed_ms(PTS_TYPE_AUDIO, + NULL, NULL); + /*max wait 100ms,if timeout,try again top level. */ + int maxretry = 10; + /*too big delay,do wait now. */ + /*if noblock mode,don't do wait. */ + if (!(file->f_flags & O_NONBLOCK)) { + while (vdelay > vbuf->max_buffer_delay_ms + && adelay > abuf->max_buffer_delay_ms + && maxretry-- > 0) { + msleep(20); + vdelay = + calculation_stream_delayed_ms + (PTS_TYPE_VIDEO, NULL, NULL); + adelay = + calculation_stream_delayed_ms + (PTS_TYPE_AUDIO, NULL, NULL); + } + } + if (vdelay > vbuf->max_buffer_delay_ms + && adelay > abuf->max_buffer_delay_ms) + return 0; + } + write_size = min(stbuf_space(vbuf), stbuf_space(abuf)); + write_size = min_t(int, count, write_size); + return write_size; +} + +ssize_t drm_tswrite(struct file *file, + struct stream_buf_s *vbuf, + struct stream_buf_s *abuf, + const char __user *buf, size_t count) +{ + s32 r; + u32 realcount = count; + u32 re_count = count; + u32 havewritebytes = 0; + + struct drm_info tmpmm; + struct drm_info *drm = &tmpmm; + u32 res = 0; + int isphybuf = 0; + unsigned long realbuf; + + struct port_priv_s *priv = (struct port_priv_s *)file->private_data; + struct stream_port_s *port = priv->port; + size_t wait_size, write_size; + + if (buf == NULL || count == 0) + return -EINVAL; + + res = copy_from_user(drm, buf, sizeof(struct drm_info)); + if (res) { + pr_info("drm kmalloc failed res[%d]\n", res); + return -EFAULT; + } + + if (drm->drm_flag == TYPE_DRMINFO && drm->drm_level == DRM_LEVEL1) { + /* buf only has drminfo not have esdata; */ + realcount = drm->drm_pktsize; + realbuf = drm->drm_phy; + isphybuf = 1; + } else + realbuf = (unsigned long)buf; + /* pr_info("drm->drm_flag = 0x%x,realcount = %d , buf = 0x%x ",*/ + /*drm->drm_flag,realcount, buf); */ + + count = realcount; + + while (count > 0) { + if ((stbuf_space(vbuf) < count) || + (stbuf_space(abuf) < count)) { + if (file->f_flags & O_NONBLOCK) { + int v_stbuf_space = stbuf_space(vbuf); + int a_stbuf_space = stbuf_space(abuf); + + write_size = min(v_stbuf_space, a_stbuf_space); + /*have 188 bytes,write now., */ + if (write_size <= 188) + return -EAGAIN; + } else { + wait_size = + min(stbuf_canusesize(vbuf) / 8, + stbuf_canusesize(abuf) / 4); + if ((port->flag & PORT_FLAG_VID) + && (stbuf_space(vbuf) < wait_size)) { + r = stbuf_wait_space(vbuf, wait_size); + + if (r < 0) { + pr_info + ("write no space--- "); + pr_info + ("no space,%d--%d,r-%d\n", + stbuf_space(vbuf), + stbuf_space(abuf), r); + return r; + } + } + + if ((port->flag & PORT_FLAG_AID) + && (stbuf_space(abuf) < wait_size)) { + r = stbuf_wait_space(abuf, wait_size); + + if (r < 0) { + pr_info + ("write no stbuf_wait_space--"); + pr_info + ("no space,%d--%d,r-%d\n", + stbuf_space(vbuf), + stbuf_space(abuf), r); + return r; + } + } + } + } + + write_size = min(stbuf_space(vbuf), stbuf_space(abuf)); + write_size = min(count, write_size); + /* pr_info("write_size = %d,count = %d,\n",*/ + /*write_size, count); */ + if (write_size > 0) + r = _tsdemux_write((const char __user *)realbuf, + write_size, isphybuf); + else + return -EAGAIN; + + havewritebytes += r; + + /* pr_info("havewritebytes = %d, r = %d,\n",*/ + /*havewritebytes, r); */ + if (havewritebytes == realcount) + break; /* write ok; */ + else if (havewritebytes > realcount) + pr_info(" error ! write too much\n"); + + count -= r; + } + return re_count; +} + +ssize_t tsdemux_write(struct file *file, + struct stream_buf_s *vbuf, + struct stream_buf_s *abuf, + const char __user *buf, size_t count) +{ + s32 r; + struct port_priv_s *priv = (struct port_priv_s *)file->private_data; + struct stream_port_s *port = priv->port; + size_t wait_size, write_size; + + if ((stbuf_space(vbuf) < count) || (stbuf_space(abuf) < count)) { + if (file->f_flags & O_NONBLOCK) { + write_size = min(stbuf_space(vbuf), stbuf_space(abuf)); + if (write_size <= 188) /*have 188 bytes,write now., */ + return -EAGAIN; + } else { + wait_size = + min(stbuf_canusesize(vbuf) / 8, + stbuf_canusesize(abuf) / 4); + if ((port->flag & PORT_FLAG_VID) + && (stbuf_space(vbuf) < wait_size)) { + r = stbuf_wait_space(vbuf, wait_size); + + if (r < 0) { + /* pr_info("write no space--- "); + * pr_info("no space,%d--%d,r-%d\n", + * stbuf_space(vbuf), + * stbuf_space(abuf),r); + */ + return r; + } + } + + if ((port->flag & PORT_FLAG_AID) + && (stbuf_space(abuf) < wait_size)) { + r = stbuf_wait_space(abuf, wait_size); + + if (r < 0) { + /* pr_info("write no stbuf_wait_space")' + * pr_info{"---no space,%d--%d,r-%d\n", + * stbuf_space(vbuf), + * stbuf_space(abuf),r); + */ + return r; + } + } + } + } + vbuf->last_write_jiffies64 = jiffies_64; + abuf->last_write_jiffies64 = jiffies_64; + write_size = limited_delay_check(file, vbuf, abuf, buf, count); + if (write_size > 0) + return _tsdemux_write(buf, write_size, 0); + else + return -EAGAIN; +} + +static ssize_t show_discontinue_counter(struct class *class, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", discontinued_counter); +} + +static struct class_attribute tsdemux_class_attrs[] = { + __ATTR(discontinue_counter, S_IRUGO, show_discontinue_counter, NULL), + __ATTR_NULL +}; + +static struct class tsdemux_class = { + .name = "tsdemux", + .class_attrs = tsdemux_class_attrs, + }; + +int tsdemux_class_register(void) +{ + int r = class_register(&tsdemux_class); + + if (r < 0) + pr_info("register tsdemux class error!\n"); + discontinued_counter = 0; + return r; +} + +void tsdemux_class_unregister(void) +{ + class_unregister(&tsdemux_class); +} + +void tsdemux_change_avid(unsigned int vid, unsigned int aid) +{ + if (!enable_demux_driver()) { + WRITE_DEMUX_REG(FM_WR_DATA, + (((vid & 0x1fff) | (VIDEO_PACKET << 13)) << 16) + | ((aid & 0x1fff) | (AUDIO_PACKET << 13))); + WRITE_DEMUX_REG(FM_WR_ADDR, 0x8000); + while (READ_DEMUX_REG(FM_WR_ADDR) & 0x8000) + ; + } else { + curr_vid_id = vid; + curr_aud_id = aid; + + tsdemux_set_vid(vid); + tsdemux_set_aid(aid); + + reset_pcr_regs(); + } + +} + +void tsdemux_change_sid(unsigned int sid) +{ + if (!enable_demux_driver()) { + WRITE_DEMUX_REG(FM_WR_DATA, + (((sid & 0x1fff) | (SUB_PACKET << 13)) << 16) + | 0xffff); + WRITE_DEMUX_REG(FM_WR_ADDR, 0x8001); + while (READ_DEMUX_REG(FM_WR_ADDR) & 0x8000) + ; + } else { + curr_sub_id = sid; + + tsdemux_set_sid(sid); + + reset_pcr_regs(); + } + +} + +void tsdemux_audio_reset(void) +{ + ulong flags; + + DEFINE_SPINLOCK(lock); + + spin_lock_irqsave(&lock, flags); + + WRITE_PARSER_REG(PARSER_AUDIO_WP, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + WRITE_PARSER_REG(PARSER_AUDIO_RP, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + + WRITE_PARSER_REG(PARSER_AUDIO_START_PTR, + READ_AIU_REG(AIU_MEM_AIFIFO_START_PTR)); + WRITE_PARSER_REG(PARSER_AUDIO_END_PTR, + READ_AIU_REG(AIU_MEM_AIFIFO_END_PTR)); + CLEAR_PARSER_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR); + + WRITE_AIU_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + CLEAR_AIU_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT); + + spin_unlock_irqrestore(&lock, flags); + +} + +void tsdemux_sub_reset(void) +{ + ulong flags; + DEFINE_SPINLOCK(lock); + u32 parser_sub_start_ptr; + u32 parser_sub_end_ptr; + + spin_lock_irqsave(&lock, flags); + + parser_sub_start_ptr = READ_PARSER_REG(PARSER_SUB_START_PTR); + parser_sub_end_ptr = READ_PARSER_REG(PARSER_SUB_END_PTR); + + WRITE_PARSER_REG(PARSER_SUB_START_PTR, parser_sub_start_ptr); + WRITE_PARSER_REG(PARSER_SUB_END_PTR, parser_sub_end_ptr); + WRITE_PARSER_REG(PARSER_SUB_RP, parser_sub_start_ptr); + WRITE_PARSER_REG(PARSER_SUB_WP, parser_sub_start_ptr); + SET_PARSER_REG_MASK(PARSER_ES_CONTROL, + (7 << ES_SUB_WR_ENDIAN_BIT) | ES_SUB_MAN_RD_PTR); + + spin_unlock_irqrestore(&lock, flags); + +} + +void tsdemux_set_skipbyte(int skipbyte) +{ + if (!enable_demux_driver()) + demux_skipbyte = skipbyte; + else + tsdemux_set_skip_byte(skipbyte); + +} + +void tsdemux_set_demux(int dev) +{ + if (enable_demux_driver()) { + unsigned long flags; + int r = 0; + + spin_lock_irqsave(&demux_ops_lock, flags); + if (demux_ops && demux_ops->set_demux) + r = demux_ops->set_demux(dev); + spin_unlock_irqrestore(&demux_ops_lock, flags); + } +} + +u32 tsdemux_pcrscr_get(void) +{ + u32 pcr = 0; + + if (pcrscr_valid == 0) + return 0; + + if (READ_DEMUX_REG(TS_HIU_CTL_2) & 0x80) + pcr = READ_DEMUX_REG(PCR_DEMUX_2); + else if (READ_DEMUX_REG(TS_HIU_CTL_3) & 0x80) + pcr = READ_DEMUX_REG(PCR_DEMUX_3); + else + pcr = READ_DEMUX_REG(PCR_DEMUX); + if (first_pcr == 0) + first_pcr = pcr; + return pcr; +} + +u32 tsdemux_first_pcrscr_get(void) +{ + if (pcrscr_valid == 0) + return 0; + + if (first_pcr == 0) { + u32 pcr; + if (READ_DEMUX_REG(TS_HIU_CTL_2) & 0x80) + pcr = READ_DEMUX_REG(PCR_DEMUX_2); + else if (READ_DEMUX_REG(TS_HIU_CTL_3) & 0x80) + pcr = READ_DEMUX_REG(PCR_DEMUX_3); + else + pcr = READ_DEMUX_REG(PCR_DEMUX); + first_pcr = pcr; + /* pr_info("set first_pcr = 0x%x\n", pcr); */ + } + + return first_pcr; +} + +u8 tsdemux_pcrscr_valid(void) +{ + return pcrscr_valid; +} + +u8 tsdemux_pcraudio_valid(void) +{ + return pcraudio_valid; +} + +u8 tsdemux_pcrvideo_valid(void) +{ + return pcrvideo_valid; +} + +void tsdemux_pcr_set(unsigned int pcr) +{ + if (pcr_init_flag == 0) { + timestamp_pcrscr_set(pcr); + timestamp_pcrscr_enable(1); + pcr_init_flag = 1; + } +} + +void tsdemux_tsync_func_init(void) +{ + register_tsync_callbackfunc( + TSYNC_PCRSCR_VALID, (void *)(tsdemux_pcrscr_valid)); + register_tsync_callbackfunc( + TSYNC_PCRSCR_GET, (void *)(tsdemux_pcrscr_get)); + register_tsync_callbackfunc( + TSYNC_FIRST_PCRSCR_GET, (void *)(tsdemux_first_pcrscr_get)); + register_tsync_callbackfunc( + TSYNC_PCRAUDIO_VALID, (void *)(tsdemux_pcraudio_valid)); + register_tsync_callbackfunc( + TSYNC_PCRVIDEO_VALID, (void *)(tsdemux_pcrvideo_valid)); + register_tsync_callbackfunc( + TSYNC_BUF_BY_BYTE, (void *)(get_buf_by_type)); + register_tsync_callbackfunc( + TSYNC_STBUF_LEVEL, (void *)(stbuf_level)); + register_tsync_callbackfunc( + TSYNC_STBUF_SPACE, (void *)(stbuf_space)); + register_tsync_callbackfunc( + TSYNC_STBUF_SIZE, (void *)(stbuf_size)); +} + + diff --git a/drivers/amlogic/media_modules/stream_input/parser/tsdemux.h b/drivers/amlogic/media_modules/stream_input/parser/tsdemux.h new file mode 100644 index 000000000000..f63bcdf0b632 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/parser/tsdemux.h @@ -0,0 +1,103 @@ +/* + * drivers/amlogic/media/stream_input/parser/tsdemux.h + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef TSDEMUX_H +#define TSDEMUX_H +#include + +/* TODO: move to register headers */ +#define NEW_PDTS_READY 4 +#define AUDIO_PTS_READY 2 +#define VIDEO_PTS_READY 0 +#define DIS_CONTINUITY_PACKET 6 +#define SUB_PES_READY 7 +#define PCR_READY 11 + +#define PARSER_INTSTAT_FETCH_CMD (1<<7) + +#define FETCH_ENDIAN 27 +#define FETCH_ENDIAN_MASK (0x7<<27) + +#define RESET_DEMUXSTB (1<<1) +#define RESET_PARSER (1<<8) + +#define VIDEO_PACKET 0 +#define AUDIO_PACKET 1 +#define SUB_PACKET 2 + +#define OTHER_ENDIAN 6 +#define BYPASS_ENDIAN 3 +#define SECTION_ENDIAN 0 + +#define USE_HI_BSF_INTERFACE 7 +#define DES_OUT_DLY 8 +#define TRANSPORT_SCRAMBLING_CONTROL_ODD 6 +#define TS_HIU_ENABLE 5 +#define FEC_FILE_CLK_DIV 0 +#define STB_DEMUX_ENABLE 4 +#define KEEP_DUPLICATE_PACKAGE 6 + +#define ES_VID_MAN_RD_PTR (1<<0) +#define ES_AUD_MAN_RD_PTR (1<<4) + +#define PS_CFG_PFIFO_EMPTY_CNT_BIT 16 +#define PS_CFG_MAX_ES_WR_CYCLE_BIT 12 +#define PS_CFG_MAX_FETCH_CYCLE_BIT 0 + +#define ES_SUB_WR_ENDIAN_BIT 9 +#define ES_SUB_MAN_RD_PTR (1<<8) +#define PARSER_INTSTAT_FETCH_CMD (1<<7) + +#define PARSER_INT_HOST_EN_BIT 8 + +struct stream_buf_s; +struct vdec_s; + +extern s32 tsdemux_init(u32 vid, u32 aid, u32 sid, u32 pcrid, bool is_hevc, + struct vdec_s *vdec); + +extern void tsdemux_release(void); +extern ssize_t drm_tswrite(struct file *file, + struct stream_buf_s *vbuf, + struct stream_buf_s *abuf, + const char __user *buf, size_t count); + +extern ssize_t tsdemux_write(struct file *file, + struct stream_buf_s *vbuf, + struct stream_buf_s *abuf, + const char __user *buf, size_t count); + +extern u32 tsdemux_pcrscr_get(void); +extern u8 tsdemux_pcrscr_valid(void); +extern u8 tsdemux_pcraudio_valid(void); +extern u8 tsdemux_pcrvideo_valid(void); +extern u32 tsdemux_first_pcrscr_get(void); +extern void timestamp_pcrscr_enable(u32 enable); +extern void timestamp_pcrscr_set(u32 pts); + +int tsdemux_class_register(void); +void tsdemux_class_unregister(void); +void tsdemux_change_avid(unsigned int vid, unsigned int aid); +void tsdemux_change_sid(unsigned int sid); +void tsdemux_audio_reset(void); +void tsdemux_sub_reset(void); +void tsdemux_set_skipbyte(int skipbyte); +void tsdemux_set_demux(int dev); +void tsdemux_tsync_func_init(void); + + +#endif /* TSDEMUX_H */ diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/Makefile b/drivers/amlogic/media_modules/stream_input/tv_frontend/Makefile new file mode 100644 index 000000000000..404c513d23f2 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/Makefile @@ -0,0 +1,16 @@ +obj-m += aml_hardware_fe.o + +ccflags-y += -I$(srctree)/drivers/media/dvb-core -I$(srctree)/drivers/gpio -I$(srctree)/include + +aml_hardware_fe-objs += aml_fe.o + +# aml_atvdemod-objs += atv_demod/atvdemod_frontend.o +# aml_atvdemod-objs += atv_demod/atvdemod_func.o + +# aml_dtvdemod-objs += dtv_demod/aml_demod.o +# aml_dtvdemod-objs += dtv_demod/amlfrontend.o +# aml_dtvdemod-objs += dtv_demod/demod_func.o +# aml_dtvdemod-objs += dtv_demod/dvbc_func.o +# aml_dtvdemod-objs += dtv_demod/dvbt_func.o +# aml_dtvdemod-objs += dtv_demod/i2c_func.o +# aml_dtvdemod-objs += dtv_demod/tuner_func.o diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/aml_fe.c b/drivers/amlogic/media_modules/stream_input/tv_frontend/aml_fe.c new file mode 100644 index 000000000000..f683f2ca5f34 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/aml_fe.c @@ -0,0 +1,1353 @@ +/* + * AMLOGIC DVB frontend driver. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +/*add for gpio api by hualing.chen*/ +#include + +#include "aml_fe.h" + +#ifdef pr_dbg +#undef pr_dbg +#endif + +#define pr_dbg(fmt, args ...) \ + pr_info("FE: " fmt, ## args) +#define pr_error(fmt, args ...) pr_err("FE: " fmt, ## args) +#define pr_inf(fmt, args ...) pr_info("FE: " fmt, ## args) + +static DEFINE_SPINLOCK(lock); +static struct aml_fe_drv *tuner_drv_list; +static struct aml_fe_drv *atv_demod_drv_list; +static struct aml_fe_drv *dtv_demod_drv_list; +static struct aml_fe_man fe_man; +static long aml_fe_suspended; + +static int aml_fe_set_sys(struct dvb_frontend *dev, + enum fe_delivery_system sys); + +static struct aml_fe_drv **aml_get_fe_drv_list(enum aml_fe_dev_type_t type) +{ + switch (type) { + case AM_DEV_TUNER: + return &tuner_drv_list; + case AM_DEV_ATV_DEMOD: + return &atv_demod_drv_list; + case AM_DEV_DTV_DEMOD: + return &dtv_demod_drv_list; + default: + return NULL; + } +} + + + +int amlogic_gpio_direction_output(unsigned int pin, int value, + const char *owner) +{ + gpio_direction_output(pin, value); + return 0; +} +EXPORT_SYMBOL(amlogic_gpio_direction_output); +int amlogic_gpio_request(unsigned int pin, const char *label) +{ + return 0; +} +EXPORT_SYMBOL(amlogic_gpio_request); +int aml_register_fe_drv(enum aml_fe_dev_type_t type, struct aml_fe_drv *drv) +{ + if (drv) { + struct aml_fe_drv **list = aml_get_fe_drv_list(type); + unsigned long flags; + + spin_lock_irqsave(&lock, flags); + + drv->next = *list; + *list = drv; + + drv->ref = 0; + + spin_unlock_irqrestore(&lock, flags); + } + + return 0; +} +EXPORT_SYMBOL(aml_register_fe_drv); + +int aml_unregister_fe_drv(enum aml_fe_dev_type_t type, struct aml_fe_drv *drv) +{ + int ret = 0; + + if (drv) { + struct aml_fe_drv *pdrv, *pprev; + struct aml_fe_drv **list = aml_get_fe_drv_list(type); + unsigned long flags; + + spin_lock_irqsave(&lock, flags); + + if (!drv->ref) { + for (pprev = NULL, pdrv = *list; + pdrv; pprev = pdrv, pdrv = pdrv->next) { + if (pdrv == drv) { + if (pprev) + pprev->next = pdrv->next; + else + *list = pdrv->next; + break; + } + } + } else { + pr_error("fe driver %d is inused\n", drv->id); + ret = -1; + } + + spin_unlock_irqrestore(&lock, flags); + } + + return ret; +} +EXPORT_SYMBOL(aml_unregister_fe_drv); + +static int aml_fe_support_sys(struct aml_fe *fe, + enum fe_delivery_system sys) +{ + if (fe->dtv_demod + && fe->dtv_demod->drv + && fe->dtv_demod->drv->support) { + if (!fe->dtv_demod->drv->support(fe->dtv_demod, sys)) + return 0; + } + + if (fe->atv_demod + && fe->atv_demod->drv + && fe->atv_demod->drv->support) { + if (!fe->atv_demod->drv->support(fe->atv_demod, sys)) + return 0; + } + + if (fe->tuner + && fe->tuner->drv + && fe->tuner->drv->support) { + if (!fe->tuner->drv->support(fe->tuner, sys)) + return 0; + } + + return 1; +} +/* + *#define DTV_START_BLIND_SCAN 71 + *#define DTV_CANCEL_BLIND_SCAN 72 + *#define DTV_BLIND_SCAN_MIN_FRE 73 + *#define DTV_BLIND_SCAN_MAX_FRE 74 + *#define DTV_BLIND_SCAN_MIN_SRATE 75 + *#define DTV_BLIND_SCAN_MAX_SRATE 76 + *#define DTV_BLIND_SCAN_FRE_RANGE 77 + *#define DTV_BLIND_SCAN_FRE_STEP 78 + *#define DTV_BLIND_SCAN_TIMEOUT 79 + */ +static int aml_fe_blind_cmd(struct dvb_frontend *dev, + struct dtv_property *tvp) +{ + struct aml_fe *fe; + int ret = 0; + + fe = dev->demodulator_priv; + pr_error("fe blind cmd into cmd:[%d]\n", tvp->cmd); + switch (tvp->cmd) { + case DTV_START_BLIND_SCAN: + if (fe->dtv_demod + && fe->dtv_demod->drv + && fe->dtv_demod->drv->start_blind_scan) { + ret = fe->dtv_demod->drv->start_blind_scan( + fe->dtv_demod); + } else { + pr_error("fe dtv_demod not surport blind start\n"); + } + break; + case DTV_CANCEL_BLIND_SCAN: + if (fe->dtv_demod + && fe->dtv_demod->drv + && fe->dtv_demod->drv->stop_blind_scan) { + ret = fe->dtv_demod->drv->stop_blind_scan( + fe->dtv_demod); + } else { + pr_error("fe dtv_demod not surport blind stop\n"); + } + break; + case DTV_BLIND_SCAN_MIN_FRE: + fe->blind_scan_para.minfrequency = tvp->u.data; + break; + case DTV_BLIND_SCAN_MAX_FRE: + fe->blind_scan_para.maxfrequency = tvp->u.data; + break; + case DTV_BLIND_SCAN_MIN_SRATE: + fe->blind_scan_para.minSymbolRate = tvp->u.data; + break; + case DTV_BLIND_SCAN_MAX_SRATE: + fe->blind_scan_para.maxSymbolRate = tvp->u.data; + break; + case DTV_BLIND_SCAN_FRE_RANGE: + fe->blind_scan_para.frequencyRange = tvp->u.data; + break; + case DTV_BLIND_SCAN_FRE_STEP: + fe->blind_scan_para.frequencyStep = tvp->u.data; + break; + case DTV_BLIND_SCAN_TIMEOUT: + fe->blind_scan_para.timeout = tvp->u.data; + break; + default: + ret = 0; + break; + } + return ret; +} + +static int aml_fe_set_property(struct dvb_frontend *dev, + struct dtv_property *tvp) +{ + struct aml_fe *fe; + int r = 0; + + fe = dev->demodulator_priv; + + if (tvp->cmd == DTV_DELIVERY_SYSTEM) { + enum fe_delivery_system sys = tvp->u.data; + + pr_error("fe aml_fe_set_property %d\n", sys); + r = aml_fe_set_sys(dev, sys); + if (r < 0) + return r; + } + + if (tvp->cmd == DTV_DELIVERY_SUB_SYSTEM) { + int sub_sys = tvp->u.data; + + pr_error("fe aml_fe_set_property sub_sys: %d\n", sub_sys); + fe->sub_sys = sub_sys; + r = 0; + } + pr_error("fe aml_fe_set_property -tvp->cmd[%d]\n", tvp->cmd); + switch (tvp->cmd) { + case DTV_START_BLIND_SCAN: + case DTV_CANCEL_BLIND_SCAN: + case DTV_BLIND_SCAN_MIN_FRE: + case DTV_BLIND_SCAN_MAX_FRE: + case DTV_BLIND_SCAN_MIN_SRATE: + case DTV_BLIND_SCAN_MAX_SRATE: + case DTV_BLIND_SCAN_FRE_RANGE: + case DTV_BLIND_SCAN_FRE_STEP: + case DTV_BLIND_SCAN_TIMEOUT: + r = aml_fe_blind_cmd(dev, tvp); + if (r < 0) + return r; + default: + break; + } + + if (fe->set_property) { + pr_error("fe fe->set_property -0\n"); + return fe->set_property(dev, tvp); + } + pr_error("fe aml_fe_set_property -2\n"); + return r; +} + +static int aml_fe_get_property(struct dvb_frontend *dev, + struct dtv_property *tvp) +{ + struct aml_fe *fe; + int r = 0; + + fe = dev->demodulator_priv; + + if (tvp->cmd == DTV_TS_INPUT) + tvp->u.data = fe->ts; + if (tvp->cmd == DTV_DELIVERY_SUB_SYSTEM) { + tvp->u.data = fe->sub_sys; + pr_error("fe aml_fe_get_property sub_sys: %d\n", fe->sub_sys); + r = 0; + } + if (fe->get_property) + return fe->get_property(dev, tvp); + + return r; +} + +static int aml_fe_set_sys(struct dvb_frontend *dev, + enum fe_delivery_system sys) +{ + struct aml_fe *fe = dev->demodulator_priv; + unsigned long flags; + int ret = -1; + + if (fe->sys == sys) { + pr_dbg("[%s]:the mode is not change!!!!\n", __func__); + return 0; + } + /*set dvb-t or dvb-t2 + * if dvb-t or t2 is set + * we only set sys value, not init sys + */ + if (fe->sys != SYS_UNDEFINED) { + pr_dbg("release system %d\n", fe->sys); + + if (fe->dtv_demod + && fe->dtv_demod->drv + && fe->dtv_demod->drv->release_sys) + fe->dtv_demod->drv->release_sys(fe->dtv_demod, fe->sys); + if (fe->atv_demod + && fe->atv_demod->drv + && fe->atv_demod->drv->release_sys) + fe->atv_demod->drv->release_sys(fe->atv_demod, fe->sys); + if (fe->tuner + && fe->tuner->drv + && fe->tuner->drv->release_sys) + fe->tuner->drv->release_sys(fe->tuner, fe->sys); + + fe->set_property = NULL; + fe->get_property = NULL; + + fe->sys = SYS_UNDEFINED; + } + + if (sys == SYS_UNDEFINED) + return 0; + + if (!aml_fe_support_sys(fe, sys)) { + int i; + + spin_lock_irqsave(&lock, flags); + for (i = 0; i < FE_DEV_COUNT; i++) { + if (aml_fe_support_sys(&fe_man.fe[i], sys) + && (fe_man.fe[i].dev_id == fe->dev_id)) + break; + } + spin_unlock_irqrestore(&lock, flags); + + if (i >= FE_DEV_COUNT) { + pr_error("do not support delivery system %d\n", sys); + return -1; + } + + fe = &fe_man.fe[i]; + dev->demodulator_priv = fe; + } + + spin_lock_irqsave(&fe->slock, flags); + + memset(&fe->fe->ops.tuner_ops, 0, sizeof(fe->fe->ops.tuner_ops)); + memset(&fe->fe->ops.analog_ops, 0, sizeof(fe->fe->ops.analog_ops)); + memset(&fe->fe->ops.info, 0, sizeof(fe->fe->ops.info)); + fe->fe->ops.release = NULL; + fe->fe->ops.release_sec = NULL; + fe->fe->ops.init = NULL; + fe->fe->ops.sleep = NULL; + fe->fe->ops.write = NULL; + fe->fe->ops.tune = NULL; + fe->fe->ops.get_frontend_algo = NULL; + fe->fe->ops.set_frontend = NULL; + fe->fe->ops.get_tune_settings = NULL; + fe->fe->ops.get_frontend = NULL; + fe->fe->ops.read_status = NULL; + fe->fe->ops.read_ber = NULL; + fe->fe->ops.read_signal_strength = NULL; + fe->fe->ops.read_snr = NULL; + fe->fe->ops.read_ucblocks = NULL; + fe->fe->ops.diseqc_reset_overload = NULL; + fe->fe->ops.diseqc_send_master_cmd = NULL; + fe->fe->ops.diseqc_recv_slave_reply = NULL; + fe->fe->ops.diseqc_send_burst = NULL; + fe->fe->ops.set_tone = NULL; + fe->fe->ops.set_voltage = NULL; + fe->fe->ops.enable_high_lnb_voltage = NULL; + fe->fe->ops.dishnetwork_send_legacy_command = NULL; + fe->fe->ops.i2c_gate_ctrl = NULL; + fe->fe->ops.ts_bus_ctrl = NULL; + fe->fe->ops.search = NULL; + fe->fe->ops.set_property = NULL; + fe->fe->ops.get_property = NULL; + + if (fe->tuner + && fe->tuner->drv + && fe->tuner->drv->get_ops) + fe->tuner->drv->get_ops(fe->tuner, sys, &fe->fe->ops); + + if (fe->atv_demod + && fe->atv_demod->drv + && fe->atv_demod->drv->get_ops) + fe->atv_demod->drv->get_ops(fe->atv_demod, sys, &fe->fe->ops); + + if (fe->dtv_demod + && fe->dtv_demod->drv + && fe->dtv_demod->drv->get_ops) + fe->dtv_demod->drv->get_ops(fe->dtv_demod, sys, &fe->fe->ops); + + spin_unlock_irqrestore(&fe->slock, flags); + + pr_dbg("init system %d\n", sys); + + if (fe->dtv_demod + && fe->dtv_demod->drv + && fe->dtv_demod->drv->init_sys) + ret = fe->dtv_demod->drv->init_sys(fe->dtv_demod, sys); + if (fe->atv_demod + && fe->atv_demod->drv + && fe->atv_demod->drv->init_sys) + ret = fe->atv_demod->drv->init_sys(fe->atv_demod, sys); + if (fe->tuner + && fe->tuner->drv + && fe->tuner->drv->init_sys) + ret = fe->tuner->drv->init_sys(fe->tuner, sys); + + if (ret != 0) { + pr_error("init system, %d fail, ret %d\n", sys, ret); + goto end; + } + + fe->set_property = fe->fe->ops.set_property; + fe->get_property = fe->fe->ops.get_property; + + strcpy(fe->fe->ops.info.name, "amlogic dvb frontend"); + fe->sys = sys; + pr_dbg("set mode ok\n"); + +end: + fe->fe->ops.set_property = aml_fe_set_property; + fe->fe->ops.get_property = aml_fe_get_property; + + return 0; +} + +static const char *aml_fe_dev_type_str(struct aml_fe_dev *dev) +{ + switch (dev->type) { + case AM_DEV_TUNER: + return "tuner"; + case AM_DEV_ATV_DEMOD: + return "atv_demod"; + case AM_DEV_DTV_DEMOD: + return "dtv_demod"; + } + + return ""; +} + +static void aml_fe_property_name(struct aml_fe_dev *dev, const char *name, + char *buf) +{ + const char *tstr; + + tstr = aml_fe_dev_type_str(dev); + + if (name) + sprintf(buf, "%s%d_%s", tstr, dev->dev_id, name); + else + sprintf(buf, "%s%d", tstr, dev->dev_id); +} + +int aml_fe_of_property_string(struct aml_fe_dev *dev, + const char *name, const char **str) +{ + struct platform_device *pdev = dev->man->pdev; + //char buf[128]; + int r; + + //aml_fe_property_name(dev, name, buf); + pr_error("start find resource: \"%s\" --\n", name); + r = of_property_read_string(pdev->dev.of_node, name, str); + if (r) + pr_error("cannot find resource: \"%s\"\n", name); + + return r; +} +EXPORT_SYMBOL(aml_fe_of_property_string); + +int aml_fe_of_property_u32(struct aml_fe_dev *dev, + const char *name, u32 *v) +{ + struct platform_device *pdev = dev->man->pdev; + //char buf[128]; + int r; + + //aml_fe_property_name(dev, name, buf); + r = of_property_read_u32(pdev->dev.of_node, name, v); + if (r) + pr_error("cannot find resource \"%s\"\n", name); + + return r; +} +EXPORT_SYMBOL(aml_fe_of_property_u32); + +static int aml_fe_dev_init(struct aml_fe_man *man, + enum aml_fe_dev_type_t type, + struct aml_fe_dev *dev, + int id) +{ + struct aml_fe_drv **list = aml_get_fe_drv_list(type); + struct aml_fe_drv *drv; + unsigned long flags; + char buf[128]; + const char *str; + char *name = NULL; + u32 value; + int ret; + struct device_node *node; + + dev->man = man; + dev->dev_id = id; + dev->type = type; + dev->drv = NULL; + dev->fe = NULL; + dev->priv_data = NULL; + + memset(buf, 0, 128); + name = NULL; + aml_fe_property_name(dev, name, buf); + pr_dbg("get string: %s\n", buf); + ret = aml_fe_of_property_string(dev, buf, &str); + if (ret) { + pr_dbg("get string: %s error\n", buf); + return 0; + } + + + spin_lock_irqsave(&lock, flags); + + for (drv = *list; drv; drv = drv->next) + if (!strcmp(drv->name, str)) + break; + + if (dev->drv != drv) { + if (dev->drv) { + dev->drv->ref--; + if (dev->drv->owner) + module_put(dev->drv->owner); + } + if (drv) { + drv->ref++; + if (drv->owner) + try_module_get(drv->owner); + } + dev->drv = drv; + } + + spin_unlock_irqrestore(&lock, flags); + + if (drv) { + pr_inf("found driver: %s\n", str); + } else { + pr_err("cannot find driver: %s\n", str); + return -1; + } + /*get i2c adap and i2c addr*/ + memset(buf, 0, 128); + name = "i2c_adap"; + aml_fe_property_name(dev, name, buf); + pr_dbg("get u32: %s\n", buf); + //ret = aml_fe_of_property_u32(dev, buf, &value); + node = of_parse_phandle(dev->man->pdev->dev.of_node, buf, 0); + if (node) { + dev->i2c_adap = of_find_i2c_adapter_by_node(node); + pr_inf("%s:[%p]\n", buf, dev->i2c_adap); + of_node_put(node); + } else { + dev->i2c_adap_id = -1; + pr_error("cannot find resource \"%s\"\n", buf); + } + memset(buf, 0, 128); + name = "i2c_addr"; + aml_fe_property_name(dev, name, buf); + pr_dbg("get u32: %s\n", buf); + ret = aml_fe_of_property_u32(dev, buf, &value); + if (!ret) { + dev->i2c_addr = value; + pr_inf("%s: %d\n", buf, dev->i2c_addr); + } else { + dev->i2c_addr = -1; + pr_error("cannot find resource \"%s\"\n", buf); + } + /*get i2c reset and reset value*/ + memset(buf, 0, 128); + name = "reset_gpio"; + aml_fe_property_name(dev, name, buf); + pr_dbg("get string: %s\n", buf); + ret = aml_fe_of_property_string(dev, buf, &str); + if (!ret) { + dev->reset_gpio = + of_get_named_gpio_flags(dev->man->pdev->dev.of_node, + buf, 0, NULL); + pr_inf("%s: %s\n", buf, str); + } else { + dev->reset_gpio = -1; + pr_error("cannot find resource \"%s\"\n", buf); + } + memset(buf, 0, 128); + name = "reset_value"; + aml_fe_property_name(dev, name, buf); + pr_dbg("get u32: %s\n", buf); + ret = aml_fe_of_property_u32(dev, buf, &value); + if (!ret) { + dev->reset_value = value; + pr_inf("%s: %d\n", buf, dev->reset_value); + } else { + dev->reset_value = -1; + } + + if (dev->drv && dev->drv->init) { + int ret; + + ret = dev->drv->init(dev); + if (ret != 0) { + dev->drv = NULL; + pr_error("[aml_fe..]%s error.\n", __func__); + return ret; + } + } + + return 0; +} + +static int aml_fe_dev_release(struct aml_fe_dev *dev) +{ + if (dev->drv) { + if (dev->drv->owner) + module_put(dev->drv->owner); + dev->drv->ref--; + if (dev->drv->release) + dev->drv->release(dev); + } + + dev->drv = NULL; + return 0; +} + +static void aml_fe_man_run(struct aml_fe *fe) +{ + if (fe->init) + return; + + if (fe->tuner && fe->tuner->drv) + fe->init = 1; + + if (fe->atv_demod && fe->atv_demod->drv) + fe->init = 1; + + if (fe->dtv_demod && fe->dtv_demod->drv) + fe->init = 1; + + if (fe->init) { + struct aml_dvb *dvb = fe->man->dvb; + int reg = 1; + int ret; + int id; + + spin_lock_init(&fe->slock); + + fe->sys = SYS_UNDEFINED; + + pr_dbg("fe: %p\n", fe); + + for (id = 0; id < FE_DEV_COUNT; id++) { + struct aml_fe *prev_fe = &fe_man.fe[id]; + + if (prev_fe == fe) + continue; + if (prev_fe->init && (prev_fe->dev_id == fe->dev_id)) { + reg = 0; + break; + } + } + + fe->fe = &fe_man.dev[fe->dev_id]; + if (reg) { + fe->fe->demodulator_priv = fe; + fe->fe->ops.set_property = aml_fe_set_property; + fe->fe->ops.get_property = aml_fe_set_property; + } + + if (fe->tuner) + fe->tuner->fe = fe; + if (fe->atv_demod) + fe->atv_demod->fe = fe; + if (fe->dtv_demod) + fe->dtv_demod->fe = fe; + + ret = dvb_register_frontend(&dvb->dvb_adapter, fe->fe); + if (ret) { + pr_error("register fe%d failed\n", fe->dev_id); + return; + } + } +} + +static void fe_property_name(struct aml_fe *fe, const char *name, + char *buf) +{ + if (name) + sprintf(buf, "fe%d_%s", fe->dev_id, name); + else + sprintf(buf, "fe%d", fe->dev_id); +} + +static int fe_of_property_u32(struct aml_fe *fe, + const char *name, u32 *v) +{ + struct platform_device *pdev = fe->man->pdev; + char buf[128]; + int r; + + fe_property_name(fe, name, buf); + r = of_property_read_u32(pdev->dev.of_node, buf, v); + if (r) + pr_error("cannot find resource \"%s\"\n", buf); + + return r; +} + +static int aml_fe_man_init(struct aml_fe_man *man, struct aml_fe *fe, int id) +{ + u32 value; + int ret; + + fe->sys = SYS_UNDEFINED; + fe->man = man; + fe->dev_id = id; + fe->init = 0; + fe->ts = AM_TS_SRC_TS0; + fe->work_running = 0; + fe->work_q = NULL; + fe->tuner = NULL; + fe->atv_demod = NULL; + fe->dtv_demod = NULL; + fe->do_work = NULL; + fe->get_property = NULL; + fe->set_property = NULL; + + init_waitqueue_head(&fe->wait_q); + spin_lock_init(&fe->slock); + + ret = fe_of_property_u32(fe, "tuner", &value); + if (!ret) { + int id = value; + + if ((id < 0) || (id >= FE_DEV_COUNT) || !fe_man.tuner[id].drv) { + pr_error("invalid tuner device id %d\n", id); + return -1; + } + + fe->tuner = &fe_man.tuner[id]; + fe_man.tuner[id].fe = fe; + } + + ret = fe_of_property_u32(fe, "atv_demod", &value); + if (!ret) { + int id = value; + + if ((id < 0) || + (id >= FE_DEV_COUNT) || + !fe_man.atv_demod[id].drv) { + pr_error("invalid ATV demod device id %d\n", id); + return -1; + } + + fe->atv_demod = &fe_man.atv_demod[id]; + fe_man.atv_demod[id].fe = fe; + } + + ret = fe_of_property_u32(fe, "dtv_demod", &value); + if (!ret) { + int id = value; + + if ((id < 0) || + (id >= FE_DEV_COUNT) || + !fe_man.dtv_demod[id].drv) { + pr_error("invalid DTV demod device id %d\n", id); + return -1; + } + + fe->dtv_demod = &fe_man.dtv_demod[id]; + fe_man.dtv_demod[id].fe = fe; + } + + ret = fe_of_property_u32(fe, "ts", &value); + if (!ret) { + enum aml_ts_source_t ts = AM_TS_SRC_TS0; + + switch (value) { + case 0: + ts = AM_TS_SRC_TS0; + break; + case 1: + ts = AM_TS_SRC_TS1; + break; + case 2: + ts = AM_TS_SRC_TS2; + break; + default: + break; + } + + fe->ts = ts; + } + + ret = fe_of_property_u32(fe, "dev", &value); + if (!ret) { + int id = value; + + if ((id >= 0) && (id < FE_DEV_COUNT)) + fe->dev_id = id; + else + fe->dev_id = 0; + } + + aml_fe_man_run(fe); + + return 0; +} + +static int aml_fe_man_release(struct aml_fe *fe) +{ + if (fe->init) { + aml_fe_cancel_work(fe); + + if (fe->work_q) + destroy_workqueue(fe->work_q); + + aml_fe_set_sys(fe->fe, SYS_UNDEFINED); + dvb_unregister_frontend(fe->fe); + dvb_frontend_detach(fe->fe); + + fe->tuner = NULL; + fe->atv_demod = NULL; + fe->dtv_demod = NULL; + fe->init = 0; + } + + return 0; +} + +void aml_fe_set_pdata(struct aml_fe_dev *dev, void *pdata) +{ + dev->priv_data = pdata; +} +EXPORT_SYMBOL(aml_fe_set_pdata); + +void *aml_fe_get_pdata(struct aml_fe_dev *dev) +{ + return dev->priv_data; +} +EXPORT_SYMBOL(aml_fe_get_pdata); + +static void aml_fe_do_work(struct work_struct *work) +{ + struct aml_fe *fe; + + fe = container_of(work, struct aml_fe, work); + + if (fe->do_work) + fe->do_work(fe); + + fe->work_running = 0; +} + +void aml_fe_schedule_work(struct aml_fe *fe, void(*func)(struct aml_fe *fe)) +{ + if (fe->work_running) + cancel_work_sync(&fe->work); + + fe->work_running = 1; + fe->do_work = func; + + if (!fe->work_q) { + fe->work_q = create_singlethread_workqueue("amlfe"); + INIT_WORK(&fe->work, aml_fe_do_work); + } + + queue_work(fe->work_q, &fe->work); +} +EXPORT_SYMBOL(aml_fe_schedule_work); + +void aml_fe_cancel_work(struct aml_fe *fe) +{ + if (fe->work_running) { + fe->work_running = 0; + cancel_work_sync(&fe->work); + } + + fe->do_work = NULL; +} +EXPORT_SYMBOL(aml_fe_cancel_work); + + +int aml_fe_work_cancelled(struct aml_fe *fe) +{ + return fe->work_running ? 0 : 1; +} +EXPORT_SYMBOL(aml_fe_work_cancelled); + +int aml_fe_work_sleep(struct aml_fe *fe, unsigned long delay) +{ + wait_event_interruptible_timeout(fe->wait_q, !fe->work_running, delay); + return aml_fe_work_cancelled(fe); +} +EXPORT_SYMBOL(aml_fe_work_sleep); + +static ssize_t tuner_name_show(struct class *cls, struct class_attribute *attr, + char *buf) +{ + size_t len = 0; + struct aml_fe_drv *drv; + unsigned long flags; + + struct aml_fe_drv **list = aml_get_fe_drv_list(AM_DEV_TUNER); + + spin_lock_irqsave(&lock, flags); + for (drv = *list; drv; drv = drv->next) + len += sprintf(buf + len, "%s\n", drv->name); + spin_unlock_irqrestore(&lock, flags); + return len; +} + +static ssize_t atv_demod_name_show(struct class *cls, + struct class_attribute *attr, char *buf) +{ + size_t len = 0; + struct aml_fe_drv *drv; + unsigned long flags; + + struct aml_fe_drv **list = aml_get_fe_drv_list(AM_DEV_ATV_DEMOD); + + spin_lock_irqsave(&lock, flags); + for (drv = *list; drv; drv = drv->next) + len += sprintf(buf + len, "%s\n", drv->name); + spin_unlock_irqrestore(&lock, flags); + return len; +} + +static ssize_t dtv_demod_name_show(struct class *cls, + struct class_attribute *attr, char *buf) +{ + size_t len = 0; + struct aml_fe_drv *drv; + unsigned long flags; + + struct aml_fe_drv **list = aml_get_fe_drv_list(AM_DEV_DTV_DEMOD); + + spin_lock_irqsave(&lock, flags); + for (drv = *list; drv; drv = drv->next) + len += sprintf(buf + len, "%s\n", drv->name); + spin_unlock_irqrestore(&lock, flags); + return len; +} + +static ssize_t setting_show(struct class *cls, struct class_attribute *attr, + char *buf) +{ + int r, total = 0; + int i; + struct aml_fe_man *fm = &fe_man; + + r = sprintf(buf, "tuner:\n"); + buf += r; + total += r; + for (i = 0; i < FE_DEV_COUNT; i++) { + struct aml_fe_dev *dev = &fm->tuner[i]; + + if (dev->drv) { + r = sprintf(buf, "\t%d: %s\n", i, dev->drv->name); + buf += r; + total += r; + } + } + + r = sprintf(buf, "atv_demod:\n"); + buf += r; + total += r; + for (i = 0; i < FE_DEV_COUNT; i++) { + struct aml_fe_dev *dev = &fm->atv_demod[i]; + + if (dev->drv) { + r = sprintf(buf, "\t%d: %s\n", i, dev->drv->name); + buf += r; + total += r; + } + } + + r = sprintf(buf, "dtv_demod:\n"); + buf += r; + total += r; + for (i = 0; i < FE_DEV_COUNT; i++) { + struct aml_fe_dev *dev = &fm->dtv_demod[i]; + + if (dev->drv) { + r = sprintf(buf, "\t%d: %s\n", i, dev->drv->name); + buf += r; + total += r; + } + } + + r = sprintf(buf, "frontend:\n"); + buf += r; + total += r; + for (i = 0; i < FE_DEV_COUNT; i++) { + struct aml_fe *fe = &fm->fe[i]; + + r = sprintf(buf, + "\t%d: %s device: %d ts: %d tuner: %s atv_demod: %s dtv_demod: %s\n", + i, fe->init ? "enabled" : "disabled", fe->dev_id, + fe->ts, fe->tuner ? fe->tuner->drv->name : "none", + fe->atv_demod ? fe->atv_demod->drv->name : "none", + fe->dtv_demod ? fe->dtv_demod->drv->name : "none"); + buf += r; + total += r; + } + + return total; +} + +static void reset_drv(int id, enum aml_fe_dev_type_t type, const char *name) +{ + struct aml_fe_man *fm = &fe_man; + struct aml_fe_drv **list; + struct aml_fe_drv **pdrv; + struct aml_fe_drv *drv; + struct aml_fe_drv *old; + + if ((id < 0) || (id >= FE_DEV_COUNT)) + return; + + if (fm->fe[id].init) { + pr_error("cannot reset driver when the device is inused\n"); + return; + } + + list = aml_get_fe_drv_list(type); + for (drv = *list; drv; drv = drv->next) + if (!strcmp(drv->name, name)) + break; + + switch (type) { + case AM_DEV_TUNER: + pdrv = &fm->tuner[id].drv; + break; + case AM_DEV_ATV_DEMOD: + pdrv = &fm->atv_demod[id].drv; + break; + case AM_DEV_DTV_DEMOD: + pdrv = &fm->dtv_demod[id].drv; + break; + default: + return; + } + + old = *pdrv; + if (old == drv) + return; + + if (old) { + old->ref--; + if (old->owner) + module_put(old->owner); + } + + if (drv) { + drv->ref++; + if (drv->owner) + try_module_get(drv->owner); + } + + *pdrv = drv; +} + +static ssize_t setting_store(struct class *class, struct class_attribute *attr, + const char *buf, size_t size) +{ + struct aml_fe_man *fm = &fe_man; + int id, val; + char dev_name[32]; + unsigned long flags; + + spin_lock_irqsave(&lock, flags); + + if (sscanf(buf, "tuner %i driver %s", &id, dev_name) == 2) { + reset_drv(id, AM_DEV_TUNER, dev_name); + } else if (sscanf(buf, "atv_demod %i driver %s", &id, dev_name) == 2) { + reset_drv(id, AM_DEV_ATV_DEMOD, dev_name); + } else if (sscanf(buf, "dtv_demod %i driver %s", &id, dev_name) == 2) { + reset_drv(id, AM_DEV_DTV_DEMOD, dev_name); + } else if (sscanf(buf, "frontend %i device %i", &id, &val) == 2) { + if ((id >= 0) && (id < FE_DEV_COUNT)) + fm->fe[id].dev_id = val; + } else if (sscanf(buf, "frontend %i ts %i", &id, &val) == 2) { + if ((id >= 0) && (id < FE_DEV_COUNT)) + fm->fe[id].ts = val; + } else if (sscanf(buf, "frontend %i tuner %i", &id, &val) == 2) { + if ((id >= 0) && (id < FE_DEV_COUNT) && (val >= 0) + && (val < FE_DEV_COUNT) && fm->tuner[val].drv) + fm->fe[id].tuner = &fm->tuner[val]; + } else if (sscanf(buf, "frontend %i atv_demod %i", &id, &val) == 2) { + if ((id >= 0) && (id < FE_DEV_COUNT) && (val >= 0) + && (val < FE_DEV_COUNT) && fm->atv_demod[val].drv) + fm->fe[id].atv_demod = &fm->atv_demod[val]; + } else if (sscanf(buf, "frontend %i dtv_demod %i", &id, &val) == 2) { + if ((id >= 0) && (id < FE_DEV_COUNT) && (val >= 0) + && (val < FE_DEV_COUNT) && fm->dtv_demod[val].drv) + fm->fe[id].dtv_demod = &fm->dtv_demod[val]; + } + + spin_unlock_irqrestore(&lock, flags); + + if (sscanf(buf, "enable %i", &id) == 1) { + if ((id >= 0) && (id < FE_DEV_COUNT)) + aml_fe_man_run(&fm->fe[id]); + } else if (sscanf(buf, "disable %i", &id) == 1) { + if ((id >= 0) && (id < FE_DEV_COUNT)) + aml_fe_man_release(&fm->fe[id]); + } else if (strstr(buf, "autoload")) { + for (id = 0; id < FE_DEV_COUNT; id++) { + aml_fe_dev_init(fm, AM_DEV_TUNER, + &fm->tuner[id], id); + aml_fe_dev_init(fm, AM_DEV_ATV_DEMOD, + &fm->atv_demod[id], id); + aml_fe_dev_init(fm, AM_DEV_DTV_DEMOD, + &fm->dtv_demod[id], id); + } + + for (id = 0; id < FE_DEV_COUNT; id++) + aml_fe_man_init(fm, &fm->fe[id], id); + } else if (strstr(buf, "disableall")) { + for (id = 0; id < FE_DEV_COUNT; id++) + aml_fe_man_release(&fm->fe[id]); + + for (id = 0; id < FE_DEV_COUNT; id++) { + aml_fe_dev_release(&fm->dtv_demod[id]); + aml_fe_dev_release(&fm->atv_demod[id]); + aml_fe_dev_release(&fm->tuner[id]); + } + } + + return size; +} + +static ssize_t aml_fe_show_suspended_flag(struct class *class, + struct class_attribute *attr, + char *buf) +{ + ssize_t ret = 0; + + ret = sprintf(buf, "%ld\n", aml_fe_suspended); + + return ret; +} + +static ssize_t aml_fe_store_suspended_flag(struct class *class, + struct class_attribute *attr, + const char *buf, size_t size) +{ + /*aml_fe_suspended = simple_strtol(buf, 0, 0); */ + int ret = kstrtol(buf, 0, &aml_fe_suspended); + + if (ret) + return ret; + return size; +} + +static struct class_attribute aml_fe_cls_attrs[] = { + __ATTR(tuner_name, + 0644, + tuner_name_show, NULL), + __ATTR(atv_demod_name, + 0644, + atv_demod_name_show, NULL), + __ATTR(dtv_demod_name, + 0644, + dtv_demod_name_show, NULL), + __ATTR(setting, + 0644, + setting_show, setting_store), + __ATTR(aml_fe_suspended_flag, + 0644, + aml_fe_show_suspended_flag, + aml_fe_store_suspended_flag), + __ATTR_NULL +}; + +static struct class aml_fe_class = { + .name = "amlfe", + .class_attrs = aml_fe_cls_attrs, +}; + +static int aml_fe_probe(struct platform_device *pdev) +{ + struct aml_dvb *dvb = aml_get_dvb_device(); + int i; + + fe_man.dvb = dvb; + fe_man.pdev = pdev; + + platform_set_drvdata(pdev, &fe_man); + + for (i = 0; i < FE_DEV_COUNT; i++) { + if (aml_fe_dev_init(&fe_man, + AM_DEV_TUNER, + &fe_man.tuner[i], i) < 0) + goto probe_end; + + if (aml_fe_dev_init(&fe_man, + AM_DEV_ATV_DEMOD, + &fe_man.atv_demod[i], i) < 0) + goto probe_end; + + if (aml_fe_dev_init(&fe_man, + AM_DEV_DTV_DEMOD, + &fe_man.dtv_demod[i], i) < 0) + goto probe_end; + } + + for (i = 0; i < FE_DEV_COUNT; i++) { + if (aml_fe_man_init(&fe_man, &fe_man.fe[i], i) < 0) + goto probe_end; + } + + probe_end: + + fe_man.pinctrl = devm_pinctrl_get_select_default(&pdev->dev); + + if (class_register(&aml_fe_class) < 0) + pr_error("[aml_fe..] register class error\n"); + + pr_dbg("[aml_fe..] probe ok.\n"); + + return 0; +} + +static int aml_fe_remove(struct platform_device *pdev) +{ + struct aml_fe_man *fe_man = platform_get_drvdata(pdev); + int i; + + if (fe_man) { + platform_set_drvdata(pdev, NULL); + + for (i = 0; i < FE_DEV_COUNT; i++) + aml_fe_man_release(&fe_man->fe[i]); + for (i = 0; i < FE_DEV_COUNT; i++) { + aml_fe_dev_release(&fe_man->dtv_demod[i]); + aml_fe_dev_release(&fe_man->atv_demod[i]); + aml_fe_dev_release(&fe_man->tuner[i]); + } + + if (fe_man->pinctrl) + devm_pinctrl_put(fe_man->pinctrl); + } + + class_unregister(&aml_fe_class); + + return 0; +} + +static int aml_fe_suspend(struct platform_device *dev, pm_message_t state) +{ + int i; + + for (i = 0; i < FE_DEV_COUNT; i++) { + struct aml_fe *fe = &fe_man.fe[i]; + + if (fe->tuner && fe->tuner->drv->suspend) + fe->tuner->drv->suspend(fe->tuner); + + if (fe->atv_demod && fe->atv_demod->drv->suspend) + fe->atv_demod->drv->suspend(fe->atv_demod); + + if (fe->dtv_demod && fe->dtv_demod->drv->suspend) + fe->dtv_demod->drv->suspend(fe->dtv_demod); + } + + aml_fe_suspended = 1; + + return 0; +} + +static int aml_fe_resume(struct platform_device *dev) +{ + int i; + + aml_fe_suspended = 0; + + for (i = 0; i < FE_DEV_COUNT; i++) { + struct aml_fe *fe = &fe_man.fe[i]; + + if (fe->tuner && fe->tuner->drv->resume) + fe->tuner->drv->resume(fe->tuner); + + if (fe->atv_demod && fe->atv_demod->drv->resume) + fe->atv_demod->drv->resume(fe->atv_demod); + + if (fe->dtv_demod && fe->dtv_demod->drv->resume) + fe->dtv_demod->drv->resume(fe->dtv_demod); + } + + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id aml_fe_dt_match[] = { + { + .compatible = "amlogic, dvbfe", + }, + {}, +}; +#endif /*CONFIG_OF */ + +static struct platform_driver aml_fe_driver = { + .probe = aml_fe_probe, + .remove = aml_fe_remove, + .suspend = aml_fe_suspend, + .resume = aml_fe_resume, + .driver = { + .name = "amlogic-dvb-fe", + .owner = THIS_MODULE, +#ifdef CONFIG_OF + .of_match_table = aml_fe_dt_match, +#endif + } +}; + +static int __init aml_fe_init(void) +{ + return platform_driver_register(&aml_fe_driver); +} + +static void __exit aml_fe_exit(void) +{ + platform_driver_unregister(&aml_fe_driver); +} + +module_init(aml_fe_init); +module_exit(aml_fe_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("amlogic frontend driver"); +MODULE_AUTHOR("L+#= +0=1"); + diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/aml_fe.h b/drivers/amlogic/media_modules/stream_input/tv_frontend/aml_fe.h new file mode 100644 index 000000000000..c32c3801617f --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/aml_fe.h @@ -0,0 +1,189 @@ +#ifndef _AML_FE_H_ +#define _AML_FE_H_ + + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_HAS_EARLYSUSPEND +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include "../parser/hw_demux/aml_dvb.h" + +enum aml_tuner_type_t { + AM_TUNER_SI2176 = 1, + AM_TUNER_SI2196 = 2, + AM_TUNER_FQ1216 = 3, + AM_TUNER_HTM = 4, + AM_TUNER_CTC703 = 5, + AM_TUNER_SI2177 = 6, + AM_TUNER_R840 = 7, + AM_TUNER_SI2157 = 8, + AM_TUNER_SI2151 = 9, + AM_TUNER_MXL661 = 10 +}; + +enum aml_atv_demod_type_t { + AM_ATV_DEMOD_SI2176 = 1, + AM_ATV_DEMOD_SI2196 = 2, + AM_ATV_DEMOD_FQ1216 = 3, + AM_ATV_DEMOD_HTM = 4, + AM_ATV_DEMOD_CTC703 = 5, + AM_ATV_DEMOD_SI2177 = 6, + AM_ATV_DEMOD_AML = 7, + AM_ATV_DEMOD_R840 = 8 +}; + +enum aml_dtv_demod_type_t { + AM_DTV_DEMOD_M1 = 0, + AM_DTV_DEMOD_SI2176 = 1, + AM_DTV_DEMOD_MXL101 = 2, + AM_DTV_DEMOD_SI2196 = 3, + AM_DTV_DEMOD_AVL6211 = 4, + AM_DTV_DEMOD_SI2168 = 5, + AM_DTV_DEMOD_ITE9133 = 6, + AM_DTV_DEMOD_ITE9173 = 7, + AM_DTV_DEMOD_DIB8096 = 8, + AM_DTV_DEMOD_ATBM8869 = 9, + AM_DTV_DEMOD_MXL241 = 10, + AM_DTV_DEMOD_AVL68xx = 11, + AM_DTV_DEMOD_MXL683 = 12, + AM_DTV_DEMOD_ATBM8881 = 13 +}; + +enum aml_fe_dev_type_t { + AM_DEV_TUNER, + AM_DEV_ATV_DEMOD, + AM_DEV_DTV_DEMOD +}; + +struct aml_fe_dev; +struct aml_fe_man; +struct aml_fe; + +struct aml_fe_drv { + struct module *owner; + struct aml_fe_drv *next; + enum aml_tuner_type_t id; + char *name; + int (*init)(struct aml_fe_dev *dev); + int (*release)(struct aml_fe_dev *dev); + int (*resume)(struct aml_fe_dev *dev); + int (*suspend)(struct aml_fe_dev *dev); + int (*support)(struct aml_fe_dev *dev, enum fe_delivery_system sys); + int (*get_ops)(struct aml_fe_dev *dev, enum fe_delivery_system sys, + struct dvb_frontend_ops *ops); + int (*init_sys)(struct aml_fe_dev *dev, enum fe_delivery_system sys); + int (*release_sys)(struct aml_fe_dev *dev, enum fe_delivery_system sys); + int (*start_blind_scan)(struct aml_fe_dev *dev); + int (*stop_blind_scan)(struct aml_fe_dev *dev); + int ref; +}; + +struct aml_fe_dev { + /*point to parent aml_fe */ + enum aml_fe_dev_type_t type; + int dev_id; + struct aml_fe *fe; + struct aml_fe_man *man; + struct aml_fe_drv *drv; + void *priv_data; + /*i2c and reset gpio for all demod and tune*/ + int i2c_adap_id; + int i2c_addr; + struct i2c_adapter *i2c_adap; + int reset_gpio; + int reset_value; +}; + +struct aml_fe { + struct dvb_frontend *fe; + struct aml_fe_man *man; +#ifdef CONFIG_HAS_EARLYSUSPEND + struct early_suspend es; +#endif /*CONFIG_HAS_EARLYSUSPEND */ + spinlock_t slock; + int init; + int dev_id; + enum fe_delivery_system sys; + int sub_sys; +/*used to identify T T2 OR C-A C-B C-C,S S2,ISDBT ISDBS ISDBC*/ + enum aml_ts_source_t ts; + struct aml_fe_dev *tuner; + struct aml_fe_dev *atv_demod; + struct aml_fe_dev *dtv_demod; + struct workqueue_struct *work_q; + wait_queue_head_t wait_q; + struct work_struct work; + int work_running; + struct dvbsx_blindscanpara blind_scan_para; + + /*Driver's work function.*/ + void (*do_work)(struct aml_fe *fe); + /*Driver's property function.*/ + int (*get_property)(struct dvb_frontend *fe, struct dtv_property *tvp); + int (*set_property)(struct dvb_frontend *fe, struct dtv_property *tvp); +}; + +struct aml_fe_man { + struct aml_dvb *dvb; + struct aml_fe fe[FE_DEV_COUNT]; + struct aml_fe_dev tuner[FE_DEV_COUNT]; + struct aml_fe_dev atv_demod[FE_DEV_COUNT]; + struct aml_fe_dev dtv_demod[FE_DEV_COUNT]; + struct dvb_frontend dev[FE_DEV_COUNT]; + struct pinctrl *pinctrl; + struct platform_device *pdev; +}; + +extern int aml_register_fe_drv(enum aml_fe_dev_type_t type, + struct aml_fe_drv *drv); +extern int aml_unregister_fe_drv(enum aml_fe_dev_type_t type, + struct aml_fe_drv *drv); + +extern int aml_fe_of_property_string(struct aml_fe_dev *dev, + const char *name, const char **str); +extern int aml_fe_of_property_u32(struct aml_fe_dev *dev, + const char *name, u32 *v); + +extern void aml_fe_set_pdata(struct aml_fe_dev *dev, void *pdata); +extern void *aml_fe_get_pdata(struct aml_fe_dev *dev); + +extern void aml_fe_schedule_work(struct aml_fe *fe, + void (*func)(struct aml_fe *fe)); +extern void aml_fe_cancel_work(struct aml_fe *fe); +extern int aml_fe_work_cancelled(struct aml_fe *fe); +extern int aml_fe_work_sleep(struct aml_fe *fe, unsigned long delay); + +#endif /*_AML_FE_H_*/ diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/atv_demod/atvdemod_frontend.c b/drivers/amlogic/media_modules/stream_input/tv_frontend/atv_demod/atvdemod_frontend.c new file mode 100644 index 000000000000..964bc42c224e --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/atv_demod/atvdemod_frontend.c @@ -0,0 +1,791 @@ +/* + * Silicon labs atvdemod Device Driver + * + * Author: dezhi.kong + * + * + * Copyright (C) 2014 Amlogic Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* Standard Liniux Headers */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Amlogic Headers */ + +/* Local Headers */ +#include "atvdemod_func.h" +#include "../aml_fe.h" +#include +#include + +#define ATVDEMOD_DEVICE_NAME "amlatvdemod" +#define ATVDEMOD_DRIVER_NAME "amlatvdemod" +#define ATVDEMOD_MODULE_NAME "amlatvdemod" +#define ATVDEMOD_CLASS_NAME "amlatvdemod" + +struct amlatvdemod_device_s *amlatvdemod_devp; +#define AMLATVDEMOD_VER "Ref.2015/09/01a" + +static int afc_wave_cnt; +static int last_frq, last_std; + +unsigned int reg_23cf = 0x88188832; /*IIR filter*/ +module_param(reg_23cf, uint, 0664); +MODULE_PARM_DESC(reg_23cf, "\n reg_23cf\n"); + +unsigned int atvdemod_scan_mode; /*IIR filter*/ +module_param(atvdemod_scan_mode, uint, 0664); +MODULE_PARM_DESC(atvdemod_scan_mode, "\n atvdemod_scan_mode\n"); + +/* used for resume */ +#define ATVDEMOD_STATE_IDEL 0 +#define ATVDEMOD_STATE_WORK 1 +#define ATVDEMOD_STATE_SLEEP 2 +static int atvdemod_state = ATVDEMOD_STATE_IDEL; + +int is_atvdemod_scan_mode(void) +{ + return atvdemod_scan_mode; +} +EXPORT_SYMBOL(is_atvdemod_scan_mode); + +static int aml_atvdemod_enter_mode(struct aml_fe *fe, int mode); +/*static void sound_store(const char *buff, v4l2_std_id *std);*/ +static ssize_t aml_atvdemod_store(struct class *cls, + struct class_attribute *attr, const char *buf, + size_t count) +{ + int n = 0; + unsigned int ret = 0; + char *buf_orig, *ps, *token; + char *parm[4]; + unsigned int data_snr[128]; + unsigned int data_snr_avg; + int data_afc, block_addr, block_reg, block_val = 0; + int i, val = 0; + unsigned long tmp = 0; + struct aml_fe *atvdemod_fe = NULL; + + buf_orig = kstrdup(buf, GFP_KERNEL); + ps = buf_orig; + block_addr = 0; + block_reg = 0; + while (1) { + token = strsep(&ps, "\n"); + if (token == NULL) + break; + if (*token == '\0') + continue; + parm[n++] = token; + } + if (!strncmp(parm[0], "init", strlen("init"))) { + ret = aml_atvdemod_enter_mode(atvdemod_fe, 0); + if (ret) + pr_info("[tuner..] atv_restart error.\n"); + } else if (!strcmp(parm[0], "tune")) { + /* val = simple_strtol(parm[1], NULL, 10); */ + } else if (!strcmp(parm[0], "set")) { + if (!strncmp(parm[1], "avout_gain", strlen("avout_gain"))) { + if (kstrtoul(buf+strlen("avout_offset")+1, 10, + &tmp) == 0) + val = tmp; + atv_dmd_wr_byte(0x0c, 0x01, val&0xff); + } else if (!strncmp(parm[1], "avout_offset", + strlen("avout_offset"))) { + if (kstrtoul(buf+strlen("avout_offset")+1, 10, + &tmp) == 0) + val = tmp; + atv_dmd_wr_byte(0x0c, 0x04, val&0xff); + } else if (!strncmp(parm[1], "atv_gain", strlen("atv_gain"))) { + if (kstrtoul(buf+strlen("atv_gain")+1, 10, &tmp) == 0) + val = tmp; + atv_dmd_wr_byte(0x19, 0x01, val&0xff); + } else if (!strncmp(parm[1], "atv_offset", + strlen("atv_offset"))) { + if (kstrtoul(buf+strlen("atv_offset")+1, 10, + &tmp) == 0) + val = tmp; + atv_dmd_wr_byte(0x19, 0x04, val&0xff); + } + } else if (!strcmp(parm[0], "get")) { + if (!strncmp(parm[1], "avout_gain", strlen("avout_gain"))) { + val = atv_dmd_rd_byte(0x0c, 0x01); + pr_dbg("avout_gain:0x%x\n", val); + } else if (!strncmp(parm[1], "avout_offset", + strlen("avout_offset"))) { + val = atv_dmd_rd_byte(0x0c, 0x04); + pr_dbg("avout_offset:0x%x\n", val); + } else if (!strncmp(parm[1], "atv_gain", strlen("atv_gain"))) { + val = atv_dmd_rd_byte(0x19, 0x01); + pr_dbg("atv_gain:0x%x\n", val); + } else if (!strncmp(parm[1], "atv_offset", + strlen("atv_offset"))) { + val = atv_dmd_rd_byte(0x19, 0x04); + pr_dbg("atv_offset:0x%x\n", val); + } + } else if (!strncmp(parm[0], "snr_hist", strlen("snr_hist"))) { + data_snr_avg = 0; + for (i = 0; i < 128; i++) { + data_snr[i] = + (atv_dmd_rd_long(APB_BLOCK_ADDR_VDAGC, 0x50) >> 8); + usleep_range(50*1000, 50*1000+100); + data_snr_avg += data_snr[i]; + } + data_snr_avg = data_snr_avg / 128; + pr_dbg("**********snr_hist_128avg:0x%x(%d)*********\n", + data_snr_avg, data_snr_avg); + } else if (!strncmp(parm[0], "afc_info", strlen("afc_info"))) { + data_afc = retrieve_vpll_carrier_afc(); + pr_dbg("[amlatvdemod..]afc %d Khz.\n", data_afc); + } else if (!strncmp(parm[0], "ver_info", strlen("ver_info"))) { + pr_dbg("[amlatvdemod..]aml_atvdemod_ver %s.\n", + AMLATVDEMOD_VER); + } else if (!strncmp(parm[0], "audio_autodet", + strlen("audio_autodet"))) { + aml_audiomode_autodet(NULL); + } else if (!strncmp(parm[0], "overmodule_det", + strlen("overmodule_det"))) { + /* unsigned long over_threshold, */ + /* int det_mode = auto_det_mode; */ + aml_atvdemod_overmodule_det(); + } else if (!strncmp(parm[0], "audio_gain_set", + strlen("audio_gain_set"))) { + if (kstrtoul(buf+strlen("audio_gain_set")+1, 16, &tmp) == 0) + val = tmp; + aml_audio_valume_gain_set(val); + pr_dbg("audio_gain_set : %d\n", val); + } else if (!strncmp(parm[0], "audio_gain_get", + strlen("audio_gain_get"))) { + val = aml_audio_valume_gain_get(); + pr_dbg("audio_gain_get : %d\n", val); + } else if (!strncmp(parm[0], "fix_pwm_adj", strlen("fix_pwm_adj"))) { + if (kstrtoul(parm[1], 10, &tmp) == 0) { + val = tmp; + aml_fix_PWM_adjust(val); + } + } else if (!strncmp(parm[0], "rs", strlen("rs"))) { + if (kstrtoul(parm[1], 16, &tmp) == 0) + block_addr = tmp; + if (kstrtoul(parm[2], 16, &tmp) == 0) + block_reg = tmp; + if (block_addr < APB_BLOCK_ADDR_TOP) + block_val = atv_dmd_rd_long(block_addr, block_reg); + pr_info("rs block_addr:0x%x,block_reg:0x%x,block_val:0x%x\n", + block_addr, block_reg, block_val); + } else if (!strncmp(parm[0], "ws", strlen("ws"))) { + if (kstrtoul(parm[1], 16, &tmp) == 0) + block_addr = tmp; + if (kstrtoul(parm[2], 16, &tmp) == 0) + block_reg = tmp; + if (kstrtoul(parm[3], 16, &tmp) == 0) + block_val = tmp; + if (block_addr < APB_BLOCK_ADDR_TOP) + atv_dmd_wr_long(block_addr, block_reg, block_val); + pr_info("ws block_addr:0x%x,block_reg:0x%x,block_val:0x%x\n", + block_addr, block_reg, block_val); + block_val = atv_dmd_rd_long(block_addr, block_reg); + pr_info("readback_val:0x%x\n", block_val); + } else if (!strncmp(parm[0], "pin_mux", strlen("pin_mux"))) { + amlatvdemod_devp->pin = + devm_pinctrl_get_select(amlatvdemod_devp->dev, + amlatvdemod_devp->pin_name); + pr_dbg("atvdemod agc pinmux name:%s\n", + amlatvdemod_devp->pin_name); + } else if (!strncmp(parm[0], "snr_cur", strlen("snr_cur"))) { + data_snr_avg = aml_atvdemod_get_snr_ex(); + pr_dbg("**********snr_cur:%d*********\n", data_snr_avg); + } else + pr_dbg("invalid command\n"); + kfree(buf_orig); + return count; +} + +static ssize_t aml_atvdemod_show(struct class *cls, + struct class_attribute *attr, char *buff) +{ + pr_dbg("\n usage:\n"); + pr_dbg("[get soft version] echo ver_info > /sys/class/amlatvdemod/atvdemod_debug\n"); + pr_dbg("[get afc value] echo afc_info > /sys/class/amlatvdemod/atvdemod_debug\n"); + pr_dbg("[reinit atvdemod] echo init > /sys/class/amlatvdemod/atvdemod_debug\n"); + pr_dbg("[get av-out-gain/av-out-offset/atv-gain/atv-offset]:\n" + "echo get av_gain/av_offset/atv_gain/atv_offset > /sys/class/amlatvdemod/atvdemod_debug\n"); + pr_dbg("[set av-out-gain/av-out-offset/atv-gain/atv-offset]:\n" + "echo set av_gain/av_offset/atv_gain/atv_offset val(0~255) > /sys/class/amlatvdemod/atvdemod_debug\n"); + return 0; +} +static CLASS_ATTR(atvdemod_debug, 0644, aml_atvdemod_show, aml_atvdemod_store); + +void aml_atvdemod_set_frequency(unsigned int freq) +{ +} + +/*static void aml_atvdemod_set_std(void);*/ + +/*try audmode B,CH,I,DK,return the sound level*/ +/*static unsigned char set_video_audio_mode(unsigned char color, + *unsigned char audmode); + */ +/*static void aml_atvdemod_get_status(struct dvb_frontend *fe, + *void *stat); + */ +/*static void aaaml_atvdemod_get_pll_status(struct dvb_frontend *fe, + *void *stat); + */ + +static int aml_atvdemod_fe_init(struct aml_fe_dev *dev) +{ + + int error_code = 0; + + if (!dev) { + pr_dbg("[amlatvdemod..]%s: null pointer error.\n", __func__); + return -1; + } + return error_code; +} + +static int aml_atvdemod_enter_mode(struct aml_fe *fe, int mode) +{ + int err_code; + + if (amlatvdemod_devp->pin_name != NULL) + amlatvdemod_devp->pin = + devm_pinctrl_get_select(amlatvdemod_devp->dev, + amlatvdemod_devp->pin_name); + /* printk("\n%s: set atvdemod pll...\n",__func__); */ + adc_set_pll_cntl(1, 0x1); + atvdemod_clk_init(); + err_code = atvdemod_init(); + if (err_code) { + pr_dbg("[amlatvdemod..]%s init atvdemod error.\n", __func__); + return err_code; + } + + set_aft_thread_enable(1); + atvdemod_state = ATVDEMOD_STATE_WORK; + return 0; +} + +static int aml_atvdemod_leave_mode(struct aml_fe *fe, int mode) +{ + set_aft_thread_enable(0); + atvdemod_uninit(); + if (amlatvdemod_devp->pin != NULL) { + devm_pinctrl_put(amlatvdemod_devp->pin); + amlatvdemod_devp->pin = NULL; + } + /* reset adc pll flag */ + /* printk("\n%s: init atvdemod flag...\n",__func__); */ + adc_set_pll_cntl(0, 0x1); + atvdemod_state = ATVDEMOD_STATE_IDEL; + return 0; +} + +static int aml_atvdemod_suspend(struct aml_fe_dev *dev) +{ + pr_info("%s\n", __func__); + if (atvdemod_state != ATVDEMOD_STATE_IDEL) { + aml_atvdemod_leave_mode(NULL, 0); + atvdemod_state = ATVDEMOD_STATE_SLEEP; + } + return 0; +} + +static int aml_atvdemod_resume(struct aml_fe_dev *dev) +{ + pr_info("%s\n", __func__); + if (atvdemod_state == ATVDEMOD_STATE_SLEEP) + aml_atvdemod_enter_mode(NULL, 0); + return 0; +} + +/* + *static int aml_atvdemod_get_afc(struct dvb_frontend *fe,int *afc) + *{ + * return 0; + *} + */ + +/*ret:5~100;the val is bigger,the signal is better*/ +int aml_atvdemod_get_snr(struct dvb_frontend *fe) +{ +#if 1 + return get_atvdemod_snr_val(); +#else + unsigned int snr_val; + int ret; + + snr_val = atv_dmd_rd_long(APB_BLOCK_ADDR_VDAGC, 0x50) >> 8; + /* snr_val:900000~0xffffff,ret:5~15 */ + if (snr_val > 900000) + ret = 15 - (snr_val - 900000)*10/(0xffffff - 900000); + /* snr_val:158000~900000,ret:15~30 */ + else if (snr_val > 158000) + ret = 30 - (snr_val - 158000)*15/(900000 - 158000); + /* snr_val:31600~158000,ret:30~50 */ + else if (snr_val > 31600) + ret = 50 - (snr_val - 31600)*20/(158000 - 31600); + /* snr_val:316~31600,ret:50~80 */ + else if (snr_val > 316) + ret = 80 - (snr_val - 316)*30/(31600 - 316); + /* snr_val:0~316,ret:80~100 */ + else + ret = 100 - (316 - snr_val)*20/316; + return ret; +#endif +} +EXPORT_SYMBOL(aml_atvdemod_get_snr); + +int aml_atvdemod_get_snr_ex(void) +{ +#if 1 + return get_atvdemod_snr_val(); +#else + unsigned int snr_val; + int ret; + + snr_val = atv_dmd_rd_long(APB_BLOCK_ADDR_VDAGC, 0x50) >> 8; + /* snr_val:900000~0xffffff,ret:5~15 */ + if (snr_val > 900000) + ret = 15 - (snr_val - 900000)*10/(0xffffff - 900000); + /* snr_val:158000~900000,ret:15~30 */ + else if (snr_val > 158000) + ret = 30 - (snr_val - 158000)*15/(900000 - 158000); + /* snr_val:31600~158000,ret:30~50 */ + else if (snr_val > 31600) + ret = 50 - (snr_val - 31600)*20/(158000 - 31600); + /* snr_val:316~31600,ret:50~80 */ + else if (snr_val > 316) + ret = 80 - (snr_val - 316)*30/(31600 - 316); + /* snr_val:0~316,ret:80~100 */ + else + ret = 100 - (316 - snr_val)*20/316; + return ret; +#endif +} +EXPORT_SYMBOL(aml_atvdemod_get_snr_ex); + +/*tuner lock status & demod lock status should be same in silicon tuner*/ +static int aml_atvdemod_get_status(struct dvb_frontend *fe, void *stat) +{ + int video_lock; + fe_status_t *status = (fe_status_t *) stat; + + retrieve_video_lock(&video_lock); + if ((video_lock & 0x1) == 0) { + /* *status = FE_HAS_LOCK;*/ + *status = FE_TIMEDOUT; + pr_info("video lock:locked\n"); + } else { + pr_info("video lock:unlocked\n"); + *status = FE_TIMEDOUT; + /* *status = FE_HAS_LOCK;*/ + } + return 0; +} + +/*tuner lock status & demod lock status should be same in silicon tuner*/ +/* force return lock, for atvdemo status not sure */ +static void aml_atvdemod_get_pll_status(struct dvb_frontend *fe, void *stat) +{ + int vpll_lock; + fe_status_t *status = (fe_status_t *) stat; + + retrieve_vpll_carrier_lock(&vpll_lock); + if ((vpll_lock&0x1) == 0) { + *status = FE_HAS_LOCK; + pr_info("visual carrier lock:locked\n"); + } else { + pr_info("visual carrier lock:unlocked\n"); + *status = FE_TIMEDOUT; + /* *status = FE_HAS_LOCK;*/ + } +} + +static int aml_atvdemod_get_atv_status(struct dvb_frontend *fe, + struct atv_status_s *atv_status) +{ + int vpll_lock = 0, line_lock = 0; + int try_std = 1; + int loop_cnt = 5; + int cnt = 10; + int try_std_cnt = 0; + static int last_report_freq; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + + while (fe && atv_status && loop_cnt--) { + atv_status->afc = retrieve_vpll_carrier_afc(); + retrieve_vpll_carrier_lock(&vpll_lock); + line_lock = atv_dmd_rd_byte(APB_BLOCK_ADDR_VDAGC, 0x4f)&0x10; + if ((vpll_lock&0x1) == 0 || line_lock == 0) { + atv_status->atv_lock = 1; + try_std_cnt = 2; + while (try_std_cnt--) { + atv_status->afc = retrieve_vpll_carrier_afc(); + if (atv_status->afc > 1500 + && atvdemod_scan_mode) { + if ((c->analog.std & 0xff000000) + != V4L2_COLOR_STD_PAL) { + c->analog.std = + V4L2_COLOR_STD_PAL + | V4L2_STD_PAL_BG; + c->frequency += 1; + fe->ops.set_frontend(fe); + msleep(20); + } else { + c->analog.std = + V4L2_COLOR_STD_NTSC + | V4L2_STD_NTSC_M; + c->frequency += 1; + fe->ops.set_frontend(fe); + usleep_range(20*1000, + 20*1000+100); + } + atv_status->afc = + retrieve_vpll_carrier_afc(); + + cnt = 4; + while (cnt--) { + if (atv_status->afc < 1500) + break; + atv_status->afc = + retrieve_vpll_carrier_afc(); + usleep_range(5*1000, 5*1000+100); + } + if (atv_status->afc < 1500) + break; + } + } + + if (atv_status->afc > 4000 && !atvdemod_scan_mode) + atv_status->atv_lock = 0; + + if (last_report_freq != c->frequency) + last_report_freq = c->frequency; + + if (atvdemod_scan_mode) + pr_err("%s,lock freq:%d, afc:%d\n", __func__, + c->frequency, atv_status->afc); + break; + + } else if (try_std%3 == 0 && atvdemod_scan_mode) { + if ((c->analog.std & 0xff000000) + != V4L2_COLOR_STD_PAL) { + c->analog.std = + V4L2_COLOR_STD_PAL | V4L2_STD_PAL_DK; + } + if (abs(c->frequency - last_report_freq) > 1000000) { + c->frequency -= 500000; + pr_err("@@@ %s freq:%d unlock,try back 0.5M\n", + __func__, c->frequency); + } else + c->frequency += 1; + fe->ops.set_frontend(fe); + usleep_range(10*1000, 10*1000+100); + } + if (atvdemod_scan_mode) + pr_err("@@@ %s freq:%d unlock, read lock again\n", + __func__, c->frequency); + if (atvdemod_scan_mode == 0) + usleep_range(10*1000, 10*1000+100); + else + usleep_range(1000, 1200); + + atv_status->atv_lock = 0; + try_std++; + } + if (atvdemod_scan_mode == 0) { + if (abs(atv_status->afc) < 20) + afc_wave_cnt = 0; + if (500*1000 > abs(last_frq - c->frequency) + && 20 < abs(atv_status->afc) + && 200 > abs(atv_status->afc)) { + afc_wave_cnt++; + pr_err("%s play mode,afc_wave_cnt:%d\n", + __func__, afc_wave_cnt); + if (afc_wave_cnt < 20) { + atv_status->afc = 0; + pr_err("%s, afc is wave,ignore\n", __func__); + } + } + } + return 0; +} + +void aml_atvdemod_set_params(struct dvb_frontend *fe, + struct analog_parameters *p) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + + if (fe->ops.info.type == FE_ANALOG) { + if ((p->std != amlatvdemod_devp->parm.std) || + (p->tuner_id == AM_TUNER_R840) || + (p->tuner_id == AM_TUNER_SI2151) || + (p->tuner_id == AM_TUNER_MXL661)) { + amlatvdemod_devp->parm.std = p->std; + amlatvdemod_devp->parm.if_freq = p->if_freq; + amlatvdemod_devp->parm.if_inv = p->if_inv; + amlatvdemod_devp->parm.tuner_id = p->tuner_id; + /* open AGC if needed */ + if (amlatvdemod_devp->pin != NULL) + devm_pinctrl_put(amlatvdemod_devp->pin); + if (amlatvdemod_devp->pin_name) + amlatvdemod_devp->pin = + devm_pinctrl_get_select(amlatvdemod_devp->dev, + amlatvdemod_devp->pin_name); + atv_dmd_set_std(); + last_frq = c->frequency; + last_std = c->analog.std; + pr_info("[amlatvdemod..]%s set std color %s, audio type %s.\n", + __func__, + v4l2_std_to_str(0xff000000&amlatvdemod_devp->parm.std), + v4l2_std_to_str(0xffffff&amlatvdemod_devp->parm.std)); + pr_info("[amlatvdemod..]%s set if_freq 0x%x, if_inv 0x%x.\n", + __func__, amlatvdemod_devp->parm.if_freq, + amlatvdemod_devp->parm.if_inv); + } + } +} +static int aml_atvdemod_get_afc(struct dvb_frontend *fe, s32 *afc) +{ + *afc = retrieve_vpll_carrier_afc(); + pr_info("[amlatvdemod..]%s afc %d.\n", __func__, *afc); + return 0; +} + +static int aml_atvdemod_get_ops(struct aml_fe_dev *dev, int mode, void *ops) +{ + struct analog_demod_ops *aml_analog_ops = + (struct analog_demod_ops *)ops; + if (!ops) { + pr_dbg("[amlatvdemod..]%s null pointer error.\n", __func__); + return -1; + } + aml_analog_ops->get_afc = aml_atvdemod_get_afc; + aml_analog_ops->get_snr = aml_atvdemod_get_snr; + aml_analog_ops->get_status = aml_atvdemod_get_status; + aml_analog_ops->set_params = aml_atvdemod_set_params; + aml_analog_ops->get_pll_status = aml_atvdemod_get_pll_status; + aml_analog_ops->get_atv_status = aml_atvdemod_get_atv_status; + return 0; +} + +static struct aml_fe_drv aml_atvdemod_drv = { + .name = "aml_atv_demod", + .capability = AM_FE_ANALOG, + .id = AM_ATV_DEMOD_AML, + .get_ops = aml_atvdemod_get_ops, + .init = aml_atvdemod_fe_init, + .enter_mode = aml_atvdemod_enter_mode, + .leave_mode = aml_atvdemod_leave_mode, + .suspend = aml_atvdemod_suspend, + .resume = aml_atvdemod_resume, +}; + +struct class *aml_atvdemod_clsp; + +static void aml_atvdemod_dt_parse(struct platform_device *pdev) +{ + struct device_node *node; + unsigned int val; + int ret; + + node = pdev->dev.of_node; + /* get integer value */ + if (node) { + ret = of_property_read_u32(node, "reg_23cf", &val); + if (ret) + pr_dbg("Can't find reg_23cf.\n"); + else + reg_23cf = val; + ret = of_property_read_u32(node, "audio_gain_val", &val); + if (ret) + pr_dbg("Can't find audio_gain_val.\n"); + else + set_audio_gain_val(val); + ret = of_property_read_u32(node, "video_gain_val", &val); + if (ret) + pr_dbg("Can't find video_gain_val.\n"); + else + set_video_gain_val(val); + /* agc pin mux */ + ret = of_property_read_string(node, "pinctrl-names", + &amlatvdemod_devp->pin_name); + if (!ret) { + /* amlatvdemod_devp->pin = */ + /* devm_pinctrl_get_select(&pdev->dev, */ + /* amlatvdemod_devp->pin_name); */ + pr_dbg("atvdemod agc pinmux name:%s\n", + amlatvdemod_devp->pin_name); + } + } +} +static struct resource amlatvdemod_memobj; +void __iomem *amlatvdemod_reg_base; +void __iomem *amlatvdemod_hiu_reg_base; +void __iomem *amlatvdemod_periphs_reg_base; +int amlatvdemod_reg_read(unsigned int reg, unsigned int *val) +{ + *val = readl(amlatvdemod_reg_base + reg); + return 0; +} + +int amlatvdemod_reg_write(unsigned int reg, unsigned int val) +{ + writel(val, (amlatvdemod_reg_base + reg)); + return 0; +} + +int amlatvdemod_hiu_reg_read(unsigned int reg, unsigned int *val) +{ + *val = readl(amlatvdemod_hiu_reg_base + ((reg - 0x1000)<<2)); + return 0; +} + +int amlatvdemod_hiu_reg_write(unsigned int reg, unsigned int val) +{ + writel(val, (amlatvdemod_hiu_reg_base + ((reg - 0x1000)<<2))); + return 0; +} +int amlatvdemod_periphs_reg_read(unsigned int reg, unsigned int *val) +{ + *val = readl(amlatvdemod_periphs_reg_base + ((reg - 0x1000)<<2)); + return 0; +} + +int amlatvdemod_periphs_reg_write(unsigned int reg, unsigned int val) +{ + writel(val, (amlatvdemod_periphs_reg_base + ((reg - 0x1000)<<2))); + return 0; +} + +static int aml_atvdemod_probe(struct platform_device *pdev) +{ + int ret = 0; + struct resource *res; + int size_io_reg; + + res = &amlatvdemod_memobj; + amlatvdemod_devp = kmalloc(sizeof(struct amlatvdemod_device_s), + GFP_KERNEL); + if (!amlatvdemod_devp) + goto fail_alloc_region; + memset(amlatvdemod_devp, 0, sizeof(struct amlatvdemod_device_s)); + amlatvdemod_devp->clsp = class_create(THIS_MODULE, + ATVDEMOD_DEVICE_NAME); + if (!amlatvdemod_devp->clsp) + goto fail_create_class; + ret = class_create_file(amlatvdemod_devp->clsp, + &class_attr_atvdemod_debug); + if (ret) + goto fail_class_create_file; + amlatvdemod_devp->dev = &pdev->dev; + + /*reg mem*/ + pr_info("%s:amlatvdemod start get ioremap .\n", __func__); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "missing memory resource\n"); + return -ENODEV; + } + size_io_reg = resource_size(res); + pr_info("amlatvdemod_probe reg=%p,size=%x\n", + (void *)res->start, size_io_reg); + amlatvdemod_reg_base = + devm_ioremap_nocache(&pdev->dev, res->start, size_io_reg); + if (!amlatvdemod_reg_base) { + dev_err(&pdev->dev, "amlatvdemod ioremap failed\n"); + return -ENOMEM; + } + pr_info("%s: amlatvdemod maped reg_base =%p, size=%x\n", + __func__, amlatvdemod_reg_base, size_io_reg); + /*remap hiu mem*/ + amlatvdemod_hiu_reg_base = ioremap(0xc883c000, 0x2000); + /*remap periphs mem*/ + amlatvdemod_periphs_reg_base = ioremap(0xc8834000, 0x2000); + + /*initialize the tuner common struct and register*/ + aml_register_fe_drv(AM_DEV_ATV_DEMOD, &aml_atvdemod_drv); + + aml_atvdemod_dt_parse(pdev); + pr_dbg("[amlatvdemod.] : probe ok.\n"); + return 0; + +fail_class_create_file: + pr_dbg("[amlatvdemod.] : atvdemod class file create error.\n"); + class_destroy(amlatvdemod_devp->clsp); +fail_create_class: + pr_dbg("[amlatvdemod.] : atvdemod class create error.\n"); + kfree(amlatvdemod_devp); +fail_alloc_region: + pr_dbg("[amlatvdemod.] : atvdemod alloc error.\n"); + pr_dbg("[amlatvdemod.] : atvdemod_init fail.\n"); + return ret; +} + +static int __exit aml_atvdemod_remove(struct platform_device *pdev) +{ + if (amlatvdemod_devp == NULL) + return -1; + class_destroy(amlatvdemod_devp->clsp); + aml_unregister_fe_drv(AM_DEV_ATV_DEMOD, &aml_atvdemod_drv); + kfree(amlatvdemod_devp); + pr_dbg("[amlatvdemod.] : amvecm_remove.\n"); + return 0; +} + + +static const struct of_device_id aml_atvdemod_dt_match[] = { + { + .compatible = "amlogic, aml_atv_demod", + }, + {}, +}; + +static struct platform_driver aml_atvdemod_driver = { + .driver = { + .name = "aml_atv_demod", + .owner = THIS_MODULE, + .of_match_table = aml_atvdemod_dt_match, + }, + .probe = aml_atvdemod_probe, + .remove = __exit_p(aml_atvdemod_remove), +}; + + +static int __init aml_atvdemod_init(void) +{ + if (platform_driver_register(&aml_atvdemod_driver)) { + pr_err("failed to register amlatvdemod driver module\n"); + return -ENODEV; + } + pr_dbg("[amlatvdemod..]%s.\n", __func__); + return 0; +} + +static void __exit aml_atvdemod_exit(void) +{ + platform_driver_unregister(&aml_atvdemod_driver); + pr_dbg("[amlatvdemod..]%s: driver removed ok.\n", __func__); +} + +MODULE_AUTHOR("dezhi.kong "); +MODULE_DESCRIPTION("aml atv demod device driver"); +MODULE_LICENSE("GPL"); + +fs_initcall(aml_atvdemod_init); +module_exit(aml_atvdemod_exit); diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/atv_demod/atvdemod_func.c b/drivers/amlogic/media_modules/stream_input/tv_frontend/atv_demod/atvdemod_func.c new file mode 100644 index 000000000000..f5a086e8e932 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/atv_demod/atvdemod_func.c @@ -0,0 +1,2163 @@ +/* + * Silicon labs amlogic Atvdemod Device Driver + * + * Author: dezhi kong + * + * + * Copyright (C) 2014 Amlogic Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* Standard Liniux Headers */ +#include +#include +#include +#include +#include +#include +#include + +#include "atvdemod_func.h" +#include "../aml_dvb_reg.h" + +static int broad_std = AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC; +module_param(broad_std, int, 0644); +MODULE_PARM_DESC(broad_std, "\n broad_std\n"); + +static unsigned long over_threshold = 0xffff; +module_param(over_threshold, ulong, 0644); +MODULE_PARM_DESC(over_threshold, "\n over_threshold\n"); + +static unsigned long input_amplitude = 0xffff; +module_param(input_amplitude, ulong, 0644); +MODULE_PARM_DESC(input_amplitude, "\n input_amplitude\n"); + +static bool audio_det_en; +module_param(audio_det_en, bool, 0644); +MODULE_PARM_DESC(audio_det_en, "\n audio_det_en\n"); + +static bool non_std_en; +module_param(non_std_en, bool, 0644); +MODULE_PARM_DESC(non_std__en, "\n non_std_en\n"); + +static int atv_video_gain; +module_param(atv_video_gain, int, 0644); +MODULE_PARM_DESC(atv_video_gain, "\n atv_video_gain\n"); + +static int audio_det_mode = AUDIO_AUTO_DETECT; +module_param(audio_det_mode, int, 0644); +MODULE_PARM_DESC(audio_det_mode, "\n audio_det_mode\n"); + +static int aud_dmd_jilinTV; +module_param(aud_dmd_jilinTV, int, 0644); +MODULE_PARM_DESC(aud_dmd_jilinTV, "\naud dmodulation setting for jilin TV\n"); + +static unsigned int if_freq = 4250000; /*PAL-DK:3250000;NTSC-M:4250000*/ +module_param(if_freq, uint, 0644); +MODULE_PARM_DESC(if_freq, "\n if_freq\n"); + +static int if_inv; +module_param(if_inv, int, 0644); +MODULE_PARM_DESC(if_inv, "\n if_inv\n"); + +static int afc_default = CARR_AFC_DEFAULT_VAL; +module_param(afc_default, int, 0644); +MODULE_PARM_DESC(afc_default, "\n afc_default\n"); + +/*GDE_Curve + * 0: CURVE-M + * 1: CURVE-A + * 2: CURVE-B + * 3: CURVE-CHINA + * 4: BYPASS + *BG --> CURVE-B(BYPASS) + *DK --> CURVE-CHINA + *NM --> CURVE-M + *I --> BYPASS + *SECAM --> BYPASS + */ +static int gde_curve; +module_param(gde_curve, int, 0644); +MODULE_PARM_DESC(gde_curve, "\n gde_curve\n"); + +static int sound_format; +module_param(sound_format, int, 0644); +MODULE_PARM_DESC(sound_format, "\n sound_format\n"); + +static unsigned int freq_hz_cvrt = AML_ATV_DEMOD_FREQ_60HZ_VERT; +module_param(freq_hz_cvrt, int, 0644); +MODULE_PARM_DESC(freq_hz_cvrt, "\n freq_hz\n"); + +int atvdemod_debug_en; +module_param(atvdemod_debug_en, int, 0644); +MODULE_PARM_DESC(atvdemod_debug_en, "\n atvdemod_debug_en\n"); + +/*1:gpio mode output low;2:pwm mode*/ +static unsigned int atvdemod_agc_pinmux = 2; +module_param(atvdemod_agc_pinmux, int, 0644); +MODULE_PARM_DESC(atvdemod_agc_pinmux, "\n atvdemod_agc_pinmux\n"); + +static unsigned int atvdemod_afc_range = 5; +module_param(atvdemod_afc_range, uint, 0644); +MODULE_PARM_DESC(atvdemod_afc_range, "\n atvdemod_afc_range\n"); + +static unsigned int atvdemod_afc_offset = 500; +module_param(atvdemod_afc_offset, uint, 0644); +MODULE_PARM_DESC(atvdemod_afc_offset, "\n atvdemod_afc_offset\n"); + +static unsigned int atvdemod_timer_en = 1; +module_param(atvdemod_timer_en, uint, 0644); +MODULE_PARM_DESC(atvdemod_timer_en, "\n atvdemod_timer_en\n"); + +static unsigned int atvdemod_afc_en; +module_param(atvdemod_afc_en, uint, 0644); +MODULE_PARM_DESC(atvdemod_afc_en, "\n atvdemod_afc_en\n"); + +static unsigned int atvdemod_monitor_en; +module_param(atvdemod_monitor_en, uint, 0644); +MODULE_PARM_DESC(atvdemod_monitor_en, "\n atvdemod_monitor_en\n"); + +static unsigned int atvdemod_det_snr_en = 1; +module_param(atvdemod_det_snr_en, uint, 0644); +MODULE_PARM_DESC(atvdemod_det_snr_en, "\n atvdemod_det_snr_en\n"); + +static unsigned int pwm_kp = 0x19; +module_param(pwm_kp, uint, 0644); +MODULE_PARM_DESC(pwm_kp, "\n pwm_kp\n"); + +static unsigned int reg_dbg_en; +module_param(reg_dbg_en, uint, 0644); +MODULE_PARM_DESC(reg_dbg_en, "\n reg_dbg_en\n"); + +static unsigned int audio_gain_val = 512; +module_param(audio_gain_val, uint, 0644); +MODULE_PARM_DESC(audio_gain_val, "\n audio_gain_val\n"); + +enum AUDIO_SCAN_ID { + ID_PAL_I = 0, + ID_PAL_M, + ID_PAL_DK, + ID_PAL_BG, + ID_MAX, +}; + +static unsigned int mix1_freq; +static unsigned int timer_init_flag; +struct timer_list atvdemod_timer; +static int snr_val; +int broad_std_except_pal_m; + +int get_atvdemod_snr_val(void) +{ + return snr_val; +} +EXPORT_SYMBOL(get_atvdemod_snr_val); + +void amlatvdemod_set_std(int val) +{ + broad_std = val; +} +EXPORT_SYMBOL(amlatvdemod_set_std); + +void atv_dmd_wr_reg(unsigned char block, unsigned char reg, unsigned long data) +{ + /* unsigned long data_tmp; */ + unsigned long reg_addr = (block<<8) + reg * 4; + + amlatvdemod_reg_write(reg_addr, data); +} + +unsigned long atv_dmd_rd_reg(unsigned char block, unsigned char reg) +{ + unsigned long data = 0; + unsigned long reg_addr = (block<<8) + reg * 4; + + amlatvdemod_reg_read(reg_addr, (unsigned int *)&data); + return data; +} + +unsigned long atv_dmd_rd_byte(unsigned long block_addr, unsigned long reg_addr) +{ + unsigned long data; + + data = atv_dmd_rd_long(block_addr, reg_addr); + /*R_APB_REG((((block_addr & 0xff) <<6) + ((reg_addr & 0xff) >>2)) << 2); + *((volatile unsigned long *) (ATV_DMD_APB_BASE_ADDR+ + ((((block_addr & 0xff) <<6) + ((reg_addr & 0xff) >>2)) << 2))); + */ + if ((reg_addr & 0x3) == 0) + data = data >> 24; + else if ((reg_addr & 0x3) == 1) + data = (data >> 16 & 0xff); + else if ((reg_addr & 0x3) == 2) + data = (data >> 8 & 0xff); + else if ((reg_addr & 0x3) == 3) + data = (data >> 0 & 0xff); + return data; +} + +unsigned long atv_dmd_rd_word(unsigned long block_addr, unsigned long reg_addr) +{ + unsigned long data; + + data = atv_dmd_rd_long(block_addr, reg_addr); + /*R_APB_REG((((block_addr & 0xff) <<6) + ((reg_addr & 0xff) >>2)) << 2); + *((volatile unsigned long *) (ATV_DMD_APB_BASE_ADDR+ + ((((block_addr & 0xff) <<6) + ((reg_addr & 0xff) >>2)) << 2))); + */ + if ((reg_addr & 0x3) == 0) + data = data >> 16; + else if ((reg_addr & 0x3) == 1) + data = (data >> 8 & 0xffff); + else if ((reg_addr & 0x3) == 2) + data = (data >> 0 & 0xffff); + else if ((reg_addr & 0x3) == 3) + data = (((data & 0xff) << 8) | ((data >> 24) & 0xff)); + return data; +} + +unsigned long atv_dmd_rd_long(unsigned long block_addr, unsigned long reg_addr) +{ + unsigned long data; + /*data = *((volatile unsigned long *) (ATV_DMD_APB_BASE_ADDR+ + *((((block_addr & 0xff) <<6) + ((reg_addr & 0xff) >>2)) << 2))); + */ + data = + R_ATVDEMOD_REG((((block_addr & 0xff) << 6) + + ((reg_addr & 0xff) >> 2)) << 2); + + return data; +} +EXPORT_SYMBOL(atv_dmd_rd_long); + +void atv_dmd_wr_long(unsigned long block_addr, unsigned long reg_addr, + unsigned long data) +{ + W_ATVDEMOD_REG((((block_addr & 0xff) << 6) + + ((reg_addr & 0xff) >> 2)) << 2, data); + if (reg_dbg_en) + pr_dbg("block_addr:0x%x,reg_addr:0x%x;data:0x%x\n", + (unsigned int)block_addr, (unsigned int)reg_addr, + (unsigned int)data); + /**((volatile unsigned long *) + * (ATV_DMD_APB_BASE_ADDR+((((block_addr & 0xff) << 6) + + * ((reg_addr & 0xff) >> 2)) << 2))) = data; + */ + +} +EXPORT_SYMBOL(atv_dmd_wr_long); + +void atv_dmd_wr_word(unsigned long block_addr, unsigned long reg_addr, + unsigned long data) +{ + unsigned long data_tmp; + + data_tmp = atv_dmd_rd_long(block_addr, reg_addr); + data = data & 0xffff; + if ((reg_addr & 0x3) == 0) + data = (data << 16 | (data_tmp & 0xffff)); + else if ((reg_addr & 0x3) == 1) + data = + ((data_tmp & 0xff000000) | (data << 8) | (data_tmp & 0xff)); + else if ((reg_addr & 0x3) == 2) + data = (data | (data_tmp & 0xffff0000)); + else if ((reg_addr & 0x3) == 3) + data = + (((data & 0xff) << 24) | ((data_tmp & 0xffff0000) >> 8) | + ((data & 0xff00) >> 8)); + + /**((volatile unsigned long *) (ATV_DMD_APB_BASE_ADDR+ + *((((block_addr & 0xff) <<6) + ((reg_addr & 0xff) >>2)) << 2))) = data; + */ + atv_dmd_wr_long(block_addr, reg_addr, data); + /*W_ATVDEMOD_REG(((((block_addr & 0xff) <<6) + + *((reg_addr & 0xff) >>2)) << 2), data); + */ + +} + +void atv_dmd_wr_byte(unsigned long block_addr, unsigned long reg_addr, + unsigned long data) +{ + unsigned long data_tmp; + + data_tmp = atv_dmd_rd_long(block_addr, reg_addr); + + /*pr_info("atv demod wr byte, read block addr %lx\n",block_addr);*/ + /*pr_info("atv demod wr byte, read reg addr %lx\n", reg_addr);*/ + /*pr_info("atv demod wr byte, wr data %lx\n",data);*/ + /*pr_info("atv demod wr byte, read data out %lx\n",data_tmp);*/ + + data = data & 0xff; + /*pr_info("atv demod wr byte, data & 0xff %lx\n",data);*/ + if ((reg_addr & 0x3) == 0) { + data = (data << 24 | (data_tmp & 0xffffff)); + /*pr_info("atv demod wr byte, reg_addr & 0x3 == 0, + *wr data %lx\n",data); + */ + } else if ((reg_addr & 0x3) == 1) + data = + ((data_tmp & 0xff000000) | (data << 16) | + (data_tmp & 0xffff)); + else if ((reg_addr & 0x3) == 2) + data = + ((data_tmp & 0xffff0000) | (data << 8) | (data_tmp & 0xff)); + else if ((reg_addr & 0x3) == 3) + data = ((data_tmp & 0xffffff00) | (data & 0xff)); + + /*pr_info("atv demod wr byte, wr data %lx\n",data);*/ + + /**((volatile unsigned long *) (ATV_DMD_APB_BASE_ADDR+ + *((((block_addr & 0xff) <<6) + ((reg_addr & 0xff) >>2)) << 2))) = data; + */ + atv_dmd_wr_long(block_addr, reg_addr, data); + /*W_ATVDEMOD_REG(((((block_addr & 0xff) <<6) + + *((reg_addr & 0xff) >>2)) << 2), data); + */ +} + +void set_audio_gain_val(int val) +{ + audio_gain_val = val; +} + +void set_video_gain_val(int val) +{ + atv_video_gain = val; +} + +void atv_dmd_soft_reset(void) +{ + atv_dmd_wr_long(0x1d, 0x0, 0x1035);/* disable dac */ + atv_dmd_wr_byte(APB_BLOCK_ADDR_SYSTEM_MGT, 0x0, 0x0); + atv_dmd_wr_byte(APB_BLOCK_ADDR_SYSTEM_MGT, 0x0, 0x1); + atv_dmd_wr_long(0x1d, 0x0, 0x1037);/* enable dac */ +} + +void atv_dmd_input_clk_32m(void) +{ + atv_dmd_wr_byte(APB_BLOCK_ADDR_ADC_MGR, 0x2, 0x1); +} + +void read_version_register(void) +{ + unsigned long data, Byte1, Byte2, Word; + + pr_info("ATV-DMD read version register\n"); + Byte1 = atv_dmd_rd_byte(APB_BLOCK_ADDR_VERS_REGISTER, 0x0); + Byte2 = atv_dmd_rd_byte(APB_BLOCK_ADDR_VERS_REGISTER, 0x1); + Word = atv_dmd_rd_word(APB_BLOCK_ADDR_VERS_REGISTER, 0x2); + data = atv_dmd_rd_long(APB_BLOCK_ADDR_VERS_REGISTER, 0x0); + + pr_info("atv demod read version register data out %lx\n", data); + + if ((data != 0x516EAB13) + || (((Byte1 << 24) | (Byte2 << 16) | Word) != 0x516EAB13)) + pr_info("atv demod read version reg failed\n"); +} + +void check_communication_interface(void) +{ + unsigned long data_tmp; + + pr_info("ATV-DMD check communication intf\n"); + atv_dmd_wr_long(APB_BLOCK_ADDR_VERS_REGISTER, 0x0, 0xA1B2C3D4); + atv_dmd_wr_byte(APB_BLOCK_ADDR_VERS_REGISTER, 0x1, 0x34); + atv_dmd_wr_word(APB_BLOCK_ADDR_VERS_REGISTER, 0x2, 0xBCDE); + data_tmp = atv_dmd_rd_long(APB_BLOCK_ADDR_VERS_REGISTER, 0x0); + pr_info("atv demod check communication intf data out %lx\n", data_tmp); + + if (data_tmp != 0xa134bcde) + pr_info("atv demod check communication intf failed\n"); + atv_dmd_wr_long(APB_BLOCK_ADDR_VERS_REGISTER, 0x0, 0x516EAB13); +} + +void power_on_receiver(void) +{ + atv_dmd_wr_byte(APB_BLOCK_ADDR_ADC_MGR, 0x2, 0x11); +} + +void atv_dmd_misc(void) +{ + atv_dmd_wr_byte(APB_BLOCK_ADDR_AGC_PWM, 0x08, 0x38); /*zhuangwei*/ + /*cpu.write_byte(8'h1A,8'h0E,8'h06);//zhuangwei*/ + /*cpu.write_byte(8'h19,8'h01,8'h7f);//zhuangwei*/ + atv_dmd_wr_byte(0x0f, 0x45, 0x90); /*zhuangwei*/ + + atv_dmd_wr_long(0x0f, 0x44, 0x5c8808c1);/*zhuangwei*/ + if (amlatvdemod_devp->parm.tuner_id == AM_TUNER_R840) { + atv_dmd_wr_long(0x0f, 0x3c, reg_23cf);/*zhuangwei*/ + /*guanzhong@20150804a*/ + atv_dmd_wr_byte(APB_BLOCK_ADDR_SIF_STG_2, 0x00, 0x1); + atv_dmd_wr_long(APB_BLOCK_ADDR_AGC_PWM, 0x08, 0x60180200); + /*dezhi@20150610a 0x1a maybe better?!*/ + /* atv_dmd_wr_byte(APB_BLOCK_ADDR_AGC_PWM, 0x09, 0x19); */ + } else { + atv_dmd_wr_long(0x0f, 0x3c, 0x88188832);/*zhuangwei*/ + atv_dmd_wr_long(APB_BLOCK_ADDR_AGC_PWM, 0x08, 0x46170200); + } + + if (amlatvdemod_devp->parm.tuner_id == AM_TUNER_MXL661) { + atv_dmd_wr_long(0x0c, 0x04, 0xbffa0000) ;/*test in sky*/ + atv_dmd_wr_long(0x0c, 0x00, 0x5a4000);/*test in sky*/ + /*guanzhong@20151013 fix nonstd def is:0x0c010301;0x0c020601*/ + atv_dmd_wr_long(APB_BLOCK_ADDR_CARR_RCVY, 0x24, 0x0c030901); + } else { + /*zhuangwei 0xdafa0000*/ + atv_dmd_wr_long(0x0c, 0x04, 0xc8fa0000); + atv_dmd_wr_long(0x0c, 0x00, 0x554000);/*zhuangwei*/ + } + atv_dmd_wr_long(0x19, 0x04, 0xdafa0000);/*zhuangwei*/ + atv_dmd_wr_long(0x19, 0x00, 0x4a4000);/*zhuangwei*/ + /*atv_dmd_wr_byte(0x0c,0x01,0x28);//pwd-out gain*/ + /*atv_dmd_wr_byte(0x0c,0x04,0xc0);//pwd-out offset*/ + + aml_audio_valume_gain_set(audio_gain_val); + /* 20160121 fix audio demodulation over */ + atv_dmd_wr_long(0x09, 0x00, 0x1030501); + atv_dmd_wr_long(0x09, 0x04, 0x1900000); + if (aud_dmd_jilinTV) + atv_dmd_wr_long(0x09, 0x00, 0x2030503); + if (non_std_en == 1) { + atv_dmd_wr_long(0x09, 0x00, 0x2030503); + atv_dmd_wr_long(0x0f, 0x44, 0x7c8808c1); + atv_dmd_wr_long(0x06, 0x24, 0x0c010801); + } else { + atv_dmd_wr_long(0x09, 0x00, 0x1030501); + if (atv_video_gain) + atv_dmd_wr_long(0x0f, 0x44, atv_video_gain); + else + atv_dmd_wr_long(0x0f, 0x44, 0xfc0808c1); + atv_dmd_wr_long(0x06, 0x24, 0xc030901); + } + +} + +/*Broadcast_Standard*/ +/* 0: NTSC*/ +/* 1: NTSC-J*/ +/* 2: PAL-M,*/ +/* 3: PAL-BG*/ +/* 4: DTV*/ +/* 5: SECAM- DK2*/ +/* 6: SECAM -DK3*/ +/* 7: PAL-BG, NICAM*/ +/* 8: PAL-DK-CHINA*/ +/* 9: SECAM-L / SECAM-DK3*/ +/* 10: PAL-I*/ +/* 11: PAL-DK1*/ +/*GDE_Curve*/ +/* 0: CURVE-M*/ +/* 1: CURVE-A*/ +/* 2: CURVE-B*/ +/* 3: CURVE-CHINA*/ +/* 4: BYPASS*/ +/*sound format 0: MONO;1:NICAM*/ +void configure_receiver(int Broadcast_Standard, unsigned int Tuner_IF_Frequency, + int Tuner_Input_IF_inverted, int GDE_Curve, + int sound_format) +{ + int tmp_int; + int mixer1 = 0; + int mixer3 = 0; + int mixer3_bypass = 0; + int cv = 0; + /*int if_freq = 0;*/ + + int i = 0; + int super_coef0 = 0; + int super_coef1 = 0; + int super_coef2 = 0; + int gp_coeff_1[37]; + int gp_coeff_2[37]; + int gp_cv_g1 = 0; + int gp_cv_g2 = 0; + int crvy_reg_1 = 0; + int crvy_reg_2 = 0; + int sif_co_mx = 0; + int sif_fi_mx = 0; + int sif_ic_bw = 0; + int sif_bb_bw = 0; + int sif_deemp = 0; + int sif_cfg_demod = 0; + int sif_fm_gain = 0; + int gd_coeff[6]; + int gd_bypass; + + pr_info("ATV-DMD configure receiver register\n"); + + if ((Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC) || + (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_J) || + (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_M) || + (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_DK) || + (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_BG) || + (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_I)) { + gp_coeff_1[0] = 0x57777; + gp_coeff_1[1] = 0xdd777; + gp_coeff_1[2] = 0x7d777; + gp_coeff_1[3] = 0x75777; + gp_coeff_1[4] = 0x75777; + gp_coeff_1[5] = 0x7c777; + gp_coeff_1[6] = 0x5c777; + gp_coeff_1[7] = 0x44777; + gp_coeff_1[8] = 0x54777; + gp_coeff_1[9] = 0x47d77; + gp_coeff_1[10] = 0x55d77; + gp_coeff_1[11] = 0x55577; + gp_coeff_1[12] = 0x77577; + gp_coeff_1[13] = 0xc4c77; + gp_coeff_1[14] = 0xd7d77; + gp_coeff_1[15] = 0x75477; + gp_coeff_1[16] = 0xcc477; + gp_coeff_1[17] = 0x575d7; + gp_coeff_1[18] = 0xc4c77; + gp_coeff_1[19] = 0xdd757; + gp_coeff_1[20] = 0xdd477; + gp_coeff_1[21] = 0x77dd7; + gp_coeff_1[22] = 0x5dc77; + gp_coeff_1[23] = 0x47c47; + gp_coeff_1[24] = 0x57477; + gp_coeff_1[25] = 0x5c7c7; + gp_coeff_1[26] = 0xccc77; + gp_coeff_1[27] = 0x5ddd5; + gp_coeff_1[28] = 0x54477; + gp_coeff_1[29] = 0x7757d; + gp_coeff_1[30] = 0x755d7; + gp_coeff_1[31] = 0x47cc4; + gp_coeff_1[32] = 0x57d57; + gp_coeff_1[33] = 0x554cc; + gp_coeff_1[34] = 0x755d7; + gp_coeff_1[35] = 0x7d3b2; + gp_coeff_1[36] = 0x73a91; + gp_coeff_2[0] = 0xd5777; + gp_coeff_2[1] = 0x77777; + gp_coeff_2[2] = 0x7c777; + gp_coeff_2[3] = 0xcc777; + gp_coeff_2[4] = 0xc7777; + gp_coeff_2[5] = 0xdd777; + gp_coeff_2[6] = 0x44c77; + gp_coeff_2[7] = 0x54c77; + gp_coeff_2[8] = 0xdd777; + gp_coeff_2[9] = 0x7c777; + gp_coeff_2[10] = 0xc7c77; + gp_coeff_2[11] = 0x75c77; + gp_coeff_2[12] = 0xdd577; + gp_coeff_2[13] = 0x44777; + gp_coeff_2[14] = 0xd5c77; + gp_coeff_2[15] = 0xdc777; + gp_coeff_2[16] = 0xd7757; + gp_coeff_2[17] = 0x4c757; + gp_coeff_2[18] = 0x7d777; + gp_coeff_2[19] = 0x75477; + gp_coeff_2[20] = 0x57547; + gp_coeff_2[21] = 0xdc747; + gp_coeff_2[22] = 0x74777; + gp_coeff_2[23] = 0x75757; + gp_coeff_2[24] = 0x4cc75; + gp_coeff_2[25] = 0xd4747; + gp_coeff_2[26] = 0x7d7d7; + gp_coeff_2[27] = 0xd5577; + gp_coeff_2[28] = 0xc4c75; + gp_coeff_2[29] = 0xcc477; + gp_coeff_2[30] = 0xdd54c; + gp_coeff_2[31] = 0x7547d; + gp_coeff_2[32] = 0x55547; + gp_coeff_2[33] = 0x5575c; + gp_coeff_2[34] = 0xd543a; + gp_coeff_2[35] = 0x57b3a; + gp_coeff_2[36] = 0x77777; + gp_cv_g1 = 0x2b062d; + gp_cv_g2 = 0x40fa2d; + } else if ((Broadcast_Standard == + AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_BG) || + (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_SECAM_DK2) || + (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_SECAM_DK3) || + (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_BG_NICAM)) { + gp_coeff_1[0] = 0x75777; + gp_coeff_1[1] = 0x57777; + gp_coeff_1[2] = 0x7d777; + gp_coeff_1[3] = 0x75777; + gp_coeff_1[4] = 0x75777; + gp_coeff_1[5] = 0x7c777; + gp_coeff_1[6] = 0x47777; + gp_coeff_1[7] = 0x74777; + gp_coeff_1[8] = 0xd5d77; + gp_coeff_1[9] = 0xc7777; + gp_coeff_1[10] = 0x77577; + gp_coeff_1[11] = 0xd7d77; + gp_coeff_1[12] = 0x75d77; + gp_coeff_1[13] = 0xdd477; + gp_coeff_1[14] = 0x77d77; + gp_coeff_1[15] = 0x75c77; + gp_coeff_1[16] = 0xc4477; + gp_coeff_1[17] = 0x4c777; + gp_coeff_1[18] = 0x5d5d7; + gp_coeff_1[19] = 0xd7d57; + gp_coeff_1[20] = 0x47577; + gp_coeff_1[21] = 0xd7dd7; + gp_coeff_1[22] = 0xd7d57; + gp_coeff_1[23] = 0xdd757; + gp_coeff_1[24] = 0xc75c7; + gp_coeff_1[25] = 0x7d477; + gp_coeff_1[26] = 0x5d747; + gp_coeff_1[27] = 0x7ddc7; + gp_coeff_1[28] = 0xc4c77; + gp_coeff_1[29] = 0xd4c75; + gp_coeff_1[30] = 0xc755d; + gp_coeff_1[31] = 0x47cc7; + gp_coeff_1[32] = 0xdd7d4; + gp_coeff_1[33] = 0x4c75d; + gp_coeff_1[34] = 0xc7dcc; + gp_coeff_1[35] = 0xd52a2; + gp_coeff_1[36] = 0x555a1; + gp_coeff_2[0] = 0x5d777; + gp_coeff_2[1] = 0x47777; + gp_coeff_2[2] = 0x7d777; + gp_coeff_2[3] = 0xcc777; + gp_coeff_2[4] = 0xd7777; + gp_coeff_2[5] = 0x7c777; + gp_coeff_2[6] = 0x7dd77; + gp_coeff_2[7] = 0xdd777; + gp_coeff_2[8] = 0x7c777; + gp_coeff_2[9] = 0x57c77; + gp_coeff_2[10] = 0x7c777; + gp_coeff_2[11] = 0xd5777; + gp_coeff_2[12] = 0xd7c77; + gp_coeff_2[13] = 0xdd777; + gp_coeff_2[14] = 0x77477; + gp_coeff_2[15] = 0xc7d77; + gp_coeff_2[16] = 0xc4777; + gp_coeff_2[17] = 0x57557; + gp_coeff_2[18] = 0xd5577; + gp_coeff_2[19] = 0xd5577; + gp_coeff_2[20] = 0x7d547; + gp_coeff_2[21] = 0x74757; + gp_coeff_2[22] = 0xc7577; + gp_coeff_2[23] = 0xcc7d5; + gp_coeff_2[24] = 0x4c747; + gp_coeff_2[25] = 0xddc77; + gp_coeff_2[26] = 0x54447; + gp_coeff_2[27] = 0xcc447; + gp_coeff_2[28] = 0x5755d; + gp_coeff_2[29] = 0x5dd57; + gp_coeff_2[30] = 0x54747; + gp_coeff_2[31] = 0x5747c; + gp_coeff_2[32] = 0xc77dd; + gp_coeff_2[33] = 0x47557; + gp_coeff_2[34] = 0x7a22a; + gp_coeff_2[35] = 0xc73aa; + gp_coeff_2[36] = 0x77777; + gp_cv_g1 = 0x2b2834; + gp_cv_g2 = 0x3f6c2e; + } else if ((Broadcast_Standard == + AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_DK) || + (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_SECAM_DK3)) { + gp_coeff_1[0] = 0x47777; + gp_coeff_1[1] = 0x77777; + gp_coeff_1[2] = 0x5d777; + gp_coeff_1[3] = 0x47777; + gp_coeff_1[4] = 0x75777; + gp_coeff_1[5] = 0x5c777; + gp_coeff_1[6] = 0x57777; + gp_coeff_1[7] = 0x44777; + gp_coeff_1[8] = 0x55d77; + gp_coeff_1[9] = 0x7d777; + gp_coeff_1[10] = 0x55577; + gp_coeff_1[11] = 0xd5d77; + gp_coeff_1[12] = 0xd7d77; + gp_coeff_1[13] = 0x47477; + gp_coeff_1[14] = 0xdc777; + gp_coeff_1[15] = 0x4cc77; + gp_coeff_1[16] = 0x77d57; + gp_coeff_1[17] = 0xc4777; + gp_coeff_1[18] = 0xdd7d7; + gp_coeff_1[19] = 0x7c757; + gp_coeff_1[20] = 0xd4477; + gp_coeff_1[21] = 0x755c7; + gp_coeff_1[22] = 0x47d57; + gp_coeff_1[23] = 0xd7c47; + gp_coeff_1[24] = 0xd4cc7; + gp_coeff_1[25] = 0x47577; + gp_coeff_1[26] = 0x5c7d5; + gp_coeff_1[27] = 0x4c75d; + gp_coeff_1[28] = 0xd57d7; + gp_coeff_1[29] = 0x44755; + gp_coeff_1[30] = 0x7557d; + gp_coeff_1[31] = 0xc477d; + gp_coeff_1[32] = 0xd5d44; + gp_coeff_1[33] = 0xdd77d; + gp_coeff_1[34] = 0x5d75b; + gp_coeff_1[35] = 0x74332; + gp_coeff_1[36] = 0xd4311; + gp_coeff_2[0] = 0xd7777; + gp_coeff_2[1] = 0x77777; + gp_coeff_2[2] = 0xdd777; + gp_coeff_2[3] = 0xdc777; + gp_coeff_2[4] = 0xc7777; + gp_coeff_2[5] = 0xdd777; + gp_coeff_2[6] = 0x77d77; + gp_coeff_2[7] = 0x77777; + gp_coeff_2[8] = 0x55777; + gp_coeff_2[9] = 0xc7d77; + gp_coeff_2[10] = 0xd4777; + gp_coeff_2[11] = 0xc7477; + gp_coeff_2[12] = 0x7c777; + gp_coeff_2[13] = 0xd5577; + gp_coeff_2[14] = 0xdd557; + gp_coeff_2[15] = 0x47577; + gp_coeff_2[16] = 0xd7477; + gp_coeff_2[17] = 0x55747; + gp_coeff_2[18] = 0xdd757; + gp_coeff_2[19] = 0xd7477; + gp_coeff_2[20] = 0x7d7d5; + gp_coeff_2[21] = 0xddd47; + gp_coeff_2[22] = 0xdd777; + gp_coeff_2[23] = 0x575d5; + gp_coeff_2[24] = 0x47547; + gp_coeff_2[25] = 0x555c7; + gp_coeff_2[26] = 0x7d447; + gp_coeff_2[27] = 0xd7447; + gp_coeff_2[28] = 0x757dd; + gp_coeff_2[29] = 0x7dc77; + gp_coeff_2[30] = 0x54747; + gp_coeff_2[31] = 0xc743b; + gp_coeff_2[32] = 0xd7c7c; + gp_coeff_2[33] = 0xd7557; + gp_coeff_2[34] = 0x55c7a; + gp_coeff_2[35] = 0x4cc29; + gp_coeff_2[36] = 0x77777; + gp_cv_g1 = 0x20682b; + gp_cv_g2 = 0x29322f; + } else if (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_I) { + gp_coeff_1[0] = 0x77777; + gp_coeff_1[1] = 0x75777; + gp_coeff_1[2] = 0x7d777; + gp_coeff_1[3] = 0xd7777; + gp_coeff_1[4] = 0x74777; + gp_coeff_1[5] = 0xcc777; + gp_coeff_1[6] = 0x57777; + gp_coeff_1[7] = 0x5d577; + gp_coeff_1[8] = 0x5dd77; + gp_coeff_1[9] = 0x74777; + gp_coeff_1[10] = 0x77577; + gp_coeff_1[11] = 0x77c77; + gp_coeff_1[12] = 0xdc477; + gp_coeff_1[13] = 0x5d577; + gp_coeff_1[14] = 0x575d7; + gp_coeff_1[15] = 0xc7d57; + gp_coeff_1[16] = 0x77777; + gp_coeff_1[17] = 0x557d7; + gp_coeff_1[18] = 0xc7557; + gp_coeff_1[19] = 0x75c77; + gp_coeff_1[20] = 0x477d7; + gp_coeff_1[21] = 0xcc747; + gp_coeff_1[22] = 0x47dd7; + gp_coeff_1[23] = 0x775d7; + gp_coeff_1[24] = 0x47447; + gp_coeff_1[25] = 0x75cc7; + gp_coeff_1[26] = 0xc7777; + gp_coeff_1[27] = 0xc75d5; + gp_coeff_1[28] = 0x44c7d; + gp_coeff_1[29] = 0x74c47; + gp_coeff_1[30] = 0x47d75; + gp_coeff_1[31] = 0x7d57c; + gp_coeff_1[32] = 0xd5dc4; + gp_coeff_1[33] = 0xdd575; + gp_coeff_1[34] = 0xdb3bb; + gp_coeff_1[35] = 0x5c752; + gp_coeff_1[36] = 0x90880; + gp_coeff_2[0] = 0x5d777; + gp_coeff_2[1] = 0xd7777; + gp_coeff_2[2] = 0x77777; + gp_coeff_2[3] = 0xd5d77; + gp_coeff_2[4] = 0xc7777; + gp_coeff_2[5] = 0xd7777; + gp_coeff_2[6] = 0xddd77; + gp_coeff_2[7] = 0x55777; + gp_coeff_2[8] = 0x57777; + gp_coeff_2[9] = 0x54c77; + gp_coeff_2[10] = 0x4c477; + gp_coeff_2[11] = 0x74777; + gp_coeff_2[12] = 0xd5d77; + gp_coeff_2[13] = 0x47757; + gp_coeff_2[14] = 0x75577; + gp_coeff_2[15] = 0xc7577; + gp_coeff_2[16] = 0x4c747; + gp_coeff_2[17] = 0x7d477; + gp_coeff_2[18] = 0x7c757; + gp_coeff_2[19] = 0x55dd5; + gp_coeff_2[20] = 0x57577; + gp_coeff_2[21] = 0x44c47; + gp_coeff_2[22] = 0x5cc75; + gp_coeff_2[23] = 0x4cc77; + gp_coeff_2[24] = 0x47547; + gp_coeff_2[25] = 0x777d5; + gp_coeff_2[26] = 0xcccc7; + gp_coeff_2[27] = 0x57447; + gp_coeff_2[28] = 0xdc757; + gp_coeff_2[29] = 0x5755c; + gp_coeff_2[30] = 0x44747; + gp_coeff_2[31] = 0x5d5dd; + gp_coeff_2[32] = 0x5747b; + gp_coeff_2[33] = 0x77557; + gp_coeff_2[34] = 0xdcb2a; + gp_coeff_2[35] = 0xd5779; + gp_coeff_2[36] = 0x77777; + gp_cv_g1 = 0x72242f; + gp_cv_g2 = 0x28822a; + } + + if ((Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC) || + (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_J)) { + sif_co_mx = 0xb8; + sif_fi_mx = 0x0; + sif_ic_bw = 0x1; + sif_bb_bw = 0x1; + sif_deemp = 0x1; + sif_cfg_demod = (sound_format == 0) ? 0x0:0x2; + sif_fm_gain = 0x4; + } else if ((Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_BG) + || (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_BG)) { + sif_co_mx = 0xa6; + sif_fi_mx = 0x10; + sif_ic_bw = 0x2; + sif_bb_bw = 0x0; + sif_deemp = 0x2; + sif_cfg_demod = (sound_format == 0) ? 0x0:0x2; + sif_fm_gain = 0x3; + } else if (Broadcast_Standard == + AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_DK1) { + sif_co_mx = 154; + sif_fi_mx = 240; + sif_ic_bw = 2; + sif_bb_bw = 0; + sif_deemp = 2; + sif_cfg_demod = (sound_format == 0) ? 0:2; + sif_fm_gain = 3; + } else if (Broadcast_Standard == + AML_ATV_DEMOD_VIDEO_MODE_PROP_SECAM_DK2) { + sif_co_mx = 150; + sif_fi_mx = 16; + sif_ic_bw = 2; + sif_bb_bw = 0; + sif_deemp = 2; + sif_cfg_demod = (sound_format == 0) ? 0:2; + sif_fm_gain = 3; + } else if (Broadcast_Standard == + AML_ATV_DEMOD_VIDEO_MODE_PROP_SECAM_DK3) { + sif_co_mx = 158; + sif_fi_mx = 208; + sif_ic_bw = 3; + sif_bb_bw = 0; + sif_deemp = 2; + sif_cfg_demod = (sound_format == 0) ? 0:2; + sif_fm_gain = 3; + } else if ((Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_I) + || (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_I)) { + sif_co_mx = 153; + sif_fi_mx = 56; + sif_ic_bw = 3; + sif_bb_bw = 0; + sif_deemp = 2; + sif_cfg_demod = (sound_format == 0) ? 0:2; + sif_fm_gain = 3; + } else if (Broadcast_Standard == + AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_BG_NICAM) { + sif_co_mx = 163; + sif_fi_mx = 40; + sif_ic_bw = 0; + sif_bb_bw = 0; + sif_deemp = 2; + sif_cfg_demod = (sound_format == 0) ? 0:2; + sif_fm_gain = 3; + } else if (Broadcast_Standard == + AML_ATV_DEMOD_VIDEO_MODE_PROP_SECAM_L) { + sif_co_mx = 159; + sif_fi_mx = 200; + sif_ic_bw = 3; + sif_bb_bw = 0; + sif_deemp = 0; + sif_cfg_demod = (sound_format == 0) ? 1:2; + sif_fm_gain = 5; + } else if ((Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_DK) + || (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_DK)) { + sif_co_mx = 159; + sif_fi_mx = 200; + sif_ic_bw = 3; + sif_bb_bw = 0; + sif_deemp = 2; + sif_cfg_demod = (sound_format == 0) ? 0:2; + sif_fm_gain = 3; + } else if (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_M) { + sif_co_mx = 182; + sif_fi_mx = 16; + sif_ic_bw = 1; + sif_bb_bw = 0; + sif_deemp = 1; + sif_cfg_demod = (sound_format == 0) ? 0:2; + sif_fm_gain = 3; + } + sif_fm_gain -= 2; /*avoid sound overflow@guanzhong*/ + /*FE PATH*/ + pr_info("ATV-DMD configure mixer\n"); + if (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_DTV) { + tmp_int = (Tuner_IF_Frequency/125000); + if (Tuner_Input_IF_inverted == 0x0) + mixer1 = -tmp_int; + else + mixer1 = tmp_int; + + mixer3 = 0; + mixer3_bypass = 0; + } else { + tmp_int = (Tuner_IF_Frequency/125000); + pr_info("ATV-DMD configure mixer 1\n"); + + if (Tuner_Input_IF_inverted == 0x0) + mixer1 = 0xe8 - tmp_int; + else + mixer1 = tmp_int - 0x18; + + pr_info("ATV-DMD configure mixer 2\n"); + mixer3 = 0x30; + mixer3_bypass = 0x1; + } + + pr_info("ATV-DMD configure mixer 3\n"); + atv_dmd_wr_byte(APB_BLOCK_ADDR_MIXER_1, 0x0, mixer1); + atv_dmd_wr_word(APB_BLOCK_ADDR_MIXER_3, 0x0, + (((mixer3 & 0xff) << 8) | (mixer3_bypass & 0xff))); + + if (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_SECAM_L) + atv_dmd_wr_long(APB_BLOCK_ADDR_ADC_SE, 0x0, 0x03180e0f); + else + atv_dmd_wr_long(APB_BLOCK_ADDR_ADC_SE, 0x0, 0x03150e0f); + if (amlatvdemod_devp->parm.tuner_id == AM_TUNER_R840) { + /*config pwm for tuner r840*/ + atv_dmd_wr_byte(APB_BLOCK_ADDR_ADC_SE, 1, 0xf); + } + + /*GP Filter*/ + pr_info("ATV-DMD configure GP_filter\n"); + if (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_DTV) { + cv = gp_cv_g1; + atv_dmd_wr_long(APB_BLOCK_ADDR_GP_VD_FLT, 0x0, + (0x08000000 | (cv & 0x7fffff))); + atv_dmd_wr_byte(APB_BLOCK_ADDR_GP_VD_FLT, 0x4, 0x04); + for (i = 0; i < 9; i = i + 1) { + /*super_coef = {gp_coeff_1[i*4],gp_coeff_1[i*4+1], + *gp_coeff_1[i*4+2],gp_coeff_1[i*4+3]}; + */ + super_coef0 = + (((gp_coeff_1[i * 4 + 2] & 0xfff) << 20) | + (gp_coeff_1[i * 4 + 3] & 0xfffff)); + super_coef1 = + (((gp_coeff_1[i * 4] & 0xf) << 28) | + ((gp_coeff_1[i * 4 + 1] & 0xfffff) << 8) | + ((gp_coeff_1[i * 4 + 2] >> 12) & 0xff)); + super_coef2 = ((gp_coeff_1[i * 4] >> 4) & 0xffff); + + /*atv_dmd_wr_long(APB_BLOCK_ADDR_GP_VD_FLT, + *0x8,super_coef[79:48]); + */ + /*atv_dmd_wr_long(APB_BLOCK_ADDR_GP_VD_FLT, + *0xC,super_coef[47:16]); + */ + /*atv_dmd_wr_word(APB_BLOCK_ADDR_GP_VD_FLT, + *0x10,super_coef[15:0]); + */ + atv_dmd_wr_long(APB_BLOCK_ADDR_GP_VD_FLT, 0x8, + (((super_coef2 & 0xffff) << 16) | + ((super_coef1 & 0xffff0000) >> 16))); + atv_dmd_wr_long(APB_BLOCK_ADDR_GP_VD_FLT, 0xC, + (((super_coef1 & 0xffff) << 16) | + ((super_coef0 & 0xffff0000) >> 16))); + atv_dmd_wr_word(APB_BLOCK_ADDR_GP_VD_FLT, 0x10, + (super_coef0 & 0xffff)); + atv_dmd_wr_byte(APB_BLOCK_ADDR_GP_VD_FLT, 0x05, i); + } + /*atv_dmd_wr_long + *(APB_BLOCK_ADDR_GP_VD_FLT,0x8,{gp_coeff_1[36],12'd0}); + */ + atv_dmd_wr_long(APB_BLOCK_ADDR_GP_VD_FLT, 0x8, + ((gp_coeff_1[36] & 0xfffff) << 12)); + atv_dmd_wr_byte(APB_BLOCK_ADDR_GP_VD_FLT, 0x05, 0x09); + + } else { + cv = gp_cv_g1 - gp_cv_g2; + atv_dmd_wr_long(APB_BLOCK_ADDR_GP_VD_FLT, 0x0, cv & 0x7fffff); + atv_dmd_wr_byte(APB_BLOCK_ADDR_GP_VD_FLT, 0x4, 0x00); + for (i = 0; i < 9; i = i + 1) { + /*super_coef = {gp_coeff_1[i*4],gp_coeff_1[i*4+1], + *gp_coeff_1[i*4+2],gp_coeff_1[i*4+3]}; + */ + super_coef0 = + (((gp_coeff_1[i * 4 + 2] & 0xfff) << 20) | + (gp_coeff_1[i * 4 + 3] & 0xfffff)); + super_coef1 = + (((gp_coeff_1[i * 4] & 0xf) << 28) | + ((gp_coeff_1[i * 4 + 1] & 0xfffff) << 8) | + ((gp_coeff_1[i * 4 + 2] >> 12) & 0xff)); + super_coef2 = ((gp_coeff_1[i * 4] >> 4) & 0xffff); + + /*atv_dmd_wr_long(APB_BLOCK_ADDR_GP_VD_FLT, + *0x8,super_coef[79:48]); + */ + /*atv_dmd_wr_long(APB_BLOCK_ADDR_GP_VD_FLT, + *0xC,super_coef[47:16]); + */ + /*atv_dmd_wr_word(APB_BLOCK_ADDR_GP_VD_FLT, + *0x10,super_coef[15:0]); + */ + atv_dmd_wr_long(APB_BLOCK_ADDR_GP_VD_FLT, 0x8, + (((super_coef2 & 0xffff) << 16) | + ((super_coef1 & 0xffff0000) >> 16))); + atv_dmd_wr_long(APB_BLOCK_ADDR_GP_VD_FLT, 0xC, + (((super_coef1 & 0xffff) << 16) | + ((super_coef0 & 0xffff0000) >> 16))); + atv_dmd_wr_word(APB_BLOCK_ADDR_GP_VD_FLT, 0x10, + (super_coef0 & 0xffff)); + atv_dmd_wr_byte(APB_BLOCK_ADDR_GP_VD_FLT, 0x05, i); + + /*atv_dmd_wr_long(APB_BLOCK_ADDR_GP_VD_FLT, + *0x8,{gp_coeff_1[36],12'd0}); + */ + } + atv_dmd_wr_long(APB_BLOCK_ADDR_GP_VD_FLT, 0x8, + ((gp_coeff_1[36] & 0xfffff) << 12)); + atv_dmd_wr_byte(APB_BLOCK_ADDR_GP_VD_FLT, 0x05, 9); + atv_dmd_wr_byte(APB_BLOCK_ADDR_GP_VD_FLT, 0x4, 0x01); + + for (i = 0; i < 9; i = i + 1) { + /*super_coef = {gp_coeff_2[i*4],gp_coeff_2[i*4+1], + *gp_coeff_2[i*4+2],gp_coeff_2[i*4+3]}; + */ + super_coef0 = + (((gp_coeff_2[i * 4 + 2] & 0xfff) << 20) | + (gp_coeff_2[i * 4 + 3] & 0xfffff)); + super_coef1 = + (((gp_coeff_2[i * 4] & 0xf) << 28) | + ((gp_coeff_2[i * 4 + 1] & 0xfffff) << 8) | + ((gp_coeff_2[i * 4 + 2] >> 12) & 0xff)); + super_coef2 = ((gp_coeff_2[i * 4] >> 4) & 0xffff); + + atv_dmd_wr_long(APB_BLOCK_ADDR_GP_VD_FLT, 0x8, + (((super_coef2 & 0xffff) << 16) | + ((super_coef1 & 0xffff0000) >> 16))); + atv_dmd_wr_long(APB_BLOCK_ADDR_GP_VD_FLT, 0xC, + (((super_coef1 & 0xffff) << 16) | + ((super_coef0 & 0xffff0000) >> 16))); + atv_dmd_wr_word(APB_BLOCK_ADDR_GP_VD_FLT, 0x10, + (super_coef0 & 0xffff)); + atv_dmd_wr_byte(APB_BLOCK_ADDR_GP_VD_FLT, 0x05, i); + } + + atv_dmd_wr_long(APB_BLOCK_ADDR_GP_VD_FLT, 0x8, + ((gp_coeff_2[36] & 0xfffff) << 12)); + atv_dmd_wr_byte(APB_BLOCK_ADDR_GP_VD_FLT, 0x05, 0x09); + } + + /*CRVY*/ + pr_info("ATV-DMD configure CRVY\n"); + if (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_DTV) { + crvy_reg_1 = 0xFF; + crvy_reg_2 = 0x00; + } else { + crvy_reg_1 = 0x04; + crvy_reg_2 = 0x01; + } + + atv_dmd_wr_byte(APB_BLOCK_ADDR_CARR_RCVY, 0x29, crvy_reg_1); + pr_info("ATV-DMD configure rcvy 2\n"); + pr_info("ATV-DMD configure rcvy, crvy_reg_2 = %x\n", crvy_reg_2); + atv_dmd_wr_byte(APB_BLOCK_ADDR_CARR_RCVY, 0x20, crvy_reg_2); + + /*SOUND SUPPRESS*/ + pr_info("ATV-DMD configure sound suppress\n"); + + if ((Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_DTV) || + (sound_format == 0)) + atv_dmd_wr_byte(APB_BLOCK_ADDR_SIF_VD_IF, 0x02, 0x01); + else + atv_dmd_wr_byte(APB_BLOCK_ADDR_SIF_VD_IF, 0x02, 0x00); + + /*SIF*/ + pr_info("ATV-DMD configure sif\n"); + if (!(Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_DTV)) { + atv_dmd_wr_byte(APB_BLOCK_ADDR_SIF_IC_STD, 0x03, sif_ic_bw); + atv_dmd_wr_byte(APB_BLOCK_ADDR_SIF_IC_STD, 0x01, sif_fi_mx); + atv_dmd_wr_byte(APB_BLOCK_ADDR_SIF_IC_STD, 0x02, sif_co_mx); + + atv_dmd_wr_long(APB_BLOCK_ADDR_SIF_STG_2, 0x00, + (((sif_bb_bw & 0xff) << 24) | + ((sif_deemp & 0xff) << 16) | 0x0500 | + sif_fm_gain)); + atv_dmd_wr_byte(APB_BLOCK_ADDR_SIF_STG_2, 0x06, sif_cfg_demod); + atv_dmd_wr_long(APB_BLOCK_ADDR_SIF_STG_2, 0x24, + (((sif_bb_bw & 0xff) << 24) | + 0xfffff)); + atv_dmd_wr_long(APB_BLOCK_ADDR_SIF_STG_2, 0x1c, 0x1f000); + } + + if (Broadcast_Standard != AML_ATV_DEMOD_VIDEO_MODE_PROP_DTV) { + if (sound_format == 0) { + tmp_int = 0; + atv_dmd_wr_long(APB_BLOCK_ADDR_SIF_STG_3, 0x00, + (0x01000000 | (tmp_int & 0xffffff))); + } else { + tmp_int = (256 - sif_co_mx) << 13; + atv_dmd_wr_long(APB_BLOCK_ADDR_SIF_STG_3, 0x00, + (tmp_int & 0xffffff)); + } + } + + if (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_DTV) { + atv_dmd_wr_long(APB_BLOCK_ADDR_IC_AGC, 0x00, 0x02040E0A); + atv_dmd_wr_word(APB_BLOCK_ADDR_IC_AGC, 0x04, 0x0F0D); + } else if (sound_format == 0) + atv_dmd_wr_byte(APB_BLOCK_ADDR_IC_AGC, 0x00, 0x04); + else if (Broadcast_Standard == + AML_ATV_DEMOD_VIDEO_MODE_PROP_SECAM_L) { + atv_dmd_wr_long(APB_BLOCK_ADDR_IC_AGC, 0x00, 0x0003140A); + atv_dmd_wr_word(APB_BLOCK_ADDR_IC_AGC, 0x04, 0x1244); + } else { + atv_dmd_wr_long(APB_BLOCK_ADDR_IC_AGC, 0x00, 0x00040E0A); + atv_dmd_wr_word(APB_BLOCK_ADDR_IC_AGC, 0x04, 0x0D68); + } + + /*VAGC*/ + pr_info("ATV-DMD configure vagc\n"); + atv_dmd_wr_long(APB_BLOCK_ADDR_VDAGC, 0x48, 0x9B6F2C00); + /*bw select mode*/ + atv_dmd_wr_byte(APB_BLOCK_ADDR_VDAGC, 0x37, 0x1C); + /*disable prefilter*/ + + if (Broadcast_Standard == AML_ATV_DEMOD_VIDEO_MODE_PROP_SECAM_L) { + atv_dmd_wr_word(APB_BLOCK_ADDR_VDAGC, 0x44, 0x4450); + atv_dmd_wr_byte(APB_BLOCK_ADDR_VDAGC, 0x46, 0x44); + atv_dmd_wr_long(APB_BLOCK_ADDR_VDAGC, 0x4, 0x3E04FC); + atv_dmd_wr_word(APB_BLOCK_ADDR_VDAGC, 0x3C, 0x4848); + atv_dmd_wr_byte(APB_BLOCK_ADDR_VDAGC, 0x3E, 0x48); + } else { + atv_dmd_wr_word(APB_BLOCK_ADDR_VDAGC, 0x44, 0xB800); + atv_dmd_wr_byte(APB_BLOCK_ADDR_VDAGC, 0x46, 0x08); + atv_dmd_wr_long(APB_BLOCK_ADDR_VDAGC, 0x4, 0x3C04FC); + atv_dmd_wr_word(APB_BLOCK_ADDR_VDAGC, 0x3C, 0x1818); + atv_dmd_wr_byte(APB_BLOCK_ADDR_VDAGC, 0x3E, 0x10); + } + + /*tmp_real = $itor(Hz_Freq)/0.23841858; //TODO*/ + /*tmp_int = $rtoi(tmp_real); //TODO*/ + /*tmp_int = Hz_Freq/0.23841858; //TODO*/ + /*tmp_int_2 = ((unsigned long)15625)*10000/23841858;*/ + /*tmp_int_2 = ((unsigned long)Hz_Freq)*10000/23841858;*/ + atv_dmd_wr_word(APB_BLOCK_ADDR_VDAGC, 0x10, + (freq_hz_cvrt >> 8) & 0xffff); + atv_dmd_wr_byte(APB_BLOCK_ADDR_VDAGC, 0x12, (freq_hz_cvrt & 0xff)); + + /*OUTPUT STAGE*/ + pr_info("ATV-DMD configure output stage\n"); + if (Broadcast_Standard != AML_ATV_DEMOD_VIDEO_MODE_PROP_DTV) { + atv_dmd_wr_byte(APB_BLOCK_ADDR_DAC_UPS, 0x0, 0x00); + atv_dmd_wr_byte(APB_BLOCK_ADDR_DAC_UPS, 0x1, 0x40); + atv_dmd_wr_byte(APB_BLOCK_ADDR_DAC_UPS, 0x2, 0x40); + atv_dmd_wr_byte(APB_BLOCK_ADDR_DAC_UPS, 0x4, 0xFA); + atv_dmd_wr_byte(APB_BLOCK_ADDR_DAC_UPS, 0x5, 0xFA); + } + + /*GDE FILTER*/ + pr_info("ATV-DMD configure gde filter\n"); + if (GDE_Curve == 0) { + gd_coeff[0] = 0x020; /*12'sd32;*/ + gd_coeff[1] = 0xf5f; /*-12'sd161;*/ + gd_coeff[2] = 0x1fe; /*12'sd510;*/ + gd_coeff[3] = 0xc0b; /*-12'sd1013;*/ + gd_coeff[4] = 0x536; /*12'sd1334;*/ + gd_coeff[5] = 0xb34; /*-12'sd1228;*/ + gd_bypass = 0x1; + } else if (GDE_Curve == 1) { + gd_coeff[0] = 0x8; /*12'sd8;*/ + gd_coeff[1] = 0xfd5; /*-12'sd43;*/ + gd_coeff[2] = 0x8d; /*12'sd141;*/ + gd_coeff[3] = 0xe69; /*-12'sd407;*/ + gd_coeff[4] = 0x1f1; /*12'sd497;*/ + gd_coeff[5] = 0xe7e; /*-12'sd386;*/ + gd_bypass = 0x1; + } else if (GDE_Curve == 2) { + gd_coeff[0] = 0x35; /*12'sd53;*/ + gd_coeff[1] = 0xf41; /*-12'sd191;*/ + gd_coeff[2] = 0x68; /*12'sd104;*/ + gd_coeff[3] = 0xea5; /*-12'sd347;*/ + gd_coeff[4] = 0x322; /*12'sd802;*/ + gd_coeff[5] = 0x1bb; /*12'sd443;*/ + gd_bypass = 0x1; + } else if (GDE_Curve == 3) { + gd_coeff[0] = 0xf; /*12'sd15;*/ + gd_coeff[1] = 0xfb5; /*-12'sd75;*/ + gd_coeff[2] = 0xcc; /*12'sd204;*/ + gd_coeff[3] = 0xe51; + gd_coeff[4] = 0x226; /*12'sd550;*/ + gd_coeff[5] = 0xd02; + gd_bypass = 0x1; + } else + gd_bypass = 0x0; + + if (gd_bypass == 0x0) + atv_dmd_wr_byte(APB_BLOCK_ADDR_GDE_EQUAL, 0x0D, gd_bypass); + else { + for (i = 0; i < 6; i = i + 1) + atv_dmd_wr_word(APB_BLOCK_ADDR_GDE_EQUAL, i << 1, + gd_coeff[i]); + atv_dmd_wr_byte(APB_BLOCK_ADDR_GDE_EQUAL, 0x0C, 0x01); + atv_dmd_wr_byte(APB_BLOCK_ADDR_GDE_EQUAL, 0x0D, gd_bypass); + } + + /*PWM*/ + pr_info("ATV-DMD configure pwm\n"); + atv_dmd_wr_long(APB_BLOCK_ADDR_AGC_PWM, 0x00, 0x1f40); /*4KHz*/ + atv_dmd_wr_long(APB_BLOCK_ADDR_AGC_PWM, 0x04, 0xc8); + /*26 dB dynamic range*/ + atv_dmd_wr_byte(APB_BLOCK_ADDR_AGC_PWM, 0x09, 0xa); + if (amlatvdemod_devp->parm.tuner_id == AM_TUNER_R840) { + /*config pwm for tuner r840*/ + atv_dmd_wr_long(APB_BLOCK_ADDR_AGC_PWM, 0, 0xc80); + /* guanzhong for Tuner AGC shock */ + atv_dmd_wr_long(APB_BLOCK_ADDR_AGC_PWM, 0x08, 0x46180200); + /* atv_dmd_wr_byte(APB_BLOCK_ADDR_ADC_SE,1,0xf);//Kd = 0xf */ + } +} + +void retrieve_adc_power(int *adc_level) +{ + *adc_level = atv_dmd_rd_long(APB_BLOCK_ADDR_ADC_SE, 0x0c); + /*adc_level = adc_level/32768*100;*/ + *adc_level = (*adc_level) * 100 / 32768; +} + +void retrieve_vpll_carrier_lock(int *lock) +{ + unsigned int data; + + data = atv_dmd_rd_byte(APB_BLOCK_ADDR_CARR_RCVY, 0x43); + *lock = (data & 0x1); +} +int retrieve_vpll_carrier_afc(void) +{ + int data_ret, pll_lock, field_lock, line_lock, line_lock_strong; + unsigned int data_h, data_l, data_exg = 0; + + pll_lock = atv_dmd_rd_byte(APB_BLOCK_ADDR_CARR_RCVY, 0x43)&0x1; + field_lock = atv_dmd_rd_byte(APB_BLOCK_ADDR_VDAGC, 0x4f)&0x4; + line_lock = atv_dmd_rd_byte(APB_BLOCK_ADDR_VDAGC, 0x4f)&0x10; + line_lock_strong = atv_dmd_rd_byte(APB_BLOCK_ADDR_VDAGC, 0x4f)&0x8; + /* if((atv_dmd_rd_byte(APB_BLOCK_ADDR_CARR_RCVY,0x43)&0x1) == 1){ */ + if ((pll_lock == 1) || (line_lock == 0x10)) { + /*if pll unlock, afc is invalid*/ + data_ret = 0xffff;/* 500; */ + return data_ret; + } + data_h = atv_dmd_rd_byte(APB_BLOCK_ADDR_CARR_RCVY, 0x40); + data_l = atv_dmd_rd_byte(APB_BLOCK_ADDR_CARR_RCVY, 0x41); + data_exg = ((data_h&0x7) << 8) | data_l; + if (data_h&0x8) { + data_ret = (((~data_exg)&0x7ff) - 1); + data_ret = data_ret*488*(-1)/1000; + } else { + data_ret = data_exg; + data_ret = data_ret*488/1000; + } + if ((abs(data_ret) < 50) && (line_lock_strong == 0x8) && + (field_lock == 0x4)) { + data_ret = 100; + return data_ret; + } + return data_ret; +} +void set_pll_lpf(unsigned int lock) +{ + atv_dmd_wr_byte(APB_BLOCK_ADDR_CARR_RCVY, 0x24, lock); +} + +void retrieve_frequency_offset(int *freq_offset) +{ + /*unsigned int data; + *data = atv_dmd_rd_word(APB_BLOCK_ADDR_CARR_RCVY,0x40); + **freq_offset = (int)data; + */ + unsigned int data_h, data_l, data_exg; + int data_ret; + + data_h = atv_dmd_rd_byte(APB_BLOCK_ADDR_CARR_RCVY, 0x40); + data_l = atv_dmd_rd_byte(APB_BLOCK_ADDR_CARR_RCVY, 0x41); + data_exg = ((data_h&0x7)<<8) | data_l; + if (data_h&0x8) { + data_ret = (((~data_exg) & 0x7ff) - 1); + data_ret = data_ret*(-1); + /* data_ret = data_ret*488*(-1) /1000; */ + } else + data_ret = data_exg;/* data_ret = data_ret*488/100; */ + *freq_offset = data_ret; +} +EXPORT_SYMBOL(retrieve_frequency_offset); +void retrieve_video_lock(int *lock) +{ + unsigned int data, wlock, slock; + + data = atv_dmd_rd_byte(APB_BLOCK_ADDR_VDAGC, 0x4f); + wlock = data & 0x10; + slock = data & 0x80; + *lock = wlock & slock; +} + +void retrieve_fh_frequency(int *fh) +{ + unsigned long data1, data2; + + data1 = atv_dmd_rd_word(APB_BLOCK_ADDR_VDAGC, 0x58); + data2 = atv_dmd_rd_long(APB_BLOCK_ADDR_VDAGC, 0x10); + data1 = data1 >> 11; + data2 = data2 >> 3; + *fh = data1 + data2; +} +/*tune mix to adapt afc*/ +void atvdemod_afc_tune(void) +{ + /* int adc_level,lock,freq_offset,fh; */ + int freq_offset, lock, mix1_freq_cur, delta_mix1_freq; + + /* retrieve_adc_power(&adc_level); */ + /* pr_info("adc_level: 0x%x\n",adc_level); */ + retrieve_vpll_carrier_lock(&lock); + mix1_freq_cur = atv_dmd_rd_byte(APB_BLOCK_ADDR_MIXER_1, 0x0); + delta_mix1_freq = abs(mix1_freq_cur - mix1_freq); + if ((lock&0x1) == 0) + pr_info("%s visual carrier lock:locked\n", __func__); + else + pr_info("%s visual carrier lock:unlocked\n", __func__); + /* set_pll_lpf(lock); */ + retrieve_frequency_offset(&freq_offset); + freq_offset = freq_offset*488/1000; + /* pr_info("visual carrier offset:%d Hz\n", + *freq_offset*48828125/100000); + */ + /* retrieve_video_lock(&lock); */ + if ((lock&0x1) == 1) { + if (delta_mix1_freq == atvdemod_afc_range) + atv_dmd_wr_byte(APB_BLOCK_ADDR_MIXER_1, 0x0, mix1_freq); + else if ((freq_offset >= atvdemod_afc_offset) && + (delta_mix1_freq < atvdemod_afc_range)) + atv_dmd_wr_byte(APB_BLOCK_ADDR_MIXER_1, 0x0, + mix1_freq_cur-1); + else if ((freq_offset <= (-1)*atvdemod_afc_offset) && + (delta_mix1_freq < atvdemod_afc_range-1)) + atv_dmd_wr_byte(APB_BLOCK_ADDR_MIXER_1, 0x0, + mix1_freq_cur+1); + /* pr_info("video lock:locked\n"); */ + } + /* retrieve_fh_frequency(&fh); */ + /* pr_info("horizontal frequency:%d Hz\n",fh*190735/100000); */ +} +static enum amlatvdemod_snr_level_e aml_atvdemod_get_snr_level(void) +{ + unsigned int snr_val, i, snr_d[8]; + enum amlatvdemod_snr_level_e ret; + unsigned long fsnr; + + snr_val = atv_dmd_rd_long(APB_BLOCK_ADDR_VDAGC, 0x50)>>8; + fsnr = snr_val; + for (i = 1; i < 8; i++) { + snr_d[i] = snr_d[i-1]; + fsnr = fsnr + snr_d[i]; + } + snr_d[0] = snr_val; + fsnr = fsnr >> 3; + if (fsnr < 316) + ret = high; + else if (fsnr < 31600) + ret = ok_plus; + else if (fsnr < 158000) + ret = ok_minus; + else if (fsnr < 700000) + ret = low; + else + ret = very_low; + return ret; +} + +void atvdemod_monitor_serice(void) +{ + enum amlatvdemod_snr_level_e snr_level; + unsigned int vagc_bw_typ, vagc_bw_fast, vpll_kptrack, vpll_kitrack; + unsigned int agc_register, vfmat_reg, agc_pll_kptrack, agc_pll_kitrack; + /*1.get current snr*/ + snr_level = aml_atvdemod_get_snr_level(); + /*2.*/ + if (snr_level > very_low) { + vagc_bw_typ = 0x1818; + vagc_bw_fast = (snr_level == low) ? 0x18:0x10; + vpll_kptrack = 0x05; + vpll_kitrack = 0x0c; + agc_pll_kptrack = 0x6; + agc_pll_kitrack = 0xc; + } else { + vagc_bw_typ = 0x6f6f; + vagc_bw_fast = 0x6f; + vpll_kptrack = 0x06; + vpll_kitrack = 0x0e; + agc_pll_kptrack = 0x8; + agc_pll_kitrack = 0xf; + } + atv_dmd_wr_word(APB_BLOCK_ADDR_VDAGC, 0x3c, vagc_bw_typ); + atv_dmd_wr_byte(APB_BLOCK_ADDR_VDAGC, 0x3e, vagc_bw_fast); + atv_dmd_wr_byte(APB_BLOCK_ADDR_CARR_RCVY, 0x23, vpll_kptrack); + atv_dmd_wr_byte(APB_BLOCK_ADDR_CARR_RCVY, 0x24, vpll_kitrack); + atv_dmd_wr_byte(APB_BLOCK_ADDR_VDAGC, 0x0c, + ((atv_dmd_rd_byte(APB_BLOCK_ADDR_VDAGC, 0x0c) & 0xf0)| + agc_pll_kptrack)); + atv_dmd_wr_byte(APB_BLOCK_ADDR_VDAGC, 0x0d, + ((atv_dmd_rd_byte(APB_BLOCK_ADDR_VDAGC, 0x0d) & 0xf0)| + agc_pll_kitrack)); + /*3.*/ + agc_register = atv_dmd_rd_long(APB_BLOCK_ADDR_VDAGC, 0x28); + if (snr_level < low) { + agc_register = ((agc_register&0xff80fe03) | (25 << 16) | + (15 << 2)); + atv_dmd_wr_long(APB_BLOCK_ADDR_VDAGC, 0x28, agc_register); + } else if (snr_level > low) { + agc_register = ((agc_register&0xff80fe03) | (38 << 16) | + (30 << 2)); + atv_dmd_wr_long(APB_BLOCK_ADDR_VDAGC, 0x28, agc_register); + } + /*4.*/ + if (snr_level < ok_minus) + atv_dmd_wr_byte(APB_BLOCK_ADDR_VDAGC, 0x47, + (atv_dmd_rd_byte(APB_BLOCK_ADDR_VDAGC, 0x47) & 0x7f)); + else + atv_dmd_wr_byte(APB_BLOCK_ADDR_VDAGC, 0x47, + (atv_dmd_rd_byte(APB_BLOCK_ADDR_VDAGC, 0x47) | 0x80)); + /*5.vformat*/ + if (snr_level < ok_minus) { + if (atv_dmd_rd_byte(APB_BLOCK_ADDR_VFORMAT, 0xe) != 0xf) + atv_dmd_wr_byte(APB_BLOCK_ADDR_VFORMAT, 0xe, 0xf); + } else if (snr_level > ok_minus) { + vfmat_reg = atv_dmd_rd_word(APB_BLOCK_ADDR_VFORMAT, 0x16); + if ((vfmat_reg << 4) < 0xf000) { + if (atv_dmd_rd_byte(APB_BLOCK_ADDR_VFORMAT, 0xe) == + 0x0f) + atv_dmd_wr_byte(APB_BLOCK_ADDR_VFORMAT, 0xe, + 0x6); + else + atv_dmd_wr_byte(APB_BLOCK_ADDR_VFORMAT, 0xe, + 0x6); + } + } else { + if (atv_dmd_rd_byte(APB_BLOCK_ADDR_VFORMAT, 0xe) == 0x0f) + atv_dmd_wr_byte(APB_BLOCK_ADDR_VFORMAT, 0xe, 0xe); + else + atv_dmd_wr_byte(APB_BLOCK_ADDR_VFORMAT, 0xe, 0xe); + } +} + +static int atvdemod_get_snr(struct dvb_frontend *fe) +{ + unsigned int snr_val = 0; + int ret = 0; + + snr_val = atv_dmd_rd_long(APB_BLOCK_ADDR_VDAGC, 0x50) >> 8; + /* snr_val:900000~0xffffff,ret:5~15 */ + if (snr_val > 900000) + ret = 15 - (snr_val - 900000)*10/(0xffffff - 900000); + /* snr_val:158000~900000,ret:15~30 */ + else if (snr_val > 158000) + ret = 30 - (snr_val - 158000)*15/(900000 - 158000); + /* snr_val:31600~158000,ret:30~50 */ + else if (snr_val > 31600) + ret = 50 - (snr_val - 31600)*20/(158000 - 31600); + /* snr_val:316~31600,ret:50~80 */ + else if (snr_val > 316) + ret = 80 - (snr_val - 316)*30/(31600 - 316); + /* snr_val:0~316,ret:80~100 */ + else + ret = 100 - (316 - snr_val)*20/316; + return ret; +} + +void atvdemod_det_snr_serice(void) +{ + snr_val = atvdemod_get_snr(NULL); +} + +void atvdemod_timer_handler(unsigned long arg) +{ + if (atvdemod_timer_en == 0) + return; + atvdemod_timer.expires = jiffies + ATVDEMOD_INTERVAL*10;/*100ms timer*/ + add_timer(&atvdemod_timer); + if (atvdemod_afc_en) + atvdemod_afc_tune(); + if (atvdemod_monitor_en) + atvdemod_monitor_serice(); + if (audio_det_en) + aml_atvdemod_overmodule_det(); + if (atvdemod_det_snr_en) + atvdemod_det_snr_serice(); +} + +int atvdemod_clk_init(void) +{ + /* clocks_set_hdtv (); */ + /* 1.set system clock */ +#if 0 /* now set pll in tvafe_general.c */ + if (is_meson_txl_cpu()) { + amlatvdemod_hiu_reg_write(HHI_VDAC_CNTL0, 0x6e0201); + amlatvdemod_hiu_reg_write(HHI_VDAC_CNTL1, 0x8); + /* for TXL(T962) */ + pr_err("%s in TXL\n", __func__); + + /* W_HIU_REG(HHI_ADC_PLL_CNTL, 0x30c54260); */ + #if 0 + W_HIU_REG(HHI_ADC_PLL_CNTL, 0x30f14250); + W_HIU_REG(HHI_ADC_PLL_CNTL1, 0x22000442); + W_HIU_REG(HHI_ADC_PLL_CNTL2, 0x5ba00380); + W_HIU_REG(HHI_ADC_PLL_CNTL3, 0xac6a2114); + W_HIU_REG(HHI_ADC_PLL_CNTL4, 0x02953004); + W_HIU_REG(HHI_ADC_PLL_CNTL5, 0x00030a00); + W_HIU_REG(HHI_ADC_PLL_CNTL6, 0x00005000); + W_HIU_REG(HHI_ADC_PLL_CNTL3, 0x2c6a2114); + #else /* get from feijun 2015/07/19 */ + W_HIU_REG(HHI_ADC_PLL_CNTL3, 0x4a6a2110); + W_HIU_REG(HHI_ADC_PLL_CNTL, 0x30f14250); + W_HIU_REG(HHI_ADC_PLL_CNTL1, 0x22000442); + /*0x5ba00380 from pll;0x5ba00384 clk + *form crystal + */ + W_HIU_REG(HHI_ADC_PLL_CNTL2, 0x5ba00384); + W_HIU_REG(HHI_ADC_PLL_CNTL3, 0x4a6a2110); + W_HIU_REG(HHI_ADC_PLL_CNTL4, 0x02913004); + W_HIU_REG(HHI_ADC_PLL_CNTL5, 0x00034a00); + W_HIU_REG(HHI_ADC_PLL_CNTL6, 0x00005000); + W_HIU_REG(HHI_ADC_PLL_CNTL3, 0xca6a2110); + W_HIU_REG(HHI_ADC_PLL_CNTL3, 0x4a6a2110); + #endif + W_HIU_REG(HHI_DADC_CNTL, 0x00102038); + W_HIU_REG(HHI_DADC_CNTL2, 0x00000406); + W_HIU_REG(HHI_DADC_CNTL3, 0x00082183); + + } else { + W_HIU_REG(HHI_ADC_PLL_CNTL3, 0xca2a2110); + W_HIU_REG(HHI_ADC_PLL_CNTL4, 0x2933800); + W_HIU_REG(HHI_ADC_PLL_CNTL, 0xe0644220); + W_HIU_REG(HHI_ADC_PLL_CNTL2, 0x34e0bf84); + W_HIU_REG(HHI_ADC_PLL_CNTL3, 0x4a2a2110); + + W_HIU_REG(HHI_ATV_DMD_SYS_CLK_CNTL, 0x80); + /* TVFE reset */ + W_HIU_BIT(RESET1_REGISTER, 1, 7, 1); + } +#endif + W_HIU_REG(HHI_ATV_DMD_SYS_CLK_CNTL, 0x80); + + /* read_version_register(); */ + + /*2.set atv demod top page control register*/ + atv_dmd_input_clk_32m(); + atv_dmd_wr_long(APB_BLOCK_ADDR_TOP, ATV_DMD_TOP_CTRL, 0x1037); + atv_dmd_wr_long(APB_BLOCK_ADDR_TOP, (ATV_DMD_TOP_CTRL1 << 2), 0x1f); + + /*3.configure atv demod*/ + check_communication_interface(); + power_on_receiver(); + pr_err("%s done\n", __func__); + + return 0; +} + +int atvdemod_init(void) +{ + /* unsigned long data32; */ + if (atvdemod_timer_en == 1) { + if (timer_init_flag == 1) { + del_timer_sync(&atvdemod_timer); + timer_init_flag = 0; + } + } + + /* 1.set system clock when atv enter*/ + + configure_receiver(broad_std, if_freq, if_inv, gde_curve, sound_format); + atv_dmd_misc(); + /*4.software reset*/ + atv_dmd_soft_reset(); + atv_dmd_soft_reset(); + atv_dmd_soft_reset(); + atv_dmd_soft_reset(); + + /* ????? + *while (!all_lock) { + * data32 = atv_dmd_rd_long(APB_BLOCK_ADDR_VDAGC,0x13<<2); + * if ((data32 & 0x1c) == 0x0) { + * all_lock = 1; + * } + * delay_us(400); + *} + */ + #if 1/* temp mark */ + if (atvdemod_timer_en == 1) { + /*atvdemod timer handler*/ + init_timer(&atvdemod_timer); + /* atvdemod_timer.data = (ulong) devp; */ + atvdemod_timer.function = atvdemod_timer_handler; + /* after 3s enable demod auto detect */ + atvdemod_timer.expires = jiffies + ATVDEMOD_INTERVAL*300; + add_timer(&atvdemod_timer); + mix1_freq = atv_dmd_rd_byte(APB_BLOCK_ADDR_MIXER_1, 0x0); + timer_init_flag = 1; + } + #endif + pr_info("%s done\n", __func__); + return 0; +} +void atvdemod_uninit(void) +{ + /* del the timer */ + if (atvdemod_timer_en == 1) { + if (timer_init_flag == 1) { + del_timer_sync(&atvdemod_timer); + timer_init_flag = 0; + } + } +} + +void atv_dmd_set_std(void) +{ + v4l2_std_id ptstd = amlatvdemod_devp->parm.std; + /* set broad standard of tuner*/ + if ((ptstd & V4L2_COLOR_STD_PAL) && ((ptstd & V4L2_STD_B) || + (ptstd & V4L2_STD_G))) { + amlatvdemod_devp->fre_offset = 2250000; + freq_hz_cvrt = AML_ATV_DEMOD_FREQ_50HZ_VERT; + broad_std = AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_BG; + if_freq = 3250000; + gde_curve = 2; + } else if ((ptstd & V4L2_COLOR_STD_PAL) && (ptstd & V4L2_STD_DK)) { + amlatvdemod_devp->fre_offset = 2250000; + freq_hz_cvrt = AML_ATV_DEMOD_FREQ_50HZ_VERT; + if_freq = 3250000; + broad_std = AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_DK; + gde_curve = 3; + } else if ((ptstd & V4L2_COLOR_STD_PAL) && (ptstd & V4L2_STD_PAL_M)) { + amlatvdemod_devp->fre_offset = 2250000; + freq_hz_cvrt = AML_ATV_DEMOD_FREQ_60HZ_VERT; + broad_std = AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_M; + if_freq = 4250000; + gde_curve = 0; + } else if ((ptstd & V4L2_COLOR_STD_NTSC) && (ptstd & V4L2_STD_NTSC_M)) { + amlatvdemod_devp->fre_offset = 1750000; + freq_hz_cvrt = AML_ATV_DEMOD_FREQ_60HZ_VERT; + if_freq = 4250000; + broad_std = AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC; + gde_curve = 0; + } else if ((ptstd & V4L2_COLOR_STD_NTSC) && (ptstd & V4L2_STD_DK)) { + amlatvdemod_devp->fre_offset = 1750000; + freq_hz_cvrt = AML_ATV_DEMOD_FREQ_60HZ_VERT; + if_freq = 4250000; + broad_std = AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_DK; + gde_curve = 0; + } else if ((ptstd & V4L2_COLOR_STD_NTSC) && (ptstd & V4L2_STD_BG)) { + amlatvdemod_devp->fre_offset = 1750000; + freq_hz_cvrt = AML_ATV_DEMOD_FREQ_60HZ_VERT; + if_freq = 4250000; + broad_std = AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_BG; + gde_curve = 0; + } else if ((ptstd & V4L2_COLOR_STD_NTSC) && (ptstd & V4L2_STD_PAL_I)) { + amlatvdemod_devp->fre_offset = 1750000; + freq_hz_cvrt = AML_ATV_DEMOD_FREQ_60HZ_VERT; + if_freq = 4250000; + broad_std = AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_I; + gde_curve = 0; + } else if ((ptstd & V4L2_COLOR_STD_NTSC) && + (ptstd & V4L2_STD_NTSC_M_JP)) { + amlatvdemod_devp->fre_offset = 1750000; + freq_hz_cvrt = AML_ATV_DEMOD_FREQ_50HZ_VERT; + broad_std = AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_J; + if_freq = 4250000; + gde_curve = 0; + } else if ((ptstd & V4L2_COLOR_STD_PAL) && (ptstd & V4L2_STD_PAL_I)) { + amlatvdemod_devp->fre_offset = 2750000; + freq_hz_cvrt = AML_ATV_DEMOD_FREQ_50HZ_VERT; + broad_std = AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_I; + if_freq = 3250000; + gde_curve = 4; + } else if (ptstd & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { + amlatvdemod_devp->fre_offset = 2750000; + freq_hz_cvrt = AML_ATV_DEMOD_FREQ_50HZ_VERT; + broad_std = AML_ATV_DEMOD_VIDEO_MODE_PROP_SECAM_L; + gde_curve = 4; + } + if (amlatvdemod_devp->parm.tuner_id == AM_TUNER_R840) { + if_freq = amlatvdemod_devp->parm.if_freq; + if_inv = amlatvdemod_devp->parm.if_inv; + } else if (amlatvdemod_devp->parm.tuner_id == AM_TUNER_MXL661) { + if_freq = amlatvdemod_devp->parm.if_freq; + if_inv = amlatvdemod_devp->parm.if_inv; + } else if (amlatvdemod_devp->parm.tuner_id == AM_TUNER_SI2151) { + if_freq = amlatvdemod_devp->parm.if_freq; + if_inv = amlatvdemod_devp->parm.if_inv; + } + pr_info + ("[atvdemod..]%s: broad_std %d,freq_hz_cvrt:0x%x,fre_offset:%d.\n", + __func__, broad_std, freq_hz_cvrt, amlatvdemod_devp->fre_offset); + if (atvdemod_init()) + pr_info("[atvdemod..]%s: atv restart error.\n", __func__); +} + +int aml_audiomode_autodet(struct dvb_frontend *fe) +{ + unsigned long carrier_power = 0; + unsigned long carrier_power_max = 0; + unsigned long carrier_power_average_max = 0; + unsigned long carrier_power_average[4] = {0}; + unsigned long reg_addr = 0x03, temp_data; + int carrier_lock_count = 0; + int lock = 0; + int broad_std_final = 0; + int num = 0, i = 0, final_id = 0; + int delay_ms = 10, delay_ms_default = 10; + int cur_std = ID_PAL_DK; + struct dtv_frontend_properties + *p = fe != NULL ? &fe->dtv_property_cache:NULL; +#if 0 + temp_data = atv_dmd_rd_reg(APB_BLOCK_ADDR_SIF_STG_2, 0x02); + temp_data = temp_data | 0x80;/* 0x40 */ + atv_dmd_wr_reg(APB_BLOCK_ADDR_SIF_STG_2, 0x02, temp_data); +#endif + + switch (broad_std) { + case AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_DK: + case AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_I: + case AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_BG: + case AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_M: + broad_std = AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_M; + break; + case AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_DK: + case AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_I: + case AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_BG: + case AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_M: + case AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC: + + broad_std = AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_M; + atvdemod_init(); + temp_data = atv_dmd_rd_reg(APB_BLOCK_ADDR_SIF_STG_2, 0x02); + temp_data = temp_data & (~0x80); /* 0xbf; */ + atv_dmd_wr_reg(APB_BLOCK_ADDR_SIF_STG_2, 0x02, temp_data); + /* pr_err("%s, SECAM ,audio set SECAM_L\n", __func__); */ + return broad_std; + + case AML_ATV_DEMOD_VIDEO_MODE_PROP_SECAM_L: + case AML_ATV_DEMOD_VIDEO_MODE_PROP_SECAM_DK2: + case AML_ATV_DEMOD_VIDEO_MODE_PROP_SECAM_DK3: + broad_std = AML_ATV_DEMOD_VIDEO_MODE_PROP_SECAM_L; + atvdemod_init(); + temp_data = atv_dmd_rd_reg(APB_BLOCK_ADDR_SIF_STG_2, 0x02); + + temp_data = temp_data & (~0x80); /* 0xbf; */ + + atv_dmd_wr_reg(APB_BLOCK_ADDR_SIF_STG_2, 0x02, temp_data); + /* pr_err("%s, SECAM ,audio set SECAM_L\n", __func__); */ + return broad_std; + default: + pr_err("unsupport broadcast_standard!!!\n"); + temp_data = atv_dmd_rd_reg(APB_BLOCK_ADDR_SIF_STG_2, 0x02); + temp_data = temp_data & (~0x80); /* 0xbf; */ + atv_dmd_wr_reg(APB_BLOCK_ADDR_SIF_STG_2, 0x02, temp_data); + return broad_std; + } + /* ----------------read carrier_power--------------------- */ + /* SIF_STG_2[0x09],address 0x03 */ + while (1) { + if (num >= 4) { + temp_data = + atv_dmd_rd_reg(APB_BLOCK_ADDR_SIF_STG_2, 0x02); + temp_data = temp_data & (~0x80); + atv_dmd_wr_reg(APB_BLOCK_ADDR_SIF_STG_2, 0x02, + temp_data); + carrier_power_max = carrier_power_average[0]; + for (i = 0; i < ID_MAX; i++) { + if (carrier_power_max + < carrier_power_average[i]) { + carrier_power_max = + carrier_power_average[i]; + final_id = i; + } + } + switch (final_id) { + case ID_PAL_I: + broad_std_final = + AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_I; + break; + case ID_PAL_BG: + broad_std_final = + AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_BG; + break; + case ID_PAL_M: + broad_std_final = + AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_M; + break; + case ID_PAL_DK: + broad_std_final = + AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_DK; + break; + } + carrier_power_average_max = carrier_power_max; + broad_std = broad_std_final; + pr_err("%s:broad_std:%d,carrier_power_average_max:%lu\n", + __func__, broad_std, carrier_power_average_max); + if (carrier_power_average_max < 150) + pr_err("%s,carrier too low error\n", __func__); + if (broad_std == AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_M) { + /*the max except palm*/ + carrier_power_average[final_id] = 0; + final_id = 0; + carrier_power_max = carrier_power_average[0]; + for (i = 0; i < ID_MAX; i++) { + if (carrier_power_max + < carrier_power_average[i]) { + carrier_power_max = + carrier_power_average[i]; + final_id = i; + } + } + switch (final_id) { + case ID_PAL_I: + broad_std_except_pal_m = + AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_I; + break; + case ID_PAL_BG: + broad_std_except_pal_m = + AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_BG; + break; + case ID_PAL_DK: + broad_std_except_pal_m = + AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_DK; + break; + } + } + if (p != NULL) { + p->analog.std = V4L2_COLOR_STD_PAL; + switch (broad_std) { + case AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_DK: + p->analog.std |= V4L2_STD_PAL_DK; + p->analog.audmode = V4L2_STD_PAL_DK; + break; + case AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_I: + p->analog.std |= V4L2_STD_PAL_I; + p->analog.audmode = V4L2_STD_PAL_I; + break; + case AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_BG: + p->analog.std |= V4L2_STD_PAL_BG; + p->analog.audmode = V4L2_STD_PAL_BG; + break; + case AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_M: + p->analog.std |= V4L2_STD_PAL_M; + p->analog.audmode = V4L2_STD_PAL_M; + break; + default: + p->analog.std |= V4L2_STD_PAL_DK; + p->analog.audmode = V4L2_STD_PAL_DK; + } + p->frequency += 1; + fe->ops.set_frontend(fe); + } + return broad_std; + } + switch (broad_std) { + case AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_DK: + broad_std = AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_I; + cur_std = ID_PAL_I; + if (p != NULL) { + p->analog.std = + V4L2_COLOR_STD_PAL | V4L2_STD_PAL_I; + p->frequency += 1; + p->analog.audmode = V4L2_STD_PAL_I; + } + delay_ms = delay_ms_default; + break; + case AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_I: + broad_std = AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_BG; + cur_std = ID_PAL_BG; + if (p != NULL) { + p->analog.std = + V4L2_COLOR_STD_PAL | V4L2_STD_PAL_BG; + p->frequency += 1; + p->analog.audmode = V4L2_STD_PAL_BG; + } + delay_ms = delay_ms_default; + break; + case AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_BG: + broad_std = AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_M; + cur_std = ID_PAL_M; + if (p != NULL) { + p->analog.std = + V4L2_COLOR_STD_PAL | V4L2_STD_PAL_M; + p->frequency += 1; + p->analog.audmode = V4L2_STD_PAL_M; + } + delay_ms = delay_ms_default; + break; + case AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_M: + broad_std = AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_DK; + cur_std = ID_PAL_DK; + if (p != NULL) { + p->analog.std = + V4L2_COLOR_STD_PAL | V4L2_STD_PAL_DK; + p->frequency += 1; + p->analog.audmode = V4L2_STD_PAL_DK; + } + delay_ms = delay_ms_default; + break; + + default: + pr_err("unsupport broadcast_standard!!!\n"); + break; + } + if (p != NULL) + fe->ops.set_frontend(fe); + /* atvdemod_init(); //set_frontend has already been called it */ + + /* enable audio detect function */ + temp_data = atv_dmd_rd_reg(APB_BLOCK_ADDR_SIF_STG_2, 0x02); + temp_data = temp_data | 0x80;/* 0x40 */ + atv_dmd_wr_reg(APB_BLOCK_ADDR_SIF_STG_2, 0x02, temp_data); + + usleep_range(delay_ms*1000, delay_ms*1000+100); + + carrier_lock_count = 0; + i = 4; + while (i--) { + retrieve_vpll_carrier_lock(&lock); + if (lock == 0) + break; + carrier_lock_count++; + if (carrier_lock_count >= 20) { + pr_err("%s step2, retrieve_vpll_carrier_lock failed\n", + __func__); + /* return broad_std; */ + } + usleep_range(6000, 9000); + } + /* ----------------read carrier_power--------------------- */ + for (i = 0; i < 100; i++) { + carrier_power = + atv_dmd_rd_reg(APB_BLOCK_ADDR_SIF_STG_2, + reg_addr); + carrier_power_max += carrier_power; + } + carrier_power = carrier_power_max/i; + carrier_power_max = 0; + pr_err("[amlatvdemod.. %d,std:%d ]%s: atvdemo audio carrier power report:%lu. @@@@@@@@@@\n", + num, broad_std, __func__, carrier_power); + carrier_power_average[cur_std] += carrier_power; + num++; + } + + return broad_std; +} + +void aml_audio_valume_gain_set(unsigned int audio_gain) +{ + unsigned long audio_gain_data, temp_data; + + if (audio_gain > 0xfff) { + pr_err("Error: atv in gain max 7.998, min 0.002! gain = value/512\n"); + pr_err("value (0~0xfff)\n"); + return; + } + audio_gain_data = audio_gain & 0xfff; + temp_data = atv_dmd_rd_word(APB_BLOCK_ADDR_MONO_PROC, 0x52); + temp_data = (temp_data & 0xf000) | audio_gain_data; + atv_dmd_wr_word(APB_BLOCK_ADDR_MONO_PROC, 0x52, temp_data); +} + +unsigned int aml_audio_valume_gain_get(void) +{ + unsigned long audio_gain_data; + + audio_gain_data = atv_dmd_rd_word(APB_BLOCK_ADDR_MONO_PROC, 0x52); + audio_gain_data = audio_gain_data & 0xfff; + return audio_gain_data; +} + +void aml_atvdemod_overmodule_det(void) +{ + unsigned long temp_data, temp_data2;/* , temp_data3 , temp_data4; */ + unsigned long counter_report; + int carrier_lock_count = 0; + int vlock = 0; + + switch (audio_det_mode) { + case AUDIO_AUTO_DETECT: + aml_audiomode_autodet(NULL); + return; +#if 0 + while (1) { + retrieve_vpll_carrier_lock(&vlock); + if (vlock) + break; + carrier_lock_count++; + if (carrier_lock_count >= 1000) + return; + /* ------------whether need timer delays between the detect lock---- */ + } + /* -----------------enable auto_adjust_en------------- */ + temp_data = atv_dmd_rd_word(APB_BLOCK_ADDR_SIF_STG_2, 0x02); + temp_data = temp_data | 0x100; + /* set the bit 9 of the temp_data to 1 */ + atv_dmd_wr_word(APB_BLOCK_ADDR_SIF_STG_2, 0x02, temp_data); + /* -----------------enable auto_adjust_en end----------------- */ + /* -----------------begain to set ov_cnt_en enable------------- */ + temp_data2 = atv_dmd_rd_word(APB_BLOCK_ADDR_SIF_STG_2, 0x02); + temp_data2 = temp_data2 | 0x80; + /* set the bit 8 of the temp_data to 1 */ + atv_dmd_wr_word(APB_BLOCK_ADDR_SIF_STG_2, 0x02, temp_data2); + /* ------------------set ov_cnt_en enable end---------------- */ + udelay(1000);/* timer delay needed , */ + /* ------------------------------------------------------------ */ + /* -----------------disable auto_adjust_en------------- */ + temp_data3 = atv_dmd_rd_word(APB_BLOCK_ADDR_SIF_STG_2, 0x02); + temp_data3 = temp_data3 & 0xfeff; + /* set the bit 9 of the temp_data to 0 */ + atv_dmd_wr_word(APB_BLOCK_ADDR_SIF_STG_2, 0x02, temp_data3); + /* -----------------disable auto_adjust_en end------------ */ + /* -----------------begain to set ov_cnt_en disable------------- */ + temp_data4 = atv_dmd_rd_word(APB_BLOCK_ADDR_SIF_STG_2, 0x02); + temp_data4 = temp_data4 & 0xff7f; + /* set the bit 8 of the temp_data to 0 */ + atv_dmd_wr_word(APB_BLOCK_ADDR_SIF_STG_2, 0x02, temp_data4); + break; + /* ------------------set ov_cnt_en disable end------ */ +#endif + case AUDIO_MANUAL_DETECT: + while (1) { + retrieve_vpll_carrier_lock(&vlock); + if (vlock) + break; + carrier_lock_count++; + if (carrier_lock_count >= 1000) + return; + } + + /* -----------------begain to set ov_cnt_en enable---- */ + temp_data = atv_dmd_rd_word(APB_BLOCK_ADDR_SIF_STG_2, 0x02); + temp_data = temp_data | 0x80; + /* set the bit 8 of the temp_data to 1 */ + atv_dmd_wr_word(APB_BLOCK_ADDR_SIF_STG_2, 0x02, temp_data); + /* ------------------set ov_cnt_en enable end--------------- */ + /* -----------------disable auto_adjust_en------------- */ + temp_data2 = atv_dmd_rd_word(APB_BLOCK_ADDR_SIF_STG_2, 0x02); + temp_data2 = temp_data2 & 0xfeff; + /* set the bit 9 of the temp_data to 0 */ + atv_dmd_wr_word(APB_BLOCK_ADDR_SIF_STG_2, 0x02, temp_data2); + /* -----------------disable auto_adjust_en end------------ */ + udelay(1000);/* timer delay needed , */ + /* ------------------------------------------------------- */ + counter_report = + atv_dmd_rd_word(APB_BLOCK_ADDR_SIF_STG_2, 0x04); + + while (counter_report > over_threshold) { + unsigned long shift_gain, shift_gain_report; + + temp_data2 = atv_dmd_rd_byte( + APB_BLOCK_ADDR_SIF_STG_2, 0x00); + shift_gain = temp_data2 & 0x07; + shift_gain--; + temp_data2 = (temp_data2 & 0xf8) | shift_gain; + atv_dmd_wr_byte(APB_BLOCK_ADDR_SIF_STG_2, 0x00, + temp_data2); + shift_gain_report = ( + (atv_dmd_rd_long(APB_BLOCK_ADDR_SIF_STG_2, 0x04) + & 0x00070000) >> 16); + if (shift_gain_report != shift_gain) + pr_info("[atvdemo...]:set shift_gain error\n"); + /* ------------------timer delay needed- */ + udelay(1000);/* timer delay needed , */ + /* ----------------------- */ + counter_report = + atv_dmd_rd_word(APB_BLOCK_ADDR_SIF_STG_2, 0x04); + } + break; + default: + pr_info("invalid over_module_det mode!!!\n"); + break; + } +} + +void aml_fix_PWM_adjust(int enable) +{ + unsigned long temp_data; + /* + *temp_data = atv_dmd_rd_byte(APB_BLOCK_ADDR_AGC_PWM, 0x08); + *temp_data = temp_data | 0x01; + *atv_dmd_wr_byte(APB_BLOCK_ADDR_AGC_PWM, 0x08, temp_data); + */ + temp_data = atv_dmd_rd_reg(APB_BLOCK_ADDR_SIF_STG_2, 0x02); + if (enable) + temp_data = temp_data & ~((0x3)<<8); + else + temp_data = temp_data & ~((0x1)<<9); + + atv_dmd_wr_reg(APB_BLOCK_ADDR_SIF_STG_2, 0x02, temp_data); + if (enable) { + temp_data = temp_data | ((0x3)<<8); + atv_dmd_wr_reg(APB_BLOCK_ADDR_SIF_STG_2, 0x02, temp_data); + } +} + +void aml_audio_overmodulation(int enable) +{ + static int ov_flag; + unsigned long tmp_v; + unsigned long tmp_v1; + u32 Broadcast_Standard = broad_std; + + if (enable && Broadcast_Standard == + AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_DK) { + tmp_v = atv_dmd_rd_long(APB_BLOCK_ADDR_SIF_STG_2, 0x28); + tmp_v = tmp_v&0xffff; + if (tmp_v >= 0x10 && ov_flag == 0) { + tmp_v1 = + atv_dmd_rd_long(APB_BLOCK_ADDR_SIF_STG_2, 0); + tmp_v1 = (tmp_v1&0xffffff)|(1<<24); + atv_dmd_wr_long(APB_BLOCK_ADDR_SIF_STG_2, 0, tmp_v1); + atv_dmd_wr_long(APB_BLOCK_ADDR_SIF_STG_2, + 0x14, 0x8000015); + atv_dmd_wr_long(APB_BLOCK_ADDR_SIF_STG_2, + 0x1c, 0x0f000); + } else if (tmp_v >= 0x2500 && ov_flag == 0) { + tmp_v1 = atv_dmd_rd_long(APB_BLOCK_ADDR_SIF_STG_2, 0); + tmp_v1 = (tmp_v1&0xffffff)|(1<<24); + atv_dmd_wr_long(APB_BLOCK_ADDR_SIF_STG_2, 0, tmp_v1); + atv_dmd_wr_long(APB_BLOCK_ADDR_SIF_STG_2, + 0x14, 0xf400015); + atv_dmd_wr_long(APB_BLOCK_ADDR_SIF_STG_2, + 0x18, 0xc000); + atv_dmd_wr_long(APB_BLOCK_ADDR_SIF_STG_2, + 0x1c, 0x0f000); + ov_flag = 1; + } else if (tmp_v <= 0x10 && ov_flag == 1) { + tmp_v1 = atv_dmd_rd_long(APB_BLOCK_ADDR_SIF_STG_2, 0); + tmp_v1 = (tmp_v1&0xffffff)|(0<<24); + atv_dmd_wr_long(APB_BLOCK_ADDR_SIF_STG_2, 0, tmp_v1); + atv_dmd_wr_long(APB_BLOCK_ADDR_SIF_STG_2, + 0x14, 0xf400000); + atv_dmd_wr_long(APB_BLOCK_ADDR_SIF_STG_2, + 0x18, 0xc000); + atv_dmd_wr_long(APB_BLOCK_ADDR_SIF_STG_2, + 0x1c, 0x1f000); + ov_flag = 0; + } + } +} + diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/atv_demod/atvdemod_func.h b/drivers/amlogic/media_modules/stream_input/tv_frontend/atv_demod/atvdemod_func.h new file mode 100644 index 000000000000..807239206f8f --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/atv_demod/atvdemod_func.h @@ -0,0 +1,323 @@ +/* + * ATVDEMOD Device Driver + * + * Author: dezhi kong + * + * + * Copyright (C) 2014 Amlogic Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ATVDEMOD_FUN_H +#define __ATVDEMOD_FUN_H + +/*#include "../aml_fe.h"*/ +#include +#include "../aml_fe.h" +#include + +/*#define TVFE_APB_BASE_ADDR 0xd0046000*/ +#define ATV_DMD_APB_BASE_ADDR 0xc8008000 +#define ATV_DMD_APB_BASE_ADDR_GXTVBB 0xc8840000 + +#define HHI_ATV_DMD_SYS_CLK_CNTL 0x10f3 + +extern int atvdemod_debug_en; +extern struct amlatvdemod_device_s *amlatvdemod_devp; +extern unsigned int reg_23cf; /* IIR filter */ +extern int broad_std_except_pal_m; +#undef pr_info +#define pr_info(args...)\ + do {\ + if (atvdemod_debug_en)\ + printk(args);\ + } while (0) +#undef pr_dbg +#define pr_dbg(a...) \ + do {\ + if (1)\ + printk(a);\ + } while (0) + +#define ATVDEMOD_INTERVAL (HZ/100) /*10ms, #define HZ 100*/ + +extern int amlatvdemod_reg_read(unsigned int reg, unsigned int *val); +extern int amlatvdemod_reg_write(unsigned int reg, unsigned int val); +extern int amlatvdemod_hiu_reg_read(unsigned int reg, unsigned int *val); +extern int amlatvdemod_hiu_reg_write(unsigned int reg, unsigned int val); + +static inline uint32_t R_ATVDEMOD_REG(uint32_t reg) +{ + unsigned int val; + + amlatvdemod_reg_read(reg, &val); + return val; +} + +static inline void W_ATVDEMOD_REG(uint32_t reg, + const uint32_t val) +{ + amlatvdemod_reg_write(reg, val); +} + +static inline void W_ATVDEMOD_BIT(uint32_t reg, + const uint32_t value, + const uint32_t start, + const uint32_t len) +{ + W_ATVDEMOD_REG(reg, ((R_ATVDEMOD_REG(reg) & + ~(((1L << (len)) - 1) << (start))) | + (((value) & ((1L << (len)) - 1)) << (start)))); +} + +static inline uint32_t R_ATVDEMOD_BIT(uint32_t reg, + const uint32_t start, + const uint32_t len) +{ + uint32_t val; + + val = ((R_ATVDEMOD_REG(reg) >> (start)) & ((1L << (len)) - 1)); + + return val; +} + +static inline uint32_t R_HIU_REG(uint32_t reg) +{ + unsigned int val; + + amlatvdemod_hiu_reg_read(reg, &val); + return val; +} + +static inline void W_HIU_REG(uint32_t reg, + const uint32_t val) +{ + amlatvdemod_hiu_reg_write(reg, val); +} + +static inline void W_HIU_BIT(uint32_t reg, + const uint32_t value, + const uint32_t start, + const uint32_t len) +{ + W_HIU_REG(reg, ((R_HIU_REG(reg) & + ~(((1L << (len)) - 1) << (start))) | + (((value) & ((1L << (len)) - 1)) << (start)))); +} + +static inline uint32_t R_HIU_BIT(uint32_t reg, + const uint32_t start, + const uint32_t len) +{ + uint32_t val; + + val = ((R_HIU_REG(reg) >> (start)) & ((1L << (len)) - 1)); + + return val; +} + +enum broadcast_standard_e { + ATVDEMOD_STD_NTSC = 0, + ATVDEMOD_STD_NTSC_J, + ATVDEMOD_STD_PAL_M, + ATVDEMOD_STD_PAL_BG, + ATVDEMOD_STD_DTV, + ATVDEMOD_STD_SECAM_DK2, + ATVDEMOD_STD_SECAM_DK3, + ATVDEMOD_STD_PAL_BG_NICAM, + ATVDEMOD_STD_PAL_DK_CHINA, + ATVDEMOD_STD_SECAM_L, + ATVDEMOD_STD_PAL_I, + ATVDEMOD_STD_PAL_DK1, + ATVDEMOD_STD_MAX, +}; +enum gde_curve_e { + ATVDEMOD_CURVE_M = 0, + ATVDEMOD_CURVE_A, + ATVDEMOD_CURVE_B, + ATVDEMOD_CURVE_CHINA, + ATVDEMOD_CURVE_MAX, +}; +enum sound_format_e { + ATVDEMOD_SOUND_STD_MONO = 0, + ATVDEMOD_SOUND_STD_NICAM, + ATVDEMOD_SOUND_STD_MAX, +}; +extern void atv_dmd_wr_reg(unsigned char block, unsigned char reg, + unsigned long data); +extern unsigned long atv_dmd_rd_reg(unsigned char block, unsigned char reg); +extern unsigned long atv_dmd_rd_byte(unsigned long block_address, + unsigned long reg_addr); +extern unsigned long atv_dmd_rd_word(unsigned long block_address, + unsigned long reg_addr); +extern unsigned long atv_dmd_rd_long(unsigned long block_address, + unsigned long reg_addr); +extern void atv_dmd_wr_long(unsigned long block_address, + unsigned long reg_addr, + unsigned long data); +extern void atv_dmd_wr_word(unsigned long block_address, + unsigned long reg_addr, + unsigned long data); +extern void atv_dmd_wr_byte(unsigned long block_address, + unsigned long reg_addr, + unsigned long data); +extern void set_audio_gain_val(int val); +extern void set_video_gain_val(int val); +extern void atv_dmd_soft_reset(void); +extern void atv_dmd_input_clk_32m(void); +extern void read_version_register(void); +extern void check_communication_interface(void); +extern void power_on_receiver(void); +extern void atv_dmd_misc(void); +extern void configure_receiver(int Broadcast_Standard, + unsigned int Tuner_IF_Frequency, + int Tuner_Input_IF_inverted, int GDE_Curve, + int sound_format); +extern int atvdemod_clk_init(void); +extern int atvdemod_init(void); +extern void atvdemod_uninit(void); +extern void atv_dmd_set_std(void); +extern void retrieve_vpll_carrier_lock(int *lock); +extern void retrieve_video_lock(int *lock); +extern int retrieve_vpll_carrier_afc(void); + +extern int get_atvdemod_snr_val(void); +extern int aml_atvdemod_get_snr(struct dvb_frontend *fe); + +/*atv demod block address*/ +/*address interval is 4, because it's 32bit interface, + * but the address is in byte + */ +#define ATV_DMD_TOP_CTRL 0x0 +#define ATV_DMD_TOP_CTRL1 0x4 +#define ATV_DMD_RST_CTRL 0x8 + +#define APB_BLOCK_ADDR_SYSTEM_MGT 0x0 +#define APB_BLOCK_ADDR_AA_LP_NOTCH 0x1 +#define APB_BLOCK_ADDR_MIXER_1 0x2 +#define APB_BLOCK_ADDR_MIXER_3 0x3 +#define APB_BLOCK_ADDR_ADC_SE 0x4 +#define APB_BLOCK_ADDR_PWR_ANL 0x5 +#define APB_BLOCK_ADDR_CARR_RCVY 0x6 +#define APB_BLOCK_ADDR_FE_DROOP_MDF 0x7 +#define APB_BLOCK_ADDR_SIF_IC_STD 0x8 +#define APB_BLOCK_ADDR_SIF_STG_2 0x9 +#define APB_BLOCK_ADDR_SIF_STG_3 0xa +#define APB_BLOCK_ADDR_IC_AGC 0xb +#define APB_BLOCK_ADDR_DAC_UPS 0xc +#define APB_BLOCK_ADDR_GDE_EQUAL 0xd +#define APB_BLOCK_ADDR_VFORMAT 0xe +#define APB_BLOCK_ADDR_VDAGC 0xf +#define APB_BLOCK_ADDR_VERS_REGISTER 0x10 +#define APB_BLOCK_ADDR_INTERPT_MGT 0x11 +#define APB_BLOCK_ADDR_ADC_MGR 0x12 +#define APB_BLOCK_ADDR_GP_VD_FLT 0x13 +#define APB_BLOCK_ADDR_CARR_DMD 0x14 +#define APB_BLOCK_ADDR_SIF_VD_IF 0x15 +#define APB_BLOCK_ADDR_VD_PKING 0x16 +#define APB_BLOCK_ADDR_FE_DR_SMOOTH 0x17 +#define APB_BLOCK_ADDR_AGC_PWM 0x18 +#define APB_BLOCK_ADDR_DAC_UPS_24M 0x19 +#define APB_BLOCK_ADDR_VFORMAT_DP 0x1a +#define APB_BLOCK_ADDR_VD_PKING_DAC 0x1b +#define APB_BLOCK_ADDR_MONO_PROC 0x1c +#define APB_BLOCK_ADDR_TOP 0x1d + +#define SLAVE_BLOCKS_NUMBER 0x1d /*indeed totals 0x1e, adding top*/ + +/*Broadcast_Standard*/ +/* 0: NTSC*/ +/* 1: NTSC-J*/ +/* 2: PAL-M,*/ +/* 3: PAL-BG*/ +/* 4: DTV*/ +/* 5: SECAM- DK2*/ +/* 6: SECAM -DK3*/ +/* 7: PAL-BG, NICAM*/ +/* 8: PAL-DK-CHINA*/ +/* 9: SECAM-L / SECAM-DK3*/ +/* 10: PAL-I*/ +/* 11: PAL-DK1*/ +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC 0 +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_J 1 +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_M 2 +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_BG 3 +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_DTV 4 +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_SECAM_DK2 5 +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_SECAM_DK3 6 +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_BG_NICAM 7 +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_DK 8 +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_SECAM_L 9 +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_I 10 +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_PAL_DK1 11 +/* new add @20150813 begin */ +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_DK 12 +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_BG 13 +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_I 14 +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_NTSC_M 15 +/* new add @20150813 end */ + +/*GDE_Curve*/ +/* 0: CURVE-M*/ +/* 1: CURVE-A*/ +/* 2: CURVE-B*/ +/* 3: CURVE-CHINA*/ +/* 4: BYPASS*/ +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_CURVE_M 0 +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_CURVE_A 1 +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_CURVE_B 2 +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_CURVE_CHINA 3 +#define AML_ATV_DEMOD_VIDEO_MODE_PROP_CURVE_BYPASS 4 + +/*sound format 0: MONO;1:NICAM*/ +#define AML_ATV_DEMOD_SOUND_MODE_PROP_MONO 0 +#define AML_ATV_DEMOD_SOUND_MODE_PROP_NICAM 1 +/** + *freq_hz:hs_freq + *freq_hz_cvrt=hs_freq/0.23841858 + *vs_freq==50,freq_hz=15625;freq_hz_cvrt=0xffff + *vs_freq==60,freq_hz=15734,freq_hz_cvrt=0x101c9 + ** + */ +#define AML_ATV_DEMOD_FREQ_50HZ_VERT 0xffff /*65535*/ +#define AML_ATV_DEMOD_FREQ_60HZ_VERT 0x101c9 /*65993*/ + +#define CARR_AFC_DEFAULT_VAL 0xffff + +enum amlatvdemod_snr_level_e { + very_low = 1, + low, + ok_minus, + ok_plus, + high, +}; + +enum audio_detect_mode { + AUDIO_AUTO_DETECT = 0, + AUDIO_MANUAL_DETECT, +}; + +struct amlatvdemod_device_s { + struct class *clsp; + struct device *dev; + struct analog_parameters parm; + int fre_offset; + struct pinctrl *pin; + const char *pin_name; +}; + +extern void aml_audio_overmodulation(int enable); +extern void amlatvdemod_set_std(int val); +extern struct amlatvdemod_device_s *amlatvdemod_devp; +extern void aml_fix_PWM_adjust(int enable); +extern void aml_audio_valume_gain_set(unsigned int audio_gain); +extern unsigned int aml_audio_valume_gain_get(void); +extern void aml_atvdemod_overmodule_det(void); +extern int aml_audiomode_autodet(struct dvb_frontend *fe); +extern void retrieve_frequency_offset(int *freq_offset); +extern int aml_atvdemod_get_snr_ex(void); + +#endif /* __ATVDEMOD_FUN_H */ diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/aml_demod.c b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/aml_demod.c new file mode 100644 index 000000000000..009f81e2f727 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/aml_demod.c @@ -0,0 +1,706 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +/* #include */ +#include +#include + +/* #include */ +#include +#include +#include "demod_func.h" + +#include +#ifdef CONFIG_COMPAT +#include +#endif +/*#include "sdio/sdio_init.h"*/ +#define DRIVER_NAME "aml_demod" +#define MODULE_NAME "aml_demod" +#define DEVICE_NAME "aml_demod" +#define DEVICE_UI_NAME "aml_demod_ui" + +#define pr_dbg(a ...) \ + do { \ + if (1) { \ + printk(a); \ + } \ + } while (0) + + +const char aml_demod_dev_id[] = "aml_demod"; + +/*#ifndef CONFIG_AM_DEMOD_DVBAPI + * static struct aml_demod_i2c demod_i2c; + * static struct aml_demod_sta demod_sta; + * #else + * extern struct aml_demod_i2c demod_i2c; + * extern struct aml_demod_sta demod_sta; + #endif +*/ + +static struct aml_demod_i2c demod_i2c; +static struct aml_demod_sta demod_sta; +static int read_start; + +int sdio_read_ddr(unsigned long sdio_addr, unsigned long byte_count, + unsigned char *data_buf) +{ + return 0; +} + +int sdio_write_ddr(unsigned long sdio_addr, unsigned long byte_count, + unsigned char *data_buf) +{ + return 0; +} + +int read_reg(int addr) +{ + addr = addr + DEMOD_BASE; + return apb_read_reg(addr); +} + +void wait_capture(int cap_cur_addr, int depth_MB, int start) +{ + int readfirst; + int tmp; + int time_out; + int last = 0x90000000; + + time_out = readfirst = 0; + tmp = depth_MB << 20; + while (tmp && (time_out < 1000)) { /*10seconds time out */ + time_out = time_out + 1; + msleep(20); + readfirst = app_apb_read_reg(cap_cur_addr); + if ((last - readfirst) > 0) + tmp = 0; + else + last = readfirst; + /* usleep(1000); */ + /* readsecond= app_apb_read_reg(cap_cur_addr); */ + + /* if((readsecond-start)>tmp) */ +/* tmp=0;*/ +/* if((readsecond-readfirst)<0) // turn around*/ +/* tmp=0;*/ + pr_dbg("First %x = [%08x],[%08x]%x\n", cap_cur_addr, readfirst, + last, (last - readfirst)); +/* printf("Second %x = [%08x]\n",cap_cur_addr, readsecond);*/ + msleep(20); + } + read_start = readfirst + 0x40000000; + pr_dbg("read_start is %x\n", read_start); +} + +int cap_adc_data(struct aml_cap_data *cap) +{ + int tmp; + int tb_depth; + + pr_dbg("capture ADC\n "); + /* printf("set mem_start (you can read in kernel start log + * (memstart is ).(hex) : "); + */ + /* scanf("%x",&tmp);*/ + tmp = 0x94400000; + app_apb_write_reg(0x9d, cap->cap_addr); + app_apb_write_reg(0x9e, cap->cap_addr + cap->cap_size * 0x100000); + /*0x8000000-128m, 0x400000-4m */ + read_start = tmp + 0x40000000; + /*printf("set afifo rate. (hex)(adc_clk/demod_clk)*256+2 : "); // + * (adc_clk/demod_clk)*256+2 + */ + /* scanf("%x",&tmp); */ + cap->cap_afifo = 0x60; + app_apb_write_reg(0x15, 0x18715f2); + app_apb_write_reg(0x15, (app_apb_read_reg(0x15) & 0xfff00fff) | + ((cap->cap_afifo & 0xff) << 12)); /* set afifo */ + app_apb_write_reg(0x9b, 0x1c9); /* capture ADC 10bits */ + app_apb_write_reg(0x7f, 0x00008000); /* enable testbus 0x8000 */ + + tb_depth = cap->cap_size; /*127; */ + tmp = 9; + app_apb_write_reg(0x9b, (app_apb_read_reg(0x9b) & ~0x1f) | tmp); + /* set testbus width */ + + tmp = 0x100000; + app_apb_write_reg(0x9c, tmp); /* by ADC data enable */ + /* printf("Set test mode. (0 is normal ,1 is testmode) : "); //0 */ + /* scanf("%d",&tmp); */ + tmp = 0; + if (tmp == 1) + app_apb_write_reg(0x9b, app_apb_read_reg(0x9b) | (1 << 10)); + /* set test mode; */ + else + app_apb_write_reg(0x9b, app_apb_read_reg(0x9b) & ~(1 << 10)); + /* close test mode; */ + + app_apb_write_reg(0x9b, app_apb_read_reg(0x9b) & ~(1 << 9)); + /* close cap; */ + app_apb_write_reg(0x9b, app_apb_read_reg(0x9b) | (1 << 9)); + /* open cap; */ + + app_apb_write_reg(0x9b, app_apb_read_reg(0x9b) | (1 << 7)); + /* close tb; */ + app_apb_write_reg(0x9b, app_apb_read_reg(0x9b) & ~(1 << 7)); + /* open tb; */ + + app_apb_write_reg(0x9b, app_apb_read_reg(0x9b) | (1 << 5)); + /* close intlv; */ + + app_apb_write_reg(0x303, 0x8); /* open dc_arbit */ + + tmp = 0; + if (tmp) + app_apb_write_reg(0x9b, app_apb_read_reg(0x9b) & ~(1 << 5)); + /* open intlv; */ + + app_apb_write_reg(0x9b, app_apb_read_reg(0x9b) & ~(1 << 8)); + /* go tb; */ + + wait_capture(0x9f, tb_depth, app_apb_read_reg(0x9d)); + + app_apb_write_reg(0x9b, app_apb_read_reg(0x9b) | (1 << 8)); + /* stop tb; */ + app_apb_write_reg(0x9b, app_apb_read_reg(0x9b) | (1 << 7)); + /* close tb; */ + return 0; +} + +static DECLARE_WAIT_QUEUE_HEAD(lock_wq); + +static ssize_t aml_demod_info(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return 0; +} + +static struct class_attribute aml_demod_class_attrs[] = { + __ATTR(info, + 0644, + aml_demod_info, + NULL), + __ATTR_NULL +}; + +static struct class aml_demod_class = { + .name = "aml_demod", + .class_attrs = aml_demod_class_attrs, +}; + +#if 0 + +static irqreturn_t aml_demod_isr(int irq, void *dev_id) +{ + if (demod_sta.dvb_mode == 0) { + /*dvbc_isr(&demod_sta); */ + if (dvbc_isr_islock()) { + pr_dbg("sync4\n"); + /*if (waitqueue_active(&lock_wq)) + *wake_up_interruptible(&lock_wq); + */ + } + } else { + dvbt_isr(&demod_sta); + } + + return IRQ_HANDLED; +} +#endif + +static int aml_demod_open(struct inode *inode, struct file *file) +{ + pr_dbg("Amlogic Demod DVB-T/C Open\n"); + return 0; +} + +static int aml_demod_release(struct inode *inode, struct file *file) +{ + pr_dbg("Amlogic Demod DVB-T/C Release\n"); + return 0; +} + +#if 0 +static int amdemod_islock(void) +{ + struct aml_demod_sts demod_sts; + + if (demod_sta.dvb_mode == 0) { + dvbc_status(&demod_sta, &demod_i2c, &demod_sts); + return demod_sts.ch_sts & 0x1; + } else if (demod_sta.dvb_mode == 1) { + dvbt_status(&demod_sta, &demod_i2c, &demod_sts); + return demod_sts.ch_sts >> 12 & 0x1; + } + return 0; +} +#endif + +void mem_read(struct aml_demod_mem *arg) +{ + int data; + int addr; + + addr = arg->addr; + data = arg->dat; +/* memcpy(mem_buf[addr],data,1);*/ + pr_dbg("[addr %x] data is %x\n", addr, data); +} +static long aml_demod_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + int strength = 0; + struct dvb_frontend *dvbfe; + struct aml_tuner_sys *tuner; + + switch (cmd) { + case AML_DEMOD_GET_RSSI: + pr_dbg("Ioctl Demod GET_RSSI.\n"); + dvbfe = get_si2177_tuner(); + if (dvbfe != NULL) + strength = dvbfe->ops.tuner_ops.get_strength(dvbfe); + pr_dbg("[si2177] strength is %d\n", strength - 256); + if (strength < 0) + strength = 0 - strength; + tuner = (struct aml_tuner_sys *)arg; + tuner->rssi = strength; + break; + + case AML_DEMOD_SET_TUNER: + pr_dbg("Ioctl Demod Set Tuner.\n"); + dvbfe = get_si2177_tuner(); + if (dvbfe != NULL) + dvbfe->ops.tuner_ops.set_tuner(dvbfe, &demod_sta, + &demod_i2c, + (struct aml_tuner_sys *) + arg); + break; + + case AML_DEMOD_SET_SYS: + pr_dbg("Ioctl Demod Set System\n"); + demod_set_sys(&demod_sta, &demod_i2c, + (struct aml_demod_sys *)arg); + break; + + case AML_DEMOD_GET_SYS: + pr_dbg("Ioctl Demod Get System\n"); + + /*demod_get_sys(&demod_i2c, (struct aml_demod_sys *)arg); */ + break; + + case AML_DEMOD_TEST: + pr_dbg("Ioctl Demod Test. It is blank now\n"); + /*demod_msr_clk(13); */ + /*demod_msr_clk(14); */ + /*demod_calc_clk(&demod_sta); */ + break; + + case AML_DEMOD_TURN_ON: + pr_dbg("Ioctl Demod Turn ON.It is blank now\n"); + /*demod_turn_on(&demod_sta, (struct aml_demod_sys *)arg); */ + break; + + case AML_DEMOD_TURN_OFF: + pr_dbg("Ioctl Demod Turn OFF.It is blank now\n"); + /*demod_turn_off(&demod_sta, (struct aml_demod_sys *)arg); */ + break; + + case AML_DEMOD_DVBC_SET_CH: + pr_dbg("Ioctl DVB-C Set Channel.\n"); + dvbc_set_ch(&demod_sta, &demod_i2c, + (struct aml_demod_dvbc *)arg); + break; + + case AML_DEMOD_DVBC_GET_CH: + /* pr_dbg("Ioctl DVB-C Get Channel. It is blank\n"); */ + dvbc_status(&demod_sta, &demod_i2c, + (struct aml_demod_sts *)arg); + break; + case AML_DEMOD_DVBC_TEST: + pr_dbg("Ioctl DVB-C Test. It is blank\n"); + /*dvbc_get_test_out(0xb, 1000, (u32 *)arg); */ + break; + case AML_DEMOD_DVBT_SET_CH: + pr_dbg("Ioctl DVB-T Set Channel\n"); + dvbt_set_ch(&demod_sta, &demod_i2c, + (struct aml_demod_dvbt *)arg); + break; + + case AML_DEMOD_DVBT_GET_CH: + pr_dbg("Ioctl DVB-T Get Channel\n"); + /*dvbt_status(&demod_sta, &demod_i2c, + * (struct aml_demod_sts *)arg); + */ + break; + + case AML_DEMOD_DVBT_TEST: + pr_dbg("Ioctl DVB-T Test. It is blank\n"); + /*dvbt_get_test_out(0x1e, 1000, (u32 *)arg); */ + break; + + case AML_DEMOD_DTMB_SET_CH: + dtmb_set_ch(&demod_sta, &demod_i2c, + (struct aml_demod_dtmb *)arg); + break; + + case AML_DEMOD_DTMB_GET_CH: + break; + + case AML_DEMOD_DTMB_TEST: + break; + + case AML_DEMOD_ATSC_SET_CH: + atsc_set_ch(&demod_sta, &demod_i2c, + (struct aml_demod_atsc *)arg); + break; + + case AML_DEMOD_ATSC_GET_CH: + check_atsc_fsm_status(); + break; + + case AML_DEMOD_ATSC_TEST: + break; + + case AML_DEMOD_SET_REG: + /* pr_dbg("Ioctl Set Register\n"); */ + demod_set_reg((struct aml_demod_reg *)arg); + break; + + case AML_DEMOD_GET_REG: + /* pr_dbg("Ioctl Get Register\n"); */ + demod_get_reg((struct aml_demod_reg *)arg); + break; + +/* case AML_DEMOD_SET_REGS: */ +/* break; */ + +/* case AML_DEMOD_GET_REGS: */ +/* break; */ + + case AML_DEMOD_RESET_MEM: + pr_dbg("set mem ok\n"); + break; + + case AML_DEMOD_READ_MEM: + break; + case AML_DEMOD_SET_MEM: + /*step=(struct aml_demod_mem)arg; + * pr_dbg("[%x]0x%x------------------\n",i,mem_buf[step]); + * for(i=step;i<1024-1;i++){ + * pr_dbg("0x%x,",mem_buf[i]); + * } + */ + mem_read((struct aml_demod_mem *)arg); + break; + + case AML_DEMOD_ATSC_IRQ: + atsc_read_iqr_reg(); + break; + + default: + pr_dbg("Enter Default ! 0x%X\n", cmd); +/* pr_dbg("AML_DEMOD_GET_REGS=0x%08X\n", AML_DEMOD_GET_REGS); */ +/* pr_dbg("AML_DEMOD_SET_REGS=0x%08X\n", AML_DEMOD_SET_REGS); */ + return -EINVAL; + } + + return 0; +} + +#ifdef CONFIG_COMPAT + +static long aml_demod_compat_ioctl(struct file *file, unsigned int cmd, + ulong arg) +{ + return aml_demod_ioctl(file, cmd, (ulong)compat_ptr(arg)); +} + +#endif + + +static const struct file_operations aml_demod_fops = { + .owner = THIS_MODULE, + .open = aml_demod_open, + .release = aml_demod_release, + .unlocked_ioctl = aml_demod_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = aml_demod_compat_ioctl, +#endif +}; + +static int aml_demod_ui_open(struct inode *inode, struct file *file) +{ + pr_dbg("Amlogic aml_demod_ui_open Open\n"); + return 0; +} + +static int aml_demod_ui_release(struct inode *inode, struct file *file) +{ + pr_dbg("Amlogic aml_demod_ui_open Release\n"); + return 0; +} +char buf_all[100]; +static ssize_t aml_demod_ui_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + char *capture_buf = buf_all; + int res = 0; + + if (count >= 4 * 1024 * 1024) + count = 4 * 1024 * 1024; + else if (count == 0) + return 0; + + res = copy_to_user((void *)buf, (char *)capture_buf, count); + if (res < 0) { + pr_dbg("[aml_demod_ui_read]res is %d", res); + return res; + } + + return count; +} + +static ssize_t aml_demod_ui_write(struct file *file, const char *buf, + size_t count, loff_t *ppos) +{ + return 0; +} + +static struct device *aml_demod_ui_dev; +static dev_t aml_demod_devno_ui; +static struct cdev *aml_demod_cdevp_ui; +static const struct file_operations aml_demod_ui_fops = { + .owner = THIS_MODULE, + .open = aml_demod_ui_open, + .release = aml_demod_ui_release, + .read = aml_demod_ui_read, + .write = aml_demod_ui_write, + /* .unlocked_ioctl = aml_demod_ui_ioctl, */ +}; + +#if 0 +static ssize_t aml_demod_ui_info(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return 0; +} + +static struct class_attribute aml_demod_ui_class_attrs[] = { + __ATTR(info, + 0644, + aml_demod_ui_info, + NULL), + __ATTR_NULL +}; +#endif + +static struct class aml_demod_ui_class = { + .name = "aml_demod_ui", +/* .class_attrs = aml_demod_ui_class_attrs,*/ +}; + +int aml_demod_ui_init(void) +{ + int r = 0; + + r = class_register(&aml_demod_ui_class); + if (r) { + pr_dbg("create aml_demod class fail\r\n"); + class_unregister(&aml_demod_ui_class); + return r; + } + + r = alloc_chrdev_region(&aml_demod_devno_ui, 0, 1, DEVICE_UI_NAME); + if (r < 0) { + pr_dbg("aml_demod_ui: failed to alloc major number\n"); + r = -ENODEV; + unregister_chrdev_region(aml_demod_devno_ui, 1); + class_unregister(&aml_demod_ui_class); + return r; + } + + aml_demod_cdevp_ui = kmalloc(sizeof(struct cdev), GFP_KERNEL); + if (!aml_demod_cdevp_ui) { + r = -ENOMEM; + unregister_chrdev_region(aml_demod_devno_ui, 1); + kfree(aml_demod_cdevp_ui); + class_unregister(&aml_demod_ui_class); + return r; + } + /* connect the file operation with cdev */ + cdev_init(aml_demod_cdevp_ui, &aml_demod_ui_fops); + aml_demod_cdevp_ui->owner = THIS_MODULE; + /* connect the major/minor number to cdev */ + r = cdev_add(aml_demod_cdevp_ui, aml_demod_devno_ui, 1); + if (r) { + pr_dbg("aml_demod_ui:failed to add cdev\n"); + unregister_chrdev_region(aml_demod_devno_ui, 1); + cdev_del(aml_demod_cdevp_ui); + kfree(aml_demod_cdevp_ui); + class_unregister(&aml_demod_ui_class); + return r; + } + + aml_demod_ui_dev = device_create(&aml_demod_ui_class, NULL, + MKDEV(MAJOR(aml_demod_devno_ui), 0), + NULL, DEVICE_UI_NAME); + + if (IS_ERR(aml_demod_ui_dev)) { + pr_dbg("Can't create aml_demod device\n"); + unregister_chrdev_region(aml_demod_devno_ui, 1); + cdev_del(aml_demod_cdevp_ui); + kfree(aml_demod_cdevp_ui); + class_unregister(&aml_demod_ui_class); + return r; + } + + return r; +} + +void aml_demod_exit_ui(void) +{ + unregister_chrdev_region(aml_demod_devno_ui, 1); + cdev_del(aml_demod_cdevp_ui); + kfree(aml_demod_cdevp_ui); + class_unregister(&aml_demod_ui_class); +} + +static struct device *aml_demod_dev; +static dev_t aml_demod_devno; +static struct cdev *aml_demod_cdevp; + +#ifdef CONFIG_AM_DEMOD_DVBAPI +int aml_demod_init(void) +#else +static int __init aml_demod_init(void) +#endif +{ + int r = 0; + + pr_dbg("Amlogic Demod DVB-T/C DebugIF Init\n"); + + init_waitqueue_head(&lock_wq); + + /* hook demod isr */ + /* r = request_irq(INT_DEMOD, &aml_demod_isr, + * IRQF_SHARED, "aml_demod", + * (void *)aml_demod_dev_id); + * if (r) { + * pr_dbg("aml_demod irq register error.\n"); + * r = -ENOENT; + * goto err0; + * } + */ + + /* sysfs node creation */ + r = class_register(&aml_demod_class); + if (r) { + pr_dbg("create aml_demod class fail\r\n"); + goto err1; + } + + r = alloc_chrdev_region(&aml_demod_devno, 0, 1, DEVICE_NAME); + if (r < 0) { + pr_dbg("aml_demod: failed to alloc major number\n"); + r = -ENODEV; + goto err2; + } + + aml_demod_cdevp = kmalloc(sizeof(struct cdev), GFP_KERNEL); + if (!aml_demod_cdevp) { + r = -ENOMEM; + goto err3; + } + /* connect the file operation with cdev */ + cdev_init(aml_demod_cdevp, &aml_demod_fops); + aml_demod_cdevp->owner = THIS_MODULE; + /* connect the major/minor number to cdev */ + r = cdev_add(aml_demod_cdevp, aml_demod_devno, 1); + if (r) { + pr_dbg("aml_demod:failed to add cdev\n"); + goto err4; + } + + aml_demod_dev = device_create(&aml_demod_class, NULL, + MKDEV(MAJOR(aml_demod_devno), 0), NULL, + DEVICE_NAME); + + if (IS_ERR(aml_demod_dev)) { + pr_dbg("Can't create aml_demod device\n"); + goto err5; + } + pr_dbg("Amlogic Demod DVB-T/C DebugIF Init ok----------------\n"); +#if defined(CONFIG_AM_AMDEMOD_FPGA_VER) && !defined(CONFIG_AM_DEMOD_DVBAPI) + pr_dbg("sdio_init\n"); + sdio_init(); +#endif + aml_demod_ui_init(); + + return 0; + +err5: + cdev_del(aml_demod_cdevp); +err4: + kfree(aml_demod_cdevp); + +err3: + unregister_chrdev_region(aml_demod_devno, 1); + +err2: +/* free_irq(INT_DEMOD, (void *)aml_demod_dev_id);*/ + +err1: + class_unregister(&aml_demod_class); + +/* err0:*/ + return r; +} + +#ifdef CONFIG_AM_DEMOD_DVBAPI +void aml_demod_exit(void) +#else +static void __exit aml_demod_exit(void) +#endif +{ + pr_dbg("Amlogic Demod DVB-T/C DebugIF Exit\n"); + + unregister_chrdev_region(aml_demod_devno, 1); + device_destroy(&aml_demod_class, MKDEV(MAJOR(aml_demod_devno), 0)); + cdev_del(aml_demod_cdevp); + kfree(aml_demod_cdevp); + + /* free_irq(INT_DEMOD, (void *)aml_demod_dev_id); */ + + class_unregister(&aml_demod_class); + + aml_demod_exit_ui(); +} + +#ifndef CONFIG_AM_DEMOD_DVBAPI +module_init(aml_demod_init); +module_exit(aml_demod_exit); + +MODULE_LICENSE("GPL"); +/*MODULE_AUTHOR(DRV_AUTHOR);*/ +/*MODULE_DESCRIPTION(DRV_DESC);*/ +#endif diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/amlfrontend.c b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/amlfrontend.c new file mode 100644 index 000000000000..357b6db90966 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/amlfrontend.c @@ -0,0 +1,1402 @@ +/***************************************************************** + ** + ** Copyright (C) 2009 Amlogic,Inc. + ** All rights reserved + ** Filename : amlfrontend.c + ** + ** comment: + ** Driver for m6_demod demodulator + ** author : + ** Shijie.Rong@amlogic + ** version : + ** v1.0 12/3/13 + ** v2.0 15/10/12 + **************************************************************** + */ + +/* + * Driver for gxtv_demod demodulator + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARC_700 +#include +#else +/* #include */ +#endif +#include +#include +#include "../aml_fe.h" + +#include +#include +#include "demod_func.h" +#include "../aml_dvb.h" +#include "amlfrontend.h" + +MODULE_PARM_DESC(debug_aml, "\n\t\t Enable frontend debug information"); +static int debug_aml; +module_param(debug_aml, int, 0644); + +#define pr_dbg(a ...) \ + do { \ + if (debug_aml) { \ + printk(a); \ + } \ + } while (0) +#define pr_error(fmt, args ...) pr_err("GXTV_DEMOD: "fmt, ## args) +#define pr_inf(fmt, args...) pr_err("GXTV_DEMOD: " fmt, ## args) + +static int last_lock = -1; +#define DEMOD_DEVICE_NAME "gxtv_demod" +static int cci_thread; +static int freq_dvbc; +static struct aml_demod_sta demod_status; +static fe_modulation_t atsc_mode = VSB_8; + +long *mem_buf; + +MODULE_PARM_DESC(frontend_mode, "\n\t\t Frontend mode 0-DVBC, 1-DVBT"); +static int frontend_mode = -1; +module_param(frontend_mode, int, 0444); + +MODULE_PARM_DESC(frontend_i2c, "\n\t\t IIc adapter id of frontend"); +static int frontend_i2c = -1; +module_param(frontend_i2c, int, 0444); + +MODULE_PARM_DESC(frontend_tuner, + "\n\t\t Frontend tuner type 0-NULL, 1-DCT7070, 2-Maxliner, 3-FJ2207, 4-TD1316"); +static int frontend_tuner = -1; +module_param(frontend_tuner, int, 0444); + +MODULE_PARM_DESC(frontend_tuner_addr, "\n\t\t Tuner IIC address of frontend"); +static int frontend_tuner_addr = -1; +module_param(frontend_tuner_addr, int, 0444); +static int autoflags, autoFlagsTrig; +static struct mutex aml_lock; + +static int Gxtv_Demod_Dvbc_Init(struct aml_fe_dev *dev, int mode); + +static ssize_t dvbc_auto_sym_show(struct class *cls, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "dvbc_autoflags: %s\n", autoflags ? "on" : "off"); +} + +static ssize_t dvbc_auto_sym_store(struct class *cls, + struct class_attribute *attr, + const char *buf, size_t count) +{ + + return 0; +} + +static unsigned int dtmb_mode; + +enum { + DTMB_READ_STRENGTH = 0, + DTMB_READ_SNR = 1, + DTMB_READ_LOCK = 2, + DTMB_READ_BCH = 3, +}; + + + +int convert_snr(int in_snr) +{ + int out_snr; + static int calce_snr[40] = { + 5, 6, 8, 10, 13, + 16, 20, 25, 32, 40, + 50, 63, 80, 100, 126, + 159, 200, 252, 318, 400, + 504, 634, 798, 1005, 1265, + 1592, 2005, 2524, 3177, 4000, + 5036, 6340, 7981, 10048, 12649, + 15924, 20047, 25238, 31773, 40000}; + for (out_snr = 1 ; out_snr <= 40; out_snr++) + if (in_snr <= calce_snr[out_snr]) + break; + + return out_snr; +} + + +static ssize_t dtmb_para_show(struct class *cls, + struct class_attribute *attr, char *buf) +{ + int snr, lock_status, bch, agc_if_gain; + struct dvb_frontend *dvbfe; + int strength = 0; + + if (dtmb_mode == DTMB_READ_STRENGTH) { + dvbfe = get_si2177_tuner(); + if (dvbfe != NULL) + if (dvbfe->ops.tuner_ops.get_strength) { + strength = + dvbfe->ops.tuner_ops.get_strength(dvbfe); + } + if (strength <= -56) { + agc_if_gain = + ((dtmb_read_reg(DTMB_TOP_FRONT_AGC))&0x3ff); + strength = dtmb_get_power_strength(agc_if_gain); + } + return sprintf(buf, "strength is %d\n", strength); + } else if (dtmb_mode == DTMB_READ_SNR) { + snr = dtmb_read_reg(DTMB_TOP_FEC_LOCK_SNR) & 0x3fff; + snr = convert_snr(snr); + return sprintf(buf, "snr is %d\n", snr); + } else if (dtmb_mode == DTMB_READ_LOCK) { + lock_status = + (dtmb_read_reg(DTMB_TOP_FEC_LOCK_SNR) >> 14) & 0x1; + return sprintf(buf, "lock_status is %d\n", lock_status); + } else if (dtmb_mode == DTMB_READ_BCH) { + bch = dtmb_read_reg(DTMB_TOP_FEC_BCH_ACC); + return sprintf(buf, "bch is %d\n", bch); + } else { + return sprintf(buf, "dtmb_para_show can't match mode\n"); + } +} + + + +static ssize_t dtmb_para_store(struct class *cls, + struct class_attribute *attr, + const char *buf, size_t count) +{ + if (buf[0] == '0') + dtmb_mode = DTMB_READ_STRENGTH; + else if (buf[0] == '1') + dtmb_mode = DTMB_READ_SNR; + else if (buf[0] == '2') + dtmb_mode = DTMB_READ_LOCK; + else if (buf[0] == '3') + dtmb_mode = DTMB_READ_BCH; + + return count; +} + +static int readregdata; + +static ssize_t dvbc_reg_show(struct class *cls, struct class_attribute *attr, + char *buf) +{ +/* int readregaddr=0;*/ + char *pbuf = buf; + + pbuf += sprintf(pbuf, "%x", readregdata); + + pr_dbg("read dvbc_reg\n"); + return pbuf - buf; +} + +static ssize_t dvbc_reg_store(struct class *cls, struct class_attribute *attr, + const char *buf, size_t count) +{ + return 0; +} + +static CLASS_ATTR(auto_sym, 0644, dvbc_auto_sym_show, dvbc_auto_sym_store); +static CLASS_ATTR(dtmb_para, 0644, dtmb_para_show, dtmb_para_store); +static CLASS_ATTR(dvbc_reg, 0644, dvbc_reg_show, dvbc_reg_store); + +#if 0 +static irqreturn_t amdemod_isr(int irq, void *data) +{ +/* struct aml_fe_dev *state = data; + * + * #define dvb_isr_islock() (((frontend_mode==0)&&dvbc_isr_islock()) \ + * ||((frontend_mode==1)&&dvbt_isr_islock())) + * #define dvb_isr_monitor() do {\ + * if(frontend_mode==1) dvbt_isr_monitor(); }while(0) + * #define dvb_isr_cancel() do { if(frontend_mode==1) dvbt_isr_cancel(); \ + * else if(frontend_mode==0) dvbc_isr_cancel();}while(0) + * + * dvb_isr_islock(); + * { + * if(waitqueue_active(&state->lock_wq)) + * wake_up_interruptible(&state->lock_wq); + * } + * + * dvb_isr_monitor(); + * + * dvb_isr_cancel(); + */ + + return IRQ_HANDLED; +} +#endif + +static int install_isr(struct aml_fe_dev *state) +{ + int r = 0; + + /* hook demod isr */ +/* pr_dbg("amdemod irq register[IRQ(%d)].\n", INT_DEMOD); + * r = request_irq(INT_DEMOD, &amdemod_isr, + * IRQF_SHARED, "amldemod", + * (void *)state); + * if (r) { + * pr_error("amdemod irq register error.\n"); + * } + */ + return r; +} + + +static int amdemod_qam(fe_modulation_t qam) +{ + switch (qam) { + case QAM_16: + return 0; + case QAM_32: + return 1; + case QAM_64: + return 2; + case QAM_128: + return 3; + case QAM_256: + return 4; + case VSB_8: + return 5; + case QAM_AUTO: + return 6; + default: + return 2; + } + return 2; +} + +static int amdemod_stat_islock(struct aml_fe_dev *dev, int mode) +{ + struct aml_demod_sts demod_sts; + int lock_status; + int dvbt_status1; + + if (mode == 0) { + /*DVBC*/ + /*dvbc_status(state->sta, state->i2c, &demod_sts);*/ + demod_sts.ch_sts = apb_read_reg(QAM_BASE + 0x18); + return demod_sts.ch_sts & 0x1; + } else if (mode == 1) { + /*DVBT*/ + dvbt_status1 = + ((apb_read_reg(DVBT_BASE + (0x0a << 2)) >> 20) & 0x3ff); + lock_status = (apb_read_reg(DVBT_BASE + (0x2a << 2))) & 0xf; + if ((((lock_status) == 9) || ((lock_status) == 10)) + && ((dvbt_status1) != 0)) + return 1; + else + return 0; + /*((apb_read_reg(DVBT_BASE+0x0)>>12)&0x1);// + * dvbt_get_status_ops()->get_status(&demod_sts, &demod_sta); + */ + } else if (mode == 2) { + /*ISDBT*/ + /*return dvbt_get_status_ops()->get_status + * (demod_sts, demod_sta); + */ + } else if (mode == 3) { + /*ATSC*/ + if ((atsc_mode == QAM_64) || (atsc_mode == QAM_256)) + return (atsc_read_iqr_reg() >> 16) == 0x1f; + else if (atsc_mode == VSB_8) + return atsc_read_reg(0x0980) == 0x79; + else + return (atsc_read_iqr_reg() >> 16) == 0x1f; + } else if (mode == 4) { + /*DTMB*/ + /* pr_dbg("DTMB lock status is %u\n", + * ((dtmb_read_reg(DTMB_BASE + (0x0e3 << 2)) >> 14) & + * 0x1)); + */ + return (dtmb_read_reg(DTMB_BASE + (0x0e3 << 2)) >> 14) & 0x1; + } + return 0; +} + +#define amdemod_dvbc_stat_islock(dev) amdemod_stat_islock((dev), 0) +#define amdemod_dvbt_stat_islock(dev) amdemod_stat_islock((dev), 1) +#define amdemod_isdbt_stat_islock(dev) amdemod_stat_islock((dev), 2) +#define amdemod_atsc_stat_islock(dev) amdemod_stat_islock((dev), 3) +#define amdemod_dtmb_stat_islock(dev) amdemod_stat_islock((dev), 4) + +static int gxtv_demod_dvbc_set_qam_mode(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct aml_demod_dvbc param; /*mode 0:16, 1:32, 2:64, 3:128, 4:256*/ + + memset(¶m, 0, sizeof(param)); + param.mode = amdemod_qam(c->modulation); + dvbc_set_qam_mode(param.mode); + return 0; +} + +static void gxtv_demod_dvbc_release(struct dvb_frontend *fe) +{ +/* + * struct aml_fe_dev *state = fe->demodulator_priv; + * + * uninstall_isr(state); + * + * kfree(state); + */ +} + +static int gxtv_demod_dvbc_read_status + (struct dvb_frontend *fe, fe_status_t *status) +{ +/* struct aml_fe_dev *dev = afe->dtv_demod;*/ + struct aml_demod_sts demod_sts; +/* struct aml_demod_sta demod_sta;*/ +/* struct aml_demod_i2c demod_i2c;*/ + int ilock; + + demod_sts.ch_sts = apb_read_reg(QAM_BASE + 0x18); +/* dvbc_status(&demod_sta, &demod_i2c, &demod_sts);*/ + if (demod_sts.ch_sts & 0x1) { + ilock = 1; + *status = + FE_HAS_LOCK | FE_HAS_SIGNAL | FE_HAS_CARRIER | + FE_HAS_VITERBI | FE_HAS_SYNC; + } else { + ilock = 0; + *status = FE_TIMEDOUT; + } + if (last_lock != ilock) { + pr_error("%s.\n", + ilock ? "!! >> LOCK << !!" : "!! >> UNLOCK << !!"); + last_lock = ilock; + } + + return 0; +} + +static int gxtv_demod_dvbc_read_ber(struct dvb_frontend *fe, u32 *ber) +{ + /*struct aml_fe_dev *dev = afe->dtv_demod;*/ + struct aml_demod_sts demod_sts; + struct aml_demod_i2c demod_i2c; + struct aml_demod_sta demod_sta; + + dvbc_status(&demod_sta, &demod_i2c, &demod_sts); + *ber = demod_sts.ch_ber; + return 0; +} + +static int gxtv_demod_dvbc_read_signal_strength + (struct dvb_frontend *fe, u16 *strength) +{ + struct aml_fe *afe = fe->demodulator_priv; + struct aml_fe_dev *dev = afe->dtv_demod; + + *strength = 256 - tuner_get_ch_power(dev); + + return 0; +} + +static int gxtv_demod_dvbc_read_snr(struct dvb_frontend *fe, u16 *snr) +{ + struct aml_demod_sts demod_sts; + struct aml_demod_i2c demod_i2c; + struct aml_demod_sta demod_sta; + + dvbc_status(&demod_sta, &demod_i2c, &demod_sts); + *snr = demod_sts.ch_snr / 100; + return 0; +} + +static int gxtv_demod_dvbc_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +{ + *ucblocks = 0; + return 0; +} + +/*extern int aml_fe_analog_set_frontend(struct dvb_frontend *fe);*/ + +static int gxtv_demod_dvbc_set_frontend(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct aml_demod_dvbc param; /*mode 0:16, 1:32, 2:64, 3:128, 4:256*/ + struct aml_demod_sts demod_sts; + struct aml_demod_i2c demod_i2c; + struct aml_fe *afe = fe->demodulator_priv; + struct aml_fe_dev *dev = afe->dtv_demod; + int error, times; + + demod_i2c.tuner = dev->drv->id; + demod_i2c.addr = dev->i2c_addr; + times = 2; + memset(¶m, 0, sizeof(param)); + param.ch_freq = c->frequency / 1000; + param.mode = amdemod_qam(c->modulation); + param.symb_rate = c->symbol_rate / 1000; + if ((param.mode == 3) && (demod_status.tmp != Adc_mode)) { + Gxtv_Demod_Dvbc_Init(dev, Adc_mode); + pr_dbg("Gxtv_Demod_Dvbc_Init,Adc_mode\n"); + } else { + /*Gxtv_Demod_Dvbc_Init(dev,Cry_mode);*/ + } + if (autoflags == 0) { + /*pr_dbg("QAM_TUNING mode\n");*/ + /*flag=0;*/ + } + if ((autoflags == 1) && (autoFlagsTrig == 0) + && (freq_dvbc == param.ch_freq)) { + pr_dbg("now is auto symbrating\n"); + return 0; + } + autoFlagsTrig = 0; + last_lock = -1; + pr_dbg("[gxtv_demod_dvbc_set_frontend]PARA\t" + "demod_i2c.tuner is %d||||demod_i2c.addr is %d||||\t" + "param.ch_freq is %d||||param.symb_rate is %d,\t" + "param.mode is %d\n", + demod_i2c.tuner, demod_i2c.addr, param.ch_freq, + param.symb_rate, param.mode); +retry: + aml_dmx_before_retune(afe->ts, fe); + aml_fe_analog_set_frontend(fe); + dvbc_set_ch(&demod_status, &demod_i2c, ¶m); + if (autoflags == 1) { + pr_dbg("QAM_PLAYING mode,start auto sym\n"); + dvbc_set_auto_symtrack(); + /* flag=1;*/ + } +/*rsj_debug*/ + + dvbc_status(&demod_status, &demod_i2c, &demod_sts); + freq_dvbc = param.ch_freq; + + times--; + if (amdemod_dvbc_stat_islock(dev) && times) { + int lock; + + aml_dmx_start_error_check(afe->ts, fe); + msleep(20); + error = aml_dmx_stop_error_check(afe->ts, fe); + lock = amdemod_dvbc_stat_islock(dev); + if ((error > 200) || !lock) { + pr_error + ("amlfe too many error, error count:%d\t" + "lock statuc:%d, retry\n", + error, lock); + goto retry; + } + } + + aml_dmx_after_retune(afe->ts, fe); + + afe->params = *c; +/* afe->params.frequency = c->frequency; + * afe->params.u.qam.symbol_rate = c->symbol_rate; + * afe->params.u.qam.modulation = c->modulation; + */ + + pr_dbg("AML amldemod => frequency=%d,symbol_rate=%d\r\n", c->frequency, + c->symbol_rate); + return 0; +} + +static int gxtv_demod_dvbc_get_frontend(struct dvb_frontend *fe) +{ /*these content will be writed into eeprom .*/ + struct aml_fe *afe = fe->demodulator_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + int qam_mode; + + qam_mode = apb_read_reg(QAM_BASE + 0x008); + afe->params.modulation = (qam_mode & 7) + 1; + pr_dbg("[mode] is %d\n", afe->params.modulation); + + *c = afe->params; +/* c->modulation= afe->params.u.qam.modulation; + * c->frequency= afe->params.frequency; + * c->symbol_rate= afe->params.u.qam.symbol_rate; + */ + return 0; +} + +static int Gxtv_Demod_Dvbc_Init(struct aml_fe_dev *dev, int mode) +{ + struct aml_demod_sys sys; + struct aml_demod_i2c i2c; + + pr_dbg("AML Demod DVB-C init\r\n"); + memset(&sys, 0, sizeof(sys)); + memset(&i2c, 0, sizeof(i2c)); + i2c.tuner = dev->drv->id; + i2c.addr = dev->i2c_addr; + /* 0 -DVBC, 1-DVBT, ISDBT, 2-ATSC*/ + demod_status.dvb_mode = Gxtv_Dvbc; + + if (mode == Adc_mode) { + sys.adc_clk = Adc_Clk_25M; + sys.demod_clk = Demod_Clk_200M; + demod_status.tmp = Adc_mode; + } else { + sys.adc_clk = Adc_Clk_24M; + sys.demod_clk = Demod_Clk_72M; + demod_status.tmp = Cry_mode; + } + demod_status.ch_if = Si2176_5M_If * 1000; + pr_dbg("[%s]adc_clk is %d,demod_clk is %d\n", __func__, sys.adc_clk, + sys.demod_clk); + autoFlagsTrig = 0; + demod_set_sys(&demod_status, &i2c, &sys); + return 0; +} + +static void gxtv_demod_dvbt_release(struct dvb_frontend *fe) +{ +/* + * struct aml_fe_dev *state = fe->demodulator_priv; + * + * uninstall_isr(state); + * + * kfree(state); + */ +} + +static int gxtv_demod_dvbt_read_status + (struct dvb_frontend *fe, fe_status_t *status) +{ +/* struct aml_fe *afe = fe->demodulator_priv;*/ + struct aml_demod_i2c demod_i2c; + struct aml_demod_sta demod_sta; + int ilock; + unsigned char s = 0; + + s = dvbt_get_status_ops()->get_status(&demod_sta, &demod_i2c); + if (s == 1) { + ilock = 1; + *status = + FE_HAS_LOCK | FE_HAS_SIGNAL | FE_HAS_CARRIER | + FE_HAS_VITERBI | FE_HAS_SYNC; + } else { + ilock = 0; + *status = FE_TIMEDOUT; + } + if (last_lock != ilock) { + pr_error("%s.\n", + ilock ? "!! >> LOCK << !!" : "!! >> UNLOCK << !!"); + last_lock = ilock; + } + + return 0; +} + +static int gxtv_demod_dvbt_read_ber(struct dvb_frontend *fe, u32 *ber) +{ +/* struct aml_fe *afe = fe->demodulator_priv;*/ + struct aml_demod_i2c demod_i2c; + struct aml_demod_sta demod_sta; + + *ber = dvbt_get_status_ops()->get_ber(&demod_sta, &demod_i2c) & 0xffff; + return 0; +} + +static int gxtv_demod_dvbt_read_signal_strength + (struct dvb_frontend *fe, u16 *strength) +{ + struct aml_fe *afe = fe->demodulator_priv; + struct aml_fe_dev *dev = afe->dtv_demod; + + *strength = 256 - tuner_get_ch_power(dev); + pr_dbg("[RSJ]tuner strength is %d dbm\n", *strength); + return 0; +} + +static int gxtv_demod_dvbt_read_snr(struct dvb_frontend *fe, u16 *snr) +{ +/* struct aml_fe *afe = fe->demodulator_priv;*/ +/* struct aml_demod_sts demod_sts;*/ + struct aml_demod_i2c demod_i2c; + struct aml_demod_sta demod_sta; + + *snr = dvbt_get_status_ops()->get_snr(&demod_sta, &demod_i2c); + *snr /= 8; + pr_dbg("[RSJ]snr is %d dbm\n", *snr); + return 0; +} + +static int gxtv_demod_dvbt_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +{ + *ucblocks = 0; + return 0; +} + +static int gxtv_demod_dvbt_set_frontend(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + /*struct aml_demod_sts demod_sts;*/ + struct aml_demod_i2c demod_i2c; + int error, times; + struct aml_demod_dvbt param; + struct aml_fe *afe = fe->demodulator_priv; + struct aml_fe_dev *dev = afe->dtv_demod; + + demod_i2c.tuner = dev->drv->id; + demod_i2c.addr = dev->i2c_addr; + + times = 2; + + /*////////////////////////////////////*/ + /* bw == 0 : 8M*/ + /* 1 : 7M*/ + /* 2 : 6M*/ + /* 3 : 5M*/ + /* agc_mode == 0: single AGC*/ + /* 1: dual AGC*/ + /*////////////////////////////////////*/ + memset(¶m, 0, sizeof(param)); + param.ch_freq = c->frequency / 1000; + param.bw = c->bandwidth_hz; + param.agc_mode = 1; + /*ISDBT or DVBT : 0 is QAM, 1 is DVBT, 2 is ISDBT, + * 3 is DTMB, 4 is ATSC + */ + param.dat0 = 1; + last_lock = -1; + +retry: + aml_dmx_before_retune(AM_TS_SRC_TS2, fe); + aml_fe_analog_set_frontend(fe); + dvbt_set_ch(&demod_status, &demod_i2c, ¶m); + + /* for(count=0;count<10;count++){ + * if(amdemod_dvbt_stat_islock(dev)){ + * pr_dbg("first lock success\n"); + * break; + * } + * + * msleep(200); + * } + */ +/*rsj_debug*/ + +/**/ + + times--; + if (amdemod_dvbt_stat_islock(dev) && times) { + int lock; + + aml_dmx_start_error_check(AM_TS_SRC_TS2, fe); + msleep(20); + error = aml_dmx_stop_error_check(AM_TS_SRC_TS2, fe); + lock = amdemod_dvbt_stat_islock(dev); + if ((error > 200) || !lock) { + pr_error + ("amlfe too many error,\t" + "error count:%d lock statuc:%d, retry\n", + error, lock); + goto retry; + } + } + + aml_dmx_after_retune(AM_TS_SRC_TS2, fe); + + afe->params = *c; + + /*pr_dbg("AML amldemod => frequency=%d,symbol_rate=%d\r\n", + * p->frequency,p->u.qam.symbol_rate); + */ + return 0; +} + +static int gxtv_demod_dvbt_get_frontend(struct dvb_frontend *fe) +{ /*these content will be writed into eeprom .*/ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct aml_fe *afe = fe->demodulator_priv; + + *c = afe->params; + return 0; +} + +int Gxtv_Demod_Dvbt_Init(struct aml_fe_dev *dev) +{ + struct aml_demod_sys sys; + struct aml_demod_i2c i2c; + + pr_dbg("AML Demod DVB-T init\r\n"); + + memset(&sys, 0, sizeof(sys)); + memset(&i2c, 0, sizeof(i2c)); + memset(&demod_status, 0, sizeof(demod_status)); + i2c.tuner = dev->drv->id; + i2c.addr = dev->i2c_addr; + /* 0 -DVBC, 1-DVBT, ISDBT, 2-ATSC*/ + demod_status.dvb_mode = Gxtv_Dvbt_Isdbt; + sys.adc_clk = Adc_Clk_24M; + sys.demod_clk = Demod_Clk_60M; + demod_status.ch_if = Si2176_5M_If * 1000; + demod_set_sys(&demod_status, &i2c, &sys); + return 0; +} + +static void gxtv_demod_atsc_release(struct dvb_frontend *fe) +{ +/* + * struct aml_fe_dev *state = fe->demodulator_priv; + * + * uninstall_isr(state); + * + * kfree(state); + */ +} + +static int gxtv_demod_atsc_set_qam_mode(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct aml_demod_atsc param; /*mode 3:64, 5:256, 7:vsb*/ + fe_modulation_t mode; + + memset(¶m, 0, sizeof(param)); + mode = c->modulation; + pr_dbg("mode is %d\n", mode); + atsc_qam_set(mode); + return 0; +} + +static int gxtv_demod_atsc_read_status + (struct dvb_frontend *fe, fe_status_t *status) +{ + struct aml_fe *afe = fe->demodulator_priv; + struct aml_fe_dev *dev = afe->dtv_demod; +/* struct aml_demod_i2c demod_i2c;*/ +/* struct aml_demod_sta demod_sta;*/ + int ilock; + unsigned char s = 0; + + s = amdemod_atsc_stat_islock(dev); + if (s == 1) { + ilock = 1; + *status = + FE_HAS_LOCK | FE_HAS_SIGNAL | FE_HAS_CARRIER | + FE_HAS_VITERBI | FE_HAS_SYNC; + } else { + ilock = 0; + *status = FE_TIMEDOUT; + } + if (last_lock != ilock) { + pr_error("%s.\n", + ilock ? "!! >> LOCK << !!" : "!! >> UNLOCK << !!"); + last_lock = ilock; + } + + return 0; +} + +static int gxtv_demod_atsc_read_ber(struct dvb_frontend *fe, u32 *ber) +{ +/* struct aml_fe *afe = fe->demodulator_priv;*/ +/* struct aml_fe_dev *dev = afe->dtv_demod;*/ +/* struct aml_demod_sts demod_sts;*/ +/* struct aml_demod_i2c demod_i2c;*/ +/* struct aml_demod_sta demod_sta;*/ + +/* check_atsc_fsm_status();*/ + return 0; +} + +static int gxtv_demod_atsc_read_signal_strength + (struct dvb_frontend *fe, u16 *strength) +{ + struct aml_fe *afe = fe->demodulator_priv; + struct aml_fe_dev *dev = afe->dtv_demod; + + *strength = tuner_get_ch_power(dev); + return 0; +} + +static int gxtv_demod_atsc_read_snr(struct dvb_frontend *fe, u16 *snr) +{ +/* struct aml_fe *afe = fe->demodulator_priv;*/ +/* struct aml_fe_dev *dev = afe->dtv_demod;*/ + +/* struct aml_demod_sts demod_sts;*/ +/* struct aml_demod_i2c demod_i2c;*/ +/* struct aml_demod_sta demod_sta;*/ + +/* * snr=check_atsc_fsm_status();*/ + return 0; +} + +static int gxtv_demod_atsc_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +{ + *ucblocks = 0; + return 0; +} + +static int gxtv_demod_atsc_set_frontend(struct dvb_frontend *fe) +{ +/* struct amlfe_state *state = fe->demodulator_priv;*/ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct aml_demod_atsc param; +/* struct aml_demod_sta demod_sta;*/ +/* struct aml_demod_sts demod_sts;*/ + struct aml_demod_i2c demod_i2c; + int error, times; + struct aml_fe *afe = fe->demodulator_priv; + struct aml_fe_dev *dev = afe->dtv_demod; + + demod_i2c.tuner = dev->drv->id; + demod_i2c.addr = dev->i2c_addr; + times = 2; + + memset(¶m, 0, sizeof(param)); + param.ch_freq = c->frequency / 1000; + + last_lock = -1; + /*p->u.vsb.modulation=QAM_64;*/ + atsc_mode = c->modulation; + /* param.mode = amdemod_qam(p->u.vsb.modulation);*/ + param.mode = c->modulation; + +retry: + aml_dmx_before_retune(AM_TS_SRC_TS2, fe); + aml_fe_analog_set_frontend(fe); + atsc_set_ch(&demod_status, &demod_i2c, ¶m); + + /*{ + * int ret; + * ret = wait_event_interruptible_timeout( + * dev->lock_wq, amdemod_atsc_stat_islock(dev), 4*HZ); + * if(!ret) pr_error("amlfe wait lock timeout.\n"); + * } + */ +/*rsj_debug*/ + /* int count; + * for(count=0;count<10;count++){ + * if(amdemod_atsc_stat_islock(dev)){ + * pr_dbg("first lock success\n"); + * break; + * } + * + * msleep(200); + * } + */ + + times--; + if (amdemod_atsc_stat_islock(dev) && times) { + int lock; + + aml_dmx_start_error_check(AM_TS_SRC_TS2, fe); + msleep(20); + error = aml_dmx_stop_error_check(AM_TS_SRC_TS2, fe); + lock = amdemod_atsc_stat_islock(dev); + if ((error > 200) || !lock) { + pr_error + ("amlfe too many error,\t" + "error count:%d lock statuc:%d, retry\n", + error, lock); + goto retry; + } + } + + aml_dmx_after_retune(AM_TS_SRC_TS2, fe); + + afe->params = *c; + /*pr_dbg("AML amldemod => frequency=%d,symbol_rate=%d\r\n", + * p->frequency,p->u.qam.symbol_rate); + */ + return 0; +} + +static int gxtv_demod_atsc_get_frontend(struct dvb_frontend *fe) +{ /*these content will be writed into eeprom .*/ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct aml_fe *afe = fe->demodulator_priv; + + pr_dbg("c->frequency is %d\n", c->frequency); + *c = afe->params; + return 0; +} + +int Gxtv_Demod_Atsc_Init(struct aml_fe_dev *dev) +{ + struct aml_demod_sys sys; + struct aml_demod_i2c i2c; + + pr_dbg("AML Demod ATSC init\r\n"); + + memset(&sys, 0, sizeof(sys)); + memset(&i2c, 0, sizeof(i2c)); + memset(&demod_status, 0, sizeof(demod_status)); + /* 0 -DVBC, 1-DVBT, ISDBT, 2-ATSC*/ + demod_status.dvb_mode = Gxtv_Atsc; + sys.adc_clk = Adc_Clk_25_2M; /*Adc_Clk_26M;*/ + sys.demod_clk = Demod_Clk_75M; /*Demod_Clk_71M;//Demod_Clk_78M;*/ + demod_status.ch_if = 6350; + demod_status.tmp = Adc_mode; + demod_set_sys(&demod_status, &i2c, &sys); + return 0; +} + +static void gxtv_demod_dtmb_release(struct dvb_frontend *fe) +{ +/* + * struct aml_fe_dev *state = fe->demodulator_priv; + * + * uninstall_isr(state); + * + * kfree(state); + */ +} + +static int gxtv_demod_dtmb_read_status + (struct dvb_frontend *fe, fe_status_t *status) +{ + struct aml_fe *afe = fe->demodulator_priv; + struct aml_fe_dev *dev = afe->dtv_demod; +/* struct aml_demod_i2c demod_i2c;*/ +/* struct aml_demod_sta demod_sta;*/ + int ilock; + unsigned char s = 0; + +/* s = amdemod_dtmb_stat_islock(dev);*/ +/* if(s==1)*/ + if (is_meson_txl_cpu()) + s = dtmb_check_status_txl(fe); + else + s = dtmb_check_status_gxtv(fe); + s = amdemod_dtmb_stat_islock(dev); +/* s=1;*/ + if (s == 1) { + ilock = 1; + *status = + FE_HAS_LOCK | FE_HAS_SIGNAL | FE_HAS_CARRIER | + FE_HAS_VITERBI | FE_HAS_SYNC; + } else { + ilock = 0; + *status = FE_TIMEDOUT; + } + if (last_lock != ilock) { + pr_error("%s.\n", + ilock ? "!! >> LOCK << !!" : "!! >> UNLOCK << !!"); + last_lock = ilock; + } + + return 0; +} + +static int gxtv_demod_dtmb_read_ber(struct dvb_frontend *fe, u32 *ber) +{ +/* struct aml_fe *afe = fe->demodulator_priv;*/ +/* struct aml_fe_dev *dev = afe->dtv_demod;*/ +/* struct aml_demod_sts demod_sts;*/ +/* struct aml_demod_i2c demod_i2c;*/ +/* struct aml_demod_sta demod_sta;*/ + +/* check_atsc_fsm_status();*/ +/* int fec_bch_add; */ +/* fec_bch_add = dtmb_read_reg(0xdf); */ +/* *ber = fec_bch_add; */ + return 0; +} + +static int gxtv_demod_dtmb_read_signal_strength + (struct dvb_frontend *fe, u16 *strength) +{ + struct aml_fe *afe = fe->demodulator_priv; + struct aml_fe_dev *dev = afe->dtv_demod; + + *strength = tuner_get_ch_power(dev); + return 0; +} + +static int gxtv_demod_dtmb_read_snr(struct dvb_frontend *fe, u16 *snr) +{ +/* struct aml_fe *afe = fe->demodulator_priv;*/ +/* struct aml_fe_dev *dev = afe->dtv_demod;*/ +#if 1 + int tmp, snr_avg; + + tmp = snr_avg = 0; + tmp = dtmb_read_reg(DTMB_TOP_FEC_LOCK_SNR); +/* snr_avg = (tmp >> 16) & 0x3fff; + * if (snr_avg >= 2048) + * snr_avg = snr_avg - 4096; + * snr_avg = snr_avg / 32; + */ + *snr = tmp&0xff; +#endif + return 0; +} + +static int gxtv_demod_dtmb_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +{ + *ucblocks = 0; + return 0; +} + +static int gxtv_demod_dtmb_read_fsm(struct dvb_frontend *fe, u32 *fsm_status) +{ + int tmp; + + tmp = dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE0); + *fsm_status = tmp&0xffffffff; + pr_dbg("[rsj] fsm_status is %x\n", *fsm_status); + return 0; +} + + +static int gxtv_demod_dtmb_set_frontend(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct aml_demod_dtmb param; +/* struct aml_demod_sta demod_sta;*/ +/* struct aml_demod_sts demod_sts;*/ + struct aml_demod_i2c demod_i2c; + int times; + struct aml_fe *afe = fe->demodulator_priv; + struct aml_fe_dev *dev = afe->dtv_demod; + + demod_i2c.tuner = dev->drv->id; + demod_i2c.addr = dev->i2c_addr; + times = 2; + pr_dbg("gxtv_demod_dtmb_set_frontend,freq is %d\n", c->frequency); + memset(¶m, 0, sizeof(param)); + param.ch_freq = c->frequency / 1000; + + last_lock = -1; +/* demod_power_switch(PWR_OFF); */ + aml_fe_analog_set_frontend(fe); + msleep(100); +/* demod_power_switch(PWR_ON); */ + dtmb_set_ch(&demod_status, &demod_i2c, ¶m); + afe->params = *c; + /* pr_dbg("AML amldemod => frequency=%d,symbol_rate=%d\r\n", + * p->frequency,p->u.qam.symbol_rate); + */ + return 0; +} + +static int gxtv_demod_dtmb_get_frontend(struct dvb_frontend *fe) +{ /*these content will be writed into eeprom .*/ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct aml_fe *afe = fe->demodulator_priv; + + *c = afe->params; +/* pr_dbg("[get frontend]c->frequency is %d\n",c->frequency);*/ + return 0; +} + +int Gxtv_Demod_Dtmb_Init(struct aml_fe_dev *dev) +{ + struct aml_demod_sys sys; + struct aml_demod_i2c i2c; + + pr_dbg("AML Demod DTMB init\r\n"); + + memset(&sys, 0, sizeof(sys)); + memset(&i2c, 0, sizeof(i2c)); + memset(&demod_status, 0, sizeof(demod_status)); + /* 0 -DVBC, 1-DVBT, ISDBT, 2-ATSC*/ + demod_status.dvb_mode = Gxtv_Dtmb; + if (is_meson_txl_cpu()) { + sys.adc_clk = Adc_Clk_25M; /*Adc_Clk_26M;*/ + sys.demod_clk = Demod_Clk_225M; + } else { + sys.adc_clk = Adc_Clk_25M; /*Adc_Clk_26M;*/ + sys.demod_clk = Demod_Clk_200M; + } + demod_status.ch_if = Si2176_5M_If; + demod_status.tmp = Adc_mode; + demod_status.spectrum = dev->spectrum; + demod_set_sys(&demod_status, &i2c, &sys); + return 0; +} + +static int gxtv_demod_fe_get_ops(struct aml_fe_dev *dev, int mode, void *ops) +{ + struct dvb_frontend_ops *fe_ops = (struct dvb_frontend_ops *)ops; + + if (mode == AM_FE_OFDM) { + fe_ops->info.frequency_min = 51000000; + fe_ops->info.frequency_max = 858000000; + fe_ops->info.frequency_stepsize = 0; + fe_ops->info.frequency_tolerance = 0; + fe_ops->info.caps = + FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | + FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | + FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | + FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | + FE_CAN_RECOVER | FE_CAN_MUTE_TS; + fe_ops->release = gxtv_demod_dvbt_release; + fe_ops->set_frontend = gxtv_demod_dvbt_set_frontend; + fe_ops->get_frontend = gxtv_demod_dvbt_get_frontend; + fe_ops->read_status = gxtv_demod_dvbt_read_status; + fe_ops->read_ber = gxtv_demod_dvbt_read_ber; + fe_ops->read_signal_strength = + gxtv_demod_dvbt_read_signal_strength; + fe_ops->read_snr = gxtv_demod_dvbt_read_snr; + fe_ops->read_ucblocks = gxtv_demod_dvbt_read_ucblocks; + fe_ops->read_dtmb_fsm = NULL; + + pr_dbg("=========================dvbt demod init\r\n"); + Gxtv_Demod_Dvbt_Init(dev); + } else if (mode == AM_FE_QAM) { + fe_ops->info.frequency_min = 51000000; + fe_ops->info.frequency_max = 858000000; + fe_ops->info.frequency_stepsize = 0; + fe_ops->info.frequency_tolerance = 0; + fe_ops->info.caps = + FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | + FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | + FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_32 | + FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_64 | + FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | + FE_CAN_RECOVER | FE_CAN_MUTE_TS; + + fe_ops->release = gxtv_demod_dvbc_release; + fe_ops->set_frontend = gxtv_demod_dvbc_set_frontend; + fe_ops->get_frontend = gxtv_demod_dvbc_get_frontend; + fe_ops->read_status = gxtv_demod_dvbc_read_status; + fe_ops->read_ber = gxtv_demod_dvbc_read_ber; + fe_ops->read_signal_strength = + gxtv_demod_dvbc_read_signal_strength; + fe_ops->read_snr = gxtv_demod_dvbc_read_snr; + fe_ops->read_ucblocks = gxtv_demod_dvbc_read_ucblocks; + fe_ops->set_qam_mode = gxtv_demod_dvbc_set_qam_mode; + fe_ops->read_dtmb_fsm = NULL; + install_isr(dev); + pr_dbg("=========================dvbc demod init\r\n"); + Gxtv_Demod_Dvbc_Init(dev, Adc_mode); + } else if (mode == AM_FE_ATSC) { + fe_ops->info.frequency_min = 51000000; + fe_ops->info.frequency_max = 858000000; + fe_ops->info.frequency_stepsize = 0; + fe_ops->info.frequency_tolerance = 0; + fe_ops->info.caps = + FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | + FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | + FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | + FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | + FE_CAN_RECOVER | FE_CAN_MUTE_TS; + + fe_ops->release = gxtv_demod_atsc_release; + fe_ops->set_frontend = gxtv_demod_atsc_set_frontend; + fe_ops->get_frontend = gxtv_demod_atsc_get_frontend; + fe_ops->read_status = gxtv_demod_atsc_read_status; + fe_ops->read_ber = gxtv_demod_atsc_read_ber; + fe_ops->read_signal_strength = + gxtv_demod_atsc_read_signal_strength; + fe_ops->read_snr = gxtv_demod_atsc_read_snr; + fe_ops->read_ucblocks = gxtv_demod_atsc_read_ucblocks; + fe_ops->set_qam_mode = gxtv_demod_atsc_set_qam_mode; + fe_ops->read_dtmb_fsm = NULL; + Gxtv_Demod_Atsc_Init(dev); + } else if (mode == AM_FE_DTMB) { + fe_ops->info.frequency_min = 51000000; + fe_ops->info.frequency_max = 900000000; + fe_ops->info.frequency_stepsize = 0; + fe_ops->info.frequency_tolerance = 0; + fe_ops->info.caps = + FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | + FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | + FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | + FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | + FE_CAN_RECOVER | FE_CAN_MUTE_TS; + + fe_ops->release = gxtv_demod_dtmb_release; + fe_ops->set_frontend = gxtv_demod_dtmb_set_frontend; + fe_ops->get_frontend = gxtv_demod_dtmb_get_frontend; + fe_ops->read_status = gxtv_demod_dtmb_read_status; + fe_ops->read_ber = gxtv_demod_dtmb_read_ber; + fe_ops->read_signal_strength = + gxtv_demod_dtmb_read_signal_strength; + fe_ops->read_snr = gxtv_demod_dtmb_read_snr; + fe_ops->read_ucblocks = gxtv_demod_dtmb_read_ucblocks; + fe_ops->read_dtmb_fsm = gxtv_demod_dtmb_read_fsm; + Gxtv_Demod_Dtmb_Init(dev); + } + return 0; +} + +static int gxtv_demod_fe_resume(struct aml_fe_dev *dev) +{ + int memstart_dtmb; + + pr_inf("gxtv_demod_fe_resume\n"); +/* demod_power_switch(PWR_ON);*/ + Gxtv_Demod_Dtmb_Init(dev); + memstart_dtmb = dev->fe->dtv_demod->mem_start; + pr_dbg("[im]memstart is %x\n", memstart_dtmb); + dtmb_write_reg(DTMB_FRONT_MEM_ADDR, memstart_dtmb); + pr_dbg("[dtmb]mem_buf is 0x%x\n", + dtmb_read_reg(DTMB_FRONT_MEM_ADDR)); + return 0; +} + +static int gxtv_demod_fe_suspend(struct aml_fe_dev *dev) +{ + pr_inf("gxtv_demod_fe_suspend\n"); +/* demod_power_switch(PWR_OFF);*/ + return 0; +} + +#ifdef CONFIG_CMA +void dtmb_cma_alloc(struct aml_fe_dev *devp) +{ + unsigned int mem_size = devp->cma_mem_size; + + devp->venc_pages = + dma_alloc_from_contiguous(&(devp->this_pdev->dev), + mem_size >> PAGE_SHIFT, 0); + pr_dbg("[cma]mem_size is %d,%d\n", + mem_size, mem_size >> PAGE_SHIFT); + if (devp->venc_pages) { + devp->mem_start = page_to_phys(devp->venc_pages); + devp->mem_size = mem_size; + pr_dbg("demod mem_start = 0x%x, mem_size = 0x%x\n", + devp->mem_start, devp->mem_size); + pr_dbg("demod cma alloc ok!\n"); + } else { + pr_dbg("demod cma mem undefined2.\n"); + } +} + +void dtmb_cma_release(struct aml_fe_dev *devp) +{ + dma_release_from_contiguous(&(devp->this_pdev->dev), + devp->venc_pages, + devp->cma_mem_size>>PAGE_SHIFT); + pr_dbg("demod cma release ok!\n"); + devp->mem_start = 0; + devp->mem_size = 0; +} +#endif + + +static int gxtv_demod_fe_enter_mode(struct aml_fe *fe, int mode) +{ + struct aml_fe_dev *dev = fe->dtv_demod; + int memstart_dtmb; + + /* must enable the adc ref signal for demod, */ + vdac_enable(1, 0x2); + + autoFlagsTrig = 1; + if (cci_thread) + if (dvbc_get_cci_task() == 1) + dvbc_create_cci_task(); + /*mem_buf = (long *)phys_to_virt(memstart);*/ + if (mode == AM_FE_DTMB) { + Gxtv_Demod_Dtmb_Init(dev); + if (fe->dtv_demod->cma_flag == 1) { + pr_dbg("CMA MODE, cma flag is %d,mem size is %d", + fe->dtv_demod->cma_flag, fe->dtv_demod->cma_mem_size); + dtmb_cma_alloc(dev); + memstart_dtmb = dev->mem_start; + } else { + memstart_dtmb = fe->dtv_demod->mem_start; + } + pr_dbg("[im]memstart is %x\n", memstart_dtmb); + dtmb_write_reg(DTMB_FRONT_MEM_ADDR, memstart_dtmb); + pr_dbg("[dtmb]mem_buf is 0x%x\n", + dtmb_read_reg(DTMB_FRONT_MEM_ADDR)); + /* open arbit */ + demod_set_demod_reg(0x8, DEMOD_REG4); + } else if (mode == AM_FE_QAM) { + Gxtv_Demod_Dvbc_Init(dev, Adc_mode); + } + + return 0; +} + +static int gxtv_demod_fe_leave_mode(struct aml_fe *fe, int mode) +{ + struct aml_fe_dev *dev = fe->dtv_demod; + + dtvpll_init_flag(0); + /*dvbc_timer_exit();*/ + if (cci_thread) + dvbc_kill_cci_task(); + if (mode == AM_FE_DTMB) { + /* close arbit */ + demod_set_demod_reg(0x0, DEMOD_REG4); + if (fe->dtv_demod->cma_flag == 1) + dtmb_cma_release(dev); + } + + /* should disable the adc ref signal for demod */ + vdac_enable(0, 0x2); + + return 0; +} + +static struct aml_fe_drv gxtv_demod_dtv_demod_drv = { + .id = AM_DTV_DEMOD_M1, + .name = "AMLDEMOD", + .capability = + AM_FE_QPSK | AM_FE_QAM | AM_FE_ATSC | AM_FE_OFDM | AM_FE_DTMB, + .get_ops = gxtv_demod_fe_get_ops, + .suspend = gxtv_demod_fe_suspend, + .resume = gxtv_demod_fe_resume, + .enter_mode = gxtv_demod_fe_enter_mode, + .leave_mode = gxtv_demod_fe_leave_mode +}; + +struct class *gxtv_clsp; +struct class *gxtv_para_clsp; + +static int __init gxtvdemodfrontend_init(void) +{ + int ret; + + pr_dbg("register gxtv_demod demod driver\n"); + ret = 0; + + dtvpll_lock_init(); + mutex_init(&aml_lock); + + gxtv_clsp = class_create(THIS_MODULE, DEMOD_DEVICE_NAME); + if (!gxtv_clsp) { + pr_error("[gxtv demod]%s:create class error.\n", __func__); + return PTR_ERR(gxtv_clsp); + } + ret = class_create_file(gxtv_clsp, &class_attr_auto_sym); + if (ret) + pr_error("[gxtv demod]%s create class error.\n", __func__); + + ret = class_create_file(gxtv_clsp, &class_attr_dtmb_para); + if (ret) + pr_error("[gxtv demod]%s create class error.\n", __func__); + + ret = class_create_file(gxtv_clsp, &class_attr_dvbc_reg); + if (ret) + pr_error("[gxtv demod]%s create class error.\n", __func__); + + return aml_register_fe_drv(AM_DEV_DTV_DEMOD, &gxtv_demod_dtv_demod_drv); +} + +static void __exit gxtvdemodfrontend_exit(void) +{ + pr_dbg("unregister gxtv_demod demod driver\n"); + + mutex_destroy(&aml_lock); + + class_remove_file(gxtv_clsp, &class_attr_auto_sym); + class_remove_file(gxtv_clsp, &class_attr_dtmb_para); + class_remove_file(gxtv_clsp, &class_attr_dvbc_reg); + class_destroy(gxtv_clsp); + aml_unregister_fe_drv(AM_DEV_DTV_DEMOD, &gxtv_demod_dtv_demod_drv); +} + +fs_initcall(gxtvdemodfrontend_init); +module_exit(gxtvdemodfrontend_exit); + +MODULE_DESCRIPTION("gxtv_demod DVB-T/DVB-C/DTMB Demodulator driver"); +MODULE_AUTHOR("RSJ"); +MODULE_LICENSE("GPL"); diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/demod_func.c b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/demod_func.c new file mode 100644 index 000000000000..9609a93c6b00 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/demod_func.c @@ -0,0 +1,2977 @@ +/*#include "register.h"*/ +/*#include "c_arc_pointer_reg.h"*/ +/*#include "a9_func.h"*/ +/*#include "clk_util.h"*/ +/*#include "c_stimulus.h"*/ +/*#include "a9_l2_func.h"*/ + +#include "demod_func.h" +#include +#include +#include +#include "acf_filter_coefficient.h" +#include + +#define M6D + +/* static void __iomem * demod_meson_reg_map[4]; */ + +#define pr_dbg(fmt, args ...) \ + do { \ + if (debug_demod) \ + pr_info("FE: " fmt, ## args); \ + } while (0) +#define pr_error(fmt, args ...) pr_info("FE: " fmt, ## args) + +MODULE_PARM_DESC(debug_demod, "\n\t\t Enable frontend debug information"); +static int debug_demod; +module_param(debug_demod, int, 0644); + +MODULE_PARM_DESC(demod_timeout, "\n\t\t timeout debug information"); +static int demod_timeout = 120; +module_param(demod_timeout, int, 0644); + +MODULE_PARM_DESC(demod_sync_count, "\n\t\t timeout debug information"); +static int demod_sync_count = 60; +module_param(demod_sync_count, int, 0644); + +MODULE_PARM_DESC(demod_sync_delay_time, "\n\t\t timeout debug information"); +static int demod_sync_delay_time = 8; +module_param(demod_sync_delay_time, int, 0644); + + + +MODULE_PARM_DESC(demod_mobile_power, "\n\t\t demod_mobile_power debug information"); +static int demod_mobile_power = 100; +module_param(demod_mobile_power, int, 0644); + +MODULE_PARM_DESC(demod_enable_performance, "\n\t\t demod_enable_performance information"); +static int demod_enable_performance = 1; +module_param(demod_enable_performance, int, 0644); + + +static struct mutex mp; +static struct mutex dtvpll_init_lock; +static int dtvpll_init; +static int dtmb_spectrum = 2; + + +/* 8vsb */ +static struct atsc_cfg list_8vsb[22] = { + {0x0733, 0x00, 0}, + {0x0734, 0xff, 0}, + {0x0716, 0x02, 0}, /* F06[7] invert spectrum 0x02 0x06 */ + {0x05e7, 0x00, 0}, + {0x05e8, 0x00, 0}, + {0x0f06, 0x80, 0}, + {0x0f09, 0x04, 0}, + {0x070c, 0x18, 0}, + {0x070d, 0x9d, 0}, + {0x070e, 0x89, 0}, + {0x070f, 0x6a, 0}, + {0x0710, 0x75, 0}, + {0x0711, 0x6f, 0}, + {0x072a, 0x02, 0}, + {0x072c, 0x02, 0}, + {0x090d, 0x03, 0}, + {0x090e, 0x02, 0}, + {0x090f, 0x00, 0}, + {0x0900, 0x01, 0}, + {0x0900, 0x00, 0}, + {0x0f00, 0x01, 0}, + {0x0000, 0x00, 1} +}; + +/* 64qam */ +static struct atsc_cfg list_qam64[111] = { + {0x0900, 0x01, 0}, + {0x0f04, 0x08, 0}, + {0x0f06, 0x80, 0}, + {0x0f07, 0x00, 0}, + {0x0f00, 0xe0, 0}, + {0x0f00, 0xec, 0}, + {0x0001, 0x05, 0}, + {0x0002, 0x61, 0}, /* /0x61 invert spectrum */ + {0x0003, 0x3e, 0}, + {0x0004, 0xed, 0}, /* 0x9d */ + {0x0005, 0x10, 0}, + {0x0006, 0xc0, 0}, + {0x0007, 0x5c, 0}, + {0x0008, 0x0f, 0}, + {0x0009, 0x4f, 0}, + {0x000a, 0xfc, 0}, + {0x000b, 0x0c, 0}, + {0x000c, 0x6c, 0}, + {0x000d, 0x3a, 0}, + {0x000e, 0x10, 0}, + {0x000f, 0x02, 0}, + {0x0011, 0x00, 0}, + {0x0012, 0xf5, 0}, + {0x0013, 0x74, 0}, + {0x0014, 0xb9, 0}, + {0x0015, 0x1f, 0}, + {0x0016, 0x80, 0}, + {0x0017, 0x1f, 0}, + {0x0018, 0x0f, 0}, + {0x001e, 0x00, 0}, + {0x001f, 0x00, 0}, + {0x0023, 0x03, 0}, + {0x0025, 0x20, 0}, + {0x0026, 0xff, 0}, + {0x0027, 0xff, 0}, + {0x0028, 0xf8, 0}, + {0x0200, 0x20, 0}, + {0x0201, 0x62, 0}, + {0x0202, 0x23, 0}, + {0x0204, 0x19, 0}, + {0x0205, 0x74, 0}, + {0x0206, 0xab, 0}, + {0x0207, 0xff, 0}, + {0x0208, 0xc0, 0}, + {0x0209, 0xff, 0}, + {0x0211, 0xc0, 0}, + {0x0212, 0xb0, 0}, + {0x0213, 0x05, 0}, + {0x0215, 0x08, 0}, + {0x0222, 0xe0, 0}, + {0x0223, 0xf0, 0}, + {0x0226, 0x40, 0}, + {0x0229, 0x23, 0}, + {0x022a, 0x02, 0}, + {0x022c, 0x01, 0}, + {0x022e, 0x01, 0}, + {0x022f, 0x25, 0}, + {0x0230, 0x40, 0}, + {0x0231, 0x01, 0}, + {0x0734, 0xff, 0}, + {0x073a, 0xff, 0}, + {0x073b, 0x04, 0}, + {0x073c, 0x08, 0}, + {0x073d, 0x08, 0}, + {0x073e, 0x01, 0}, + {0x073f, 0xf8, 0}, + {0x0740, 0xf1, 0}, + {0x0741, 0xf3, 0}, + {0x0742, 0xff, 0}, + {0x0743, 0x0f, 0}, + {0x0744, 0x1a, 0}, + {0x0745, 0x16, 0}, + {0x0746, 0x00, 0}, + {0x0747, 0xe3, 0}, + {0x0748, 0xce, 0}, + {0x0749, 0xd4, 0}, + {0x074a, 0x00, 0}, + {0x074b, 0x4b, 0}, + {0x074c, 0x00, 0}, + {0x074d, 0xa2, 0}, + {0x074e, 0x00, 0}, + {0x074f, 0xe6, 0}, + {0x0750, 0x00, 0}, + {0x0751, 0x00, 0}, + {0x0752, 0x01, 0}, + {0x0753, 0x03, 0}, + {0x0400, 0x00, 0}, + {0x0408, 0x04, 0}, + {0x040e, 0xe0, 0}, + {0x0500, 0x02, 0}, + {0x05e7, 0x00, 0}, + {0x05e8, 0x00, 0}, + {0x0f09, 0x18, 0}, + {0x070c, 0x20, 0}, + {0x070d, 0x41, 0}, /* 0x49 */ + {0x070e, 0x04, 0}, /* 0x37 */ + {0x070f, 0x00, 0}, + {0x0710, 0x00, 0}, + {0x0711, 0x00, 0}, + {0x0716, 0xf0, 0}, + {0x090f, 0x00, 0}, + {0x0900, 0x01, 1}, + {0x0900, 0x00, 0}, + {0x0001, 0xf5, 0}, + {0x0001, 0xf5, 1}, + {0x0001, 0xf5, 1}, + {0x0001, 0xf5, 1}, + {0x0001, 0xf5, 1}, + {0x0001, 0x05, 0}, + {0x0001, 0x05, 1}, + {0x0000, 0x00, 1} +}; + +/* 256qam */ +static struct atsc_cfg list_qam256[113] = { + {0x0900, 0x01, 0}, + {0x0f04, 0x08, 0}, + {0x0f06, 0x80, 0}, + {0x0f00, 0xe0, 0}, + {0x0f00, 0xec, 0}, + {0x0001, 0x05, 0}, + {0x0002, 0x01, 0}, /* 0x09 */ + {0x0003, 0x2c, 0}, + {0x0004, 0x91, 0}, + {0x0005, 0x10, 0}, + {0x0006, 0xc0, 0}, + {0x0007, 0x5c, 0}, + {0x0008, 0x0f, 0}, + {0x0009, 0x4f, 0}, + {0x000a, 0xfc, 0}, + {0x000b, 0x0c, 0}, + {0x000c, 0x6c, 0}, + {0x000d, 0x3a, 0}, + {0x000e, 0x10, 0}, + {0x000f, 0x02, 0}, + {0x0011, 0x80, 0}, + {0x0012, 0xf5, 0}, /* a5 */ + {0x0013, 0x74, 0}, + {0x0014, 0xb9, 0}, + {0x0015, 0x1f, 0}, + {0x0016, 0x80, 0}, + {0x0017, 0x1f, 0}, + {0x0018, 0x0f, 0}, + {0x001e, 0x00, 0}, + {0x001f, 0x00, 0}, + {0x0023, 0x03, 0}, + {0x0025, 0x20, 0}, + {0x0026, 0xff, 0}, + {0x0027, 0xff, 0}, + {0x0028, 0xf8, 0}, + {0x0200, 0x20, 0}, + {0x0201, 0x62, 0}, + {0x0202, 0x23, 0}, + {0x0204, 0x19, 0}, + {0x0205, 0x76, 0}, + {0x0206, 0xd2, 0}, + {0x0207, 0xff, 0}, + {0x0208, 0xc0, 0}, + {0x0209, 0xff, 0}, + {0x0211, 0xc0, 0}, + {0x0212, 0xb0, 0}, + {0x0213, 0x05, 0}, + {0x0215, 0x08, 0}, + {0x0222, 0xf0, 0}, + {0x0223, 0xff, 0}, + {0x0226, 0x40, 0}, + {0x0229, 0x23, 0}, + {0x022a, 0x02, 0}, + {0x022c, 0x01, 0}, + {0x022e, 0x01, 0}, + {0x022f, 0x05, 0}, + {0x0230, 0x40, 0}, + {0x0231, 0x01, 0}, + {0x0400, 0x02, 0}, + {0x0401, 0x30, 0}, + {0x0402, 0x13, 0}, + {0x0406, 0x06, 0}, + {0x0408, 0x04, 0}, + {0x040e, 0xe0, 0}, + {0x0411, 0x02, 0}, + {0x073a, 0x02, 0}, + {0x073b, 0x09, 0}, + {0x073c, 0x0c, 0}, + {0x073d, 0x08, 0}, + {0x073e, 0xfd, 0}, + {0x073f, 0xf2, 0}, + {0x0740, 0xed, 0}, + {0x0741, 0xf4, 0}, + {0x0742, 0x03, 0}, + {0x0743, 0x15, 0}, + {0x0744, 0x1d, 0}, + {0x0745, 0x15, 0}, + {0x0746, 0xfc, 0}, + {0x0747, 0xde, 0}, + {0x0748, 0xcc, 0}, + {0x0749, 0xd6, 0}, + {0x074a, 0x04, 0}, + {0x074b, 0x4f, 0}, + {0x074c, 0x00, 0}, + {0x074d, 0xa2, 0}, + {0x074e, 0x00, 0}, + {0x074f, 0xe3, 0}, + {0x0750, 0x00, 0}, + {0x0751, 0xfc, 0}, + {0x0752, 0x00, 0}, + {0x0753, 0x03, 0}, + {0x0500, 0x02, 0}, + {0x05e7, 0x00, 0}, + {0x05e8, 0x00, 0}, + {0x0f09, 0x18, 0}, + {0x070c, 0x20, 0}, + {0x070d, 0x49, 0}, + {0x070e, 0x37, 0}, + {0x070f, 0x00, 0}, + {0x0710, 0x00, 0}, + {0x0711, 0x00, 0}, + {0x0716, 0xf0, 0}, + {0x090f, 0x00, 0}, + {0x0900, 0x01, 1}, + {0x0900, 0x00, 0}, + {0x0001, 0xf5, 0}, + {0x0001, 0xf5, 1}, + {0x0001, 0xf5, 1}, + {0x0001, 0xf5, 1}, + {0x0001, 0xf5, 1}, + {0x0001, 0x05, 0}, + {0x0001, 0x05, 1}, + {0x0000, 0x00, 1} +}; + +void dtvpll_lock_init(void) +{ + mutex_init(&dtvpll_init_lock); +} + +void dtvpll_init_flag(int on) +{ + mutex_lock(&dtvpll_init_lock); + dtvpll_init = on; + mutex_unlock(&dtvpll_init_lock); + pr_err("%s %d\n", __func__, on); +} + +int get_dtvpll_init_flag(void) +{ + int val; + + mutex_lock(&dtvpll_init_lock); + val = dtvpll_init; + mutex_unlock(&dtvpll_init_lock); + if (!val) + pr_err("%s: %d\n", __func__, val); + return val; +} + +void adc_dpll_setup(int clk_a, int clk_b, int clk_sys) +{ + int unit, found, ena, enb, div2; + int pll_m, pll_n, pll_od_a, pll_od_b, pll_xd_a, pll_xd_b; + long freq_osc, freq_dco, freq_b, freq_a, freq_sys; + long freq_b_act, freq_a_act, freq_sys_act, err_tmp, best_err; + union adc_pll_cntl adc_pll_cntl; + union adc_pll_cntl2 adc_pll_cntl2; + union adc_pll_cntl3 adc_pll_cntl3; + union adc_pll_cntl4 adc_pll_cntl4; + union demod_dig_clk dig_clk_cfg; + + adc_pll_cntl.d32 = 0; + adc_pll_cntl2.d32 = 0; + adc_pll_cntl3.d32 = 0; + adc_pll_cntl4.d32 = 0; + + pr_dbg("target clk_a %d clk_b %d\n", clk_a, clk_b); + + unit = 10000; /* 10000 as 1 MHz, 0.1 kHz resolution. */ + freq_osc = 24 * unit; + + if (clk_a < 1000) + freq_a = clk_a * unit; + else + freq_a = clk_a * (unit / 1000); + + if (clk_b < 1000) + freq_b = clk_b * unit; + else + freq_b = clk_b * (unit / 1000); + + ena = clk_a > 0 ? 1 : 0; + enb = clk_b > 0 ? 1 : 0; + + if (ena || enb) + adc_pll_cntl3.b.enable = 1; + adc_pll_cntl3.b.reset = 1; + + found = 0; + best_err = 100 * unit; + pll_od_a = 1; + pll_od_b = 1; + pll_n = 1; + for (pll_m = 1; pll_m < 512; pll_m++) { + /* for (pll_n=1; pll_n<=5; pll_n++) { */ + if (is_meson_txl_cpu()) { + freq_dco = freq_osc * pll_m / pll_n / 2;/*txl add div2*/ + if (freq_dco < 700 * unit || freq_dco > 1000 * unit) + continue; + } else { + freq_dco = freq_osc * pll_m / pll_n; + if (freq_dco < 750 * unit || freq_dco > 1550 * unit) + continue; + } + pll_xd_a = freq_dco / (1 << pll_od_a) / freq_a; + pll_xd_b = freq_dco / (1 << pll_od_b) / freq_b; + + freq_a_act = freq_dco / (1 << pll_od_a) / pll_xd_a; + freq_b_act = freq_dco / (1 << pll_od_b) / pll_xd_b; + + err_tmp = (freq_a_act - freq_a) * ena + (freq_b_act - freq_b) * + enb; + + if (err_tmp >= best_err) + continue; + + adc_pll_cntl.b.pll_m = pll_m; + adc_pll_cntl.b.pll_n = pll_n; + adc_pll_cntl.b.pll_od0 = pll_od_b; + adc_pll_cntl.b.pll_od1 = pll_od_a; + adc_pll_cntl.b.pll_xd0 = pll_xd_b; + adc_pll_cntl.b.pll_xd1 = pll_xd_a; + if (is_meson_txl_cpu()) { + adc_pll_cntl4.b.pll_od3 = 0; + adc_pll_cntl.b.pll_od2 = 0; + } else { + adc_pll_cntl2.b.div2_ctrl = + freq_dco > 1000 * unit ? 1 : 0; + } + found = 1; + best_err = err_tmp; + /* } */ + } + + pll_m = adc_pll_cntl.b.pll_m; + pll_n = adc_pll_cntl.b.pll_n; + pll_od_b = adc_pll_cntl.b.pll_od0; + pll_od_a = adc_pll_cntl.b.pll_od1; + pll_xd_b = adc_pll_cntl.b.pll_xd0; + pll_xd_a = adc_pll_cntl.b.pll_xd1; + + if (is_meson_txl_cpu()) + div2 = 1; + else + div2 = adc_pll_cntl2.b.div2_ctrl; + /* + * p_adc_pll_cntl = adc_pll_cntl.d32; + * p_adc_pll_cntl2 = adc_pll_cntl2.d32; + * p_adc_pll_cntl3 = adc_pll_cntl3.d32; + * p_adc_pll_cntl4 = adc_pll_cntl4.d32; + */ + adc_pll_cntl3.b.reset = 0; + /* *p_adc_pll_cntl3 = adc_pll_cntl3.d32; */ + if (!found) { + pr_dbg(" ERROR can't setup %7ld kHz %7ld kHz\n", + freq_b / (unit / 1000), freq_a / (unit / 1000)); + } else { + if (is_meson_txl_cpu()) + freq_dco = freq_osc * pll_m / pll_n / 2; + else + freq_dco = freq_osc * pll_m / pll_n; + pr_dbg(" ADC PLL M %3d N %3d\n", pll_m, pll_n); + pr_dbg(" ADC PLL DCO %ld kHz\n", freq_dco / (unit / 1000)); + + pr_dbg(" ADC PLL XD %3d OD %3d\n", pll_xd_b, pll_od_b); + pr_dbg(" ADC PLL XD %3d OD %3d\n", pll_xd_a, pll_od_a); + + freq_a_act = freq_dco / (1 << pll_od_a) / pll_xd_a; + freq_b_act = freq_dco / (1 << pll_od_b) / pll_xd_b; + + pr_dbg(" B %7ld kHz %7ld kHz\n", + freq_b / (unit / 1000), freq_b_act / (unit / 1000)); + pr_dbg(" A %7ld kHz %7ld kHz\n", + freq_a / (unit / 1000), freq_a_act / (unit / 1000)); + + if (clk_sys > 0) { + dig_clk_cfg.b.demod_clk_en = 1; + dig_clk_cfg.b.demod_clk_sel = 3; + if (clk_sys < 1000) + freq_sys = clk_sys * unit; + else + freq_sys = clk_sys * (unit / 1000); + + dig_clk_cfg.b.demod_clk_div = freq_dco / (1 + div2) / + freq_sys - 1; + freq_sys_act = freq_dco / (1 + div2) / + (dig_clk_cfg.b.demod_clk_div + 1); + pr_dbg(" SYS %7ld kHz div %d+1 %7ld kHz\n", + freq_sys / (unit / 1000), + dig_clk_cfg.b.demod_clk_div, + freq_sys_act / (unit / 1000)); + } else { + dig_clk_cfg.b.demod_clk_en = 0; + } + + /* *p_demod_dig_clk = dig_clk_cfg.d32; */ + } + if (is_meson_txl_cpu()) { + demod_set_demod_reg(TXLTV_ADC_RESET_VALUE, ADC_REG3); + demod_set_demod_reg(adc_pll_cntl.d32, ADC_REG1); + demod_set_demod_reg(dig_clk_cfg.d32, ADC_REG6); + demod_set_demod_reg(TXLTV_ADC_REG3_VALUE, ADC_REG3); + /* debug */ + pr_dbg("[adc][%x]%x\n", ADC_REG1, + demod_read_demod_reg(ADC_REG1)); + pr_dbg("[adc][%x]%x\n", ADC_REG2, + demod_read_demod_reg(ADC_REG2)); + pr_dbg("[adc][%x]%x\n", ADC_REG3, + demod_read_demod_reg(ADC_REG3)); + pr_dbg("[adc][%x]%x\n", ADC_REG4, + demod_read_demod_reg(ADC_REG4)); + pr_dbg("[adc][%x]%x\n", ADC_REG5, + demod_read_demod_reg(ADC_REG5)); + pr_dbg("[adc][%x]%x\n", ADC_REG6, + demod_read_demod_reg(ADC_REG6)); + pr_dbg("[adc][%x]%x\n", ADC_REG7, + demod_read_demod_reg(ADC_REG7)); + pr_dbg("[adc][%x]%x\n", ADC_REG8, + demod_read_demod_reg(ADC_REG8)); + pr_dbg("[adc][%x]%x\n", ADC_REG9, + demod_read_demod_reg(ADC_REG9)); + pr_dbg("[adc][%x]%x\n", ADC_REGB, + demod_read_demod_reg(ADC_REGB)); + pr_dbg("[adc][%x]%x\n", ADC_REGC, + demod_read_demod_reg(ADC_REGC)); + pr_dbg("[adc][%x]%x\n", ADC_REGD, + demod_read_demod_reg(ADC_REGD)); + pr_dbg("[adc][%x]%x\n", ADC_REGE, + demod_read_demod_reg(ADC_REGE)); + pr_dbg("[demod][%x]%x\n", DEMOD_REG1, + demod_read_demod_reg(DEMOD_REG1)); + pr_dbg("[demod][%x]%x\n", DEMOD_REG2, + demod_read_demod_reg(DEMOD_REG2)); + pr_dbg("[demod][%x]%x\n", DEMOD_REG3, + demod_read_demod_reg(DEMOD_REG3)); + } else { + demod_set_demod_reg(ADC_RESET_VALUE, ADC_REG3); /* adc reset */ + demod_set_demod_reg(adc_pll_cntl.d32, ADC_REG1); + demod_set_demod_reg(dig_clk_cfg.d32, ADC_REG6); + demod_set_demod_reg(ADC_REG3_VALUE, ADC_REG3); + /* debug */ + pr_dbg("[adc][%x]%x\n", ADC_REG1, + demod_read_demod_reg(ADC_REG1)); + pr_dbg("[adc][%x]%x\n", ADC_REG2, + demod_read_demod_reg(ADC_REG2)); + pr_dbg("[adc][%x]%x\n", ADC_REG3, + demod_read_demod_reg(ADC_REG3)); + pr_dbg("[adc][%x]%x\n", ADC_REG4, + demod_read_demod_reg(ADC_REG4)); + pr_dbg("[adc][%x]%x\n", ADC_REG6, + demod_read_demod_reg(ADC_REG6)); + pr_dbg("[demod][%x]%x\n", DEMOD_REG1, + demod_read_demod_reg(DEMOD_REG1)); + pr_dbg("[demod][%x]%x\n", DEMOD_REG2, + demod_read_demod_reg(DEMOD_REG2)); + pr_dbg("[demod][%x]%x\n", DEMOD_REG3, + demod_read_demod_reg(DEMOD_REG3)); + } + dtvpll_init_flag(1); +} + +void demod_set_adc_core_clk(int adc_clk, int sys_clk, int dvb_mode) +{ + adc_dpll_setup(25, adc_clk, sys_clk); +} + +void demod_set_cbus_reg(unsigned int data, unsigned int addr) +{ + void __iomem *vaddr; + + pr_dbg("[cbus][write]%x\n", (IO_CBUS_PHY_BASE + (addr << 2))); + vaddr = ioremap((IO_CBUS_PHY_BASE + (addr << 2)), 0x4); + writel(data, vaddr); + iounmap(vaddr); +} + +unsigned int demod_read_cbus_reg(unsigned int addr) +{ +/* return __raw_readl(CBUS_REG_ADDR(addr)); */ + unsigned int tmp; + void __iomem *vaddr; + + vaddr = ioremap((IO_CBUS_PHY_BASE + (addr << 2)), 0x4); + tmp = readl(vaddr); + iounmap(vaddr); +/* tmp = aml_read_cbus(addr); */ + pr_dbg("[cbus][read]%x,data is %x\n", + (IO_CBUS_PHY_BASE + (addr << 2)), tmp); + return tmp; +} + +void demod_set_ao_reg(unsigned int data, unsigned int addr) +{ + void __iomem *vaddr; + +/* pr_dbg("[ao][write]%x,data is %x\n",(IO_AOBUS_BASE+addr),data); */ + vaddr = ioremap((IO_AOBUS_BASE + addr), 0x4); + writel(data, vaddr); + iounmap(vaddr); +} + +unsigned int demod_read_ao_reg(unsigned int addr) +{ + unsigned int tmp; + void __iomem *vaddr; + +/* pr_dbg("[ao][read]%x\n",(IO_AOBUS_BASE+addr)); */ + vaddr = ioremap((IO_AOBUS_BASE + addr), 0x4); + tmp = readl(vaddr); +/* pr_dbg("[ao][read]%x,data is %x\n",(IO_AOBUS_BASE+addr),tmp); */ + iounmap(vaddr); + return tmp; +} + +void demod_set_demod_reg(unsigned int data, unsigned int addr) +{ + void __iomem *vaddr; + + mutex_lock(&mp); +/* printk("[demod][write]%x,data is %x\n",(addr),data); */ + vaddr = ioremap((addr), 0x4); + writel(data, vaddr); + iounmap(vaddr); + mutex_unlock(&mp); +} + +unsigned int demod_read_demod_reg(unsigned int addr) +{ + unsigned int tmp; + void __iomem *vaddr; + + mutex_lock(&mp); + vaddr = ioremap((addr), 0x4); + tmp = readl(vaddr); + iounmap(vaddr); + mutex_unlock(&mp); +/* printk("[demod][read]%x,data is %x\n",(addr),tmp); */ + return tmp; +} + +void demod_power_switch(int pwr_cntl) +{ + int reg_data; +#if 1 + if (pwr_cntl == PWR_ON) { + pr_dbg("[PWR]: Power on demod_comp %x,%x\n", + AO_RTI_GEN_PWR_SLEEP0, AO_RTI_GEN_PWR_ISO0); + /* Powerup demod_comb */ + reg_data = demod_read_ao_reg(AO_RTI_GEN_PWR_SLEEP0); + demod_set_ao_reg((reg_data & (~(0x1 << 10))), + AO_RTI_GEN_PWR_SLEEP0); + /* [10] power on */ + pr_dbg("[PWR]: Power on demod_comp %x,%x\n", + HHI_DEMOD_MEM_PD_REG, RESET0_LEVEL); + /* Power up memory */ + demod_set_demod_reg((demod_read_demod_reg(HHI_DEMOD_MEM_PD_REG) + & (~0x2fff)), HHI_DEMOD_MEM_PD_REG); + /* reset */ + demod_set_demod_reg((demod_read_demod_reg(RESET0_LEVEL) & + (~(0x1 << 8))), RESET0_LEVEL); + /* msleep(20);*/ + + /* remove isolation */ + demod_set_ao_reg( + (demod_read_ao_reg(AO_RTI_GEN_PWR_ISO0) & + (~(0x3 << 14))), AO_RTI_GEN_PWR_ISO0); + /* pull up reset */ + demod_set_demod_reg((demod_read_demod_reg(RESET0_LEVEL) | + (0x1 << 8)), RESET0_LEVEL); +/* *P_RESET0_LEVEL |= (0x1<<8); */ + } else { + pr_dbg("[PWR]: Power off demod_comp\n"); + /* add isolation */ + + demod_set_ao_reg( + (demod_read_ao_reg(AO_RTI_GEN_PWR_ISO0) | + (0x3 << 14)), AO_RTI_GEN_PWR_ISO0); + + /* power down memory */ + demod_set_demod_reg((demod_read_demod_reg(HHI_DEMOD_MEM_PD_REG) + | 0x2fff), HHI_DEMOD_MEM_PD_REG); + /* power down demod_comb */ + reg_data = demod_read_ao_reg(AO_RTI_GEN_PWR_SLEEP0); + demod_set_ao_reg((reg_data | (0x1 << 10)), + AO_RTI_GEN_PWR_SLEEP0); + /* [10] power on */ + } +#endif +} + +static void clocks_set_sys_defaults(unsigned char dvb_mode) +{ + union demod_cfg0 cfg0; + union demod_cfg2 cfg2; + + demod_power_switch(PWR_ON); + + if (is_meson_gxtvbb_cpu()) { + pr_dbg("GX_TV config\n"); + demod_set_demod_reg(ADC_RESET_VALUE, ADC_REG3); + demod_set_demod_reg(ADC_REG1_VALUE, ADC_REG1); + demod_set_demod_reg(ADC_REG2_VALUE, ADC_REG2); + demod_set_demod_reg(ADC_REG4_VALUE, ADC_REG4); + demod_set_demod_reg(ADC_REG3_VALUE, ADC_REG3); + /* dadc */ + demod_set_demod_reg(ADC_REG7_VALUE, ADC_REG7); + demod_set_demod_reg(ADC_REG8_VALUE, ADC_REG8); + demod_set_demod_reg(ADC_REG9_VALUE, ADC_REG9); + demod_set_demod_reg(ADC_REGA_VALUE, ADC_REGA); + } else if (is_meson_txl_cpu()) { + pr_dbg("TXL_TV config\n"); + demod_set_demod_reg(TXLTV_ADC_REG3_VALUE, ADC_REG3); + demod_set_demod_reg(TXLTV_ADC_REG1_VALUE, ADC_REG1); + demod_set_demod_reg(TXLTV_ADC_REGB_VALUE, ADC_REGB); + demod_set_demod_reg(TXLTV_ADC_REG2_VALUE, ADC_REG2); + demod_set_demod_reg(TXLTV_ADC_REG3_VALUE, ADC_REG3); + demod_set_demod_reg(TXLTV_ADC_REG4_VALUE, ADC_REG4); + demod_set_demod_reg(TXLTV_ADC_REGC_VALUE, ADC_REGC); + demod_set_demod_reg(TXLTV_ADC_REGD_VALUE, ADC_REGD); + demod_set_demod_reg(TXLTV_ADC_RESET_VALUE, ADC_REG3); + demod_set_demod_reg(TXLTV_ADC_REG3_VALUE, ADC_REG3); + + /* dadc */ + demod_set_demod_reg(TXLTV_ADC_REG7_VALUE, ADC_REG7); + demod_set_demod_reg(TXLTV_ADC_REG8_VALUE, ADC_REG8); + demod_set_demod_reg(TXLTV_ADC_REG9_VALUE, ADC_REG9); + demod_set_demod_reg(TXLTV_ADC_REGE_VALUE, ADC_REGE); + } + + demod_set_demod_reg(DEMOD_REG1_VALUE, DEMOD_REG1); + demod_set_demod_reg(DEMOD_REG2_VALUE, DEMOD_REG2); + demod_set_demod_reg(DEMOD_REG3_VALUE, DEMOD_REG3); + cfg0.b.mode = 7; + cfg0.b.adc_format = 1; + if (dvb_mode == Gxtv_Dvbc) { /* // 0 -DVBC, 1-DVBT, ISDBT, 2-ATSC */ + cfg0.b.ts_sel = 2; + } else if ((dvb_mode == Gxtv_Dvbt_Isdbt) || (dvb_mode == Gxtv_Dtmb)) { + cfg0.b.ts_sel = 1; + cfg0.b.adc_regout = 1; + } else if (dvb_mode == Gxtv_Atsc) { + cfg0.b.ts_sel = 4; + } + demod_set_demod_reg(cfg0.d32, DEMOD_REG1); + cfg2.b.biasgen_en = 1; + cfg2.b.en_adc = 1; + demod_set_demod_reg(cfg2.d32, DEMOD_REG3); + pr_dbg("0xc8020c00 is %x,dvb_mode is %d\n", + demod_read_demod_reg(DEMOD_REG1), dvb_mode); +} + +void dtmb_write_reg(int reg_addr, int reg_data) +{ + if (!get_dtvpll_init_flag()) + return; + demod_set_demod_reg(reg_data, reg_addr); +/* apb_write_reg(reg_addr,reg_data); */ +} + +int dtmb_read_reg(int reg_addr) +{ + if (!get_dtvpll_init_flag()) + return 0; + return demod_read_demod_reg(reg_addr); /* apb_read_reg(reg_addr); */ +} + +void atsc_write_reg(int reg_addr, int reg_data) +{ + if (!get_dtvpll_init_flag()) + return; + apb_write_reg(ATSC_BASE, (reg_addr & 0xffff) << 8 | (reg_data & 0xff)); +} + +unsigned long atsc_read_reg(int reg_addr) +{ + unsigned long tmp; + + if (!get_dtvpll_init_flag()) + return 0; + apb_write_reg(ATSC_BASE + 4, (reg_addr & 0xffff) << 8); + tmp = apb_read_reg(ATSC_BASE); + + return tmp & 0xff; +} + +unsigned long atsc_read_iqr_reg(void) +{ + unsigned long tmp; + + tmp = apb_read_reg(ATSC_BASE + 8); + pr_dbg("[atsc irq] is %lx\n", tmp); + return tmp & 0xffffffff; +} + +int atsc_qam_set(fe_modulation_t mode) +{ + int i, j; + + if (mode == VSB_8) { /* 5-8vsb, 2-64qam, 4-256qam */ + for (i = 0; list_8vsb[i].adr != 0; i++) { + if (list_8vsb[i].rw) + atsc_read_reg(list_8vsb[i].adr); + /* msleep(20); */ + else + atsc_write_reg(list_8vsb[i].adr, + list_8vsb[i].dat); + /* msleep(20); */ + } + j = 15589; + pr_dbg("8-vsb mode\n"); + } else if (mode == QAM_64) { + for (i = 0; list_qam64[i].adr != 0; i++) { + if (list_qam64[i].rw) { + atsc_read_reg(list_qam64[i].adr); + msleep(20); + } else { + atsc_write_reg(list_qam64[i].adr, + list_qam64[i].dat); + msleep(20); + } + } + j = 16588; /* 33177; */ + pr_dbg("64qam mode\n"); + } else if (mode == QAM_256) { + for (i = 0; list_qam256[i].adr != 0; i++) { + if (list_qam256[i].rw) { + atsc_read_reg(list_qam256[i].adr); + msleep(20); + } else { + atsc_write_reg(list_qam256[i].adr, + list_qam256[i].dat); + msleep(20); + } + } + j = 15649; /* 31298; */ + pr_dbg("256qam mode\n"); + } else { + for (i = 0; list_qam256[i].adr != 0; i++) { + if (list_qam256[i].rw) { + atsc_read_reg(list_qam256[i].adr); + msleep(20); + } else { + atsc_write_reg(list_qam256[i].adr, + list_qam256[i].dat); + msleep(20); + } + } + j = 15649; /* 31298; */ + pr_dbg("256qam mode\n"); + } + return j; +} + +void atsc_initial(struct aml_demod_sta *demod_sta) +{ + int fc, fs, cr, ck, j; + fe_modulation_t mode; + + mode = demod_sta->ch_mode; + + j = atsc_qam_set(mode); /* set mode */ + + fs = demod_sta->adc_freq; /* KHZ 25200 */ + fc = demod_sta->ch_if; /* KHZ 6350 */ + + cr = (fc * (1 << 17) / fs) * (1 << 6); + ck = fs * j / 10 - (1 << 25); + /* ck_rate = (f_samp / f_vsb /2 -1)*(1<<25); + *double f_vsb = 10.76238;// double f_64q = 5.056941; + * // double f_256q = 5.360537; + */ + + atsc_write_reg(0x070e, cr & 0xff); + atsc_write_reg(0x070d, (cr >> 8) & 0xff); + atsc_write_reg(0x070c, (cr >> 16) & 0xff); + + if (demod_sta->ch_mode == VSB_8) { + atsc_write_reg(0x0711, ck & 0xff); + atsc_write_reg(0x0710, (ck >> 8) & 0xff); + atsc_write_reg(0x070f, (ck >> 16) & 0xff); + } + pr_dbg("0x70e is %x, 0x70d is %x, 0x70c is %x\n", cr & 0xff, + (cr >> 8) & 0xff, (cr >> 16) & 0xff); + pr_dbg("fs is %d(SR),fc is %d(IF),cr is %x,ck is %x\n", fs, fc, cr, ck); +} + +int atsc_set_ch(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c, + struct aml_demod_atsc *demod_atsc) +{ + int ret = 0; + u8 demod_mode; + u8 bw, sr, ifreq, agc_mode; + u32 ch_freq; + + bw = demod_atsc->bw; + sr = demod_atsc->sr; + ifreq = demod_atsc->ifreq; + agc_mode = demod_atsc->agc_mode; + ch_freq = demod_atsc->ch_freq; + demod_mode = demod_atsc->dat0; + demod_sta->ch_mode = demod_atsc->mode; /* TODO */ + demod_sta->agc_mode = agc_mode; + demod_sta->ch_freq = ch_freq; + demod_sta->dvb_mode = demod_mode; + demod_sta->ch_bw = (8 - bw) * 1000; + atsc_initial(demod_sta); + pr_dbg("ATSC mode\n"); + return ret; +} + +#if 0 +static dtmb_cfg_t list_dtmb_v1[99] = { + {0x00000000, 0x01, 0}, + {0x00001000, 0x02, 0}, + {0x00000000, 0x03, 0}, + {0x00000000, 0x04, 0}, + {0x00000000, 0x05, 0}, + {0x00000000, 0x06, 0}, + {0x007fffff, 0x07, 0}, + {0x0000000f, 0x08, 0}, + {0x00003000, 0x09, 0}, + {0x00000001, 0x0a, 0}, + {0x0c403006, 0x0b, 0}, + {0x44444400, 0x0c, 0}, + {0x1412c320, 0x0d, 0}, + {0x00000152, 0x10, 0}, + {0x47080137, 0x11, 0}, + {0x02200a16, 0x12, 0}, + {0x42190190, 0x13, 0}, + {0x7f807f80, 0x14, 0}, + {0x0000199a, 0x15, 0}, + {0x000a1466, 0x18, 0}, + {0x00274217, 0x1a, 0}, + {0x00131036, 0x1b, 1}, + {0x00000396, 0x1c, 0}, + {0x0037f3cc, 0x1d, 0}, + {0x00000029, 0x1e, 0}, + {0x0004f031, 0x1f, 0}, + {0x00f3cbd4, 0x20, 0}, + {0x0000007e, 0x21, 0}, + {0x23270b6a, 0x22, 0}, + {0x5f700c1b, 0x23, 0}, + {0x00133c2b, 0x24, 0}, + {0x2d3e0f12, 0x25, 0}, + {0x06363038, 0x26, 0}, + {0x060e0a3e, 0x27, 0}, + {0x0015161f, 0x28, 0}, + {0x0809031b, 0x29, 0}, + {0x181c0307, 0x2a, 0}, + {0x051f1a1b, 0x2b, 0}, + {0x00451dce, 0x2c, 0}, + {0x242fde12, 0x2d, 0}, + {0x0034e8fa, 0x2e, 0}, + {0x00000007, 0x30, 0}, + {0x16000d0c, 0x31, 0}, + {0x0000011f, 0x32, 0}, + {0x01000200, 0x33, 0}, + {0x10bbf376, 0x34, 0}, + {0x00000044, 0x35, 0}, + {0x00000000, 0x36, 0}, + {0x00000000, 0x37, 0}, + {0x00000000, 0x38, 0}, + {0x00000000, 0x39, 0}, + {0x00000031, 0x3a, 0}, + {0x4d6b0a58, 0x3b, 0}, + {0x00000c04, 0x3c, 0}, + {0x0d3b0a50, 0x3d, 0}, + {0x03140480, 0x3e, 0}, + {0x05e60452, 0x3f, 0}, + {0x05780400, 0x40, 0}, + {0x0063c025, 0x41, 0}, + {0x05050202, 0x42, 0}, + {0x5e4a0a14, 0x43, 0}, + {0x00003b42, 0x44, 0}, + {0xa53080ff, 0x45, 0}, + {0x00000000, 0x46, 0}, + {0x00133202, 0x47, 0}, + {0x01f00000, 0x48, 0}, + {0x00000000, 0x49, 0}, + {0x00000000, 0x4a, 0}, + {0x00000000, 0x4b, 0}, + {0x00000000, 0x4c, 0}, + {0x20405dc8, 0x4d, 0}, + {0x00000000, 0x4e, 0}, + {0x1f0205df, 0x4f, 0}, + {0x00001120, 0x50, 0}, + {0x4f190803, 0x51, 0}, + {0x00000000, 0x52, 0}, + {0x00000040, 0x53, 0}, + {0x00100050, 0x54, 0}, + {0x00cd1000, 0x55, 0}, + {0x00010fab, 0x56, 0}, + {0x03f0fc3f, 0x58, 0}, + {0x02005014, 0x59, 0}, + {0x01405014, 0x5a, 0}, + {0x00014284, 0x5b, 0}, + {0x00000320, 0x5c, 0}, + {0x14130e05, 0x5d, 0}, + {0x4321c963, 0x5f, 0}, + {0x624668f8, 0x60, 0}, + {0xccc08888, 0x61, 0}, + {0x13212111, 0x62, 0}, + {0x21100000, 0x63, 0}, + {0x624668f8, 0x64, 0}, + {0xccc08888, 0x65, 0}, + {0x13212111, 0x66, 0}, + {0x21100000, 0x67, 0}, + {0x624668f8, 0x68, 0}, + {0xccc08888, 0x69, 0}, + {0x0, 0x0, 0} +}; +#endif + +void dtmb_all_reset(void) +{ + int temp_data = 0; + + if (is_meson_txl_cpu()) { + dtmb_write_reg(DTMB_FRONT_AFIFO_ADC, 0x1f); + /*modified bu xiaotong*/ + dtmb_write_reg(DTMB_CHE_TPS_CONFIG, 0xc00000); + dtmb_write_reg(DTMB_CHE_EQ_CONFIG, 0x1a027719); + dtmb_write_reg(DTMB_FRONT_AGC_CONFIG1, 0x101a7); + dtmb_write_reg(DTMB_FRONT_47_CONFIG, 0x131a31); + /*detect 64qam 420 595 problems*/ + dtmb_write_reg(DTMB_FRONT_19_CONFIG, 0x300); + dtmb_write_reg(DTMB_FRONT_4d_CONFIG, 0x12ffbe0); + /*fix fsm b bug*/ + dtmb_write_reg(DTMB_FRONT_DEBUG_CFG, 0x5680000); + /*fix agc problem,skip warm_up status*/ + dtmb_write_reg(DTMB_FRONT_46_CONFIG, 0x1a000f0f); + dtmb_write_reg(DTMB_FRONT_ST_FREQ, 0xf2400000); + } else { + dtmb_write_reg(DTMB_FRONT_AGC_CONFIG1, 0x10127); + dtmb_write_reg(DTMB_CHE_IBDFE_CONFIG6, 0x943228cc); + dtmb_write_reg(DTMB_CHE_IBDFE_CONFIG7, 0xc09aa8cd); + dtmb_write_reg(DTMB_CHE_FD_TD_COEFF, 0x0); + dtmb_write_reg(DTMB_CHE_EQ_CONFIG, 0x9dc59); + /*0x2 is auto,0x406 is invert spectrum*/ + if (dtmb_spectrum == 0) + dtmb_write_reg(DTMB_TOP_CTRL_TPS, 0x406); + else if (dtmb_spectrum == 1) + dtmb_write_reg(DTMB_TOP_CTRL_TPS, 0x402); + else + dtmb_write_reg(DTMB_TOP_CTRL_TPS, 0x2); + + pr_dbg("dtmb_spectrum is %d\n", dtmb_spectrum); + dtmb_write_reg(DTMB_TOP_CTRL_FEC, 0x41444400); + dtmb_write_reg(DTMB_TOP_CTRL_INTLV_TIME, 0x180300); + dtmb_write_reg(DTMB_FRONT_DDC_BYPASS, 0x662ca0); + dtmb_write_reg(DTMB_FRONT_AFIFO_ADC, 0x29); + dtmb_write_reg(DTMB_FRONT_DC_HOLD, 0xa1066); + /*cci para*/ + dtmb_write_reg(DTMB_CHE_M_CCI_THR_CONFIG3, 0x80201f6); + dtmb_write_reg(DTMB_CHE_M_CCI_THR_CONFIG2, 0x3f20080); + dtmb_write_reg(DTMB_CHE_TPS_CONFIG, 0xc00000); + dtmb_write_reg(DTMB_TOP_CTRL_AGC, 0x3); + dtmb_write_reg(DTMB_TOP_CTRL_TS_SFO_CFO, 0x20403006); + dtmb_write_reg(DTMB_FRONT_AGC_CONFIG2, 0x7200a16); + dtmb_write_reg(DTMB_FRONT_DEBUG_CFG, 0x1e00000); + dtmb_write_reg(DTMB_TOP_CTRL_ENABLE, 0x7fffff); + /*close ts3 timing loop*/ + dtmb_write_reg(DTMB_TOP_CTRL_DAGC_CCI, 0x305); + /*dektec card issue,close f case snr drop*/ + dtmb_write_reg(DTMB_CHE_MC_SC_TIMING_POWTHR, 0xc06100a); + if (demod_enable_performance) { + dtmb_write_reg(DTMB_CHE_IBDFE_CONFIG1, 0x4040002); + temp_data = dtmb_read_reg(DTMB_CHE_FD_TD_COEFF); + temp_data = (temp_data & ~0x3fff)|(0x241f & 0x3fff); + temp_data = temp_data | (1<<21); + /*Set freeze_mode and reset coeff*/ + dtmb_write_reg(DTMB_CHE_FD_TD_COEFF, temp_data); + temp_data = temp_data & ~(1<<21); + /*Set freeze_mode and reset coeff*/ + dtmb_write_reg(DTMB_CHE_FD_TD_COEFF, temp_data); + } + } +} + +void dtmb_initial(struct aml_demod_sta *demod_sta) +{ +/* dtmb_write_reg(0x049, memstart); //only for init */ + dtmb_spectrum = 1; + dtmb_spectrum = demod_sta->spectrum; + dtmb_register_reset(); + dtmb_all_reset(); +#if 0 + int i; + + for (i = 0; list_dtmb_v1[i].adr != 0; i++) { + if (list_dtmb_v1[i].rw) + apb_read_reg(DTMB_BASE + ((list_dtmb_v1[i].adr) << 2)); + /* msleep(20); */ + else + apb_write_reg(DTMB_BASE + ((list_dtmb_v1[i].adr) << 2), + list_dtmb_v1[i].dat); + /* msleep(20); */ + } +#endif +} + +int check_dtmb_fec_lock(void) +{ + int fec_lock, snr, status; + + fec_lock = (dtmb_read_reg(DTMB_TOP_FEC_LOCK_SNR) >> 14) & 0x1; + snr = dtmb_read_reg(DTMB_TOP_FEC_LOCK_SNR) & 0x3fff; + if (fec_lock && (snr > 4)) + status = 1; + else + status = 0; + return status; +} + +int check_dtmb_mobile_det(void) +{ + int mobile_det = 0; + + mobile_det = (dtmb_read_reg(DTMB_TOP_CTRL_SYS_OFDM_CNT) >> 8) & 0x7ffff; + return mobile_det; + +} + + +int dtmb_information(void) +{ + int tps, snr, fec_lock, fec_bch_add, fec_ldpc_unc_acc, fec_ldpc_it_avg, + tmp, che_snr; + struct aml_fe_dev *dev; + + dev = NULL; + tps = dtmb_read_reg(DTMB_TOP_CTRL_CHE_WORKCNT); + tmp = dtmb_read_reg(DTMB_TOP_FEC_LOCK_SNR); + if (is_meson_txl_cpu()) + che_snr = tmp & 0x3fff; + else + che_snr = tmp & 0xfff; + snr = che_snr; + snr = convert_snr(snr); + /* if (che_snr >= 8192) */ + /* che_snr = che_snr - 16384;*/ + /* snr = che_snr / 32;*/ + /* snr = 10*log10(snr)-6; */ + fec_lock = (dtmb_read_reg(DTMB_TOP_FEC_LOCK_SNR) >> 14) & 0x1; + fec_bch_add = dtmb_read_reg(DTMB_TOP_FEC_BCH_ACC); + fec_ldpc_unc_acc = dtmb_read_reg(DTMB_TOP_FEC_LDPC_UNC_ACC); + fec_ldpc_it_avg = dtmb_read_reg(DTMB_TOP_FEC_LDPC_IT_AVG); + pr_dbg("¡¾FSM ¡¿: %x %x %x %x\n", + dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE0), + dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE1), + dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE2), + dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE3)); + pr_dbg + ("¡¾AGC ¡¿: agc_power %d,agc_if_gain %d,agc_rf_gain %d,", + (-(((dtmb_read_reg(DTMB_TOP_FRONT_AGC) >> 22) & 0x3ff) / 16)), + ((dtmb_read_reg(DTMB_TOP_FRONT_AGC)) & 0x3ff), + ((dtmb_read_reg(DTMB_TOP_FRONT_AGC) >> 11) & 0x7ff)); + pr_dbg + ("dagc_power %3d,dagc_gain %3d mobi_det_power %d\n", + ((dtmb_read_reg(DTMB_TOP_FRONT_DAGC) >> 0) & 0xff), + ((dtmb_read_reg(DTMB_TOP_FRONT_DAGC) >> 8) & 0xfff), + (dtmb_read_reg(DTMB_TOP_CTRL_SYS_OFDM_CNT) >> 8) & 0x7ffff); + pr_dbg + ("¡¾TPS ¡¿ SC or MC %2d,f_r %2d qam_nr %2d ", + (dtmb_read_reg(DTMB_TOP_CHE_OBS_STATE1) >> 1) & 0x1, + (tps >> 22) & 0x1, (tps >> 21) & 0x1); + pr_dbg + ("intlv %2d,cr %2d constl %2d\n", + (tps >> 20) & 0x1, + (tps >> 18) & 0x3, (tps >> 16) & 0x3); + + pr_dbg + ("[dtmb] snr is %d,fec_lock is %d,fec_bch_add is %d,", + snr, fec_lock, fec_bch_add); + pr_dbg + ("fec_ldpc_unc_acc is %d ,fec_ldpc_it_avg is %d\n", + fec_ldpc_unc_acc, + fec_ldpc_it_avg / 256); + pr_dbg + ("------------------------------------------------------------\n"); + + tuner_get_ch_power(dev); + + return 0; +} + +int dtmb_check_cci(void) +{ + int cci_det = 0; + + cci_det = + ((dtmb_read_reg(DTMB_TOP_SYNC_CCI_NF2_POSITION) >> 22) + & 0x3); + if (cci_det > 0) { + pr_dbg("find cci\n"); + dtmb_write_reg(DTMB_CHE_CCIDET_CONFIG, 0x20210290); + dtmb_write_reg(DTMB_CHE_M_CCI_THR_CONFIG3, 0x20081f6); + dtmb_write_reg(DTMB_CHE_M_CCI_THR_CONFIG2, 0x3f08020); + } + return cci_det; +} + +int dtmb_bch_check(void) +{ + int fec_bch_add, i; + + fec_bch_add = dtmb_read_reg(DTMB_TOP_FEC_BCH_ACC); + pr_dbg("[debug]fec lock,fec_bch_add is %d\n", fec_bch_add); + msleep(100); + if (((dtmb_read_reg(DTMB_TOP_FEC_BCH_ACC))-fec_bch_add) >= 50) { + pr_dbg("[debug]fec lock,but bch add ,need reset,wait not to reset\n"); + dtmb_reset(); + for (i = 0; i < 30; i++) { + msleep(100); + if (check_dtmb_fec_lock() == 1) { + pr_dbg("[debug]fec lock,but bch add ,need reset,now is lock\n"); + return 0; + } + } + } + return 0; +} + +int dtmb_constell_check(void) +{ + int constell; + + constell = dtmb_read_reg(DTMB_TOP_CTRL_CHE_WORKCNT)>>16 & 0x3; + if (constell == 0)/*4qam*/ + dtmb_write_reg(DTMB_FRONT_47_CONFIG, 0x133221); + else if (constell == 1)/*16qam*/ + dtmb_write_reg(DTMB_FRONT_47_CONFIG, 0x132821); + else if (constell == 2)/*32qam*/ + dtmb_write_reg(DTMB_FRONT_47_CONFIG, 0x131e21); + else if (constell == 3)/*64qam*/ + dtmb_write_reg(DTMB_FRONT_47_CONFIG, 0x131a31); + + return 0; +} + + +int dtmb_check_fsm(void) +{ + int tmp, fsm_status, i, has_singnal; + + tmp = dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE0); + fsm_status = tmp&0xffffffff; + has_singnal = 0; + pr_dbg("[rsj1] fsm_status is %x\n", fsm_status); + for (i = 0 ; i < 8 ; i++) { + if (((fsm_status >> (i*4)) & 0xf) > 3) { + /*has signal*/ + /* pr_dbg("has signal\n");*/ + has_singnal = 1; + } + } + return has_singnal; + +} + +int patch_ts3(int delay1_us, int delay2_us) +{ + if (((dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE0)&0xf) == 0x7)&1) { + dtmb_write_reg(DTMB_TOP_CTRL_FSM, 0x300f); + dtmb_write_reg(DTMB_TOP_CTRL_FSM, 0x310f); + msleep(delay1_us); + dtmb_write_reg(DTMB_TOP_CTRL_ENABLE, 0xffdfff); + dtmb_write_reg(DTMB_TOP_CTRL_ENABLE, 0xffffff); + dtmb_write_reg(DTMB_TOP_CTRL_FSM, 0x3110); + dtmb_write_reg(DTMB_TOP_CTRL_FSM, 0x3010); + dtmb_write_reg(DTMB_TOP_CTRL_FSM, 0x3000); + return 1; + } else + return 0; +} + + +int read_cfo_all(void) +{ + int icfo_all, fcfo_all; + + icfo_all = dtmb_read_reg(DTMB_TOP_CTRL_ICFO_ALL) & 0xfffff; + fcfo_all = dtmb_read_reg(DTMB_TOP_CTRL_FCFO_ALL) & 0x3fff; + if (icfo_all > (1 << 19)) + icfo_all = icfo_all - (1 << 20); + if (fcfo_all > (1 << 13)) + fcfo_all = fcfo_all - (1 << 14); + + return (int)(icfo_all*4+fcfo_all); + +} + + +int dtmb_v3_soft_sync(int cfo_init) +{ + +/* int cfo_all;*/ +/* int cfo_setting;*/ + + if (cfo_init == 0) { + cfo_init = patch_ts3(11, 0); + #if 0 + if (cfo_init == 1) { + cfo_all = read_cfo_all(); + cfo_setting = dtmb_read_reg(DTMB_FRONT_DDC_BYPASS); + dtmb_write_reg(DTMB_FRONT_DDC_BYPASS, + cfo_setting+cfo_all); + dtmb_write_reg(DTMB_TOP_CTRL_LOOP, 0x3); + dtmb_reset(); + } + #endif + } + return cfo_init; + +} + +int dtmb_check_status_gxtv(struct dvb_frontend *fe) +{ + int local_state; + int time_cnt;/* cci_det, src_config;*/ + int cfo_init, count; + + dtmb_information(); + time_cnt = 0; + local_state = 0; + cfo_init = 0; + if (check_dtmb_fec_lock() != 1) { + dtmb_register_reset(); + dtmb_all_reset(); + count = 15; + while ((count) && + ((dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE0)&0xf) < 0x6)) { + msleep(20); + count--; + } + + count = demod_sync_count; + while ((count) && (cfo_init == 0)) { + + cfo_init = dtmb_v3_soft_sync(cfo_init); + + msleep(demod_sync_delay_time); + count--; + } + if ((cfo_init == 0) && + ((dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE0)&0xf) <= 7)) { + pr_dbg("over 400ms,status is %x, need reset\n", + (dtmb_read_reg(DTMB_TOP_CTRL_FSM_STATE0)&0xf)); + return 0; + } + while ((time_cnt < 10) && (check_dtmb_fec_lock() != 1)) { + msleep(demod_timeout); + time_cnt++; + local_state = AMLOGIC_DTMB_STEP3; + dtmb_information(); + dtmb_check_cci(); + if (time_cnt > 8) + pr_dbg + ("* local_state = %d\n", local_state); + } + if (time_cnt >= 10 && (check_dtmb_fec_lock() != 1)) { + local_state = AMLOGIC_DTMB_STEP4; + time_cnt = 0; + pr_dbg + ("*all reset,timeout is %d\n", demod_timeout); + } + } else { + dtmb_check_cci(); + dtmb_bch_check(); + #if 0 + cci_det = dtmb_check_cci(); + if ((check_dtmb_mobile_det() <= demod_mobile_power) + && (cci_det == 0)) { + /* open */ + src_config = (dtmb_read_reg(DTMB_FRONT_SRC_CONFIG1)); + dtmb_write_reg(DTMB_FRONT_SRC_CONFIG1, + src_config & (~(0x1 << 28))); + } else { + /* close */ + src_config = (dtmb_read_reg(DTMB_FRONT_SRC_CONFIG1)); + dtmb_write_reg(DTMB_FRONT_SRC_CONFIG1, + src_config | (0x1 << 28)); + } + #endif + } + if (check_dtmb_fec_lock() == 1) + dtmb_write_reg(DTMB_TOP_CTRL_LOOP, 0xf); + return 0; +} + + +int dtmb_check_status_txl(struct dvb_frontend *fe) +{ + int time_cnt; + + time_cnt = 0; + dtmb_information(); + if (check_dtmb_fec_lock() != 1) { + while ((time_cnt < 10) && (check_dtmb_fec_lock() != 1)) { + msleep(demod_timeout); + time_cnt++; + dtmb_information(); + if (((dtmb_read_reg(DTMB_TOP_CTRL_CHE_WORKCNT) + >> 21) & 0x1) == 0x1) { + pr_dbg("4qam-nr,need set spectrum\n"); + if (dtmb_spectrum == 1) { + dtmb_write_reg + (DTMB_TOP_CTRL_TPS, 0x1010406); + } else if (dtmb_spectrum == 0) { + dtmb_write_reg + (DTMB_TOP_CTRL_TPS, 0x1010402); + } else { + dtmb_write_reg + (DTMB_TOP_CTRL_TPS, 0x1010002); + } + } + if (time_cnt > 8) + pr_dbg + ("* time_cnt = %d\n", time_cnt); + } + if (time_cnt >= 10 && (check_dtmb_fec_lock() != 1)) { + time_cnt = 0; + dtmb_register_reset(); + dtmb_all_reset(); + if (dtmb_spectrum == 0) + dtmb_spectrum = 1; + else + dtmb_spectrum = 0; + pr_dbg + ("*all reset,timeout is %d\n", demod_timeout); + } + } else { + dtmb_bch_check(); + dtmb_constell_check(); + } + return 0; +} + + +void dtmb_reset(void) +{ + union DTMB_TOP_CTRL_SW_RST_BITS sw_rst; + + sw_rst.b.ctrl_sw_rst = 1; + sw_rst.b.ctrl_sw_rst_noreg = 1; + dtmb_write_reg(DTMB_TOP_CTRL_SW_RST, sw_rst.d32); + sw_rst.b.ctrl_sw_rst = 0; + sw_rst.b.ctrl_sw_rst_noreg = 0; + dtmb_write_reg(DTMB_TOP_CTRL_SW_RST, sw_rst.d32); +} + +void dtmb_register_reset(void) +{ + union DTMB_TOP_CTRL_SW_RST_BITS sw_rst; + + sw_rst.b.ctrl_sw_rst = 1; + dtmb_write_reg(DTMB_TOP_CTRL_SW_RST, sw_rst.d32); + sw_rst.b.ctrl_sw_rst = 0; + dtmb_write_reg(DTMB_TOP_CTRL_SW_RST, sw_rst.d32); +} + +int dtmb_set_ch(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c, + struct aml_demod_dtmb *demod_dtmb) +{ + int ret = 0; + u8 demod_mode; + u8 bw, sr, ifreq, agc_mode; + u32 ch_freq; + + bw = demod_dtmb->bw; + sr = demod_dtmb->sr; + ifreq = demod_dtmb->ifreq; + agc_mode = demod_dtmb->agc_mode; + ch_freq = demod_dtmb->ch_freq; + demod_mode = demod_dtmb->dat0; + demod_sta->ch_mode = demod_dtmb->mode; /* TODO */ + demod_sta->agc_mode = agc_mode; + demod_sta->ch_freq = ch_freq; + demod_sta->dvb_mode = demod_mode; + demod_sta->ch_bw = (8 - bw) * 1000; + dtmb_initial(demod_sta); + pr_dbg("DTMB mode\n"); + return ret; +} + +int dvbt_set_ch(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c, + struct aml_demod_dvbt *demod_dvbt) +{ + int ret = 0; + u8_t demod_mode = 1; + u8_t bw, sr, ifreq, agc_mode; + u32_t ch_freq; + + bw = demod_dvbt->bw; + sr = demod_dvbt->sr; + ifreq = demod_dvbt->ifreq; + agc_mode = demod_dvbt->agc_mode; + ch_freq = demod_dvbt->ch_freq; + demod_mode = demod_dvbt->dat0; + if (ch_freq < 1000 || ch_freq > 900000000) { + /* pr_dbg("Error: Invalid Channel Freq option %d\n", + *ch_freq); + */ + ch_freq = 474000; + ret = -1; + } + + if (demod_mode < 0 || demod_mode > 4) { + /* pr_dbg("Error: Invalid demod mode option %d\n", + *demod_mode); + */ + demod_mode = 1; + ret = -1; + } + + /* demod_sta->dvb_mode = 1; */ + demod_sta->ch_mode = 0; /* TODO */ + demod_sta->agc_mode = agc_mode; + demod_sta->ch_freq = ch_freq; + demod_sta->dvb_mode = demod_mode; + /* if (demod_i2c->tuner == 1) + * demod_sta->ch_if = 36130; + * else if (demod_i2c->tuner == 2) + * demod_sta->ch_if = 4570; + * else if (demod_i2c->tuner == 3) + * demod_sta->ch_if = 4000;// It is nouse.(alan) + * else if (demod_i2c->tuner == 7) + * demod_sta->ch_if = 5000;//silab 5000kHz IF + */ + + demod_sta->ch_bw = (8 - bw) * 1000; + demod_sta->symb_rate = 0; /* TODO */ + +/* bw=0; */ + demod_mode = 1; + /* for si2176 IF:5M sr 28.57 */ + sr = 4; + ifreq = 4; + if (bw == BANDWIDTH_AUTO) + demod_mode = 2; + ofdm_initial(bw, + /* 00:8M 01:7M 10:6M 11:5M */ + sr, + /* 00:45M 01:20.8333M 10:20.7M 11:28.57 100:24m */ + ifreq, + /* 000:36.13M 001:-5.5M 010:4.57M 011:4M 100:5M */ + demod_mode - 1, + /* 00:DVBT,01:ISDBT */ + 1 + /* 0: Unsigned, 1:TC */ + ); + pr_dbg("DVBT/ISDBT mode\n"); + + return ret; +} + +int demod_set_sys(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c, + struct aml_demod_sys *demod_sys) +{ +/* int adc_clk; */ +/* demod_sta->tmp=Adc_mode; */ + unsigned char dvb_mode; + int clk_adc, clk_dem; + int gpioDV_2; + int gpiW_2; + + dvb_mode = demod_sta->dvb_mode; + clk_adc = demod_sys->adc_clk; + clk_dem = demod_sys->demod_clk; + pr_dbg + ("demod_set_sys,clk_adc is %d,clk_demod is %d\n", + clk_adc, clk_dem); + mutex_init(&mp); + clocks_set_sys_defaults(dvb_mode); + /* open dtv adc pinmux */ + if (is_meson_txl_cpu()) { + gpioDV_2 = demod_read_demod_reg(0xc8834400 + (0x2e << 2)); + pr_dbg("[R840]set adc pinmux,gpioDV_2 %x\n", gpioDV_2); + gpioDV_2 = gpioDV_2 | (0x1 << 22); + gpioDV_2 = gpioDV_2 & ~(0x3 << 19); + gpioDV_2 = gpioDV_2 & ~(0x1 << 23); + gpioDV_2 = gpioDV_2 & ~(0x1 << 31); + demod_set_demod_reg(gpioDV_2, 0xc8834400 + (0x2e << 2)); + pr_dbg("[R840]set adc pinmux,gpioDV_2 %x\n", gpioDV_2); + } else { + gpiW_2 = demod_read_demod_reg(0xc88344c4); + gpiW_2 = gpiW_2 | (0x1 << 25); + gpiW_2 = gpiW_2 & ~(0xd << 24); + demod_set_demod_reg(gpiW_2, 0xc88344c4); + pr_dbg("[R840]set adc pinmux,gpiW_2 %x\n", gpiW_2); + } + /* set adc clk */ + demod_set_adc_core_clk(clk_adc, clk_dem, dvb_mode); + /* init for dtmb */ + if (dvb_mode == Gxtv_Dtmb) { + /* open arbit */ + /* demod_set_demod_reg(0x8, DEMOD_REG4);*/ + } + demod_sta->adc_freq = clk_adc; + demod_sta->clk_freq = clk_dem; + return 0; +} + +void demod_set_reg(struct aml_demod_reg *demod_reg) +{ + switch (demod_reg->mode) { + case 0: + demod_reg->addr = demod_reg->addr + QAM_BASE; + break; + case 1: + case 2: + demod_reg->addr = DTMB_TOP_ADDR(demod_reg->addr); + break; + case 3: + /* demod_reg->addr=ATSC_BASE; */ + break; + case 4: + demod_reg->addr = demod_reg->addr * 4 + DEMOD_CFG_BASE; + break; + case 5: + demod_reg->addr = demod_reg->addr + DEMOD_BASE; + break; + case 6: + /* demod_reg->addr=demod_reg->addr*4+DEMOD_CFG_BASE; */ + break; + case 11: + demod_reg->addr = demod_reg->addr; + break; + case 10: + /* demod_reg->addr=(u32_t)phys_to_virt(demod_reg->addr); */ + break; + } + + if (demod_reg->mode == 3) + atsc_write_reg(demod_reg->addr, demod_reg->val); + else if (demod_reg->mode == 11) + demod_set_cbus_reg(demod_reg->val, demod_reg->addr); + else if (demod_reg->mode == 10) + apb_write_reg_collect(demod_reg->addr, demod_reg->val); + /* demod_reg->val_high = apb_read_reg_high(demod_reg->addr); */ + else + demod_set_demod_reg(demod_reg->val, demod_reg->addr); +} + +void demod_get_reg(struct aml_demod_reg *demod_reg) +{ + if (demod_reg->mode == 0) { + demod_reg->addr = demod_reg->addr + QAM_BASE; + } else if ((demod_reg->mode == 1) || (demod_reg->mode == 2)) { + demod_reg->addr = DTMB_TOP_ADDR(demod_reg->addr); + } else if (demod_reg->mode == 3) { + /* demod_reg->addr=demod_reg->addr+ATSC_BASE; */ + } else if (demod_reg->mode == 4) { + demod_reg->addr = demod_reg->addr * 4 + DEMOD_CFG_BASE; + } else if (demod_reg->mode == 5) { + demod_reg->addr = demod_reg->addr + DEMOD_BASE; + } else if (demod_reg->mode == 6) { + /* demod_reg->addr=demod_reg->addr*4+DEMOD_CFG_BASE; */ + } else if (demod_reg->mode == 11) { + demod_reg->addr = demod_reg->addr; + } else if (demod_reg->mode == 10) { + /* printk("demod_reg->addr is %x\n",demod_reg->addr); */ + /* test=(unsigned long)phys_to_virt(test); */ +/* demod_reg->addr=(unsigned long)phys_to_virt(demod_reg->addr); */ +/* printk("demod_reg->addr is %lx %x\n",test,demod_reg->addr); */ + } + + if (demod_reg->mode == 3) { + demod_reg->val = atsc_read_reg(demod_reg->addr); + /* apb_write_reg(ATSC_BASE+4, (demod_reg->addr&0xffff)<<8); */ + /* demod_reg->val = apb_read_reg(ATSC_BASE)&0xff; */ + } else if (demod_reg->mode == 6) { + demod_reg->val = atsc_read_iqr_reg(); + /* apb_write_reg(ATSC_BASE+4, (demod_reg->addr&0xffff)<<8); */ + /* demod_reg->val = apb_read_reg(ATSC_BASE)&0xff; */ + } else if (demod_reg->mode == 11) { + demod_reg->val = demod_read_cbus_reg(demod_reg->addr); + } else if (demod_reg->mode == 10) { + demod_reg->val = apb_read_reg_collect(demod_reg->addr); + /* demod_reg->val_high = apb_read_reg_high(demod_reg->addr);*/ + } else { + demod_reg->val = demod_read_demod_reg(demod_reg->addr); + } +} + +void apb_write_reg_collect(unsigned int addr, unsigned int data) +{ + writel(data, ((void __iomem *)(phys_to_virt(addr)))); +/* *(volatile unsigned int*)addr = data; */ +} + +unsigned long apb_read_reg_collect(unsigned long addr) +{ + unsigned long tmp; +/* void __iomem *vaddr; + * vaddr = ioremap(((unsigned long)phys_to_virt(addr)), 0x4); + * tmp = readl(vaddr); + * iounmap(vaddr); + */ + tmp = readl((void __iomem *)(phys_to_virt(addr))); +/*tmp = *(volatile unsigned long *)((unsigned long)phys_to_virt(addr));*/ +/* printk("[all][read]%lx,data is %lx\n",addr,tmp); */ + return tmp & 0xffffffff; +} + + + +void apb_write_reg(unsigned int addr, unsigned int data) +{ + demod_set_demod_reg(data, addr); +} + +unsigned long apb_read_reg_high(unsigned long addr) +{ + unsigned long tmp; + + tmp = 0; + return (tmp >> 32) & 0xffffffff; +} + +unsigned long apb_read_reg(unsigned long addr) +{ + return demod_read_demod_reg(addr); +} + +void apb_write_regb(unsigned long addr, int index, unsigned long data) +{ + /*to achieve write func*/ +} + +void enable_qam_int(int idx) +{ + unsigned long mask; + + mask = apb_read_reg(QAM_BASE + 0xd0); + mask |= (1 << idx); + apb_write_reg(QAM_BASE + 0xd0, mask); +} + +void disable_qam_int(int idx) +{ + unsigned long mask; + + mask = apb_read_reg(QAM_BASE + 0xd0); + mask &= ~(1 << idx); + apb_write_reg(QAM_BASE + 0xd0, mask); +} + +char *qam_int_name[] = { " ADC", + " Symbol", + " RS", + " In_Sync0", + " In_Sync1", + " In_Sync2", + " In_Sync3", + " In_Sync4", + "Out_Sync0", + "Out_Sync1", + "Out_Sync2", + "Out_Sync3", + "Out_Sync4", + "In_SyncCo", + "OutSyncCo", + " In_Dagc", + " Out_Dagc", + " Eq_Mode", + "RS_Uncorr" +}; + +#define OFDM_INT_STS 0 +#define OFDM_INT_EN 0 + +void enable_ofdm_int(int ofdm_irq) +{ + +} + +void disable_ofdm_int(int ofdm_irq) +{ + +} + +char *ofdm_int_name[] = { "PFS_FCFO", + "PFS_ICFO", + " CS_FCFO", + " PFS_SFO", + " PFS_TPS", + " SP", + " CCI", + " Symbol", + " In_Sync", + "Out_Sync", + "FSM Stat" +}; + +unsigned long read_ofdm_int(void) +{ + + return 0; +} + +#define PHS_LOOP_OPEN + +void qam_read_all_regs(void) +{ + +} + +void ini_icfo_pn_index(int mode) +{ /* 00:DVBT,01:ISDBT */ + if (mode == 0) { + apb_write_reg(DVBT_BASE + 0x3f8, 0x00000031); + apb_write_reg(DVBT_BASE + 0x3fc, 0x00030000); + apb_write_reg(DVBT_BASE + 0x3f8, 0x00000032); + apb_write_reg(DVBT_BASE + 0x3fc, 0x00057036); + apb_write_reg(DVBT_BASE + 0x3f8, 0x00000033); + apb_write_reg(DVBT_BASE + 0x3fc, 0x0009c08d); + apb_write_reg(DVBT_BASE + 0x3f8, 0x00000034); + apb_write_reg(DVBT_BASE + 0x3fc, 0x000c90c0); + apb_write_reg(DVBT_BASE + 0x3f8, 0x00000035); + apb_write_reg(DVBT_BASE + 0x3fc, 0x001170ff); + apb_write_reg(DVBT_BASE + 0x3f8, 0x00000036); + apb_write_reg(DVBT_BASE + 0x3fc, 0x0014d11a); + } else if (mode == 1) { + apb_write_reg(DVBT_BASE + 0x3f8, 0x00000031); + apb_write_reg(DVBT_BASE + 0x3fc, 0x00085046); + apb_write_reg(DVBT_BASE + 0x3f8, 0x00000032); + apb_write_reg(DVBT_BASE + 0x3fc, 0x0019a0e9); + apb_write_reg(DVBT_BASE + 0x3f8, 0x00000033); + apb_write_reg(DVBT_BASE + 0x3fc, 0x0024b1dc); + apb_write_reg(DVBT_BASE + 0x3f8, 0x00000034); + apb_write_reg(DVBT_BASE + 0x3fc, 0x003b3313); + apb_write_reg(DVBT_BASE + 0x3f8, 0x00000035); + apb_write_reg(DVBT_BASE + 0x3fc, 0x0048d409); + apb_write_reg(DVBT_BASE + 0x3f8, 0x00000036); + apb_write_reg(DVBT_BASE + 0x3fc, 0x00527509); + } +} + +static int coef[] = { + 0xf900, 0xfe00, 0x0000, 0x0000, 0x0100, 0x0100, 0x0000, 0x0000, + 0xfd00, 0xf700, 0x0000, 0x0000, 0x4c00, 0x0000, 0x0000, 0x0000, + 0x2200, 0x0c00, 0x0000, 0x0000, 0xf700, 0xf700, 0x0000, 0x0000, + 0x0300, 0x0900, 0x0000, 0x0000, 0x0600, 0x0600, 0x0000, 0x0000, + 0xfc00, 0xf300, 0x0000, 0x0000, 0x2e00, 0x0000, 0x0000, 0x0000, + 0x3900, 0x1300, 0x0000, 0x0000, 0xfa00, 0xfa00, 0x0000, 0x0000, + 0x0100, 0x0200, 0x0000, 0x0000, 0xf600, 0x0000, 0x0000, 0x0000, + 0x0700, 0x0700, 0x0000, 0x0000, 0xfe00, 0xfb00, 0x0000, 0x0000, + 0x0900, 0x0000, 0x0000, 0x0000, 0x3200, 0x1100, 0x0000, 0x0000, + 0x0400, 0x0400, 0x0000, 0x0000, 0xfe00, 0xfb00, 0x0000, 0x0000, + 0x0e00, 0x0000, 0x0000, 0x0000, 0xfb00, 0xfb00, 0x0000, 0x0000, + 0x0100, 0x0200, 0x0000, 0x0000, 0xf400, 0x0000, 0x0000, 0x0000, + 0x3900, 0x1300, 0x0000, 0x0000, 0x1700, 0x1700, 0x0000, 0x0000, + 0xfc00, 0xf300, 0x0000, 0x0000, 0x0c00, 0x0000, 0x0000, 0x0000, + 0x0300, 0x0900, 0x0000, 0x0000, 0xee00, 0x0000, 0x0000, 0x0000, + 0x2200, 0x0c00, 0x0000, 0x0000, 0x2600, 0x2600, 0x0000, 0x0000, + 0xfd00, 0xf700, 0x0000, 0x0000, 0x0200, 0x0000, 0x0000, 0x0000, + 0xf900, 0xfe00, 0x0000, 0x0000, 0x0400, 0x0b00, 0x0000, 0x0000, + 0xf900, 0x0000, 0x0000, 0x0000, 0x0700, 0x0200, 0x0000, 0x0000, + 0x2100, 0x2100, 0x0000, 0x0000, 0x0200, 0x0700, 0x0000, 0x0000, + 0xf900, 0x0000, 0x0000, 0x0000, 0x0b00, 0x0400, 0x0000, 0x0000, + 0xfe00, 0xf900, 0x0000, 0x0000, 0x0200, 0x0000, 0x0000, 0x0000, + 0xf700, 0xfd00, 0x0000, 0x0000, 0x2600, 0x2600, 0x0000, 0x0000, + 0x0c00, 0x2200, 0x0000, 0x0000, 0xee00, 0x0000, 0x0000, 0x0000, + 0x0900, 0x0300, 0x0000, 0x0000, 0x0c00, 0x0000, 0x0000, 0x0000, + 0xf300, 0xfc00, 0x0000, 0x0000, 0x1700, 0x1700, 0x0000, 0x0000, + 0x1300, 0x3900, 0x0000, 0x0000, 0xf400, 0x0000, 0x0000, 0x0000, + 0x0200, 0x0100, 0x0000, 0x0000, 0xfb00, 0xfb00, 0x0000, 0x0000, + 0x0e00, 0x0000, 0x0000, 0x0000, 0xfb00, 0xfe00, 0x0000, 0x0000, + 0x0400, 0x0400, 0x0000, 0x0000, 0x1100, 0x3200, 0x0000, 0x0000, + 0x0900, 0x0000, 0x0000, 0x0000, 0xfb00, 0xfe00, 0x0000, 0x0000, + 0x0700, 0x0700, 0x0000, 0x0000, 0xf600, 0x0000, 0x0000, 0x0000, + 0x0200, 0x0100, 0x0000, 0x0000, 0xfa00, 0xfa00, 0x0000, 0x0000, + 0x1300, 0x3900, 0x0000, 0x0000, 0x2e00, 0x0000, 0x0000, 0x0000, + 0xf300, 0xfc00, 0x0000, 0x0000, 0x0600, 0x0600, 0x0000, 0x0000, + 0x0900, 0x0300, 0x0000, 0x0000, 0xf700, 0xf700, 0x0000, 0x0000, + 0x0c00, 0x2200, 0x0000, 0x0000, 0x4c00, 0x0000, 0x0000, 0x0000, + 0xf700, 0xfd00, 0x0000, 0x0000, 0x0100, 0x0100, 0x0000, 0x0000, + 0xfe00, 0xf900, 0x0000, 0x0000, 0x0b00, 0x0400, 0x0000, 0x0000, + 0xfc00, 0xfc00, 0x0000, 0x0000, 0x0200, 0x0700, 0x0000, 0x0000, + 0x4200, 0x0000, 0x0000, 0x0000, 0x0700, 0x0200, 0x0000, 0x0000, + 0xfc00, 0xfc00, 0x0000, 0x0000, 0x0400, 0x0b00, 0x0000, 0x0000 +}; + +void tfd_filter_coff_ini(void) +{ + int i = 0; + + for (i = 0; i < 336; i++) { + apb_write_reg(DVBT_BASE + 0x99 * 4, (i << 16) | coef[i]); + apb_write_reg(DVBT_BASE + 0x03 * 4, (1 << 12)); + } +} + +void ofdm_initial(int bandwidth, + /* 00:8M 01:7M 10:6M 11:5M */ + int samplerate, + /* 00:45M 01:20.8333M 10:20.7M 11:28.57 100: 24.00 */ + int IF, + /* 000:36.13M 001:-5.5M 010:4.57M 011:4M 100:5M */ + int mode, + /* 00:DVBT,01:ISDBT */ + int tc_mode + /* 0: Unsigned, 1:TC */ + ) +{ +#if 0 + int tmp; + int ch_if; + int adc_freq; + + pr_dbg + ("[ofdm_initial]bandwidth is %d,samplerate is %d", + bandwidth, samplerate); + pr_dbg + ("IF is %d, mode is %d,tc_mode is %d\n", + IF, mode, tc_mode); + switch (IF) { + case 0: + ch_if = 36130; + break; + case 1: + ch_if = -5500; + break; + case 2: + ch_if = 4570; + break; + case 3: + ch_if = 4000; + break; + case 4: + ch_if = 5000; + break; + default: + ch_if = 4000; + break; + } + switch (samplerate) { + case 0: + adc_freq = 45000; + break; + case 1: + adc_freq = 20833; + break; + case 2: + adc_freq = 20700; + break; + case 3: + adc_freq = 28571; + break; + case 4: + adc_freq = 24000; + break; + default: + adc_freq = 28571; + break; + } + + apb_write_reg(DVBT_BASE + (0x02 << 2), 0x00800000); + /* SW reset bit[23] ; write anything to zero */ + apb_write_reg(DVBT_BASE + (0x00 << 2), 0x00000000); + + apb_write_reg(DVBT_BASE + (0xe << 2), 0xffff); + /* enable interrupt */ + + if (mode == 0) { /* DVBT */ + switch (samplerate) { + case 0: + apb_write_reg(DVBT_BASE + (0x08 << 2), 0x00005a00); + break; /* 45MHz */ + case 1: + apb_write_reg(DVBT_BASE + (0x08 << 2), 0x000029aa); + break; /* 20.833 */ + case 2: + apb_write_reg(DVBT_BASE + (0x08 << 2), 0x00002966); + break; /* 20.7 SAMPLERATE*512 */ + case 3: + apb_write_reg(DVBT_BASE + (0x08 << 2), 0x00003924); + break; /* 28.571 */ + case 4: + apb_write_reg(DVBT_BASE + (0x08 << 2), 0x00003000); + break; /* 24 */ + default: + apb_write_reg(DVBT_BASE + (0x08 << 2), 0x00003924); + break; /* 28.571 */ + } + } else { /* ISDBT */ + switch (samplerate) { + case 0: + apb_write_reg(DVBT_BASE + (0x08 << 2), 0x0000580d); + break; /* 45MHz */ + case 1: + apb_write_reg(DVBT_BASE + (0x08 << 2), 0x0000290d); + break; /* 20.833 = 56/7 * 20.8333 / (512/63)*512 */ + case 2: + apb_write_reg(DVBT_BASE + (0x08 << 2), 0x000028da); + break; /* 20.7 */ + case 3: + apb_write_reg(DVBT_BASE + (0x08 << 2), 0x0000383F); + break; /* 28.571 3863 */ + case 4: + apb_write_reg(DVBT_BASE + (0x08 << 2), 0x00002F40); + break; /* 24 */ + default: + apb_write_reg(DVBT_BASE + (0x08 << 2), 0x00003863); + break; /* 28.571 */ + } + } +/* memstart=0x93900000; */ + pr_dbg("memstart is %x\n", memstart); + apb_write_reg(DVBT_BASE + (0x10 << 2), memstart); + /* 0x8f300000 */ + + apb_write_reg(DVBT_BASE + (0x14 << 2), 0xe81c4ff6); + /* AGC_TARGET 0xf0121385 */ + + switch (samplerate) { + case 0: + apb_write_reg(DVBT_BASE + (0x15 << 2), 0x018c2df2); + break; + case 1: + apb_write_reg(DVBT_BASE + (0x15 << 2), 0x0185bdf2); + break; + case 2: + apb_write_reg(DVBT_BASE + (0x15 << 2), 0x0185bdf2); + break; + case 3: + apb_write_reg(DVBT_BASE + (0x15 << 2), 0x0187bdf2); + break; + case 4: + apb_write_reg(DVBT_BASE + (0x15 << 2), 0x0187bdf2); + break; + default: + apb_write_reg(DVBT_BASE + (0x15 << 2), 0x0187bdf2); + break; + } + if (tc_mode == 1) + apb_write_regb(DVBT_BASE + (0x15 << 2), 11, 0); + /* For TC mode. Notice, For ADC input is Unsigned, + *For Capture Data, It is TC. + */ + apb_write_regb(DVBT_BASE + (0x15 << 2), 26, 1); + /* [19:0] = [I , Q], I is high, Q is low. This bit is swap I/Q. */ + + apb_write_reg(DVBT_BASE + (0x16 << 2), 0x00047f80); + /* AGC_IFGAIN_CTRL */ + apb_write_reg(DVBT_BASE + (0x17 << 2), 0x00027f80); + /* AGC_RFGAIN_CTRL */ + apb_write_reg(DVBT_BASE + (0x18 << 2), 0x00000190); + /* AGC_IFGAIN_ACCUM */ + apb_write_reg(DVBT_BASE + (0x19 << 2), 0x00000190); + /* AGC_RFGAIN_ACCUM */ + if (ch_if < 0) + ch_if += adc_freq; + if (ch_if > adc_freq) + ch_if -= adc_freq; + + tmp = ch_if * (1 << 15) / adc_freq; + apb_write_reg(DVBT_BASE + (0x20 << 2), tmp); + + apb_write_reg(DVBT_BASE + (0x21 << 2), 0x001ff000); + /* DDC CS_FCFO_ADJ_CTRL */ + apb_write_reg(DVBT_BASE + (0x22 << 2), 0x00000000); + /* DDC ICFO_ADJ_CTRL */ + apb_write_reg(DVBT_BASE + (0x23 << 2), 0x00004000); + /* DDC TRACK_FCFO_ADJ_CTRL */ + + apb_write_reg(DVBT_BASE + (0x27 << 2), (1 << 23) + | (3 << 19) | (3 << 15) | (1000 << 4) | 9); + /* {8'd0,1'd1,4'd3,4'd3,11'd50,4'd9});//FSM_1 */ + apb_write_reg(DVBT_BASE + (0x28 << 2), (100 << 13) | 1000); + /* {8'd0,11'd40,13'd50});//FSM_2 */ + apb_write_reg(DVBT_BASE + (0x29 << 2), (31 << 20) | (1 << 16) | + (24 << 9) | (3 << 6) | 20); + /* {5'd0,7'd127,1'd0,3'd0,7'd24,3'd5,6'd20}); */ + + if (mode == 0) { /* DVBT */ + if (bandwidth == 0) { /* 8M */ + switch (samplerate) { + case 0: + ini_acf_iireq_src_45m_8m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x004ebf2e); + break; /* 45M */ + case 1: + ini_acf_iireq_src_207m_8m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x00247551); + break; /* 20.833M */ + case 2: + ini_acf_iireq_src_207m_8m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x00243999); + break; /* 20.7M */ + case 3: + ini_acf_iireq_src_2857m_8m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x0031ffcd); + break; /* 28.57M */ + case 4: + ini_acf_iireq_src_24m_8m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x002A0000); + break; /* 24M */ + default: + ini_acf_iireq_src_2857m_8m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x0031ffcd); + break; /* 28.57M */ + } + } else if (bandwidth == 1) { /* 7M */ + switch (samplerate) { + case 0: + ini_acf_iireq_src_45m_7m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x0059ff10); + break; /* 45M */ + case 1: + ini_acf_iireq_src_207m_7m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x0029aaa6); + break; /* 20.833M */ + case 2: + ini_acf_iireq_src_207m_7m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x00296665); + break; /* 20.7M */ + case 3: + ini_acf_iireq_src_2857m_7m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x00392491); + break; /* 28.57M */ + case 4: + ini_acf_iireq_src_24m_7m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x00300000); + break; /* 24M */ + default: + ini_acf_iireq_src_2857m_7m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x00392491); + break; /* 28.57M */ + } + } else if (bandwidth == 2) { /* 6M */ + switch (samplerate) { + case 0: + ini_acf_iireq_src_45m_6m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x00690000); + break; /* 45M */ + case 1: + ini_acf_iireq_src_207m_6m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x00309c3e); + break; /* 20.833M */ + case 2: + ini_acf_iireq_src_207m_6m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x002eaaaa); + break; /* 20.7M */ + case 3: + ini_acf_iireq_src_2857m_6m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x0042AA69); + break; /* 28.57M */ + case 4: + ini_acf_iireq_src_24m_6m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x00380000); + break; /* 24M */ + default: + ini_acf_iireq_src_2857m_6m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x0042AA69); + break; /* 28.57M */ + } + } else { /* 5M */ + switch (samplerate) { + case 0: + ini_acf_iireq_src_45m_5m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x007dfbe0); + break; /* 45M */ + case 1: + ini_acf_iireq_src_207m_5m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x003a554f); + break; /* 20.833M */ + case 2: + ini_acf_iireq_src_207m_5m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x0039f5c0); + break; /* 20.7M */ + case 3: + ini_acf_iireq_src_2857m_5m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x004FFFFE); + break; /* 28.57M */ + case 4: + ini_acf_iireq_src_24m_5m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x00433333); + break; /* 24M */ + default: + ini_acf_iireq_src_2857m_5m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), + 0x004FFFFE); + break; /* 28.57M */ + } + } + } else { /* ISDBT */ + switch (samplerate) { + case 0: + ini_acf_iireq_src_45m_6m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), 0x00589800); + break; + +/* 45M + * SampleRate/(symbolRate)*2^20, + * symbolRate = 512/63 for isdbt + */ + case 1: + ini_acf_iireq_src_207m_6m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), 0x002903d4); + break; /* 20.833M */ + case 2: + ini_acf_iireq_src_207m_6m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), 0x00280ccc); + break; /* 20.7M */ + case 3: + ini_acf_iireq_src_2857m_6m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), 0x00383fc8); + break; /* 28.57M */ + case 4: + ini_acf_iireq_src_24m_6m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), 0x002F4000); + break; /* 24M */ + default: + ini_acf_iireq_src_2857m_6m(); + apb_write_reg(DVBT_BASE + (0x44 << 2), 0x00383fc8); + break; /* 28.57M */ + } + } + + if (mode == 0) /* DVBT */ + apb_write_reg(DVBT_BASE + (0x02 << 2), + (bandwidth << 20) | 0x10002); + else /* ISDBT */ + apb_write_reg(DVBT_BASE + (0x02 << 2), (1 << 20) | 0x1001a); + /* {0x000,2'h1,20'h1_001a}); // For ISDBT , bandwidth should be 1, */ + + apb_write_reg(DVBT_BASE + (0x45 << 2), 0x00000000); + /* SRC SFO_ADJ_CTRL */ + apb_write_reg(DVBT_BASE + (0x46 << 2), 0x02004000); + /* SRC SFO_ADJ_CTRL */ + apb_write_reg(DVBT_BASE + (0x48 << 2), 0x000c0287); + /* DAGC_CTRL1 */ + apb_write_reg(DVBT_BASE + (0x49 << 2), 0x00000005); + /* DAGC_CTRL2 */ + apb_write_reg(DVBT_BASE + (0x4c << 2), 0x00000bbf); + /* CCI_RP */ + apb_write_reg(DVBT_BASE + (0x4d << 2), 0x00000376); + /* CCI_RPSQ */ + apb_write_reg(DVBT_BASE + (0x4e << 2), 0x0f0f1d09); + /* CCI_CTRL */ + apb_write_reg(DVBT_BASE + (0x4f << 2), 0x00000000); + /* CCI DET_INDX1 */ + apb_write_reg(DVBT_BASE + (0x50 << 2), 0x00000000); + /* CCI DET_INDX2 */ + apb_write_reg(DVBT_BASE + (0x51 << 2), 0x00000000); + /* CCI_NOTCH1_A1 */ + apb_write_reg(DVBT_BASE + (0x52 << 2), 0x00000000); + /* CCI_NOTCH1_A2 */ + apb_write_reg(DVBT_BASE + (0x53 << 2), 0x00000000); + /* CCI_NOTCH1_B1 */ + apb_write_reg(DVBT_BASE + (0x54 << 2), 0x00000000); + /* CCI_NOTCH2_A1 */ + apb_write_reg(DVBT_BASE + (0x55 << 2), 0x00000000); + /* CCI_NOTCH2_A2 */ + apb_write_reg(DVBT_BASE + (0x56 << 2), 0x00000000); + /* CCI_NOTCH2_B1 */ + apb_write_reg(DVBT_BASE + (0x58 << 2), 0x00000885); + /* MODE_DETECT_CTRL // 582 */ + if (mode == 0) /* DVBT */ + apb_write_reg(DVBT_BASE + (0x5c << 2), 0x00001011); /* */ + else + apb_write_reg(DVBT_BASE + (0x5c << 2), 0x00000753); + /* ICFO_EST_CTRL ISDBT ICFO thres = 2 */ + + apb_write_reg(DVBT_BASE + (0x5f << 2), 0x0ffffe10); + /* TPS_FCFO_CTRL */ + apb_write_reg(DVBT_BASE + (0x61 << 2), 0x0000006c); + /* FWDT ctrl */ + apb_write_reg(DVBT_BASE + (0x68 << 2), 0x128c3929); + apb_write_reg(DVBT_BASE + (0x69 << 2), 0x91017f2d); + /* 0x1a8 */ + apb_write_reg(DVBT_BASE + (0x6b << 2), 0x00442211); + /* 0x1a8 */ + apb_write_reg(DVBT_BASE + (0x6c << 2), 0x01fc400a); + /* 0x */ + apb_write_reg(DVBT_BASE + (0x6d << 2), 0x0030303f); + /* 0x */ + apb_write_reg(DVBT_BASE + (0x73 << 2), 0xffffffff); + /* CCI0_PILOT_UPDATE_CTRL */ + apb_write_reg(DVBT_BASE + (0x74 << 2), 0xffffffff); + /* CCI0_DATA_UPDATE_CTRL */ + apb_write_reg(DVBT_BASE + (0x75 << 2), 0xffffffff); + /* CCI1_PILOT_UPDATE_CTRL */ + apb_write_reg(DVBT_BASE + (0x76 << 2), 0xffffffff); + /* CCI1_DATA_UPDATE_CTRL */ + + tmp = mode == 0 ? 0x000001a2 : 0x00000da2; + apb_write_reg(DVBT_BASE + (0x78 << 2), tmp); /* FEC_CTR */ + + apb_write_reg(DVBT_BASE + (0x7d << 2), 0x0000009d); + apb_write_reg(DVBT_BASE + (0x7e << 2), 0x00004000); + apb_write_reg(DVBT_BASE + (0x7f << 2), 0x00008000); + + apb_write_reg(DVBT_BASE + ((0x8b + 0) << 2), 0x20002000); + apb_write_reg(DVBT_BASE + ((0x8b + 1) << 2), 0x20002000); + apb_write_reg(DVBT_BASE + ((0x8b + 2) << 2), 0x20002000); + apb_write_reg(DVBT_BASE + ((0x8b + 3) << 2), 0x20002000); + apb_write_reg(DVBT_BASE + ((0x8b + 4) << 2), 0x20002000); + apb_write_reg(DVBT_BASE + ((0x8b + 5) << 2), 0x20002000); + apb_write_reg(DVBT_BASE + ((0x8b + 6) << 2), 0x20002000); + apb_write_reg(DVBT_BASE + ((0x8b + 7) << 2), 0x20002000); + + apb_write_reg(DVBT_BASE + (0x93 << 2), 0x31); + apb_write_reg(DVBT_BASE + (0x94 << 2), 0x00); + apb_write_reg(DVBT_BASE + (0x95 << 2), 0x7f1); + apb_write_reg(DVBT_BASE + (0x96 << 2), 0x20); + + apb_write_reg(DVBT_BASE + (0x98 << 2), 0x03f9115a); + apb_write_reg(DVBT_BASE + (0x9b << 2), 0x000005df); + + apb_write_reg(DVBT_BASE + (0x9c << 2), 0x00100000); + /* TestBus write valid, 0 is system clk valid */ + apb_write_reg(DVBT_BASE + (0x9d << 2), 0x01000000); + /* DDR Start address */ + apb_write_reg(DVBT_BASE + (0x9e << 2), 0x02000000); + /* DDR End address */ + + apb_write_regb(DVBT_BASE + (0x9b << 2), 7, 0); + /* Enable Testbus dump to DDR */ + apb_write_regb(DVBT_BASE + (0x9b << 2), 8, 0); + /* Run Testbus dump to DDR */ + + apb_write_reg(DVBT_BASE + (0xd6 << 2), 0x00000003); + /* apb_write_reg(DVBT_BASE+(0xd7<<2), 0x00000008); */ + apb_write_reg(DVBT_BASE + (0xd8 << 2), 0x00000120); + apb_write_reg(DVBT_BASE + (0xd9 << 2), 0x01010101); + + ini_icfo_pn_index(mode); + tfd_filter_coff_ini(); + + calculate_cordic_para(); + msleep(20); + /* delay_us(1); */ + + apb_write_reg(DVBT_BASE + (0x02 << 2), + apb_read_reg(DVBT_BASE + (0x02 << 2)) | (1 << 0)); + apb_write_reg(DVBT_BASE + (0x02 << 2), + apb_read_reg(DVBT_BASE + (0x02 << 2)) | (1 << 24)); +#endif +/* dvbt_check_status(); */ +} + +void calculate_cordic_para(void) +{ + apb_write_reg(DVBT_BASE + 0x0c, 0x00000040); +} + +char *ofdm_fsm_name[] = { " IDLE", + " AGC", + " CCI", + " ACQ", + " SYNC", + "TRACKING", + " TIMING", + " SP_SYNC", + " TPS_DEC", + "FEC_LOCK", + "FEC_LOST" +}; + +void check_fsm_state(void) +{ + unsigned long tmp; + + tmp = apb_read_reg(DVBT_BASE + 0xa8); + /* printk(">>>>>>>>>>>>>>>>>>>>>>>>> OFDM FSM From %d + *to %d\n", tmp>>4&0xf, tmp&0xf); + */ + + if ((tmp & 0xf) == 3) { + apb_write_regb(DVBT_BASE + (0x9b << 2), 8, 1); + /* Stop dump testbus; */ + apb_write_regb(DVBT_BASE + (0x0f << 2), 0, 1); + tmp = apb_read_reg(DVBT_BASE + (0x9f << 2)); + /* printk(">>>>>>>>>>>>>>>>>>>>>>>>> STOP DUMP DATA To DDR : + *End Addr %d,Is it overflow?%d\n", tmp>>1, tmp&0x1); + */ + } +} + +void ofdm_read_all_regs(void) +{ + int i; + unsigned long tmp; + + for (i = 0; i < 0xff; i++) + tmp = apb_read_reg(DVBT_BASE + 0x00 + i * 4); + /* printk("OFDM Reg (0x%x) is 0x%x\n", i, tmp); */ + +} + +static int dvbt_get_status(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c) +{ + return apb_read_reg(DVBT_BASE + 0x0) >> 12 & 1; +} + +static int dvbt_get_ber(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c) +{ +/* pr_dbg("[RSJ]per is %u\n",apb_read_reg(DVBT_BASE+(0xbf<<2))); */ + return apb_read_reg(DVBT_BASE + (0xbf << 2)); +} + +static int dvbt_get_snr(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c) +{ +/* pr_dbg("2snr is %u\n",((apb_read_reg(DVBT_BASE+(0x0a<<2)))>>20)&0x3ff); */ + return ((apb_read_reg(DVBT_BASE + (0x0a << 2))) >> 20) & 0x3ff; + /*dBm: bit0~bit2=decimal */ +} + +static int dvbt_get_strength(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c) +{ +/* int dbm = dvbt_get_ch_power(demod_sta, demod_i2c); */ +/* return dbm; */ + return 0; +} + +static int dvbt_get_ucblocks(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c) +{ + return 0; +/* return dvbt_get_per(); */ +} + +struct demod_status_ops *dvbt_get_status_ops(void) +{ + static struct demod_status_ops ops = { + .get_status = dvbt_get_status, + .get_ber = dvbt_get_ber, + .get_snr = dvbt_get_snr, + .get_strength = dvbt_get_strength, + .get_ucblocks = dvbt_get_ucblocks, + }; + + return &ops; +} + +int app_apb_read_reg(int addr) +{ + addr = DTMB_TOP_ADDR(addr); + return (int)demod_read_demod_reg(addr); +} + +int app_apb_write_reg(int addr, int data) +{ + addr = DTMB_TOP_ADDR(addr); + demod_set_demod_reg(data, addr); + return 0; +} + +void monitor_isdbt(void) +{ + int SNR; + int SNR_SP = 500; + int SNR_TPS = 0; + int SNR_CP = 0; + int timeStamp = 0; + int SFO_residual = 0; + int SFO_esti = 0; + int FCFO_esti = 0; + int FCFO_residual = 0; + int AGC_Gain = 0; + int RF_AGC = 0; + int Signal_power = 0; + int FECFlag = 0; + int EQ_seg_ratio = 0; + int tps_0 = 0; + int tps_1 = 0; + int tps_2 = 0; + + int time_stamp; + int SFO; + int FCFO; + int timing_adj; + int RS_CorrectNum; + + int cnt; + int tmpAGCGain; + + tmpAGCGain = 0; + cnt = 0; + +/* app_apb_write_reg(0x8, app_apb_read_reg(0x8) & ~(1 << 17)); + * // TPS symbol index update : active high + */ + time_stamp = app_apb_read_reg(0x07) & 0xffff; + SNR = app_apb_read_reg(0x0a); + FECFlag = (app_apb_read_reg(0x00) >> 11) & 0x3; + SFO = app_apb_read_reg(0x47) & 0xfff; + SFO_esti = app_apb_read_reg(0x60) & 0xfff; + FCFO_esti = (app_apb_read_reg(0x60) >> 11) & 0xfff; + FCFO = (app_apb_read_reg(0x26)) & 0xffffff; + RF_AGC = app_apb_read_reg(0x0c) & 0x1fff; + timing_adj = app_apb_read_reg(0x6f) & 0x1fff; + RS_CorrectNum = app_apb_read_reg(0xc1) & 0xfffff; + Signal_power = (app_apb_read_reg(0x1b)) & 0x1ff; + EQ_seg_ratio = app_apb_read_reg(0x6e) & 0x3ffff; + tps_0 = app_apb_read_reg(0x64); + tps_1 = app_apb_read_reg(0x65); + tps_2 = app_apb_read_reg(0x66) & 0xf; + + timeStamp = (time_stamp >> 8) * 68 + (time_stamp & 0x7f); + SFO_residual = (SFO > 0x7ff) ? (SFO - 0x1000) : SFO; + FCFO_residual = (FCFO > 0x7fffff) ? (FCFO - 0x1000000) : FCFO; + /* RF_AGC = (RF_AGC>0x3ff)? (RF_AGC - 0x800): RF_AGC; */ + FCFO_esti = (FCFO_esti > 0x7ff) ? (FCFO_esti - 0x1000) : FCFO_esti; + SNR_CP = (SNR) & 0x3ff; + SNR_TPS = (SNR >> 10) & 0x3ff; + SNR_SP = (SNR >> 20) & 0x3ff; + SNR_SP = (SNR_SP > 0x1ff) ? SNR_SP - 0x400 : SNR_SP; + SNR_TPS = (SNR_TPS > 0x1ff) ? SNR_TPS - 0x400 : SNR_TPS; + SNR_CP = (SNR_CP > 0x1ff) ? SNR_CP - 0x400 : SNR_CP; + AGC_Gain = tmpAGCGain >> 4; + tmpAGCGain = (AGC_Gain > 0x3ff) ? AGC_Gain - 0x800 : AGC_Gain; + timing_adj = (timing_adj > 0xfff) ? timing_adj - 0x2000 : timing_adj; + EQ_seg_ratio = + (EQ_seg_ratio > 0x1ffff) ? EQ_seg_ratio - 0x40000 : EQ_seg_ratio; + + pr_dbg + ("T %4x SP %3d TPS %3d CP %3d EQS %8x RSC %4d", + app_apb_read_reg(0xbf) + , SNR_SP, SNR_TPS, SNR_CP +/* ,EQ_seg_ratio */ + , app_apb_read_reg(0x62) + , RS_CorrectNum); + pr_dbg + ("SFO %4d FCFO %4d Vit %4x Timing %3d SigP %3x", + SFO_residual, FCFO_residual, RF_AGC, timing_adj, + Signal_power); + pr_dbg + ("FEC %x RSErr %8x ReSyn %x tps %03x%08x", + FECFlag, app_apb_read_reg(0x0b) + , (app_apb_read_reg(0xc0) >> 20) & 0xff, + app_apb_read_reg(0x05) & 0xfff, app_apb_read_reg(0x04) + ); + pr_dbg("\n"); +} + +int find_2(int data, int *table, int len) +{ + int end; + int index; + int start; + int cnt = 0; + + start = 0; + end = len; + /* printf("data is %d\n",data); */ + while ((len > 1) && (cnt < 10)) { + cnt++; + index = (len / 2); + if (data > table[start + index]) { + start = start + index; + len = len - index - 1; + } + if (data < table[start + index]) { + len = index + 1; + } else if (data == table[start + index]) { + start = start + index; + break; + } + } + return start; +} + +int read_atsc_all_reg(void) +{ + return 0; +#if 0 + int i, j, k; + + j = 4; + unsigned long data; + + pr_dbg("system agc is:"); /* system agc */ + for (i = 0xc00; i <= 0xc0c; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + j = 4; + for (i = 0xc80; i <= 0xc87; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + pr_dbg("\n vsb control is:"); /*vsb control */ + j = 4; + for (i = 0x900; i <= 0x905; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + j = 4; + for (i = 0x908; i <= 0x912; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + j = 4; + for (i = 0x917; i <= 0x91b; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + j = 4; + for (i = 0x980; i <= 0x992; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + pr_dbg("\n vsb demod is:"); /*vsb demod */ + j = 4; + for (i = 0x700; i <= 0x711; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + j = 4; + for (i = 0x716; i <= 0x720; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + j = 4; + for (i = 0x722; i <= 0x724; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + j = 4; + for (i = 0x726; i <= 0x72c; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + j = 4; + for (i = 0x730; i <= 0x732; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + j = 4; + for (i = 0x735; i <= 0x751; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + j = 4; + for (i = 0x780; i <= 0x795; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + j = 4; + for (i = 0x752; i <= 0x755; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + pr_dbg("\n vsb equalizer is:"); /*vsb equalizer */ + j = 4; + for (i = 0x501; i <= 0x5ff; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + pr_dbg("\n vsb fec is:"); /*vsb fec */ + j = 4; + for (i = 0x601; i <= 0x601; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + j = 4; + for (i = 0x682; i <= 0x685; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + pr_dbg("\n qam demod is:"); /*qam demod */ + j = 4; + for (i = 0x1; i <= 0x1a; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + j = 4; + for (i = 0x25; i <= 0x28; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + j = 4; + for (i = 0x101; i <= 0x10b; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + j = 4; + for (i = 0x206; i <= 0x207; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + pr_dbg("\n qam equalize is:"); /*qam equalize */ + j = 4; + for (i = 0x200; i <= 0x23d; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + j = 4; + for (i = 0x260; i <= 0x275; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + pr_dbg("\n qam fec is:"); /*qam fec */ + j = 4; + for (i = 0x400; i <= 0x418; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + pr_dbg("\n system mpeg formatter is:"); /*system mpeg formatter */ + j = 4; + for (i = 0xf00; i <= 0xf09; i++) { + data = atsc_read_reg(i); + if (j == 4) { + pr_dbg("\n[addr:0x%x]", i); + j = 0; + } + pr_dbg("%02x ", data); + j++; + } + pr_dbg("\n\n"); + return 0; +#endif +} + +int check_atsc_fsm_status(void) +{ + int SNR; + int atsc_snr = 0; + int SNR_dB; + int SNR_table[56] = { 0, 7, 9, 11, 14, + 17, + 22, + 27, 34, 43, 54, + 68, 86, 108, 136, 171, + 215, + 271, 341, + 429, 540, + 566, 592, 620, 649, 680, + 712, + 746, 781, + 818, 856, + 896, 939, 983, 1029, 1078, + 1182, + 1237, + 1237, 1296, 1357, + 1708, 2150, 2707, 3408, 4291, + 5402, + 6800, + 8561, 10778, 13568, + 16312, 17081, 18081, 19081, 65536 + }; + int SNR_dB_table[56] = { 360, 350, 340, 330, 320, 310, 300, + 290, + 280, + 270, 260, + 250, 240, 230, 220, 210, 200, 190, + 180, + 170, + 160, + 158, 156, 154, 152, 150, 148, 146, + 144, + 142, + 140, + 138, 136, 134, 132, 130, 128, 126, + 124, + 122, + 120, + 110, 100, 90, 80, 70, 60, 50, + 40, + 30, + 20, + 12, 10, 4, 2, 0 + }; + + int tmp[3]; + int cr; + int ck; + int SM; + int tni; + int ber; + int per; + + int cnt; + + cnt = 0; + ber = 0; + per = 0; + +/* g_demod_mode = 2; */ + tni = atsc_read_reg((0x08) >> 16); +/* g_demod_mode = 4; */ + tmp[0] = atsc_read_reg(0x0511); + tmp[1] = atsc_read_reg(0x0512); + SNR = (tmp[0] << 8) + tmp[1]; + SNR_dB = SNR_dB_table[find_2(SNR, SNR_table, 56)]; + + tmp[0] = atsc_read_reg(0x0780); + tmp[1] = atsc_read_reg(0x0781); + tmp[2] = atsc_read_reg(0x0782); + cr = tmp[0] + (tmp[1] << 8) + (tmp[2] << 16); + tmp[0] = atsc_read_reg(0x0786); + tmp[1] = atsc_read_reg(0x0787); + tmp[2] = atsc_read_reg(0x0788); + ck = (tmp[0] << 16) + (tmp[1] << 8) + tmp[2]; + ck = (ck > 8388608) ? ck - 16777216 : ck; + SM = atsc_read_reg(0x0980); +/* ber per */ + atsc_write_reg(0x0601, atsc_read_reg(0x0601) & (~(1 << 3))); + atsc_write_reg(0x0601, atsc_read_reg(0x0601) | (1 << 3)); + ber = atsc_read_reg(0x0683) + (atsc_read_reg(0x0682) << 8); + per = atsc_read_reg(0x0685) + (atsc_read_reg(0x0684) << 8); + +/* read_atsc_all_reg(); */ + + pr_dbg + ("INT %x SNR %x SNRdB %d.%d FSM %x cr %d ck %d", + tni, SNR, (SNR_dB / 10) + , (SNR_dB - (SNR_dB / 10) * 10) + , SM, cr, ck); + pr_dbg + ("ber is %d, per is %d\n", + ber, per); + + atsc_snr = (SNR_dB / 10); + return atsc_snr; + + /* unsigned long sm,snr1,snr2,snr; + * static int fec_lock_cnt = 0; + * + * delay_us(10000); + * sm = atsc_read_reg(0x0980); + * snr1 = atsc_read_reg(0x0511)&0xff; + * snr2 = atsc_read_reg(0x0512)&0xff; + * snr = (snr1 << 8) + snr2; + * + * printk(">>>>>>>>>>>>>>>>>>>>>>>>> + OFDM FSM %x SNR %x\n", sm&0xff, snr); + * + * if (sm == 0x79) stimulus_finish_pass(); + */ +} diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/dvbc_func.c b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/dvbc_func.c new file mode 100644 index 000000000000..8f10dccffd82 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/dvbc_func.c @@ -0,0 +1,1312 @@ +#include +#include +#include +#include +#include "demod_func.h" +#include + +static int debug_amldvbc = 1; +#define dprintk(a ...) do { if (debug_amldvbc) printk(a); } while (0) + +static struct task_struct *cci_task; +int cciflag; +struct timer_list mytimer; + +static void dvbc_cci_timer(unsigned long data) +{ +#if 0 + int count; + int maxCCI_p, re, im, j, i, times, maxCCI, sum, sum1, reg_0xf0, tmp1, + tmp, tmp2, reg_0xa8, reg_0xac; + int reg_0xa8_t, reg_0xac_t; + + count = 100; + if ((((apb_read_reg(QAM_BASE + 0x18)) & 0x1) == 1)) { + dprintk("[cci]lock "); + if (cciflag == 0) { + apb_write_reg(QAM_BASE + 0xa8, 0); + + cciflag = 0; + } + dprintk("\n"); + mdelay(500); + mod_timer(&mytimer, jiffies + 2 * HZ); + return; + } + if (cciflag == 1) { + dprintk("[cci]cciflag is 1,wait 20\n"); + mdelay(20000); + } + times = 300; + tmp = 0x2be2be3; + /*0x2ae4772; IF = 6M, fs = 35M, dec2hex(round(8*IF/fs*2^25)) */ + tmp2 = 0x2000; + tmp1 = 8; + reg_0xa8 = 0xc0000000; /* bypass CCI */ + reg_0xac = 0xc0000000; /* bypass CCI */ + + maxCCI = 0; + maxCCI_p = 0; + for (i = 0; i < times; i++) { + /*reg_0xa8 = app_apb_read_reg(0xa8); */ + reg_0xa8_t = reg_0xa8 + tmp + i * tmp2; + apb_write_reg(QAM_BASE + 0xa8, reg_0xa8_t); + reg_0xac_t = reg_0xac + tmp - i * tmp2; + apb_write_reg(QAM_BASE + 0xac, reg_0xac_t); + sum = 0; + sum1 = 0; + for (j = 0; j < tmp1; j++) { + /* msleep(20); */ + /* mdelay(20); */ + reg_0xf0 = apb_read_reg(QAM_BASE + 0xf0); + re = (reg_0xf0 >> 24) & 0xff; + im = (reg_0xf0 >> 16) & 0xff; + if (re > 127) + /*re = re - 256; */ + re = 256 - re; + if (im > 127) + /*im = im - 256; */ + im = 256 - im; + + sum += re + im; + re = (reg_0xf0 >> 8) & 0xff; + im = (reg_0xf0 >> 0) & 0xff; + if (re > 127) + /*re = re - 256; */ + re = 256 - re; + if (im > 127) + /*im = im - 256; */ + im = 256 - im; + + sum1 += re + im; + } + sum = sum / tmp1; + sum1 = sum1 / tmp1; + if (sum1 > sum) { + sum = sum1; + reg_0xa8_t = reg_0xac_t; + } + if (sum > maxCCI) { + maxCCI = sum; + if (maxCCI > 24) + maxCCI_p = reg_0xa8_t & 0x7fffffff; + } + if ((sum < 24) && (maxCCI_p > 0)) + break; /* stop CCI detect. */ + } + + if (maxCCI_p > 0) { + apb_write_reg(QAM_BASE + 0xa8, maxCCI_p & 0x7fffffff); + /* enable CCI */ + apb_write_reg(QAM_BASE + 0xac, maxCCI_p & 0x7fffffff); + /* enable CCI */ + /* if(dvbc.mode == 4) // 256QAM */ + apb_write_reg(QAM_BASE + 0x54, 0xa25705fa); + /**/ cciflag = 1; + mdelay(1000); + } else { + dprintk + ("[cci] ------------ find NO CCI -------------------\n"); + cciflag = 0; + } + + dprintk("[cci][%s]--------------------------\n", __func__); + mod_timer(&mytimer, jiffies + 2 * HZ); + return; +/* }*/ +#endif +} + +int dvbc_timer_init(void) +{ + dprintk("%s\n", __func__); + setup_timer(&mytimer, dvbc_cci_timer, (unsigned long)"Hello, world!"); + mytimer.expires = jiffies + 2 * HZ; + add_timer(&mytimer); + return 0; +} + +void dvbc_timer_exit(void) +{ + dprintk("%s\n", __func__); + del_timer(&mytimer); +} + +int dvbc_cci_task(void *data) +{ + int count; + int maxCCI_p, re, im, j, i, times, maxCCI, sum, sum1, reg_0xf0, tmp1, + tmp, tmp2, reg_0xa8, reg_0xac; + int reg_0xa8_t, reg_0xac_t; + + count = 100; + while (1) { + msleep(200); + if ((((apb_read_reg(QAM_BASE + 0x18)) & 0x1) == 1)) { + dprintk("[cci]lock "); + if (cciflag == 0) { + apb_write_reg(QAM_BASE + 0xa8, 0); + apb_write_reg(QAM_BASE + 0xac, 0); + dprintk("no cci "); + cciflag = 0; + } + dprintk("\n"); + msleep(500); + continue; + } + + if (cciflag == 1) { + dprintk("[cci]cciflag is 1,wait 20\n"); + msleep(20000); + } + times = 300; + tmp = 0x2be2be3; + /*0x2ae4772; IF = 6M,fs = 35M, dec2hex(round(8*IF/fs*2^25)) */ + tmp2 = 0x2000; + tmp1 = 8; + reg_0xa8 = 0xc0000000; /* bypass CCI */ + reg_0xac = 0xc0000000; /* bypass CCI */ + + maxCCI = 0; + maxCCI_p = 0; + for (i = 0; i < times; i++) { + /*reg_0xa8 = app_apb_read_reg(0xa8); */ + reg_0xa8_t = reg_0xa8 + tmp + i * tmp2; + apb_write_reg(QAM_BASE + 0xa8, reg_0xa8_t); + reg_0xac_t = reg_0xac + tmp - i * tmp2; + apb_write_reg(QAM_BASE + 0xac, reg_0xac_t); + sum = 0; + sum1 = 0; + for (j = 0; j < tmp1; j++) { + /* msleep(1); */ + reg_0xf0 = apb_read_reg(QAM_BASE + 0xf0); + re = (reg_0xf0 >> 24) & 0xff; + im = (reg_0xf0 >> 16) & 0xff; + if (re > 127) + /*re = re - 256; */ + re = 256 - re; + if (im > 127) + /*im = im - 256; */ + im = 256 - im; + + sum += re + im; + + re = (reg_0xf0 >> 8) & 0xff; + im = (reg_0xf0 >> 0) & 0xff; + if (re > 127) + /*re = re - 256; */ + re = 256 - re; + if (im > 127) + /*im = im - 256; */ + im = 256 - im; + + sum1 += re + im; + } + sum = sum / tmp1; + sum1 = sum1 / tmp1; + if (sum1 > sum) { + sum = sum1; + reg_0xa8_t = reg_0xac_t; + } + if (sum > maxCCI) { + maxCCI = sum; + if (maxCCI > 24) + maxCCI_p = reg_0xa8_t & 0x7fffffff; + } + + if ((sum < 24) && (maxCCI_p > 0)) + break; /* stop CCI detect. */ + } + + if (maxCCI_p > 0) { + apb_write_reg(QAM_BASE + 0xa8, maxCCI_p & 0x7fffffff); + /* enable CCI */ + apb_write_reg(QAM_BASE + 0xac, maxCCI_p & 0x7fffffff); + /* enable CCI */ + /* if(dvbc.mode == 4) // 256QAM */ + apb_write_reg(QAM_BASE + 0x54, 0xa25705fa); + /**/ cciflag = 1; + msleep(1000); + } else { + cciflag = 0; + } + + dprintk("[cci][%s]--------------------------\n", __func__); + } + return 0; +} + +int dvbc_get_cci_task(void) +{ + if (cci_task) + return 0; + else + return 1; +} + +void dvbc_create_cci_task(void) +{ + int ret; + + /*apb_write_reg(QAM_BASE+0xa8, 0x42b2ebe3); // enable CCI */ + /* apb_write_reg(QAM_BASE+0xac, 0x42b2ebe3); // enable CCI */ +/* if(dvbc.mode == 4) // 256QAM*/ + /* apb_write_reg(QAM_BASE+0x54, 0xa25705fa); // */ + ret = 0; + cci_task = kthread_create(dvbc_cci_task, NULL, "cci_task"); + if (ret != 0) { + dprintk("[%s]Create cci kthread error!\n", __func__); + cci_task = NULL; + return; + } + wake_up_process(cci_task); + dprintk("[%s]Create cci kthread and wake up!\n", __func__); +} + +void dvbc_kill_cci_task(void) +{ + if (cci_task) { + kthread_stop(cci_task); + cci_task = NULL; + dprintk("[%s]kill cci kthread !\n", __func__); + } +} + +u32 dvbc_set_qam_mode(unsigned char mode) +{ + dprintk("auto change mode ,now mode is %d\n", mode); + apb_write_reg(QAM_BASE + 0x008, (mode & 7)); + /* qam mode */ + switch (mode) { + case 0: /* 16 QAM */ + apb_write_reg(QAM_BASE + 0x054, 0x23460224); + /* EQ_FIR_CTL, */ + apb_write_reg(QAM_BASE + 0x068, 0x00c000c0); + /* EQ_CRTH_SNR */ + apb_write_reg(QAM_BASE + 0x074, 0x50001a0); + /* EQ_TH_LMS 40db 13db */ + apb_write_reg(QAM_BASE + 0x07c, 0x003001e9); + /* EQ_NORM and EQ_TH_MMA */ + /*apb_write_reg(QAM_BASE+0x080, 0x000be1ff); + * // EQ_TH_SMMA0 + */ + apb_write_reg(QAM_BASE + 0x080, 0x000e01fe); + /* EQ_TH_SMMA0 */ + apb_write_reg(QAM_BASE + 0x084, 0x00000000); + /* EQ_TH_SMMA1 */ + apb_write_reg(QAM_BASE + 0x088, 0x00000000); + /* EQ_TH_SMMA2 */ + apb_write_reg(QAM_BASE + 0x08c, 0x00000000); + /* EQ_TH_SMMA3 */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f800d2b); + * // AGC_CTRL ALPS tuner + */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f80292b); + * // Pilips Tuner + */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f80292d); + * // Pilips Tuner + */ + apb_write_reg(QAM_BASE + 0x094, 0x7f80092d); + /* Pilips Tuner */ + apb_write_reg(QAM_BASE + 0x0c0, 0x061f2f66); + /* by raymond 20121213 */ + break; + + case 1: /* 32 QAM */ + apb_write_reg(QAM_BASE + 0x054, 0x24560506); + /* EQ_FIR_CTL, */ + apb_write_reg(QAM_BASE + 0x068, 0x00c000c0); + /* EQ_CRTH_SNR */ + /*apb_write_reg(QAM_BASE+0x074, 0x5000260); + * // EQ_TH_LMS 40db 19db + */ + apb_write_reg(QAM_BASE + 0x074, 0x50001f0); + /* EQ_TH_LMS 40db 17.5db */ + apb_write_reg(QAM_BASE + 0x07c, 0x00500102); + /* EQ_TH_MMA 0x000001cc */ + apb_write_reg(QAM_BASE + 0x080, 0x00077140); + /* EQ_TH_SMMA0 */ + apb_write_reg(QAM_BASE + 0x084, 0x001fb000); + /* EQ_TH_SMMA1 */ + apb_write_reg(QAM_BASE + 0x088, 0x00000000); + /* EQ_TH_SMMA2 */ + apb_write_reg(QAM_BASE + 0x08c, 0x00000000); + /* EQ_TH_SMMA3 */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f800d2b); + * // AGC_CTRL ALPS tuner + */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f80292b); + * // Pilips Tuner + */ + apb_write_reg(QAM_BASE + 0x094, 0x7f80092b); + /* Pilips Tuner */ + apb_write_reg(QAM_BASE + 0x0c0, 0x061f2f66); + /* by raymond 20121213 */ + break; + + case 2: /* 64 QAM */ + /*apb_write_reg(QAM_BASE+0x054, 0x2256033a); + * // EQ_FIR_CTL, + */ + apb_write_reg(QAM_BASE + 0x054, 0x2336043a); + /* EQ_FIR_CTL, by raymond */ + apb_write_reg(QAM_BASE + 0x068, 0x00c000c0); + /* EQ_CRTH_SNR */ + /*apb_write_reg(QAM_BASE+0x074, 0x5000260); + * // EQ_TH_LMS 40db 19db + */ + apb_write_reg(QAM_BASE + 0x074, 0x5000230); + /* EQ_TH_LMS 40db 17.5db */ + apb_write_reg(QAM_BASE + 0x07c, 0x007001bd); + /* EQ_TH_MMA */ + apb_write_reg(QAM_BASE + 0x080, 0x000580ed); + /* EQ_TH_SMMA0 */ + apb_write_reg(QAM_BASE + 0x084, 0x001771fb); + /* EQ_TH_SMMA1 */ + apb_write_reg(QAM_BASE + 0x088, 0x00000000); + /* EQ_TH_SMMA2 */ + apb_write_reg(QAM_BASE + 0x08c, 0x00000000); + /* EQ_TH_SMMA3 */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f800d2c); + * // AGC_CTRL ALPS tuner + */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f80292c); + * // Pilips & maxlinear Tuner + */ + apb_write_reg(QAM_BASE + 0x094, 0x7f802b3d); + /* Pilips Tuner & maxlinear Tuner */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f802b3a); + * // Pilips Tuner & maxlinear Tuner + */ + apb_write_reg(QAM_BASE + 0x0c0, 0x061f2f66); + /* by raymond 20121213 */ + break; + + case 3: /* 128 QAM */ + /*apb_write_reg(QAM_BASE+0x054, 0x2557046a); + * // EQ_FIR_CTL, + */ + apb_write_reg(QAM_BASE + 0x054, 0x2437067a); + /* EQ_FIR_CTL, by raymond 20121213 */ + apb_write_reg(QAM_BASE + 0x068, 0x00c000d0); + /* EQ_CRTH_SNR */ + /* apb_write_reg(QAM_BASE+0x074, 0x02440240); + * // EQ_TH_LMS 18.5db 18db + */ + /* apb_write_reg(QAM_BASE+0x074, 0x04000400); + * // EQ_TH_LMS 22db 22.5db + */ + apb_write_reg(QAM_BASE + 0x074, 0x5000260); + /* EQ_TH_LMS 40db 19db */ + /*apb_write_reg(QAM_BASE+0x07c, 0x00b000f2); + * // EQ_TH_MMA0x000000b2 + */ + apb_write_reg(QAM_BASE + 0x07c, 0x00b00132); + /* EQ_TH_MMA0x000000b2 by raymond 20121213 */ + apb_write_reg(QAM_BASE + 0x080, 0x0003a09d); + /* EQ_TH_SMMA0 */ + apb_write_reg(QAM_BASE + 0x084, 0x000f8150); + /* EQ_TH_SMMA1 */ + apb_write_reg(QAM_BASE + 0x088, 0x001a51f8); + /* EQ_TH_SMMA2 */ + apb_write_reg(QAM_BASE + 0x08c, 0x00000000); + /* EQ_TH_SMMA3 */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f800d2c); + * // AGC_CTRL ALPS tuner + */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f80292c); + * // Pilips Tuner + */ + apb_write_reg(QAM_BASE + 0x094, 0x7f80092c); + /* Pilips Tuner */ + apb_write_reg(QAM_BASE + 0x0c0, 0x061f2f66); + /* by raymond 20121213 */ + break; + + case 4: /* 256 QAM */ + /*apb_write_reg(QAM_BASE+0x054, 0xa2580588); + * // EQ_FIR_CTL, + */ + apb_write_reg(QAM_BASE + 0x054, 0xa25905f9); + /* EQ_FIR_CTL, by raymond 20121213 */ + apb_write_reg(QAM_BASE + 0x068, 0x01e00220); + /* EQ_CRTH_SNR */ + /*apb_write_reg(QAM_BASE+0x074, 0x50002a0); + * // EQ_TH_LMS 40db 19db + */ + apb_write_reg(QAM_BASE + 0x074, 0x5000270); + /* EQ_TH_LMS 40db 19db by raymond 201211213 */ + apb_write_reg(QAM_BASE + 0x07c, 0x00f001a5); + /* EQ_TH_MMA */ + apb_write_reg(QAM_BASE + 0x080, 0x0002c077); + /* EQ_TH_SMMA0 */ + apb_write_reg(QAM_BASE + 0x084, 0x000bc0fe); + /* EQ_TH_SMMA1 */ + apb_write_reg(QAM_BASE + 0x088, 0x0013f17e); + /* EQ_TH_SMMA2 */ + apb_write_reg(QAM_BASE + 0x08c, 0x01bc01f9); + /* EQ_TH_SMMA3 */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f800d2c); + * // AGC_CTRL ALPS tuner + */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f80292c); + * // Pilips Tuner + */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f80292d); + * // Maxlinear Tuner + */ + apb_write_reg(QAM_BASE + 0x094, 0x7f80092d); + /* Maxlinear Tuner */ + apb_write_reg(QAM_BASE + 0x0c0, 0x061f2f67); + /* by raymond 20121213, when adc=35M,sys=70M, + * its better than 0x61f2f66 + */ + break; + default: /*64qam */ + /*apb_write_reg(QAM_BASE+0x054, 0x2256033a); + * // EQ_FIR_CTL, + */ + apb_write_reg(QAM_BASE + 0x054, 0x2336043a); + /* EQ_FIR_CTL, by raymond */ + apb_write_reg(QAM_BASE + 0x068, 0x00c000c0); + /* EQ_CRTH_SNR */ + /*apb_write_reg(QAM_BASE+0x074, 0x5000260); + * // EQ_TH_LMS 40db 19db + */ + apb_write_reg(QAM_BASE + 0x074, 0x5000230); + /* EQ_TH_LMS 40db 17.5db */ + apb_write_reg(QAM_BASE + 0x07c, 0x007001bd); + /* EQ_TH_MMA */ + apb_write_reg(QAM_BASE + 0x080, 0x000580ed); + /* EQ_TH_SMMA0 */ + apb_write_reg(QAM_BASE + 0x084, 0x001771fb); + /* EQ_TH_SMMA1 */ + apb_write_reg(QAM_BASE + 0x088, 0x00000000); + /* EQ_TH_SMMA2 */ + apb_write_reg(QAM_BASE + 0x08c, 0x00000000); + /* EQ_TH_SMMA3 */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f800d2c); + * // AGC_CTRL ALPS tuner + */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f80292c); + * // Pilips & maxlinear Tuner + */ + apb_write_reg(QAM_BASE + 0x094, 0x7f802b3d); + /* Pilips Tuner & maxlinear Tuner */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f802b3a); + * // Pilips Tuner & maxlinear Tuner + */ + apb_write_reg(QAM_BASE + 0x0c0, 0x061f2f66); + /* by raymond 20121213 */ + break; + } + return 0; +} + +u32 dvbc_get_status(void) +{ +/* dprintk("c4 is %x\n",apb_read_reg(QAM_BASE+0xc4));*/ + return apb_read_reg(QAM_BASE + 0xc4) & 0xf; +} +EXPORT_SYMBOL(dvbc_get_status); + +static u32 dvbc_get_ch_power(void) +{ + u32 tmp; + u32 ad_power; + u32 agc_gain; + u32 ch_power; + + tmp = apb_read_reg(QAM_BASE + 0x09c); + + ad_power = (tmp >> 22) & 0x1ff; + agc_gain = (tmp >> 0) & 0x7ff; + + ad_power = ad_power >> 4; + /* ch_power = lookuptable(agc_gain) + ad_power; TODO */ + ch_power = (ad_power & 0xffff) + ((agc_gain & 0xffff) << 16); + + return ch_power; +} + +static u32 dvbc_get_snr(void) +{ + u32 tmp, snr; + + tmp = apb_read_reg(QAM_BASE + 0x14) & 0xfff; + snr = tmp * 100 / 32; /* * 1e2 */ + + return snr; +} + +static u32 dvbc_get_ber(void) +{ + u32 rs_ber; + u32 rs_packet_len; + + rs_packet_len = apb_read_reg(QAM_BASE + 0x10) & 0xffff; + rs_ber = apb_read_reg(QAM_BASE + 0x14) >> 12 & 0xfffff; + + /* rs_ber = rs_ber / 204.0 / 8.0 / rs_packet_len; */ + if (rs_packet_len == 0) + rs_ber = 1000000; + else + rs_ber = rs_ber * 613 / rs_packet_len; /* 1e-6 */ + + return rs_ber; +} + +static u32 dvbc_get_per(void) +{ + u32 rs_per; + u32 rs_packet_len; + u32 acc_rs_per_times; + + rs_packet_len = apb_read_reg(QAM_BASE + 0x10) & 0xffff; + rs_per = apb_read_reg(QAM_BASE + 0x18) >> 16 & 0xffff; + + acc_rs_per_times = apb_read_reg(QAM_BASE + 0xcc) & 0xffff; + /*rs_per = rs_per / rs_packet_len; */ + + if (rs_packet_len == 0) + rs_per = 10000; + else + rs_per = 10000 * rs_per / rs_packet_len; /* 1e-4 */ + + /*return rs_per; */ + return acc_rs_per_times; +} + +static u32 dvbc_get_symb_rate(void) +{ + u32 tmp; + u32 adc_freq; + u32 symb_rate; + + adc_freq = apb_read_reg(QAM_BASE + 0x34) >> 16 & 0xffff; + tmp = apb_read_reg(QAM_BASE + 0xb8); + + if ((tmp >> 15) == 0) + symb_rate = 0; + else + symb_rate = 10 * (adc_freq << 12) / (tmp >> 15); + /* 1e4 */ + + return symb_rate; +} + +static int dvbc_get_freq_off(void) +{ + int tmp; + int symb_rate; + int freq_off; + + symb_rate = dvbc_get_symb_rate(); + tmp = apb_read_reg(QAM_BASE + 0xe0) & 0x3fffffff; + if (tmp >> 29 & 1) + tmp -= (1 << 30); + + freq_off = ((tmp >> 16) * 25 * (symb_rate >> 10)) >> 3; + + return freq_off; +} + +static void dvbc_set_test_bus(u8 sel) +{ + u32 tmp; + + tmp = apb_read_reg(QAM_BASE + 0x08); + tmp &= ~(0x1f << 4); + tmp |= ((sel & 0x1f) << 4) | (1 << 3); + apb_write_reg(QAM_BASE + 0x08, tmp); +} + +void dvbc_get_test_out(u8 sel, u32 len, u32 *buf) +{ + int i, cnt; + + dvbc_set_test_bus(sel); + + for (i = 0, cnt = 0; i < len - 4 && cnt < 1000000; i++) { + buf[i] = apb_read_reg(QAM_BASE + 0xb0); + if (buf[i] >> 11 & 1) { + buf[i++] = apb_read_reg(QAM_BASE + 0xb0); + buf[i++] = apb_read_reg(QAM_BASE + 0xb0); + buf[i++] = apb_read_reg(QAM_BASE + 0xb0); + buf[i++] = apb_read_reg(QAM_BASE + 0xb0); + } else { + i--; + } + + cnt++; + } +} + +#if 0 +static void dvbc_sw_reset(int addr, int idx) +{ + u32 tmp; + + tmp = apb_read_reg(QAM_BASE + addr); + + tmp &= ~(1 << idx); + apb_write_reg(QAM_BASE + addr, tmp); + + udelay(1); + + tmp |= (1 << idx); + apb_write_reg(QAM_BASE + addr, tmp); +} + +static void dvbc_reset(void) +{ + dvbc_sw_reset(0x04, 0); +} + +static void dvbc_eq_reset(void) +{ + dvbc_sw_reset(0x50, 3); +} + +static void dvbc_eq_smma_reset(void) +{ + dvbc_sw_reset(0xe8, 0); +} +#endif +static void dvbc_reg_initial(struct aml_demod_sta *demod_sta) +{ + u32 clk_freq; + u32 adc_freq; + u8 tuner; + u8 ch_mode; + u8 agc_mode; + u32 ch_freq; + u16 ch_if; + u16 ch_bw; + u16 symb_rate; + u32 phs_cfg; + int afifo_ctr; + int max_frq_off, tmp; + + clk_freq = demod_sta->clk_freq; /* kHz */ + adc_freq = demod_sta->adc_freq; /* kHz */ +/* adc_freq = 25414;*/ + tuner = demod_sta->tuner; + ch_mode = demod_sta->ch_mode; + agc_mode = demod_sta->agc_mode; + ch_freq = demod_sta->ch_freq; /* kHz */ + ch_if = demod_sta->ch_if; /* kHz */ + ch_bw = demod_sta->ch_bw; /* kHz */ + symb_rate = demod_sta->symb_rate; /* k/sec */ + dprintk("ch_if is %d, %d, %d, %d, %d\n", + ch_if, ch_mode, ch_freq, ch_bw, symb_rate); +/* ch_mode=4;*/ +/* apb_write_reg(DEMOD_CFG_BASE,0x00000007);*/ + /* disable irq */ + apb_write_reg(QAM_BASE + 0xd0, 0); + + /* reset */ + /*dvbc_reset(); */ + apb_write_reg(QAM_BASE + 0x4, apb_read_reg(QAM_BASE + 0x4) & ~(1 << 4)); + /* disable fsm_en */ + apb_write_reg(QAM_BASE + 0x4, apb_read_reg(QAM_BASE + 0x4) & ~(1 << 0)); + /* Sw disable demod */ + apb_write_reg(QAM_BASE + 0x4, apb_read_reg(QAM_BASE + 0x4) | (1 << 0)); + /* Sw enable demod */ + + apb_write_reg(QAM_BASE + 0x000, 0x00000000); + /* QAM_STATUS */ + apb_write_reg(QAM_BASE + 0x004, 0x00000f00); + /* QAM_GCTL0 */ + apb_write_reg(QAM_BASE + 0x008, (ch_mode & 7)); + /* qam mode */ + + switch (ch_mode) { + case 0: /* 16 QAM */ + apb_write_reg(QAM_BASE + 0x054, 0x23460224); + /* EQ_FIR_CTL, */ + apb_write_reg(QAM_BASE + 0x068, 0x00c000c0); + /* EQ_CRTH_SNR */ + apb_write_reg(QAM_BASE + 0x074, 0x50001a0); + /* EQ_TH_LMS 40db 13db */ + apb_write_reg(QAM_BASE + 0x07c, 0x003001e9); + /* EQ_NORM and EQ_TH_MMA */ + /*apb_write_reg(QAM_BASE+0x080, 0x000be1ff); + * // EQ_TH_SMMA0 + */ + apb_write_reg(QAM_BASE + 0x080, 0x000e01fe); + /* EQ_TH_SMMA0 */ + apb_write_reg(QAM_BASE + 0x084, 0x00000000); + /* EQ_TH_SMMA1 */ + apb_write_reg(QAM_BASE + 0x088, 0x00000000); + /* EQ_TH_SMMA2 */ + apb_write_reg(QAM_BASE + 0x08c, 0x00000000); + /* EQ_TH_SMMA3 */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f800d2b); + * // AGC_CTRL ALPS tuner + */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f80292b); + * // Pilips Tuner + */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f80292d); + * // Pilips Tuner + */ + apb_write_reg(QAM_BASE + 0x094, 0x7f80092d); + /* Pilips Tuner */ + apb_write_reg(QAM_BASE + 0x0c0, 0x061f2f67); + /* by raymond 20121213 */ + break; + + case 1: /* 32 QAM */ + apb_write_reg(QAM_BASE + 0x054, 0x24560506); + /* EQ_FIR_CTL, */ + apb_write_reg(QAM_BASE + 0x068, 0x00c000c0); + /* EQ_CRTH_SNR */ + /*apb_write_reg(QAM_BASE+0x074, 0x5000260); + * // EQ_TH_LMS 40db 19db + */ + apb_write_reg(QAM_BASE + 0x074, 0x50001f0); + /* EQ_TH_LMS 40db 17.5db */ + apb_write_reg(QAM_BASE + 0x07c, 0x00500102); + /* EQ_TH_MMA 0x000001cc */ + apb_write_reg(QAM_BASE + 0x080, 0x00077140); + /* EQ_TH_SMMA0 */ + apb_write_reg(QAM_BASE + 0x084, 0x001fb000); + /* EQ_TH_SMMA1 */ + apb_write_reg(QAM_BASE + 0x088, 0x00000000); + /* EQ_TH_SMMA2 */ + apb_write_reg(QAM_BASE + 0x08c, 0x00000000); + /* EQ_TH_SMMA3 */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f800d2b); + * // AGC_CTRL ALPS tuner + */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f80292b); + * // Pilips Tuner + */ + apb_write_reg(QAM_BASE + 0x094, 0x7f80092b); + /* Pilips Tuner */ + apb_write_reg(QAM_BASE + 0x0c0, 0x061f2f67); + /* by raymond 20121213 */ + break; + + case 2: /* 64 QAM */ + /*apb_write_reg(QAM_BASE+0x054, 0x2256033a); + * // EQ_FIR_CTL, + */ + apb_write_reg(QAM_BASE + 0x054, 0x2336043a); + /* EQ_FIR_CTL, by raymond */ + apb_write_reg(QAM_BASE + 0x068, 0x00c000c0); + /* EQ_CRTH_SNR */ + /*apb_write_reg(QAM_BASE+0x074, 0x5000260); + * // EQ_TH_LMS 40db 19db + */ + apb_write_reg(QAM_BASE + 0x074, 0x5000230); + /* EQ_TH_LMS 40db 17.5db */ + apb_write_reg(QAM_BASE + 0x07c, 0x007001bd); + /* EQ_TH_MMA */ + apb_write_reg(QAM_BASE + 0x080, 0x000580ed); + /* EQ_TH_SMMA0 */ + apb_write_reg(QAM_BASE + 0x084, 0x001771fb); + /* EQ_TH_SMMA1 */ + apb_write_reg(QAM_BASE + 0x088, 0x00000000); + /* EQ_TH_SMMA2 */ + apb_write_reg(QAM_BASE + 0x08c, 0x00000000); + /* EQ_TH_SMMA3 */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f800d2c); + * // AGC_CTRL ALPS tuner + */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f80292c); + * // Pilips & maxlinear Tuner + */ + apb_write_reg(QAM_BASE + 0x094, 0x7f802b3d); + /* Pilips Tuner & maxlinear Tuner */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f802b3a); + * // Pilips Tuner & maxlinear Tuner + */ + apb_write_reg(QAM_BASE + 0x0c0, 0x061f2f67); + /* by raymond 20121213 */ + break; + + case 3: /* 128 QAM */ + /*apb_write_reg(QAM_BASE+0x054, 0x2557046a); + * // EQ_FIR_CTL, + */ + apb_write_reg(QAM_BASE + 0x054, 0x2437067a); + /* EQ_FIR_CTL, by raymond 20121213 */ + apb_write_reg(QAM_BASE + 0x068, 0x00c000d0); + /* EQ_CRTH_SNR */ + /* apb_write_reg(QAM_BASE+0x074, 0x02440240); + * // EQ_TH_LMS 18.5db 18db + */ + /* apb_write_reg(QAM_BASE+0x074, 0x04000400); + * // EQ_TH_LMS 22db 22.5db + */ + apb_write_reg(QAM_BASE + 0x074, 0x5000260); + /* EQ_TH_LMS 40db 19db */ + /*apb_write_reg(QAM_BASE+0x07c, 0x00b000f2); + * // EQ_TH_MMA0x000000b2 + */ + apb_write_reg(QAM_BASE + 0x07c, 0x00b00132); + /* EQ_TH_MMA0x000000b2 by raymond 20121213 */ + apb_write_reg(QAM_BASE + 0x080, 0x0003a09d); + /* EQ_TH_SMMA0 */ + apb_write_reg(QAM_BASE + 0x084, 0x000f8150); + /* EQ_TH_SMMA1 */ + apb_write_reg(QAM_BASE + 0x088, 0x001a51f8); + /* EQ_TH_SMMA2 */ + apb_write_reg(QAM_BASE + 0x08c, 0x00000000); + /* EQ_TH_SMMA3 */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f800d2c); + * // AGC_CTRL ALPS tuner + */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f80292c); + * // Pilips Tuner + */ + apb_write_reg(QAM_BASE + 0x094, 0x7f80092c); + /* Pilips Tuner */ + apb_write_reg(QAM_BASE + 0x0c0, 0x061f2f67); + /* by raymond 20121213 */ + break; + + case 4: /* 256 QAM */ + /*apb_write_reg(QAM_BASE+0x054, 0xa2580588); + * // EQ_FIR_CTL, + */ + apb_write_reg(QAM_BASE + 0x054, 0xa25905f9); + /* EQ_FIR_CTL, by raymond 20121213 */ + apb_write_reg(QAM_BASE + 0x068, 0x01e00220); + /* EQ_CRTH_SNR */ + /*apb_write_reg(QAM_BASE+0x074, 0x50002a0); + * // EQ_TH_LMS 40db 19db + */ + apb_write_reg(QAM_BASE + 0x074, 0x5000270); + /* EQ_TH_LMS 40db 19db by raymond 201211213 */ + apb_write_reg(QAM_BASE + 0x07c, 0x00f001a5); + /* EQ_TH_MMA */ + apb_write_reg(QAM_BASE + 0x080, 0x0002c077); + /* EQ_TH_SMMA0 */ + apb_write_reg(QAM_BASE + 0x084, 0x000bc0fe); + /* EQ_TH_SMMA1 */ + apb_write_reg(QAM_BASE + 0x088, 0x0013f17e); + /* EQ_TH_SMMA2 */ + apb_write_reg(QAM_BASE + 0x08c, 0x01bc01f9); + /* EQ_TH_SMMA3 */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f800d2c); + * // AGC_CTRL ALPS tuner + */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f80292c); + * // Pilips Tuner + */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f80292d); + * // Maxlinear Tuner + */ + apb_write_reg(QAM_BASE + 0x094, 0x7f80092d); + /* Maxlinear Tuner */ + apb_write_reg(QAM_BASE + 0x0c0, 0x061f2f67); + /* by raymond 20121213, when adc=35M,sys=70M, + * its better than 0x61f2f66 + */ + break; + default: /*64qam */ + /*apb_write_reg(QAM_BASE+0x054, 0x2256033a); + * // EQ_FIR_CTL, + */ + apb_write_reg(QAM_BASE + 0x054, 0x2336043a); + /* EQ_FIR_CTL, by raymond */ + apb_write_reg(QAM_BASE + 0x068, 0x00c000c0); + /* EQ_CRTH_SNR */ + /* EQ_TH_LMS 40db 19db */ + apb_write_reg(QAM_BASE + 0x074, 0x5000230); + /* EQ_TH_LMS 40db 17.5db */ + apb_write_reg(QAM_BASE + 0x07c, 0x007001bd); + /* EQ_TH_MMA */ + apb_write_reg(QAM_BASE + 0x080, 0x000580ed); + /* EQ_TH_SMMA0 */ + apb_write_reg(QAM_BASE + 0x084, 0x001771fb); + /* EQ_TH_SMMA1 */ + apb_write_reg(QAM_BASE + 0x088, 0x00000000); + /* EQ_TH_SMMA2 */ + apb_write_reg(QAM_BASE + 0x08c, 0x00000000); + /* EQ_TH_SMMA3 */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f800d2c); + * // AGC_CTRL ALPS tuner + */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f80292c); + * // Pilips & maxlinear Tuner + */ + apb_write_reg(QAM_BASE + 0x094, 0x7f802b3d); + /* Pilips Tuner & maxlinear Tuner */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f802b3a); + * // Pilips Tuner & maxlinear Tuner + */ + apb_write_reg(QAM_BASE + 0x0c0, 0x061f2f67); + /* by raymond 20121213 */ + break; + } + + /*apb_write_reg(QAM_BASE+0x00c, 0xfffffffe); + * // adc_cnt, symb_cnt + */ + apb_write_reg(QAM_BASE + 0x00c, 0xffff8ffe); + /* adc_cnt, symb_cnt by raymond 20121213 */ + if (clk_freq == 0) + afifo_ctr = 0; + else + afifo_ctr = (adc_freq * 256 / clk_freq) + 2; + if (afifo_ctr > 255) + afifo_ctr = 255; + apb_write_reg(QAM_BASE + 0x010, (afifo_ctr << 16) | 8000); + /* afifo, rs_cnt_cfg */ + + /*apb_write_reg(QAM_BASE+0x020, 0x21353e54); + * // PHS_reset & TIM_CTRO_ACCURATE sw_tim_select=0 + */ + /*apb_write_reg(QAM_BASE+0x020, 0x21b53e54); + * //modified by qiancheng + */ + apb_write_reg(QAM_BASE + 0x020, 0x61b53e54); + /*modified by qiancheng by raymond 20121208 0x63b53e54 for cci */ + /* apb_write_reg(QAM_BASE+0x020, 0x6192bfe2); + * //modifed by ligg 20130613 auto symb_rate scan + */ + if (adc_freq == 0) + phs_cfg = 0; + else + phs_cfg = (1 << 31) / adc_freq * ch_if / (1 << 8); + /* 8*fo/fs*2^20 fo=36.125, fs = 28.57114, = 21d775 */ + /* dprintk("phs_cfg = %x\n", phs_cfg); */ + apb_write_reg(QAM_BASE + 0x024, 0x4c000000 | (phs_cfg & 0x7fffff)); + /* PHS_OFFSET, IF offset, */ + + if (adc_freq == 0) { + max_frq_off = 0; + } else { + max_frq_off = (1 << 29) / symb_rate; + /* max_frq_off = (400KHz * 2^29) / + * (AD=28571 * symbol_rate=6875) + */ + tmp = 40000000 / adc_freq; + max_frq_off = tmp * max_frq_off; + } + dprintk("max_frq_off is %x,\n", max_frq_off); + apb_write_reg(QAM_BASE + 0x02c, max_frq_off & 0x3fffffff); + /* max frequency offset, by raymond 20121208 */ + + /*apb_write_reg(QAM_BASE+0x030, 0x011bf400); + * // TIM_CTL0 start speed is 0, when know symbol rate + */ + apb_write_reg(QAM_BASE + 0x030, 0x245cf451); + /*MODIFIED BY QIANCHENG */ +/* apb_write_reg(QAM_BASE+0x030, 0x245bf451); + * //modified by ligg 20130613 --auto symb_rate scan + */ + apb_write_reg(QAM_BASE + 0x034, + ((adc_freq & 0xffff) << 16) | (symb_rate & 0xffff)); + + apb_write_reg(QAM_BASE + 0x038, 0x00400000); + /* TIM_SWEEP_RANGE 16000 */ + +/************* hw state machine config **********/ + apb_write_reg(QAM_BASE + 0x040, 0x003c); +/* configure symbol rate step step 0*/ + + /* modified 0x44 0x48 */ + apb_write_reg(QAM_BASE + 0x044, (symb_rate & 0xffff) * 256); + /* blind search, configure max symbol_rate for 7218 fb=3.6M */ + /*apb_write_reg(QAM_BASE+0x048, 3600*256); + * // configure min symbol_rate fb = 6.95M + */ + apb_write_reg(QAM_BASE + 0x048, 3400 * 256); + /* configure min symbol_rate fb = 6.95M */ + + /*apb_write_reg(QAM_BASE+0x0c0, 0xffffff68); // threshold */ + /*apb_write_reg(QAM_BASE+0x0c0, 0xffffff6f); // threshold */ + /*apb_write_reg(QAM_BASE+0x0c0, 0xfffffd68); // threshold */ + /*apb_write_reg(QAM_BASE+0x0c0, 0xffffff68); // threshold */ + /*apb_write_reg(QAM_BASE+0x0c0, 0xffffff68); // threshold */ + /*apb_write_reg(QAM_BASE+0x0c0, 0xffff2f67); + * // threshold for skyworth + */ + /* apb_write_reg(QAM_BASE+0x0c0, 0x061f2f67); // by raymond 20121208 */ + /* apb_write_reg(QAM_BASE+0x0c0, 0x061f2f66); + * // by raymond 20121213, remove it to every constellation + */ +/************* hw state machine config **********/ + + apb_write_reg(QAM_BASE + 0x04c, 0x00008800); /* reserved */ + + /*apb_write_reg(QAM_BASE+0x050, 0x00000002); // EQ_CTL0 */ + apb_write_reg(QAM_BASE + 0x050, 0x01472002); + /* EQ_CTL0 by raymond 20121208 */ + + /*apb_write_reg(QAM_BASE+0x058, 0xff550e1e); // EQ_FIR_INITPOS */ + apb_write_reg(QAM_BASE + 0x058, 0xff100e1e); + /* EQ_FIR_INITPOS for skyworth */ + + apb_write_reg(QAM_BASE + 0x05c, 0x019a0000); /* EQ_FIR_INITVAL0 */ + apb_write_reg(QAM_BASE + 0x060, 0x019a0000); /* EQ_FIR_INITVAL1 */ + + /*apb_write_reg(QAM_BASE+0x064, 0x01101128); // EQ_CRTH_TIMES */ + apb_write_reg(QAM_BASE + 0x064, 0x010a1128); + /* EQ_CRTH_TIMES for skyworth */ + apb_write_reg(QAM_BASE + 0x06c, 0x00041a05); /* EQ_CRTH_PPM */ + + apb_write_reg(QAM_BASE + 0x070, 0xffb9aa01); /* EQ_CRLP */ + + /*apb_write_reg(QAM_BASE+0x090, 0x00020bd5); // agc control */ + apb_write_reg(QAM_BASE + 0x090, 0x00000bd5); /* agc control */ + + /* agc control */ + /* apb_write_reg(QAM_BASE+0x094, 0x7f800d2c);// AGC_CTRL ALPS tuner */ + /* apb_write_reg(QAM_BASE+0x094, 0x7f80292c); // Pilips Tuner */ + if ((agc_mode & 1) == 0) + /* freeze if agc */ + apb_write_reg(QAM_BASE + 0x094, + apb_read_reg(QAM_BASE + 0x94) | (0x1 << 10)); + if ((agc_mode & 2) == 0) { + /* IF control */ + /*freeze rf agc */ + apb_write_reg(QAM_BASE + 0x094, + apb_read_reg(QAM_BASE + 0x94) | (0x1 << 13)); + } + /*Maxlinear Tuner */ + /*apb_write_reg(QAM_BASE+0x094, 0x7f80292d); */ + apb_write_reg(QAM_BASE + 0x098, 0x9fcc8190); + /* AGC_IFGAIN_CTRL */ + /*apb_write_reg(QAM_BASE+0x0a0, 0x0e028c00); + * // AGC_RFGAIN_CTRL 0x0e020800 + */ + /*apb_write_reg(QAM_BASE+0x0a0, 0x0e03cc00); + * // AGC_RFGAIN_CTRL 0x0e020800 + */ + /*apb_write_reg(QAM_BASE+0x0a0, 0x0e028700); + * // AGC_RFGAIN_CTRL 0x0e020800 now + */ + /*apb_write_reg(QAM_BASE+0x0a0, 0x0e03cd00); + * // AGC_RFGAIN_CTRL 0x0e020800 + */ + /*apb_write_reg(QAM_BASE+0x0a0, 0x0603cd11); + * // AGC_RFGAIN_CTRL 0x0e020800 by raymond, + * if Adjcent channel test, maybe it need change.20121208 ad invert + */ + apb_write_reg(QAM_BASE + 0x0a0, 0x0603cd10); + /* AGC_RFGAIN_CTRL 0x0e020800 by raymond, + * if Adjcent channel test, maybe it need change. + * 20121208 ad invert,20130221, suit for two path channel. + */ + + apb_write_reg(QAM_BASE + 0x004, apb_read_reg(QAM_BASE + 0x004) | 0x33); + /* IMQ, QAM Enable */ + + /* start hardware machine */ + /*dvbc_sw_reset(0x004, 4); */ + apb_write_reg(QAM_BASE + 0x4, apb_read_reg(QAM_BASE + 0x4) | (1 << 4)); + apb_write_reg(QAM_BASE + 0x0e8, + (apb_read_reg(QAM_BASE + 0x0e8) | (1 << 2))); + + /* clear irq status */ + apb_read_reg(QAM_BASE + 0xd4); + + /* enable irq */ + apb_write_reg(QAM_BASE + 0xd0, 0x7fff << 3); + +/*auto track*/ + /* dvbc_set_auto_symtrack(); */ +} + +u32 dvbc_set_auto_symtrack(void) +{ + apb_write_reg(QAM_BASE + 0x030, 0x245bf45c); /*open track */ + apb_write_reg(QAM_BASE + 0x020, 0x61b2bf5c); + apb_write_reg(QAM_BASE + 0x044, (7000 & 0xffff) * 256); + apb_write_reg(QAM_BASE + 0x038, 0x00220000); + apb_write_reg(QAM_BASE + 0x4, apb_read_reg(QAM_BASE + 0x4) & ~(1 << 0)); + /* Sw disable demod */ + apb_write_reg(QAM_BASE + 0x4, apb_read_reg(QAM_BASE + 0x4) | (1 << 0)); + /* Sw enable demod */ + return 0; +} + +int dvbc_set_ch(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c, + struct aml_demod_dvbc *demod_dvbc) +{ + int ret = 0; + u16 symb_rate; + u8 mode; + u32 ch_freq; + + dprintk("f=%d, s=%d, q=%d\n", + demod_dvbc->ch_freq, demod_dvbc->symb_rate, demod_dvbc->mode); + demod_i2c->tuner = 7; + mode = demod_dvbc->mode; + symb_rate = demod_dvbc->symb_rate; + ch_freq = demod_dvbc->ch_freq; + if (mode > 4) { + dprintk("Error: Invalid QAM mode option %d\n", mode); + mode = 2; + ret = -1; + } + + if (symb_rate < 1000 || symb_rate > 7000) { + dprintk("Error: Invalid Symbol Rate option %d\n", symb_rate); + symb_rate = 6875; + ret = -1; + } + + if (ch_freq < 1000 || ch_freq > 900000) { + dprintk("Error: Invalid Channel Freq option %d\n", ch_freq); + ch_freq = 474000; + ret = -1; + } + /* if (ret != 0) return ret; */ + demod_sta->dvb_mode = 0; + demod_sta->ch_mode = mode; + /* 0:16, 1:32, 2:64, 3:128, 4:256 */ + demod_sta->agc_mode = 1; + /* 0:NULL, 1:IF, 2:RF, 3:both */ + demod_sta->ch_freq = ch_freq; + demod_sta->tuner = demod_i2c->tuner; + + if (demod_i2c->tuner == 1) + demod_sta->ch_if = 36130; /* TODO DCT tuner */ + else if (demod_i2c->tuner == 2) + demod_sta->ch_if = 4570; /* TODO Maxlinear tuner */ + else if (demod_i2c->tuner == 7) + /* demod_sta->ch_if = 5000; // TODO Si2176 tuner */ + + demod_sta->ch_bw = 8000; /* TODO */ + if (demod_sta->ch_if == 0) + demod_sta->ch_if = 5000; + demod_sta->symb_rate = symb_rate; + dvbc_reg_initial(demod_sta); + + return ret; +} + +int dvbc_status(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c, + struct aml_demod_sts *demod_sts) +{ + struct aml_fe_dev *dev; + +/* int ftmp, tmp; */ + dev = NULL; + demod_sts->ch_sts = apb_read_reg(QAM_BASE + 0x18); + demod_sts->ch_pow = dvbc_get_ch_power(); + demod_sts->ch_snr = dvbc_get_snr(); + demod_sts->ch_ber = dvbc_get_ber(); + demod_sts->ch_per = dvbc_get_per(); + demod_sts->symb_rate = dvbc_get_symb_rate(); + demod_sts->freq_off = dvbc_get_freq_off(); + /*demod_sts->dat0 = apb_read_reg(QAM_BASE+0x28); */ +/* demod_sts->dat0 = tuner_get_ch_power(demod_i2c);*/ + demod_sts->dat1 = tuner_get_ch_power(dev); +#if 0 + + ftmp = demod_sts->ch_sts; + dprintk("[dvbc debug] ch_sts is %x\n", ftmp); + ftmp = demod_sts->ch_snr; + ftmp /= 100; + dprintk("snr %d dB ", ftmp); + ftmp = demod_sts->ch_ber; + dprintk("ber %.d ", ftmp); + tmp = demod_sts->ch_per; + dprintk("per %d ", tmp); + ftmp = demod_sts->symb_rate; + dprintk("srate %.d ", ftmp); + ftmp = demod_sts->freq_off; + dprintk("freqoff %.d kHz ", ftmp); + tmp = demod_sts->dat1; + dprintk("strength %ddb 0xe0 status is %lu ,b4 status is %lu", tmp, + (apb_read_reg(QAM_BASE + 0xe0) & 0xffff), + (apb_read_reg(QAM_BASE + 0xb4) & 0xffff)); + dprintk("dagc_gain is %lu ", apb_read_reg(QAM_BASE + 0xa4) & 0x7f); + tmp = demod_sts->ch_pow; + dprintk("power is %ddb\n", (tmp & 0xffff)); + +#endif + + return 0; +} + +void dvbc_enable_irq(int dvbc_irq) +{ + u32 mask; + + /* clear status */ + apb_read_reg(QAM_BASE + 0xd4); + /* enable irq */ + mask = apb_read_reg(QAM_BASE + 0xd0); + mask |= (1 << dvbc_irq); + apb_write_reg(QAM_BASE + 0xd0, mask); +} + +void dvbc_disable_irq(int dvbc_irq) +{ + u32 mask; + + /* disable irq */ + mask = apb_read_reg(QAM_BASE + 0xd0); + mask &= ~(1 << dvbc_irq); + apb_write_reg(QAM_BASE + 0xd0, mask); + /* clear status */ + apb_read_reg(QAM_BASE + 0xd4); +} + +char *dvbc_irq_name[] = { + " ADC", + " Symbol", + " RS", + " In_Sync0", + " In_Sync1", + " In_Sync2", + " In_Sync3", + " In_Sync4", + "Out_Sync0", + "Out_Sync1", + "Out_Sync2", + "Out_Sync3", + "Out_Sync4", + "In_SyncCo", + "OutSyncCo", + " In_Dagc", + " Out_Dagc", + " Eq_Mode", + "RS_Uncorr" +}; + +void dvbc_isr(struct aml_demod_sta *demod_sta) +{ + u32 stat, mask; + int dvbc_irq; + + stat = apb_read_reg(QAM_BASE + 0xd4); + mask = apb_read_reg(QAM_BASE + 0xd0); + stat &= mask; + + for (dvbc_irq = 0; dvbc_irq < 20; dvbc_irq++) { + if (stat >> dvbc_irq & 1) { + if (demod_sta->debug) + dprintk("irq: dvbc %2d %s %8x\n", + dvbc_irq, dvbc_irq_name[dvbc_irq], + stat); + /* dvbc_disable_irq(dvbc_irq); */ + } + } +} + +int dvbc_isr_islock(void) +{ +#define IN_SYNC4_MASK (0x80) + + u32 stat, mask; + + stat = apb_read_reg(QAM_BASE + 0xd4); + apb_write_reg(QAM_BASE + 0xd4, 0); + mask = apb_read_reg(QAM_BASE + 0xd0); + stat &= mask; + + return (stat & IN_SYNC4_MASK) == IN_SYNC4_MASK; +} diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/dvbt_func.c b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/dvbt_func.c new file mode 100644 index 000000000000..b8515d888eda --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/dvbt_func.c @@ -0,0 +1,2169 @@ +#include +#include +#include +#include +#include "demod_func.h" + +static int debug_amldvbt; + +module_param(debug_amldvbt, int, 0644); +MODULE_PARM_DESC(debug_amldvbt, "turn on debugging (default: 0)"); +#define dprintk(args ...) do { if (debug_amldvbt) printk(args); } while (0) + +static int tuner_type = 3; + +static void set_ACF_coef(int ADsample, int bandwidth) +{ + if (ADsample == 45) { + /* Set ACF and IIREQ */ + if (bandwidth == 0) { + /*8M Hz */ + apb_write_reg(2, 0x2c, 0x255); /* ACF_STAGE1_A1 */ + apb_write_reg(2, 0x2d, 0x0B5); /* ACF_STAGE1_A2 */ + apb_write_reg(2, 0x2e, 0x091); /* ACF_STAGE1_B1 */ + apb_write_reg(2, 0x2f, 0x02E); /* ACF_STAGE1_GAIN */ + apb_write_reg(2, 0x30, 0x253); /* ACF_STAGE2_A1 */ + apb_write_reg(2, 0x31, 0x0CB); /* ACF_STAGE2_A2 */ + apb_write_reg(2, 0x32, 0x2CD); /* ACF_STAGE2_B1 */ + apb_write_reg(2, 0x33, 0x07C); /* ACF_STAGE2_GAIN */ + apb_write_reg(2, 0x34, 0x250); /* ACF_STAGE3_A1 */ + apb_write_reg(2, 0x35, 0x0E4); /* ACF_STAGE3_A2 */ + apb_write_reg(2, 0x36, 0x276); /* ACF_STAGE3_B1 */ + apb_write_reg(2, 0x37, 0x05D); /* ACF_STAGE3_GAIN */ + apb_write_reg(2, 0x38, 0x24D); /* ACF_STAGE4_A1 */ + apb_write_reg(2, 0x39, 0x0F3); /* ACF_STAGE4_A2 */ + apb_write_reg(2, 0x3a, 0x25E); /* ACF_STAGE4_B1 */ + apb_write_reg(2, 0x3b, 0x05A); /* ACF_STAGE4_GAIN */ + apb_write_reg(2, 0x3c, 0x24A); /* ACF_STAGE5_A1 */ + apb_write_reg(2, 0x3d, 0x0FD); /* ACF_STAGE5_A2 */ + apb_write_reg(2, 0x3e, 0x256); /* ACF_STAGE5_B1 */ + apb_write_reg(2, 0x3f, 0x04B); /* ACF_STAGE5_GAIN */ + + apb_write_reg(2, 0xfe, 0x000); + apb_write_reg(2, 0xff, 0x003effff); + apb_write_reg(2, 0xfe, 0x001); + apb_write_reg(2, 0xff, 0x003cefbe); + apb_write_reg(2, 0xfe, 0x002); + apb_write_reg(2, 0xff, 0x003adf7c); + apb_write_reg(2, 0xfe, 0x003); + apb_write_reg(2, 0xff, 0x0038bf39); + apb_write_reg(2, 0xfe, 0x004); + apb_write_reg(2, 0xff, 0x003696f5); + apb_write_reg(2, 0xfe, 0x005); + apb_write_reg(2, 0xff, 0x003466b0); + apb_write_reg(2, 0xfe, 0x006); + apb_write_reg(2, 0xff, 0x00322e69); + apb_write_reg(2, 0xfe, 0x007); + apb_write_reg(2, 0xff, 0x002fee21); + apb_write_reg(2, 0xfe, 0x008); + apb_write_reg(2, 0xff, 0x002dadd9); + apb_write_reg(2, 0xfe, 0x009); + apb_write_reg(2, 0xff, 0x002b6d91); + apb_write_reg(2, 0xfe, 0x00a); + apb_write_reg(2, 0xff, 0x00291d48); + apb_write_reg(2, 0xfe, 0x00b); + apb_write_reg(2, 0xff, 0x0026ccfe); + apb_write_reg(2, 0xfe, 0x00c); + apb_write_reg(2, 0xff, 0x00245cb2); + apb_write_reg(2, 0xfe, 0x00d); + apb_write_reg(2, 0xff, 0x0021d463); + apb_write_reg(2, 0xfe, 0x00e); + apb_write_reg(2, 0xff, 0x001f2410); + apb_write_reg(2, 0xfe, 0x00f); + apb_write_reg(2, 0xff, 0x001c3bb6); + apb_write_reg(2, 0xfe, 0x010); + apb_write_reg(2, 0xff, 0x00192b57); + apb_write_reg(2, 0xfe, 0x011); + apb_write_reg(2, 0xff, 0x0015e2f1); + apb_write_reg(2, 0xfe, 0x012); + apb_write_reg(2, 0xff, 0x00127285); + apb_write_reg(2, 0xfe, 0x013); + apb_write_reg(2, 0xff, 0x000eca14); + apb_write_reg(2, 0xfe, 0x014); + apb_write_reg(2, 0xff, 0x000ac99b); + apb_write_reg(2, 0xfe, 0x015); + apb_write_reg(2, 0xff, 0x00063913); + apb_write_reg(2, 0xfe, 0x016); + apb_write_reg(2, 0xff, 0x0000c073); + apb_write_reg(2, 0xfe, 0x017); + apb_write_reg(2, 0xff, 0x003a3fb4); + apb_write_reg(2, 0xfe, 0x018); + apb_write_reg(2, 0xff, 0x00347ecf); + apb_write_reg(2, 0xfe, 0x019); + apb_write_reg(2, 0xff, 0x002ff649); + apb_write_reg(2, 0xfe, 0x01a); + apb_write_reg(2, 0xff, 0x002a8dab); + apb_write_reg(2, 0xfe, 0x01b); + apb_write_reg(2, 0xff, 0x002444f0); + apb_write_reg(2, 0xfe, 0x01c); + apb_write_reg(2, 0xff, 0x001d0c1b); + apb_write_reg(2, 0xfe, 0x01d); + apb_write_reg(2, 0xff, 0x000fc300); + apb_write_reg(2, 0xfe, 0x01e); + apb_write_reg(2, 0xff, 0x000118ce); + apb_write_reg(2, 0xfe, 0x01f); + apb_write_reg(2, 0xff, 0x003c17c3); + apb_write_reg(2, 0xfe, 0x020); + apb_write_reg(2, 0xff, 0x00000751); + } else if (bandwidth == 1) { + /* 7Mhz */ + apb_write_reg(2, 0x2c, 0x24B); /* ACF_STAGE1_A1 */ + apb_write_reg(2, 0x2d, 0x0BD); /* ACF_STAGE1_A2 */ + apb_write_reg(2, 0x2e, 0x04B); /* ACF_STAGE1_B1 */ + apb_write_reg(2, 0x2f, 0x03E); /* ACF_STAGE1_GAIN */ + apb_write_reg(2, 0x30, 0x246); /* ACF_STAGE2_A1 */ + apb_write_reg(2, 0x31, 0x0D1); /* ACF_STAGE2_A2 */ + apb_write_reg(2, 0x32, 0x2A2); /* ACF_STAGE2_B1 */ + apb_write_reg(2, 0x33, 0x07C); /* ACF_STAGE2_GAIN */ + apb_write_reg(2, 0x34, 0x241); /* ACF_STAGE3_A1 */ + apb_write_reg(2, 0x35, 0x0E7); /* ACF_STAGE3_A2 */ + apb_write_reg(2, 0x36, 0x25B); /* ACF_STAGE3_B1 */ + apb_write_reg(2, 0x37, 0x05D); /* ACF_STAGE3_GAIN */ + apb_write_reg(2, 0x38, 0x23D); /* ACF_STAGE4_A1 */ + apb_write_reg(2, 0x39, 0x0F5); /* ACF_STAGE4_A2 */ + apb_write_reg(2, 0x3a, 0x248); /* ACF_STAGE4_B1 */ + apb_write_reg(2, 0x3b, 0x05A); /* ACF_STAGE4_GAIN */ + apb_write_reg(2, 0x3c, 0x23A); /* ACF_STAGE5_A1 */ + apb_write_reg(2, 0x3d, 0x0FD); /* ACF_STAGE5_A2 */ + apb_write_reg(2, 0x3e, 0x242); /* ACF_STAGE5_B1 */ + apb_write_reg(2, 0x3f, 0x04B); /* ACF_STAGE5_GAIN */ + apb_write_reg(2, 0xfe, 0x000); + apb_write_reg(2, 0xff, 0x003f07ff); + apb_write_reg(2, 0xfe, 0x001); + apb_write_reg(2, 0xff, 0x003cffbf); + apb_write_reg(2, 0xfe, 0x002); + apb_write_reg(2, 0xff, 0x003aef7e); + apb_write_reg(2, 0xfe, 0x003); + apb_write_reg(2, 0xff, 0x0038d73c); + apb_write_reg(2, 0xfe, 0x004); + apb_write_reg(2, 0xff, 0x0036b6f9); + apb_write_reg(2, 0xfe, 0x005); + apb_write_reg(2, 0xff, 0x003486b3); + apb_write_reg(2, 0xfe, 0x006); + apb_write_reg(2, 0xff, 0x00324e6d); + apb_write_reg(2, 0xfe, 0x007); + apb_write_reg(2, 0xff, 0x00300e25); + apb_write_reg(2, 0xfe, 0x008); + apb_write_reg(2, 0xff, 0x002dcddd); + apb_write_reg(2, 0xfe, 0x009); + apb_write_reg(2, 0xff, 0x002b8594); + apb_write_reg(2, 0xfe, 0x00a); + apb_write_reg(2, 0xff, 0x00292d4b); + apb_write_reg(2, 0xfe, 0x00b); + apb_write_reg(2, 0xff, 0x0026d500); + apb_write_reg(2, 0xfe, 0x00c); + apb_write_reg(2, 0xff, 0x00245cb3); + apb_write_reg(2, 0xfe, 0x00d); + apb_write_reg(2, 0xff, 0x0021cc62); + apb_write_reg(2, 0xfe, 0x00e); + apb_write_reg(2, 0xff, 0x001f0c0d); + apb_write_reg(2, 0xfe, 0x00f); + apb_write_reg(2, 0xff, 0x001c1bb3); + apb_write_reg(2, 0xfe, 0x010); + apb_write_reg(2, 0xff, 0x0018fb52); + apb_write_reg(2, 0xfe, 0x011); + apb_write_reg(2, 0xff, 0x0015b2eb); + apb_write_reg(2, 0xfe, 0x012); + apb_write_reg(2, 0xff, 0x00123a7f); + apb_write_reg(2, 0xfe, 0x013); + apb_write_reg(2, 0xff, 0x000e9a0e); + apb_write_reg(2, 0xfe, 0x014); + apb_write_reg(2, 0xff, 0x000a9995); + apb_write_reg(2, 0xfe, 0x015); + apb_write_reg(2, 0xff, 0x0006090d); + apb_write_reg(2, 0xfe, 0x016); + apb_write_reg(2, 0xff, 0x0000a06e); + apb_write_reg(2, 0xfe, 0x017); + apb_write_reg(2, 0xff, 0x003a57b3); + apb_write_reg(2, 0xfe, 0x018); + apb_write_reg(2, 0xff, 0x0034ded8); + apb_write_reg(2, 0xfe, 0x019); + apb_write_reg(2, 0xff, 0x00309659); + apb_write_reg(2, 0xfe, 0x01a); + apb_write_reg(2, 0xff, 0x002b75c4); + apb_write_reg(2, 0xfe, 0x01b); + apb_write_reg(2, 0xff, 0x0025350e); + apb_write_reg(2, 0xfe, 0x01c); + apb_write_reg(2, 0xff, 0x001dec37); + apb_write_reg(2, 0xfe, 0x01d); + apb_write_reg(2, 0xff, 0x00126b28); + apb_write_reg(2, 0xfe, 0x01e); + apb_write_reg(2, 0xff, 0x00031130); + apb_write_reg(2, 0xfe, 0x01f); + apb_write_reg(2, 0xff, 0x003cffec); + apb_write_reg(2, 0xfe, 0x020); + apb_write_reg(2, 0xff, 0x00000767); + } else if (bandwidth == 2) { + /* 6MHz */ + apb_write_reg(2, 0x2c, 0x240); /* ACF_STAGE1_A1 */ + apb_write_reg(2, 0x2d, 0x0C6); /* ACF_STAGE1_A2 */ + apb_write_reg(2, 0x2e, 0x3F9); /* ACF_STAGE1_B1 */ + apb_write_reg(2, 0x2f, 0x03E); /* ACF_STAGE1_GAIN */ + apb_write_reg(2, 0x30, 0x23A); /* ACF_STAGE2_A1 */ + apb_write_reg(2, 0x31, 0x0D7); /* ACF_STAGE2_A2 */ + apb_write_reg(2, 0x32, 0x27B); /* ACF_STAGE2_B1 */ + apb_write_reg(2, 0x33, 0x07C); /* ACF_STAGE2_GAIN */ + apb_write_reg(2, 0x34, 0x233); /* ACF_STAGE3_A1 */ + apb_write_reg(2, 0x35, 0x0EA); /* ACF_STAGE3_A2 */ + apb_write_reg(2, 0x36, 0x244); /* ACF_STAGE3_B1 */ + apb_write_reg(2, 0x37, 0x05D); /* ACF_STAGE3_GAIN */ + apb_write_reg(2, 0x38, 0x22F); /* ACF_STAGE4_A1 */ + apb_write_reg(2, 0x39, 0x0F6); /* ACF_STAGE4_A2 */ + apb_write_reg(2, 0x3a, 0x235); /* ACF_STAGE4_B1 */ + apb_write_reg(2, 0x3b, 0x05A); /* ACF_STAGE4_GAIN */ + apb_write_reg(2, 0x3c, 0x22B); /* ACF_STAGE5_A1 */ + apb_write_reg(2, 0x3d, 0x0FD); /* ACF_STAGE5_A2 */ + apb_write_reg(2, 0x3e, 0x231); /* ACF_STAGE5_B1 */ + apb_write_reg(2, 0x3f, 0x04B); /* ACF_STAGE5_GAIN */ + apb_write_reg(2, 0xfe, 0x000); + apb_write_reg(2, 0xff, 0x003f07ff); + apb_write_reg(2, 0xfe, 0x001); + apb_write_reg(2, 0xff, 0x003cffbf); + apb_write_reg(2, 0xfe, 0x002); + apb_write_reg(2, 0xff, 0x003aef7e); + apb_write_reg(2, 0xfe, 0x003); + apb_write_reg(2, 0xff, 0x0038d73c); + apb_write_reg(2, 0xfe, 0x004); + apb_write_reg(2, 0xff, 0x0036b6f8); + apb_write_reg(2, 0xfe, 0x005); + apb_write_reg(2, 0xff, 0x003486b3); + apb_write_reg(2, 0xfe, 0x006); + apb_write_reg(2, 0xff, 0x0032466c); + apb_write_reg(2, 0xfe, 0x007); + apb_write_reg(2, 0xff, 0x002ffe24); + apb_write_reg(2, 0xfe, 0x008); + apb_write_reg(2, 0xff, 0x002dadda); + apb_write_reg(2, 0xfe, 0x009); + apb_write_reg(2, 0xff, 0x002b5d90); + apb_write_reg(2, 0xfe, 0x00a); + apb_write_reg(2, 0xff, 0x0028fd45); + apb_write_reg(2, 0xfe, 0x00b); + apb_write_reg(2, 0xff, 0x002694f9); + apb_write_reg(2, 0xfe, 0x00c); + apb_write_reg(2, 0xff, 0x002414ab); + apb_write_reg(2, 0xfe, 0x00d); + apb_write_reg(2, 0xff, 0x00217458); + apb_write_reg(2, 0xfe, 0x00e); + apb_write_reg(2, 0xff, 0x001ea402); + apb_write_reg(2, 0xfe, 0x00f); + apb_write_reg(2, 0xff, 0x001ba3a5); + apb_write_reg(2, 0xfe, 0x010); + apb_write_reg(2, 0xff, 0x00187342); + apb_write_reg(2, 0xfe, 0x011); + apb_write_reg(2, 0xff, 0x00151ad9); + apb_write_reg(2, 0xfe, 0x012); + apb_write_reg(2, 0xff, 0x0011926b); + apb_write_reg(2, 0xfe, 0x013); + apb_write_reg(2, 0xff, 0x000dc9f6); + apb_write_reg(2, 0xfe, 0x014); + apb_write_reg(2, 0xff, 0x0009a178); + apb_write_reg(2, 0xfe, 0x015); + apb_write_reg(2, 0xff, 0x0004d8eb); + apb_write_reg(2, 0xfe, 0x016); + apb_write_reg(2, 0xff, 0x003f4045); + apb_write_reg(2, 0xfe, 0x017); + apb_write_reg(2, 0xff, 0x0038e785); + apb_write_reg(2, 0xfe, 0x018); + apb_write_reg(2, 0xff, 0x00337eab); + apb_write_reg(2, 0xfe, 0x019); + apb_write_reg(2, 0xff, 0x002f3e2d); + apb_write_reg(2, 0xfe, 0x01a); + apb_write_reg(2, 0xff, 0x002a1599); + apb_write_reg(2, 0xfe, 0x01b); + apb_write_reg(2, 0xff, 0x0023ace1); + apb_write_reg(2, 0xfe, 0x01c); + apb_write_reg(2, 0xff, 0x001b33fb); + apb_write_reg(2, 0xfe, 0x01d); + apb_write_reg(2, 0xff, 0x000cd29c); + apb_write_reg(2, 0xfe, 0x01e); + apb_write_reg(2, 0xff, 0x0001c0c1); + apb_write_reg(2, 0xfe, 0x01f); + apb_write_reg(2, 0xff, 0x003cefde); + apb_write_reg(2, 0xfe, 0x020); + apb_write_reg(2, 0xff, 0x0000076a); + } else { + /* 5MHz */ + apb_write_reg(2, 0x2c, 0x236); /* ACF_STAGE1_A1 */ + apb_write_reg(2, 0x2d, 0x0CE); /* ACF_STAGE1_A2 */ + apb_write_reg(2, 0x2e, 0x39A); /* ACF_STAGE1_B1 */ + apb_write_reg(2, 0x2f, 0x03E); /* ACF_STAGE1_GAIN */ + apb_write_reg(2, 0x30, 0x22F); /* ACF_STAGE2_A1 */ + apb_write_reg(2, 0x31, 0x0DE); /* ACF_STAGE2_A2 */ + apb_write_reg(2, 0x32, 0x257); /* ACF_STAGE2_B1 */ + apb_write_reg(2, 0x33, 0x07C); /* ACF_STAGE2_GAIN */ + apb_write_reg(2, 0x34, 0x227); /* ACF_STAGE3_A1 */ + apb_write_reg(2, 0x35, 0x0EE); /* ACF_STAGE3_A2 */ + apb_write_reg(2, 0x36, 0x230); /* ACF_STAGE3_B1 */ + apb_write_reg(2, 0x37, 0x05D); /* ACF_STAGE3_GAIN */ + apb_write_reg(2, 0x38, 0x222); /* ACF_STAGE4_A1 */ + apb_write_reg(2, 0x39, 0x0F8); /* ACF_STAGE4_A2 */ + apb_write_reg(2, 0x3a, 0x225); /* ACF_STAGE4_B1 */ + apb_write_reg(2, 0x3b, 0x05A); /* ACF_STAGE4_GAIN */ + apb_write_reg(2, 0x3c, 0x21E); /* ACF_STAGE5_A1 */ + apb_write_reg(2, 0x3d, 0x0FE); /* ACF_STAGE5_A2 */ + apb_write_reg(2, 0x3e, 0x222); /* ACF_STAGE5_B1 */ + apb_write_reg(2, 0x3f, 0x04B); /* ACF_STAGE5_GAIN */ + apb_write_reg(2, 0xfe, 0x000); + apb_write_reg(2, 0xff, 0x003effff); + apb_write_reg(2, 0xfe, 0x001); + apb_write_reg(2, 0xff, 0x003ce7bd); + apb_write_reg(2, 0xfe, 0x002); + apb_write_reg(2, 0xff, 0x003ac77a); + apb_write_reg(2, 0xfe, 0x003); + apb_write_reg(2, 0xff, 0x0038a737); + apb_write_reg(2, 0xfe, 0x004); + apb_write_reg(2, 0xff, 0x00367ef2); + apb_write_reg(2, 0xfe, 0x005); + apb_write_reg(2, 0xff, 0x00344eac); + apb_write_reg(2, 0xfe, 0x006); + apb_write_reg(2, 0xff, 0x00321e66); + apb_write_reg(2, 0xfe, 0x007); + apb_write_reg(2, 0xff, 0x002fee20); + apb_write_reg(2, 0xfe, 0x008); + apb_write_reg(2, 0xff, 0x002dbdda); + apb_write_reg(2, 0xfe, 0x009); + apb_write_reg(2, 0xff, 0x002b8d94); + apb_write_reg(2, 0xfe, 0x00a); + apb_write_reg(2, 0xff, 0x00295d4e); + apb_write_reg(2, 0xfe, 0x00b); + apb_write_reg(2, 0xff, 0x00272508); + apb_write_reg(2, 0xfe, 0x00c); + apb_write_reg(2, 0xff, 0x0024dcc0); + apb_write_reg(2, 0xfe, 0x00d); + apb_write_reg(2, 0xff, 0x00227475); + apb_write_reg(2, 0xfe, 0x00e); + apb_write_reg(2, 0xff, 0x001fe426); + apb_write_reg(2, 0xfe, 0x00f); + apb_write_reg(2, 0xff, 0x001d1bd1); + apb_write_reg(2, 0xfe, 0x010); + apb_write_reg(2, 0xff, 0x001a2374); + apb_write_reg(2, 0xfe, 0x011); + apb_write_reg(2, 0xff, 0x0016e311); + apb_write_reg(2, 0xfe, 0x012); + apb_write_reg(2, 0xff, 0x00136aa6); + apb_write_reg(2, 0xfe, 0x013); + apb_write_reg(2, 0xff, 0x000fba33); + apb_write_reg(2, 0xfe, 0x014); + apb_write_reg(2, 0xff, 0x000ba9b8); + apb_write_reg(2, 0xfe, 0x015); + apb_write_reg(2, 0xff, 0x0007092e); + apb_write_reg(2, 0xfe, 0x016); + apb_write_reg(2, 0xff, 0x0001988e); + apb_write_reg(2, 0xfe, 0x017); + apb_write_reg(2, 0xff, 0x003b37d0); + apb_write_reg(2, 0xfe, 0x018); + apb_write_reg(2, 0xff, 0x0035aef3); + apb_write_reg(2, 0xfe, 0x019); + apb_write_reg(2, 0xff, 0x00316673); + apb_write_reg(2, 0xfe, 0x01a); + apb_write_reg(2, 0xff, 0x002c45de); + apb_write_reg(2, 0xfe, 0x01b); + apb_write_reg(2, 0xff, 0x0025e527); + apb_write_reg(2, 0xfe, 0x01c); + apb_write_reg(2, 0xff, 0x001da444); + apb_write_reg(2, 0xfe, 0x01d); + apb_write_reg(2, 0xff, 0x000deaea); + apb_write_reg(2, 0xfe, 0x01e); + apb_write_reg(2, 0xff, 0x000178bf); + apb_write_reg(2, 0xfe, 0x01f); + apb_write_reg(2, 0xff, 0x003cb7d6); + apb_write_reg(2, 0xfe, 0x020); + apb_write_reg(2, 0xff, 0x00000765); + } + } else if (ADsample == 28) { + /* 28.5714 MHz Set ACF */ + if (bandwidth == 0) { + /*8M Hz */ + apb_write_reg(2, 0x2c, 0x2DB); /* ACF_STAGE1_A1 */ + apb_write_reg(2, 0x2d, 0x05B); /* ACF_STAGE1_A2 */ + apb_write_reg(2, 0x2e, 0x163); /* ACF_STAGE1_B1 */ + apb_write_reg(2, 0x2f, 0x00E); /* ACF_STAGE1_GAIN */ + apb_write_reg(2, 0x30, 0x2D5); /* ACF_STAGE2_A1 */ + apb_write_reg(2, 0x31, 0x08B); /* ACF_STAGE2_A2 */ + apb_write_reg(2, 0x32, 0x3BC); /* ACF_STAGE2_B1 */ + apb_write_reg(2, 0x33, 0x06D); /* ACF_STAGE2_GAIN */ + apb_write_reg(2, 0x34, 0x2CF); /* ACF_STAGE3_A1 */ + apb_write_reg(2, 0x35, 0x0BF); /* ACF_STAGE3_A2 */ + apb_write_reg(2, 0x36, 0x321); /* ACF_STAGE3_B1 */ + apb_write_reg(2, 0x37, 0x008); /* ACF_STAGE3_GAIN */ + apb_write_reg(2, 0x38, 0x2C9); /* ACF_STAGE4_A1 */ + apb_write_reg(2, 0x39, 0x0E3); /* ACF_STAGE4_A2 */ + apb_write_reg(2, 0x3a, 0x2EE); /* ACF_STAGE4_B1 */ + apb_write_reg(2, 0x3b, 0x058); /* ACF_STAGE4_GAIN */ + apb_write_reg(2, 0x3c, 0x2C3); /* ACF_STAGE5_A1 */ + apb_write_reg(2, 0x3d, 0x0F8); /* ACF_STAGE5_A2 */ + apb_write_reg(2, 0x3e, 0x2DD); /* ACF_STAGE5_B1 */ + apb_write_reg(2, 0x3f, 0x04D); /* ACF_STAGE5_GAIN */ + + apb_write_reg(2, 0xfe, 0x000); + apb_write_reg(2, 0xff, 0x003ef7ff); + apb_write_reg(2, 0xfe, 0x001); + apb_write_reg(2, 0xff, 0x003d37c0); + apb_write_reg(2, 0xfe, 0x002); + apb_write_reg(2, 0xff, 0x003c3f94); + apb_write_reg(2, 0xfe, 0x003); + apb_write_reg(2, 0xff, 0x003b0f78); + apb_write_reg(2, 0xfe, 0x004); + apb_write_reg(2, 0xff, 0x0038c73f); + apb_write_reg(2, 0xfe, 0x005); + apb_write_reg(2, 0xff, 0x00369ef1); + apb_write_reg(2, 0xfe, 0x006); + apb_write_reg(2, 0xff, 0x003576be); + apb_write_reg(2, 0xfe, 0x007); + apb_write_reg(2, 0xff, 0x0033b698); + apb_write_reg(2, 0xfe, 0x008); + apb_write_reg(2, 0xff, 0x0031164d); + apb_write_reg(2, 0xfe, 0x009); + apb_write_reg(2, 0xff, 0x002f1dfd); + apb_write_reg(2, 0xfe, 0x00a); + apb_write_reg(2, 0xff, 0x002de5cf); + apb_write_reg(2, 0xfe, 0x00b); + apb_write_reg(2, 0xff, 0x002c15a2); + apb_write_reg(2, 0xfe, 0x00c); + apb_write_reg(2, 0xff, 0x0029f560); + apb_write_reg(2, 0xfe, 0x00d); + apb_write_reg(2, 0xff, 0x0027bd1b); + apb_write_reg(2, 0xfe, 0x00e); + apb_write_reg(2, 0xff, 0x00252ccf); + apb_write_reg(2, 0xfe, 0x00f); + apb_write_reg(2, 0xff, 0x0022bc7c); + apb_write_reg(2, 0xfe, 0x010); + apb_write_reg(2, 0xff, 0x00207c34); + apb_write_reg(2, 0xfe, 0x011); + apb_write_reg(2, 0xff, 0x001da3e5); + apb_write_reg(2, 0xfe, 0x012); + apb_write_reg(2, 0xff, 0x001a9b83); + apb_write_reg(2, 0xfe, 0x013); + apb_write_reg(2, 0xff, 0x0017db27); + apb_write_reg(2, 0xfe, 0x014); + apb_write_reg(2, 0xff, 0x001432c6); + apb_write_reg(2, 0xfe, 0x015); + apb_write_reg(2, 0xff, 0x000fa23e); + apb_write_reg(2, 0xfe, 0x016); + apb_write_reg(2, 0xff, 0x000b91af); + apb_write_reg(2, 0xfe, 0x017); + apb_write_reg(2, 0xff, 0x00077136); + apb_write_reg(2, 0xfe, 0x018); + apb_write_reg(2, 0xff, 0x0002c090); + apb_write_reg(2, 0xfe, 0x019); + apb_write_reg(2, 0xff, 0x003ec01a); + apb_write_reg(2, 0xfe, 0x01a); + apb_write_reg(2, 0xff, 0x003a3f92); + apb_write_reg(2, 0xfe, 0x01b); + apb_write_reg(2, 0xff, 0x00354efa); + apb_write_reg(2, 0xfe, 0x01c); + apb_write_reg(2, 0xff, 0x002fee54); + apb_write_reg(2, 0xfe, 0x01d); + apb_write_reg(2, 0xff, 0x002a35a3); + apb_write_reg(2, 0xfe, 0x01e); + apb_write_reg(2, 0xff, 0x0023f4e4); + apb_write_reg(2, 0xfe, 0x01f); + apb_write_reg(2, 0xff, 0x001cdc12); + apb_write_reg(2, 0xfe, 0x020); + apb_write_reg(2, 0xff, 0x00000316); + } else if (bandwidth == 1) { + apb_write_reg(2, 0x2c, 0x2C2); /* ACF_STAGE1_A1 */ + apb_write_reg(2, 0x2d, 0x069); /* ACF_STAGE1_A2 */ + apb_write_reg(2, 0x2e, 0x134); /* ACF_STAGE1_B1 */ + apb_write_reg(2, 0x2f, 0x00E); /* ACF_STAGE1_GAIN */ + apb_write_reg(2, 0x30, 0x2B7); /* ACF_STAGE2_A1 */ + apb_write_reg(2, 0x31, 0x095); /* ACF_STAGE2_A2 */ + apb_write_reg(2, 0x32, 0x36F); /* ACF_STAGE2_B1 */ + apb_write_reg(2, 0x33, 0x06D); /* ACF_STAGE2_GAIN */ + apb_write_reg(2, 0x34, 0x2AA); /* ACF_STAGE3_A1 */ + apb_write_reg(2, 0x35, 0x0C6); /* ACF_STAGE3_A2 */ + apb_write_reg(2, 0x36, 0x2E5); /* ACF_STAGE3_B1 */ + apb_write_reg(2, 0x37, 0x008); /* ACF_STAGE3_GAIN */ + apb_write_reg(2, 0x38, 0x2A1); /* ACF_STAGE4_A1 */ + apb_write_reg(2, 0x39, 0x0E6); /* ACF_STAGE4_A2 */ + apb_write_reg(2, 0x3a, 0x2BA); /* ACF_STAGE4_B1 */ + apb_write_reg(2, 0x3b, 0x058); /* ACF_STAGE4_GAIN */ + apb_write_reg(2, 0x3c, 0x299); /* ACF_STAGE5_A1 */ + apb_write_reg(2, 0x3d, 0x0F9); /* ACF_STAGE5_A2 */ + apb_write_reg(2, 0x3e, 0x2AC); /* ACF_STAGE5_B1 */ + apb_write_reg(2, 0x3f, 0x04D); /* ACF_STAGE5_GAIN */ + + apb_write_reg(2, 0xfe, 0x000); + apb_write_reg(2, 0xff, 0x003ee7ff); + apb_write_reg(2, 0xfe, 0x001); + apb_write_reg(2, 0xff, 0x003d1fbc); + apb_write_reg(2, 0xfe, 0x002); + apb_write_reg(2, 0xff, 0x003bf790); + apb_write_reg(2, 0xfe, 0x003); + apb_write_reg(2, 0xff, 0x003a876a); + apb_write_reg(2, 0xfe, 0x004); + apb_write_reg(2, 0xff, 0x00388f31); + apb_write_reg(2, 0xfe, 0x005); + apb_write_reg(2, 0xff, 0x0036c6f3); + apb_write_reg(2, 0xfe, 0x006); + apb_write_reg(2, 0xff, 0x003536bf); + apb_write_reg(2, 0xfe, 0x007); + apb_write_reg(2, 0xff, 0x00334689); + apb_write_reg(2, 0xfe, 0x008); + apb_write_reg(2, 0xff, 0x00310644); + apb_write_reg(2, 0xfe, 0x009); + apb_write_reg(2, 0xff, 0x002ef5fd); + apb_write_reg(2, 0xfe, 0x00a); + apb_write_reg(2, 0xff, 0x002d45c2); + apb_write_reg(2, 0xfe, 0x00b); + apb_write_reg(2, 0xff, 0x002b7d8c); + apb_write_reg(2, 0xfe, 0x00c); + apb_write_reg(2, 0xff, 0x00298550); + apb_write_reg(2, 0xfe, 0x00d); + apb_write_reg(2, 0xff, 0x00278510); + apb_write_reg(2, 0xfe, 0x00e); + apb_write_reg(2, 0xff, 0x00252ccc); + apb_write_reg(2, 0xfe, 0x00f); + apb_write_reg(2, 0xff, 0x0022847c); + apb_write_reg(2, 0xfe, 0x010); + apb_write_reg(2, 0xff, 0x00201427); + apb_write_reg(2, 0xfe, 0x011); + apb_write_reg(2, 0xff, 0x001e03e0); + apb_write_reg(2, 0xfe, 0x012); + apb_write_reg(2, 0xff, 0x001b6b9b); + apb_write_reg(2, 0xfe, 0x013); + apb_write_reg(2, 0xff, 0x0017c336); + apb_write_reg(2, 0xfe, 0x014); + apb_write_reg(2, 0xff, 0x0013e2b8); + apb_write_reg(2, 0xfe, 0x015); + apb_write_reg(2, 0xff, 0x0010b246); + apb_write_reg(2, 0xfe, 0x016); + apb_write_reg(2, 0xff, 0x000d81e8); + apb_write_reg(2, 0xfe, 0x017); + apb_write_reg(2, 0xff, 0x00084966); + apb_write_reg(2, 0xfe, 0x018); + apb_write_reg(2, 0xff, 0x0003089c); + apb_write_reg(2, 0xfe, 0x019); + apb_write_reg(2, 0xff, 0x003f0022); + apb_write_reg(2, 0xfe, 0x01a); + apb_write_reg(2, 0xff, 0x003aaf9c); + apb_write_reg(2, 0xfe, 0x01b); + apb_write_reg(2, 0xff, 0x00360f0c); + apb_write_reg(2, 0xfe, 0x01c); + apb_write_reg(2, 0xff, 0x00312e74); + apb_write_reg(2, 0xfe, 0x01d); + apb_write_reg(2, 0xff, 0x002c05d3); + apb_write_reg(2, 0xfe, 0x01e); + apb_write_reg(2, 0xff, 0x00268d2a); + apb_write_reg(2, 0xfe, 0x01f); + apb_write_reg(2, 0xff, 0x0020bc76); + apb_write_reg(2, 0xfe, 0x020); + apb_write_reg(2, 0xff, 0x000003b3); + } else if (bandwidth == 2) { + /* 6MHz */ + apb_write_reg(2, 0x2c, 0x2A9); /* ACF_STAGE1_A1 */ + apb_write_reg(2, 0x2d, 0x078); /* ACF_STAGE1_A2 */ + apb_write_reg(2, 0x2e, 0x0F4); /* ACF_STAGE1_B1 */ + apb_write_reg(2, 0x2f, 0x01E); /* ACF_STAGE1_GAIN */ + apb_write_reg(2, 0x30, 0x299); /* ACF_STAGE2_A1 */ + apb_write_reg(2, 0x31, 0x0A1); /* ACF_STAGE2_A2 */ + apb_write_reg(2, 0x32, 0x321); /* ACF_STAGE2_B1 */ + apb_write_reg(2, 0x33, 0x078); /* ACF_STAGE2_GAIN */ + apb_write_reg(2, 0x34, 0x288); /* ACF_STAGE3_A1 */ + apb_write_reg(2, 0x35, 0x0CD); /* ACF_STAGE3_A2 */ + apb_write_reg(2, 0x36, 0x2AE); /* ACF_STAGE3_B1 */ + apb_write_reg(2, 0x37, 0x05F); /* ACF_STAGE3_GAIN */ + apb_write_reg(2, 0x38, 0x27C); /* ACF_STAGE4_A1 */ + apb_write_reg(2, 0x39, 0x0E9); /* ACF_STAGE4_A2 */ + apb_write_reg(2, 0x3a, 0x28B); /* ACF_STAGE4_B1 */ + apb_write_reg(2, 0x3b, 0x058); /* ACF_STAGE4_GAIN */ + apb_write_reg(2, 0x3c, 0x273); /* ACF_STAGE5_A1 */ + apb_write_reg(2, 0x3d, 0x0FA); /* ACF_STAGE5_A2 */ + apb_write_reg(2, 0x3e, 0x281); /* ACF_STAGE5_B1 */ + apb_write_reg(2, 0x3f, 0x04D); /* ACF_STAGE5_GAIN */ + + apb_write_reg(2, 0xfe, 0x000); + apb_write_reg(2, 0xff, 0x003f17ff); + apb_write_reg(2, 0xfe, 0x001); + apb_write_reg(2, 0xff, 0x003d3fc4); + apb_write_reg(2, 0xfe, 0x002); + apb_write_reg(2, 0xff, 0x003b7f8a); + apb_write_reg(2, 0xfe, 0x003); + apb_write_reg(2, 0xff, 0x0039df55); + apb_write_reg(2, 0xfe, 0x004); + apb_write_reg(2, 0xff, 0x00381720); + apb_write_reg(2, 0xfe, 0x005); + apb_write_reg(2, 0xff, 0x00360ee2); + apb_write_reg(2, 0xfe, 0x006); + apb_write_reg(2, 0xff, 0x00342ea1); + apb_write_reg(2, 0xfe, 0x007); + apb_write_reg(2, 0xff, 0x0032ee6e); + apb_write_reg(2, 0xfe, 0x008); + apb_write_reg(2, 0xff, 0x0031e64e); + apb_write_reg(2, 0xfe, 0x009); + apb_write_reg(2, 0xff, 0x00300e22); + apb_write_reg(2, 0xfe, 0x00a); + apb_write_reg(2, 0xff, 0x002daddc); + apb_write_reg(2, 0xfe, 0x00b); + apb_write_reg(2, 0xff, 0x002b758f); + apb_write_reg(2, 0xfe, 0x00c); + apb_write_reg(2, 0xff, 0x0029ad51); + apb_write_reg(2, 0xfe, 0x00d); + apb_write_reg(2, 0xff, 0x0027ad18); + apb_write_reg(2, 0xfe, 0x00e); + apb_write_reg(2, 0xff, 0x00250ccd); + apb_write_reg(2, 0xfe, 0x00f); + apb_write_reg(2, 0xff, 0x00227476); + apb_write_reg(2, 0xfe, 0x010); + apb_write_reg(2, 0xff, 0x00204c2a); + apb_write_reg(2, 0xfe, 0x011); + apb_write_reg(2, 0xff, 0x001de3e6); + apb_write_reg(2, 0xfe, 0x012); + apb_write_reg(2, 0xff, 0x001a838a); + apb_write_reg(2, 0xfe, 0x013); + apb_write_reg(2, 0xff, 0x0016ab12); + apb_write_reg(2, 0xfe, 0x014); + apb_write_reg(2, 0xff, 0x00137a9d); + apb_write_reg(2, 0xfe, 0x015); + apb_write_reg(2, 0xff, 0x00113a4a); + apb_write_reg(2, 0xfe, 0x016); + apb_write_reg(2, 0xff, 0x000db1f8); + apb_write_reg(2, 0xfe, 0x017); + apb_write_reg(2, 0xff, 0x0007c15f); + apb_write_reg(2, 0xfe, 0x018); + apb_write_reg(2, 0xff, 0x00022883); + apb_write_reg(2, 0xfe, 0x019); + apb_write_reg(2, 0xff, 0x003df803); + apb_write_reg(2, 0xfe, 0x01a); + apb_write_reg(2, 0xff, 0x00398f79); + apb_write_reg(2, 0xfe, 0x01b); + apb_write_reg(2, 0xff, 0x0034d6e6); + apb_write_reg(2, 0xfe, 0x01c); + apb_write_reg(2, 0xff, 0x002fd64b); + apb_write_reg(2, 0xfe, 0x01d); + apb_write_reg(2, 0xff, 0x002a8da7); + apb_write_reg(2, 0xfe, 0x01e); + apb_write_reg(2, 0xff, 0x002504fa); + apb_write_reg(2, 0xfe, 0x01f); + apb_write_reg(2, 0xff, 0x001f2443); + apb_write_reg(2, 0xfe, 0x020); + apb_write_reg(2, 0xff, 0x00000382); + } else { + apb_write_reg(2, 0x2c, 0x28F); /* ACF_STAGE1_A1 */ + apb_write_reg(2, 0x2d, 0x088); /* ACF_STAGE1_A2 */ + apb_write_reg(2, 0x2e, 0x09E); /* ACF_STAGE1_B1 */ + apb_write_reg(2, 0x2f, 0x01E); /* ACF_STAGE1_GAIN */ + apb_write_reg(2, 0x30, 0x27C); /* ACF_STAGE2_A1 */ + apb_write_reg(2, 0x31, 0x0AD); /* ACF_STAGE2_A2 */ + apb_write_reg(2, 0x32, 0x2D6); /* ACF_STAGE2_B1 */ + apb_write_reg(2, 0x33, 0x078); /* ACF_STAGE2_GAIN */ + apb_write_reg(2, 0x34, 0x268); /* ACF_STAGE3_A1 */ + apb_write_reg(2, 0x35, 0x0D4); /* ACF_STAGE3_A2 */ + apb_write_reg(2, 0x36, 0x27C); /* ACF_STAGE3_B1 */ + apb_write_reg(2, 0x37, 0x05F); /* ACF_STAGE3_GAIN */ + apb_write_reg(2, 0x38, 0x25B); /* ACF_STAGE4_A1 */ + apb_write_reg(2, 0x39, 0x0ED); /* ACF_STAGE4_A2 */ + apb_write_reg(2, 0x3a, 0x262); /* ACF_STAGE4_B1 */ + apb_write_reg(2, 0x3b, 0x058); /* ACF_STAGE4_GAIN */ + apb_write_reg(2, 0x3c, 0x252); /* ACF_STAGE5_A1 */ + apb_write_reg(2, 0x3d, 0x0FB); /* ACF_STAGE5_A2 */ + apb_write_reg(2, 0x3e, 0x25A); /* ACF_STAGE5_B1 */ + apb_write_reg(2, 0x3f, 0x04D); /* ACF_STAGE5_GAIN */ + + apb_write_reg(2, 0xfe, 0x000); + apb_write_reg(2, 0xff, 0x003f17ff); + apb_write_reg(2, 0xfe, 0x001); + apb_write_reg(2, 0xff, 0x003d4fc5); + apb_write_reg(2, 0xfe, 0x002); + apb_write_reg(2, 0xff, 0x003baf8e); + apb_write_reg(2, 0xfe, 0x003); + apb_write_reg(2, 0xff, 0x003a3f5d); + apb_write_reg(2, 0xfe, 0x004); + apb_write_reg(2, 0xff, 0x0038df32); + apb_write_reg(2, 0xfe, 0x005); + apb_write_reg(2, 0xff, 0x00374703); + apb_write_reg(2, 0xfe, 0x006); + apb_write_reg(2, 0xff, 0x00354ec9); + apb_write_reg(2, 0xfe, 0x007); + apb_write_reg(2, 0xff, 0x00333e88); + apb_write_reg(2, 0xfe, 0x008); + apb_write_reg(2, 0xff, 0x00314e47); + apb_write_reg(2, 0xfe, 0x009); + apb_write_reg(2, 0xff, 0x002f860c); + apb_write_reg(2, 0xfe, 0x00a); + apb_write_reg(2, 0xff, 0x002d9dd2); + apb_write_reg(2, 0xfe, 0x00b); + apb_write_reg(2, 0xff, 0x002b5590); + apb_write_reg(2, 0xfe, 0x00c); + apb_write_reg(2, 0xff, 0x0028cd42); + apb_write_reg(2, 0xfe, 0x00d); + apb_write_reg(2, 0xff, 0x00266cf2); + apb_write_reg(2, 0xfe, 0x00e); + apb_write_reg(2, 0xff, 0x00245cab); + apb_write_reg(2, 0xfe, 0x00f); + apb_write_reg(2, 0xff, 0x00225c6b); + apb_write_reg(2, 0xfe, 0x010); + apb_write_reg(2, 0xff, 0x00200427); + apb_write_reg(2, 0xfe, 0x011); + apb_write_reg(2, 0xff, 0x001d4bd5); + apb_write_reg(2, 0xfe, 0x012); + apb_write_reg(2, 0xff, 0x001a9b7d); + apb_write_reg(2, 0xfe, 0x013); + apb_write_reg(2, 0xff, 0x00183b2b); + apb_write_reg(2, 0xfe, 0x014); + apb_write_reg(2, 0xff, 0x0015b2e1); + apb_write_reg(2, 0xfe, 0x015); + apb_write_reg(2, 0xff, 0x00122a83); + apb_write_reg(2, 0xfe, 0x016); + apb_write_reg(2, 0xff, 0x000d49fc); + apb_write_reg(2, 0xfe, 0x017); + apb_write_reg(2, 0xff, 0x0007594e); + apb_write_reg(2, 0xfe, 0x018); + apb_write_reg(2, 0xff, 0x00024080); + apb_write_reg(2, 0xfe, 0x019); + apb_write_reg(2, 0xff, 0x003e980e); + apb_write_reg(2, 0xfe, 0x01a); + apb_write_reg(2, 0xff, 0x003ab796); + apb_write_reg(2, 0xfe, 0x01b); + apb_write_reg(2, 0xff, 0x00368f15); + apb_write_reg(2, 0xfe, 0x01c); + apb_write_reg(2, 0xff, 0x00320e8a); + apb_write_reg(2, 0xfe, 0x01d); + apb_write_reg(2, 0xff, 0x002d25f4); + apb_write_reg(2, 0xfe, 0x01e); + apb_write_reg(2, 0xff, 0x0027ad4f); + apb_write_reg(2, 0xfe, 0x01f); + apb_write_reg(2, 0xff, 0x00219496); + apb_write_reg(2, 0xfe, 0x020); + apb_write_reg(2, 0xff, 0x000003c9); + } + } else { + /* 20.7 MHz Set ACF */ + if (bandwidth == 0) { + /*8M Hz */ + apb_write_reg(2, 0x2c, 0x318); /* ACF_STAGE1_A1 */ + apb_write_reg(2, 0x2d, 0x03E); /* ACF_STAGE1_A2 */ + apb_write_reg(2, 0x2e, 0x1AE); /* ACF_STAGE1_B1 */ + apb_write_reg(2, 0x2f, 0x00E); /* ACF_STAGE1_GAIN */ + apb_write_reg(2, 0x30, 0x326); /* ACF_STAGE2_A1 */ + apb_write_reg(2, 0x31, 0x074); /* ACF_STAGE2_A2 */ + apb_write_reg(2, 0x32, 0x074); /* ACF_STAGE2_B1 */ + apb_write_reg(2, 0x33, 0x06F); /* ACF_STAGE2_GAIN */ + apb_write_reg(2, 0x34, 0x336); /* ACF_STAGE3_A1 */ + apb_write_reg(2, 0x35, 0x0B1); /* ACF_STAGE3_A2 */ + apb_write_reg(2, 0x36, 0x3C9); /* ACF_STAGE3_B1 */ + apb_write_reg(2, 0x37, 0x008); /* ACF_STAGE3_GAIN */ + apb_write_reg(2, 0x38, 0x33F); /* ACF_STAGE4_A1 */ + apb_write_reg(2, 0x39, 0x0DC); /* ACF_STAGE4_A2 */ + apb_write_reg(2, 0x3a, 0x384); /* ACF_STAGE4_B1 */ + apb_write_reg(2, 0x3b, 0x05A); /* ACF_STAGE4_GAIN */ + apb_write_reg(2, 0x3c, 0x340); /* ACF_STAGE5_A1 */ + apb_write_reg(2, 0x3d, 0x0F6); /* ACF_STAGE5_A2 */ + apb_write_reg(2, 0x3e, 0x36D); /* ACF_STAGE5_B1 */ + apb_write_reg(2, 0x3f, 0x04B); /* ACF_STAGE5_GAIN */ + + apb_write_reg(2, 0xfe, 0x000); + apb_write_reg(2, 0xff, 0x003f37ff); + apb_write_reg(2, 0xfe, 0x001); + apb_write_reg(2, 0xff, 0x003d97cc); + apb_write_reg(2, 0xfe, 0x002); + apb_write_reg(2, 0xff, 0x003bf798); + apb_write_reg(2, 0xfe, 0x003); + apb_write_reg(2, 0xff, 0x003a4f64); + apb_write_reg(2, 0xfe, 0x004); + apb_write_reg(2, 0xff, 0x0038a72f); + apb_write_reg(2, 0xfe, 0x005); + apb_write_reg(2, 0xff, 0x0036f6f9); + apb_write_reg(2, 0xfe, 0x006); + apb_write_reg(2, 0xff, 0x003546c3); + apb_write_reg(2, 0xfe, 0x007); + apb_write_reg(2, 0xff, 0x0033868c); + apb_write_reg(2, 0xfe, 0x008); + apb_write_reg(2, 0xff, 0x0031be54); + apb_write_reg(2, 0xfe, 0x009); + apb_write_reg(2, 0xff, 0x002fe61a); + apb_write_reg(2, 0xfe, 0x00a); + apb_write_reg(2, 0xff, 0x002e05df); + apb_write_reg(2, 0xfe, 0x00b); + apb_write_reg(2, 0xff, 0x002c15a2); + apb_write_reg(2, 0xfe, 0x00c); + apb_write_reg(2, 0xff, 0x002a1562); + apb_write_reg(2, 0xfe, 0x00d); + apb_write_reg(2, 0xff, 0x0027f520); + apb_write_reg(2, 0xfe, 0x00e); + apb_write_reg(2, 0xff, 0x0025c4dc); + apb_write_reg(2, 0xfe, 0x00f); + apb_write_reg(2, 0xff, 0x00236c93); + apb_write_reg(2, 0xfe, 0x010); + apb_write_reg(2, 0xff, 0x0020f446); + apb_write_reg(2, 0xfe, 0x011); + apb_write_reg(2, 0xff, 0x001e4bf4); + apb_write_reg(2, 0xfe, 0x012); + apb_write_reg(2, 0xff, 0x001b739d); + apb_write_reg(2, 0xfe, 0x013); + apb_write_reg(2, 0xff, 0x00185b3d); + apb_write_reg(2, 0xfe, 0x014); + apb_write_reg(2, 0xff, 0x0014ead5); + apb_write_reg(2, 0xfe, 0x015); + apb_write_reg(2, 0xff, 0x00111a62); + apb_write_reg(2, 0xfe, 0x016); + apb_write_reg(2, 0xff, 0x000cb9df); + apb_write_reg(2, 0xfe, 0x017); + apb_write_reg(2, 0xff, 0x00079148); + apb_write_reg(2, 0xfe, 0x018); + apb_write_reg(2, 0xff, 0x00030093); + apb_write_reg(2, 0xfe, 0x019); + apb_write_reg(2, 0xff, 0x003f802a); + apb_write_reg(2, 0xfe, 0x01a); + apb_write_reg(2, 0xff, 0x003b77b2); + apb_write_reg(2, 0xfe, 0x01b); + apb_write_reg(2, 0xff, 0x0036a725); + apb_write_reg(2, 0xfe, 0x01c); + apb_write_reg(2, 0xff, 0x0030ae7b); + apb_write_reg(2, 0xfe, 0x01d); + apb_write_reg(2, 0xff, 0x00285d9f); + apb_write_reg(2, 0xfe, 0x01e); + apb_write_reg(2, 0xff, 0x001abc46); + apb_write_reg(2, 0xfe, 0x01f); + apb_write_reg(2, 0xff, 0x000f8a85); + apb_write_reg(2, 0xfe, 0x020); + apb_write_reg(2, 0xff, 0x00000187); + } else if (bandwidth == 1) { + apb_write_reg(2, 0x2c, 0x2F9); /* ACF_STAGE1_A1 */ + apb_write_reg(2, 0x2d, 0x04C); /* ACF_STAGE1_A2 */ + apb_write_reg(2, 0x2e, 0x18E); /* ACF_STAGE1_B1 */ + apb_write_reg(2, 0x2f, 0x00E); /* ACF_STAGE1_GAIN */ + apb_write_reg(2, 0x30, 0x2FD); /* ACF_STAGE2_A1 */ + apb_write_reg(2, 0x31, 0x07F); /* ACF_STAGE2_A2 */ + apb_write_reg(2, 0x32, 0x01A); /* ACF_STAGE2_B1 */ + apb_write_reg(2, 0x33, 0x06D); /* ACF_STAGE2_GAIN */ + apb_write_reg(2, 0x34, 0x300); /* ACF_STAGE3_A1 */ + apb_write_reg(2, 0x35, 0x0B8); /* ACF_STAGE3_A2 */ + apb_write_reg(2, 0x36, 0x372); /* ACF_STAGE3_B1 */ + apb_write_reg(2, 0x37, 0x05F); /* ACF_STAGE3_GAIN */ + apb_write_reg(2, 0x38, 0x301); /* ACF_STAGE4_A1 */ + apb_write_reg(2, 0x39, 0x0DF); /* ACF_STAGE4_A2 */ + apb_write_reg(2, 0x3a, 0x335); /* ACF_STAGE4_B1 */ + apb_write_reg(2, 0x3b, 0x05A); /* ACF_STAGE4_GAIN */ + apb_write_reg(2, 0x3c, 0x2FE); /* ACF_STAGE5_A1 */ + apb_write_reg(2, 0x3d, 0x0F7); /* ACF_STAGE5_A2 */ + apb_write_reg(2, 0x3e, 0x320); /* ACF_STAGE5_B1 */ + apb_write_reg(2, 0x3f, 0x04B); /* ACF_STAGE5_GAIN */ + + apb_write_reg(2, 0xfe, 0x000); + apb_write_reg(2, 0xff, 0x003f37ff); + apb_write_reg(2, 0xfe, 0x001); + apb_write_reg(2, 0xff, 0x003d8fcc); + apb_write_reg(2, 0xfe, 0x002); + apb_write_reg(2, 0xff, 0x003bef97); + apb_write_reg(2, 0xfe, 0x003); + apb_write_reg(2, 0xff, 0x003a4762); + apb_write_reg(2, 0xfe, 0x004); + apb_write_reg(2, 0xff, 0x0038972d); + apb_write_reg(2, 0xfe, 0x005); + apb_write_reg(2, 0xff, 0x0036e6f7); + apb_write_reg(2, 0xfe, 0x006); + apb_write_reg(2, 0xff, 0x00352ec1); + apb_write_reg(2, 0xfe, 0x007); + apb_write_reg(2, 0xff, 0x00336e89); + apb_write_reg(2, 0xfe, 0x008); + apb_write_reg(2, 0xff, 0x00319e50); + apb_write_reg(2, 0xfe, 0x009); + apb_write_reg(2, 0xff, 0x002fce16); + apb_write_reg(2, 0xfe, 0x00a); + apb_write_reg(2, 0xff, 0x002de5db); + apb_write_reg(2, 0xfe, 0x00b); + apb_write_reg(2, 0xff, 0x002bf59d); + apb_write_reg(2, 0xfe, 0x00c); + apb_write_reg(2, 0xff, 0x0029ed5e); + apb_write_reg(2, 0xfe, 0x00d); + apb_write_reg(2, 0xff, 0x0027d51c); + apb_write_reg(2, 0xfe, 0x00e); + apb_write_reg(2, 0xff, 0x00259cd7); + apb_write_reg(2, 0xfe, 0x00f); + apb_write_reg(2, 0xff, 0x0023448e); + apb_write_reg(2, 0xfe, 0x010); + apb_write_reg(2, 0xff, 0x0020cc41); + apb_write_reg(2, 0xfe, 0x011); + apb_write_reg(2, 0xff, 0x001e23ef); + apb_write_reg(2, 0xfe, 0x012); + apb_write_reg(2, 0xff, 0x001b4b98); + apb_write_reg(2, 0xfe, 0x013); + apb_write_reg(2, 0xff, 0x00183339); + apb_write_reg(2, 0xfe, 0x014); + apb_write_reg(2, 0xff, 0x0014cad1); + apb_write_reg(2, 0xfe, 0x015); + apb_write_reg(2, 0xff, 0x0010fa5e); + apb_write_reg(2, 0xfe, 0x016); + apb_write_reg(2, 0xff, 0x000c99dc); + apb_write_reg(2, 0xfe, 0x017); + apb_write_reg(2, 0xff, 0x00078145); + apb_write_reg(2, 0xfe, 0x018); + apb_write_reg(2, 0xff, 0x0002f892); + apb_write_reg(2, 0xfe, 0x019); + apb_write_reg(2, 0xff, 0x003f802a); + apb_write_reg(2, 0xfe, 0x01a); + apb_write_reg(2, 0xff, 0x003b8fb3); + apb_write_reg(2, 0xfe, 0x01b); + apb_write_reg(2, 0xff, 0x0036d729); + apb_write_reg(2, 0xfe, 0x01c); + apb_write_reg(2, 0xff, 0x00310682); + apb_write_reg(2, 0xfe, 0x01d); + apb_write_reg(2, 0xff, 0x00290dae); + apb_write_reg(2, 0xfe, 0x01e); + apb_write_reg(2, 0xff, 0x001c0c67); + apb_write_reg(2, 0xfe, 0x01f); + apb_write_reg(2, 0xff, 0x0010a2ad); + apb_write_reg(2, 0xfe, 0x020); + apb_write_reg(2, 0xff, 0x000001a8); + } else if (bandwidth == 2) { + /* 6MHz */ + apb_write_reg(2, 0x2c, 0x2D9); /* ACF_STAGE1_A1 */ + apb_write_reg(2, 0x2d, 0x05C); /* ACF_STAGE1_A2 */ + apb_write_reg(2, 0x2e, 0x161); /* ACF_STAGE1_B1 */ + apb_write_reg(2, 0x2f, 0x00E); /* ACF_STAGE1_GAIN */ + apb_write_reg(2, 0x30, 0x2D4); /* ACF_STAGE2_A1 */ + apb_write_reg(2, 0x31, 0x08B); /* ACF_STAGE2_A2 */ + apb_write_reg(2, 0x32, 0x3B8); /* ACF_STAGE2_B1 */ + apb_write_reg(2, 0x33, 0x06B); /* ACF_STAGE2_GAIN */ + apb_write_reg(2, 0x34, 0x2CD); /* ACF_STAGE3_A1 */ + apb_write_reg(2, 0x35, 0x0C0); /* ACF_STAGE3_A2 */ + apb_write_reg(2, 0x36, 0x31E); /* ACF_STAGE3_B1 */ + apb_write_reg(2, 0x37, 0x05F); /* ACF_STAGE3_GAIN */ + apb_write_reg(2, 0x38, 0x2C7); /* ACF_STAGE4_A1 */ + apb_write_reg(2, 0x39, 0x0E3); /* ACF_STAGE4_A2 */ + apb_write_reg(2, 0x3a, 0x2EB); /* ACF_STAGE4_B1 */ + apb_write_reg(2, 0x3b, 0x05A); /* ACF_STAGE4_GAIN */ + apb_write_reg(2, 0x3c, 0x2C1); /* ACF_STAGE5_A1 */ + apb_write_reg(2, 0x3d, 0x0F8); /* ACF_STAGE5_A2 */ + apb_write_reg(2, 0x3e, 0x2DA); /* ACF_STAGE5_B1 */ + apb_write_reg(2, 0x3f, 0x04B); /* ACF_STAGE5_GAIN */ + apb_write_reg(2, 0xfe, 0x000); + apb_write_reg(2, 0xff, 0x003f2fff); + apb_write_reg(2, 0xfe, 0x001); + apb_write_reg(2, 0xff, 0x003d87cb); + apb_write_reg(2, 0xfe, 0x002); + apb_write_reg(2, 0xff, 0x003bdf96); + apb_write_reg(2, 0xfe, 0x003); + apb_write_reg(2, 0xff, 0x003a2f60); + apb_write_reg(2, 0xfe, 0x004); + apb_write_reg(2, 0xff, 0x00387f2a); + apb_write_reg(2, 0xfe, 0x005); + apb_write_reg(2, 0xff, 0x0036c6f4); + apb_write_reg(2, 0xfe, 0x006); + apb_write_reg(2, 0xff, 0x00350ebd); + apb_write_reg(2, 0xfe, 0x007); + apb_write_reg(2, 0xff, 0x00334684); + apb_write_reg(2, 0xfe, 0x008); + apb_write_reg(2, 0xff, 0x0031764b); + apb_write_reg(2, 0xfe, 0x009); + apb_write_reg(2, 0xff, 0x002f9e11); + apb_write_reg(2, 0xfe, 0x00a); + apb_write_reg(2, 0xff, 0x002db5d4); + apb_write_reg(2, 0xfe, 0x00b); + apb_write_reg(2, 0xff, 0x002bbd97); + apb_write_reg(2, 0xfe, 0x00c); + apb_write_reg(2, 0xff, 0x0029b557); + apb_write_reg(2, 0xfe, 0x00d); + apb_write_reg(2, 0xff, 0x00279515); + apb_write_reg(2, 0xfe, 0x00e); + apb_write_reg(2, 0xff, 0x00255ccf); + apb_write_reg(2, 0xfe, 0x00f); + apb_write_reg(2, 0xff, 0x00230c87); + apb_write_reg(2, 0xfe, 0x010); + apb_write_reg(2, 0xff, 0x0020943a); + apb_write_reg(2, 0xfe, 0x011); + apb_write_reg(2, 0xff, 0x001debe8); + apb_write_reg(2, 0xfe, 0x012); + apb_write_reg(2, 0xff, 0x001b1b91); + apb_write_reg(2, 0xfe, 0x013); + apb_write_reg(2, 0xff, 0x00180b33); + apb_write_reg(2, 0xfe, 0x014); + apb_write_reg(2, 0xff, 0x0014aacc); + apb_write_reg(2, 0xfe, 0x015); + apb_write_reg(2, 0xff, 0x0010e25a); + apb_write_reg(2, 0xfe, 0x016); + apb_write_reg(2, 0xff, 0x000c91da); + apb_write_reg(2, 0xfe, 0x017); + apb_write_reg(2, 0xff, 0x00078945); + apb_write_reg(2, 0xfe, 0x018); + apb_write_reg(2, 0xff, 0x00031895); + apb_write_reg(2, 0xfe, 0x019); + apb_write_reg(2, 0xff, 0x003fa82e); + apb_write_reg(2, 0xfe, 0x01a); + apb_write_reg(2, 0xff, 0x003bbfb8); + apb_write_reg(2, 0xfe, 0x01b); + apb_write_reg(2, 0xff, 0x00371730); + apb_write_reg(2, 0xfe, 0x01c); + apb_write_reg(2, 0xff, 0x0031668c); + apb_write_reg(2, 0xfe, 0x01d); + apb_write_reg(2, 0xff, 0x00299dbc); + apb_write_reg(2, 0xfe, 0x01e); + apb_write_reg(2, 0xff, 0x001d1480); + apb_write_reg(2, 0xfe, 0x01f); + apb_write_reg(2, 0xff, 0x00119acf); + apb_write_reg(2, 0xfe, 0x020); + apb_write_reg(2, 0xff, 0x000001c4); + } else { + apb_write_reg(2, 0x2c, 0x2B9); /* ACF_STAGE1_A1 */ + apb_write_reg(2, 0x2d, 0x06E); /* ACF_STAGE1_A2 */ + apb_write_reg(2, 0x2e, 0x11E); /* ACF_STAGE1_B1 */ + apb_write_reg(2, 0x2f, 0x01E); /* ACF_STAGE1_GAIN */ + apb_write_reg(2, 0x30, 0x2AB); /* ACF_STAGE2_A1 */ + apb_write_reg(2, 0x31, 0x099); /* ACF_STAGE2_A2 */ + apb_write_reg(2, 0x32, 0x351); /* ACF_STAGE2_B1 */ + apb_write_reg(2, 0x33, 0x06B); /* ACF_STAGE2_GAIN */ + apb_write_reg(2, 0x34, 0x29D); /* ACF_STAGE3_A1 */ + apb_write_reg(2, 0x35, 0x0C8); /* ACF_STAGE3_A2 */ + apb_write_reg(2, 0x36, 0x2D0); /* ACF_STAGE3_B1 */ + apb_write_reg(2, 0x37, 0x05F); /* ACF_STAGE3_GAIN */ + apb_write_reg(2, 0x38, 0x292); /* ACF_STAGE4_A1 */ + apb_write_reg(2, 0x39, 0x0E7); /* ACF_STAGE4_A2 */ + apb_write_reg(2, 0x3a, 0x2A8); /* ACF_STAGE4_B1 */ + apb_write_reg(2, 0x3b, 0x05A); /* ACF_STAGE4_GAIN */ + apb_write_reg(2, 0x3c, 0x28A); /* ACF_STAGE5_A1 */ + apb_write_reg(2, 0x3d, 0x0F9); /* ACF_STAGE5_A2 */ + apb_write_reg(2, 0x3e, 0x29B); /* ACF_STAGE5_B1 */ + apb_write_reg(2, 0x3f, 0x04B); /* ACF_STAGE5_GAIN */ + + apb_write_reg(2, 0xfe, 0x000); + apb_write_reg(2, 0xff, 0x003f2fff); + apb_write_reg(2, 0xfe, 0x001); + apb_write_reg(2, 0xff, 0x003d7fca); + apb_write_reg(2, 0xfe, 0x002); + apb_write_reg(2, 0xff, 0x003bcf94); + apb_write_reg(2, 0xfe, 0x003); + apb_write_reg(2, 0xff, 0x003a1f5e); + apb_write_reg(2, 0xfe, 0x004); + apb_write_reg(2, 0xff, 0x00386727); + apb_write_reg(2, 0xfe, 0x005); + apb_write_reg(2, 0xff, 0x0036a6f0); + apb_write_reg(2, 0xfe, 0x006); + apb_write_reg(2, 0xff, 0x0034e6b8); + apb_write_reg(2, 0xfe, 0x007); + apb_write_reg(2, 0xff, 0x0033167f); + apb_write_reg(2, 0xfe, 0x008); + apb_write_reg(2, 0xff, 0x00314645); + apb_write_reg(2, 0xfe, 0x009); + apb_write_reg(2, 0xff, 0x002f660a); + apb_write_reg(2, 0xfe, 0x00a); + apb_write_reg(2, 0xff, 0x002d75cd); + apb_write_reg(2, 0xfe, 0x00b); + apb_write_reg(2, 0xff, 0x002b758e); + apb_write_reg(2, 0xfe, 0x00c); + apb_write_reg(2, 0xff, 0x0029654e); + apb_write_reg(2, 0xfe, 0x00d); + apb_write_reg(2, 0xff, 0x0027450a); + apb_write_reg(2, 0xfe, 0x00e); + apb_write_reg(2, 0xff, 0x002504c4); + apb_write_reg(2, 0xfe, 0x00f); + apb_write_reg(2, 0xff, 0x0022a47b); + apb_write_reg(2, 0xfe, 0x010); + apb_write_reg(2, 0xff, 0x0020242d); + apb_write_reg(2, 0xfe, 0x011); + apb_write_reg(2, 0xff, 0x001d7bdb); + apb_write_reg(2, 0xfe, 0x012); + apb_write_reg(2, 0xff, 0x001aa383); + apb_write_reg(2, 0xfe, 0x013); + apb_write_reg(2, 0xff, 0x00178b24); + apb_write_reg(2, 0xfe, 0x014); + apb_write_reg(2, 0xff, 0x00142abd); + apb_write_reg(2, 0xfe, 0x015); + apb_write_reg(2, 0xff, 0x0010624a); + apb_write_reg(2, 0xfe, 0x016); + apb_write_reg(2, 0xff, 0x000c11ca); + apb_write_reg(2, 0xfe, 0x017); + apb_write_reg(2, 0xff, 0x00070935); + apb_write_reg(2, 0xfe, 0x018); + apb_write_reg(2, 0xff, 0x00029885); + apb_write_reg(2, 0xfe, 0x019); + apb_write_reg(2, 0xff, 0x003f281e); + apb_write_reg(2, 0xfe, 0x01a); + apb_write_reg(2, 0xff, 0x003b3fa9); + apb_write_reg(2, 0xfe, 0x01b); + apb_write_reg(2, 0xff, 0x00369720); + apb_write_reg(2, 0xfe, 0x01c); + apb_write_reg(2, 0xff, 0x0030ce7b); + apb_write_reg(2, 0xfe, 0x01d); + apb_write_reg(2, 0xff, 0x0028dda7); + apb_write_reg(2, 0xfe, 0x01e); + apb_write_reg(2, 0xff, 0x001c6464); + apb_write_reg(2, 0xfe, 0x01f); + apb_write_reg(2, 0xff, 0x0011b2c7); + apb_write_reg(2, 0xfe, 0x020); + apb_write_reg(2, 0xff, 0x000001cb); + } + } +} + +static void dvbt_reg_initial(struct aml_demod_sta *demod_sta) +{ + u32 clk_freq; + u32 adc_freq; + u8 ch_mode; + u8 agc_mode; + u32 ch_freq; + u16 ch_if; + u16 ch_bw; + u16 symb_rate; + + u8 bw; + u8 sr; + u8 ifreq; + u32 tmp; + + clk_freq = demod_sta->clk_freq; /* kHz */ + adc_freq = demod_sta->adc_freq; /* kHz */ + ch_mode = demod_sta->ch_mode; + agc_mode = demod_sta->agc_mode; + ch_freq = demod_sta->ch_freq; /* kHz */ + ch_if = demod_sta->ch_if; /* kHz */ + ch_bw = demod_sta->ch_bw; /* kHz */ + symb_rate = demod_sta->symb_rate; /* k/sec */ + + bw = 8 - ch_bw / 1000; + sr = adc_freq > 40000 ? 3 : adc_freq > 24000 ? 2 : + adc_freq > 20770 ? 1 : 0; + ifreq = ch_if > 35000 ? 0 : 1; + + /*//////////////////////////////////// */ + /* bw == 0 : 8M */ + /* 1 : 7M */ + /* 2 : 6M */ + /* 3 : 5M */ + /* sr == 0 : 20.7M */ + /* 1 : 20.8333M */ + /* 2 : 28.5714M */ + /* 3 : 45M */ + /* ifreq == 0: 36.13MHz */ + /* 1: 4.57MHz */ + /* agc_mode == 0: single AGC */ + /* 1: dual AGC */ + /*//////////////////////////////////// */ + apb_write_reg(2, 0x02, 0x00800000); + /* SW reset bit[23] ; write anything to zero */ + apb_write_reg(2, 0x00, 0x00000000); + + switch (sr) { + case 0: + apb_write_reg(2, 0x08, 0x00002966); + break; + case 1: + apb_write_reg(2, 0x08, 0x00002999); + break; + case 2: + apb_write_reg(2, 0x08, 0x00003924); + break; + case 3: + apb_write_reg(2, 0x08, 0x00005a00); + break; /*sample_rate /*45M */ + default: + break; + } + + apb_write_reg(2, 0x0d, 0x00000000); + apb_write_reg(2, 0x0e, 0x00000000); + dvbt_enable_irq(8); + + apb_write_reg(2, 0x11, 0x00100002); /* FSM [15:0] TIMER_FEC_LOST */ + apb_write_reg(2, 0x12, 0x02100201); /* FSM */ + apb_write_reg(2, 0x14, 0xe81c4ff6); /* AGC_TARGET 0xf0121385 */ + apb_write_reg(2, 0x15, 0x02050ca6); /* AGC_CTRL */ + + switch (sr) { + case 0: + apb_write_reg(2, 0x15, apb_read_reg(2, 0x15) | (0x5b << 12)); + break; + case 1: + apb_write_reg(2, 0x15, apb_read_reg(2, 0x15) | (0x5b << 12)); + break; + case 2: + apb_write_reg(2, 0x15, apb_read_reg(2, 0x15) | (0x7b << 12)); + break; + case 3: + apb_write_reg(2, 0x15, apb_read_reg(2, 0x15) | (0xc2 << 12)); + break; /* sample_rate /*45M */ + default: + break; + } + + if (agc_mode == 0) + apb_write_reg(2, 0x16, 0x67f80); /* AGC_IFGAIN_CTRL */ + else if (agc_mode == 1) + apb_write_reg(2, 0x16, 0x07f80); /* AGC_IFGAIN_CTRL */ + + apb_write_reg(2, 0x17, 0x07f80); /* AGC_RFGAIN_CTRL */ + apb_write_reg(2, 0x18, 0x00000000); /* AGC_IFGAIN_ACCUM */ + apb_write_reg(2, 0x19, 0x00000000); /* AGC_RFGAIN_ACCUM */ + + if (ifreq == 0) { + switch (sr) { + case 0: + apb_write_reg(2, 0x20, 0x00002096); + break; + /* DDC NORM_PHASE 36.13M IF For 20.7M sample rate */ + case 1: + apb_write_reg(2, 0x20, 0x000021a9); + break; + /* DDC NORM_PHASE 36.13M IF For 20.8333M sample rate*/ + case 2: + apb_write_reg(2, 0x20, 0x000021dc); + break; + /* DDC NORM_PHASE 36.13M IF For 28.57142M sample rate*/ + case 3: + apb_write_reg(2, 0x20, 0x000066e2); + break; + /* DDC NORM_PHASE 36.13M IF For 45M sample rate */ + default: + break; + } + } else if (ifreq == 1) { + switch (sr) { + case 0: + apb_write_reg(2, 0x20, 0x00001c42); + break; + /* DDC NORM_PHASE 4.57M IF For 20.7M sample rate */ + case 1: + apb_write_reg(2, 0x20, 0x00001c1f); + break; + /* DDC NORM_PHASE 4.57M IF For 20.8333M sample rate */ + case 2: + apb_write_reg(2, 0x20, 0x00001479); + break; + /* DDC NORM_PHASE 4.57M IF For 28.57142M sample rate*/ + case 3: + apb_write_reg(2, 0x20, 0x0000d00); + break; + /* DDC NORM_PHASE 4.57M IF For 45M sample rate */ + default: + break; + } + } + */tmp = ch_if * (1 << 15)/adc_freq; + tmp &= 0x3fff; + apb_write_reg(2, 0x20, tmp); + if (demod_sta->debug) + dprintk("IF: %d kHz ADC: %d kHz DDC: %04x\n", ch_if, adc_freq, + tmp); + + apb_write_reg(2, 0x21, 0x001ff000); /* DDC CS_FCFO_ADJ_CTRL */ + apb_write_reg(2, 0x22, 0x00000000); /* DDC ICFO_ADJ_CTRL */ + apb_write_reg(2, 0x23, 0x00004000); /* DDC TRACK_FCFO_ADJ_CTRL */ + apb_write_reg(2, 0x27, 0x00a98200); + /*[23] agc state mode [22:19] icfo_time_limit ;[18:15] tps_time_limit ; + * [14:4] cs_cfo_thres ; [3:0] fsm_state_d; + */ + /* 1 010,1 001,1 + * 000,0010,0000, xxxx + */ + apb_write_reg(2, 0x28, 0x04028032); + /* [31:24] cs_Q_thres; [23:13] sfo_thres; FSM [12:0] fcfo_thres;; */ + /* 0000,0100, 0000,0010,100 0,0000,0011,0010 */ + apb_write_reg(2, 0x29, 0x0051117F); + /*apb_write_reg(2, 0x29, 0x00010f7F); */ + /* [18:16] fec_rs_sh_ctrl ;[15:9] fsm_total_timer; + * [8:6] modeDet_time_limit; FSM [5:0] sfo_time_limit; ; + */ + /* 01, () 0000,111 1,01 11,1111 */ + + /* SRC NORM_INRATE */ + switch (bw) { + case 0: + tmp = (1 << 14) * adc_freq / 125 / 8 * 7; + break; + case 1: + tmp = (1 << 14) * adc_freq / 125; + break; + case 2: + tmp = (1 << 14) * adc_freq / 125 / 6 * 7; + break; + case 3: + tmp = (1 << 14) * adc_freq / 125 / 5 * 7; + break; + default: + tmp = (1 << 14) * adc_freq / 125 / 8 * 7; + break; + } + + apb_write_reg(2, 0x44, tmp & 0x7fffff); + + apb_write_reg(2, 0x45, 0x00000000); /* SRC SRC_PHASE_INI */ + apb_write_reg(2, 0x46, 0x02004000); + /* SRC SFO_ADJ_CTRL SFO limit 0x100!! */ + apb_write_reg(2, 0x48, 0xc0287); /* DAGC_CTRL */ + apb_write_reg(2, 0x49, 0x00000005); /* DAGC_CTRL1 */ + apb_write_reg(2, 0x4c, 0x00000bbf); /* CCI_RP */ + apb_write_reg(2, 0x4d, 0x00000376); /* CCI_RPSQ */ + apb_write_reg(2, 0x4e, 0x00202109); /* CCI_CTRL */ + apb_write_reg(2, 0x52, 0x00000000); /* CCI_NOTCH1_A2 */ + apb_write_reg(2, 0x53, 0x00000000); /* CCI_NOTCH1_B1 */ + apb_write_reg(2, 0x54, 0x00c00000); /* CCI_NOTCH2_A1 */ + apb_write_reg(2, 0x55, 0x00000000); /* CCI_NOTCH2_A2 */ + apb_write_reg(2, 0x56, 0x00000000); /* CCI_NOTCH2_B1 */ + apb_write_reg(2, 0x57, 0x00000000); /* CCI_NOTCH2_B1 */ + apb_write_reg(2, 0x58, 0x00000886); /* MODE_DETECT_CTRL */ + apb_write_reg(2, 0x5c, 0x00001011); /* ICFO_EST_CTRL */ + apb_write_reg(2, 0x5f, 0x00010503); /* TPS_FCFO_CTRL */ + apb_write_reg(2, 0x61, 0x00000003); /* DE_PN_CTRL */ + apb_write_reg(2, 0x61, apb_read_reg(2, 0x61) | (1 << 2)); + /* DE_PN_CTRL SP sync close , Use TPS only ; */ + apb_write_reg(2, 0x68, 0x004060c0); /* CHAN_EST_CTRL0 */ + apb_write_reg(2, 0x68, apb_read_reg(2, 0x68) & ~(1 << 7)); + /* SNR report filter; */ + /*apb_write_reg(2, 0x68, apb_read_reg(2, 0x68) &~(1<<13)); // + * Timing Adjust Shutdown; + */ + apb_write_reg(2, 0x69, 0x148c3812); /* CHAN_EST_CTRL1 */ + /*apb_write_reg(2, 0x69, apb_read_reg(2, 0x69) | (1<<10)); // + * Disable FD data update + */ + /*apb_write_reg(2, 0x69, apb_read_reg(2, 0x69) | (1<<9)); // + * set FD coeff + */ + /*apb_write_reg(2, 0x69, apb_read_reg(2, 0x69) | (1<<8)); // + * set TD coeff + */ + apb_write_reg(2, 0x6a, 0x9101012d); /* CHAN_EST_CTRL2 */ + apb_write_reg(2, 0x6b, 0x00442211); /* CHAN_EST_CTRL2 */ + apb_write_reg(2, 0x6c, 0x01fc040a); /* CHAN_EST_CTRL3 */ + apb_write_reg(2, 0x6d, 0x0030303f); /* SET SNR THRESHOLD */ + apb_write_reg(2, 0x73, 0xffffffff); /* CCI0_PILOT_UPDATE_CTRL */ + apb_write_reg(2, 0x74, 0xffffffff); /* CCI0_DATA_UPDATE_CTRL */ + apb_write_reg(2, 0x75, 0xffffffff); /* CCI1_PILOT_UPDATE_CTRL */ + apb_write_reg(2, 0x76, 0xffffffff); /* CCI1_DATA_UPDATE_CTRL */ + + /* Set ACF and ACFEQ coeffecient */ + switch (sr) { + case 0: + set_ACF_coef(21, bw); + break; + case 1: + set_ACF_coef(21, bw); + break; + case 2: + set_ACF_coef(28, bw); + break; + case 3: + set_ACF_coef(45, bw); + break; + default: + break; + } + + apb_write_reg(2, 0x78, 0x000001a2); + /* FEC_CTRL parallel mode ; [27:24] is TS clk/valid/sync/error */ + apb_write_reg(2, 0x7d, 0x0000009d); + apb_write_reg(2, 0xd6, 0x00000003); + apb_write_reg(2, 0xd7, 0x00000008); + apb_write_reg(2, 0xd8, 0x00000120); + apb_write_reg(2, 0xd9, 0x01010101); + apb_write_reg(2, 0x04, 0x00000000); + /* TPS Current, QPSK, none Hierarchy, HP, LP 1/2 */ + + tmp = (1 << 25) | ((bw & 3) << 20) | (1 << 16) | (1 << 1); + apb_write_reg(2, 0x02, tmp); + apb_write_reg(2, 0x03, (1 << 6)); /* Cordic parameter Calc */ + + udelay(1); + + tmp = apb_read_reg(2, 0x02); + tmp |= (1 << 24) | 1; /* FSM, Demod enable. */ + apb_write_reg(2, 0x02, tmp); +} + +int dvbt_set_ch(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c, + struct aml_demod_dvbt *demod_dvbt) +{ + int ret = 0; + u8 bw, sr, ifreq, agc_mode; + u32 ch_freq; + + bw = demod_dvbt->bw; + sr = demod_dvbt->sr; + ifreq = demod_dvbt->ifreq; + agc_mode = demod_dvbt->agc_mode; + ch_freq = demod_dvbt->ch_freq; + + /* Set registers */ + /*//////////////////////////////////// */ + /* bw == 0 : 8M */ + /* 1 : 7M */ + /* 2 : 6M */ + /* 3 : 5M */ + /* sr == 0 : 20.7M */ + /* 1 : 20.8333M */ + /* 2 : 28.5714M */ + /* 3 : 45M */ + /* ifreq == 0: 36.13MHz */ + /* 1: 4.57MHz */ + /* agc_mode == 0: single AGC */ + /* 1: dual AGC */ + /*//////////////////////////////////// */ + if (bw > 3) { + dprintk("Error: Invalid Bandwidth option %d\n", bw); + bw = 0; + ret = -1; + } + + if (sr > 3) { + dprintk("Error: Invalid Sampling Freq option %d\n", sr); + sr = 2; + ret = -1; + } + + if (ifreq > 1) { + dprintk("Error: Invalid IFreq option %d\n", ifreq); + ifreq = 0; + ret = -1; + } + + if (agc_mode > 3) { + dprintk("Error: Invalid AGC mode option %d\n", agc_mode); + agc_mode = 0; + ret = -1; + } + /* if (ret != 0) return ret; */ + + /* Set DVB-T */ + (*DEMOD_REG0) |= 1; + + demod_sta->dvb_mode = 1; + demod_sta->ch_mode = 0; /* TODO */ + demod_sta->agc_mode = agc_mode; + demod_sta->ch_freq = ch_freq; + if (demod_i2c->tuner == 1) + demod_sta->ch_if = 36130; + else if (demod_i2c->tuner == 2) + demod_sta->ch_if = 4570; + + demod_sta->ch_bw = (8 - bw) * 1000; + demod_sta->symb_rate = 0; /* TODO */ + + /* Set Tuner */ + if (ch_freq < 1000 || ch_freq > 900000) { + dprintk + ( + "Error: Invalid Channel Freq option %d, Skip Set tuner\n", + ch_freq); + /*ch_freq = 474000; */ + ret = -1; + } else { + /* tuner_set_ch(demod_sta, demod_i2c); */ + } + + if ((ch_freq % 100) == 2) + dprintk("Input frequency is XXX002, Skip initial demod\n"); + else + dvbt_reg_initial(demod_sta); + + dvbt_enable_irq(7); /* open symbolhead int */ + + tuner_type = demod_i2c->tuner; + + return ret; +} + +static int dvbt_get_ch_power(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c) +{ + u32 ad_power; + + ad_power = + agc_power_to_dbm((apb_read_reg(2, 0x1c) & 0x7ff), + apb_read_reg(2, 0x1b) & 0x1ff, 0, + demod_i2c->tuner); + return ad_power; +} + +int dvbt_sfo(void) +{ + int sfo; + + sfo = apb_read_reg(2, 0x47) & 0xfff; + sfo = (sfo > 0x7ff) ? (sfo - 0x1000) : sfo; + return sfo; +} + +int dvbt_fcfo(void) +{ + int fcfo; + + fcfo = (apb_read_reg(2, 0x26)) & 0xffffff; + fcfo = (fcfo > 0x7fffff) ? (fcfo - 0x1000000) : fcfo; + return fcfo; +} + +static int dvbt_total_packet_error(void) +{ + return apb_read_reg(2, 0xbf); +} + +static int dvbt_super_frame_counter(void) +{ + return apb_read_reg(2, 0xc0) & 0xfffff; +} + +static int dvbt_packet_correct_in_sframe(void) +{ + return apb_read_reg(2, 0xc1) & 0xfffff; +} + +/*static int dvbt_resync_counter(void) + * {return((apb_read_reg(2, 0xc0)>>20)&0xff);} + */ +static int dvbt_packets_per_sframe(void) +{ + u32 tmp; + int hier_mode; + int constel; + int hp_code_rate; + int lp_code_rate; + int hier_sel; + int code_rate; + int ret; + + tmp = apb_read_reg(2, 0x06); + constel = tmp >> 13 & 3; + hier_mode = tmp >> 10 & 7; + hp_code_rate = tmp >> 7 & 7; + lp_code_rate = tmp >> 4 & 7; + + if (hier_mode == 0) { + code_rate = hp_code_rate; + } else { + tmp = apb_read_reg(2, 0x78); + hier_sel = tmp >> 9 & 1; + if (hier_sel == 0) { + constel = 0; /* QPSK; */ + code_rate = hp_code_rate; + } else { + constel = constel == 2 ? 1 : 0; + code_rate = lp_code_rate; + } + } + + switch (code_rate) { + case 0: + ret = (constel == 0) ? 1008 : (constel == 1) ? 2016 : 3024; + break; + case 1: + ret = (constel == 0) ? 1344 : (constel == 1) ? 2688 : 4032; + break; + case 2: + ret = (constel == 0) ? 1512 : (constel == 1) ? 3024 : 4536; + break; + case 3: + ret = (constel == 0) ? 1680 : (constel == 1) ? 3360 : 5040; + break; + case 4: + ret = (constel == 0) ? 1764 : (constel == 1) ? 3528 : 5292; + break; + default: + ret = (constel == 0) ? 1008 : (constel == 1) ? 2016 : 3024; + break; + } + return ret; +} + +static int dvbt_get_per(void) +{ + int packets_per_sframe; + int error; + int per; + + packets_per_sframe = dvbt_packets_per_sframe(); + error = packets_per_sframe - dvbt_packet_correct_in_sframe(); + per = 1000 * error / packets_per_sframe; + + return per; +} + +static void dvbt_set_test_bus(u8 sel) +{ + u32 tmp; + + tmp = apb_read_reg(2, 0x7f); + tmp &= ~(0x1f); + tmp |= ((1 << 15) | (1 << 5) | (sel & 0x1f)); + apb_write_reg(2, 0x7f, tmp); +} + +/* + * void dvbt_get_test_out(u8 sel, u32 len, u32 *buf) + * { + * int i; + * + * dvbt_set_test_bus(sel); + * + * for (i=0; i> 10) & 0x1) { + buf[i++] = apb_read_reg(2, 0x13); + buf[i++] = apb_read_reg(2, 0x13); + buf[i++] = apb_read_reg(2, 0x13); + buf[i++] = apb_read_reg(2, 0x13); + buf[i++] = apb_read_reg(2, 0x13); + buf[i++] = apb_read_reg(2, 0x13); + buf[i++] = apb_read_reg(2, 0x13); + buf[i++] = apb_read_reg(2, 0x13); + } else { + i--; + } + + cnt++; + } +} + +static int dvbt_get_avg_per(void) +{ + int packets_per_sframe; + static int err_last; + static int err_now; + static int rsnum_now; + static int rsnum_last; + int per; + + packets_per_sframe = dvbt_packets_per_sframe(); + rsnum_last = rsnum_now; + rsnum_now = dvbt_super_frame_counter(); + err_last = err_now; + err_now = dvbt_total_packet_error(); + if (rsnum_now != rsnum_last) + per = 1000 * (err_now - err_last) / + ((rsnum_now - rsnum_last) * packets_per_sframe); + else + per = 123; + + return per; +} + +int dvbt_status(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c, + struct aml_demod_sts *demod_sts) +{ + /* if parameters are needed to calc, pass the struct to func. */ + /* all small funcs like read_snr() should be static. */ + + demod_sts->ch_snr = apb_read_reg(2, 0x0a); + demod_sts->ch_per = dvbt_get_per(); + demod_sts->ch_pow = dvbt_get_ch_power(demod_sta, demod_i2c); + demod_sts->ch_ber = apb_read_reg(2, 0x0b); + demod_sts->ch_sts = apb_read_reg(2, 0); + demod_sts->dat0 = dvbt_get_avg_per(); + demod_sts->dat1 = apb_read_reg(2, 0x06); + return 0; +} + +static int dvbt_get_status(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c) +{ + return apb_read_reg(2, 0x0) >> 12 & 1; +} + +static int dvbt_ber(void); + +static int dvbt_get_ber(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c) +{ + return dvbt_ber(); /*unit: 1e-7 */ +} + +static int dvbt_get_snr(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c) +{ + return apb_read_reg(2, 0x0a) & 0x3ff; /*dBm: bit0~bit2=decimal */ +} + +static int dvbt_get_strength(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c) +{ + int dbm = dvbt_get_ch_power(demod_sta, demod_i2c); + + return dbm; +} + +static int dvbt_get_ucblocks(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c) +{ + return dvbt_get_per(); +} + +struct demod_status_ops *dvbt_get_status_ops(void) +{ + static struct demod_status_ops ops = { + .get_status = dvbt_get_status, + .get_ber = dvbt_get_ber, + .get_snr = dvbt_get_snr, + .get_strength = dvbt_get_strength, + .get_ucblocks = dvbt_get_ucblocks, + }; + + return &ops; +} + +void dvbt_enable_irq(int dvbt_irq) +{ + /* clear status & enable irq */ + (*OFDM_INT_STS) &= ~(1 << dvbt_irq); + (*OFDM_INT_EN) |= (1 << dvbt_irq); +} + +void dvbt_disable_irq(int dvbt_irq) +{ + /* disable irq & clear status */ + (*OFDM_INT_EN) &= ~(1 << dvbt_irq); + (*OFDM_INT_STS) &= ~(1 << dvbt_irq); +} + +char *dvbt_irq_name[] = { + "PFS_FCFO", + "PFS_ICFO", + " CS_FCFO", + " PFS_SFO", + " PFS_TPS", + " SP", + " CCI", + " Symbol", + " In_Sync", + "Out_Sync", + "FSM Stat" +}; + +void dvbt_isr(struct aml_demod_sta *demod_sta) +{ + u32 stat, mask; + int dvbt_irq; + + stat = (*OFDM_INT_STS); + mask = (*OFDM_INT_EN); + stat &= mask; + + for (dvbt_irq = 0; dvbt_irq < 11; dvbt_irq++) { + if (stat >> dvbt_irq & 1) { + if (demod_sta->debug) + dprintk("irq: aml_demod dvbt %2d %s %8x %8x\n", + dvbt_irq, dvbt_irq_name[dvbt_irq], stat, + mask); + /* dvbt_disable_irq(dvbt_irq); */ + } + } + /* clear status */ + (*OFDM_INT_STS) = 0; +} + +static int demod_monitor_ave(void); +int dvbt_isr_islock(void) +{ +#define IN_SYNC_MASK (0x100) + + u32 stat, mask; + + stat = (*OFDM_INT_STS); + *OFDM_INT_STS = stat & (~IN_SYNC_MASK); + + mask = (*OFDM_INT_EN); + stat &= mask; + + return (stat & IN_SYNC_MASK) == IN_SYNC_MASK; +} + +int dvbt_isr_monitor(void) +{ +#define SYM_HEAD_MASK (0x80) + u32 stat, mask; + + stat = (*OFDM_INT_STS); + *OFDM_INT_STS = stat & (~SYM_HEAD_MASK); + + mask = (*OFDM_INT_EN); + stat &= mask; + /* symbol_head int */ + if ((stat & SYM_HEAD_MASK) == SYM_HEAD_MASK) + demod_monitor_ave(); + return 0; +} + +int dvbt_isr_cancel(void) +{ + *OFDM_INT_STS = 0; + *OFDM_INT_EN = 0; + return 0; +} + +static int demod_monitor_instant(void) +{ + int SNR; + int SNR_SP = 500; + int SNR_TPS = 0; + int SNR_CP = 0; + int SFO_residual = 0; + int SFO_esti = 0; + int FCFO_esti = 0; + int FCFO_residual = 0; + int AGC_Gain = 0; + int be_vit_error = 0; + int Signal_power = 0; + int FECFlag = 0; + int EQ_seg_ratio = 0; + int tps_0 = 0; + int tps_1 = 0; + int tps_2 = 0; + int cci_blank = 0; + + int SFO; + int FCFO; + int timing_adj; + int RS_CorrectNum; + int RS_Error_sum; + int resync_times; + int tps_summary; + + int tps_window; + int tps_guard; + int tps_constell; + int tps_Hier_none; + int tps_Hier_alpha; + int tps_HP_cr; + int tps_LP_cr; + + int tmpAGCGain; + + /* Read Registers */ + SNR = apb_read_reg(2, 0x0a); + FECFlag = (apb_read_reg(2, 0x00) >> 11) & 0x3; + SFO = apb_read_reg(2, 0x47) & 0xfff; + SFO_esti = apb_read_reg(2, 0x60) & 0xfff; + FCFO_esti = (apb_read_reg(2, 0x60) >> 11) & 0xfff; + FCFO = (apb_read_reg(2, 0x26)) & 0xffffff; + be_vit_error = apb_read_reg(2, 0x0c) & 0x1fff; + timing_adj = apb_read_reg(2, 0x6f) & 0x1fff; + RS_CorrectNum = apb_read_reg(2, 0xc1) & 0xfffff; + Signal_power = (apb_read_reg(2, 0x1b)) & 0x1ff; + EQ_seg_ratio = apb_read_reg(2, 0x6e) & 0x3ffff; + tps_0 = apb_read_reg(2, 0x64); + tps_1 = apb_read_reg(2, 0x65); + tps_2 = apb_read_reg(2, 0x66) & 0xf; + tps_summary = apb_read_reg(2, 0x04) & 0x7fff; + cci_blank = (apb_read_reg(2, 0x66) >> 16); + RS_Error_sum = apb_read_reg(2, 0xbf) & 0x3ffff; + resync_times = (apb_read_reg(2, 0xc0) >> 20) & 0xff; + AGC_Gain = apb_read_reg(2, 0x1c) & 0x7ff; + + /* Calc */ + SFO_residual = (SFO > 0x7ff) ? (SFO - 0x1000) : SFO; + FCFO_residual = (FCFO > 0x7fffff) ? (FCFO - 0x1000000) : FCFO; + FCFO_esti = (FCFO_esti > 0x7ff) ? (FCFO_esti - 0x1000) : FCFO_esti; + SNR_CP = (SNR) & 0x3ff; + SNR_TPS = (SNR >> 10) & 0x3ff; + SNR_SP = (SNR >> 20) & 0x3ff; + SNR_SP = (SNR_SP > 0x1ff) ? SNR_SP - 0x400 : SNR_SP; + SNR_TPS = (SNR_TPS > 0x1ff) ? SNR_TPS - 0x400 : SNR_TPS; + SNR_CP = (SNR_CP > 0x1ff) ? SNR_CP - 0x400 : SNR_CP; + tmpAGCGain = AGC_Gain; + timing_adj = (timing_adj > 0xfff) ? timing_adj - 0x2000 : timing_adj; + + tps_window = (tps_summary & 0x3); + tps_guard = ((tps_summary >> 2) & 0x3); + tps_constell = ((tps_summary >> 13) & 0x3); + tps_Hier_none = (((tps_summary >> 10) & 0x7) == 0) ? 1 : 0; + tps_Hier_alpha = (tps_summary >> 11) & 0x3; + tps_Hier_alpha = (tps_Hier_alpha == 3) ? 4 : tps_Hier_alpha; + tps_LP_cr = (tps_summary >> 4) & 0x7; + tps_HP_cr = (tps_summary >> 7) & 0x7; + + dprintk("\n\n"); + switch (tps_window) { + case 0: + dprintk("2K "); + break; + case 1: + dprintk("8K "); + break; + case 2: + dprintk("4K "); + break; + default: + dprintk("UnWin "); + break; + } + switch (tps_guard) { + case 0: + dprintk("1/32 "); + break; + case 1: + dprintk("1/16 "); + break; + case 2: + dprintk("1/ 8 "); + break; + case 3: + dprintk("1/ 4 "); + break; + default: + dprintk("UnGuard "); + break; + } + switch (tps_constell) { + case 0: + dprintk(" QPSK "); + break; + case 1: + dprintk("16QAM "); + break; + case 2: + dprintk("64QAM "); + break; + default: + dprintk("UnConstl "); + break; + } + switch (tps_Hier_none) { + case 0: + dprintk("Hiera "); + break; + case 1: + dprintk("non-H "); + break; + default: + dprintk("UnHier "); + break; + } + dprintk("%d ", tps_Hier_alpha); + dprintk("HP "); + switch (tps_HP_cr) { + case 0: + dprintk("1/2 "); + break; + case 1: + dprintk("2/3 "); + break; + case 2: + dprintk("3/4 "); + break; + case 3: + dprintk("5/6 "); + break; + case 4: + dprintk("7/8 "); + break; + default: + dprintk("UnHCr "); + break; + } + dprintk("LP "); + switch (tps_LP_cr) { + case 0: + dprintk("1/2 "); + break; + case 1: + dprintk("2/3 "); + break; + case 2: + dprintk("3/4 "); + break; + case 3: + dprintk("5/6 "); + break; + case 4: + dprintk("7/8 "); + break; + default: + dprintk("UnLCr "); + break; + } + dprintk("\n"); + dprintk("P %4x ", RS_Error_sum); + dprintk("SP %2d ", SNR_SP); + dprintk("TPS %2d ", SNR_TPS); + dprintk("CP %2d ", SNR_CP); + dprintk("EQS %2x ", EQ_seg_ratio); + dprintk("RSC %4d ", RS_CorrectNum); + dprintk("SFO %3d ", SFO_residual); + dprintk("FCFO %4d ", FCFO_residual); + dprintk("Vit %3x ", be_vit_error); + dprintk("Timing %3d ", timing_adj); + dprintk("SigP %3x ", Signal_power); + dprintk("AGC %d ", tmpAGCGain); + dprintk("SigP %d ", + agc_power_to_dbm(tmpAGCGain, Signal_power, 0, tuner_type)); + dprintk("FEC %x ", FECFlag); + dprintk("ReSyn %x ", resync_times); + dprintk("cciB %x", cci_blank); + + dprintk("\n"); + + return 0; +} + +int serial_div(int a, int b) +{ + int c; + int cnt; + int b_buf; + + if (b == 0) + return 0x7fffffff; + if (a == 0) + return 0; + + c = 0; + cnt = 0; + + a = (a < 0) ? -1 * a : a; + b = (b < 0) ? -1 * b : b; + + b_buf = b; + + while (a >= b) { + b = b << 1; + cnt++; + } + while (b > b_buf) { + b = b >> 1; + c = c << 1; + if (a > b) { + c = c + 1; + a = a - b; + } + } + return c; +} + +static int ave0, bit_unit_L; + +static int dvbt_ber(void) +{ + int BER_e_n7 = serial_div(ave0 * 40, bit_unit_L); + + return BER_e_n7; +} + +static int demod_monitor_ave(void) +{ + static int i; + static int ave[3] = { 0, 0, 0 }; + + ave[0] = ave[0] + (apb_read_reg(2, 0x0b) & 0x7ff); + ave[1] = ave[1] + (apb_read_reg(2, 0x0a) & 0x3ff); + ave[2] = ave[2] + (apb_read_reg(2, 0x0c) & 0x1fff); + + i++; + + if (i >= 8192) { + int tps_mode; + int tps_constell; + int r_t; + int mode_L; + int const_L; + int SNR_Int; + int SNR_fra; + + if (debug_amldvbt) + demod_monitor_instant(); + + r_t = apb_read_reg(2, 0x04); + tps_mode = r_t & 0x3; + tps_constell = (r_t >> 13) & 0x3; + mode_L = (tps_mode == 0) ? 1 : (tps_mode == 1) ? 4 : 2; + const_L = (tps_constell == 0) ? 2 : (tps_constell == 1) ? 4 : 6; + bit_unit_L = 189 * mode_L * const_L; + SNR_Int = (ave[1] >> 16); + switch ((ave[1] >> 13) & 0x7) { + case 0: + SNR_fra = 0; + break; + case 1: + SNR_fra = 125; + break; + case 2: + SNR_fra = 250; + break; + case 3: + SNR_fra = 375; + break; + case 4: + SNR_fra = 500; + break; + case 5: + SNR_fra = 625; + break; + case 6: + SNR_fra = 750; + break; + case 7: + SNR_fra = 875; + break; + default: + SNR_fra = 0; + break; + } + + ave0 = ave[0]; + + if (debug_amldvbt) + dprintk("RSBi %d Thresh %d SNR %d.%d Vit %x\n\n", + (ave[0] >> 3) * 5, (bit_unit_L * 8), SNR_Int, + SNR_fra, (ave[2] >> 13)); + i = 0; + ave[0] = ave[1] = ave[2] = 0; + } + + return i; +} + +int dvbt_switch_to_HP(void) +{ + apb_write_reg(2, 0x78, apb_read_reg(2, 0x78) & ~(1 << 9)); + return 0; +} + +int dvbt_switch_to_LP(void) +{ + apb_write_reg(2, 0x78, apb_read_reg(2, 0x78) | (1 << 9)); + return 0; +} + +int dvbt_shutdown(void) +{ + apb_write_reg(2, 0x02, 0x00800000); + /* SW reset bit[23] ; write anything to zero */ + apb_write_reg(2, 0x00, 0x00000000); + return 0; +} + +int dvbt_get_params(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *adap, int *code_rate_HP, + /* high priority stream code rate */ + int *code_rate_LP, /* low priority stream code rate */ + int *constellation, /* modulation type (see above) */ + int *transmission_mode, + int *guard_interval, int *hierarchy_information) +{ + int tps_summary, tps_window, tps_guard, tps_constell, tps_Hier_none; + int tps_Hier_alpha, tps_LP_cr, tps_HP_cr; + + tps_summary = apb_read_reg(2, 0x04) & 0x7fff; + tps_window = (tps_summary & 0x3); + tps_guard = ((tps_summary >> 2) & 0x3); + tps_constell = ((tps_summary >> 13) & 0x3); + tps_Hier_none = (((tps_summary >> 10) & 0x7) == 0) ? 1 : 0; + tps_Hier_alpha = (tps_summary >> 11) & 0x3; + tps_Hier_alpha = (tps_Hier_alpha == 3) ? 4 : tps_Hier_alpha; + tps_LP_cr = (tps_summary >> 4) & 0x7; + tps_HP_cr = (tps_summary >> 7) & 0x7; + if (code_rate_HP) + *code_rate_HP = tps_HP_cr; /*1/2:2/3:3/4:5/6:7/8 */ + if (code_rate_LP) + *code_rate_LP = tps_LP_cr; /*1/2:2/3:3/4:5/6:7/8 */ + if (constellation) + *constellation = tps_constell; /*QPSK/16QAM/64QAM */ + if (transmission_mode) + *transmission_mode = tps_window; /*2K/8K/4K */ + if (guard_interval) + *guard_interval = tps_guard; /*1/32:1/16:1/8:1/4 */ + if (hierarchy_information) + *hierarchy_information = tps_Hier_alpha; /*1/2/4 */ + return 0; +} diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/i2c_func.c b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/i2c_func.c new file mode 100644 index 000000000000..7edef46742ff --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/i2c_func.c @@ -0,0 +1,23 @@ +#include +#include +#include +#include +#include "demod_func.h" + +int am_demod_i2c_xfer(struct aml_demod_i2c *adap, struct i2c_msg msgs[], + int num) +{ + int ret = 0; + + if (adap->scl_oe) { + /* ret = aml_i2c_sw_bit_xfer(adap, msgs, num);*/ + } else { + if (adap->i2c_priv) + ret = i2c_transfer((struct i2c_adapter *)adap->i2c_priv, + msgs, num); + else + ; + /* printk("i2c error, no valid i2c\n");*/ + } + return ret; +} diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/acf_filter_coefficient.h b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/acf_filter_coefficient.h new file mode 100644 index 000000000000..b1437a2cdab2 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/acf_filter_coefficient.h @@ -0,0 +1,395 @@ +void program_acf(int acf1[20], int acf2[33]) +{ + int i; + + for (i = 0; i < 20; i++) + apb_write_reg(DVBT_BASE + (0x2c + i) * 4, acf1[i]); + for (i = 0; i < 33; i++) { + apb_write_reg(DVBT_BASE + 0xfe * 4, i); + apb_write_reg(DVBT_BASE + 0xff * 4, acf2[i]); + } +} + +void ini_acf_iireq_src_45m_8m(void) +{ + int acf1[] = { 0x294, 0x085, 0x076, 0x01e, + 0x27c, 0x0af, 0x2bf, 0x06d, + 0x265, 0x0d8, 0x270, 0x05e, + 0x257, 0x0ef, 0x25b, 0x04b, + 0x24f, 0x0fc, 0x254, 0x04d + }; + int acf2[] = { 0x3f3fff, 0x3da7cd, 0x3c0f9b, 0x3a7768, 0x38df35, + 0x373f01, + 0x3596cd, 0x33ee98, 0x323e62, 0x307e2b, 0x2eb5f3, + 0x2ce5b9, + 0x2b057e, 0x290d41, 0x26fd00, 0x24dcbd, 0x229477, + 0x202c2c, + 0x1d93dc, 0x1ac386, 0x17b328, 0x144ac1, 0x106a4d, + 0x0be1c8, + 0x07e129, 0x04d0cc, 0x015064, 0x3d47ec, 0x38675e, + 0x326eb1, + 0x326e4d, 0x326e4d, 0x00064d + }; + + program_acf(acf1, acf2); +} + +void ini_acf_iireq_src_45m_7m(void) +{ + int acf1[] = { 0x283, 0x091, 0x02f, 0x01e, + 0x26a, 0x0b8, 0x296, 0x06d, + 0x253, 0x0dc, 0x257, 0x05e, + 0x245, 0x0f1, 0x246, 0x04b, + 0x23d, 0x0fc, 0x241, 0x04d + }; + int acf2[] = { 0x3f3fff, 0x3dafce, 0x3c1f9c, 0x3a8769, 0x38ef37, + 0x374f03, + 0x35aecf, 0x34069b, 0x325665, 0x30962e, 0x2ecdf6, + 0x2cfdbc, + 0x2b1581, 0x291d43, 0x271503, 0x24e4bf, 0x229c78, + 0x202c2d, + 0x1d8bdc, 0x1ab384, 0x179325, 0x141abc, 0x102a46, + 0x0b81be, + 0x07711c, 0x0448bd, 0x00b052, 0x3c7fd6, 0x374740, + 0x308684, + 0x308610, 0x308610, 0x000610 + }; + + program_acf(acf1, acf2); +} + +void ini_acf_iireq_src_45m_6m(void) +{ + int acf1[] = { 0x272, 0x09e, 0x3dc, 0x01e, + 0x259, 0x0c0, 0x272, 0x06d, + 0x242, 0x0e1, 0x240, 0x05e, + 0x235, 0x0f3, 0x234, 0x04b, + 0x22e, 0x0fd, 0x230, 0x04d + }; + int acf2[] = { 0x3f47ff, 0x3dbfcf, 0x3c379e, 0x3aa76d, 0x391f3c, + 0x378709, + 0x35e6d6, 0x343ea2, 0x328e6d, 0x30d636, 0x2f0dfe, + 0x2d35c4, + 0x2b4d88, 0x294d49, 0x273d08, 0x2504c4, 0x22b47c, + 0x203c2f, + 0x1d9bde, 0x1ac386, 0x17a327, 0x1432bf, 0x104249, + 0x0ba9c2, + 0x07a922, 0x0490c5, 0x01185c, 0x3d0fe5, 0x383f58, + 0x3286af, + 0x328650, 0x328650, 0x000650 + }; + + program_acf(acf1, acf2); +} + +void ini_acf_iireq_src_45m_5m(void) +{ + int acf1[] = { 0x260, 0x0ab, 0x37e, 0x02e, + 0x249, 0x0ca, 0x251, 0x06d, + 0x233, 0x0e6, 0x22d, 0x05e, + 0x227, 0x0f5, 0x224, 0x04b, + 0x220, 0x0fd, 0x221, 0x04d + }; + int acf2[] = { 0x3f3fff, 0x3db7cf, 0x3c279d, 0x3a9f6c, 0x39073a, + 0x377707, + 0x35d6d4, 0x3436a0, 0x328e6b, 0x30d636, 0x2f15ff, + 0x2d4dc6, + 0x2b758c, 0x29854f, 0x278511, 0x256ccf, 0x232c89, + 0x20cc3f, + 0x1e33f0, 0x1b6b9b, 0x185b3d, 0x14e2d5, 0x10f260, + 0x0c51d7, + 0x082934, 0x04f8d4, 0x014066, 0x3ccfe4, 0x372f46, + 0x2f5673, + 0x2f55ea, 0x2f55ea, 0x0005ea + }; + + program_acf(acf1, acf2); +} + +void ini_acf_iireq_src_2857m_8m(void) +{ + int acf1[] = { 0x2df, 0x059, 0x144, 0x00e, + 0x2d3, 0x08f, 0x38d, 0x06f, + 0x2c6, 0x0c5, 0x302, 0x05e, + 0x2be, 0x0e7, 0x2d6, 0x04b, + 0x2b7, 0x0f9, 0x2c8, 0x04d + }; + int acf2[] = { 0x3f3fff, 0x3dbfcf, 0x3c379e, 0x3aaf6d, 0x391f3c, + 0x37870a, + 0x35eed7, 0x344ea3, 0x32a66f, 0x30f639, 0x2f3602, + 0x2d65c9, + 0x2b858e, 0x299552, 0x278d12, 0x2564cf, 0x231c88, + 0x20b43d, + 0x1e13ec, 0x1b3395, 0x181336, 0x1492cc, 0x109254, + 0x0be1cb, + 0x07c127, 0x0498c7, 0x00f85b, 0x3cbfde, 0x377747, + 0x309e88, + 0x309e13, 0x309e13, 0x000613 + }; + + program_acf(acf1, acf2); +} + +void ini_acf_iireq_src_2857m_7m(void) +{ + int acf1[] = { 0x2c6, 0x067, 0x10f, 0x01e, + 0x2b4, 0x099, 0x344, 0x06f, + 0x2a2, 0x0cb, 0x2cb, 0x05e, + 0x297, 0x0ea, 0x2a7, 0x04b, + 0x28f, 0x0fa, 0x29c, 0x04d + }; + int acf2[] = { 0x3f3fff, 0x3dbfcf, 0x3c379e, 0x3aa76d, 0x39173b, + 0x378709, + 0x35e6d6, 0x3446a2, 0x329e6d, 0x30e637, 0x2f2600, + 0x2d4dc7, + 0x2b6d8c, 0x297d4e, 0x276d0e, 0x2544cb, 0x22fc84, + 0x208438, + 0x1de3e7, 0x1b0b90, 0x17eb30, 0x146ac7, 0x107250, + 0x0bc9c6, + 0x07b124, 0x0490c5, 0x00f85b, 0x3cc7df, 0x37974a, + 0x30ce8d, + 0x30ce19, 0x30ce19, 0x000619 + }; + + program_acf(acf1, acf2); +} + +void ini_acf_iireq_src_2857m_6m(void) +{ + int acf1[] = { 0x2ac, 0x076, 0x0c9, 0x01e, + 0x297, 0x0a4, 0x2fd, 0x06d, + 0x281, 0x0d2, 0x299, 0x05e, + 0x274, 0x0ed, 0x27d, 0x04b, + 0x26c, 0x0fb, 0x274, 0x04d + }; + int acf2[] = { 0x3f3fff, 0x3db7cf, 0x3c279d, 0x3a976b, 0x390739, + 0x376f07, + 0x35ced3, 0x342e9f, 0x327e6a, 0x30c634, 0x2f05fc, + 0x2d35c4, + 0x2b5d89, 0x29654c, 0x275d0c, 0x253cca, 0x22fc83, + 0x209439, + 0x1dfbe9, 0x1b2b93, 0x181b35, 0x14b2ce, 0x10ca5a, + 0x0c41d4, + 0x084935, 0x0538d9, 0x01c071, 0x3db7fa, 0x38bf6b, + 0x327eb9, + 0x327e4f, 0x327e4f, 0x00064f + }; + + program_acf(acf1, acf2); +} + +void ini_acf_iireq_src_2857m_5m(void) +{ + int acf1[] = { 0x292, 0x087, 0x06e, 0x01e, + 0x27a, 0x0b0, 0x2b9, 0x06d, + 0x262, 0x0d8, 0x26d, 0x05e, + 0x254, 0x0f0, 0x258, 0x04b, + 0x24c, 0x0fc, 0x252, 0x04d + }; + int acf2[] = { 0x3f3fff, 0x3db7ce, 0x3c279d, 0x3a976b, 0x38ff38, + 0x376706, + 0x35c6d2, 0x341e9d, 0x326e68, 0x30ae31, 0x2eedf9, + 0x2d15c0, + 0x2b2d84, 0x293546, 0x272506, 0x24fcc2, 0x22ac7b, + 0x203c2f, + 0x1d9bde, 0x1ac386, 0x17a327, 0x1422be, 0x103247, + 0x0b91bf, + 0x07891e, 0x0470c1, 0x00e858, 0x3ccfde, 0x37bf4d, + 0x313e96, + 0x313e27, 0x313e27, 0x000627 + }; + + program_acf(acf1, acf2); +} + +void ini_acf_iireq_src_24m_8m(void) +{ + int acf1[] = { 0x303, 0x048, 0x17e, 0x00e, + 0x302, 0x081, 0x3f8, 0x00a, + 0x300, 0x0bd, 0x35b, 0x05e, + 0x2fe, 0x0e3, 0x325, 0x04b, + 0x2fb, 0x0f8, 0x313, 0x04d + }; + int acf2[] = { 0x3f47ff, 0x3dc7d0, 0x3c3fa0, 0x3abf6f, 0x392f3e, + 0x37a70d, + 0x360eda, 0x346ea7, 0x32c673, 0x31163d, 0x2f5606, + 0x2d8dce, + 0x2bad93, 0x29bd56, 0x27b517, 0x258cd4, 0x23448d, + 0x20cc41, + 0x1e2bf0, 0x1b4b98, 0x182338, 0x149ace, 0x109255, + 0x0bd1ca, + 0x07a123, 0x0468c2, 0x00b054, 0x3c5fd4, 0x37073a, + 0x302e79, + 0x302e05, 0x302e05, 0x000605 + }; + + program_acf(acf1, acf2); +} + +void ini_acf_iireq_src_24m_7m(void) +{ + int acf1[] = { 0x2e7, 0x055, 0x153, 0x00e, + 0x2dd, 0x08b, 0x3a5, 0x06f, + 0x2d2, 0x0c4, 0x315, 0x05e, + 0x2cb, 0x0e6, 0x2e7, 0x04b, + 0x2c5, 0x0f9, 0x2d8, 0x04d + }; + int acf2[] = { 0x3f3fff, 0x3dbfcf, 0x3c379e, 0x3aaf6d, 0x391f3c, + 0x37870a, + 0x35eed7, 0x344ea3, 0x32a66f, 0x30ee39, 0x2f2e02, + 0x2d65c9, + 0x2b858e, 0x298d51, 0x278511, 0x255cce, 0x231487, + 0x20a43c, + 0x1e0beb, 0x1b3394, 0x181335, 0x1492cb, 0x109254, + 0x0be1ca, + 0x07b925, 0x0480c5, 0x00d858, 0x3c87d8, 0x373740, + 0x305e80, + 0x305e0b, 0x305e0b, 0x00060b + }; + + program_acf(acf1, acf2); +} + +void ini_acf_iireq_src_24m_6m(void) +{ + int acf1[] = { 0x2c9, 0x065, 0x118, 0x01e, + 0x2b9, 0x097, 0x34f, 0x06f, + 0x2a7, 0x0ca, 0x2d3, 0x05e, + 0x29c, 0x0e9, 0x2ae, 0x04b, + 0x295, 0x0fa, 0x2a2, 0x04d + }; + int acf2[] = { 0x3f3fff, 0x3db7cf, 0x3c2f9d, 0x3a9f6c, 0x390f3a, + 0x377707, + 0x35d6d4, 0x342ea0, 0x32866b, 0x30ce34, 0x2f05fd, + 0x2d35c3, + 0x2b5588, 0x295d4b, 0x27550b, 0x252cc8, 0x22dc80, + 0x206c35, + 0x1dcbe4, 0x1af38c, 0x17cb2d, 0x144ac3, 0x104a4b, + 0x0b99c1, + 0x07791d, 0x0448be, 0x00b052, 0x3c6fd4, 0x37473f, + 0x30c686, + 0x30c618, 0x30c618, 0x000618 + }; + + program_acf(acf1, acf2); +} + +void ini_acf_iireq_src_24m_5m(void) +{ + int acf1[] = { 0x2ab, 0x077, 0x0c6, 0x01e, + 0x295, 0x0a5, 0x2fa, 0x06d, + 0x27f, 0x0d2, 0x297, 0x05e, + 0x272, 0x0ed, 0x27b, 0x04b, + 0x26a, 0x0fb, 0x272, 0x04d + }; + int acf2[] = { 0x3f3fff, 0x3db7cf, 0x3c2f9e, 0x3aa76c, 0x39173b, + 0x377f08, + 0x35ded5, 0x343ea1, 0x328e6c, 0x30de36, 0x2f15ff, + 0x2d45c6, + 0x2b658a, 0x29754d, 0x27650d, 0x253cca, 0x22f483, + 0x208438, + 0x1de3e7, 0x1b0b90, 0x17eb30, 0x1472c7, 0x107a51, + 0x0bd9c8, + 0x07c927, 0x04a8c9, 0x01205f, 0x3cf7e4, 0x37e752, + 0x31669a, + 0x31662c, 0x31662c, 0x00062c + }; + + program_acf(acf1, acf2); +} + +void ini_acf_iireq_src_207m_8m(void) +{ + int acf1[] = { 0x327, 0x039, 0x1a5, 0x07b, + 0x332, 0x076, 0x05c, 0x06e, + 0x33e, 0x0b6, 0x3b8, 0x05e, + 0x344, 0x0e0, 0x37a, 0x04b, + 0x345, 0x0f7, 0x365, 0x04d + }; + int acf2[] = { 0x3f47ff, 0x3dcfd1, 0x3c57a1, 0x3ad772, 0x394f42, + 0x37c711, + 0x3636df, 0x34a6ad, 0x32fe7a, 0x315645, 0x2f9e0f, + 0x2dd5d7, + 0x2bfd9d, 0x2a0d61, 0x280d21, 0x25e4df, 0x239c98, + 0x212c4d, + 0x1e8bfc, 0x1baba4, 0x188344, 0x14fad9, 0x10ea61, + 0x0c29d4, + 0x07e92d, 0x04a8cb, 0x00f05c, 0x3c87da, 0x371f3e, + 0x30267a, + 0x302604, 0x302604, 0x000604 + }; + + program_acf(acf1, acf2); +} + +void ini_acf_iireq_src_207m_7m(void) +{ + int acf1[] = { 0x307, 0x046, 0x182, 0x00e, + 0x306, 0x080, 0x002, 0x00a, + 0x306, 0x0bd, 0x364, 0x05e, + 0x304, 0x0e3, 0x32d, 0x04b, + 0x301, 0x0f8, 0x31b, 0x04d + }; + int acf2[] = { 0x3f47ff, 0x3dc7d0, 0x3c47a0, 0x3abf6f, 0x39373f, + 0x37a70d, + 0x3616db, 0x3476a8, 0x32d674, 0x31263f, 0x2f6608, + 0x2d9dd0, + 0x2bbd96, 0x29d559, 0x27cd19, 0x25a4d7, 0x235c90, + 0x20ec45, + 0x1e53f4, 0x1b739d, 0x18533d, 0x14d2d4, 0x10d25c, + 0x0c19d1, + 0x07e12c, 0x04a8ca, 0x00f05c, 0x3c8fdb, 0x372740, + 0x302e7c, + 0x302e05, 0x302e05, 0x000605 + }; + + program_acf(acf1, acf2); +} + +void ini_acf_iireq_src_207m_6m(void) +{ + int acf1[] = { 0x2e6, 0x056, 0x151, 0x00e, + 0x2db, 0x08c, 0x3a1, 0x06f, + 0x2d0, 0x0c4, 0x312, 0x05e, + 0x2c9, 0x0e6, 0x2e4, 0x04b, + 0x2c3, 0x0f9, 0x2d6, 0x04d + }; + int acf2[] = { 0x3f47ff, 0x3dbfd0, 0x3c3f9f, 0x3ab76e, 0x39273d, + 0x37970b, + 0x35fed9, 0x345ea5, 0x32b671, 0x31063b, 0x2f4604, + 0x2d75cb, + 0x2b9590, 0x29a553, 0x279513, 0x256cd0, 0x232489, + 0x20b43d, + 0x1e0bec, 0x1b3395, 0x180b35, 0x148acb, 0x108253, + 0x0bd1c8, + 0x07a123, 0x0470c2, 0x00c055, 0x3c77d6, 0x372f3e, + 0x306e80, + 0x306e0d, 0x306e0d, 0x00060d + }; + + program_acf(acf1, acf2); +} + +void ini_acf_iireq_src_207m_5m(void) +{ + int acf1[] = { 0x2c3, 0x068, 0x109, 0x01e, + 0x2b1, 0x09a, 0x33d, 0x06f, + 0x29f, 0x0cc, 0x2c6, 0x05e, + 0x293, 0x0ea, 0x2a3, 0x04b, + 0x28c, 0x0fa, 0x298, 0x04d + }; + int acf2[] = { 0x3f3fff, 0x3db7ce, 0x3c279d, 0x3a976b, 0x38ff38, + 0x376706, + 0x35c6d2, 0x341e9e, 0x327669, 0x30be32, 0x2ef5fb, + 0x2d25c1, + 0x2b4586, 0x295549, 0x274509, 0x251cc6, 0x22dc80, + 0x206c34, + 0x1dcbe4, 0x1afb8d, 0x17db2e, 0x1462c5, 0x106a4f, + 0x0bc9c6, + 0x07b124, 0x0488c5, 0x00e859, 0x3cafdc, 0x377f47, + 0x30ee8c, + 0x30ee1d, 0x30ee1d, 0x00061d + }; + + program_acf(acf1, acf2); +} diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_che.h b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_che.h new file mode 100644 index 000000000000..01ff78361d2b --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_che.h @@ -0,0 +1,58 @@ +#ifndef __ADDR_DTMB_CHE_H__ +#define __ADDR_DTMB_CHE_H__ + +#include "addr_dtmb_top.h" + +#define DTMB_CHE_ADDR(x) (DTMB_DEMOD_BASE + (x << 2)) + +#define DTMB_CHE_TE_HREB_SNR DTMB_CHE_ADDR(0x8d) +#define DTMB_CHE_MC_SC_TIMING_POWTHR DTMB_CHE_ADDR(0x8e) +#define DTMB_CHE_MC_SC_PROTECT_GD DTMB_CHE_ADDR(0x8f) +#define DTMB_CHE_TIMING_LIMIT DTMB_CHE_ADDR(0x90) +#define DTMB_CHE_TPS_CONFIG DTMB_CHE_ADDR(0x91) +#define DTMB_CHE_FD_TD_STEPSIZE DTMB_CHE_ADDR(0x92) +#define DTMB_CHE_QSTEP_SET DTMB_CHE_ADDR(0x93) +#define DTMB_CHE_SEG_CONFIG DTMB_CHE_ADDR(0x94) +#define DTMB_CHE_FD_TD_LEAKSIZE_CONFIG1 DTMB_CHE_ADDR(0x95) +#define DTMB_CHE_FD_TD_LEAKSIZE_CONFIG2 DTMB_CHE_ADDR(0x96) +#define DTMB_CHE_FD_TD_COEFF DTMB_CHE_ADDR(0x97) +#define DTMB_CHE_M_CCI_THR_CONFIG1 DTMB_CHE_ADDR(0x98) +#define DTMB_CHE_M_CCI_THR_CONFIG2 DTMB_CHE_ADDR(0x99) +#define DTMB_CHE_M_CCI_THR_CONFIG3 DTMB_CHE_ADDR(0x9a) +#define DTMB_CHE_CCIDET_CONFIG DTMB_CHE_ADDR(0x9b) +#define DTMB_CHE_IBDFE_CONFIG1 DTMB_CHE_ADDR(0x9d) +#define DTMB_CHE_IBDFE_CONFIG2 DTMB_CHE_ADDR(0x9e) +#define DTMB_CHE_IBDFE_CONFIG3 DTMB_CHE_ADDR(0x9f) +#define DTMB_CHE_TD_COEFF DTMB_CHE_ADDR(0xa0) +#define DTMB_CHE_FD_TD_STEPSIZE_ADJ DTMB_CHE_ADDR(0xa1) +#define DTMB_CHE_FD_COEFF_FRZ DTMB_CHE_ADDR(0xa2) +#define DTMB_CHE_FD_COEFF DTMB_CHE_ADDR(0xa3) +#define DTMB_CHE_FD_LEAKSIZE DTMB_CHE_ADDR(0xa4) +#define DTMB_CHE_IBDFE_CONFIG4 DTMB_CHE_ADDR(0xa5) +#define DTMB_CHE_IBDFE_CONFIG5 DTMB_CHE_ADDR(0xa6) +#define DTMB_CHE_IBDFE_CONFIG6 DTMB_CHE_ADDR(0xa7) +#define DTMB_CHE_IBDFE_CONFIG7 DTMB_CHE_ADDR(0xa8) +#define DTMB_CHE_DCM_SC_MC_GD_LEN DTMB_CHE_ADDR(0xa9) +#define DTMB_CHE_EQMC_PICK_THR DTMB_CHE_ADDR(0xaa) +#define DTMB_CHE_EQMC_THRESHOLD DTMB_CHE_ADDR(0xab) +#define DTMB_CHE_EQSC_PICK_THR DTMB_CHE_ADDR(0xad) +#define DTMB_CHE_EQSC_THRESHOLD DTMB_CHE_ADDR(0xae) +#define DTMB_CHE_PROTECT_GD_TPS DTMB_CHE_ADDR(0xaf) +#define DTMB_CHE_FD_TD_STEPSIZE_THR1 DTMB_CHE_ADDR(0xb0) +#define DTMB_CHE_TDFD_SWITCH_SYM1 DTMB_CHE_ADDR(0xb1) +#define DTMB_CHE_TDFD_SWITCH_SYM2 DTMB_CHE_ADDR(0xb2) +#define DTMB_CHE_EQ_CONFIG DTMB_CHE_ADDR(0xb3) +#define DTMB_CHE_EQSC_SNR_IMP_THR1 DTMB_CHE_ADDR(0xb4) +#define DTMB_CHE_EQSC_SNR_IMP_THR2 DTMB_CHE_ADDR(0xb5) +#define DTMB_CHE_EQMC_SNR_IMP_THR1 DTMB_CHE_ADDR(0xb6) +#define DTMB_CHE_EQMC_SNR_IMP_THR2 DTMB_CHE_ADDR(0xb7) +#define DTMB_CHE_EQSC_SNR_DROP_THR DTMB_CHE_ADDR(0xb8) +#define DTMB_CHE_EQMC_SNR_DROP_THR DTMB_CHE_ADDR(0xb9) +#define DTMB_CHE_M_CCI_THR DTMB_CHE_ADDR(0xba) +#define DTMB_CHE_TPS_MC DTMB_CHE_ADDR(0xbb) +#define DTMB_CHE_TPS_SC DTMB_CHE_ADDR(0xbc) +#define DTMB_CHE_CHE_SET_FSM DTMB_CHE_ADDR(0xbd) +#define DTMB_CHE_ZERO_NUM_THR DTMB_CHE_ADDR(0xbe) +#define DTMB_CHE_TIMING_READY DTMB_CHE_ADDR(0xbf) + +#endif diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_che_bit.h b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_che_bit.h new file mode 100644 index 000000000000..edb848c9e676 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_che_bit.h @@ -0,0 +1,247 @@ +#ifndef __ADDR_DTMB_CHE_BIT_H__ +#define __ADDR_DTMB_CHE_BIT_H__ + +struct DTMB_CHE_TE_HREB_SNR_BITS { + unsigned int te_hreb_snr:21, reserved0:11; +}; +struct DTMB_CHE_MC_SC_TIMING_POWTHR_BITS { + unsigned int mc_timing_powthr1:5, + reserved1:3, + mc_timing_powthr0:5, + reserved2:2, + sc_timing_powthr1:5, reserved3:4, sc_timing_powthr0:5, reserved4:3; +}; +struct DTMB_CHE_MC_SC_PROTECT_GD_BITS { + unsigned int h_valid:2, + reserved5:2, + dist:3, + reserved6:1, + ma_size:3, + reserved7:1, + mc_protect_gd:5, reserved8:3, sc_protect_gd:5, reserved9:7; +}; +struct DTMB_CHE_TIMING_LIMIT_BITS { + unsigned int ncoh_thd:3, + reserved10:1, + coh_thd:3, + reserved11:1, + strong_loc_thd:8, reserved12:4, timing_limit:5, reserved13:7; +}; +struct DTMB_CHE_TPS_CONFIG_BITS { + unsigned int tps_pst_num:5, + reserved14:3, + tps_pre_num:5, reserved15:3, chi_power_thr:8, reserved16:8; +}; +struct DTMB_CHE_FD_TD_STEPSIZE_BITS { + unsigned int fd_stepsize_thr03:5, + fd_stepsize_thr02:5, + fd_stepsize_thr01:5, + td_stepsize_thr03:5, + td_stepsize_thr02:5, td_stepsize_thr01:5, reserved17:2; +}; +struct DTMB_CHE_QSTEP_SET_BITS { + unsigned int factor_stable_thres:10, + reserved18:2, qstep_set:13, qstep_set_val:1, reserved19:6; +}; +struct DTMB_CHE_SEG_CONFIG_BITS { + unsigned int seg_bypass:1, + seg_num_1seg_log2:3, + seg_alpha:3, + seg_read_val:1, seg_read_addr:12, noise_input_shift:4, reserved20:8; +}; +struct DTMB_CHE_FD_TD_LEAKSIZE_CONFIG1_BITS { + unsigned int fd_leaksize_thr03:5, + fd_leaksize_thr02:5, + fd_leaksize_thr01:5, + td_leaksize_thr03:5, + td_leaksize_thr02:5, td_leaksize_thr01:5, reserved21:2; +}; +struct DTMB_CHE_FD_TD_LEAKSIZE_CONFIG2_BITS { + unsigned int fd_leaksize_thr13:5, + fd_leaksize_thr12:5, + fd_leaksize_thr11:5, + td_leaksize_thr13:5, + td_leaksize_thr12:5, td_leaksize_thr11:5, reserved22:2; +}; +struct DTMB_CHE_FD_TD_COEFF_BITS { + unsigned int td_coeff_frz:14, + reserved23:2, + td_coeff_addr:4, + td_coeff_init:1, + td_coeff_rst:1, + fd_coeff_init:1, + fd_coeff_done:1, + fd_coeff_rst:1, td_coeff_done:1, fd_coeff_addr:5, reserved24:1; +}; +struct DTMB_CHE_M_CCI_THR_CONFIG1_BITS { + unsigned int m_cci_thr_mc1:10, + m_cci_thr_mc2:10, m_cci_thr_mc3:10, reserved25:2; +}; +struct DTMB_CHE_M_CCI_THR_CONFIG2_BITS { + unsigned int m_cci_thr_sc2:10, + m_cci_thr_sc3:10, m_cci_thr_mc0:10, reserved26:2; +}; +struct DTMB_CHE_M_CCI_THR_CONFIG3_BITS { + unsigned int m_cci_thr_ma:10, + m_cci_thr_sc0:10, m_cci_thr_sc1:10, reserved27:2; +}; +struct DTMB_CHE_CCIDET_CONFIG_BITS { + unsigned int ccidet_dly:7, + ccidet_malpha:3, + ccidet_sc_mask_rng:5, + ccidet_mc_mask_rng:5, + ccidet_masize:4, + ccidect_sat_sft:3, + ccicnt_out_sel:2, tune_mask:1, m_cci_bypass:1, reserved28:1; +}; +struct DTMB_CHE_IBDFE_CONFIG1_BITS { + unsigned int ibdfe_cci_just_thr:13, + reserved29:3, + ibdfe_dmsg_point:5, reserved30:3, ibdfe_dmsg_alp:3, reserved31:5; +}; +struct DTMB_CHE_IBDFE_CONFIG2_BITS { + unsigned int ibdfe_rou_rat_1:10, + reserved32:6, ibdfe_rou_rat_0:10, reserved33:6; +}; +struct DTMB_CHE_IBDFE_CONFIG3_BITS { + unsigned int ibdfe_rou_rat_3:10, + reserved34:6, ibdfe_rou_rat_2:10, reserved35:6; +}; +struct DTMB_CHE_TD_COEFF_BITS { + unsigned int td_coeff:24, reserved36:8; +}; +struct DTMB_CHE_FD_TD_STEPSIZE_ADJ_BITS { + unsigned int fd_stepsize_adj:3, td_stepsize_adj:3, reserved37:26; +}; +struct DTMB_CHE_FD_COEFF_BITS { + unsigned int fd_coeff:24, reserved38:8; +}; +struct DTMB_CHE_FD_LEAKSIZE_BITS { + unsigned int fd_leaksize:18, reserved39:14; +}; +struct DTMB_CHE_IBDFE_CONFIG4_BITS { + unsigned int ibdfe_fdbk_iter:4, + ibdfe_eqout_iter:4, + eq_dist_thr_tps:4, + eq_soft_slicer_en:1, + reserved40:3, + gd_len:5, ibdfe_blank_y:1, reserved41:1, ibdfe_dmsg_start_cnt:9; +}; +struct DTMB_CHE_IBDFE_CONFIG5_BITS { + unsigned int ibdfe_init_snr:12, + reserved42:4, eq_init_snr:12, reserved43:4; +}; +struct DTMB_CHE_IBDFE_CONFIG6_BITS { + unsigned int ibdfe_const_thr3:4, + ibdfe_const_thr2:4, + ibdfe_const_thr1:4, + ibdfe_const_thr0:4, + ibdfe_threshold3:4, + ibdfe_threshold2:4, ibdfe_threshold1:4, ibdfe_threshold0:4; +}; +struct DTMB_CHE_IBDFE_CONFIG7_BITS { + unsigned int ibdfe_pick_thr3:8, + ibdfe_pick_thr2:8, ibdfe_pick_thr1:8, ibdfe_pick_thr0:8; +}; +struct DTMB_CHE_DCM_SC_MC_GD_LEN_BITS { + unsigned int dcm_mc_gd_len:6, + reserved44:2, dcm_sc_gd_len:6, reserved45:2, eq_dsnr_slc2drm:16; +}; +struct DTMB_CHE_EQMC_PICK_THR_BITS { + unsigned int eqmc_pick_thr3:8, + eqmc_pick_thr2:8, eqmc_pick_thr1:8, eqmc_pick_thr0:8; +}; +struct DTMB_CHE_EQMC_THRESHOLD_BITS { + unsigned int eqmc_const_thr3:4, + eqmc_const_thr2:4, + eqmc_const_thr1:4, + eqmc_const_thr0:4, + eqmc_threshold3:4, + eqmc_threshold2:4, eqmc_threshold1:4, eqmc_threshold0:4; +}; +struct DTMB_CHE_EQSC_PICK_THR_BITS { + unsigned int eqsc_pick_thr3:8, + eqsc_pick_thr2:8, eqsc_pick_thr1:8, eqsc_pick_thr0:8; +}; +struct DTMB_CHE_EQSC_THRESHOLD_BITS { + unsigned int eqsc_const_thr3:4, + eqsc_const_thr2:4, + eqsc_const_thr1:4, + eqsc_const_thr0:4, + eqsc_threshold3:4, + eqsc_threshold2:4, eqsc_threshold1:4, eqsc_threshold0:4; +}; +struct DTMB_CHE_PROTECT_GD_TPS_BITS { + unsigned int pow_norm:10, + ncoh_thd_tps:3, + coh_thd_tps:3, thr_max:10, protect_gd_tps:5, reserved46:1; +}; +struct DTMB_CHE_FD_TD_STEPSIZE_THR1_BITS { + unsigned int fd_stepsize_thr13:5, + fd_stepsize_thr12:5, + fd_stepsize_thr11:5, + td_stepsize_thr13:5, + td_stepsize_thr12:5, td_stepsize_thr11:5, reserved47:2; +}; +struct DTMB_CHE_TDFD_SWITCH_SYM1_BITS { + unsigned int tdfd_switch_sym00:16, tdfd_switch_sym01:16; +}; +struct DTMB_CHE_TDFD_SWITCH_SYM2_BITS { + unsigned int tdfd_switch_sym10:16, tdfd_switch_sym11:16; +}; +struct DTMB_CHE_EQ_CONFIG_BITS { + unsigned int eq_dsnr_h2drm:6, + eq_cmp_en:1, + eq_imp_setzero_en:1, + dcm_sc_bypass:1, + dcm_mc_bypass:1, + dcm_sc_h_limit:4, + dcm_mc_h_limit:4, + eqsnr_imp_alp:3, eqsnr_avg_alp:3, dcm_alpha:2, reserved48:6; +}; +struct DTMB_CHE_EQSC_SNR_IMP_THR1_BITS { + unsigned int eqsc_snr_imp_thr1:12, eqsc_snr_imp_thr0:12, reserved49:8; +}; +struct DTMB_CHE_EQSC_SNR_IMP_THR2_BITS { + unsigned int eqsc_snr_imp_thr3:12, eqsc_snr_imp_thr2:12, reserved50:8; +}; +struct DTMB_CHE_EQMC_SNR_IMP_THR1_BITS { + unsigned int eqmc_snr_imp_thr1:12, eqmc_snr_imp_thr0:12, reserved51:8; +}; +struct DTMB_CHE_EQMC_SNR_IMP_THR2_BITS { + unsigned int eqmc_snr_imp_thr3:12, eqmc_snr_imp_thr2:12, reserved52:8; +}; +struct DTMB_CHE_EQSC_SNR_DROP_THR_BITS { + unsigned int eqsc_snr_drop_thr3:8, + eqsc_snr_drop_thr2:8, eqsc_snr_drop_thr1:8, eqsc_snr_drop_thr0:8; +}; +struct DTMB_CHE_EQMC_SNR_DROP_THR_BITS { + unsigned int eqmc_snr_drop_thr3:8, + eqmc_snr_drop_thr2:8, eqmc_snr_drop_thr1:8, eqmc_snr_drop_thr0:8; +}; +struct DTMB_CHE_M_CCI_THR_BITS { + unsigned int ccidet_mask_rng_tps:5, + m_cci_thr_tps:10, m_cci_thr_ma_tps:10, reserved53:7; +}; +struct DTMB_CHE_TPS_MC_BITS { + unsigned int tps_mc_run_tim_limit:10, + tps_mc_suc_limit:7, tps_mc_q_thr:7, tps_mc_alpha:3, reserved54:5; +}; +struct DTMB_CHE_TPS_SC_BITS { + unsigned int tps_sc_run_tim_limit:10, + tps_sc_suc_limit:7, tps_sc_q_thr:7, tps_sc_alpha:3, reserved55:5; +}; +struct DTMB_CHE_CHE_SET_FSM_BITS { + unsigned int che_open_loop_len:12, + reserved56:4, + che_set_fsm_st:3, reserved57:1, che_set_fsm_en:1, reserved58:11; +}; +struct DTMB_CHE_ZERO_NUM_THR_BITS { + unsigned int null_frame_thr:16, zero_num_thr:12, reserved59:4; +}; +struct DTMB_CHE_TIMING_READY_BITS { + unsigned int timing_offset:11, + reserved60:5, timing_ready:1, reserved61:15; +}; + +#endif diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_front.h b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_front.h new file mode 100644 index 000000000000..a120bc8dff82 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_front.h @@ -0,0 +1,51 @@ +#ifndef __ADDR_DTMB_FRONT_H__ +#define __ADDR_DTMB_FRONT_H__ + +#include "addr_dtmb_top.h" + +#define DTMB_FRONT_ADDR(x) (DTMB_DEMOD_BASE + (x << 2)) + +#define DTMB_FRONT_AFIFO_ADC DTMB_FRONT_ADDR(0x20) +#define DTMB_FRONT_AGC_CONFIG1 DTMB_FRONT_ADDR(0x21) +#define DTMB_FRONT_AGC_CONFIG2 DTMB_FRONT_ADDR(0x22) +#define DTMB_FRONT_AGC_CONFIG3 DTMB_FRONT_ADDR(0x23) +#define DTMB_FRONT_AGC_CONFIG4 DTMB_FRONT_ADDR(0x24) +#define DTMB_FRONT_DDC_BYPASS DTMB_FRONT_ADDR(0x25) +#define DTMB_FRONT_DC_HOLD DTMB_FRONT_ADDR(0x28) +#define DTMB_FRONT_DAGC_TARGET_POWER DTMB_FRONT_ADDR(0x29) +#define DTMB_FRONT_ACF_BYPASS DTMB_FRONT_ADDR(0x2a) +#define DTMB_FRONT_COEF_SET1 DTMB_FRONT_ADDR(0x2b) +#define DTMB_FRONT_COEF_SET2 DTMB_FRONT_ADDR(0x2c) +#define DTMB_FRONT_COEF_SET3 DTMB_FRONT_ADDR(0x2d) +#define DTMB_FRONT_COEF_SET4 DTMB_FRONT_ADDR(0x2e) +#define DTMB_FRONT_COEF_SET5 DTMB_FRONT_ADDR(0x2f) +#define DTMB_FRONT_COEF_SET6 DTMB_FRONT_ADDR(0x30) +#define DTMB_FRONT_COEF_SET7 DTMB_FRONT_ADDR(0x31) +#define DTMB_FRONT_COEF_SET8 DTMB_FRONT_ADDR(0x32) +#define DTMB_FRONT_COEF_SET9 DTMB_FRONT_ADDR(0x33) +#define DTMB_FRONT_COEF_SET10 DTMB_FRONT_ADDR(0x34) +#define DTMB_FRONT_COEF_SET11 DTMB_FRONT_ADDR(0x35) +#define DTMB_FRONT_COEF_SET12 DTMB_FRONT_ADDR(0x36) +#define DTMB_FRONT_COEF_SET13 DTMB_FRONT_ADDR(0x37) +#define DTMB_FRONT_COEF_SET14 DTMB_FRONT_ADDR(0x38) +#define DTMB_FRONT_COEF_SET15 DTMB_FRONT_ADDR(0x39) +#define DTMB_FRONT_COEF_SET16 DTMB_FRONT_ADDR(0x3a) +#define DTMB_FRONT_COEF_SET17 DTMB_FRONT_ADDR(0x3b) +#define DTMB_FRONT_COEF_SET18 DTMB_FRONT_ADDR(0x3c) +#define DTMB_FRONT_COEF_SET19 DTMB_FRONT_ADDR(0x3d) +#define DTMB_FRONT_SRC_CONFIG1 DTMB_FRONT_ADDR(0x3e) +#define DTMB_FRONT_SRC_CONFIG2 DTMB_FRONT_ADDR(0x3f) +#define DTMB_FRONT_SFIFO_OUT_LEN DTMB_FRONT_ADDR(0x40) +#define DTMB_FRONT_DAGC_GAIN DTMB_FRONT_ADDR(0x41) +#define DTMB_FRONT_IQIB_STEP DTMB_FRONT_ADDR(0x42) +#define DTMB_FRONT_IQIB_CONFIG DTMB_FRONT_ADDR(0x43) +#define DTMB_FRONT_ST_CONFIG DTMB_FRONT_ADDR(0x44) +#define DTMB_FRONT_ST_FREQ DTMB_FRONT_ADDR(0x45) +#define DTMB_FRONT_46_CONFIG DTMB_FRONT_ADDR(0x46) +#define DTMB_FRONT_47_CONFIG DTMB_FRONT_ADDR(0x47) +#define DTMB_FRONT_DEBUG_CFG DTMB_FRONT_ADDR(0x48) +#define DTMB_FRONT_MEM_ADDR DTMB_FRONT_ADDR(0x49) +#define DTMB_FRONT_19_CONFIG DTMB_FRONT_ADDR(0x19) +#define DTMB_FRONT_4d_CONFIG DTMB_FRONT_ADDR(0x4d) + +#endif diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_front_bit.h b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_front_bit.h new file mode 100644 index 000000000000..b6df7f602041 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_front_bit.h @@ -0,0 +1,312 @@ +#ifndef __ADDR_DTMB_FRONT_BIT_H__ +#define __ADDR_DTMB_FRONT_BIT_H__ + +union DTMB_FRONT_AFIFO_ADC_BITS { + unsigned int d32; + struct { + unsigned int afifo_nco_rate:8, + afifo_data_format:1, + afifo_bypass:1, + adc_sample:6, + adc_IQ:1, + reserved0:15; + } b; +}; +struct DTMB_FRONT_AGC_CONFIG1_BITS { + unsigned int agc_target:4, + agc_cal_intv:2, + reserved1:2, + agc_gain_step2:6, + reserved2:2, + agc_gain_step1:6, + reserved3:2, + agc_a_filter_coef2:3, + reserved4:1, + agc_a_filter_coef1:3, + reserved5:1; +}; +struct DTMB_FRONT_AGC_CONFIG2_BITS { + unsigned int agc_imp_thresh:4, + agc_imp_en:1, + agc_iq_exchange:1, + reserved6:2, + agc_clip_ratio:5, + reserved7:3, + agc_signal_clip_thr:6, + reserved8:2, + agc_sd_rate:7, + reserved9:1; +}; +struct DTMB_FRONT_AGC_CONFIG3_BITS { + unsigned int agc_rffb_value:11, + reserved10:1, + agc_iffb_value:11, + reserved11:1, + agc_gain_step_rf:1, + agc_rfgain_freeze:1, + agc_tuning_slope:1, + agc_rffb_set:1, + agc_gain_step_if:1, + agc_ifgain_freeze:1, + agc_if_only:1, + agc_iffb_set:1; +}; +struct DTMB_FRONT_AGC_CONFIG4_BITS { + unsigned int agc_rffb_gain_sat_i:8, + agc_rffb_gain_sat:8, + agc_iffb_gain_sat_i:8, + agc_iffb_gain_sat:8; +}; +struct DTMB_FRONT_DDC_BYPASS_BITS { + unsigned int ddc_phase:25, + reserved12:3, + ddc_bypass:1, + reserved13:3; +}; +struct DTMB_FRONT_DC_HOLD_BITS { + unsigned int dc_hold:1, + dc_alpha:3, + mobi_det_accu_len:3, + reserved14:1, + mobi_det_observe_len:3, + reserved15:1, + channel_static_th:4, + channel_portable_th:4, + dc_bypass:1, + reserved16:3, + dc_len:3, + reserved17:5; +}; +struct DTMB_FRONT_DAGC_TARGET_POWER_BITS { + unsigned int dagc_target_power_l:8, + dagc_target_power_h:8, + dagc_target_power_ler:8, + dagc_target_power_her:8; +}; +struct DTMB_FRONT_ACF_BYPASS_BITS { + unsigned int coef65:11, + reserved18:1, + coef66:11, + reserved19:1, + acf_bypass:1, + reserved20:7; +}; +struct DTMB_FRONT_COEF_SET1_BITS { + unsigned int coef63:11, + reserved21:1, + coef64:11, + reserved22:9; +}; +struct DTMB_FRONT_COEF_SET2_BITS { + unsigned int coef62:10, + reserved23:22; +}; +struct DTMB_FRONT_COEF_SET3_BITS { + unsigned int coef60:10, + reserved24:2, + coef61:10, + reserved25:10; +}; +struct DTMB_FRONT_COEF_SET4_BITS { + unsigned int coef59:9, + reserved26:23; +}; +struct DTMB_FRONT_COEF_SET5_BITS { + unsigned int coef57:9, + reserved27:3, + coef58:9, + reserved28:11; +}; +struct DTMB_FRONT_COEF_SET6_BITS { + unsigned int coef54:8, + coef55:8, + coef56:8, + reserved29:8; +}; +struct DTMB_FRONT_COEF_SET7_BITS { + unsigned int coef53:7, + reserved30:25; +}; +struct DTMB_FRONT_COEF_SET8_BITS { + unsigned int coef49:7, + reserved31:1, + coef50:7, + reserved32:1, + coef51:7, + reserved33:1, + coef52:7, + reserved34:1; +}; +struct DTMB_FRONT_COEF_SET9_BITS { + unsigned int coef45:7, + reserved35:1, + coef46:7, + reserved36:1, + coef47:7, + reserved37:1, + coef48:7, + reserved38:1; +}; +struct DTMB_FRONT_COEF_SET10_BITS { + unsigned int coef42:6, + reserved39:2, + coef43:6, + reserved40:2, + coef44:6, + reserved41:10; +}; +struct DTMB_FRONT_COEF_SET11_BITS { + unsigned int coef38:6, + reserved42:2, + coef39:6, + reserved43:2, + coef40:6, + reserved44:2, + coef41:6, + reserved45:2; +}; +struct DTMB_FRONT_COEF_SET12_BITS { + unsigned int coef34:6, + reserved46:2, + coef35:6, + reserved47:2, + coef36:6, + reserved48:2, + coef37:6, + reserved49:2; +}; +struct DTMB_FRONT_COEF_SET13_BITS { + unsigned int coef30:6, + reserved50:2, + coef31:6, + reserved51:2, + coef32:6, + reserved52:2, + coef33:6, + reserved53:2; +}; +struct DTMB_FRONT_COEF_SET14_BITS { + unsigned int coef27:5, + reserved54:3, + coef28:5, + reserved55:3, + coef29:5, + reserved56:11; +}; +struct DTMB_FRONT_COEF_SET15_BITS { + unsigned int coef23:5, + reserved57:3, + coef24:5, + reserved58:3, + coef25:5, + reserved59:3, + coef26:5, + reserved60:3; +}; +struct DTMB_FRONT_COEF_SET16_BITS { + unsigned int coef19:5, + reserved61:3, + coef20:5, + reserved62:3, + coef21:5, + reserved63:3, + coef22:5, + reserved64:3; +}; +struct DTMB_FRONT_COEF_SET17_BITS { + unsigned int coef15:5, + reserved65:3, + coef16:5, + reserved66:3, + coef17:5, + reserved67:3, + coef18:5, + reserved68:3; +}; +struct DTMB_FRONT_COEF_SET18_BITS { + unsigned int coef08:4, + coef09:4, + coef10:4, + coef11:4, + coef12:4, + coef13:4, + coef14:4, + reserved69:4; +}; +struct DTMB_FRONT_COEF_SET19_BITS { + unsigned int coef00:4, + coef01:4, + coef02:4, + coef03:4, + coef04:4, + coef05:4, + coef06:4, + coef07:4; +}; +struct DTMB_FRONT_SRC_CONFIG1_BITS { + unsigned int src_norm_inrate:24, + src_tim_shr:4, + src_ted_disable:1, + reserved70:3; +}; +struct DTMB_FRONT_SRC_CONFIG2_BITS { + unsigned int src_stable_timeout:4, + src_seg_len:3, + reserved71:1, + src_ted_beta:3, + reserved72:1, + src_time_err_thr:4, + src_time_mu1:5, + reserved73:3, + src_time_mu2:5, + reserved74:3; +}; +struct DTMB_FRONT_SFIFO_OUT_LEN_BITS { + unsigned int sfifo_out_len:4, + reserved75:28; +}; +struct DTMB_FRONT_DAGC_GAIN_BITS { + unsigned int dagc_bypass:1, + dagc_power_alpha:2, + dagc_bw:3, + dagc_gain_ctrl:12, + dagc_gain_step_er:6, + dagc_gain_step:6, + reserved76:2; +}; +struct DTMB_FRONT_IQIB_STEP_BITS { + unsigned int iqib_step_b:2, + iqib_step_a:2, + iqib_period:3, + reserved77:1, + iqib_bypass:1, + reserved78:23; +}; +struct DTMB_FRONT_IQIB_CONFIG_BITS { + unsigned int iqib_set_b:12, + iqib_set_a:10, + reserved79:2, + iqib_set_val:1, + iqib_hold:1, + reserved80:6; +}; +struct DTMB_FRONT_ST_CONFIG_BITS { + unsigned int st_enable:1, + reserved81:3, + st_dc_len:3, + reserved82:1, + st_alpha:3, + reserved83:1, + st_Q_thrsh:8, + st_dist:3, + reserved84:1, + st_len:5, + reserved85:3; +}; +struct DTMB_FRONT_ST_FREQ_BITS { + unsigned int st_freq_v:1, + st_freq_i:19, + reserved86:12; +}; + +#endif diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_sync.h b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_sync.h new file mode 100644 index 000000000000..0455a4e3e35f --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_sync.h @@ -0,0 +1,34 @@ +#ifndef __ADDR_DTMB_SYNC_H__ +#define __ADDR_DTMB_SYNC_H__ + +#include "addr_dtmb_top.h" +#define DTMB_SYNC_ADDR(x) (DTMB_DEMOD_BASE + (x << 2)) + +#define DTMB_SYNC_TS_CFO_PN_VALUE DTMB_SYNC_ADDR(0x57) +#define DTMB_SYNC_TS_CFO_ERR_LIMIT DTMB_SYNC_ADDR(0x58) +#define DTMB_SYNC_TS_CFO_PN_MODIFY DTMB_SYNC_ADDR(0x59) +#define DTMB_SYNC_TS_GAIN DTMB_SYNC_ADDR(0x5a) +#define DTMB_SYNC_FE_CONFIG DTMB_SYNC_ADDR(0x5b) +#define DTMB_SYNC_PNPHASE_OFFSET DTMB_SYNC_ADDR(0x5c) +#define DTMB_SYNC_PNPHASE_CONFIG DTMB_SYNC_ADDR(0x5d) +#define DTMB_SYNC_SFO_SFO_PN0_MODIFY DTMB_SYNC_ADDR(0x5e) +#define DTMB_SYNC_SFO_SFO_PN1_MODIFY DTMB_SYNC_ADDR(0x5f) +#define DTMB_SYNC_SFO_SFO_PN2_MODIFY DTMB_SYNC_ADDR(0x60) +#define DTMB_SYNC_SFO_CONFIG DTMB_SYNC_ADDR(0x61) +#define DTMB_SYNC_FEC_CFG DTMB_SYNC_ADDR(0x67) +#define DTMB_SYNC_FEC_DEBUG_CFG DTMB_SYNC_ADDR(0x68) +#define DTMB_SYNC_DATA_DDR_ADR DTMB_SYNC_ADDR(0x69) +#define DTMB_SYNC_DEBUG_DDR_ADR DTMB_SYNC_ADDR(0x6a) +#define DTMB_SYNC_FEC_SIM_CFG1 DTMB_SYNC_ADDR(0x6b) +#define DTMB_SYNC_FEC_SIM_CFG2 DTMB_SYNC_ADDR(0x6c) +#define DTMB_SYNC_TRACK_CFO_MAX DTMB_SYNC_ADDR(0x6d) +#define DTMB_SYNC_CCI_DAGC_CONFIG1 DTMB_SYNC_ADDR(0x6e) +#define DTMB_SYNC_CCI_DAGC_CONFIG2 DTMB_SYNC_ADDR(0x6f) +#define DTMB_SYNC_CCI_RP DTMB_SYNC_ADDR(0x70) +#define DTMB_SYNC_CCI_DET_THRES DTMB_SYNC_ADDR(0x71) +#define DTMB_SYNC_CCI_NOTCH1_CONFIG1 DTMB_SYNC_ADDR(0x72) +#define DTMB_SYNC_CCI_NOTCH1_CONFIG2 DTMB_SYNC_ADDR(0x73) +#define DTMB_SYNC_CCI_NOTCH2_CONFIG1 DTMB_SYNC_ADDR(0x74) +#define DTMB_SYNC_CCI_NOTCH2_CONFIG2 DTMB_SYNC_ADDR(0x75) + +#endif diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_sync_bit.h b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_sync_bit.h new file mode 100644 index 000000000000..51c2517d6eec --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_sync_bit.h @@ -0,0 +1,91 @@ +#ifndef __ADDR_DTMB_SYNC_BIT_H__ +#define __ADDR_DTMB_SYNC_BIT_H__ + +struct DTMB_SYNC_TS_CFO_PN_VALUE_BITS { + unsigned int ts_cfo_pn1_value:16, ts_cfo_pn0_value:16; +}; +struct DTMB_SYNC_TS_CFO_ERR_LIMIT_BITS { + unsigned int ts_cfo_err_limit:16, ts_cfo_pn2_value:16; +}; +struct DTMB_SYNC_TS_CFO_PN_MODIFY_BITS { + unsigned int ts_cfo_pn1_modify:16, ts_cfo_pn0_modify:16; +}; +struct DTMB_SYNC_TS_GAIN_BITS { + unsigned int ts_gain:2, + reserved0:2, + ts_sat_shift:3, + reserved1:1, + ts_fixpn_en:1, + ts_fixpn:2, reserved2:1, ts_cfo_cut:4, ts_cfo_pn2_modify:16; +}; +struct DTMB_SYNC_FE_CONFIG_BITS { + unsigned int fe_lock_len:4, + fe_sat_shift:3, reserved3:1, fe_cut:4, reserved4:4, fe_modify:16; +}; +struct DTMB_SYNC_PNPHASE_OFFSET_BITS { + unsigned int pnphase_offset2:4, + pnphase_offset1:4, pnphase_offset0:4, reserved5:20; +}; +struct DTMB_SYNC_PNPHASE_CONFIG_BITS { + unsigned int pnphase_gain:2, + reserved6:2, + pnphase_sat_shift:4, pnphase_cut:4, reserved7:4, pnphase_modify:16; +}; +struct DTMB_SYNC_SFO_SFO_PN0_MODIFY_BITS { + unsigned int sfo_cfo_pn0_modify:16, sfo_sfo_pn0_modify:16; +}; +struct DTMB_SYNC_SFO_SFO_PN1_MODIFY_BITS { + unsigned int sfo_cfo_pn1_modify:16, sfo_sfo_pn1_modify:16; +}; +struct DTMB_SYNC_SFO_SFO_PN2_MODIFY_BITS { + unsigned int sfo_cfo_pn2_modify:16, sfo_sfo_pn2_modify:16; +}; +struct DTMB_SYNC_SFO_CONFIG_BITS { + unsigned int sfo_sat_shift:4, + sfo_gain:2, + reserved8:2, + sfo_dist:2, + reserved9:2, + sfo_cfo_cut:4, sfo_sfo_cut:4, sfo_cci_th:4, reserved10:8; +}; +struct DTMB_SYNC_TRACK_CFO_MAX_BITS { + unsigned int track_cfo_max:8, + track_sfo_max:8, track_max_en:1, ctrl_fe_to_th:4, reserved11:11; +}; +struct DTMB_SYNC_CCI_DAGC_CONFIG1_BITS { + unsigned int cci_dagc_bypass:1, + cci_dagc_power_alpha:2, + cci_dagc_bw:3, + cci_dagc_gain_ctrl:12, + cci_dagc_gain_step_er:6, cci_dagc_gain_step:6, reserved12:2; +}; +struct DTMB_SYNC_CCI_DAGC_CONFIG2_BITS { + unsigned int cci_dagc_target_power_l:8, + cci_dagc_target_power_h:8, + cci_dagc_target_power_ler:8, cci_dagc_target_power_her:8; +}; +struct DTMB_SYNC_CCI_RP_BITS { + unsigned int cci_rpsq_n:10, reserved13:2, cci_rp_n:13, reserved14:7; +}; +struct DTMB_SYNC_CCI_DET_THRES_BITS { + unsigned int cci_avr_times:5, + reserved15:3, cci_det_thres:3, reserved16:21; +}; +struct DTMB_SYNC_CCI_NOTCH1_CONFIG1_BITS { + unsigned int cci_notch1_a1:10, + reserved17:2, cci_notch1_en:1, reserved18:19; +}; +struct DTMB_SYNC_CCI_NOTCH1_CONFIG2_BITS { + unsigned int cci_notch1_b1:10, + reserved19:2, cci_notch1_a2:10, reserved20:10; +}; +struct DTMB_SYNC_CCI_NOTCH2_CONFIG1_BITS { + unsigned int cci_notch2_a1:10, + reserved21:2, cci_notch2_en:1, reserved22:3, cci_mpthres:16; +}; +struct DTMB_SYNC_CCI_NOTCH2_CONFIG2_BITS { + unsigned int cci_notch2_b1:10, + reserved23:2, cci_notch2_a2:10, reserved24:10; +}; + +#endif diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_top.h b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_top.h new file mode 100644 index 000000000000..827c87a75260 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_top.h @@ -0,0 +1,71 @@ +#ifndef __ADDR_DTMB_TOP_H__ +#define __ADDR_DTMB_TOP_H__ + +#include "addr_dtmb_top_bit.h" +#include "addr_dtmb_sync.h" +#include "addr_dtmb_sync_bit.h" +#include "addr_dtmb_che.h" +#include "addr_dtmb_che_bit.h" +#include "addr_dtmb_front.h" +#include "addr_dtmb_front_bit.h" + +#define DTMB_DEMOD_BASE DEMOD_REG_ADDR(0x0) +#define DTMB_TOP_ADDR(x) (DTMB_DEMOD_BASE + (x << 2)) + +#define DTMB_TOP_CTRL_SW_RST DTMB_TOP_ADDR(0x1) +#define DTMB_TOP_TESTBUS DTMB_TOP_ADDR(0x2) +#define DTMB_TOP_TB DTMB_TOP_ADDR(0x3) +#define DTMB_TOP_TB_V DTMB_TOP_ADDR(0x4) +#define DTMB_TOP_TB_ADDR_BEGIN DTMB_TOP_ADDR(0x5) +#define DTMB_TOP_TB_ADDR_END DTMB_TOP_ADDR(0x6) +#define DTMB_TOP_CTRL_ENABLE DTMB_TOP_ADDR(0x7) +#define DTMB_TOP_CTRL_LOOP DTMB_TOP_ADDR(0x8) +#define DTMB_TOP_CTRL_FSM DTMB_TOP_ADDR(0x9) +#define DTMB_TOP_CTRL_AGC DTMB_TOP_ADDR(0xa) +#define DTMB_TOP_CTRL_TS_SFO_CFO DTMB_TOP_ADDR(0xb) +#define DTMB_TOP_CTRL_FEC DTMB_TOP_ADDR(0xc) +#define DTMB_TOP_CTRL_INTLV_TIME DTMB_TOP_ADDR(0xd) +#define DTMB_TOP_CTRL_DAGC_CCI DTMB_TOP_ADDR(0xe) +#define DTMB_TOP_CTRL_TPS DTMB_TOP_ADDR(0xf) +#define DTMB_TOP_TPS_BIT DTMB_TOP_ADDR(0x10) +#define DTMB_TOP_CCI_FLG DTMB_TOP_ADDR(0xc7) +#define DTMB_TOP_TESTBUS_OUT DTMB_TOP_ADDR(0xc8) +#define DTMB_TOP_TBUS_DC_ADDR DTMB_TOP_ADDR(0xc9) +#define DTMB_TOP_FRONT_IQIB_CHECK DTMB_TOP_ADDR(0xca) +#define DTMB_TOP_SYNC_TS DTMB_TOP_ADDR(0xcb) +#define DTMB_TOP_SYNC_PNPHASE DTMB_TOP_ADDR(0xcd) +#define DTMB_TOP_CTRL_DDC_ICFO DTMB_TOP_ADDR(0xd2) +#define DTMB_TOP_CTRL_DDC_FCFO DTMB_TOP_ADDR(0xd3) +#define DTMB_TOP_CTRL_FSM_STATE0 DTMB_TOP_ADDR(0xd4) +#define DTMB_TOP_CTRL_FSM_STATE1 DTMB_TOP_ADDR(0xd5) +#define DTMB_TOP_CTRL_FSM_STATE2 DTMB_TOP_ADDR(0xd6) +#define DTMB_TOP_CTRL_FSM_STATE3 DTMB_TOP_ADDR(0xd7) +#define DTMB_TOP_CTRL_TS2 DTMB_TOP_ADDR(0xd8) +#define DTMB_TOP_FRONT_AGC DTMB_TOP_ADDR(0xd9) +#define DTMB_TOP_FRONT_DAGC DTMB_TOP_ADDR(0xda) +#define DTMB_TOP_FEC_TIME_STS DTMB_TOP_ADDR(0xdb) +#define DTMB_TOP_FEC_LDPC_STS DTMB_TOP_ADDR(0xdc) +#define DTMB_TOP_FEC_LDPC_IT_AVG DTMB_TOP_ADDR(0xdd) +#define DTMB_TOP_FEC_LDPC_UNC_ACC DTMB_TOP_ADDR(0xde) +#define DTMB_TOP_FEC_BCH_ACC DTMB_TOP_ADDR(0xdf) +#define DTMB_TOP_CTRL_ICFO_ALL DTMB_TOP_ADDR(0xe0) +#define DTMB_TOP_CTRL_FCFO_ALL DTMB_TOP_ADDR(0xe1) +#define DTMB_TOP_CTRL_SFO_ALL DTMB_TOP_ADDR(0xe2) +#define DTMB_TOP_FEC_LOCK_SNR DTMB_TOP_ADDR(0xe3) +#define DTMB_TOP_CHE_SEG_FACTOR DTMB_TOP_ADDR(0xe4) +#define DTMB_TOP_CTRL_CHE_WORKCNT DTMB_TOP_ADDR(0xe5) +#define DTMB_TOP_CHE_OBS_STATE1 DTMB_TOP_ADDR(0xe6) +#define DTMB_TOP_CHE_OBS_STATE2 DTMB_TOP_ADDR(0xe7) +#define DTMB_TOP_CHE_OBS_STATE3 DTMB_TOP_ADDR(0xe8) +#define DTMB_TOP_CHE_OBS_STATE4 DTMB_TOP_ADDR(0xe9) +#define DTMB_TOP_CHE_OBS_STATE5 DTMB_TOP_ADDR(0xea) +#define DTMB_TOP_SYNC_CCI_NF1 DTMB_TOP_ADDR(0xee) +#define DTMB_TOP_SYNC_CCI_NF2 DTMB_TOP_ADDR(0xef) +#define DTMB_TOP_SYNC_CCI_NF2_POSITION DTMB_TOP_ADDR(0xf0) +#define DTMB_TOP_CTRL_SYS_OFDM_CNT DTMB_TOP_ADDR(0xf1) +#define DTMB_TOP_CTRL_TPS_Q_FINAL DTMB_TOP_ADDR(0xf2) +#define DTMB_TOP_FRONT_DC DTMB_TOP_ADDR(0xf3) +#define DTMB_TOP_CHE_DEBUG DTMB_TOP_ADDR(0xf6) +#define DTMB_TOP_CTRL_TOTPS_READY_CNT DTMB_TOP_ADDR(0xff) + +#endif diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_top_bit.h b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_top_bit.h new file mode 100644 index 000000000000..4a6df5d5e8b6 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/addr_dtmb_top_bit.h @@ -0,0 +1,159 @@ +#ifndef __ADDR_DTMB_TOP_BIT_H__ +#define __ADDR_DTMB_TOP_BIT_H__ + +union DTMB_TOP_CTRL_SW_RST_BITS { + unsigned int d32; + struct { + unsigned int ctrl_sw_rst:1, ctrl_sw_rst_noreg:1, reserved0:30; + } b; +}; +struct DTMB_TOP_TESTBUS_BITS { + unsigned int testbus_addr:16, testbus_en:1, reserved1:15; +}; +struct DTMB_TOP_TB_BITS { + unsigned int tb_act_width:5, + reserved2:3, + tb_dc_mk:3, + reserved3:1, tb_capture_stop:1, tb_self_test:1, reserved4:18; +}; +struct DTMB_TOP_CTRL_ENABLE_BITS { + unsigned int ctrl_enable:24, reserved5:8; +}; +struct DTMB_TOP_CTRL_LOOP_BITS { + unsigned int ctrl_src_pnphase_loop:1, + ctrl_src_sfo_loop:1, + ctrl_ddc_fcfo_loop:1, ctrl_ddc_icfo_loop:1, reserved6:28; +}; +struct DTMB_TOP_CTRL_FSM_BITS { + unsigned int ctrl_fsm_state:5, + reserved7:3, + ctrl_fsm_v:1, reserved8:3, ctrl_reset_state:4, reserved9:16; +}; +struct DTMB_TOP_CTRL_AGC_BITS { + unsigned int ctrl_fast_agc:1, + ctrl_agc_bypass:1, + ts_cfo_bypass:1, sfo_strong0_bypass:1, reserved10:28; +}; +struct DTMB_TOP_CTRL_TS_SFO_CFO_BITS { + unsigned int ctrl_ts_q:10, + reserved11:2, + ctrl_pnphase_q:7, reserved12:1, ctrl_sfo_q:4, ctrl_cfo_q:8; +}; +struct DTMB_TOP_CTRL_FEC_BITS { + unsigned int reserved13:8, + ctrl_ts_to_th:4, + ctrl_pnphase_to_th:4, + ctrl_sfo_to_th:4, + ctrl_fe_to_th:4, ctrl_che_to_th:4, ctrl_fec_to_th:4; +}; +struct DTMB_TOP_CTRL_INTLV_TIME_BITS { + unsigned int ctrl_intlv720_time:12, ctrl_intlv240_time:12, reserved14:8; +}; +struct DTMB_TOP_CTRL_DAGC_CCI_BITS { + unsigned int dagc_mode:2, + cci_dagc_mode:2, + cci_bypass:1, + fe_bypass:1, + reserved15:1, + new_sync1:1, new_sync2:1, fec_inzero_check:1, reserved16:22; +}; +struct DTMB_TOP_CTRL_TPS_BITS { + unsigned int sfo_gain:2, + freq_reverse:1, + qam4_nr:1, + intlv_mode:1, + code_rate:2, + constell:2, + tps_carrier_mode:1, + freq_reverse_known:1, tps_known:1, ctrl_tps_to_th:4, reserved17:16; +}; +struct DTMB_TOP_CCI_FLG_BITS { + unsigned int cci_flg_cnt:8, m_cci_ready:1, reserved18:23; +}; +struct DTMB_TOP_FRONT_IQIB_CHECK_BITS { + unsigned int front_iqib_check_b:12, + front_iqib_check_a:10, reserved19:10; +}; +struct DTMB_TOP_SYNC_TS_BITS { + unsigned int sync_ts_idx:2, sync_ts_pos:13, sync_ts_q:10, reserved20:7; +}; +struct DTMB_TOP_SYNC_PNPHASE_BITS { + unsigned int sync_pnphase_max_q_idx:2, + sync_pnphase:8, sync_pnphase_max_q:7, reserved21:15; +}; +struct DTMB_TOP_CTRL_DDC_ICFO_BITS { + unsigned int ctrl_ddc_icfo:20, reserved22:12; +}; +struct DTMB_TOP_CTRL_DDC_FCFO_BITS { + unsigned int ctrl_src_sfo:17, ctrl_ddc_fcfo:14, reserved23:1; +}; +struct DTMB_TOP_CTRL_TS2_BITS { + unsigned int ctrl_ts2_workcnt:8, + ctrl_pnphase_workcnt:8, ctrl_sfo_workcnt:8, sync_fe_workcnt:8; +}; +struct DTMB_TOP_FRONT_AGC_BITS { + unsigned int front_agc_if_gain:11, + front_agc_rf_gain:11, front_agc_power:10; +}; +struct DTMB_TOP_FRONT_DAGC_BITS { + unsigned int front_dagc_power:8, front_dagc_gain:12, reserved24:12; +}; +struct DTMB_TOP_FEC_LDPC_IT_AVG_BITS { + unsigned int fec_ldpc_it_avg:16, fec_ldpc_per_rpt:13, reserved25:3; +}; +struct DTMB_TOP_CTRL_ICFO_ALL_BITS { + unsigned int ctrl_icfo_all:20, reserved26:12; +}; +struct DTMB_TOP_CTRL_FCFO_ALL_BITS { + unsigned int ctrl_fcfo_all:20, reserved27:12; +}; +struct DTMB_TOP_CTRL_SFO_ALL_BITS { + unsigned int ctrl_sfo_all:25, reserved28:7; +}; +struct DTMB_TOP_FEC_LOCK_SNR_BITS { + unsigned int che_snr:14, + fec_lock:1, reserved29:1, che_snr_average:14, reserved30:2; +}; +struct DTMB_TOP_CHE_SEG_FACTOR_BITS { + unsigned int che_seg_factor:14, reserved31:18; +}; +struct DTMB_TOP_CTRL_CHE_WORKCNT_BITS { + unsigned int ctrl_che_workcnt:8, + ctrl_fec_workcnt:8, + ctrl_constell:2, + ctrl_code_rate:2, + ctrl_intlv_mode:1, + ctrl_qam4_nr:1, ctrl_freq_reverse:1, reserved32:9; +}; +struct DTMB_TOP_SYNC_CCI_NF1_BITS { + unsigned int sync_cci_nf1_b1:10, + sync_cci_nf1_a2:10, sync_cci_nf1_a1:10, reserved33:2; +}; +struct DTMB_TOP_SYNC_CCI_NF2_BITS { + unsigned int sync_cci_nf2_b1:10, + sync_cci_nf2_a2:10, sync_cci_nf2_a1:10, reserved34:2; +}; +struct DTMB_TOP_SYNC_CCI_NF2_POSITION_BITS { + unsigned int sync_cci_nf2_position:11, + sync_cci_nf1_position:11, + sync_cci_nf2_det:1, sync_cci_nf1_det:1, reserved35:8; +}; +struct DTMB_TOP_CTRL_SYS_OFDM_CNT_BITS { + unsigned int ctrl_sys_ofdm_cnt:8, + mobi_det_power_var:19, + reserved36:1, ctrl_che_working_state:2, reserved37:2; +}; +struct DTMB_TOP_CTRL_TPS_Q_FINAL_BITS { + unsigned int ctrl_tps_q_final:7, ctrl_tps_suc_cnt:7, reserved38:18; +}; +struct DTMB_TOP_FRONT_DC_BITS { + unsigned int front_dc_q:10, front_dc_i:10, reserved39:12; +}; +struct DTMB_TOP_CTRL_TOTPS_READY_CNT_BITS { + unsigned int ctrl_dead_lock_det:1, + ctrl_dead_lock:1, + reserved40:2, + ctrl_dead_cnt:4, reserved41:8, ctrl_totps_ready_cnt:16; +}; + +#endif diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/aml_dtv_demod_reg.h b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/aml_dtv_demod_reg.h new file mode 100644 index 000000000000..9c318b1524f3 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/aml_dtv_demod_reg.h @@ -0,0 +1,9 @@ +#ifndef _DTV_REG_H_ +#define _DTV_REG_H_ + +#include + +#define DTV_WRITE_CBUS_REG(_r, _v) aml_write_cbus(_r, _v) +#define DTV_READ_CBUS_REG(_r) aml_read_cbus(_r) + +#endif /* */ diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/amlfrontend.h b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/amlfrontend.h new file mode 100644 index 000000000000..9867a24e4ee5 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/amlfrontend.h @@ -0,0 +1,66 @@ +/***************************************************************** + ** + ** Copyright (C) 2010 Amlogic,Inc. + ** All rights reserved + ** Filename : amlfrontend.h + ** + ** comment: + ** Driver for aml demodulator + ** + **************************************************************** + */ + +#ifndef _AMLFRONTEND_H +#define _AMLFRONTEND_H + +struct amlfe_config { + int fe_mode; + int i2c_id; + int tuner_type; + int tuner_addr; +}; +enum Gxtv_Demod_Tuner_If { + Si2176_5M_If = 5, + Si2176_6M_If = 6 +}; +/* 0 -DVBC, 1-DVBT, ISDBT, 2-ATSC */ +enum Gxtv_Demod_Dvb_Mode { + Gxtv_Dvbc = 0, + Gxtv_Dvbt_Isdbt = 1, + Gxtv_Atsc = 2, + Gxtv_Dtmb = 3, +}; +#define Adc_Clk_35M 35714 /* adc clk dvbc */ +#define Demod_Clk_71M 71428 /* demod clk */ + +#define Adc_Clk_24M 24000 +#define Demod_Clk_72M 72000 +#define Demod_Clk_60M 60000 + +#define Adc_Clk_28M 28571 /* dvbt,isdbt */ +#define Demod_Clk_66M 66666 + +#define Adc_Clk_26M 26000 /* atsc air */ +#define Demod_Clk_78M 78000 /* */ + +#define Adc_Clk_25_2M 25200 /* atsc cable */ +#define Demod_Clk_75M 75600 /* */ + +#define Adc_Clk_25M 25000 /* dtmb */ +#define Demod_Clk_100M 100000 /* */ +#define Demod_Clk_180M 180000 /* */ +#define Demod_Clk_200M 200000 /* */ +#define Demod_Clk_225M 225000 + +#define Adc_Clk_27M 27777 /* atsc */ +#define Demod_Clk_83M 83333 /* */ + +enum M6_Demod_Pll_Mode { + Cry_mode = 0, + Adc_mode = 1 +}; + +int M6_Demod_Dtmb_Init(struct aml_fe_dev *dev); +int convert_snr(int in_snr); + +#endif diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/demod_func.h b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/demod_func.h new file mode 100644 index 000000000000..37f0441c644c --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/include/demod_func.h @@ -0,0 +1,607 @@ +#ifdef DEMOD_FUNC_H +#else +#define DEMOD_FUNC_H + +#include +/* #include */ +/*#include + * #include + #include +*/ +#include +#include "aml_fe.h" +#include "amlfrontend.h" +#include "addr_dtmb_top.h" +#include "c_stb_define.h" +#include "c_stb_regs_define.h" +#include + +/* #define G9_TV */ +#define GX_TV +#define safe_addr + +#define PWR_ON 1 +#define PWR_OFF 0 + +#define dtmb_mobile_mode + + +/* void __iomem *meson_reg_demod_map[1024]; */ + +#define IO_CBUS_PHY_BASE (0xc0800000) + +#ifdef safe_addr +#define IO_DEMOD_BASE (0xc8844000) +#define IO_AOBUS_BASE (0xc8100000) +#define IO_HIU_BASE (0xc883c000) +#else +#define IO_DEMOD_BASE (0xda844000) +#define IO_AOBUS_BASE (0xda100000) +#define IO_HIU_BASE (0xda83c000) +#endif + +#define DEMOD_REG_OFFSET(reg) (reg & 0xfffff) +#define DEMOD_REG_ADDR(reg) (IO_DEMOD_BASE + DEMOD_REG_OFFSET(reg)) + +#define DEMOD_CBUS_REG_OFFSET(reg) (reg << 2) +#define DEMOD_CBUS_REG_ADDR(reg) (IO_CBUS_PHY_BASE + \ + DEMOD_CBUS_REG_OFFSET(reg)) + +#define DEMOD_AOBUS_REG_OFFSET(reg) ((reg)) +#define DEMOD_AOBUS_REG_ADDR(reg) (IO_AOBUS_BASE + \ + DEMOD_AOBUS_REG_OFFSET(reg)) + +/* #define DEMOD_BASE APB_REG_ADDR(0x20000) */ +#define DEMOD_BASE DEMOD_REG_ADDR(0x0) /* 0xc8020000 */ + +/* #define DEMOD_BASE 0xc8020000 */ +#define DTMB_BASE (DEMOD_BASE + 0x000) +#define DVBT_BASE (DEMOD_BASE + 0x000) +#define ISDBT_BASE (DEMOD_BASE + 0x000) +#define QAM_BASE (DEMOD_BASE + 0x400) +#define ATSC_BASE (DEMOD_BASE + 0x800) +#define DEMOD_CFG_BASE (DEMOD_BASE + 0xC00) + +/* #ifdef TXL_TV */ +#define TXLTV_ADC_RESET_VALUE 0xca6a2110 /* 0xce7a2110 */ +#define TXLTV_ADC_REG1_VALUE 0x5d414260 +#define TXLTV_ADC_REG2_VALUE 0x5ba00384 /* 0x34e0bf81 */ +#define TXLTV_ADC_REG2_VALUE_CRY 0x34e0bf81 +#define TXLTV_ADC_REG3_VALUE 0x4a6a2110 /* 0x4e7a2110 */ +#define TXLTV_ADC_REG4_VALUE 0x02913004 +#define TXLTV_ADC_REG4_CRY_VALUE 0x301 +#define TXLTV_ADC_REG7_VALUE 0x00102038 +#define TXLTV_ADC_REG8_VALUE 0x00000406 +#define TXLTV_ADC_REG9_VALUE 0x00082183 +#define TXLTV_ADC_REGA_VALUE 0x80480240 +#define TXLTV_ADC_REGB_VALUE 0x22000442 +#define TXLTV_ADC_REGC_VALUE 0x00034a00 +#define TXLTV_ADC_REGD_VALUE 0x00005000 +#define TXLTV_ADC_REGE_VALUE 0x00000200 + + +/* DADC DPLL */ +#define ADC_REG1 (IO_HIU_BASE + (0xaa << 2)) +#define ADC_REG2 (IO_HIU_BASE + (0xab << 2)) +#define ADC_REG3 (IO_HIU_BASE + (0xac << 2)) +#define ADC_REG4 (IO_HIU_BASE + (0xad << 2)) + +#define ADC_REG5 (IO_HIU_BASE + (0x73 << 2)) +#define ADC_REG6 (IO_HIU_BASE + (0x74 << 2)) + +#define ADC_REGB (IO_HIU_BASE + (0xaf << 2)) +#define ADC_REGC (IO_HIU_BASE + (0x9e << 2)) +#define ADC_REGD (IO_HIU_BASE + (0x9f << 2)) + +/* DADC REG */ +#define ADC_REG7 (IO_HIU_BASE + (0x27 << 2)) +#define ADC_REG8 (IO_HIU_BASE + (0x28 << 2)) +#define ADC_REG9 (IO_HIU_BASE + (0x2a << 2)) +#define ADC_REGA (IO_HIU_BASE + (0x2b << 2)) +#define ADC_REGE (IO_HIU_BASE + (0xbd << 2)) + +/* #endif */ + + +/* #ifdef GX_TV */ + +#define ADC_RESET_VALUE 0x8a2a2110 /* 0xce7a2110 */ +#define ADC_REG1_VALUE 0x00100228 +#define ADC_REG2_VALUE 0x34e0bf80 /* 0x34e0bf81 */ +#define ADC_REG2_VALUE_CRY 0x34e0bf81 +#define ADC_REG3_VALUE 0x0a2a2110 /* 0x4e7a2110 */ +#define ADC_REG4_VALUE 0x02933800 +#define ADC_REG4_CRY_VALUE 0x301 +#define ADC_REG7_VALUE 0x01411036 +#define ADC_REG8_VALUE 0x00000000 +#define ADC_REG9_VALUE 0x00430036 +#define ADC_REGA_VALUE 0x80480240 +#if 0 +/* DADC DPLL */ +#define ADC_REG1 (IO_HIU_BASE + (0xaa << 2)) +#define ADC_REG2 (IO_HIU_BASE + (0xab << 2)) +#define ADC_REG3 (IO_HIU_BASE + (0xac << 2)) +#define ADC_REG4 (IO_HIU_BASE + (0xad << 2)) + +#define ADC_REG5 (IO_HIU_BASE + (0x73 << 2)) +#define ADC_REG6 (IO_HIU_BASE + (0x74 << 2)) + +/* DADC REG */ +#define ADC_REG7 (IO_HIU_BASE + (0x27 << 2)) +#define ADC_REG8 (IO_HIU_BASE + (0x28 << 2)) +#define ADC_REG9 (IO_HIU_BASE + (0x2a << 2)) +#define ADC_REGA (IO_HIU_BASE + (0x2b << 2)) +#endif +/* #endif */ + +#ifdef G9_TV + +#define ADC_RESET_VALUE 0x8a2a2110 /* 0xce7a2110 */ +#define ADC_REG1_VALUE 0x00100228 +#define ADC_REG2_VALUE 0x34e0bf80 /* 0x34e0bf81 */ +#define ADC_REG2_VALUE_CRY 0x34e0bf81 +#define ADC_REG3_VALUE 0x0a2a2110 /* 0x4e7a2110 */ +#define ADC_REG4_VALUE 0x02933800 +#define ADC_REG4_CRY_VALUE 0x301 +#define ADC_REG7_VALUE 0x01411036 +#define ADC_REG8_VALUE 0x00000000 +#define ADC_REG9_VALUE 0x00430036 +#define ADC_REGA_VALUE 0x80480240 + +/* DADC DPLL */ +#define ADC_REG1 0x10aa +#define ADC_REG2 0x10ab +#define ADC_REG3 0x10ac +#define ADC_REG4 0x10ad + +#define ADC_REG5 0x1073 +#define ADC_REG6 0x1074 + +/* DADC REG */ +#define ADC_REG7 0x1027 +#define ADC_REG8 0x1028 +#define ADC_REG9 0x102a +#define ADC_REGA 0x102b +#endif + +#ifdef M6_TV +#define ADC_REG1_VALUE 0x003b0232 +#define ADC_REG2_VALUE 0x814d3928 +#define ADC_REG3_VALUE 0x6b425012 +#define ADC_REG4_VALUE 0x101 +#define ADC_REG4_CRY_VALUE 0x301 +#define ADC_REG5_VALUE 0x70b +#define ADC_REG6_VALUE 0x713 + +#define ADC_REG1 0x10aa +#define ADC_REG2 0x10ab +#define ADC_REG3 0x10ac +#define ADC_REG4 0x10ad +#define ADC_REG5 0x1073 +#define ADC_REG6 0x1074 +#endif + +#define DEMOD_REG1_VALUE 0x0000d007 +#define DEMOD_REG2_VALUE 0x2e805400 +#define DEMOD_REG3_VALUE 0x201 + +#define DEMOD_REG1 (DEMOD_BASE + 0xc00) +#define DEMOD_REG2 (DEMOD_BASE + 0xc04) +#define DEMOD_REG3 (DEMOD_BASE + 0xc08) +#define DEMOD_REG4 (DEMOD_BASE + 0xc0c) + +/* #define Wr(addr, data) WRITE_CBUS_REG(addr, data)*/ +/* #define Rd(addr) READ_CBUS_REG(addr) */ + +/*#define Wr(addr, data) *(volatile unsigned long *)(addr) = (data)*/ +/*#define Rd(addr) *(volatile unsigned long *)(addr)*/ + +enum { + enable_mobile, + disable_mobile +}; + +enum { + OPEN_TIME_EQ, + CLOSE_TIME_EQ +}; + +enum { + AMLOGIC_DTMB_STEP0, + AMLOGIC_DTMB_STEP1, + AMLOGIC_DTMB_STEP2, + AMLOGIC_DTMB_STEP3, + AMLOGIC_DTMB_STEP4, + AMLOGIC_DTMB_STEP5, /* time eq */ + AMLOGIC_DTMB_STEP6, /* set normal mode sc */ + AMLOGIC_DTMB_STEP7, + AMLOGIC_DTMB_STEP8, /* set time eq mode */ + AMLOGIC_DTMB_STEP9, /* reset */ + AMLOGIC_DTMB_STEP10, /* set normal mode mc */ + AMLOGIC_DTMB_STEP11, +}; + +enum { + DTMB_IDLE = 0, + DTMB_AGC_READY = 1, + DTMB_TS1_READY = 2, + DTMB_TS2_READY = 3, + DTMB_FE_READY = 4, + DTMB_PNPHASE_READY = 5, + DTMB_SFO_INIT_READY = 6, + DTMB_TS3_READY = 7, + DTMB_PM_INIT_READY = 8, + DTMB_CHE_INIT_READY = 9, + DTMB_FEC_READY = 10 +}; + +/* i2c functions */ +/* int aml_i2c_sw_test_bus(struct aml_demod_i2c *adap, char *name); */ +int am_demod_i2c_xfer(struct aml_demod_i2c *adap, struct i2c_msg *msgs, + int num); +int init_tuner_fj2207(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *adap); +int set_tuner_fj2207(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *adap); + +int get_fj2207_ch_power(void); +int tuner_get_ch_power(struct aml_fe_dev *adap); +int tda18273_tuner_set_frequnecy(unsigned int dwFrequency, + unsigned int dwStandard); +int dtmb_get_power_strength(int agc_gain); + + +int tuner_set_ch(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c); + +/* dvbt */ +int dvbt_set_ch(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c, + struct aml_demod_dvbt *demod_dvbt); + +struct demod_status_ops { + int (*get_status)(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c); + int (*get_ber)(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c); + int (*get_snr)(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c); + int (*get_strength)(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c); + int (*get_ucblocks)(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c); +}; + +struct demod_status_ops *dvbt_get_status_ops(void); + +/* dvbc */ + +int dvbc_set_ch(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c, + struct aml_demod_dvbc *demod_dvbc); +int dvbc_status(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c, + struct aml_demod_sts *demod_sts); +int dvbc_isr_islock(void); +void dvbc_isr(struct aml_demod_sta *demod_sta); +u32 dvbc_set_qam_mode(unsigned char mode); +u32 dvbc_get_status(void); +u32 dvbc_set_auto_symtrack(void); +int dvbc_timer_init(void); +void dvbc_timer_exit(void); +int dvbc_cci_task(void *data); +int dvbc_get_cci_task(void); +void dvbc_create_cci_task(void); +void dvbc_kill_cci_task(void); + +/* atsc */ + +int atsc_set_ch(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c, + struct aml_demod_atsc *demod_atsc); +int check_atsc_fsm_status(void); + +void atsc_write_reg(int reg_addr, int reg_data); + +unsigned long atsc_read_reg(int reg_addr); + +unsigned long atsc_read_iqr_reg(void); + +int atsc_qam_set(fe_modulation_t mode); + +void qam_initial(int qam_id); + +/* dtmb */ + +int dtmb_set_ch(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c, + struct aml_demod_dtmb *demod_atsc); + +void dtmb_reset(void); + +int dtmb_check_status_gxtv(struct dvb_frontend *fe); +int dtmb_check_status_txl(struct dvb_frontend *fe); + + +void dtmb_write_reg(int reg_addr, int reg_data); +int dtmb_read_reg(int reg_addr); +void dtmb_register_reset(void); + +/* demod functions */ +unsigned long apb_read_reg_collect(unsigned long addr); +void apb_write_reg_collect(unsigned int addr, unsigned int data); +void apb_write_reg(unsigned int reg, unsigned int val); +unsigned long apb_read_reg_high(unsigned long addr); +unsigned long apb_read_reg(unsigned long reg); +int app_apb_write_reg(int addr, int data); +int app_apb_read_reg(int addr); + +void demod_set_cbus_reg(unsigned int data, unsigned int addr); +unsigned int demod_read_cbus_reg(unsigned int addr); +void demod_set_demod_reg(unsigned int data, unsigned int addr); +unsigned int demod_read_demod_reg(unsigned int addr); + +/* extern int clk_measure(char index); */ + +void ofdm_initial(int bandwidth, + /* 00:8M 01:7M 10:6M 11:5M */ + int samplerate, + /* 00:45M 01:20.8333M 10:20.7M 11:28.57 */ + int IF, + /* 000:36.13M 001:-5.5M 010:4.57M 011:4M 100:5M */ + int mode, + /* 00:DVBT,01:ISDBT */ + int tc_mode + /* 0: Unsigned, 1:TC */); + +void monitor_isdbt(void); +void demod_set_reg(struct aml_demod_reg *demod_reg); +void demod_get_reg(struct aml_demod_reg *demod_reg); + +/* void demod_calc_clk(struct aml_demod_sta *demod_sta); */ +int demod_set_sys(struct aml_demod_sta *demod_sta, + struct aml_demod_i2c *demod_i2c, + struct aml_demod_sys *demod_sys); +/* int demod_get_sys(struct aml_demod_i2c *demod_i2c, */ +/* struct aml_demod_sys *demod_sys); */ +/* int dvbt_set_ch(struct aml_demod_sta *demod_sta, */ +/* struct aml_demod_i2c *demod_i2c, */ +/* struct aml_demod_dvbt *demod_dvbt); */ +/* int tuner_set_ch (struct aml_demod_sta *demod_sta, */ +/* struct aml_demod_i2c *demod_i2c); */ + +/* typedef char int8_t; */ +/* typedef short int int16_t; */ +/* typedef int int32_t; */ +/* typedef long int64_t; */ +/*typedef unsigned char uint8_t; + * typedef unsigned short int uint16_t; + * typedef unsigned int uint32_t; + * typedef unsigned long uint64_t; + */ + +/*typedef unsigned char u8_t; + * typedef signed char s8_t; + * typedef unsigned short u16_t; + * typedef signed short s16_t; + * typedef unsigned int u32_t; + * typedef signed int s32_t; + * typedef unsigned long u64_t; + * typedef signed long s64_t; + */ + +/* #define extadc */ + +/* for g9tv */ +void adc_dpll_setup(int clk_a, int clk_b, int clk_sys); +void demod_power_switch(int pwr_cntl); + +union adc_pll_cntl { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned pll_m:9; + unsigned pll_n:5; + unsigned pll_od0:2; + unsigned pll_od1:2; + unsigned pll_od2:2; + unsigned pll_xd0:6; + unsigned pll_xd1:6; + } b; +}; + +union adc_pll_cntl2 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned output_mux_ctrl:4; + unsigned div2_ctrl:1; + unsigned b_polar_control:1; + unsigned a_polar_control:1; + unsigned gate_ctrl:6; + unsigned tdc_buf:8; + unsigned lm_s:6; + unsigned lm_w:4; + unsigned reserved:1; + } b; +}; + +union adc_pll_cntl3 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned afc_dsel_in:1; + unsigned afc_dsel_bypass:1; + unsigned dco_sdmck_sel:2; + unsigned dc_vc_in:2; + unsigned dco_m_en:1; + unsigned dpfd_lmode:1; + unsigned filter_acq1:11; + unsigned enable:1; + unsigned filter_acq2:11; + unsigned reset:1; + } b; +}; + +union adc_pll_cntl4 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reve:12; + unsigned tdc_en:1; + unsigned dco_sdm_en:1; + unsigned dco_iup:2; + unsigned pvt_fix_en:1; + unsigned iir_bypass_n:1; + unsigned pll_od3:2; + unsigned filter_pvt1:4; + unsigned filter_pvt2:4; + unsigned reserved:4; + } b; +}; + +/* ///////////////////////////////////////////////////////////////// */ + +union demod_dig_clk { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned demod_clk_div:7; + unsigned reserved0:1; + unsigned demod_clk_en:1; + unsigned demod_clk_sel:2; + unsigned reserved1:5; + unsigned adc_extclk_div:7; /* 34 */ + unsigned use_adc_extclk:1; /* 1 */ + unsigned adc_extclk_en:1; /* 1 */ + unsigned adc_extclk_sel:3; /* 1 */ + unsigned reserved2:4; + } b; +}; + +union demod_adc_clk { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned pll_m:9; + unsigned pll_n:5; + unsigned pll_od:2; + unsigned pll_xd:5; + unsigned reserved0:3; + unsigned pll_ss_clk:4; + unsigned pll_ss_en:1; + unsigned reset:1; + unsigned pll_pd:1; + unsigned reserved1:1; + } b; +}; + +union demod_cfg0 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned mode:4; + unsigned ts_sel:4; + unsigned test_bus_clk:1; + unsigned adc_ext:1; + unsigned adc_rvs:1; + unsigned adc_swap:1; + unsigned adc_format:1; + unsigned adc_regout:1; + unsigned adc_regsel:1; + unsigned adc_regadj:5; + unsigned adc_value:10; + unsigned adc_test:1; + unsigned ddr_sel:1; + } b; +}; + +union demod_cfg1 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved:8; + unsigned ref_top:2; + unsigned ref_bot:2; + unsigned cml_xs:2; + unsigned cml_1s:2; + unsigned vdda_sel:2; + unsigned bias_sel_sha:2; + unsigned bias_sel_mdac2:2; + unsigned bias_sel_mdac1:2; + unsigned fast_chg:1; + unsigned rin_sel:3; + unsigned en_ext_vbg:1; + unsigned en_cmlgen_res:1; + unsigned en_ext_vdd12:1; + unsigned en_ext_ref:1; + } b; +}; + +union demod_cfg2 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned en_adc:1; + unsigned biasgen_ibipt_sel:2; + unsigned biasgen_ibic_sel:2; + unsigned biasgen_rsv:4; + unsigned biasgen_en:1; + unsigned biasgen_bias_sel_adc:2; + unsigned biasgen_bias_sel_cml1:2; + unsigned biasgen_bias_sel_ref_op:2; + unsigned clk_phase_sel:1; + unsigned reserved:15; + } b; +}; + +union demod_cfg3 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned dc_arb_mask:3; + unsigned dc_arb_enable:1; + unsigned reserved:28; + } b; +}; + +struct atsc_cfg { + int adr; + int dat; + int rw; +}; + +struct agc_power_tab { + char name[128]; + int level; + int ncalcE; + int *calcE; +}; + +struct dtmb_cfg { + int dat; + int adr; + int rw; +}; + +void dtvpll_lock_init(void); +void dtvpll_init_flag(int on); +void demod_set_irq_mask(void); +void demod_clr_irq_stat(void); +void demod_set_adc_core_clk(int adc_clk, int sys_clk, int dvb_mode); +void demod_set_adc_core_clk_fix(int clk_adc, int clk_dem); +void calculate_cordic_para(void); +void ofdm_read_all_regs(void); +extern int aml_fe_analog_set_frontend(struct dvb_frontend *fe); + +#endif diff --git a/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/tuner_func.c b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/tuner_func.c new file mode 100644 index 000000000000..a6ab31882b64 --- /dev/null +++ b/drivers/amlogic/media_modules/stream_input/tv_frontend/dtv_demod/tuner_func.c @@ -0,0 +1,170 @@ +#include +#include +#include +#include "demod_func.h" +#include "../aml_fe.h" + +int tuner_get_ch_power(struct aml_fe_dev *adap) +{ + int strength = 0; + int agc_if_gain; + + struct dvb_frontend *dvbfe; + + dvbfe = get_si2177_tuner(); + if (dvbfe != NULL) + if (dvbfe->ops.tuner_ops.get_strength) + strength = dvbfe->ops.tuner_ops.get_strength(dvbfe); + if (strength <= -56) { + agc_if_gain = + ((dtmb_read_reg(DTMB_TOP_FRONT_AGC))&0x3ff); + strength = dtmb_get_power_strength(agc_if_gain); + } + + return strength; +} + +struct dvb_tuner_info *tuner_get_info(int type, int mode) +{ + /*type : 0-NULL, 1-DCT7070, 2-Maxliner, 3-FJ2207, 4-TD1316 */ + /*mode: 0-DVBC 1-DVBT */ + static struct dvb_tuner_info tinfo_null = { }; + + static struct dvb_tuner_info tinfo_MXL5003S[2] = { + [1] = { /*DVBT*/ .name = "Maxliner", + .frequency_min = 44000000, + .frequency_max = 885000000, } + }; + static struct dvb_tuner_info tinfo_FJ2207[2] = { + [0] = { /*DVBC*/ .name = "FJ2207", + .frequency_min = 54000000, + .frequency_max = 870000000, }, + [1] = { /*DVBT*/ .name = "FJ2207", + .frequency_min = 174000000, + .frequency_max = 864000000, }, + }; + static struct dvb_tuner_info tinfo_DCT7070[2] = { + [0] = { /*DVBC*/ .name = "DCT7070", + .frequency_min = 51000000, + .frequency_max = 860000000, } + }; + static struct dvb_tuner_info tinfo_TD1316[2] = { + [1] = { /*DVBT*/ .name = "TD1316", + .frequency_min = 51000000, + .frequency_max = 858000000, } + }; + static struct dvb_tuner_info tinfo_SI2176[2] = { + [0] = { /*DVBC*/ + /*#error please add SI2176 code*/ + .name = "SI2176", + .frequency_min = 51000000, + .frequency_max = 860000000, + } + }; + + struct dvb_tuner_info *tinfo[] = { + &tinfo_null, + tinfo_DCT7070, + tinfo_MXL5003S, + tinfo_FJ2207, + tinfo_TD1316, + tinfo_SI2176 + }; + + if ((type < 0) || (type > 4) || (mode < 0) || (mode > 1)) + return tinfo[0]; + + return &tinfo[type][mode]; +} + +struct agc_power_tab *tuner_get_agc_power_table(int type) +{ + /*type : 0-NULL, 1-DCT7070, 2-Maxliner, 3-FJ2207, 4-TD1316 */ + static int calcE_FJ2207[31] = { + 87, 118, 138, 154, 172, 197, 245, + 273, 292, 312, 327, 354, 406, 430, + 448, 464, 481, 505, 558, 583, 599, + 616, 632, 653, 698, 725, 745, 762, + 779, 801, 831 }; + static int calcE_Maxliner[79] = { + 543, 552, 562, 575, 586, 596, 608, + 618, 627, 635, 645, 653, 662, 668, + 678, 689, 696, 705, 715, 725, 733, + 742, 752, 763, 769, 778, 789, 800, + 807, 816, 826, 836, 844, 854, 864, + 874, 884, 894, 904, 913, 923, 932, + 942, 951, 961, 970, 980, 990, 1000, + 1012, 1022, 1031, 1040, 1049, 1059, + 1069, 1079, 1088, 1098, 1107, 1115, + 1123, 1132, 1140, 1148, 1157, 1165, + 1173, 1179, 1186, 1192, 1198, 1203, + 1208, 1208, 1214, 1217, 1218, 1220 }; + + static struct agc_power_tab power_tab[] = { + [0] = { "null", 0, 0, NULL }, + [1] = { + .name = "DCT7070", + .level = 0, + .ncalcE = 0, + .calcE = NULL, + }, + [2] = { + .name = "Maxlear", + .level = -22, + .ncalcE = sizeof(calcE_Maxliner) / sizeof(int), + .calcE = calcE_Maxliner, + }, + [3] = { + .name = "FJ2207", + .level = -62, + .ncalcE = sizeof(calcE_FJ2207) / sizeof(int), + .calcE = calcE_FJ2207, + }, + [4] = { + .name = "TD1316", + .level = 0, + .ncalcE = 0, + .calcE = NULL, + }, + }; + + if (type >= 2 && type <= 3) + return &power_tab[type]; + else + return &power_tab[3]; +}; + +int agc_power_to_dbm(int agc_gain, int ad_power, int offset, int tuner) +{ + struct agc_power_tab *ptab = tuner_get_agc_power_table(tuner); + int est_rf_power; + int j; + + for (j = 0; j < ptab->ncalcE; j++) + if (agc_gain <= ptab->calcE[j]) + break; + + est_rf_power = ptab->level - j - (ad_power >> 4) + 12 + offset; + + return est_rf_power; +} + +int dtmb_get_power_strength(int agc_gain) +{ + int strength; + int j; + static int calcE_R840[13] = { + 1010, 969, 890, 840, 800, + 760, 720, 680, 670, 660, + 510, 440, 368}; + for (j = 0; j < sizeof(calcE_R840)/sizeof(int); j++) + if (agc_gain >= calcE_R840[j]) + break; + if (agc_gain >= 440) + strength = -90+j*3; + else + strength = -56; + return strength; +} + + diff --git a/firmware/h264_enc.bin b/firmware/h264_enc.bin new file mode 100644 index 000000000000..27c54d61c881 Binary files /dev/null and b/firmware/h264_enc.bin differ diff --git a/firmware/video/h264_enc.bin b/firmware/video/h264_enc.bin new file mode 100644 index 000000000000..27c54d61c881 Binary files /dev/null and b/firmware/video/h264_enc.bin differ diff --git a/firmware/video/video_ucode.bin b/firmware/video/video_ucode.bin new file mode 100644 index 000000000000..24b752810f28 Binary files /dev/null and b/firmware/video/video_ucode.bin differ diff --git a/firmware/video_ucode.bin b/firmware/video_ucode.bin new file mode 100755 index 000000000000..24b752810f28 Binary files /dev/null and b/firmware/video_ucode.bin differ