From 5f0c2578ed8d03f81300f3225a093ae183515936 Mon Sep 17 00:00:00 2001 From: Bin Yang Date: Wed, 11 Nov 2020 11:06:37 +0800 Subject: [PATCH] usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode In the 3.0 device core, if the core is programmed to operate in 2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe) clock. Enabling this feature allows the pipe3 clock to be not-running when forcibly operating in 2.0 device mode. Signed-off-by: Bin Yang Change-Id: I217a380815c21903c1090bd003c1d8ba2fadbe7c --- drivers/usb/dwc3/core.c | 3 +++ drivers/usb/dwc3/core.h | 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 5d7ec4f239c5..f49a6ec912eb 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1092,6 +1092,9 @@ static int dwc3_core_init(struct dwc3 *dwc) if (dwc->parkmode_disable_ss_quirk) reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; + if (dwc->maximum_speed <= USB_SPEED_HIGH) + reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; + dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); } diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 83115784cf5f..b41535f8feb6 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -249,9 +249,10 @@ #define DWC3_GUCTL_HSTINAUTORETRY BIT(14) /* Global User Control 1 Register */ -#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) +#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26) #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) +#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) /* Global Status Register */ #define DWC3_GSTS_OTG_IP BIT(10)