From 5f5cb213bc403be248291a88d6111e8da142d721 Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Fri, 2 Apr 2021 15:04:07 +0800 Subject: [PATCH] pinctrl: rockchip: Add pinctrl support for rk3308b The main description for rk3308b is as follows: - Old iomux multiplexing extension; - GRF_SOC_CON5 register add some bits; - Newly added GRF_SOC_CON13/15 register. Change-Id: I94bfcae5387aceae14895f1cafa0bfea51bf8b63 Signed-off-by: David Wu Signed-off-by: Andy Yan Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.c | 50 ++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 2be7a8100f20..3803319d6da8 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -438,6 +438,8 @@ struct rockchip_pin_ctrl { struct rockchip_mux_route_data *iomux_routes; u32 niomux_routes; + int (*soc_data_init)(struct rockchip_pinctrl *info); + void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit); @@ -4778,6 +4780,46 @@ static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, rockchip_pinctrl_resume); +/* SoC data specially handle */ + +/* rk3308 SoC data initialize */ +#define RK3308_GRF_SOC_CON13 0x608 +#define RK3308_GRF_SOC_CON15 0x610 + +/* RK3308_GRF_SOC_CON13 */ +#define RK3308_GRF_I2C3_IOFUNC_SRC_CTRL (BIT(16 + 10) | BIT(10)) +#define RK3308_GRF_GPIO2A3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) +#define RK3308_GRF_GPIO2A2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) + +/* RK3308_GRF_SOC_CON15 */ +#define RK3308_GRF_GPIO2C0_SEL_SRC_CTRL (BIT(16 + 11) | BIT(11)) +#define RK3308_GRF_GPIO3B3_SEL_SRC_CTRL (BIT(16 + 7) | BIT(7)) +#define RK3308_GRF_GPIO3B2_SEL_SRC_CTRL (BIT(16 + 3) | BIT(3)) + +static int rk3308_soc_data_init(struct rockchip_pinctrl *info) +{ + int ret; + + /* + * Enable the special ctrl of selected sources. + */ + + ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON13, + RK3308_GRF_I2C3_IOFUNC_SRC_CTRL | + RK3308_GRF_GPIO2A3_SEL_SRC_CTRL | + RK3308_GRF_GPIO2A2_SEL_SRC_CTRL); + if (ret) + return ret; + + ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON15, + RK3308_GRF_GPIO2C0_SEL_SRC_CTRL | + RK3308_GRF_GPIO3B3_SEL_SRC_CTRL | + RK3308_GRF_GPIO3B2_SEL_SRC_CTRL); + + return ret; + +} + static int rockchip_pinctrl_probe(struct platform_device *pdev) { struct rockchip_pinctrl *info; @@ -4849,6 +4891,13 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) return PTR_ERR(info->regmap_pmu); } + /* Special handle for some Socs */ + if (ctrl->soc_data_init) { + ret = ctrl->soc_data_init(info); + if (ret) + return ret; + } + ret = rockchip_gpiolib_register(pdev, info); if (ret) return ret; @@ -5205,6 +5254,7 @@ static struct rockchip_pin_ctrl rk3308_pin_ctrl = { .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), .iomux_routes = rk3308_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), + .soc_data_init = rk3308_soc_data_init, .pull_calc_reg = rk3308_calc_pull_reg_and_bit, .drv_calc_reg = rk3308_calc_drv_reg_and_bit, .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,