From 5fbe472645e55dd87f9f46e6b98510d6fa55b568 Mon Sep 17 00:00:00 2001 From: Jerry Xu Date: Thu, 28 Sep 2017 10:49:41 +0800 Subject: [PATCH] drm/rockchip: dsi: fix phy pll programming order The order of the write registers is as follows: 0x17->0x18(lsb)->0x19->0x18(msb)->0x19 Change-Id: I3164a46ed49be611db5bd62d2ae7810613bdbfe0 Signed-off-by: Jerry Xu --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index ade80debd9eb..598c7dab492a 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -527,6 +527,7 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->dphy.input_div)); val = LOOP_DIV_LOW_SEL(dsi->dphy.feedback_div) | LOW_PROGRAM_EN; dw_mipi_dsi_phy_write(dsi, 0x18, val); + dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); val = LOOP_DIV_HIGH_SEL(dsi->dphy.feedback_div) | HIGH_PROGRAM_EN; dw_mipi_dsi_phy_write(dsi, 0x18, val); dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);