From 606e61abb033eab23cf64de4ddae5e47212bd803 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 10 Dec 2021 19:56:40 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add dus clk for pd npu The dus clk shouled be enabled before restore qos. Signed-off-by: Finley Xiao Change-Id: Ic981fc6d680a9be4c441c946715bf709c4e83e7b --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 992a54b33407..3e1e6f7e4401 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1374,7 +1374,8 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&cru HCLK_NPU_ROOT>, - <&cru PCLK_NPU_ROOT>; + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>; pm_qos = <&qos_npu0_mwr>, <&qos_npu0_mro>, <&qos_mcu_npu>; @@ -1382,13 +1383,15 @@ power-domain@RK3588_PD_NPU1 { reg = ; clocks = <&cru HCLK_NPU_ROOT>, - <&cru PCLK_NPU_ROOT>; + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>; pm_qos = <&qos_npu1>; }; power-domain@RK3588_PD_NPU2 { reg = ; clocks = <&cru HCLK_NPU_ROOT>, - <&cru PCLK_NPU_ROOT>; + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>; pm_qos = <&qos_npu2>; }; };