From 6092eb96b6ad98beb1525dad5fde9e20f48d4b38 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Fri, 1 Mar 2024 15:39:29 +0800 Subject: [PATCH] drm/rockchip: vop2: add possible_vp_mask to calculate the exact possible_crtcs Before the patch, the possible_crtcs in struct vop2_win_data is used to register planes for DRM. But the index in struct drm_crtc may be different from the id in struct vop2_video_port, it may cause the warning: [ 3.105377][ T10] Bogus primary plane possible_crtcs: [PLANE:56:Esmart1-win0] must be compatible with [CRTC:72:video_port1] [ 3.105395][ T10] WARNING: CPU: 6 PID: 10 at drivers/gpu/drm/drm_mode_config.c:669 drm_mode_config_validate+0x380/0x4f0 To fix it, replace the possible_crtcs with possible_vp_mask in struct vop2_win_data, which indicates the limitation by vp id exactly, and add the vop2_win_get_possible_crtcs() to calculate exact possible_crtcs for registration process. Change-Id: Iaa866e90c894b9422f55872d0c5e7056f44dd489 Signed-off-by: Damon Ding --- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 2 +- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 92 ++++++++++++++------ drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 72 ++++++++++++--- 3 files changed, 122 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index b05e84c944b2..1233ace1bb38 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -1076,7 +1076,7 @@ struct vop2_win_data { uint8_t axi_id; uint8_t axi_yrgb_id; uint8_t axi_uv_id; - uint8_t possible_crtcs; + uint8_t possible_vp_mask; uint8_t dci_rid_id; uint32_t base; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 132e37a1a52c..e581794f72d7 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -460,7 +460,7 @@ struct vop2_win { uint8_t axi_yrgb_id; uint8_t axi_uv_id; uint8_t scale_engine_num; - uint8_t possible_crtcs; + uint8_t possible_vp_mask; enum drm_plane_type type; unsigned int max_upscale_factor; unsigned int max_downscale_factor; @@ -12098,16 +12098,41 @@ static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win, unsigned lon return 0; } -static struct drm_plane *vop2_cursor_plane_init(struct vop2_video_port *vp, u32 possible_crtcs) +static u8 vop2_win_get_possible_crtcs(struct vop2 *vop2, struct vop2_win *win, u8 enabled_vp_mask) +{ + u8 enable_vp_nr = hweight8(enabled_vp_mask); + u8 possible_crtcs = 0; + u8 vp_mask = 0; + int i; + + for (i = 0; i < enable_vp_nr; i++) { + vp_mask = ffs(enabled_vp_mask) - 1; + if (win->possible_vp_mask & BIT(vp_mask)) + possible_crtcs |= BIT(i); + enabled_vp_mask &= ~BIT(vp_mask); + } + + if (!possible_crtcs) + DRM_WARN("%s(possible_vp_mask = 0x%08x) has no possible crtcs\n", + win->name, win->possible_vp_mask); + + return possible_crtcs; +} + +static struct drm_plane *vop2_cursor_plane_init(struct vop2_video_port *vp, u8 enabled_vp_mask, + u32 registered_num_crtcs) { struct vop2 *vop2 = vp->vop2; struct drm_plane *cursor = NULL; struct vop2_win *win; + u32 possible_crtcs; win = vop2_find_win_by_phys_id(vop2, vp->cursor_win_id); if (win) { - if (win->possible_crtcs) - possible_crtcs = win->possible_crtcs; + if (vop2->disable_win_move) + possible_crtcs = BIT(registered_num_crtcs); + else + possible_crtcs = vop2_win_get_possible_crtcs(vop2, win, enabled_vp_mask); win->type = DRM_PLANE_TYPE_CURSOR; win->zpos = vop2->registered_num_wins - 1; if (!vop2_plane_init(vop2, win, possible_crtcs)) @@ -12360,17 +12385,16 @@ static int vop2_crtc_create_post_sharp_property(struct vop2 *vop2, struct drm_cr #define RK3566_MIRROR_PLANE_MASK (BIT(ROCKCHIP_VOP2_CLUSTER1) | BIT(ROCKCHIP_VOP2_ESMART1) | \ BIT(ROCKCHIP_VOP2_SMART1)) -static inline bool vop2_win_can_link_to_vp(struct vop2_video_port *vp, struct vop2_win *win) +static inline bool vop2_win_can_attach_to_vp(struct vop2_video_port *vp, struct vop2_win *win) { - return (!win->possible_crtcs || - (win->possible_crtcs && (win->possible_crtcs & BIT(vp->id)))); + return win->possible_vp_mask & BIT(vp->id); } /* * Returns: * Registered crtc number on success, negative error code on failure. */ -static int vop2_create_crtc(struct vop2 *vop2) +static int vop2_create_crtc(struct vop2 *vop2, uint8_t enabled_vp_mask) { const struct vop2_data *vop2_data = vop2->data; struct drm_device *drm_dev = vop2->drm_dev; @@ -12394,9 +12418,6 @@ static int vop2_create_crtc(struct vop2 *vop2) bool bootloader_initialized = false; struct rockchip_drm_private *private = drm_dev->dev_private; - /* all planes can attach to any crtc */ - possible_crtcs = (1 << vop2_data->nr_vps) - 1; - /* * We set plane_mask from dts or bootloader * if all the plane_mask are zero, that means @@ -12427,9 +12448,6 @@ static int vop2_create_crtc(struct vop2 *vop2) primary = NULL; cursor = NULL; - if (vop2->disable_win_move) - possible_crtcs = BIT(registered_num_crtcs); - /* * we assume a vp with a zero plane_mask(set from dts or bootloader) * as unused. @@ -12485,7 +12503,7 @@ static int vop2_create_crtc(struct vop2 *vop2) if (vp->primary_plane_phy_id >= 0) { win = vop2_find_win_by_phys_id(vop2, vp->primary_plane_phy_id); - if (win && vop2_win_can_link_to_vp(vp, win)) { + if (win && vop2_win_can_attach_to_vp(vp, win)) { find_primary_plane = true; win->type = DRM_PLANE_TYPE_PRIMARY; } @@ -12504,7 +12522,7 @@ static int vop2_create_crtc(struct vop2 *vop2) if (win->type != DRM_PLANE_TYPE_PRIMARY) continue; - if (!vop2_win_can_link_to_vp(vp, win)) + if (!vop2_win_can_attach_to_vp(vp, win)) continue; for (k = 0; k < vop2_data->nr_vps; k++) { @@ -12531,8 +12549,11 @@ static int vop2_create_crtc(struct vop2 *vop2) } else { /* give lowest zpos for primary plane */ win->zpos = registered_num_crtcs; - if (win->possible_crtcs) - possible_crtcs = win->possible_crtcs; + if (vop2->disable_win_move) + possible_crtcs = BIT(registered_num_crtcs); + else + possible_crtcs = vop2_win_get_possible_crtcs(vop2, win, + enabled_vp_mask); if (vop2_plane_init(vop2, win, possible_crtcs)) { DRM_DEV_ERROR(vop2->dev, "failed to init primary plane\n"); break; @@ -12554,6 +12575,9 @@ static int vop2_create_crtc(struct vop2 *vop2) if (win->type != DRM_PLANE_TYPE_CURSOR) continue; + if (!vop2_win_can_attach_to_vp(vp, win)) + continue; + for (k = 0; k < vop2_data->nr_vps; k++) { if (vop2->vps[k].cursor_win_id == win->phys_id) be_used_for_cursor_plane = true; @@ -12565,7 +12589,7 @@ static int vop2_create_crtc(struct vop2 *vop2) } if (vp->cursor_win_id >= 0) { - cursor = vop2_cursor_plane_init(vp, possible_crtcs); + cursor = vop2_cursor_plane_init(vp, enabled_vp_mask, registered_num_crtcs); if (!cursor) DRM_WARN("failed to init cursor plane for vp%d\n", vp->id); else @@ -12665,15 +12689,21 @@ static int vop2_create_crtc(struct vop2 *vop2) */ win->zpos = registered_num_crtcs + j; + possible_crtcs = vop2_win_get_possible_crtcs(vop2, win, enabled_vp_mask); if (vop2->disable_win_move) { - crtc = vop2_find_crtc_by_plane_mask(vop2, win->phys_id); - if (crtc) - possible_crtcs = drm_crtc_mask(crtc); - else - possible_crtcs = (1 << vop2_data->nr_vps) - 1; + if (is_vop3(vop2)) { + /* + * Set possible_crtcs of overlay plane to the lowest bit + * of exact possibel_crtcs calculated from enabled_vp_mask + * for vop3, whose wins may not support every video port. + */ + possible_crtcs = BIT(ffs(possible_crtcs) - 1); + } else { + crtc = vop2_find_crtc_by_plane_mask(vop2, win->phys_id); + if (crtc) + possible_crtcs = drm_crtc_mask(crtc); + } } - if (win->possible_crtcs) - possible_crtcs = win->possible_crtcs; ret = vop2_plane_init(vop2, win, possible_crtcs); if (ret) @@ -12803,7 +12833,7 @@ static int vop2_win_init(struct vop2 *vop2) win->axi_id = win_data->axi_id; win->axi_yrgb_id = win_data->axi_yrgb_id; win->axi_uv_id = win_data->axi_uv_id; - win->possible_crtcs = win_data->possible_crtcs; + win->possible_vp_mask = win_data->possible_vp_mask; if (win_data->pd_id) win->pd = vop2_find_pd_by_id(vop2, win_data->pd_id); @@ -12834,7 +12864,7 @@ static int vop2_win_init(struct vop2 *vop2) area->vsd_filter_mode = win_data->vsd_filter_mode; area->hsd_pre_filter_mode = win_data->hsd_pre_filter_mode; area->vsd_pre_filter_mode = win_data->vsd_pre_filter_mode; - area->possible_crtcs = win->possible_crtcs; + area->possible_vp_mask = win->possible_vp_mask; area->vop2 = vop2; area->win_id = i; @@ -13244,6 +13274,7 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) int registered_num_crtcs; struct device_node *vop_out_node; struct device_node *mcu_timing_node; + u8 enabled_vp_mask = 0; vop2_data = of_device_get_match_data(dev); if (!vop2_data) @@ -13422,6 +13453,9 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) if (!of_property_read_u32(mcu_timing_node, "mcu-hold-mode", &val)) vop2->vps[vp_id].mcu_timing.mcu_hold_mode = val; } + + if (vop2_get_vp_of_status(child)) + enabled_vp_mask |= BIT(vp_id); } if (!vop2_plane_mask_check(vop2)) { @@ -13456,7 +13490,7 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) vop2_dsc_data_init(vop2); - registered_num_crtcs = vop2_create_crtc(vop2); + registered_num_crtcs = vop2_create_crtc(vop2, enabled_vp_mask); if (registered_num_crtcs <= 0) return -ENODEV; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index 6f0fc125e020..f9bb35235371 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -2973,7 +2973,7 @@ static const struct vop2_win_data rk3528_vop_win_data[] = { .axi_id = 0, .axi_yrgb_id = 0x06, .axi_uv_id = 0x07, - .possible_crtcs = 0x1,/* vp0 only */ + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0), .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 27, 45, 48 }, @@ -3002,7 +3002,7 @@ static const struct vop2_win_data rk3528_vop_win_data[] = { .axi_id = 0, .axi_yrgb_id = 0x08, .axi_uv_id = 0x09, - .possible_crtcs = 0x1,/* vp0 only */ + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0), .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 27, 45, 48 }, @@ -3031,7 +3031,7 @@ static const struct vop2_win_data rk3528_vop_win_data[] = { .axi_id = 0, .axi_yrgb_id = 0x0a, .axi_uv_id = 0x0b, - .possible_crtcs = 0x3,/* vp0 or vp1 */ + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1), .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 27, 45, 48 }, @@ -3060,7 +3060,7 @@ static const struct vop2_win_data rk3528_vop_win_data[] = { .axi_id = 0, .axi_yrgb_id = 0x0c, .axi_uv_id = 0x0d, - .possible_crtcs = 0x2,/* vp1 only */ + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP1), .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 27, 45, 48 }, @@ -3086,7 +3086,7 @@ static const struct vop2_win_data rk3528_vop_win_data[] = { .regs = &rk3528_cluster0_win_data, .axi_yrgb_id = 0x02, .axi_uv_id = 0x03, - .possible_crtcs = 0x1,/* vp0 only */ + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0), .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 27, 27, 21 }, @@ -3112,7 +3112,7 @@ static const struct vop2_win_data rk3528_vop_win_data[] = { .regs = &rk3528_cluster0_win_data, .axi_yrgb_id = 0x04, .axi_uv_id = 0x05, - .possible_crtcs = 0x1,/* vp0 only */ + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0), .max_upscale_factor = 8, .max_downscale_factor = 8, .type = DRM_PLANE_TYPE_OVERLAY, @@ -3155,6 +3155,7 @@ static const struct vop2_win_data rk3562_vop_win_data[] = { .axi_id = 0, .axi_yrgb_id = 0x02, .axi_uv_id = 0x03, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0), .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 27, 45, 48 }, @@ -3181,6 +3182,7 @@ static const struct vop2_win_data rk3562_vop_win_data[] = { .axi_id = 0, .axi_yrgb_id = 0x04, .axi_uv_id = 0x05, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0), .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 27, 45, 48 }, @@ -3207,6 +3209,7 @@ static const struct vop2_win_data rk3562_vop_win_data[] = { .axi_id = 0, .axi_yrgb_id = 0x06, .axi_uv_id = 0x07, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0), .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 27, 45, 48 }, @@ -3233,6 +3236,7 @@ static const struct vop2_win_data rk3562_vop_win_data[] = { .axi_id = 0, .axi_yrgb_id = 0x08, .axi_uv_id = 0x0d, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0), .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 27, 45, 48 }, @@ -3275,6 +3279,8 @@ static const struct vop2_win_data rk3568_vop_win_data[] = { .area = rk3568_area_data, .area_size = ARRAY_SIZE(rk3568_area_data), .type = DRM_PLANE_TYPE_PRIMARY, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2), .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 20, 47, 41 }, @@ -3298,6 +3304,8 @@ static const struct vop2_win_data rk3568_vop_win_data[] = { .area = rk3568_area_data, .area_size = ARRAY_SIZE(rk3568_area_data), .type = DRM_PLANE_TYPE_PRIMARY, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2), .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 20, 47, 41 }, @@ -3321,6 +3329,8 @@ static const struct vop2_win_data rk3568_vop_win_data[] = { .area = rk3568_area_data, .area_size = ARRAY_SIZE(rk3568_area_data), .type = DRM_PLANE_TYPE_PRIMARY, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2), .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 20, 47, 41 }, @@ -3344,6 +3354,8 @@ static const struct vop2_win_data rk3568_vop_win_data[] = { .area = rk3568_area_data, .area_size = ARRAY_SIZE(rk3568_area_data), .type = DRM_PLANE_TYPE_OVERLAY, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2), .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 20, 47, 41 }, @@ -3365,6 +3377,8 @@ static const struct vop2_win_data rk3568_vop_win_data[] = { .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, .regs = &rk3568_cluster0_win_data, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2), .max_upscale_factor = 4, .max_downscale_factor = 4, .dly = { 0, 27, 21 }, @@ -3386,6 +3400,8 @@ static const struct vop2_win_data rk3568_vop_win_data[] = { .vsu_filter_mode = VOP2_SCALE_UP_BIL, .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, .regs = &rk3568_cluster0_win_data, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2), .max_upscale_factor = 4, .max_downscale_factor = 4, .type = DRM_PLANE_TYPE_OVERLAY, @@ -3408,6 +3424,8 @@ static const struct vop2_win_data rk3568_vop_win_data[] = { .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, .regs = &rk3568_cluster1_win_data, .type = DRM_PLANE_TYPE_OVERLAY, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2), .max_upscale_factor = 4, .max_downscale_factor = 4, .dly = { 0, 27, 21 }, @@ -3429,6 +3447,8 @@ static const struct vop2_win_data rk3568_vop_win_data[] = { .vsd_filter_mode = VOP2_SCALE_DOWN_BIL, .regs = &rk3568_cluster1_win_data, .type = DRM_PLANE_TYPE_OVERLAY, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2), .max_upscale_factor = 4, .max_downscale_factor = 4, .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB | WIN_FEATURE_MIRROR, @@ -3584,7 +3604,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = { .axi_id = 0, .axi_yrgb_id = 0x0a, .axi_uv_id = 0x0b, - .possible_crtcs = 0x5,/* vp0 or vp2 */ + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP2), .max_upscale_factor = 8, .max_downscale_factor = 8, .feature = WIN_FEATURE_MULTI_AREA | WIN_FEATURE_Y2R_13BIT_DEPTH, @@ -3613,7 +3633,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = { .axi_id = 0, .axi_yrgb_id = 0x0c, .axi_uv_id = 0x0d, - .possible_crtcs = 0x6,/* vp1 or vp2 */ + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP1) | BIT(ROCKCHIP_VOP_VP2), .max_upscale_factor = 8, .max_downscale_factor = 8, .feature = WIN_FEATURE_MULTI_AREA, @@ -3642,7 +3662,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = { .axi_id = 1, .axi_yrgb_id = 0x0a, .axi_uv_id = 0x0b, - .possible_crtcs = 0x5,/* vp0 or vp2 */ + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP2), .max_upscale_factor = 8, .max_downscale_factor = 8, .feature = WIN_FEATURE_MULTI_AREA, @@ -3671,7 +3691,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = { .axi_id = 1, .axi_yrgb_id = 0x0c, .axi_uv_id = 0x0d, - .possible_crtcs = 0x6,/* vp1 or vp2 */ + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP1) | BIT(ROCKCHIP_VOP_VP2), .max_upscale_factor = 8, .max_downscale_factor = 8, .feature = WIN_FEATURE_MULTI_AREA, @@ -3697,7 +3717,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = { .axi_yrgb_id = 0x10, .axi_uv_id = 0x11, .dci_rid_id = 0x4,/* dci axi id length is 4 bits */ - .possible_crtcs = 0x3,/* vp0 or vp1 */ + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1), .max_upscale_factor = 8, .max_downscale_factor = 8, .type = DRM_PLANE_TYPE_OVERLAY, @@ -3723,7 +3743,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = { .regs = &rk3576_cluster0_win_data, .axi_yrgb_id = 0x12, .axi_uv_id = 0x13, - .possible_crtcs = 0x3,/* vp0 or vp1 */ + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1), .max_upscale_factor = 8, .max_downscale_factor = 8, .type = DRM_PLANE_TYPE_OVERLAY, @@ -3749,7 +3769,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = { .pd_id = VOP2_PD_CLUSTER, .axi_yrgb_id = 0x06, .axi_uv_id = 0x07, - .possible_crtcs = 0x3,/* vp0 or vp1 */ + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1),/* vp0 or vp1 */ .max_upscale_factor = 8, .max_downscale_factor = 8, .type = DRM_PLANE_TYPE_OVERLAY, @@ -3774,7 +3794,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = { .regs = &rk3576_cluster1_win_data, .axi_yrgb_id = 0x08, .axi_uv_id = 0x09, - .possible_crtcs = 0x3,/* vp0 or vp1 */ + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1),/* vp0 or vp1 */ .max_upscale_factor = 8, .max_downscale_factor = 8, .type = DRM_PLANE_TYPE_OVERLAY, @@ -4070,6 +4090,8 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_id = 0, .axi_yrgb_id = 2, .axi_uv_id = 3, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), .max_upscale_factor = 4, .max_downscale_factor = 4, .dly = { 4, 26, 29 }, @@ -4094,6 +4116,8 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_id = 0, .axi_yrgb_id = 4, .axi_uv_id = 5, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), .max_upscale_factor = 4, .max_downscale_factor = 4, .type = DRM_PLANE_TYPE_OVERLAY, @@ -4120,6 +4144,8 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_yrgb_id = 6, .axi_uv_id = 7, .type = DRM_PLANE_TYPE_OVERLAY, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), .max_upscale_factor = 4, .max_downscale_factor = 4, .dly = { 4, 26, 29 }, @@ -4144,6 +4170,8 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_id = 0, .axi_yrgb_id = 8, .axi_uv_id = 9, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), .max_upscale_factor = 4, .max_downscale_factor = 4, .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB, @@ -4170,6 +4198,8 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_id = 1, .axi_yrgb_id = 2, .axi_uv_id = 3, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), .max_upscale_factor = 4, .max_downscale_factor = 4, .dly = { 4, 26, 29 }, @@ -4194,6 +4224,8 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_id = 1, .axi_yrgb_id = 4, .axi_uv_id = 5, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), .max_upscale_factor = 4, .max_downscale_factor = 4, .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB, @@ -4219,6 +4251,8 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_id = 1, .axi_yrgb_id = 6, .axi_uv_id = 7, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), .max_upscale_factor = 4, .max_downscale_factor = 4, .dly = { 4, 26, 29 }, @@ -4243,6 +4277,8 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_id = 1, .axi_yrgb_id = 8, .axi_uv_id = 9, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), .max_upscale_factor = 4, .max_downscale_factor = 4, .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB, @@ -4269,6 +4305,8 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_id = 0, .axi_yrgb_id = 0x0a, .axi_uv_id = 0x0b, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 23, 45, 48 }, @@ -4297,6 +4335,8 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_id = 1, .axi_yrgb_id = 0x0a, .axi_uv_id = 0x0b, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 23, 45, 48 }, @@ -4324,6 +4364,8 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_id = 0, .axi_yrgb_id = 0x0c, .axi_uv_id = 0x01, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 23, 45, 48 }, @@ -4351,6 +4393,8 @@ static const struct vop2_win_data rk3588_vop_win_data[] = { .axi_id = 1, .axi_yrgb_id = 0x0c, .axi_uv_id = 0x0d, + .possible_vp_mask = BIT(ROCKCHIP_VOP_VP0) | BIT(ROCKCHIP_VOP_VP1) | + BIT(ROCKCHIP_VOP_VP2) | BIT(ROCKCHIP_VOP_VP3), .max_upscale_factor = 8, .max_downscale_factor = 8, .dly = { 23, 45, 48 },