From 6118992709ea83bfb580075b97d270c9d2f60c6d Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Mon, 27 Dec 2021 15:19:35 +0800 Subject: [PATCH] MALI: rockchip: Add opp info for system monitor Add support to change memory read margin according to voltage when register system monitor. Change-Id: Id1d78432b6a83bbb09b4438146a0197dc914347b Signed-off-by: Finley Xiao --- .../arm/bifrost/backend/gpu/mali_kbase_devfreq.c | 13 ++++++++----- .../arm/bifrost/platform/rk/mali_kbase_config_rk.c | 4 ++++ 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/arm/bifrost/backend/gpu/mali_kbase_devfreq.c b/drivers/gpu/arm/bifrost/backend/gpu/mali_kbase_devfreq.c index 498dc1ed617c..71bb05c0415d 100644 --- a/drivers/gpu/arm/bifrost/backend/gpu/mali_kbase_devfreq.c +++ b/drivers/gpu/arm/bifrost/backend/gpu/mali_kbase_devfreq.c @@ -141,7 +141,8 @@ int kbase_devfreq_opp_helper(struct dev_pm_set_opp_data *data) unsigned long new_freq = data->new_opp.rate; int ret = 0; - if (clk_bulk_prepare_enable(opp_info->num_clks, opp_info->clks) < 0) { + ret = clk_bulk_prepare_enable(opp_info->num_clks, opp_info->clks); + if (ret) { dev_err(dev, "failed to enable opp clks\n"); return ret; } @@ -172,7 +173,7 @@ int kbase_devfreq_opp_helper(struct dev_pm_set_opp_data *data) ret = clk_set_rate(clk, new_freq); if (ret) { dev_err(dev, "failed to set clk rate: %d\n", ret); - goto restore_voltage; + goto restore_rm; } /* Scaling down? Scale voltage after frequency */ @@ -201,15 +202,16 @@ int kbase_devfreq_opp_helper(struct dev_pm_set_opp_data *data) return 0; restore_freq: + if (clk_set_rate(clk, old_freq)) + dev_err(dev, "failed to restore old-freq %lu Hz\n", old_freq); +restore_rm: if (opp_info->data->set_read_margin) opp_info->data->set_read_margin(dev, opp_info, old_supply_vdd->u_volt); - if (clk_set_rate(clk, old_freq)) - dev_err(dev, "failed to restore old-freq %lu Hz\n", old_freq); - clk_bulk_disable_unprepare(opp_info->num_clks, opp_info->clks); restore_voltage: regulator_set_voltage(mem_reg, old_supply_mem->u_volt, INT_MAX); regulator_set_voltage(vdd_reg, old_supply_vdd->u_volt, INT_MAX); + clk_bulk_disable_unprepare(opp_info->num_clks, opp_info->clks); return ret; } @@ -741,6 +743,7 @@ int kbase_devfreq_init(struct kbase_device *kbdev) } mali_mdevp.data = kbdev->devfreq; + mali_mdevp.opp_info = &kbdev->opp_info; kbdev->mdev_info = rockchip_system_monitor_register(kbdev->dev, &mali_mdevp); if (IS_ERR(kbdev->mdev_info)) { diff --git a/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c b/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c index 572e44709c16..d9bd99ee0f94 100755 --- a/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c +++ b/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c @@ -467,6 +467,8 @@ static int rk3588_gpu_set_read_margin(struct device *dev, if (!is_found) return 0; + if (rm == opp_info->current_rm) + return 0; dev_dbg(dev, "set rm to %d\n", rm); @@ -486,6 +488,8 @@ static int rk3588_gpu_set_read_margin(struct device *dev, val &= ~0x1c; regmap_write(opp_info->grf, 0x28, val | (rm << 2)); + opp_info->current_rm = rm; + return 0; }