From 620cc157a726c0f48e7583783cea66f7c667c162 Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Wed, 20 May 2020 17:35:02 +0800 Subject: [PATCH] clk: rockchip: px30: Add CLK_SET_RATE_PARENT for clk_i2s0_tx_out_pre Signed-off-by: Wyon Bi Change-Id: I18e86d31ece992af568fca12c9af2b04f327dd67 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-px30.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c index 520dc3f5ce92..b9b34a84f1a4 100644 --- a/drivers/clk/rockchip/clk-px30.c +++ b/drivers/clk/rockchip/clk-px30.c @@ -599,7 +599,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = { COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(28), 12, 1, MFLAGS, PX30_CLKGATE_CON(9), 14, GFLAGS), - COMPOSITE_NODIV(0, "clk_i2s0_tx_out_pre", mux_i2s0_tx_out_p, 0, + COMPOSITE_NODIV(0, "clk_i2s0_tx_out_pre", mux_i2s0_tx_out_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(28), 14, 2, MFLAGS, PX30_CLKGATE_CON(9), 15, GFLAGS), GATE(SCLK_I2S0_TX_OUT, "clk_i2s0_tx_out", "clk_i2s0_tx_out_pre", CLK_SET_RATE_PARENT,