From 6273c984deff865ad7322025dc36f170d41bb3dd Mon Sep 17 00:00:00 2001
From: Ye Zhang <ye.zhang@rock-chips.com>
Date: Mon, 31 Mar 2025 10:19:50 +0800
Subject: [PATCH] arm64: dts: rockchip: rv1126b: Add cru phandle for pvtpll_npu

Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I04c3c5ab69ea6f9d4a6e1f21af283b4f30b0a48b
---
 arch/arm64/boot/dts/rockchip/rv1126b.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
index 2da244e900b3..5fe16aa1baea 100644
--- a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
@@ -227,6 +227,7 @@
 		pvtpll_npu: pvtpll-npu@22080000 {
 			compatible = "rockchip,rv1126b-npu-pvtpll", "syscon";
 			reg = <0x22080000 0x100>;
+			rockchip,cru = <&cru>;
 			clocks = <&cru ACLK_RKNN>;
 			#clock-cells = <0>;
 			clock-output-names = "clk_npu_pvtpll";
@@ -822,7 +823,7 @@
 	};
 
 	cru: clock-controller@20000000 {
-		compatible = "rockchip,rv1126b-cru";
+		compatible = "rockchip,rv1126b-cru", "syscon";
 		reg = <0x20000000 0xc0000>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;