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clk: update pcie pll config

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PD#148744: update axg pcie pll config

Change-Id: I4adf79f40f70cd23427f018e7030aeaa9bd080c4
Signed-off-by: Yun Cai <yun.cai@amlogic.com>
This commit is contained in:
Yun Cai
2017-08-09 09:35:06 +08:00
parent e9c0461057
commit 62f74f2d93
2 changed files with 2 additions and 2 deletions
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2
drivers/amlogic/clk/axg/axg.h
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@@ -274,7 +274,7 @@ static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
};
static const struct pll_rate_table axg_pcie_pll_rate_table[] = {
PLL_FRAC_RATE(100000000, 66, 1, 1, 3, 683),
PLL_FRAC_RATE(100000000, 200, 3, 1, 3, 0),
{ /* sentinel */ },
};
#endif /* __AXG_H */

2
drivers/amlogic/pci/pcie-amlogic.c
View File

@@ -725,7 +725,7 @@ static int __init amlogic_pcie_probe(struct platform_device *pdev)
goto fail_pcie;
}
if (clk_get_rate(amlogic_pcie->bus_clk) == rate) {
if (clk_get_rate(amlogic_pcie->bus_clk) != rate) {
ret = -ENODEV;
goto fail_pcie;
}