diff --git a/arch/arm64/boot/dts/amlogic/g12a_skt.dts b/arch/arm64/boot/dts/amlogic/g12a_skt.dts index dfdf231eeb39..5c426c540861 100644 --- a/arch/arm64/boot/dts/amlogic/g12a_skt.dts +++ b/arch/arm64/boot/dts/amlogic/g12a_skt.dts @@ -1002,8 +1002,8 @@ /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ display_size_default = <1920 1080 1920 2160 32>; /*1920*1080*4*3 = 0x17BB000*/ - pxp_mode = <1>; /** 0:normal mode 1:pxp mode */ - mem_alloc = <1>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ + mem_alloc = <0>; logo_addr = "0x3f800000"; }; diff --git a/drivers/amlogic/media/osd/osd.h b/drivers/amlogic/media/osd/osd.h index 240e9fd64a3f..8162dfa05b6b 100644 --- a/drivers/amlogic/media/osd/osd.h +++ b/drivers/amlogic/media/osd/osd.h @@ -551,7 +551,7 @@ struct hw_para_s { u32 vinfo_width; u32 vinfo_height; u32 fb_drvier_probe; - u32 afbc_restart_in_vsync; + u32 afbc_start_in_vsync; u32 afbc_force_reset; u32 afbc_status_err_reset; u32 afbc_use_latch; diff --git a/drivers/amlogic/media/osd/osd_backup.c b/drivers/amlogic/media/osd/osd_backup.c index ce4aa240db36..53688c516964 100644 --- a/drivers/amlogic/media/osd/osd_backup.c +++ b/drivers/amlogic/media/osd/osd_backup.c @@ -37,7 +37,7 @@ const u16 osd_afbc_reg_backup[OSD_AFBC_REG_BACKUP_COUNT] = { }; const u16 mali_afbc_reg_backup[MALI_AFBC_REG_BACKUP_COUNT] = { - 0x3a05, 0x3a07, + 0x3a03, 0x3a07, 0x3a10, 0x3a11, 0x3a12, 0x3a13, 0x3a14, 0x3a15, 0x3a16, 0x3a17, 0x3a18, 0x3a19, 0x3a1a, 0x3a1b, 0x3a1c, 0x3a30, 0x3a31, 0x3a32, 0x3a33, 0x3a34, 0x3a35, 0x3a36, @@ -80,8 +80,8 @@ void update_backup_reg(u32 addr, u32 value) osd_backup[addr - base] = value; return; } - base = VPU_MAFBC_COMMAND; - if ((addr >= VPU_MAFBC_COMMAND) + base = VPU_MAFBC_IRQ_MASK; + if ((addr >= VPU_MAFBC_IRQ_MASK) && (addr <= VPU_MAFBC_PREFETCH_CFG_S2) && (backup_enable & HW_RESET_MALI_AFBCD_REGS)) { mali_afbc_backup[addr - base] = value; @@ -116,8 +116,8 @@ s32 get_backup_reg(u32 addr, u32 *value) return 0; } } - base = VPU_MAFBC_COMMAND; - if ((addr >= VPU_MAFBC_COMMAND) && + base = VPU_MAFBC_IRQ_MASK; + if ((addr >= VPU_MAFBC_IRQ_MASK) && (addr <= VPU_MAFBC_PREFETCH_CFG_S2) && (backup_enable & HW_RESET_MALI_AFBCD_REGS)) { for (i = 0; i < MALI_AFBC_REG_BACKUP_COUNT; i++) @@ -155,7 +155,7 @@ void backup_regs_init(u32 backup_mask) i++; } i = 0; - base = VPU_MAFBC_COMMAND; + base = VPU_MAFBC_IRQ_MASK; while ((backup_mask & HW_RESET_MALI_AFBCD_REGS) && (i < MALI_AFBC_REG_BACKUP_COUNT)) { addr = mali_afbc_reg_backup[i]; @@ -173,11 +173,12 @@ u32 is_backup(void) /* recovery section */ #define INVAILD_REG_ITEM {0xffff, 0x0, 0x0, 0x0} -#define REG_RECOVERY_TABLE 5 +#define REG_RECOVERY_TABLE 11 static struct reg_recovery_table gRecovery[REG_RECOVERY_TABLE]; static u32 recovery_enable; +/* Before G12A Chip */ static struct reg_item osd1_recovery_table[] = { {VIU_OSD1_CTRL_STAT, 0x0, 0x401ff9f1, 1}, INVAILD_REG_ITEM, /* VIU_OSD1_COLOR_ADDR 0x1a11 */ @@ -275,7 +276,6 @@ static struct reg_item osd2_recovery_table[] = { {VIU_OSD2_CTRL_STAT2, 0x0, 0x00007ffd, 1} }; - static struct reg_item misc_recovery_table[] = { {VIU_OSD2_BLK0_CFG_W4, 0x0, 0x0fff0fff, 1}, {VIU_OSD2_BLK1_CFG_W4, 0x0, 0xffffffff, 0}, @@ -287,14 +287,426 @@ static struct reg_item misc_recovery_table[] = { {DOLBY_CORE2A_SWAP_CTRL2, 0x0, 0xffffffff, 1} }; -void recovery_regs_init(void) +/* After G12A Chip */ +static struct reg_item osd12_recovery_table_g12a[] = { + /* osd1 */ + {VIU_OSD1_CTRL_STAT, 0x0, 0xc01ff9f7, 1}, + INVAILD_REG_ITEM, /* VIU_OSD1_COLOR_ADDR 0x1a11 */ + INVAILD_REG_ITEM, /* VIU_OSD1_COLOR 0x1a12 */ + {VIU_OSD1_BLK0_CFG_W4, 0x0, 0x0fff0fff, 1}, + {VIU_OSD1_BLK1_CFG_W4, 0x0, 0xffffffff, 1}, + {VIU_OSD1_BLK2_CFG_W4, 0x0, 0xffffffff, 1}, + INVAILD_REG_ITEM, /* VIU_OSD1_BLK3_CFG_W4 0x1a16 */ + {VIU_OSD1_TCOLOR_AG0, 0x0, 0xffffffff, 1}, + {VIU_OSD1_TCOLOR_AG1, 0x0, 0xffffffff, 0}, + {VIU_OSD1_TCOLOR_AG2, 0x0, 0xffffffff, 0}, + {VIU_OSD1_TCOLOR_AG3, 0x0, 0xffffffff, 0}, + {VIU_OSD1_BLK0_CFG_W0, 0x0, 0x70ffff7f, 1}, + {VIU_OSD1_BLK0_CFG_W1, 0x0, 0x1fff1fff, 1}, + {VIU_OSD1_BLK0_CFG_W2, 0x0, 0x1fff1fff, 1}, + {VIU_OSD1_BLK0_CFG_W3, 0x0, 0x0fff0fff, 1}, + INVAILD_REG_ITEM, /* VIU_OSD1_BLK1_CFG_W0 0x1a1f */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK1_CFG_W1 0x1a20 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK1_CFG_W2 0x1a21 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK1_CFG_W3 0x1a22 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK2_CFG_W0 0x1a23 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK2_CFG_W1 0x1a24 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK2_CFG_W2 0x1a25 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK2_CFG_W3 0x1a26 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK3_CFG_W0 0x1a27 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK3_CFG_W1 0x1a28 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK3_CFG_W2 0x1a29 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK3_CFG_W3 0x1a2a */ + {VIU_OSD1_FIFO_CTRL_STAT, 0x0, 0xffc7ffff, 1}, + INVAILD_REG_ITEM, /* VIU_OSD1_TEST_RDDATA 0x1a2c */ + {VIU_OSD1_CTRL_STAT2, 0x0, 0x0000ffff, 1}, + {VIU_OSD1_PROT_CTRL, 0x0, 0xffff0000, 1}, + {VIU_OSD1_MALI_UNPACK_CTRL, 0x0, 0x9f01ffff, 1}, + /* osd2 */ + {VIU_OSD2_CTRL_STAT, 0x0, 0xc01ff9f7, 1}, + INVAILD_REG_ITEM, /* VIU_OSD2_COLOR_ADDR 0x1a31 */ + INVAILD_REG_ITEM, /* VIU_OSD2_COLOR 0x1a32 */ + INVAILD_REG_ITEM, /* 0x1a33 */ + INVAILD_REG_ITEM, /* 0x1a34 */ + INVAILD_REG_ITEM, /* 0x1a35 */ + INVAILD_REG_ITEM, /* 0x1a36 */ + {VIU_OSD2_TCOLOR_AG0, 0x0, 0xffffffff, 1}, + {VIU_OSD2_TCOLOR_AG1, 0x0, 0xffffffff, 0}, + {VIU_OSD2_TCOLOR_AG2, 0x0, 0xffffffff, 0}, + {VIU_OSD2_TCOLOR_AG3, 0x0, 0xffffffff, 0}, + {VIU_OSD2_BLK0_CFG_W0, 0x0, 0x70ffff7f, 1}, + {VIU_OSD2_BLK0_CFG_W1, 0x0, 0x1fff1fff, 1}, + {VIU_OSD2_BLK0_CFG_W2, 0x0, 0x1fff1fff, 1}, + {VIU_OSD2_BLK0_CFG_W3, 0x0, 0x0fff0fff, 1}, + INVAILD_REG_ITEM, /* VIU_OSD1_BLK1_CFG_W0 0x1a3f */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK1_CFG_W1 0x1a40 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK1_CFG_W2 0x1a41 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK1_CFG_W3 0x1a42 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK2_CFG_W0 0x1a43 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK2_CFG_W1 0x1a44 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK2_CFG_W2 0x1a45 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK2_CFG_W3 0x1a46 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK3_CFG_W0 0x1a47 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK3_CFG_W1 0x1a48 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK3_CFG_W2 0x1a49 */ + INVAILD_REG_ITEM, /* VIU_OSD1_BLK3_CFG_W3 0x1a4a */ + {VIU_OSD2_FIFO_CTRL_STAT, 0x0, 0xffc7ffff, 1}, + INVAILD_REG_ITEM, /* VIU_OSD2_TEST_RDDATA 0x1a4c */ + {VIU_OSD2_CTRL_STAT2, 0x0, 0x0000ffff, 1}, + {VIU_OSD2_PROT_CTRL, 0x0, 0xffff0000, 1}, +}; + +static struct reg_item osd3_recovery_table_g12a[] = { + {VIU_OSD3_CTRL_STAT, 0x0, 0xc01ff9f7, 1}, + {VIU_OSD3_CTRL_STAT2, 0x0, 0x0000ffff, 1}, + INVAILD_REG_ITEM, /* VIU_OSD3_COLOR_ADDR 0x3d82 */ + INVAILD_REG_ITEM, /* VIU_OSD3_COLOR 0x3d83 */ + {VIU_OSD3_TCOLOR_AG0, 0x0, 0xffffffff, 1}, + {VIU_OSD3_TCOLOR_AG1, 0x0, 0xffffffff, 0}, + {VIU_OSD3_TCOLOR_AG2, 0x0, 0xffffffff, 0}, + {VIU_OSD3_TCOLOR_AG3, 0x0, 0xffffffff, 0}, + {VIU_OSD3_BLK0_CFG_W0, 0x0, 0x70ffff7f, 1}, + INVAILD_REG_ITEM, /* 0x3d89 */ + INVAILD_REG_ITEM, /* 0x3d8a */ + INVAILD_REG_ITEM, /* 0x3d8b */ + {VIU_OSD3_BLK0_CFG_W1, 0x0, 0x1fff1fff, 1}, + INVAILD_REG_ITEM, /* 0x3d8d */ + INVAILD_REG_ITEM, /* 0x3d8e */ + INVAILD_REG_ITEM, /* 0x3d8f */ + {VIU_OSD3_BLK0_CFG_W2, 0x0, 0x1fff1fff, 1}, + INVAILD_REG_ITEM, /* 0x3d91 */ + INVAILD_REG_ITEM, /* 0x3d92 */ + INVAILD_REG_ITEM, /* 0x3d93 */ + {VIU_OSD3_BLK0_CFG_W3, 0x0, 0x0fff0fff, 1}, + INVAILD_REG_ITEM, /* 0x3d95 */ + INVAILD_REG_ITEM, /* 0x3d96 */ + INVAILD_REG_ITEM, /* 0x3d97 */ + {VIU_OSD3_BLK0_CFG_W4, 0x0, 0x0fff0fff, 1}, + {VIU_OSD3_BLK1_CFG_W4, 0x0, 0xffffffff, 1}, + {VIU_OSD3_BLK2_CFG_W4, 0x0, 0xffffffff, 1}, + INVAILD_REG_ITEM, /* 0x3d9b */ + {VIU_OSD2_FIFO_CTRL_STAT, 0x0, 0xffc7ffff, 1}, + INVAILD_REG_ITEM, /* VIU_OSD3_TEST_RDDATA 0x3d9d */ + {VIU_OSD3_PROT_CTRL, 0x0, 0xffff0000, 1}, + {VIU_OSD3_MALI_UNPACK_CTRL, 0x0, 0x9f01ffff, 1}, + {VIU_OSD3_DIMM_CTRL, 0x0, 0x7fffffff, 1}, +}; + +static struct reg_item osd1_sc_recovery_table_g12a[] = { + {VPP_OSD_VSC_PHASE_STEP, 0x0, 0x0fffffff, 1}, + {VPP_OSD_VSC_INI_PHASE, 0x0, 0xffffffff, 1}, + {VPP_OSD_VSC_CTRL0, 0x0, 0x01fb7b7f, 1}, + {VPP_OSD_HSC_PHASE_STEP, 0x0, 0x0fffffff, 1}, + {VPP_OSD_HSC_INI_PHASE, 0x0, 0xffffffff, 1}, + {VPP_OSD_HSC_CTRL0, 0x0, 0x007b7b7f, 1}, + {VPP_OSD_HSC_INI_PAT_CTRL, 0x0, 0x0000ff77, 1}, + {VPP_OSD_SC_DUMMY_DATA, 0x0, 0xffffffff, 0}, + {VPP_OSD_SC_CTRL0, 0x0, 0x0fff3ffc, 1}, + {VPP_OSD_SCI_WH_M1, 0x0, 0x1fff1fff, 1}, + {VPP_OSD_SCO_H_START_END, 0x0, 0x0fff0fff, 1}, + {VPP_OSD_SCO_V_START_END, 0x0, 0x0fff0fff, 1}, + {VPP_OSD_SCALE_COEF_IDX, 0x0, 0x0000c37f, 0}, + {VPP_OSD_SCALE_COEF, 0x0, 0xffffffff, 0} +}; + +static struct reg_item osd23_sc_recovery_table_g12a[] = { + {OSD2_VSC_PHASE_STEP, 0x0, 0x0fffffff, 1}, + {OSD2_VSC_INI_PHASE, 0x0, 0xffffffff, 1}, + {OSD2_VSC_CTRL0, 0x0, 0x01fb7b7f, 1}, + {OSD2_HSC_PHASE_STEP, 0x0, 0x0fffffff, 1}, + {OSD2_HSC_INI_PHASE, 0x0, 0xffffffff, 1}, + {OSD2_HSC_CTRL0, 0x0, 0x007b7b7f, 1}, + {OSD2_HSC_INI_PAT_CTRL, 0x0, 0x0000ff77, 1}, + {OSD2_SC_DUMMY_DATA, 0x0, 0xffffffff, 0}, + {OSD2_SC_CTRL0, 0x0, 0x0fff3ffc, 1}, + {OSD2_SCI_WH_M1, 0x0, 0x1fff1fff, 1}, + {OSD2_SCO_H_START_END, 0x0, 0x0fff0fff, 1}, + {OSD2_SCO_V_START_END, 0x0, 0x0fff0fff, 1}, + INVAILD_REG_ITEM, /* 0x3d0c */ + INVAILD_REG_ITEM, /* 0x3d0d */ + INVAILD_REG_ITEM, /* 0x3d0e */ + INVAILD_REG_ITEM, /* 0x3d0f */ + INVAILD_REG_ITEM, /* 0x3d10 */ + INVAILD_REG_ITEM, /* 0x3d11 */ + INVAILD_REG_ITEM, /* 0x3d12 */ + INVAILD_REG_ITEM, /* 0x3d13 */ + INVAILD_REG_ITEM, /* 0x3d14 */ + INVAILD_REG_ITEM, /* 0x3d15 */ + INVAILD_REG_ITEM, /* 0x3d16 */ + INVAILD_REG_ITEM, /* 0x3d17 */ + {OSD2_SCALE_COEF_IDX, 0x0, 0x0000c37f, 0}, + {OSD2_SCALE_COEF, 0x0, 0xffffffff, 0}, + INVAILD_REG_ITEM, /* 0x3d1a */ + INVAILD_REG_ITEM, /* 0x3d1b */ + INVAILD_REG_ITEM, /* 0x3d1c */ + INVAILD_REG_ITEM, /* 0x3d1d */ + {OSD34_SCALE_COEF_IDX, 0x0, 0x0000c37f, 0}, + {OSD34_SCALE_COEF, 0x0, 0xffffffff, 0}, + {OSD34_VSC_PHASE_STEP, 0x0, 0x0fffffff, 1}, + {OSD34_VSC_INI_PHASE, 0x0, 0xffffffff, 1}, + {OSD34_VSC_CTRL0, 0x0, 0x01fb7b7f, 1}, + {OSD34_HSC_PHASE_STEP, 0x0, 0x0fffffff, 1}, + {OSD34_HSC_INI_PHASE, 0x0, 0xffffffff, 1}, + {OSD34_HSC_CTRL0, 0x0, 0x007b7b7f, 1}, + {OSD34_HSC_INI_PAT_CTRL, 0x0, 0x0000ff77, 1}, + {OSD34_SC_DUMMY_DATA, 0x0, 0xffffffff, 0}, + {OSD34_SC_CTRL0, 0x0, 0x0fff3ffc, 1}, + {OSD34_SCI_WH_M1, 0x0, 0x1fff1fff, 1}, + {OSD34_SCO_H_START_END, 0x0, 0x0fff0fff, 1}, + {OSD34_SCO_V_START_END, 0x0, 0x0fff0fff, 1}, +}; + +static struct reg_item vpu_afbcd_recovery_table_g12a[] = { + { + VPU_MAFBC_BLOCK_ID, + 0x0, 0xffffffff, 0 + }, + { + VPU_MAFBC_IRQ_RAW_STATUS, + 0x0, 0x0000003f, 0 + }, + { + VPU_MAFBC_IRQ_CLEAR, + 0x0, 0x0000003f, 0 + }, + { + VPU_MAFBC_IRQ_MASK, + 0x0, 0x0000003f, 1 + }, + { + VPU_MAFBC_IRQ_STATUS, + 0x0, 0x0000003f, 0 + }, + { + VPU_MAFBC_COMMAND, + 0x0, 0x00000003, 0 + }, + { + VPU_MAFBC_STATUS, + 0x0, 0x00000007, 0 + }, + { + VPU_MAFBC_SURFACE_CFG, + 0x0, 0x0001000f, 1 + } +}; + +static struct reg_item osd1_afbcd_recovery_table_g12a[] = { + { + VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0, + 0x0, 0xffffffff, 1 + }, + { + VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0, + 0x0, 0x0000ffff, 1 + }, + { + VPU_MAFBC_FORMAT_SPECIFIER_S0, + 0x0, 0x000f030f, 1 + }, + { + VPU_MAFBC_BUFFER_WIDTH_S0, + 0x0, 0x00003fff, 1 + }, + { + VPU_MAFBC_BUFFER_HEIGHT_S0, + 0x0, 0x00003fff, 1 + }, + { + VPU_MAFBC_BOUNDING_BOX_X_START_S0, + 0x0, 0x00001fff, 1 + }, + { + VPU_MAFBC_BOUNDING_BOX_X_END_S0, + 0x0, 0x00001fff, 1 + }, + { + VPU_MAFBC_BOUNDING_BOX_Y_START_S0, + 0x0, 0x00001fff, 1 + }, + { + VPU_MAFBC_BOUNDING_BOX_Y_END_S0, + 0x0, 0x00001fff, 1 + }, + { + VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0, + 0x0, 0xffffffff, 1 + }, + { + VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0, + 0x0, 0x0000ffff, 1 + }, + { + VPU_MAFBC_OUTPUT_BUF_STRIDE_S0, + 0x0, 0x0000ffff, 1 + }, + { + VPU_MAFBC_PREFETCH_CFG_S0, 0x0, 3, 1 + } +}; + +static struct reg_item osd2_afbcd_recovery_table_g12a[] = { + { + VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1, + 0x0, 0xffffffff, 1 + }, + { + VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S1, + 0x0, 0x0000ffff, 1 + }, + { + VPU_MAFBC_FORMAT_SPECIFIER_S1, + 0x0, 0x000f030f, 1 + }, + { + VPU_MAFBC_BUFFER_WIDTH_S1, + 0x0, 0x00003fff, 1 + }, + { + VPU_MAFBC_BUFFER_HEIGHT_S1, + 0x0, 0x00003fff, 1 + }, + { + VPU_MAFBC_BOUNDING_BOX_X_START_S1, + 0x0, 0x00001fff, 1 + }, + { + VPU_MAFBC_BOUNDING_BOX_X_END_S1, + 0x0, 0x00001fff, 1 + }, + { + VPU_MAFBC_BOUNDING_BOX_Y_START_S1, + 0x0, 0x00001fff, 1 + }, + { + VPU_MAFBC_BOUNDING_BOX_Y_END_S1, + 0x0, 0x00001fff, 1 + }, + { + VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S1, + 0x0, 0xffffffff, 1 + }, + { + VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S1, + 0x0, 0x0000ffff, 1 + }, + { + VPU_MAFBC_OUTPUT_BUF_STRIDE_S1, + 0x0, 0x0000ffff, 1 + }, + { + VPU_MAFBC_PREFETCH_CFG_S1, 0x0, 3, 1 + } +}; + +static struct reg_item osd3_afbcd_recovery_table_g12a[] = { + { + VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2, + 0x0, 0xffffffff, 1 + }, + { + VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S2, + 0x0, 0x0000ffff, 1 + }, + { + VPU_MAFBC_FORMAT_SPECIFIER_S2, + 0x0, 0x000f030f, 1 + }, + { + VPU_MAFBC_BUFFER_WIDTH_S2, + 0x0, 0x00003fff, 1 + }, + { + VPU_MAFBC_BUFFER_HEIGHT_S2, + 0x0, 0x00003fff, 1 + }, + { + VPU_MAFBC_BOUNDING_BOX_X_START_S2, + 0x0, 0x00001fff, 1 + }, + { + VPU_MAFBC_BOUNDING_BOX_X_END_S2, + 0x0, 0x00001fff, 1 + }, + { + VPU_MAFBC_BOUNDING_BOX_Y_START_S2, + 0x0, 0x00001fff, 1 + }, + { + VPU_MAFBC_BOUNDING_BOX_Y_END_S2, + 0x0, 0x00001fff, 1 + }, + { + VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S2, + 0x0, 0xffffffff, 1 + }, + { + VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S2, + 0x0, 0x0000ffff, 1 + }, + { + VPU_MAFBC_OUTPUT_BUF_STRIDE_S2, + 0x0, 0x0000ffff, 1 + }, + { + VPU_MAFBC_PREFETCH_CFG_S1, 0x0, 3, 1 + } +}; + +static struct reg_item blend_recovery_table_g12a[] = { + {VIU_OSD_BLEND_CTRL, 0x0, 0xffffffff, 1}, + {VIU_OSD_BLEND_DIN0_SCOPE_H, 0x0, 0x1fff1fff, 1}, + {VIU_OSD_BLEND_DIN0_SCOPE_V, 0x0, 0x1fff1fff, 1}, + {VIU_OSD_BLEND_DIN1_SCOPE_H, 0x0, 0x1fff1fff, 1}, + {VIU_OSD_BLEND_DIN1_SCOPE_V, 0x0, 0x1fff1fff, 1}, + {VIU_OSD_BLEND_DIN2_SCOPE_H, 0x0, 0x1fff1fff, 1}, + {VIU_OSD_BLEND_DIN2_SCOPE_V, 0x0, 0x1fff1fff, 1}, + {VIU_OSD_BLEND_DIN3_SCOPE_H, 0x0, 0x1fff1fff, 1}, + {VIU_OSD_BLEND_DIN3_SCOPE_V, 0x0, 0x1fff1fff, 1}, + {VIU_OSD_BLEND_DUMMY_DATA0, 0x0, 0x00ffffff, 1}, + {VIU_OSD_BLEND_DUMMY_ALPHA, 0x0, 0x1fffffff, 1}, + {VIU_OSD_BLEND_BLEND0_SIZE, 0x0, 0x1fff1fff, 1}, + {VIU_OSD_BLEND_BLEND1_SIZE, 0x0, 0x1fff1fff, 1}, + INVAILD_REG_ITEM, /* 0x39bd */ + INVAILD_REG_ITEM, /* 0x39be */ + INVAILD_REG_ITEM, /* 0x39bf */ + {VIU_OSD_BLEND_CTRL1, 0x0, 0x00037337, 1}, +}; + +static struct reg_item post_blend_recovery_table_g12a[] = { + {VPP_VD2_HDR_IN_SIZE, 0x0, 0x1fff1fff, 0}, + {VPP_OSD1_IN_SIZE, 0x0, 0x1fff1fff, 1}, + INVAILD_REG_ITEM, /* 0x1df2 */ + INVAILD_REG_ITEM, /* 0x1df3 */ + INVAILD_REG_ITEM, /* 0x1df4 */ + {VPP_OSD1_BLD_H_SCOPE, 0x0, 0x1fff1fff, 1}, + {VPP_OSD1_BLD_V_SCOPE, 0x0, 0x1fff1fff, 1}, + {VPP_OSD2_BLD_H_SCOPE, 0x0, 0x1fff1fff, 1}, + {VPP_OSD2_BLD_V_SCOPE, 0x0, 0x1fff1fff, 1}, + INVAILD_REG_ITEM, /* 0x1df9 */ + INVAILD_REG_ITEM, /* 0x1dfa */ + INVAILD_REG_ITEM, /* 0x1dfb */ + INVAILD_REG_ITEM, /* 0x1dfc */ + {OSD1_BLEND_SRC_CTRL, 0x0, 0x00110f1f, 1}, + {OSD2_BLEND_SRC_CTRL, 0x0, 0x00110f1f, 1}, +}; + +static struct reg_item misc_recovery_table_g12a[] = { + {DOLBY_PATH_CTRL, 0x0, 0x000000cc, 1}, + {OSD_PATH_MISC_CTRL, 0x0, 0x000000ff, 1}, + {VIU_OSD1_DIMM_CTRL, 0x0, 0x7fffffff, 1}, + {VIU_OSD2_DIMM_CTRL, 0x0, 0x7fffffff, 1}, + {VIU_OSD2_BLK0_CFG_W4, 0x0, 0x0fff0fff, 1}, + {VIU_OSD2_BLK1_CFG_W4, 0x0, 0xffffffff, 1}, + {VIU_OSD2_BLK2_CFG_W4, 0x0, 0xffffffff, 1}, + {VIU_OSD2_MALI_UNPACK_CTRL, 0x0, 0x9f01ffff, 1}, +}; + +static void recovery_regs_init_old(void) { int i = 0, j; int cpu_id = osd_hw.osd_meson_dev.cpu_id; - if (recovery_enable) - return; - memset(gRecovery, 0, sizeof(gRecovery)); gRecovery[i].base_addr = VIU_OSD1_CTRL_STAT; gRecovery[i].size = sizeof(osd1_recovery_table) / sizeof(struct reg_item); @@ -339,10 +751,105 @@ void recovery_regs_init(void) / sizeof(struct reg_item); gRecovery[i].table = (struct reg_item *)&misc_recovery_table[0]; +} + +static void recovery_regs_init_g12a(void) +{ + int i = 0; + + gRecovery[i].base_addr = VIU_OSD1_CTRL_STAT; + gRecovery[i].size = sizeof(osd12_recovery_table_g12a) + / sizeof(struct reg_item); + gRecovery[i].table = + (struct reg_item *)&osd12_recovery_table_g12a[0]; + + i++; + gRecovery[i].base_addr = VIU_OSD3_CTRL_STAT; + gRecovery[i].size = sizeof(osd3_recovery_table_g12a) + / sizeof(struct reg_item); + gRecovery[i].table = + (struct reg_item *)&osd3_recovery_table_g12a[0]; + + i++; + gRecovery[i].base_addr = VPP_OSD_VSC_PHASE_STEP; + gRecovery[i].size = sizeof(osd1_sc_recovery_table_g12a) + / sizeof(struct reg_item); + gRecovery[i].table = + (struct reg_item *)&osd1_sc_recovery_table_g12a[0]; + + i++; + gRecovery[i].base_addr = OSD2_VSC_PHASE_STEP; + gRecovery[i].size = sizeof(osd23_sc_recovery_table_g12a) + / sizeof(struct reg_item); + gRecovery[i].table = + (struct reg_item *)&osd23_sc_recovery_table_g12a[0]; + + i++; + gRecovery[i].base_addr = VPU_MAFBC_BLOCK_ID; + gRecovery[i].size = sizeof(vpu_afbcd_recovery_table_g12a) + / sizeof(struct reg_item); + gRecovery[i].table = + (struct reg_item *)&vpu_afbcd_recovery_table_g12a[0]; + + i++; + gRecovery[i].base_addr = VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0; + gRecovery[i].size = sizeof(osd1_afbcd_recovery_table_g12a) + / sizeof(struct reg_item); + gRecovery[i].table = + (struct reg_item *)&osd1_afbcd_recovery_table_g12a[0]; + + i++; + gRecovery[i].base_addr = VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1; + gRecovery[i].size = sizeof(osd2_afbcd_recovery_table_g12a) + / sizeof(struct reg_item); + gRecovery[i].table = + (struct reg_item *)&osd2_afbcd_recovery_table_g12a[0]; + + i++; + gRecovery[i].base_addr = VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2; + gRecovery[i].size = sizeof(osd3_afbcd_recovery_table_g12a) + / sizeof(struct reg_item); + gRecovery[i].table = + (struct reg_item *)&osd3_afbcd_recovery_table_g12a[0]; + + i++; + gRecovery[i].base_addr = VIU_OSD_BLEND_CTRL; + gRecovery[i].size = sizeof(blend_recovery_table_g12a) + / sizeof(struct reg_item); + gRecovery[i].table = + (struct reg_item *)&blend_recovery_table_g12a[0]; + + i++; + gRecovery[i].base_addr = VPP_VD2_HDR_IN_SIZE; + gRecovery[i].size = sizeof(post_blend_recovery_table_g12a) + / sizeof(struct reg_item); + gRecovery[i].table = + (struct reg_item *)&post_blend_recovery_table_g12a[0]; + + i++; + gRecovery[i].base_addr = 0xffffffff; /* not base addr */ + gRecovery[i].size = sizeof(misc_recovery_table_g12a) + / sizeof(struct reg_item); + gRecovery[i].table = + (struct reg_item *)&misc_recovery_table_g12a[0]; +} + +void recovery_regs_init(void) +{ + int cpu_id = osd_hw.osd_meson_dev.cpu_id; + + if (recovery_enable) + return; + memset(gRecovery, 0, sizeof(gRecovery)); + + if (cpu_id == __MESON_CPU_MAJOR_ID_G12A) + recovery_regs_init_g12a(); + else + recovery_regs_init_old(); recovery_enable = 1; } -int update_recovery_item(u32 addr, u32 value) +static int update_recovery_item_old(u32 addr, u32 value) { u32 base, size; int i; @@ -450,7 +957,7 @@ int update_recovery_item(u32 addr, u32 value) return ret; } -s32 get_recovery_item(u32 addr, u32 *value, u32 *mask) +static s32 get_recovery_item_old(u32 addr, u32 *value, u32 *mask) { u32 base, size; int i; @@ -574,6 +1081,481 @@ s32 get_recovery_item(u32 addr, u32 *value, u32 *mask) */ return ret; } + +static int update_recovery_item_g12a(u32 addr, u32 value) +{ + u32 base, size; + int i; + struct reg_item *table = NULL; + int ret = -1; + + if (!recovery_enable) + return ret; + + base = addr & 0xfff0; + switch (base) { + case VIU_OSD1_CTRL_STAT: + case VIU_OSD1_BLK1_CFG_W1: + /* osd1 */ + if (backup_enable & + HW_RESET_OSD1_REGS) { + ret = 1; + break; + } + base = gRecovery[0].base_addr; + size = gRecovery[0].size; + table = gRecovery[0].table; + if ((addr >= base) && + (addr < base + size)) { + table[addr - base].val = value; + if (table[addr - base].recovery) + table[addr - base].recovery = 1; + ret = 0; + } + break; + case VIU_OSD2_CTRL_STAT: + case VIU_OSD2_BLK1_CFG_W1: + /* osd2 */ + if (backup_enable & + HW_RESET_OSD2_REGS) { + ret = 1; + break; + } + base = gRecovery[0].base_addr; + size = gRecovery[0].size; + table = gRecovery[0].table; + if ((addr >= base) && + (addr < base + size)) { + table[addr - base].val = value; + if (table[addr - base].recovery) + table[addr - base].recovery = 1; + ret = 0; + } + break; + case VIU_OSD3_CTRL_STAT: + case VIU_OSD3_BLK0_CFG_W2: + /* osd3 */ + if (backup_enable & + HW_RESET_OSD3_REGS) { + ret = 1; + break; + } + base = gRecovery[1].base_addr; + size = gRecovery[1].size; + table = gRecovery[1].table; + if ((addr >= base) && + (addr < base + size)) { + table[addr - base].val = value; + if (table[addr - base].recovery) + table[addr - base].recovery = 1; + ret = 0; + } + break; + case VPP_OSD_VSC_PHASE_STEP: + /* osd1 sc */ + base = gRecovery[2].base_addr; + size = gRecovery[2].size; + table = gRecovery[2].table; + if ((addr >= base) && + (addr < base + size)) { + table[addr - base].val = value; + if (table[addr - base].recovery) + table[addr - base].recovery = 1; + ret = 0; + } + break; + case OSD2_VSC_PHASE_STEP: + case 0x3d10: + case OSD34_VSC_PHASE_STEP: + /* osd2 osd 3 sc */ + base = gRecovery[3].base_addr; + size = gRecovery[3].size; + table = gRecovery[3].table; + if ((addr >= base) && + (addr < base + size)) { + table[addr - base].val = value; + if (table[addr - base].recovery) + table[addr - base].recovery = 1; + ret = 0; + } + break; + case VPU_MAFBC_BLOCK_ID: + /* vpu mali common */ + if (backup_enable & + HW_RESET_MALI_AFBCD_REGS) { + ret = 1; + break; + } + base = gRecovery[4].base_addr; + size = gRecovery[4].size; + table = gRecovery[4].table; + if ((addr >= base) && + (addr < base + size)) { + table[addr - base].val = value; + if (table[addr - base].recovery) + table[addr - base].recovery = 1; + ret = 0; + } + break; + case VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0: + /* vpu mali src0 */ + if (backup_enable & + HW_RESET_MALI_AFBCD_REGS) { + ret = 1; + break; + } + base = gRecovery[5].base_addr; + size = gRecovery[5].size; + table = gRecovery[5].table; + if ((addr >= base) && + (addr < base + size)) { + table[addr - base].val = value; + if (table[addr - base].recovery) + table[addr - base].recovery = 1; + ret = 0; + } + break; + case VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1: + /* vpu mali src1 */ + if (backup_enable & + HW_RESET_MALI_AFBCD_REGS) { + ret = 1; + break; + } + base = gRecovery[6].base_addr; + size = gRecovery[6].size; + table = gRecovery[6].table; + if ((addr >= base) && + (addr < base + size)) { + table[addr - base].val = value; + if (table[addr - base].recovery) + table[addr - base].recovery = 1; + ret = 0; + } + break; + case VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2: + /* vpu mali src2 */ + if (backup_enable & + HW_RESET_MALI_AFBCD_REGS) { + ret = 1; + break; + } + base = gRecovery[7].base_addr; + size = gRecovery[7].size; + table = gRecovery[7].table; + if ((addr >= base) && + (addr < base + size)) { + table[addr - base].val = value; + if (table[addr - base].recovery) + table[addr - base].recovery = 1; + ret = 0; + } + break; + case VIU_OSD_BLEND_CTRL: + case VIU_OSD_BLEND_CTRL1: + /* osd blend ctrl */ + base = gRecovery[8].base_addr; + size = gRecovery[8].size; + table = gRecovery[8].table; + if ((addr >= base) && + (addr < base + size)) { + table[addr - base].val = value; + if (table[addr - base].recovery) + table[addr - base].recovery = 1; + ret = 0; + } + break; + case VPP_VD2_HDR_IN_SIZE: + /* vpp blend ctrl */ + base = gRecovery[9].base_addr; + size = gRecovery[9].size; + table = gRecovery[9].table; + if ((addr >= base) && + (addr < base + size)) { + table[addr - base].val = value; + if (table[addr - base].recovery) + table[addr - base].recovery = 1; + ret = 0; + } + break; + default: + break; + } + + if ((addr == OSD_PATH_MISC_CTRL) || + (addr == VIU_OSD1_DIMM_CTRL) || + (addr == VIU_OSD2_DIMM_CTRL) || + (addr == VIU_OSD2_BLK0_CFG_W4) || + (addr == VIU_OSD2_BLK1_CFG_W4) || + (addr == VIU_OSD2_BLK2_CFG_W4) || + (addr == VIU_OSD2_MALI_UNPACK_CTRL)) { + table = gRecovery[10].table; + for (i = 0; i < gRecovery[10].size; i++) { + if (addr == table[i].addr) { + table[i].val = value; + if (table[i].recovery) + table[i].recovery = 1; + ret = 0; + break; + } + } + } + return ret; +} + +static s32 get_recovery_item_g12a(u32 addr, u32 *value, u32 *mask) +{ + u32 base, size; + int i; + struct reg_item *table = NULL; + int ret = -1; + + if (!recovery_enable) + return ret; + + base = addr & 0xfff0; + switch (base) { + case VIU_OSD1_CTRL_STAT: + case VIU_OSD1_BLK1_CFG_W1: + /* osd1 */ + if (backup_enable & + HW_RESET_OSD1_REGS) { + ret = 2; + break; + } + base = gRecovery[0].base_addr; + size = gRecovery[0].size; + table = gRecovery[0].table; + if ((addr >= base) && + (addr < base + size)) { + table += (addr - base); + ret = 0; + } + break; + case VIU_OSD2_CTRL_STAT: + case VIU_OSD2_BLK1_CFG_W1: + /* osd2 */ + if (backup_enable & + HW_RESET_OSD2_REGS) { + ret = 2; + break; + } + base = gRecovery[0].base_addr; + size = gRecovery[0].size; + table = gRecovery[0].table; + if ((addr >= base) && + (addr < base + size)) { + table += (addr - base); + ret = 0; + } + break; + case VIU_OSD3_CTRL_STAT: + case VIU_OSD3_BLK0_CFG_W2: + /* osd3 */ + if (backup_enable & + HW_RESET_OSD3_REGS) { + ret = 2; + break; + } + base = gRecovery[1].base_addr; + size = gRecovery[1].size; + table = gRecovery[1].table; + if ((addr >= base) && + (addr < base + size)) { + table += (addr - base); + ret = 0; + } + break; + case VPP_OSD_VSC_PHASE_STEP: + /* osd1 sc */ + base = gRecovery[2].base_addr; + size = gRecovery[2].size; + table = gRecovery[2].table; + if ((addr >= base) && + (addr < base + size)) { + table += (addr - base); + ret = 0; + } + break; + case OSD2_VSC_PHASE_STEP: + case 0x3d10: + case OSD34_VSC_PHASE_STEP: + /* osd2 osd 3 sc */ + base = gRecovery[3].base_addr; + size = gRecovery[3].size; + table = gRecovery[3].table; + if ((addr >= base) && + (addr < base + size)) { + table += (addr - base); + ret = 0; + } + break; + case VPU_MAFBC_BLOCK_ID: + /* vpu mali common */ + if (backup_enable & + HW_RESET_MALI_AFBCD_REGS) { + ret = 2; + break; + } + base = gRecovery[4].base_addr; + size = gRecovery[4].size; + table = gRecovery[4].table; + if ((addr >= base) && + (addr < base + size)) { + table += (addr - base); + ret = 0; + } + break; + case VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0: + /* vpu mali src0 */ + if (backup_enable & + HW_RESET_MALI_AFBCD_REGS) { + ret = 2; + break; + } + base = gRecovery[5].base_addr; + size = gRecovery[5].size; + table = gRecovery[5].table; + if ((addr >= base) && + (addr < base + size)) { + table += (addr - base); + ret = 0; + } + break; + case VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1: + /* vpu mali src1 */ + if (backup_enable & + HW_RESET_MALI_AFBCD_REGS) { + ret = 2; + break; + } + base = gRecovery[6].base_addr; + size = gRecovery[6].size; + table = gRecovery[6].table; + if ((addr >= base) && + (addr < base + size)) { + table += (addr - base); + ret = 0; + } + break; + case VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2: + /* vpu mali src2 */ + if (backup_enable & + HW_RESET_MALI_AFBCD_REGS) { + ret = 2; + break; + } + base = gRecovery[7].base_addr; + size = gRecovery[7].size; + table = gRecovery[7].table; + if ((addr >= base) && + (addr < base + size)) { + table += (addr - base); + ret = 0; + } + break; + case VIU_OSD_BLEND_CTRL: + case VIU_OSD_BLEND_CTRL1: + /* osd blend ctrl */ + base = gRecovery[8].base_addr; + size = gRecovery[8].size; + table = gRecovery[8].table; + if ((addr >= base) && + (addr < base + size)) { + table += (addr - base); + ret = 0; + } + break; + case VPP_VD2_HDR_IN_SIZE: + /* vpp blend ctrl */ + base = gRecovery[9].base_addr; + size = gRecovery[9].size; + table = gRecovery[9].table; + if ((addr >= base) && + (addr < base + size)) { + table += (addr - base); + ret = 0; + } + break; + default: + break; + } + + if ((addr == OSD_PATH_MISC_CTRL) || + (addr == VIU_OSD1_DIMM_CTRL) || + (addr == VIU_OSD2_DIMM_CTRL) || + (addr == VIU_OSD2_BLK0_CFG_W4) || + (addr == VIU_OSD2_BLK1_CFG_W4) || + (addr == VIU_OSD2_BLK2_CFG_W4) || + (addr == VIU_OSD2_MALI_UNPACK_CTRL)) { + table = gRecovery[10].table; + for (i = 0; i < gRecovery[10].size; i++) { + if (addr == table[i].addr) { + table += i; + ret = 0; + break; + } + } + } + if (ret == 0 && table) { + if (table->recovery == 1) { + u32 regmask = table->mask; + u32 real_value = osd_reg_read(addr); + + if ((real_value & regmask) + == (table->val & regmask)) { + ret = 1; + *mask = regmask; + *value = real_value; + } else { + *mask = regmask; + *value = real_value & ~(regmask); + *value |= (table->val & regmask); + } + table->recovery = 2; + } else if (table->recovery == 2) + ret = 1; + else + ret = -1; + } + /* ret = 1, 2 need not recovery, + * ret = 0 need recovery, + * ret = -1, not find + */ + return ret; +} + +int update_recovery_item(u32 addr, u32 value) +{ + int ret = -1; + int cpu_id = osd_hw.osd_meson_dev.cpu_id; + + if (!recovery_enable) + return ret; + + if (cpu_id == __MESON_CPU_MAJOR_ID_G12A) + ret = update_recovery_item_g12a(addr, value); + else + ret = update_recovery_item_old(addr, value); + + return ret; +} + +s32 get_recovery_item(u32 addr, u32 *value, u32 *mask) +{ + int ret = -1; + int cpu_id = osd_hw.osd_meson_dev.cpu_id; + + if (!recovery_enable) + return ret; + + if (cpu_id == __MESON_CPU_MAJOR_ID_G12A) + ret = get_recovery_item_g12a(addr, value, mask); + else + ret = get_recovery_item_old(addr, value, mask); + + return ret; +} #if 0 void recovery_regs_init(void) { diff --git a/drivers/amlogic/media/osd/osd_backup.h b/drivers/amlogic/media/osd/osd_backup.h index 877b8b93b4a8..9831522627b0 100644 --- a/drivers/amlogic/media/osd/osd_backup.h +++ b/drivers/amlogic/media/osd/osd_backup.h @@ -26,7 +26,7 @@ #define OSD_VALUE_COUNT (VIU_OSD1_CTRL_STAT2 - VIU_OSD1_CTRL_STAT + 1) #define OSD_AFBC_VALUE_COUNT (OSD1_AFBCD_PIXEL_VSCOPE - OSD1_AFBCD_ENABLE + 1) #define MALI_AFBC_VALUE_COUNT \ - (VPU_MAFBC_PREFETCH_CFG_S2 - VPU_MAFBC_COMMAND + 1) + (VPU_MAFBC_PREFETCH_CFG_S2 - VPU_MAFBC_IRQ_MASK + 1) extern const u16 osd_reg_backup[OSD_REG_BACKUP_COUNT]; extern const u16 osd_afbc_reg_backup[OSD_AFBC_REG_BACKUP_COUNT]; @@ -39,6 +39,8 @@ enum hw_reset_flag_e { HW_RESET_NONE = 0, HW_RESET_AFBCD_REGS = 0x80000000, HW_RESET_OSD1_REGS = 0x00000001, + HW_RESET_OSD2_REGS = 0x00000002, + HW_RESET_OSD3_REGS = 0x00000004, HW_RESET_AFBCD_HARDWARE = 0x80000000, HW_RESET_MALI_AFBCD_REGS = 0x200000, }; diff --git a/drivers/amlogic/media/osd/osd_drm.c b/drivers/amlogic/media/osd/osd_drm.c index bcfd3ffc9b21..f083db721b2d 100644 --- a/drivers/amlogic/media/osd/osd_drm.c +++ b/drivers/amlogic/media/osd/osd_drm.c @@ -732,9 +732,9 @@ void osd_drm_vsync_isr_handler(void) /* go through update list */ walk_through_update_list(); osd_update_3d_mode(); + osd_mali_afbc_start(); osd_update_vsync_hit(); osd_hw_reset(); - osd_mali_afbc_restart(); } else { if (get_cpu_type() != MESON_CPU_MAJOR_ID_AXG) osd_rdma_interrupt_done_clear(); diff --git a/drivers/amlogic/media/osd/osd_hw.c b/drivers/amlogic/media/osd/osd_hw.c index 7a33e029a78d..fb02afb81222 100644 --- a/drivers/amlogic/media/osd/osd_hw.c +++ b/drivers/amlogic/media/osd/osd_hw.c @@ -1129,7 +1129,7 @@ void osd_hw_reset(void) int i; u32 addr; u32 value; - u32 base = VPU_MAFBC_COMMAND; + u32 base = VPU_MAFBC_IRQ_MASK; for (i = 0; i < MALI_AFBC_REG_BACKUP_COUNT; i++) { addr = mali_afbc_reg_backup[i]; @@ -1137,8 +1137,8 @@ void osd_hw_reset(void) VSYNCOSD_IRQ_WR_MPEG_REG( addr, value); } + VSYNCOSD_IRQ_WR_MPEG_REG(VPU_MAFBC_COMMAND, 1); } - } else osd_rdma_reset_and_flush(reset_bit); spin_unlock_irqrestore(&osd_lock, lock_flags); @@ -1182,9 +1182,9 @@ static irqreturn_t vsync_isr(int irq, void *dev_id) /* go through update list */ walk_through_update_list(); osd_update_3d_mode(); + osd_mali_afbc_start(); osd_update_vsync_hit(); osd_hw_reset(); - osd_mali_afbc_restart(); } else osd_rdma_interrupt_done_clear(); @@ -2361,7 +2361,7 @@ void osd_set_premult(u32 index, u32 premult) void osd_get_afbc_debug(u32 *val1, u32 *val2, u32 *val3, u32 *val4) { - *val1 = osd_hw.afbc_restart_in_vsync; + *val1 = osd_hw.afbc_start_in_vsync; *val2 = osd_hw.afbc_force_reset; *val3 = osd_hw.afbc_status_err_reset; *val4 = osd_hw.afbc_use_latch; @@ -2369,7 +2369,7 @@ void osd_get_afbc_debug(u32 *val1, u32 *val2, u32 *val3, u32 *val4) void osd_set_afbc_debug(u32 val1, u32 val2, u32 val3, u32 val4) { - osd_hw.afbc_restart_in_vsync = val1; + osd_hw.afbc_start_in_vsync = val1; osd_hw.afbc_force_reset = val2; osd_hw.afbc_status_err_reset = val3; osd_hw.afbc_use_latch = val4; @@ -2420,31 +2420,31 @@ const struct color_bit_define_s extern_color_format_array[] = { { COLOR_INDEX_32_ABGR, 2, 5, 0, 8, 0, 8, 8, 0, 16, 8, 0, 24, 8, 0, - 0, 4 + 0, 32 }, /*32 bit color RGBX */ { COLOR_INDEX_32_XBGR, 2, 5, 0, 8, 0, 8, 8, 0, 16, 8, 0, 24, 0, 0, - 0, 4 + 0, 32 }, /*24 bit color RGB */ { COLOR_INDEX_24_RGB, 5, 7, 16, 8, 0, 8, 8, 0, 0, 8, 0, 0, 0, 0, - 0, 3 + 0, 24 }, /*16 bit color BGR */ { COLOR_INDEX_16_565, 4, 4, 11, 5, 0, 5, 6, 0, 0, 5, 0, 0, 0, 0, - 0, 2 + 0, 16 }, /*32 bit color BGRA */ { COLOR_INDEX_32_ARGB, 1, 5, 16, 8, 0, 8, 8, 0, 0, 8, 0, 24, 8, 0, - 0, 4 + 0, 32 }, }; @@ -2472,7 +2472,7 @@ static bool osd_ge2d_compose_pan_display(struct osd_fence_map_s *fence_map) canvas_config(osd_hw.fb_gem[index].canvas_idx, fence_map->ext_addr, CANVAS_ALIGNED(fence_map->width * - osd_hw.color_info[index]->bpp), + (osd_hw.color_info[index]->bpp >> 3)), fence_map->height, CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); @@ -2856,6 +2856,8 @@ static void osd_pan_display_fence(struct osd_fence_map_s *fence_map) osd_hw.reg[OSD_ENABLE] .update_func(index); } + if (osd_hw.hw_rdma_en) + osd_mali_afbc_start(); spin_unlock_irqrestore(&osd_lock, lock_flags); osd_wait_vsync_hw(); } else if (xoffset != osd_hw.pandata[index].x_start @@ -2964,6 +2966,8 @@ static void osd_pan_display_fence(struct osd_fence_map_s *fence_map) osd_hw.reg[OSD_ENABLE] .update_func(index); } + if (osd_hw.hw_rdma_en) + osd_mali_afbc_start(); spin_unlock_irqrestore(&osd_lock, lock_flags); osd_wait_vsync_hw(); } else if ((osd_enable != osd_hw.enable[index]) @@ -2973,6 +2977,8 @@ static void osd_pan_display_fence(struct osd_fence_map_s *fence_map) if (!osd_hw.osd_display_debug) osd_hw.reg[OSD_ENABLE] .update_func(index); + if (osd_hw.hw_rdma_en) + osd_mali_afbc_start(); spin_unlock_irqrestore(&osd_lock, lock_flags); osd_wait_vsync_hw(); } @@ -3830,11 +3836,11 @@ static void osd_update_color_mode(u32 index) /* 0 Block split mode off. * 1 Block split mode on. */ - u32 yuv_transform = 0; + u32 yuv_transform = 1; /* 0 Internal YUV transform off. * 1 Internal YUV transform on. */ - u32 afbc_color_reorder = 0x4321; + u32 afbc_color_reorder = 0x1234; /* 0x4321 = ABGR * 0x1234 = RGBA */ @@ -3969,10 +3975,12 @@ static void osd_update_enable(u32 index) VSYNCOSD_WR_MPEG_REG_BITS( VIU_MISC_CTRL1, 0x90, 8, 8); } - } else if ( - osd_hw.osd_meson_dev.afbc_type == MALI_AFBC) { + } else if (osd_hw.osd_meson_dev.afbc_type + == MALI_AFBC) { if (osd_hw.enable[index] == ENABLE) { /* enable mali afbc */ + VSYNCOSD_WR_MPEG_REG( + VPU_MAFBC_IRQ_MASK, 0xf); VSYNCOSD_WR_MPEG_REG_BITS( VPU_MAFBC_SURFACE_CFG, 1, index, 1); @@ -3985,8 +3993,30 @@ static void osd_update_enable(u32 index) 0, index, 1); osd_hw.osd_afbcd[index].afbc_start = 0; } + VSYNCOSD_WR_MPEG_REG_BITS( + osd_reg->osd_ctrl_stat2, 1, 1, 1); } } + if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE) { + u8 postbld_src_sel = 0; + + if (osd_hw.enable[index] == ENABLE) + postbld_src_sel = (index == 0) ? 3 : 4; + if (index == 0) + VSYNCOSD_WR_MPEG_REG(OSD1_BLEND_SRC_CTRL, + (0 & 0xf) << 0 | + (0 & 0x1) << 4 | + (postbld_src_sel & 0xf) << 8 | + (0 & 0x1) << 16| + (1 & 0x1) << 20); + else if (index == 1) + VSYNCOSD_WR_MPEG_REG(OSD2_BLEND_SRC_CTRL, + (0 & 0xf) << 0 | + (0 & 0x1) << 4 | + (postbld_src_sel & 0xf) << 8 | + (0 & 0x1) << 16 | + (1 & 0x1) << 20); + } remove_from_update_list(index, OSD_ENABLE); } @@ -4240,7 +4270,7 @@ static int blend_din_to_osd( blending->osd_to_bdin_table[blend_din_index]; if ((osd_index > OSD3) || (osd_index < OSD1)) { - osd_log_err("blend_din:%d no match osd find!\n", + osd_log_dbg("blend_din:%d no match osd find!\n", blend_din_index); return -1; } else @@ -5082,7 +5112,7 @@ static void osd_setting_default_hwc(void) u32 din3_osd_sel = 1; u32 din_reoder_sel = 0x1; u32 postbld_src3_sel = 3, postbld_src4_sel = 0; - u32 postbld_osd1_premult = 1, postbld_osd2_premult = 0; + u32 postbld_osd1_premult = 0, postbld_osd2_premult = 0; osd_log_dbg("osd_setting_default_hwc\n"); /* depend on din0_premult_en */ @@ -5135,13 +5165,8 @@ static void osd_setting_default_hwc(void) VSYNCOSD_WR_MPEG_REG(VIU_OSD_BLEND_BLEND1_SIZE, blend_vsize << 16 | blend_hsize); - - /* close vd1, vd2 for debug */ - VSYNCOSD_WR_MPEG_REG(VD1_BLEND_SRC_CTRL, 0); - VSYNCOSD_WR_MPEG_REG(VD2_BLEND_SRC_CTRL, 0); - VSYNCOSD_WR_MPEG_REG_BITS(DOLBY_PATH_CTRL, - 0xf, 0, 4); + 0x3, 2, 2); } int osd_setting_blend(void) @@ -5171,33 +5196,29 @@ int osd_setting_blend(void) } -void osd_mali_afbc_restart(void) +void osd_mali_afbc_start(void) { - int i, osd_count, afbc_enable; + int i, osd_count, afbc_enable = 0; - afbc_enable = 0; osd_count = osd_hw.osd_meson_dev.osd_count; - if ((osd_hw.osd_meson_dev.afbc_type == MALI_AFBC) - && osd_hw.afbc_restart_in_vsync) { - VSYNCOSD_WR_MPEG_REG(VPU_MAFBC_IRQ_MASK, 0xf); + if (osd_hw.osd_meson_dev.afbc_type == MALI_AFBC) { for (i = 0; i < osd_count; i++) { if (osd_hw.osd_afbcd[i].afbc_start) { /* enable mali afbc */ - VSYNCOSD_WR_MPEG_REG_BITS( - VPU_MAFBC_SURFACE_CFG, - 1, i, 1); - afbc_enable = 1; - } - } - if (afbc_enable) { - if (osd_hw.afbc_use_latch) - VSYNCOSD_WR_MPEG_REG(VPU_MAFBC_COMMAND, 0x2); - else { - osd_log_dbg("start afbc decode\n"); - /* start decode */ - VSYNCOSD_WR_MPEG_REG(VPU_MAFBC_COMMAND, 1); + afbc_enable |= (1 << i); + /* afbc_enable |= 0x10000; */ } } + /* + if (osd_hw.afbc_start_in_vsync) + VSYNCOSD_WR_MPEG_REG( + VPU_MAFBC_SURFACE_CFG, + afbc_enable); + */ + if (afbc_enable) + VSYNCOSD_WR_MPEG_REG( + VPU_MAFBC_COMMAND, + (osd_hw.afbc_use_latch ? 2 : 1)); } } @@ -5715,7 +5736,7 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe, osd_hw.hw_rdma_en = 1; } else if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE) { osd_hw.hw_cursor_en = 0; - osd_hw.hw_rdma_en = 0; + osd_hw.hw_rdma_en = 1; } /* here we will init default value ,these value only set once . */ if (!logo_loaded) { @@ -5802,10 +5823,12 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe, osd_hw.premult_en[idx] = 0; osd_hw.osd_afbcd[idx].format = COLOR_INDEX_32_ABGR; osd_hw.osd_afbcd[idx].inter_format = - MALI_AFBC_16X16_PIXEL << 1 | + MALI_AFBC_32X8_PIXEL << 1 | MALI_AFBC_SPLIT_ON; osd_hw.osd_afbcd[idx].afbc_start = 0; - osd_hw.afbc_restart_in_vsync = 1; + osd_hw.afbc_start_in_vsync = 0; + osd_hw.afbc_force_reset = 1; +#if 0 /* enable for latch */ osd_hw.osd_use_latch = 1; data32 = 0; @@ -5814,6 +5837,7 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe, data32 |= 0x80000000; osd_reg_write( hw_osd_reg_array[idx].osd_ctrl_stat, data32); +#endif } osd_setting_default_hwc(); } @@ -6606,6 +6630,8 @@ void osd_page_flip(struct osd_plane_map_s *plane_map) osd_hw.reg[OSD_ENABLE] .update_func(index); } + if (osd_hw.hw_rdma_en) + osd_mali_afbc_start(); osd_wait_vsync_hw(); } else if (plane_map->phy_addr && plane_map->src_w && plane_map->src_h && index == OSD2) { @@ -6625,7 +6651,8 @@ void osd_page_flip(struct osd_plane_map_s *plane_map) osd_hw.reg[OSD_ENABLE] .update_func(index); } - + if (osd_hw.hw_rdma_en) + osd_mali_afbc_start(); } } else { if (plane_map->phy_addr && plane_map->src_w @@ -6664,6 +6691,8 @@ void osd_page_flip(struct osd_plane_map_s *plane_map) osd_hw.reg[OSD_ENABLE] .update_func(index); } + if (osd_hw.hw_rdma_en) + osd_mali_afbc_start(); osd_wait_vsync_hw(); } } diff --git a/drivers/amlogic/media/osd/osd_hw.h b/drivers/amlogic/media/osd/osd_hw.h index bde84660e172..19b5b757c90b 100644 --- a/drivers/amlogic/media/osd/osd_hw.h +++ b/drivers/amlogic/media/osd/osd_hw.h @@ -157,7 +157,7 @@ void osd_update_scan_mode(void); void osd_update_3d_mode(void); void osd_update_vsync_hit(void); void osd_hw_reset(void); -void osd_mali_afbc_restart(void); +void osd_mali_afbc_start(void); int logo_work_init(void); void set_logo_loaded(void); int set_osd_logo_freescaler(void); diff --git a/drivers/amlogic/media/osd/osd_rdma.c b/drivers/amlogic/media/osd/osd_rdma.c index 87d3325a8b1c..9e4fb9e3e718 100644 --- a/drivers/amlogic/media/osd/osd_rdma.c +++ b/drivers/amlogic/media/osd/osd_rdma.c @@ -921,7 +921,6 @@ static void osd_rdma_irq(void *arg) osd_update_3d_mode(); osd_update_vsync_hit(); osd_hw_reset(); - osd_mali_afbc_restart(); rdma_irq_count++; { /*This is a memory barrier*/ @@ -1118,7 +1117,7 @@ int osd_rdma_reset_and_flush(u32 reset_bit) i++; } i = 0; - base = VPU_MAFBC_COMMAND; + base = VPU_MAFBC_IRQ_MASK; while ((reset_bit & HW_RESET_MALI_AFBCD_REGS) && (i < MALI_AFBC_REG_BACKUP_COUNT)) { addr = mali_afbc_reg_backup[i]; @@ -1128,6 +1127,11 @@ int osd_rdma_reset_and_flush(u32 reset_bit) i++; } + if ((reset_bit & HW_RESET_MALI_AFBCD_REGS) + && (osd_hw.osd_meson_dev.cpu_id + == __MESON_CPU_MAJOR_ID_G12A)) + wrtie_reg_internal(VPU_MAFBC_COMMAND, 1); + if (item_count < 500) osd_reg_write(END_ADDR, (table_paddr + item_count * 8 - 1)); else { diff --git a/drivers/amlogic/media/osd/osd_reg.h b/drivers/amlogic/media/osd/osd_reg.h index bcb4ff795cda..36f31820fad9 100644 --- a/drivers/amlogic/media/osd/osd_reg.h +++ b/drivers/amlogic/media/osd/osd_reg.h @@ -1542,10 +1542,7 @@ #define VPU_MAFBC_OUTPUT_BUF_STRIDE_S3 0x3a7b #define VPU_MAFBC_PREFETCH_CFG_S3 0x3a7c -#define VD1_AFBCD0_MISC_CTRL 0x1a0a -#define VD2_AFBCD1_MISC_CTRL 0x1a0b -#define DOLBY_PATH_CTRL 0x1a0c -#define WR_BACK_MISC_CTRL 0x1a0d +#define DOLBY_PATH_CTRL 0x1a0c #define OSD_PATH_MISC_CTRL 0x1a0e #define MALI_AFBCD_TOP_CTRL 0x1a0f