From 63d457fdbd6f337ee2fa6cc86fd44058502dd6b8 Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Wed, 26 Jan 2022 17:52:12 +0800 Subject: [PATCH] PCI: rockchip: dw: Change ep BAR distribution scheme Change from: BAR0 512GB 32bits mem BAR1~5 64MB 32bits mem to: BAR0 512GB np 32bits mem BAR1 8MB np 32bits mem BAR2 BAR4 64MB pref 64bits mem And the log is like the following: [ 5.245427] [ T148] pci 0000:01:00.0: BAR 2: assigned [mem 0x900000000-0x903ffffff 64bit pref] [ 5.245449] [ T148] pci 0000:01:00.0: BAR 4: assigned [mem 0x904000000-0x907ffffff 64bit pref] [ 5.245471] [ T148] pci 0000:01:00.0: BAR 1: assigned [mem 0xf0800000-0xf0ffffff] Change-Id: I43ba2ebe0aacdc2b7f49175a6008d22c26ffd220 Signed-off-by: Jon Lin --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 38 +++++++++++++++---- 1 file changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index cd07583a9c0b..ec32eaf8ef97 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -836,6 +836,24 @@ static int rk_pci_find_resbar_capability(struct rk_pcie *rk_pcie) return 0; } +static int rk_pcie_ep_set_bar_flag(struct rk_pcie *rk_pcie, enum pci_barno barno, int flags) +{ + enum pci_barno bar = barno; + u32 reg; + + reg = PCI_BASE_ADDRESS_0 + (4 * bar); + + /* Disabled the upper 32bits BAR to make a 64bits bar pair */ + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) + dw_pcie_writel_dbi2(rk_pcie->pci, reg + 4, 0); + + dw_pcie_writel_dbi(rk_pcie->pci, reg, flags); + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) + dw_pcie_writel_dbi(rk_pcie->pci, reg + 4, 0); + + return 0; +} + static void rk_pcie_ep_setup(struct rk_pcie *rk_pcie) { int ret; @@ -912,17 +930,21 @@ static void rk_pcie_ep_setup(struct rk_pcie *rk_pcie) if (!resbar_base) { dev_warn(dev, "failed to find resbar_base\n"); } else { - /* Resize BAR0 to support 512GB */ + /* Resize BAR0 to support 512GB, BAR1 to support 8M, BAR2~5 to support 64M */ dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + 0x4, 0xfffff0); - /* Bit13-8 set to 19 means 2^19MB (512GB) */ dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + 0x8, 0x13c0); - /* Resize bar1 - bar6 to 64M */ - for (bar = 1; bar < 6; bar++) { - dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + - 0x4 + bar * 0x8, 0xfffff0); - dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + - 0x8 + bar * 0x8, 0x6c0); + dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + 0xc, 0xfffff0); + dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + 0x10, 0x3c0); + for (bar = 2; bar < 6; bar++) { + dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0); + dw_pcie_writel_dbi(rk_pcie->pci, resbar_base + 0x8 + bar * 0x8, 0x6c0); } + + /* Set flags */ + rk_pcie_ep_set_bar_flag(rk_pcie, BAR_0, PCI_BASE_ADDRESS_MEM_TYPE_32); + rk_pcie_ep_set_bar_flag(rk_pcie, BAR_1, PCI_BASE_ADDRESS_MEM_TYPE_32); + rk_pcie_ep_set_bar_flag(rk_pcie, BAR_2, PCI_BASE_ADDRESS_MEM_PREFETCH | PCI_BASE_ADDRESS_MEM_TYPE_64); + rk_pcie_ep_set_bar_flag(rk_pcie, BAR_4, PCI_BASE_ADDRESS_MEM_PREFETCH | PCI_BASE_ADDRESS_MEM_TYPE_64); } /* Device id and class id needed for request bar address */